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Update README.md #4

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5 changes: 3 additions & 2 deletions README.md
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Expand Up @@ -41,7 +41,8 @@ The aim is to design and implement a 1-bit Full Adder using Cadence Virtuoso and

## Schematic Diagram
### 1. Schematic of 1-Bit Full Adder:
![Screenshot 2025-04-11 142821](https://github.com/user-attachments/assets/f1ad2463-1f53-4cff-b844-1634ba94d46b)
![WhatsApp Image 2025-05-12 at 10 24 58_b6b373f0](https://github.com/user-attachments/assets/fe21dde0-5161-4c9b-8c17-18aaab20dac7)


![image](https://github.com/user-attachments/assets/1a962018-9d6b-4246-ab5f-424602551e87)

Expand All @@ -51,7 +52,7 @@ The aim is to design and implement a 1-bit Full Adder using Cadence Virtuoso and
### Transient Analysis Output:
![Screenshot 2025-04-11 142904](https://github.com/user-attachments/assets/dc5a3489-8b68-427e-adb9-c71cee1367a4)
![Screenshot 2025-04-11 142843](https://github.com/user-attachments/assets/1f58672f-b0cb-4455-b436-9236da9a6af8)
![Screenshot 2025-04-11 142750](https://github.com/user-attachments/assets/308f0333-8d0e-4b4e-a6cd-41d857c3d8bf)
![WhatsApp Image 2025-05-12 at 10 24 57_c61f9ef6](https://github.com/user-attachments/assets/bbf6943c-adb5-4922-b18a-d5a0f0963e2a)

## Results
1. Successfully designed the **1-bit Full Adder** schematic using **Cadence Virtuoso**.
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