Description:

It is responsible for receiving commands through UART receiver to do different system functions as register file reading/writing or doing some processing using ALU block and send result to UART transmitter through asynchronous FIFO for handling different clock rates and avoid data loss.

Block Diagram

System Specifications

• Reference clock (REF_CLK) is 50 MHz.
• UART clock (UART_CLK) is 3.6864 MHz.
• Clock Divider is always on (clock divider enable = 1).

Supported Commands

• Register File Write.

• Register file read.

• ALU operation with input operands.

• ALU operation with previous operands.

Documentation

For detailed documentation, please refer to the PDF version, RTL to GDS Implementation of Low Power Configurable Multi Clock Digital System, or the Word document for higher-quality figures, available here.