Firmware release: LHC stable beams

.gitignore

@@ -1,17 +1,23 @@
 *~
 *.jou
-*.log
 build
 *.xcix
 *.pb
 .Xil
 *.zip
+*.str
 
-simulation_inputs
-simulation_outputs
-test_data
+__pycache__
+sim_data
 
 .idea
 venv
 *.pyc
+*.run
 
+#notepad++ backup
+nppBackup
+*.run
+*.pyc
+*.log
+firmware/FT0/bits

Jenkinsfile

@@ -42,15 +42,30 @@ pipeline {
       }
     }
     stage('Build FIT bitstreams') {
-      parallel {
+      stages {
+        stage('FTM_PM') {
+          steps {
+            sh('./software/ci/build.sh FTM_PM')
+          }
+        }
+        stage('FTM_TCM') {
+          steps {
+            sh('./software/ci/build.sh FTM_TCM')
+          }
+        }
         stage('PM') {
           steps {
             sh('./software/ci/build.sh PM')
           }
         }
-        stage('TCM') {
+        stage('TCM_proto') {
+          steps {
+            sh('./software/ci/build.sh TCM_proto')
+          }
+        }
+        stage('TCM_v1') {
           steps {
-            sh('./software/ci/build.sh TCM')
+            sh('./software/ci/build.sh TCM_v1')
           }
         }
       }

README.md

@@ -1,4 +1,4 @@
-![PM_TCM](https://repository-images.githubusercontent.com/238522341/aca2c500-48cf-11ea-95b5-4a498a732d8e?dl=0)
+![PM_TCM](https://github.com/dfinogee/alice-fit-fpga/blob/devel/photo/FT0_front.jpg?raw=true)
 
 ----
 # ALICE Fast Interaction Trigger (FIT) firmware repository
@@ -11,50 +11,48 @@ Authors: [email protected], [email protected]
 ### Clone the Git repository
 
     git clone https://github.com/AliceO2Group/alice-fit-fpga.git
-
-### Update to latest version
-
     git pull --recurse-submodules
 
 ----
-### Set up Vivado 2019.2.1 (NEW !!!)
-    source /opt/Xilinx/Vivado/2019.2/settings64.sh
-
-	used vivado version:
-	Vivado v2019.2.1 (64-bit)
-	SW Build: 2729669 on Thu Dec 5 04:49:17 MST 2019
-	IP Build: 2729494 on Thu Dec 5 07:38:25 MST 2019
-
-----
-## Generate bitstreams
+## Projects compilation
+'\<projec\>' = PM/TCM_v1/TCM_proto/FTM_PM/FTM_TCM
 
-### FIT/FT0/PM
+### Vivado tcl mode (linux)
 
-     cd alice-fit-fpga/firmware/FT0/PM
+     cd alice-fit-fpga/firmware/FT0/<projec>
      vivado -mode batch -source make.tcl 
 
-### FIT/FT0/TCM
+### Macro (linux)
 
-     cd alice-fit-fpga/firmware/FT0/TCM
-     vivado -mode batch -source make.tcl 
+Macro will compile project and copy bit + bin + logs files into firmware/FT0/bits/
 
-### FIT/FT0/FTM
+     cd alice-fit-fpga/
+     ./software/ci/build_local.sh <project>
 
-     cd alice-fit-fpga/firmware/FT0/FTM
-     vivado -mode batch -source make.tcl 
+### Vivado GUI (win/linux)
+
+run vivado v2019.2.1/v2020.1
+
+	(linux)
+	source /opt/Xilinx/Vivado/2019.2/settings64.sh
+	vivado
+
+open tcl console and change directory to the project
+
+	(in tcl console)
+	cd /<path>/alice-fit-fpga/firmware/FT0/<projec>
+
+remove build directory (if exist) and run compilation
+
+	(in tcl console)
+	source ./make.tcl
 
-----
-## After any change to IP cores
+
+### Export IP cores to `ipcore_properties`
 
 Open the TCL console in the Vivado window and type in the following commands:
 
     source ../../tcl/fit.tcl
     fit::update_ip_properties
 
-Then git add/commit any new/changed files in the directory `ipcore_properties`
-
-----
-## After any change to IP cores and/or to VHDL source files
-
-git add/commit any new/changed VHDL files
 

firmware/FT0/FTM_PM/ipcore_properties/cntpck_fifo_comp.txt

@@ -14,7 +14,7 @@ CONFIG.Clock_Type_AXI                               string  false      Common_Cl
 CONFIG.Component_Name                               string  false      cntpck_fifo_comp
 CONFIG.DATA_WIDTH                                   string  false      64
 CONFIG.Data_Count                                   string  false      false
-CONFIG.Data_Count_Width                             string  false      7
+CONFIG.Data_Count_Width                             string  false      8
 CONFIG.Disable_Timing_Violations                    string  false      false
 CONFIG.Disable_Timing_Violations_AXI                string  false      false
 CONFIG.Dout_Reset_Value                             string  false      0
@@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch                     string  false      Common_Cl
 CONFIG.FIFO_Implementation_wrch                     string  false      Common_Clock_Block_RAM
 CONFIG.Fifo_Implementation                          string  false      Independent_Clocks_Block_RAM
 CONFIG.Full_Flags_Reset_Value                       string  false      1
-CONFIG.Full_Threshold_Assert_Value                  string  false      127
+CONFIG.Full_Threshold_Assert_Value                  string  false      255
 CONFIG.Full_Threshold_Assert_Value_axis             string  false      1023
 CONFIG.Full_Threshold_Assert_Value_rach             string  false      1023
 CONFIG.Full_Threshold_Assert_Value_rdch             string  false      1023
 CONFIG.Full_Threshold_Assert_Value_wach             string  false      1023
 CONFIG.Full_Threshold_Assert_Value_wdch             string  false      1023
 CONFIG.Full_Threshold_Assert_Value_wrch             string  false      1023
-CONFIG.Full_Threshold_Negate_Value                  string  false      126
+CONFIG.Full_Threshold_Negate_Value                  string  false      254
 CONFIG.HAS_ACLKEN                                   string  false      false
 CONFIG.HAS_TKEEP                                    string  false      false
 CONFIG.HAS_TSTRB                                    string  false      false
@@ -87,8 +87,8 @@ CONFIG.Inject_Sbit_Error_rdch                       string  false      false
 CONFIG.Inject_Sbit_Error_wach                       string  false      false
 CONFIG.Inject_Sbit_Error_wdch                       string  false      false
 CONFIG.Inject_Sbit_Error_wrch                       string  false      false
-CONFIG.Input_Data_Width                             string  false      160
-CONFIG.Input_Depth                                  string  false      128
+CONFIG.Input_Data_Width                             string  false      128
+CONFIG.Input_Depth                                  string  false      256
 CONFIG.Input_Depth_axis                             string  false      1024
 CONFIG.Input_Depth_rach                             string  false      16
 CONFIG.Input_Depth_rdch                             string  false      1024
@@ -100,8 +100,8 @@ CONFIG.MASTER_ACLK.INSERT_VIP                       string  false      0
 CONFIG.M_AXI.INSERT_VIP                             string  false      0
 CONFIG.M_AXIS.INSERT_VIP                            string  false      0
 CONFIG.Master_interface_Clock_enable_memory_mapped  string  false      false
-CONFIG.Output_Data_Width                            string  false      160
-CONFIG.Output_Depth                                 string  false      128
+CONFIG.Output_Data_Width                            string  false      128
+CONFIG.Output_Depth                                 string  false      256
 CONFIG.Output_Register_Type                         string  false      Embedded_Reg
 CONFIG.Overflow_Flag                                string  false      false
 CONFIG.Overflow_Flag_AXI                            string  false      false
@@ -157,7 +157,7 @@ CONFIG.Underflow_Sense_AXI                          string  false      Active_Hi
 CONFIG.Use_Dout_Reset                               string  false      true
 CONFIG.Use_Embedded_Registers                       string  false      false
 CONFIG.Use_Embedded_Registers_axis                  string  false      false
-CONFIG.Use_Extra_Logic                              string  false      true
+CONFIG.Use_Extra_Logic                              string  false      false
 CONFIG.Valid_Flag                                   string  false      false
 CONFIG.Valid_Sense                                  string  false      Active_High
 CONFIG.WRITE_CLK.FREQ_HZ                            string  false      100000000