GitHub - Alexyazdani/Verilog-Interview-Questions: Sample Interview Questions in Verilog

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 9 Commits
4_to_16_decoder.v		4_to_16_decoder.v
README.txt		README.txt
elevator.v		elevator.v
fifo.v		fifo.v
frequency_divider.v		frequency_divider.v
priority_encoder.v		priority_encoder.v
rca.v		rca.v
sequence_detect.v		sequence_detect.v
traffic_controller.v		traffic_controller.v
vending_machine.v		vending_machine.v
water_fountain.v		water_fountain.v

Repository files navigation

Common Topics Asked by Interviewers:
- Clock Division / Frequency Dividers
- Static Timing Analysis (STA)
- Clock Domain Crossing (CDC)
- FIFO Design - Synchronous vs Asynchronous
- State Machines - Mealey vs Moore
- Resets - Synchronous vs Asynchronous
- Arbiters
- Power Optimizations
- Assertions
- Coverage
- Polymorphism


https://thedatabus.in/interview_list
https://www.autonomousvision.io/rtl-practice