fix(flydsl): make PyTorch→FlyDSL e2e reliable (gate, harness resolution, verify/opt wiring)

[Umangatamd]

✅ Errors fixed — PyTorch→FlyDSL e2e now runs end-to-end (translation → baseline → optimization)

Validated on KernelBench/level3/1_MLP.py (claude-opus-4.8 / amd_llm gateway). Reproduced the original FAIL_PREPROCESS/no-baseline/step_limit failures, traced the full chain, and fixed each root cause.

Root causes found & fixed

1. Baseline correctness-gate false-abort — collect_baseline re-validated correctness on the stricter harness-generator harness and aborted on any non-zero exit, discarding kernels translation already validated → scoped skip when translation.success (env-independent; user-supplied harnesses still gate).
2. Harness couldn't resolve the kernel (LLM guessed a wrong rel-path, e.g. a spurious KernelBench/ segment) → deterministic kernel_relpath injection into the harness subagents.
3. Silent no-baseline → loud kernel not found at X diagnostic (detect_kernel_resolution_failure).
4. Spin to step_limit on a broken harness → fail-closed once the harness-generator retry budget is exhausted.
5. Work-dir mismatch across verify/baseline/optimize → retarget preprocess (subagent sandbox + baseline work_dir) to the per-run _opt_repo, git-init it for patch capture, and fix _copy_repo_sandbox to copy a repo that lives under output_dir.
6. Verifier never confirms a working harness → deterministic --correctness backstop (mark HARNESS_VERIFIED when the harness passes --correctness but the LLM verifier didn't confirm).
7. mini.py — use the per-run _opt_repo as the optimization root for translation runs even when --repo is passed (otherwise preflight/opt root at the source repo, which has no translated kernel).
8. RAG postprocessor built a provider-less LitellmModel (else: get_model()) → litellm.BadRequestError: LLM Provider NOT provided crashing the optimize loop → route through the gateway model (load_geak_model) + make post-processing non-fatal.

Plus: raise full-mode preprocess soft cap 900s → 2400s (geak.yaml) so translation + multi-round harness-gen + baseline fit.

Result

Optimize loop now produces real patches with verified speedups (round-1, over the translated FlyDSL baseline):

strategy	speedup
gemm-tile-tuning-per-layer	1.68× (0.609 → 0.363 ms)
fixed-pad-2	1.46×
fixed-pad-3	1.17×

Cross-verified speedup 1.14×. Tests: 20 new preprocess_v3 bugfix unit tests + broader suite green.

Note for main

Fixes #7 (mini.py) and #8 (RAG postprocessor) are general bugs that exist on main too (affect any amd_llm + RAG / translation run), worth landing independently of the FlyDSL branch.

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