diff --git a/umi/sumi/umi_fifo/rtl/umi_fifo.v b/umi/sumi/umi_fifo/rtl/umi_fifo.v
index 28795f5..572a577 100644
--- a/umi/sumi/umi_fifo/rtl/umi_fifo.v
+++ b/umi/sumi/umi_fifo/rtl/umi_fifo.v
@@ -23,16 +23,18 @@
  ******************************************************************************/
 
 module umi_fifo
-  #(parameter TARGET  = "DEFAULT", // implementation target
-    parameter DEPTH   = 4,         // FIFO depth
-    parameter AW      = 64,        // UMI width
-    parameter CW      = 32,        // UMI width
-    parameter DW      = 256        // UMI width
+  #(parameter TARGET      = "DEFAULT", // implementation target
+    parameter DEPTH       = 4,         // FIFO depth
+    parameter ALMOSTFULL  = 0,         // Almost full threshold
+    parameter AW          = 64,        // UMI width
+    parameter CW          = 32,        // UMI width
+    parameter DW          = 256        // UMI width
     )
    (// control/status signals
     input           bypass, // bypass FIFO
     input           chaosmode, // enable "random" fifo pushback
     output          fifo_full,
+    output          fifo_almost_full,
     output          fifo_empty,
     // Input
     input           umi_in_clk,
@@ -86,24 +88,26 @@ module umi_fifo
    //#################################
 
    la_asyncfifo  #(.DW(CW+AW+AW+DW),
-                   .DEPTH(DEPTH))
+                   .DEPTH(DEPTH),
+                   .ALMOSTFULL(ALMOSTFULL))
    fifo  (// Outputs
-          .wr_full      (fifo_full),
-          .rd_dout      (fifo_dout[DW+AW+AW+CW-1:0]),
-          .rd_empty     (fifo_empty),
+          .wr_full        (fifo_full),
+          .wr_almost_full (fifo_almost_full),
+          .rd_dout        (fifo_dout[DW+AW+AW+CW-1:0]),
+          .rd_empty       (fifo_empty),
           // Inputs
-          .wr_clk       (umi_in_clk),
-          .wr_nreset    (umi_in_nreset),
-          .wr_din       ({umi_in_data[DW-1:0],umi_in_srcaddr[AW-1:0],umi_in_dstaddr[AW-1:0],umi_in_cmd[CW-1:0]}),
-          .wr_en        (umi_in_valid),
-          .wr_chaosmode (chaosmode),
-          .rd_clk       (umi_out_clk),
-          .rd_nreset    (umi_out_nreset),
-          .rd_en        (fifo_read),
-          .vss          (vss),
-          .vdd          (vdd),
-          .ctrl         (1'b0),
-          .test         (1'b0));
+          .wr_clk         (umi_in_clk),
+          .wr_nreset      (umi_in_nreset),
+          .wr_din         ({umi_in_data[DW-1:0],umi_in_srcaddr[AW-1:0],umi_in_dstaddr[AW-1:0],umi_in_cmd[CW-1:0]}),
+          .wr_en          (umi_in_valid),
+          .wr_chaosmode   (chaosmode),
+          .rd_clk         (umi_out_clk),
+          .rd_nreset      (umi_out_nreset),
+          .rd_en          (fifo_read),
+          .vss            (vss),
+          .vdd            (vdd),
+          .ctrl           (1'b0),
+          .test           (1'b0));
 
    //#################################
    // FIFO Bypass
diff --git a/umi/sumi/umi_unpack/rtl/umi_unpack.v b/umi/sumi/umi_unpack/rtl/umi_unpack.v
index 7e27847..1137ac0 100644
--- a/umi/sumi/umi_unpack/rtl/umi_unpack.v
+++ b/umi/sumi/umi_unpack/rtl/umi_unpack.v
@@ -54,7 +54,7 @@ module umi_unpack
    // outputs
    assign cmd_opcode[4:0] = packet_cmd[4:0];
    assign cmd_size[2:0]   = packet_cmd[7:5];
-   assign cmd_len[7:0]    = {8{cmd_atomic}} & packet_cmd[15:8];
+   assign cmd_len[7:0]    = {8{~cmd_atomic}} & packet_cmd[15:8];
    assign cmd_atype[7:0]  = packet_cmd[15:8];
    assign cmd_qos[3:0]    = packet_cmd[19:16];
    assign cmd_prot[1:0]   = packet_cmd[21:20];