From bcec46da6714d0d4c9e3ce1d053b5f7a301ad4f9 Mon Sep 17 00:00:00 2001 From: Andreas Olofsson Date: Tue, 28 Jan 2025 19:18:16 -0500 Subject: [PATCH 1/3] Adding ascii in display to somplify debug --- umi/sumi/rtl/umi_tester.v | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/umi/sumi/rtl/umi_tester.v b/umi/sumi/rtl/umi_tester.v index 119988e..b8ffcbb 100644 --- a/umi/sumi/rtl/umi_tester.v +++ b/umi/sumi/rtl/umi_tester.v @@ -123,9 +123,11 @@ module umi_tester // file names reg [8*128-1:0] memhreq; reg [8*128-1:0] memhresp; + reg [8*32-1:0] req_opcode; + reg [8*32-1:0] resp_opcode; // local state - reg [MAW-1:0] req_addr; + reg [MAW-1:0] req_addr; reg [MAW-1:0] resp_addr; reg req_valid; @@ -168,19 +170,37 @@ module umi_tester // Monitor Transactions //##################################################### + always @* + case(uhost_req_cmd[4:0]) + UMI_REQ_READ : req_opcode = "READ"; + UMI_REQ_WRITE : req_opcode = "WRITE"; + UMI_REQ_POSTED : req_opcode = "POSTED"; + UMI_REQ_ATOMIC : req_opcode = "ATOMIC"; + UMI_INVALID : req_opcode = "INVALID"; + default: req_opcode = "UNKNOWN"; + endcase + + always @* + case(uhost_resp_cmd[4:0]) + UMI_RESP_READ : resp_opcode = "READ-RESP"; + UMI_RESP_WRITE : resp_opcode = "WRITE-RESP"; + UMI_INVALID : resp_opcode = "INVALID"; + default: resp_opcode = "UNKNOWN"; + endcase + if(DEBUG) begin always @ (posedge clk) begin if (uhost_req_valid & uhost_req_ready) - $display("(request) data=%h srcaddr=%h dstaddr=%h cmd=%h (%0t)", + $display("data=%h srcaddr=%h dstaddr=%h cmd=%h (%0t) (%0s)", uhost_req_data, uhost_req_srcaddr, uhost_req_dstaddr, uhost_req_cmd, - $time); + $time, req_opcode); if (uhost_resp_valid & uhost_resp_ready) - $display("(response) data=%h srcaddr=%h dstaddr=%h cmd=%h (%0t)", + $display("data=%h srcaddr=%h dstaddr=%h cmd=%h (%0t) (%0s)", uhost_resp_data, uhost_resp_srcaddr, uhost_resp_dstaddr, uhost_resp_cmd, - $time); + $time, resp_opcode); end end From a90e4f3a100d463021cbcb87ebcae116100cb715 Mon Sep 17 00:00:00 2001 From: Andreas Olofsson Date: Sun, 20 Jul 2025 08:54:49 -0400 Subject: [PATCH 2/3] Addingh missing asyncfifo almost_full signal (was changed in lambdalib v0.3.4) --- umi/lumi/rtl/lumi_rx.v | 1 + umi/lumi/rtl/lumi_tx.v | 1 + umi/sumi/rtl/umi_fifo.v | 1 + umi/sumi/rtl/umi_fifo_flex.v | 1 + 4 files changed, 4 insertions(+) diff --git a/umi/lumi/rtl/lumi_rx.v b/umi/lumi/rtl/lumi_rx.v index aad3deb..9b8b5e2 100644 --- a/umi/lumi/rtl/lumi_rx.v +++ b/umi/lumi/rtl/lumi_rx.v @@ -662,6 +662,7 @@ module lumi_rx .TESTW(1), // width of asic test interface .PROP("DEFAULT")) // Pass through variable for hard macro lnk_fifo_i(// Outputs + .wr_almost_full (), .wr_full (), .rd_dout (lnk_fifo_dout[CW-1:0]), .rd_empty (lnk_fifo_empty), diff --git a/umi/lumi/rtl/lumi_tx.v b/umi/lumi/rtl/lumi_tx.v index c683c65..a4cd00f 100644 --- a/umi/lumi/rtl/lumi_tx.v +++ b/umi/lumi/rtl/lumi_tx.v @@ -631,6 +631,7 @@ module lumi_tx .TESTW(1), // width of asic test interface .PROP("DEFAULT")) // Pass through variable for hard macro phy_fifo_i(// Outputs + .wr_almost_full (), .wr_full (phy_fifo_full), .rd_dout (phy_txdata[IOW-1:0]), .rd_empty (phy_fifo_empty), diff --git a/umi/sumi/rtl/umi_fifo.v b/umi/sumi/rtl/umi_fifo.v index 28795f5..fa991cf 100644 --- a/umi/sumi/rtl/umi_fifo.v +++ b/umi/sumi/rtl/umi_fifo.v @@ -88,6 +88,7 @@ module umi_fifo la_asyncfifo #(.DW(CW+AW+AW+DW), .DEPTH(DEPTH)) fifo (// Outputs + .wr_almost_full(), .wr_full (fifo_full), .rd_dout (fifo_dout[DW+AW+AW+CW-1:0]), .rd_empty (fifo_empty), diff --git a/umi/sumi/rtl/umi_fifo_flex.v b/umi/sumi/rtl/umi_fifo_flex.v index 445eed4..ba9fb83 100644 --- a/umi/sumi/rtl/umi_fifo_flex.v +++ b/umi/sumi/rtl/umi_fifo_flex.v @@ -600,6 +600,7 @@ module umi_fifo_flex la_syncfifo #(.DW(CW+AW+AW+ODW), .DEPTH(DEPTH)) fifo (// Outputs + .wr_almost_full (), .wr_full (fifo_full_raw), .rd_dout (fifo_dout[ODW+AW+AW+CW-1:0]), .rd_empty (fifo_empty_raw), From 4bb8e80466ffb76dcfc5171b4a615db9a1264148 Mon Sep 17 00:00:00 2001 From: Andreas Olofsson Date: Sun, 20 Jul 2025 09:10:49 -0400 Subject: [PATCH 3/3] Fixing broken fix --- umi/lumi/rtl/lumi_rx.v | 2 ++ umi/sumi/rtl/umi_fifo_flex.v | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/umi/lumi/rtl/lumi_rx.v b/umi/lumi/rtl/lumi_rx.v index 9b8b5e2..823b606 100644 --- a/umi/lumi/rtl/lumi_rx.v +++ b/umi/lumi/rtl/lumi_rx.v @@ -782,6 +782,7 @@ module lumi_rx .TESTW(1), // width of asic test interface .PROP("DEFAULT")) // Pass through variable for hard macro req_syncfifo_i(// Outputs + .wr_almost_full (), .wr_full (sync_fifo_full[0]), .rd_dout (sync_fifo_dout[IOW-1:0]), .rd_empty (sync_fifo_empty[0]), @@ -810,6 +811,7 @@ module lumi_rx .TESTW(1), // width of asic test interface .PROP("DEFAULT")) // Pass through variable for hard macro resp_syncfifo_i(// Outputs + .wr_almost_full (), .wr_full (sync_fifo_full[1]), .rd_dout (sync_fifo_dout[2*IOW-1:IOW]), .rd_empty (sync_fifo_empty[1]), diff --git a/umi/sumi/rtl/umi_fifo_flex.v b/umi/sumi/rtl/umi_fifo_flex.v index ba9fb83..d5ea30a 100644 --- a/umi/sumi/rtl/umi_fifo_flex.v +++ b/umi/sumi/rtl/umi_fifo_flex.v @@ -578,6 +578,7 @@ module umi_fifo_flex la_asyncfifo #(.DW(CW+AW+AW+ODW), .DEPTH(DEPTH)) fifo (// Outputs + .wr_almost_full(), .wr_full (fifo_full_raw), .rd_dout (fifo_dout[ODW+AW+AW+CW-1:0]), .rd_empty (fifo_empty_raw), @@ -600,7 +601,6 @@ module umi_fifo_flex la_syncfifo #(.DW(CW+AW+AW+ODW), .DEPTH(DEPTH)) fifo (// Outputs - .wr_almost_full (), .wr_full (fifo_full_raw), .rd_dout (fifo_dout[ODW+AW+AW+CW-1:0]), .rd_empty (fifo_empty_raw),