boards: s32z270: enable support psi5

enable support psi5

Signed-off-by: Cong Nguyen Huu <[email protected]>

Author: congnguyenhuu

boards/nxp/s32z2xxdc2/doc/index.rst

@@ -68,6 +68,8 @@ The boards support the following hardware features:
 +-----------+------------+-------------------------------------+
 | PIT       | on-chip    | counter                             |
 +-----------+------------+-------------------------------------+
+| PSI5      | on-chip    | psi5                                |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not currently supported by the port.
 

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml

@@ -1,4 +1,4 @@
-# Copyright 2022-2024 NXP
+# Copyright 2022-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 identifier: s32z2xxdc2/s32z270/rtu0
@@ -20,4 +20,5 @@ supported:
   - i2c
   - dma
   - pwm
+  - psi5
 vendor: nxp

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml

@@ -1,4 +1,4 @@
-# Copyright 2023-2024 NXP
+# Copyright 2023-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 identifier: s32z2xxdc2@D/s32z270/rtu0
@@ -20,4 +20,5 @@ supported:
   - i2c
   - dma
   - pwm
+  - psi5
 vendor: nxp

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml

@@ -1,4 +1,4 @@
-# Copyright 2022-2024 NXP
+# Copyright 2022-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 identifier: s32z2xxdc2/s32z270/rtu1
@@ -20,4 +20,5 @@ supported:
   - i2c
   - dma
   - pwm
+  - psi5
 vendor: nxp

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml

@@ -1,4 +1,4 @@
-# Copyright 2022-2024 NXP
+# Copyright 2022-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 identifier: s32z2xxdc2@D/s32z270/rtu1
@@ -20,4 +20,5 @@ supported:
   - i2c
   - dma
   - pwm
+  - psi5
 vendor: nxp

dts/arm/nxp/nxp_s32z27x_r52.dtsi

@@ -1,5 +1,5 @@
 /*
- * Copyright 2022-2024 NXP
+ * Copyright 2022-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -1452,5 +1452,77 @@
 			#size-cells = <0>;
 			status = "disabled";
 		};
+
+		psi5_0: psi5@401e0000 {
+			compatible = "nxp,s32-psi5";
+			reg = <0x401e0000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			psi5_0_ch0: ch@0 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <0>;
+				interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+
+			psi5_0_ch1: ch@1 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <1>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+
+			psi5_0_ch2: ch@2 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <2>;
+				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+
+			psi5_0_ch3: ch@3 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <3>;
+				interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+		};
+
+		psi5_1: psi5@421e0000 {
+			compatible = "nxp,s32-psi5";
+			reg = <0x421e0000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			psi5_1_ch0: ch@0 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <0>;
+				interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+
+			psi5_1_ch1: ch@1 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <1>;
+				interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+
+			psi5_1_ch2: ch@2 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <2>;
+				interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+
+			psi5_1_ch3: ch@3 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <3>;
+				interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+		};
 	};
 };