diff --git a/mcux/mcux-sdk/devices/MIMX9352/drivers/fsl_clock.h b/mcux/mcux-sdk/devices/MIMX9352/drivers/fsl_clock.h
index 5278b290e..e31d14bc7 100644
--- a/mcux/mcux-sdk/devices/MIMX9352/drivers/fsl_clock.h
+++ b/mcux/mcux-sdk/devices/MIMX9352/drivers/fsl_clock.h
@@ -1082,6 +1082,12 @@ typedef enum _clock_lpcg
         kCLOCK_Pdm \
     }
 
+/*! @brief Clock ip name array for USDHC. */
+#define USDHC_CLOCKS                                                  \
+    {                                                                 \
+        kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2, kCLOCK_Usdhc3 \
+    }
+
 /*! @brief Clock ip name array for ENET QOS. */
 #define ENETQOS_CLOCKS  \
     {                   \
diff --git a/mcux/mcux-sdk/drivers/usdhc/fsl_usdhc.c b/mcux/mcux-sdk/drivers/usdhc/fsl_usdhc.c
index 7738f5314..729860301 100644
--- a/mcux/mcux-sdk/drivers/usdhc/fsl_usdhc.c
+++ b/mcux/mcux-sdk/drivers/usdhc/fsl_usdhc.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2021, 2025 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -1222,11 +1222,11 @@ status_t USDHC_SetADMA1Descriptor(
 
     uint32_t miniEntries, startEntries = 0UL,
                           maxEntries = (admaTableWords * sizeof(uint32_t)) / sizeof(usdhc_adma1_descriptor_t);
-    usdhc_adma1_descriptor_t *adma1EntryAddress = (usdhc_adma1_descriptor_t *)(uint32_t)(admaTable);
+    usdhc_adma1_descriptor_t *adma1EntryAddress = (usdhc_adma1_descriptor_t *)(uintptr_t)(admaTable);
     uint32_t i, dmaBufferLen = 0UL;
     const uint32_t *data = dataBufferAddr;
 
-    if (((uint32_t)data % USDHC_ADMA1_ADDRESS_ALIGN) != 0UL)
+    if (((uintptr_t)data % USDHC_ADMA1_ADDRESS_ALIGN) != 0UL)
     {
         return kStatus_USDHC_DMADataAddrNotAlign;
     }
@@ -1277,10 +1277,10 @@ status_t USDHC_SetADMA1Descriptor(
 
         adma1EntryAddress[i] = (dmaBufferLen << USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT);
         adma1EntryAddress[i] |= (uint32_t)kUSDHC_Adma1DescriptorTypeSetLength;
-        adma1EntryAddress[i + 1UL] = (uint32_t)(data);
+        adma1EntryAddress[i + 1UL] = (uintptr_t)(data);
         adma1EntryAddress[i + 1UL] |=
             (uint32_t)kUSDHC_Adma1DescriptorTypeTransfer | (uint32_t)kUSDHC_Adma1DescriptorInterrupFlag;
-        data = (uint32_t *)((uint32_t)data + dmaBufferLen);
+        data = (uint32_t *)((uintptr_t)data + dmaBufferLen);
         dataBytes -= dmaBufferLen;
     }
     /* the end of the descriptor */
@@ -1309,11 +1309,11 @@ status_t USDHC_SetADMA2Descriptor(
 
     uint32_t miniEntries, startEntries = 0UL,
                           maxEntries = (admaTableWords * sizeof(uint32_t)) / sizeof(usdhc_adma2_descriptor_t);
-    usdhc_adma2_descriptor_t *adma2EntryAddress = (usdhc_adma2_descriptor_t *)(uint32_t)(admaTable);
+    usdhc_adma2_descriptor_t *adma2EntryAddress = (usdhc_adma2_descriptor_t *)(uintptr_t)(admaTable);
     uint32_t i, dmaBufferLen = 0UL;
     const uint32_t *data = dataBufferAddr;
 
-    if (((uint32_t)data % USDHC_ADMA2_ADDRESS_ALIGN) != 0UL)
+    if (((uintptr_t)data % USDHC_ADMA2_ADDRESS_ALIGN) != 0UL)
     {
         return kStatus_USDHC_DMADataAddrNotAlign;
     }
@@ -1371,13 +1371,17 @@ status_t USDHC_SetADMA2Descriptor(
         }
 
         /* Each descriptor for ADMA2 is 64-bit in length */
+#if INTPTR_MAX == INT64_MAX
+        adma2EntryAddress[i].address   = (uintptr_t)((dataBytes == 0UL) ? &s_usdhcBootDummy : data);
+#else
         adma2EntryAddress[i].address   = (dataBytes == 0UL) ? &s_usdhcBootDummy : data;
+#endif
         adma2EntryAddress[i].attribute = (dmaBufferLen << USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT);
         adma2EntryAddress[i].attribute |=
             (dataBytes == 0UL) ?
                 0UL :
                 ((uint32_t)kUSDHC_Adma2DescriptorTypeTransfer | (uint32_t)kUSDHC_Adma2DescriptorInterruptFlag);
-        data = (uint32_t *)((uint32_t)data + dmaBufferLen);
+        data = (uint32_t *)((uintptr_t)data + dmaBufferLen);
 
         if (dataBytes != 0UL)
         {
@@ -1420,7 +1424,7 @@ status_t USDHC_SetInternalDmaConfig(USDHC_Type *base,
     assert(dmaConfig != NULL);
     assert(dataAddr != NULL);
     assert((NULL != dmaConfig->admaTable) &&
-           (((USDHC_ADMA_TABLE_ADDRESS_ALIGN - 1U) & (uint32_t)dmaConfig->admaTable) == 0UL));
+           (((USDHC_ADMA_TABLE_ADDRESS_ALIGN - 1U) & (uintptr_t)dmaConfig->admaTable) == 0UL));
 
 #if FSL_FEATURE_USDHC_HAS_EXT_DMA
     /* disable the external DMA if support */
@@ -1430,7 +1434,7 @@ status_t USDHC_SetInternalDmaConfig(USDHC_Type *base,
     if (dmaConfig->dmaMode == kUSDHC_DmaModeSimple)
     {
         /* check DMA data buffer address align or not */
-        if (((uint32_t)dataAddr % USDHC_ADMA2_ADDRESS_ALIGN) != 0UL)
+        if (((uintptr_t)dataAddr % USDHC_ADMA2_ADDRESS_ALIGN) != 0UL)
         {
             return kStatus_USDHC_DMADataAddrNotAlign;
         }
@@ -1438,18 +1442,18 @@ status_t USDHC_SetInternalDmaConfig(USDHC_Type *base,
              and block count should load to DS_ADDR*/
         if (enAutoCmd23)
         {
-            base->ADMA_SYS_ADDR = USDHC_ADDR_CPU_2_DMA((uint32_t)dataAddr);
+            base->ADMA_SYS_ADDR = USDHC_ADDR_CPU_2_DMA((uintptr_t)dataAddr);
         }
         else
         {
-            base->DS_ADDR = USDHC_ADDR_CPU_2_DMA((uint32_t)dataAddr);
+            base->DS_ADDR = USDHC_ADDR_CPU_2_DMA((uintptr_t)dataAddr);
         }
     }
     else
     {
         /* When use ADMA, disable simple DMA */
         base->DS_ADDR       = 0UL;
-        base->ADMA_SYS_ADDR = USDHC_ADDR_CPU_2_DMA((uint32_t)(dmaConfig->admaTable));
+        base->ADMA_SYS_ADDR = USDHC_ADDR_CPU_2_DMA((uintptr_t)(dmaConfig->admaTable));
     }
 
 #if (defined(FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN) && FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN)
@@ -1485,14 +1489,14 @@ status_t USDHC_SetAdmaTableConfig(USDHC_Type *base,
 {
     assert(NULL != dmaConfig);
     assert((NULL != dmaConfig->admaTable) &&
-           (((USDHC_ADMA_TABLE_ADDRESS_ALIGN - 1U) & (uint32_t)dmaConfig->admaTable) == 0UL));
+           (((USDHC_ADMA_TABLE_ADDRESS_ALIGN - 1U) & (uintptr_t)dmaConfig->admaTable) == 0UL));
     assert(NULL != dataConfig);
 
     status_t error = kStatus_Fail;
     uint32_t bootDummyOffset =
         dataConfig->dataType == (uint32_t)kUSDHC_TransferDataBootcontinous ? sizeof(uint32_t) : 0UL;
-    const uint32_t *data = (const uint32_t *)USDHC_ADDR_CPU_2_DMA((uint32_t)(
-        (uint32_t)((dataConfig->rxData == NULL) ? dataConfig->txData : dataConfig->rxData) + bootDummyOffset));
+    const uint32_t *data = (const uint32_t *)USDHC_ADDR_CPU_2_DMA((uintptr_t)(
+        (uintptr_t)((dataConfig->rxData == NULL) ? dataConfig->txData : dataConfig->rxData) + bootDummyOffset));
     uint32_t blockSize   = dataConfig->blockSize * dataConfig->blockCount - bootDummyOffset;
 
 #if FSL_FEATURE_USDHC_HAS_EXT_DMA
@@ -1605,12 +1609,12 @@ status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig
         if (data->txData != NULL)
         {
             /* clear the DCACHE */
-            DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount));
+            DCACHE_CleanByRange((uintptr_t)data->txData, (data->blockSize) * (data->blockCount));
         }
         else
         {
             /* clear the DCACHE */
-            DCACHE_CleanInvalidateByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount));
+            DCACHE_CleanInvalidateByRange((uintptr_t)data->rxData, (data->blockSize) * (data->blockCount));
         }
     }
 #endif
@@ -1926,12 +1930,12 @@ status_t USDHC_TransferNonBlocking(USDHC_Type *base,
         if (data->txData != NULL)
         {
             /* clear the DCACHE */
-            DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount));
+            DCACHE_CleanByRange((uintptr_t)data->txData, (data->blockSize) * (data->blockCount));
         }
         else
         {
             /* clear the DCACHE */
-            DCACHE_CleanInvalidateByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount));
+            DCACHE_CleanInvalidateByRange((uintptr_t)data->rxData, (data->blockSize) * (data->blockCount));
         }
     }
 #endif
@@ -2345,7 +2349,7 @@ static void USDHC_TransferHandleData(USDHC_Type *base, usdhc_handle_t *handle, u
 #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
                 if (handle->data->rxData != NULL)
                 {
-                    DCACHE_InvalidateByRange((uint32_t)(handle->data->rxData),
+                    DCACHE_InvalidateByRange((uintptr_t)(handle->data->rxData),
                                              (handle->data->blockSize) * (handle->data->blockCount));
                 }
 #endif
diff --git a/mcux/mcux-sdk/drivers/usdhc/fsl_usdhc.h b/mcux/mcux-sdk/drivers/usdhc/fsl_usdhc.h
index 4dce57d2b..cf9f852b7 100644
--- a/mcux/mcux-sdk/drivers/usdhc/fsl_usdhc.h
+++ b/mcux/mcux-sdk/drivers/usdhc/fsl_usdhc.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2021, 2025 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -21,8 +21,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief Driver version 2.8.4. */
-#define FSL_USDHC_DRIVER_VERSION (MAKE_VERSION(2U, 8U, 4U))
+/*! @brief Driver version 2.8.5. */
+#define FSL_USDHC_DRIVER_VERSION (MAKE_VERSION(2U, 8U, 5U))
 /*@}*/
 
 /*! @brief Maximum block count can be set one time */
@@ -587,7 +587,11 @@ typedef uint32_t usdhc_adma1_descriptor_t;
 typedef struct _usdhc_adma2_descriptor
 {
     uint32_t attribute;      /*!< The control and status field. */
+#if INTPTR_MAX == INT64_MAX
+    uint32_t address;        /*!< The address field. */
+#else
     const uint32_t *address; /*!< The address field. */
+#endif
 } usdhc_adma2_descriptor_t;
 
 /*!