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recently tried to optimize convolutions using\nSIMD\ninstructions, but what I thought would be a simple task ended up taking me days,\nwith issue after issue popping up one after another. Some of them make sense in\nhindsight, but others were utterly baffling. While the specific examples are for\ndirect convolution, these considerations apply to pretty much any code with a\nhot loop.\n\nNote:\nThis blog post is mostly written from memory, since I didn't keep around every version of the code\nbeing discussed. The values in the benchmarks are a rough recreation of the real values.\n\nBackground\nI work on burn and recently wanted to\noptimize direct convolution on the burn-ndarray CPU backend.\nFor convolutions you need to move a two-dimensional kernel across an input\nfeature map and sum all the values across all input channels. This is repeated\nfor each output channel. The input can have padding pixels of zero-padding\naround the actual data, and the kernel can move in a strided manner (i.e. two\npixels at once). There are many algorithms with different tradeoffs, but I\ndecided to go with direct convolutions since they don't have memory overhead and\nare still very efficient when implemented correctly. The basic outline is that\nyou have many nested loops, some bounds checks and a very frequently executed\nfused-multiply-add (FMA) instruction.\nMy initial implementation looked something like this1 (simplified):\n\nIn this implementation I use several techniques. In addition to SIMD loads and\nfmadds I use the optimized loop order and register blocking (using the\nseq macro) techniques from\nthis paper. I finished the implementation,\nexecuted a benchmark, and... it's slower. More than two times slower than a\nnaive unvectorized2 implementation in fact (~670ms vs ~300ms).\nStarting to investigate\nTo do this I tried to use various profilers,\ncargo-flamegraph,\nsamply and, after a lot of desperation,\nAMD μProf. After a few days of\ntrying to get useful information out of these profilers (and getting μProf to\nwork at all), I realized it wasn't getting me anywhere. The flamegraph and\nhotspots just didn't seem to make any sense at all.\nSo what's the next step?\nReducing the problem\nOk, none of my attempts to profile led to any success. So let's try to reduce\nthe code to only what's actually needed in the benchmark. The benchmark uses\nunpadded, unstrided, undilated and ungrouped convolutions, so I stripped all\npadding checks and all stride/dilation calculations - it was faster, but still\nslow.\nThere was one branch left to eliminate: The check for border pixels in the\nregister-blocking loop.\nJust to check I shortened the loop to only consider pixels up to the last\nmultiple of 8. This yields incorrect results, but should help with debugging\nperformance.\n\nExecuting the benchmark, the code is now significantly faster on a single\nthread than the old code with multiple threads!\n\nThe problem seems to have been a mixture between spilling registers (as someone\npreviously focused on GPU, I was shocked to find modern CPUs only have 16 of\nthem), and too many branches. This is why the profilers didn't lead me anywhere\nuseful. Branching in modern CPUs is just too complicated to be meaningfully\nrepresented by a profiler hotspot. This is probably the biggest takeaway from\nthis article: branches are much worse than you think, because the CPU can't\npredict more than one3 branch per cycle4. A single if statement inside a loop is enough to\nstop any further instructions from being decoded in that cycle. Since optimal performance requires\n2 FMA instructions per cycle (they take 1 cycle with a 5 cycle latency, and Zen 4 has 2 FMA\nunits), having a branch on every instruction massively hamstrings the performance. This may be\ndifferent on Zen 5, but remember, we still have other branches in addition to the ow bounds check\nthat need predicting. So it's worse than 50% performance in practice.\nAlright, now we have a good place to start. Let's start adding things back again\nand see where the performance starts getting bad.\nFirst, we need to deal with the remaining pixels after the register-blocking\ncode. To do this we're going to use a technique, that we'll be using several\nmore times coming up:\nWhy have one loop, when you can have two?\nI mentioned before that I shortened the loop to only deal with clean multiples\nof the register-blocking factor. So the way to deal with these remaining pixels\nis to just... - add another loop.\nWe add a second unblocked loop that starts at the end of the first loop, and\nruns until the edge of the feature map. Since it's not unrolled, we don't need\nto add any bounds checks.\n\nRunning the benchmarks, it's still fast - yay! It's much more efficient to run\ntwo loops than to check if we're in bounds on every iteration.\nAdding back the other variables\nTo add back padding, stride and dilation, without tanking the performance again,\nI decided to use\ncompile-time monomorphization\nto eliminate the common zero-padding and/or unit stride/dilation cases. So I use\na technique I saw used in the original convolution implementation, added by\nJustin Moore, to enable auto-vectorization for unit\nstride convolutions. By adding an if-statement that checks if stride and\ndilation are all 1, we allow the compiler to\nconstant propagate\nthis value into that branch. The inner loop is extracted into a separate,\ninlined function. This trick allows unstrided convolution to be auto-vectorized in the original,\nnon-SIMD implementation.\n\nThe padding support is added back via a const generic bool, that sets the\npadding to 0. This allows the compiler to, once again, constant propagate it.\n\nNice and easy.\nLet's run the benchmark again!\n\nOh. Oh dear. What happened?\nWhen the compiler gets it wrong\nTo explain what just happened I need to add another small background detail I\ndidn't mention before. To use modern SIMD features, the code uses runtime\nfeature selection with pulp. The way\nthis works is that pulp annotates a function with something like\n#[target_feature(enable = \"avx2\")], based on the available features. This\ntells the compiler it's allowed to use avx2 features, even if the target\nwouldn't normally include avx2. However, only inlined functions will have the\nfeatures enabled and non-inlined function calls will not (this is\nforeshadowing).\nThis is where samply starts becoming actually useful. Running it allows me to\nsee the assembly for each function and find the hotspots. And this time they\nare actually meaningful! samply tells me, I'm spending all my time in the\nline that calls the FMA and in the FMA itself. So I take a look at the assembly\nand -oh no!\n\n\nWhy is it using SSE registers instead of AVX registers?\nWhy is it putting them onto the stack?\nIt's using call to execute the\n_mm256_fmadd_ps\nintrinsic for some reason?\n\nTurns out: These things are linked. Coming up is what I think is a pretty\naccurate guess of what happened here.\nSee, the compiler has a size limit for inlined functions. #[inline(always)]\ntells the compiler to ignore the size limit, and almost all of my functions\nwere marked as #[inline(always)]. However, the outermost function was\nnot.\nThese are the steps I think happened next:\n\nAdding these inlined branches caused the size of the function to exceed\nRust's inlining limit\nRust outlined (is that a word?) the top-level function from pulps wrapper\nfunction, the one that is marked with #[target_feature]\nThe compiler now treats my function as a regular function, causing it to\nfall back to the default feature set (x86-64-v1)\nThis means 256-bit registers are no longer available in my function.\nSince _mm256_fmadd_ps is an AVX2 instruction that requires 256-bit\nregisters, the compiler must now call it dynamically and transfer the data\nvia the stack. This is slow. Very slow.\n\nI'm somewhat unsure about that last step, maybe someone with more knowledge of\ncompiler internals can enlighten me on the actual reason the intrinsic is no\nlonger inlined.\nFortunately, the solution was much simpler than this chain of events: Annotate\nthe top-level function with #[inline(always)].\n\nMuch better. And the benchmark?\n\nNice!\nFinishing up the optimizations\nPerformance was good for unpadded convolutions, but would still have been\nlackluster for padded ones, since we need to check if we are in padding in\nevery single loop iteration. To solve this, we can use the same technique we\nused for the out_width earlier: All pixels that are more than padding away\nfrom the edges are guaranteed to always be in bounds, so we can run one loop\nfrom padding_h to out_height - padding_h and padding_w to\nwidth - padding_w without bounds checks, then a second loop for the border\npixels that does do bounds checks. This is much faster than checking every\npixel, since most pixels are always in bounds.\n\nFinal thoughts\nModern CPUs are weird, and performance is not always obvious. Inlining is\nfragile, and adding a single line of code can completely change the way your\nprogram is compiled without you even noticing. Profilers aren't always helpful,\nespecially when your problem is more complex than something like using a slow\nfunction or allocating memory too often. My tip is to just try to figure out\njust when things start getting bad and maybe learn some basic assembly, so you\ncan spot things like way too many stack loads/stores (which indicates register\nspilling).\nI hope this helps someone deal with their performance issues a little bit more\nquickly than I did.\nAlso big shout out once again to samply.\nEven when the performance data didn't mean much, being able to easily view\nassembly for any given function was very useful.\nThe final version of the code for this implementation can be found\nhere.\nAnd just for fun, here is the final benchmark after all optimizations, using\nmulti-threading:\n\n\n\n\n\nI originally used an array of accumulators, but quickly found out that Rust\nwasn't capable of optimizing the constant array indices into a set of\nregister accesses, and instead accessed the value from the stack. For the\nsake of brevity, I omitted this version. ↩\n\n\nIt's actually auto-vectorized using a trick we'll get to later ↩\n\n\nIt's two on Zen 5 ↩\n\n\nThanks to /u/caelunshun for correcting me ↩\n\n\n\n","id":"https://genna.win/blog/convolution-simd/","title":"Performance optimization, and how to do it wrong"}},"docInfo":{"https://genna.win/":{"body":0,"title":0},"https://genna.win/blog/":{"body":0,"title":1},"https://genna.win/blog/convolution-simd/":{"body":992,"title":3}},"length":3},"lang":"English"}