Running in lockstep with Verilog simulator

[weedmank]

"It can also run in lock step with a Verilog simulator serving as a "golden model" against which an implementation is checked after each instruction of a test program."

Do you have documentation how use your ISS "in lock step" with Modelsim/Questasim? I have one open source design I'm creating (www.hdlexpress.com see RisKy1) that I'd like to try and use your ISS with. I'm at a point where I can compile C & assembly code and run the code in my System Verilog simulations of my RTL design.