|
7 | 7 | #define INCLUDE_HW_SPI_H_
|
8 | 8 |
|
9 | 9 | /**
|
10 |
| - * Max supported Hardware SPI speed |
| 10 | + * Max supported Hardware SPI speed (default 10MHz) |
11 | 11 | */
|
12 |
| -#define SPI_MAX_SPEED 10000000U |
| 12 | +#define SPI_MAX_SPEED 32000000U |
| 13 | + |
| 14 | +/** |
| 15 | + * SPI Modes to configure clock polarity and clock phase. |
| 16 | + * |
| 17 | + * For more information see https://en.wikipedia.org/wiki/Serial_Peripheral_Interface#Clock_polarity_and_phase |
| 18 | + */ |
| 19 | +enum spi_mode_e { |
| 20 | + SPI_MODE0,/**< Mode 0 (default): CPOL = 0, CPHA = 0 */ |
| 21 | + SPI_MODE1,/**< Mode 1: CPOL = 0, CPHA = 1 */ |
| 22 | + SPI_MODE2,/**< Mode 2: CPOL = 1, CPHA = 0 */ |
| 23 | + SPI_MODE3,/**< Mode 3: CPOL = 1, CPHA = 1 */ |
| 24 | +}; |
| 25 | + |
| 26 | +/** |
| 27 | + * SPI byte order to configure shit in/out order of data byte. |
| 28 | + */ |
| 29 | +enum spi_byteorder_e { |
| 30 | + SPI_BYTE_MSB_FIRST,/**< MSB sent first (default) */ |
| 31 | + SPI_BYTE_LSB_FIRST,/**< LSB sent first */ |
| 32 | +}; |
| 33 | + |
| 34 | +/** |
| 35 | + * Chip select mode configures how chip select line is de-asserted during a |
| 36 | + * transaction. It only used when hardware chip select is used during |
| 37 | + * initialization. See @ref spi_hw_init |
| 38 | + */ |
| 39 | +enum spi_csmode_e { |
| 40 | + SPI_CSMODE_TRANSACTION,/**< CS line de-asserted between each transaction. |
| 41 | + This is default behavior of CS line. */ |
| 42 | + SPI_CSMODE_BYTE, /**< CS line de-asserted after each byte in a |
| 43 | + transaction */ |
| 44 | +}; |
| 45 | + |
| 46 | +/** |
| 47 | + * Chip select polarity flags |
| 48 | + */ |
| 49 | +enum spi_cspol_e { |
| 50 | + SPI_CSPOL_LOW, /**< Chip select is active low (default) */ |
| 51 | + SPI_CSPOL_HIGH,/**< Chip select is active high */ |
| 52 | +}; |
13 | 53 |
|
14 | 54 | #ifdef __cplusplus
|
15 | 55 | extern "C" {
|
16 | 56 | #endif
|
17 | 57 |
|
18 | 58 | /**
|
19 | 59 | * Initialize SPI Hardware and setup pinmux
|
20 |
| - * @param managed_cs [in] Set it TRUE, if application software manages chip select status, FALSE otherwise |
21 |
| - * @param clock_hz [in] SPI Clock speed |
22 |
| - * @param mode [in] SPI Mode (0-3) |
23 |
| - * @return 0 on success, negative on error |
| 60 | + * @param int hardware_cs [in] Set it TRUE, if application hardware chip |
| 61 | + * select is used and hardware controls chip |
| 62 | + * select status, FALSE otherwise |
| 63 | + * @return 0 on success, negative on error |
24 | 64 | */
|
25 |
| -int spi_hw_init(int managed_cs, unsigned int clock_hz, int mode); |
| 65 | +int spi_hw_init(int hardware_cs); |
26 | 66 |
|
27 | 67 | /**
|
28 |
| - * SPI Master harware read |
29 |
| - * @param buf [out] Pointer to buffer where received data is stored |
30 |
| - * @param len [in] Data to read |
31 |
| - * @return Length of data read on success, negative on error |
| 68 | + * Set/Change SPI clock speed. Default speed is @ref SPI_MAX_SPEED |
| 69 | + * @param clock_hz [in] Clock speed in Hz |
| 70 | + * @return 0 on success, negative value on error |
32 | 71 | */
|
33 |
| -int spi_hw_read(unsigned char *buf, int len); |
| 72 | +int spi_hw_setclock(unsigned long clock_hz); |
34 | 73 |
|
35 | 74 | /**
|
36 |
| - * SPI Master write |
37 |
| - * @param buf [in] Pointer to data buffer to write |
38 |
| - * @param len [in] Length of data in buffer |
39 |
| - * @return Length of data written on success, negative on error |
| 75 | + * Configure SPI clock mode |
| 76 | + * @param mode [in] SPI mode, see @ref spi_mode_e |
| 77 | + * @return 0 on success, negative value on error |
40 | 78 | */
|
41 |
| -int spi_hw_write(const unsigned char *buf, int len); |
| 79 | +int spi_hw_setmode(int mode); |
42 | 80 |
|
43 | 81 | /**
|
44 |
| - * SPI Master write then read |
45 |
| - * @param wrbuf [in] Pointer to data buffer to write |
46 |
| - * @param wrlen [in] Length of data to write |
47 |
| - * @param rdbuf [out] Pointer to buffer to store data |
48 |
| - * @param rdlen [in] Length of data to read |
49 |
| - * @return Length of data read on success, negative on error |
| 82 | + * Configure SPI byte shift order |
| 83 | + * @param byte_order [in] SPI byte order, see @ref spi_byteorder_e |
| 84 | + * @return 0 on success, negative value on error |
50 | 85 | */
|
51 |
| -int spi_hw_writeread(const unsigned char *wrbuf, int wrlen, unsigned char *rdbuf, int rdlen); |
| 86 | +int spi_hw_setbyteorder(int byte_order); |
52 | 87 |
|
53 | 88 | /**
|
54 |
| - * Set/Change SPI clock speed |
55 |
| - * @param clock_hz [in] Clock speed in Hz |
| 89 | + * Configure chip-select line. Only needed when hardware_cs is used |
| 90 | + * @param cs_mode [in] Chip select mode, see @ref spi_csmode_e |
| 91 | + * @param cs_pol [in] Chip select polarity, see @ref spi_cspol_e |
| 92 | + * @return 0 on success, negative value on error |
56 | 93 | */
|
57 |
| -void spi_hw_setclock(unsigned int clock_hz); |
| 94 | +int spi_hw_setcsmode(int cs_mode, int cs_pol); |
58 | 95 |
|
59 | 96 | /**
|
60 |
| - * Get currently set SPI clock speed |
61 |
| - * @return Clock speed in Hz |
| 97 | + * Perform SPI transaction |
| 98 | + * @param wrbuf [in] Pointer to data buffer to write, can be NULL |
| 99 | + * if only read operation to be performed |
| 100 | + * @param rdbuf [out] Pointer to buffer to store data, can be NULL |
| 101 | + * if only write operation to be performed |
| 102 | + * @param length [in] Length of data to read/write |
| 103 | + * @return Length of data read/write on success, negative on error |
62 | 104 | */
|
63 |
| -unsigned int spi_hw_getclock(void); |
| 105 | +int spi_hw_transfer(const unsigned char *wrbuf, unsigned char *rdbuf, int length); |
64 | 106 |
|
65 | 107 | /**
|
66 | 108 | * Release SPI hardware
|
67 |
| - * @return 0 on success, negative on error |
| 109 | + * @return 0 on success, negative on error |
68 | 110 | */
|
69 | 111 | int spi_hw_free(void);
|
70 | 112 |
|
|
0 commit comments