From e8cffbed9031f90aee0aaeee17407ea600b68c35 Mon Sep 17 00:00:00 2001 From: lecorre-m Date: Mon, 6 May 2024 12:27:18 +0200 Subject: [PATCH 1/3] rework directory and expand zips Signed-off-by: lecorre-m --- build_pcb/backside.zip | Bin 615171 -> 0 bytes build_pcb/front_integrated.zip | Bin 286794 -> 0 bytes build_pcb/front_thin_lfo.zip | Bin 476070 -> 0 bytes build_pcb/longan_adapters.zip | Bin 67068 -> 0 bytes build_pcb/middle.zip | Bin 1790352 -> 0 bytes code/script_icon.zip | Bin 1954 -> 0 bytes code/script_lut.zip | Bin 894 -> 0 bytes code/script_menu.zip | Bin 1790 -> 0 bytes code/src_generic.zip | Bin 91926 -> 0 bytes code/src_midi2cv.zip | Bin 1346262 -> 0 bytes {code => firmware}/README.md | 0 firmware/generic/src/data/font.cpp | 119 + firmware/generic/src/data/frequency.cpp | 9 + firmware/generic/src/data/images.cpp | 7 + firmware/generic/src/drivers/SysTick.cpp | 67 + firmware/generic/src/drivers/SysTick.h | 16 + firmware/generic/src/drivers/adc.cpp | 28 + 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firmware/generic/src/data/font.cpp create mode 100644 firmware/generic/src/data/frequency.cpp create mode 100644 firmware/generic/src/data/images.cpp create mode 100644 firmware/generic/src/drivers/SysTick.cpp create mode 100644 firmware/generic/src/drivers/SysTick.h create mode 100644 firmware/generic/src/drivers/adc.cpp create mode 100644 firmware/generic/src/drivers/adc.h create mode 100644 firmware/generic/src/drivers/display.cpp create mode 100644 firmware/generic/src/drivers/display.h create mode 100644 firmware/generic/src/drivers/encoder.cpp create mode 100644 firmware/generic/src/drivers/encoder.h create mode 100644 firmware/generic/src/drivers/led.h create mode 100644 firmware/generic/src/drivers/scope.cpp create mode 100644 firmware/generic/src/drivers/scope.h create mode 100644 firmware/generic/src/drivers/spi.cpp create mode 100644 firmware/generic/src/drivers/spi.h create mode 100644 firmware/generic/src/drivers/timer.cpp create mode 100644 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b/firmware/README.md similarity index 100% rename from code/README.md rename to firmware/README.md diff --git a/firmware/generic/src/data/font.cpp b/firmware/generic/src/data/font.cpp new file mode 100644 index 0000000..cc35ec4 --- /dev/null +++ b/firmware/generic/src/data/font.cpp @@ -0,0 +1,119 @@ +extern "C" +{ +#include "gd32vf103.h" + extern const uint8_t font[1520] ; +} + +/* + Font copied from https://github.com/sipeed/Longan_GD32VF_examples.git + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +const uint8_t font[1520]={ +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x00,0x00,0x18,0x18,0x00,0x00, +0x00,0x48,0x6C,0x24,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x24,0x24,0x24,0x7F,0x12,0x12,0x12,0x7F,0x12,0x12,0x12,0x00,0x00, +0x00,0x00,0x08,0x1C,0x2A,0x2A,0x0A,0x0C,0x18,0x28,0x28,0x2A,0x2A,0x1C,0x08,0x08, +0x00,0x00,0x00,0x22,0x25,0x15,0x15,0x15,0x2A,0x58,0x54,0x54,0x54,0x22,0x00,0x00, +0x00,0x00,0x00,0x0C,0x12,0x12,0x12,0x0A,0x76,0x25,0x29,0x11,0x91,0x6E,0x00,0x00, +0x00,0x06,0x06,0x04,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x40,0x20,0x10,0x10,0x08,0x08,0x08,0x08,0x08,0x08,0x10,0x10,0x20,0x40,0x00, +0x00,0x02,0x04,0x08,0x08,0x10,0x10,0x10,0x10,0x10,0x10,0x08,0x08,0x04,0x02,0x00, +0x00,0x00,0x00,0x00,0x08,0x08,0x6B,0x1C,0x1C,0x6B,0x08,0x08,0x00,0x00,0x00,0x00, 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a/firmware/generic/src/data/frequency.cpp b/firmware/generic/src/data/frequency.cpp new file mode 100644 index 0000000..00767e2 --- /dev/null +++ b/firmware/generic/src/data/frequency.cpp @@ -0,0 +1,9 @@ +extern "C" +{ +#include "gd32vf103.h" + extern const float freq[2113]; +} + +// logaritmic frequency look up table (generated with python script - covers MIDI range for -3V to 8V CV) +const float freq[2113] = {24.135547645748918, 24.22283785971846, 24.310443773234866, 24.398366528077922, 24.48660727015689, 24.5751671495254, 24.6640473203964, 24.753248941157278, 24.842773174384938, 24.93262118686087, 25.02279414958649, 25.113293237798324, 25.204119630983286, 25.295274512894157, 25.386759071564942, 25.478574499326342, 25.57072199282135, 25.66320275302082, 25.75601798523907, 25.849168899149685, 25.94265670880125, 26.036482632633078, 26.13064789349125, 26.22515371864445, 26.320001339799955, 26.41519199311974, 26.510726919236586, 26.606607363270175, 26.702834574843408, 26.799409808098666, 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44036.76868446777, 44196.03496743829, 44355.87726335536, 44516.2976554655, 44677.29823454968, 44838.88109895015, 45001.04835459851, 45163.802115042825, 45327.1445014748, 45491.07764275814, 45655.60367545592, 45820.72474385812, 45986.443000010244, 46152.76060374103, 46319.67972269022, 46487.20253233758, 46655.33121603081, 46824.067965013746, 46993.414978455534, 47163.374463479, 47333.94863518904, 47505.1397167022, 47676.94993917529, 47849.38154183411, 48022.43677200337, 48196.11788513557, 48370.4271448401, 48545.36682291341, 48720.93919936829, 48897.1465624632, 49073.99120873285, 49251.475443017705, 49429.601578493784}; + diff --git a/firmware/generic/src/data/images.cpp b/firmware/generic/src/data/images.cpp new file mode 100644 index 0000000..9f89ab6 --- /dev/null +++ b/firmware/generic/src/data/images.cpp @@ -0,0 +1,7 @@ +extern "C" +{ +#include "gd32vf103.h" +} + + +const uint8_t img1[176] = {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 50, 8, 102, 66, 38, 15, 115, 1, 66, 1, 34, 1, 130, 0, 70, 0, 32, 0, 131, 0, 72, 0, 30, 0, 131, 0, 74, 0, 28, 0, 255, 116, 0, 76, 0, 26, 0, 255, 255, 112, 24, 9, 24, 45, 11, 120, 0, 33, 0, 69, 0, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 146, 0, 239, 68, 255, 255, 130, 0, 76, 0, 26, 0, 104, 0, 210, 0, 55, 0, 74, 0, 28, 0, 74, 0, 28, 0, 27, 0, 72, 0, 30, 0, 72, 0, 30, 0, 27, 0, 70, 0, 32, 0, 70, 0, 32, 0, 27, 1, 66, 1, 34, 1, 66, 1, 34, 1, 27, 66, 38, 2, 25, 8, 25, 2, 38, 2, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 252}; diff --git a/firmware/generic/src/drivers/SysTick.cpp b/firmware/generic/src/drivers/SysTick.cpp new file mode 100644 index 0000000..1f34d47 --- /dev/null +++ b/firmware/generic/src/drivers/SysTick.cpp @@ -0,0 +1,67 @@ +extern "C" { +#include "gd32vf103.h" +} +#include +#include "SysTick.h" +static SysTick *pSysTick = 0; +void SysTick::begin(uint32_t usPeriod) +{ + pSysTick = this; + SystemClockSpeed = 108000000/8; // the GD32VF103 divides the high speed clock by 8 + Period = usPeriod; + Period = Period * SystemClockSpeed; + Period = Period / 1000000; + NextInterruptTime = Period; + // Zero the clock to start with + *(volatile uint32_t *)(TIMER_CTRL_ADDR + TIMER_MTIME + 4)=0; + *(volatile uint32_t *)(TIMER_CTRL_ADDR + TIMER_MTIME )=0; + *(volatile uint32_t *)(TIMER_CTRL_ADDR + TIMER_MTIMECMP + 4)=NextInterruptTime >> 32; + *(volatile uint32_t *)(TIMER_CTRL_ADDR + TIMER_MTIMECMP ) = NextInterruptTime & 0xffffffff; + eclic_enable_interrupt(CLIC_INT_TMR); +} +void SysTick::OnInterrupt() +{ + // At each interrupt the Timer compare register has to be updated to the next + // interrupt time. + NextInterruptTime += Period; + *(volatile uint32_t *)(TIMER_CTRL_ADDR + TIMER_MTIMECMP + 4)=NextInterruptTime >> 32; + *(volatile uint32_t *)(TIMER_CTRL_ADDR + TIMER_MTIMECMP ) = NextInterruptTime & 0xffffffff; + + // LED blink (relies on the LED port bits being initialized elsewhere) + static int State = 0; + if (State) + { + GPIO_BOP(GPIOA) = GPIO_PIN_1; + State = 0; + } + else + { + GPIO_BC(GPIOA) = GPIO_PIN_1; + State = 1; + } +} +void SysTick::delay(uint32_t msdly) +{ +// delay for thet specified number of milliseconds; + uint64_t EndTime = msdly; + EndTime = (EndTime * SystemCoreClock/8000); + EndTime = EndTime + get_timer_value(); + + while(get_timer_value() < EndTime); +} + +// The interrupt handler for the internal timer. C naming is required +// to allow it to over-ride the weak symbol defined in the startup code. +// Also have to insert assembler to back up and restore registers prior +// to calling C++ interrupt handler +// Based on initial investigations it would seem that context is saved +// before entry in to this function and restored afterwards i.e. this +// is not an interrupt service routine in the true sense - it is a +// function called by another interrupt handler buried deeper in the +// SDK. +extern "C" { +void eclic_mtip_handler() +{ + pSysTick->OnInterrupt(); +} +} diff --git a/firmware/generic/src/drivers/SysTick.h b/firmware/generic/src/drivers/SysTick.h new file mode 100644 index 0000000..653bdf9 --- /dev/null +++ b/firmware/generic/src/drivers/SysTick.h @@ -0,0 +1,16 @@ +#ifndef __SysTick_h +#define __SysTick_h +#include +class SysTick{ + +public: + SysTick() {}; + void begin(uint32_t usPeriod); + void OnInterrupt(); + void delay(uint32_t msdly); +private: + uint64_t SystemClockSpeed; + uint64_t NextInterruptTime; + uint64_t Period; +}; +#endif \ No newline at end of file diff --git a/firmware/generic/src/drivers/adc.cpp b/firmware/generic/src/drivers/adc.cpp new file mode 100644 index 0000000..0abe2bc --- /dev/null +++ b/firmware/generic/src/drivers/adc.cpp @@ -0,0 +1,28 @@ +#include "adc.h" +extern "C" +{ +#include "gd32vf103.h" +} + +// anUpdate (downshifted oversampling) +uint8_t anCount = 0; // counter for oversampling (new value after 255, @44,4KHz => 173Hz, suitable for potentiometers) +uint32_t anTotal[MAX_AN]; // the running total +int anAvg[MAX_AN]; // analog average +uint16_t anRaw[8]; // raw sampled values stored by DMA + +// analog average (downshifted oversampling) +void adc::update(uint8_t ch) +{ + if (anCount < 255) + { + anTotal[ch] += anRaw[ch]; + } + else + { + if (ch == 2 || ch == 3) // these potentiometers are inverted due to routing + anAvg[ch] = 4095 - (anTotal[ch] >> 8); // note that raw[2] and raw[3] is still inverted... + else + anAvg[ch] = anTotal[ch] >> 8; // inputs and pot 3 is not inverted + anTotal[ch] = 0; + } +} \ No newline at end of file diff --git a/firmware/generic/src/drivers/adc.h b/firmware/generic/src/drivers/adc.h new file mode 100644 index 0000000..4bca932 --- /dev/null +++ b/firmware/generic/src/drivers/adc.h @@ -0,0 +1,22 @@ +#ifndef __adc_h +#define __adc_h +extern "C" +{ +#include +} + +#define MAX_AN 5 // number of analog filters + +class adc +{ +public: + adc(){}; + uint16_t anRaw[8]; // raw sampled values stored by DMA + int anAvg[MAX_AN]; // analog average + uint8_t anCount; // counter for oversampling (new value after 255, @44,4KHz => 173Hz, suitable for potentiometers) + void update(uint8_t ch); + +private: + uint32_t anTotal[MAX_AN]; // the running total +}; +#endif \ No newline at end of file diff --git a/firmware/generic/src/drivers/display.cpp b/firmware/generic/src/drivers/display.cpp new file mode 100644 index 0000000..a9bfb3c --- /dev/null +++ b/firmware/generic/src/drivers/display.cpp @@ -0,0 +1,581 @@ +#include +#include "display.h" +#include "spi.h" +#include "SysTick.h" +extern "C" +{ +#include "gd32vf103.h" +} +extern SysTick stk; +/* + The LCD display on the eurorack module is an ST7789 with a resolution + of 240 x 240 + It's an SPI device connected as follows: + SCK PB13 (SCK1) + MOSI PB15 (MOSI1) + RST PA8 (reset) + DC PA11 (aka RS) + BLK PB10 (backlight) + +*/ + +/* + The LCD display on the sipeed longan nano seems to be an ST7735 with a resolution + of 160 x 80 + It's an SPI device connected as follows: + SCK PA5 (SCK0) + MOSI PA7 (MOSI0) + RS PB0 + RST PB1 + CS PB2 +*/ +void display::begin(spi *SPI, const uint8_t *font) +{ + + this->SPI = SPI; // remember the SPI interface + XYSwapped = 0; // XY Not swapped to begin with + + // Turn on Port A + rcu_periph_clock_enable(RCU_GPIOA); + // Turn on Port B + rcu_periph_clock_enable(RCU_GPIOB); + + // Configure the various control pins + gpio_init(GPIOA, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_8 | GPIO_PIN_11); + gpio_init(GPIOB, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_10); + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13 | GPIO_PIN_15); + SPI->begin(); + + // Initialization sequence from Longan sample code + RSTHigh(); // Drive reset high + stk.delay(25); // wait + RSTLow(); // Drive reset low + stk.delay(250); // wait + RSTHigh(); // Drive reset high + stk.delay(25); // wait + + writeCommand(0x01); // sw reset + stk.delay(150); // wait + + writeCommand(0x11); // turn off sleep mode + stk.delay(100); + + writeCommand(0x3A); // set color mode + writeData8(0x55); // 16 bit color + stk.delay(10); + + writeCommand(0x36); // Color order RGB:0x00 BGR:0x08 + writeData8(0x00); // + + // power settings + writeCommand(0xb2); // porch control + writeData8(0x0c); + writeData8(0x0c); + writeData8(0x00); + writeData8(0x33); + writeData8(0x33); + writeCommand(0xb7); // gate control + writeData8(0x35); + writeCommand(0xbb); // vcoms + writeData8(0x28); + writeCommand(0xc0); // LCM control + writeData8(0x0c); + writeCommand(0xc2); // VDV and VRH command enable + writeData8(0x01); + writeData8(0xff); + writeCommand(0xc3); // voltage VRHS set + writeData8(0x10); + writeCommand(0xc4); // VDV set + writeData8(0x20); + writeCommand(0xc6); // FR control 2 + writeData8(0x0f); + writeCommand(0xd0); // power control 1 + writeData8(0xa4); + writeData8(0xa1); + + writeCommand(0xe0); // positive gamma control + writeData8(0xd0); + writeData8(0x00); + writeData8(0x02); + writeData8(0x07); + writeData8(0x0a); + writeData8(0x28); + writeData8(0x32); + writeData8(0x44); + writeData8(0x42); + writeData8(0x06); + writeData8(0x0e); + writeData8(0x12); + writeData8(0x14); + writeData8(0x17); + + writeCommand(0xe1); // negative gamma control + writeData8(0xd0); + writeData8(0x00); + writeData8(0x02); + writeData8(0x07); + writeData8(0x0a); + writeData8(0x28); + writeData8(0x31); + writeData8(0x54); + writeData8(0x47); + writeData8(0x0e); + writeData8(0x1c); + writeData8(0x17); + writeData8(0x1b); + writeData8(0x1e); + + writeCommand(0x2A); // column address set + writeData8(0x00); // + writeData8(0x00); // x start + writeData8(0x00); // + writeData8(0xef); // x end (240) + + writeCommand(0x2B); // row address set + writeData8(0x00); // + writeData8(0x00); // y start + writeData8(0x00); // y end upper + writeData8(0xef); // y end lower (240) + + writeCommand(0x21); // invon + stk.delay(10); + writeCommand(0x13); // normal display on + stk.delay(10); + writeCommand(0x29); // main screen turn on + stk.delay(10); + + BLKHigh(); // turn on backlight + fillRectangle(0, 0, SCREEN_WIDTH, SCREEN_HEIGHT, 0x0000); // black out the screen +} + +void display::showImg(const uint8_t *img, uint16_t size, uint8_t x, uint8_t y, uint16_t width, uint16_t height, uint16_t color) +{ + uint8_t preRow[width]; + uint8_t pixel = 0; + uint8_t invert = 0; + uint8_t pixelCount; + uint16_t rgb = 0; + for (uint8_t i = 0; i < width; i++) + preRow[i] = 0; + openAperture(x, y, x + width, y + height); + for (uint16_t pImg = 0; pImg < size; pImg++) + { + pixelCount = *(img + pImg); + if (pixelCount < 255) + { + pixelCount++; + invert = 1; + } + while (pixelCount > 0) + { + preRow[x] ^= pixel; + rgb = RGBToWord(0x0, 0x0, 0x0); + if (preRow[x] != 0) + { + rgb = color; + } + writeData16(rgb); + pixelCount--; + x++; + if (x == width) + x = 0; + } + if (invert == 1) + { + pixel ^= 1; + invert = 0; + } + } +} + +void display::putChar(char ch, uint8_t x, uint8_t y, uint16_t txtFg, uint16_t txtBg) +{ + if ((' ' <= ch) && (ch <= '~')) // 7bit ASCII + { + openAperture(x, y, x + 8 - 1, y + 16 - 1); + ch += 4; + const uint8_t *charFont = _font + (uint8_t)ch * 16; + for (uint8_t y = 0; y < 16; ++y) + { + for (uint8_t x = 0, c = charFont[y]; x < 8; ++x, c >>= 1) + { + uint16_t rgb = (c & 0x01) ? txtFg : txtBg; + writeData16(rgb); + } + } + } +} + +void display::putStr(const char *str, uint8_t x, uint8_t y, uint16_t txtFg, uint16_t txtBg) +{ + while (*str) + putChar(*(str++), x += 9, y, txtFg, txtBg); +} + +void display::putPixel(uint16_t x, uint16_t y, uint16_t colour) +{ + openAperture(x, y, x + 1, y + 1); + writeData16(colour); +} + +void display::putImage(uint16_t x, uint16_t y, uint16_t width, uint16_t height, const uint16_t *Image) +{ + uint16_t Colour; + openAperture(x, y, x + width - 1, y + height - 1); + for (y = 0; y < height; y++) + { + for (x = 0; x < width; x++) + { + Colour = *(Image++); + writeData16(Colour); + } + } +} +void display::drawRectangle(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint16_t Colour) +{ + drawLine(x, y, x + w, y, Colour); + drawLine(x, y, x, y + h, Colour); + drawLine(x + w, y, x + w, y + h, Colour); + drawLine(x, y + h, x + w, y + h, Colour); +} +void display::fillRectangle(uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint16_t Colour) +{ + openAperture(x, y, x + width - 1, y + height - 1); + for (y = 0; y < height; y++) + { + for (x = 0; x < width; x++) + { + writeData16(Colour); + } + } +} +void display::drawCircle(uint16_t x0, uint16_t y0, uint16_t radius, uint16_t Colour) +{ + // Reference : https://en.wikipedia.org/wiki/Midpoint_circle_algorithm + int x = radius - 1; + int y = 0; + int dx = 1; + int dy = 1; + int err = dx - (radius << 1); + if (radius > x0) + return; // don't draw even parially off-screen circles + if (radius > y0) + return; // don't draw even parially off-screen circles + + if ((x0 + radius) > SCREEN_WIDTH) + return; // don't draw even parially off-screen circles + if ((y0 + radius) > SCREEN_HEIGHT) + return; // don't draw even parially off-screen circles + while (x >= y) + { + putPixel(x0 + x, y0 + y, Colour); + putPixel(x0 + y, y0 + x, Colour); + putPixel(x0 - y, y0 + x, Colour); + putPixel(x0 - x, y0 + y, Colour); + putPixel(x0 - x, y0 - y, Colour); + putPixel(x0 - y, y0 - x, Colour); + putPixel(x0 + y, y0 - x, Colour); + putPixel(x0 + x, y0 - y, Colour); + + if (err <= 0) + { + y++; + err += dy; + dy += 2; + } + + if (err > 0) + { + x--; + dx += 2; + err += dx - (radius << 1); + } + } +} +void display::fillCircle(uint16_t x0, uint16_t y0, uint16_t radius, uint16_t Colour) +{ + // Reference : https://en.wikipedia.org/wiki/Midpoint_circle_algorithm + // Similar to drawCircle but fills the circle with lines instead + int x = radius - 1; + int y = 0; + int dx = 1; + int dy = 1; + int err = dx - (radius << 1); + + if (radius > x0) + return; // don't draw even parially off-screen circles + if (radius > y0) + return; // don't draw even parially off-screen circles + + if ((x0 + radius) > SCREEN_WIDTH) + return; // don't draw even parially off-screen circles + if ((y0 + radius) > SCREEN_HEIGHT) + return; // don't draw even parially off-screen circles + while (x >= y) + { + drawLine(x0 - x, y0 + y, x0 + x, y0 + y, Colour); + drawLine(x0 - y, y0 + x, x0 + y, y0 + x, Colour); + drawLine(x0 - x, y0 - y, x0 + x, y0 - y, Colour); + drawLine(x0 - y, y0 - x, x0 + y, y0 - x, Colour); + + if (err <= 0) + { + y++; + err += dy; + dy += 2; + } + + if (err > 0) + { + x--; + dx += 2; + err += dx - (radius << 1); + } + } +} +void display::drawLineLowSlope(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1, uint16_t Colour) +{ + // Reference : https://en.wikipedia.org/wiki/Bresenham%27s_line_algorithm + int dx = x1 - x0; + int dy = y1 - y0; + int yi = 1; + if (dy < 0) + { + yi = -1; + dy = -dy; + } + int D = 2 * dy - dx; + + int y = y0; + + for (int x = x0; x <= x1; x++) + { + putPixel(x, y, Colour); + if (D > 0) + { + y = y + yi; + D = D - 2 * dx; + } + D = D + 2 * dy; + } +} + +void display::drawLineHighSlope(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1, uint16_t Colour) +{ + // Reference : https://en.wikipedia.org/wiki/Bresenham%27s_line_algorithm + + int dx = x1 - x0; + int dy = y1 - y0; + int xi = 1; + if (dx < 0) + { + xi = -1; + dx = -dx; + } + int D = 2 * dx - dy; + int x = x0; + + for (int y = y0; y <= y1; y++) + { + putPixel(x, y, Colour); + if (D > 0) + { + x = x + xi; + D = D - 2 * dy; + } + D = D + 2 * dx; + } +} +void display::drawLine(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1, uint16_t Colour) +{ + // Reference : https://en.wikipedia.org/wiki/Bresenham%27s_line_algorithm + if (iabs(y1 - y0) < iabs(x1 - x0)) + { + if (x0 > x1) + { + drawLineLowSlope(x1, y1, x0, y0, Colour); + } + else + { + drawLineLowSlope(x0, y0, x1, y1, Colour); + } + } + else + { + if (y0 > y1) + { + drawLineHighSlope(x1, y1, x0, y0, Colour); + } + else + { + drawLineHighSlope(x0, y0, x1, y1, Colour); + } + } +} + +void display::openAperture(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2) +{ + // open up an area for drawing on the display + /* + // For some strange reason, the LCD on the Sipeed Longan Nano has a 26 pixel + // offset on the x dimension and 1 pixel on the y-dimension + if (!XYSwapped) + { + x1 += 26; + x2 += 26; + y1++; + y2++; + } + else + { + y1 += 26; + y2 += 26; + x1++; + x2++; + } + */ + writeCommand(0x2A); // Set X limits + RSHigh(); + CSLow(); + SPI->writeData8(x1 >> 8); + SPI->writeData8(x1 & 0xff); + SPI->writeData8(x2 >> 8); + SPI->writeData8(x2 & 0xff); + CSHigh(); + writeCommand(0x2B); // Set Y limits + RSHigh(); + CSLow(); + SPI->writeData8(y1 >> 8); + SPI->writeData8(y1 & 0xff); + SPI->writeData8(y2 >> 8); + SPI->writeData8(y2 & 0xff); + CSHigh(); + writeCommand(0x2c); // put display in to data write mode +} + +void display::RSLow() +{ // drive D/C pin low + gpio_bit_reset(GPIOA, GPIO_PIN_11); +} +void display::RSHigh() +{ // drive D/C pin high + gpio_bit_set(GPIOA, GPIO_PIN_11); +} +void display::RSTLow() +{ // Drive reset low + gpio_bit_reset(GPIOA, GPIO_PIN_8); +} +void display::RSTHigh() +{ // Drive reset high + gpio_bit_set(GPIOA, GPIO_PIN_8); +} +void display::CSLow() +{ // Drive chip select low + // gpio_bit_reset(GPIOB,GPIO_PIN_2); +} +void display::CSHigh() +{ // Drive chip select high + // gpio_bit_set(GPIOB,GPIO_PIN_2); +} +void display::BLKLow() +{ // Drive backlight low (off) + gpio_bit_reset(GPIOB, GPIO_PIN_10); +} +void display::BLKHigh() +{ // Drive backlight high (on) + gpio_bit_set(GPIOB, GPIO_PIN_10); +} +void display::writeCommand(uint8_t Cmd) +{ + RSLow(); + CSLow(); + SPI->writeData8(Cmd); + CSHigh(); +} +void display::writeData8(uint8_t Data) +{ + RSHigh(); + CSLow(); + SPI->writeData8(Data); + CSHigh(); +} +void display::writeData16(uint16_t Data) +{ + RSHigh(); + CSLow(); + SPI->writeData16(Data); + CSHigh(); +} +void display::exchangeXY() +{ + writeCommand(0x36); + if (!XYSwapped) + { + XYSwapped = 1; + writeData8(0x20); + } + else + { + XYSwapped = 0; + writeData8(0x00); + } +} +uint32_t display::getWidth() +{ + if (!XYSwapped) + { + return SCREEN_WIDTH; + } + else + { + return SCREEN_HEIGHT; + } +} +uint32_t display::getHeight() +{ + if (!XYSwapped) + { + return SCREEN_HEIGHT; + } + else + { + return SCREEN_WIDTH; + } +} + +void display::showSprite(const uint8_t *rle_data, uint16_t size) +{ + const uint8_t *__ip, *__il, *__rd; + __ip = (rle_data); + __il = __ip + (size)*2; + __rd = (rle_data); + { /* RGB16 */ + while (__ip < __il) + { + uint16_t __l = *(__rd++); + if (__l & 128) + { + __l = __l - 128; + do + { + // memcpy (__ip, __rd, 2); + writeData8(*__rd); + writeData8(*(__rd + 1)); + __ip += 2; + } while (--__l); + __rd += 2; + } + else + { + __l *= 2; + //memcpy (__ip, __rd, __l); + for (int i = 0; i < __l; i++) + { + writeData8(*(__rd + i)); + } + __ip += __l; + __rd += __l; + } + } + } +} diff --git a/firmware/generic/src/drivers/display.h b/firmware/generic/src/drivers/display.h new file mode 100644 index 0000000..0242612 --- /dev/null +++ b/firmware/generic/src/drivers/display.h @@ -0,0 +1,58 @@ +#ifndef __display_h +#define __display_h +#include +#include "spi.h" +// Assumption: Top left of display is 0,0 +#define SCREEN_WIDTH 240 +#define SCREEN_HEIGHT 240 +// Define a macro to allow easy definition of colours +// Format of colour value: +//#define RGBToWord( R, G, B) ( ((G&0xf8) << (11-3)) | ((R&0xfc) << (5-2)) | ((B&0xf8)>>3) ) +#define RGBToWord( R, G, B) ( ((B&0xf8) << (11-3)) | ((G&0xfc) << (5-2)) | ((R&0xf8)>>3) ) +class display +{ +public: + display(){}; + void begin(spi *SPI, const uint8_t *font); + void showImg(const uint8_t *img, uint16_t size, uint8_t x, uint8_t y, uint16_t width, uint16_t height, uint16_t color); + void putChar(char ch, uint8_t x, uint8_t y, uint16_t txtFg, uint16_t txtBg); + void putStr(const char *str, uint8_t x, uint8_t y, uint16_t txtFg, uint16_t txtBg); + void putPixel(uint16_t x, uint16_t y, uint16_t colour); + void putImage(uint16_t x, uint16_t y, uint16_t width, uint16_t height, const uint16_t *Image); + void drawRectangle(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint16_t Colour); + void fillRectangle(uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint16_t Colour); + void drawCircle(uint16_t x0, uint16_t y0, uint16_t radius, uint16_t Colour); + void fillCircle(uint16_t x0, uint16_t y0, uint16_t radius, uint16_t Colour); + void drawLineLowSlope(uint16_t x0, uint16_t y0, uint16_t x1,uint16_t y1, uint16_t Colour); + void drawLineHighSlope(uint16_t x0, uint16_t y0, uint16_t x1,uint16_t y1, uint16_t Colour); + void drawLine(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1, uint16_t Colour); + void openAperture(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2); + void exchangeXY(); + uint32_t getWidth(); + uint32_t getHeight(); + void showSprite(const uint8_t *rle_data, uint16_t size); +private: + void RSLow(); + void RSHigh(); + void resetDisplay(); + void writeCommand(uint8_t Cmd); + void writeData8(uint8_t Data); + void writeData16(uint16_t Data); + void RSTLow(); + void RSTHigh(); + void CSLow(); + void CSHigh(); + void BLKLow(); + void BLKHigh(); + int iabs(int x) // simple integer version of abs for use by graphics functions + { + if (x < 0) + return -x; + else + return x; + } + spi *SPI; + int XYSwapped; + const uint8_t *_font ; // ' ' .. '~' +}; +#endif \ No newline at end of file diff --git a/firmware/generic/src/drivers/encoder.cpp b/firmware/generic/src/drivers/encoder.cpp new file mode 100644 index 0000000..45e2304 --- /dev/null +++ b/firmware/generic/src/drivers/encoder.cpp @@ -0,0 +1,51 @@ +extern "C" +{ +#include "gd32vf103.h" +} +#include "encoder.h" + +// Check rotation encoder for changes. +// Does not use gpio interrupts, designed to be called @ ~44Khz inside timer int. + +char encoder::get() +{ + uint16_t portB = gpio_input_port_get(GPIOB) & 0x70; // PB4 select, PB5 & PB6 encoder data + if (portB == 0x70) + { + if (ccCount > 0) + ccCount--; + if (cwCount > 0) + cwCount--; + if (ccCount == 0 && cwCount == 0) + { + encDir = 0; + } + } + else if (cwCount < 32 && portB == 0x50) + cwCount++; + else if (ccCount < 32 && portB == 0x30) + ccCount++; + + // test clockwise + if (cwCount == 32 && encDir == 0) + { + encDir = 'W'; + return 'W'; + } + + // test counter clockwise + else if (ccCount == 32 && encDir == 0) + { + encDir = 'C'; + return 'C'; + } + + // test encoder click + else if (portB == 0x60 && encDir == 0) + { + encDir = 'S'; + ccCount = 32; // delay before reset (remove debounce jitter) + return 'S'; + } + return 0; +} \ No newline at end of file diff --git a/firmware/generic/src/drivers/encoder.h b/firmware/generic/src/drivers/encoder.h new file mode 100644 index 0000000..3315117 --- /dev/null +++ b/firmware/generic/src/drivers/encoder.h @@ -0,0 +1,19 @@ +#ifndef __encoder_h +#define __encoder_h +extern "C" +{ +#include +} + +class encoder +{ +public: + encoder(){}; + char get(); + +private: + char encDir; // encoder direction + uint8_t cwCount; // clockwise encoder count + uint8_t ccCount; // counter clockwise encoder count +}; +#endif \ No newline at end of file diff --git a/firmware/generic/src/drivers/led.h b/firmware/generic/src/drivers/led.h new file mode 100644 index 0000000..e313dd2 --- /dev/null +++ b/firmware/generic/src/drivers/led.h @@ -0,0 +1,73 @@ +#ifndef __led_h +#define __led_h +extern "C" { + #include +} +class led { +public: + led() {}; + void begin() { + /* enable the led clock */ + rcu_periph_clock_enable(RCU_GPIOC); + rcu_periph_clock_enable(RCU_GPIOA); + + /* configure led GPIO port */ + gpio_init(GPIOC, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13); + gpio_init(GPIOA, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_1); + gpio_init(GPIOA, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2); + + GPIO_BOP(GPIOC) = GPIO_PIN_13; + GPIO_BOP(GPIOA) = GPIO_PIN_1; + GPIO_BOP(GPIOA) = GPIO_PIN_2; + } + /*! + Turn on the red part of the RGB LED + by clearing PC13 + */ + void red_on() + { + GPIO_BC(GPIOC) = GPIO_PIN_13; + } + /*! + Turn off the red part of the RGB LED + by setting PC13 + */ + void red_off() + { + GPIO_BOP(GPIOC) = GPIO_PIN_13; + } + /*! + Turn on the blue part of the RGB LED + by clearing PA1 + */ + void green_on() + { + GPIO_BC(GPIOA) = GPIO_PIN_1; + } + /*! + Turn off the green part of the RGB LED + by setting PA1 + */ + void green_off() + { + GPIO_BOP(GPIOA) = GPIO_PIN_1; + } + /*! + Turn on the blue part of the RGB LED + by clearing PA2 + */ + void blue_on() + { + GPIO_BC(GPIOA) = GPIO_PIN_2; + } + /*! + Turn off the blue part of the RGB LED + by setting PA2 + */ + void blue_off() + { + GPIO_BOP(GPIOA) = GPIO_PIN_2; + } + +}; +#endif \ No newline at end of file diff --git a/firmware/generic/src/drivers/scope.cpp b/firmware/generic/src/drivers/scope.cpp new file mode 100644 index 0000000..f49ad27 --- /dev/null +++ b/firmware/generic/src/drivers/scope.cpp @@ -0,0 +1,46 @@ +#include "scope.h" +#include "drivers\display.h" +scope::scope(uint16_t Colour) +{ + this->Colour = Colour; + offset = 76; // add space above scope + scale = 1; + BufferInputIndex = 0; + for (uint32_t i = 0; i < SCOPE_BUFFER_SIZE; i++) + { + Buffer[i] = 0; + } +} + +void scope::draw(display &dsp) +{ + uint16_t YLocn; + for (uint32_t i = 0; i < SCOPE_BUFFER_SIZE; i++) + { + YLocn = /*dsp.getHeight()/2 +*/ offset + (Buffer[i] * scale); + dsp.putPixel(i, YLocn, Colour); + } +} + +void scope::draw1(display &dsp, uint16_t pos) +{ + uint16_t YLocn; + YLocn = /*dsp.getHeight()/2 +*/ offset + (Buffer[pos] * scale); + dsp.putPixel(pos, YLocn + 1, Colour); +} + +uint16_t scope::read(uint16_t pos) +{ + return (Buffer[pos]); +} + +void scope::write(uint16_t pos, uint16_t value) +{ + Buffer[pos] = value; +} + +void scope::insert(uint16_t value) +{ + Buffer[BufferInputIndex] = value; + BufferInputIndex = (BufferInputIndex + 1) % SCOPE_BUFFER_SIZE; +} diff --git a/firmware/generic/src/drivers/scope.h b/firmware/generic/src/drivers/scope.h new file mode 100644 index 0000000..74dd7ed --- /dev/null +++ b/firmware/generic/src/drivers/scope.h @@ -0,0 +1,41 @@ +#ifndef __SCOPE_H +#define __SCOPE_H +#include +#include "drivers\display.h" +// Drawing of scope data: +/* Two basic approaches: + 1: Don't remember any scope data and simply overwrite the + screen each time you want to draw. + 2: Remember the scope data and "undraw" before draw. + This also allows dot-joining +Third possible approach is to have a screen buffer and do DMA +A bit concerned that this might cause interrupt jitter though. +Whatever the mechanism it would be nice to avoid too much flicker +on the display. +*/ +// In order to avoid dynamic memory allocation for scope data +// a fixed size array has to be declared here. +#if SCREEN_WIDTH > SCREEN_HEIGHT +#define SCOPE_BUFFER_SIZE SCREEN_WIDTH +#else +#define SCOPE_BUFFER_SIZE SCREEN_HEIGHT +#endif + +class scope +{ +public: + scope(uint16_t Colour); + void draw(display &dsp); + void draw1(display &dsp, uint16_t pos); + uint16_t read(uint16_t pos); + void write(uint16_t pos, uint16_t value); + void insert(uint16_t value); + +private: + uint32_t offset; + uint32_t scale; + uint16_t Buffer[SCOPE_BUFFER_SIZE]; + uint32_t BufferInputIndex; + uint16_t Colour; +}; +#endif \ No newline at end of file diff --git a/firmware/generic/src/drivers/spi.cpp b/firmware/generic/src/drivers/spi.cpp new file mode 100644 index 0000000..8ad5f08 --- /dev/null +++ b/firmware/generic/src/drivers/spi.cpp @@ -0,0 +1,38 @@ +extern "C" { +#include +#include +} +#include "spi.h" +// SPI1 is wired to the LCD display on the eurorack module. +void spi::begin() +{ + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_SPI1); + spi_parameter_struct spi_init_struct; + spi_struct_para_init(&spi_init_struct); + /* SPI0 configuration 8-bit full duplex, software control of slave select, master more*/ + spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_init_struct.device_mode = SPI_MASTER; + spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT; + spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; + spi_init_struct.nss = SPI_NSS_SOFT; + spi_init_struct.prescale = SPI_PSC_8; + spi_init_struct.endian = SPI_ENDIAN_MSB; + spi_init(SPI1, &spi_init_struct); + spi_crc_off(SPI1); + spi_enable(SPI1); +} +uint8_t spi::writeData8(uint8_t data) +{ + spi_i2s_data_transmit(SPI1,data); + while(spi_i2s_flag_get(SPI1,SPI_FLAG_TRANS)); // wait for transmit to complete + return 0; +} +uint16_t spi::writeData16(uint16_t data) +{ + spi_i2s_data_transmit(SPI1,data>>8); + while(spi_i2s_flag_get(SPI1,SPI_FLAG_TRANS)); // wait for transmit to complete + spi_i2s_data_transmit(SPI1,data & 0xff); + while(spi_i2s_flag_get(SPI1,SPI_FLAG_TRANS)); // wait for transmit to complete + return 0; +} \ No newline at end of file diff --git a/firmware/generic/src/drivers/spi.h b/firmware/generic/src/drivers/spi.h new file mode 100644 index 0000000..6524fa3 --- /dev/null +++ b/firmware/generic/src/drivers/spi.h @@ -0,0 +1,11 @@ +#ifndef __spi_h +#define __spi_h +class spi { + +public: + spi() {}; + void begin(); + uint8_t writeData8(uint8_t data); + uint16_t writeData16(uint16_t data); +}; +#endif \ No newline at end of file diff --git a/firmware/generic/src/drivers/timer.cpp b/firmware/generic/src/drivers/timer.cpp new file mode 100644 index 0000000..6e563de --- /dev/null +++ b/firmware/generic/src/drivers/timer.cpp @@ -0,0 +1,97 @@ +extern "C" +{ +#include "gd32vf103.h" +} +#include "timer.h" +static timer *ptimer = 0; + +void timer::begin() +{ + ptimer = this; + /* ---------------------------------------------------------------------------- + TIMER6 Configuration: + Want the timer to run with an interrupt frequency of ~44.1kHz. + SystemCoreClock = 108MHz + TIMER6CLK = SystemCoreClock/2431 = 44.4KHz. + TIMER6 configuration is timing mode, and the timing is 44400/1 = 44400 + ---------------------------------------------------------------------------- */ + // timer_oc_parameter_struct timer_ocinitpara; + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER6); + + timer_deinit(TIMER6); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + /* TIMER6 configuration */ + timer_initpara.prescaler = 2430; // 108MHz /2431 => 44.4 kHz + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 1; // divide by one + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_init(TIMER6, &timer_initpara); + timer_interrupt_enable(TIMER6, TIMER_INT_UP); + timer_enable(TIMER6); + eclic_global_interrupt_enable(); + eclic_enable_interrupt(TIMER6_IRQn); + // zero out the callback array + for (int i = 0; i < MAX_CB; i++) + { + cb[i] = 0; + } +} + +int timer::attach(fptr Callback) +{ + for (int i = 0; i < MAX_CB; i++) + { + if (cb[i] == 0) + { + // found a free slot + cb[i] = Callback; + return 0; + } + } + return -1; // no room left +} + +int timer::detach(fptr Callback) +{ + for (int i = 0; i < MAX_CB; i++) + { + if (cb[i] == Callback) + { + // found the slot so empty it + cb[i] = 0; + return 0; + } + } + return -1; // didn't find that one +} + +void timer::OnInterrupt(void) +{ + for (int i = 0; i < MAX_CB; i++) + { // look through callback array and call the non-zero entries. + if (cb[i] != 0) + { + cb[i](); + } + } +} + +extern "C" +{ + void TIMER6_IRQHandler(void) + { + if (timer_interrupt_flag_get(TIMER6, TIMER_INT_UP) == SET) + { + /* clear Timer 6 update interrupt bit */ + timer_interrupt_flag_clear(TIMER6, TIMER_INT_UP); + } + if (ptimer) + { + ptimer->OnInterrupt(); + } + } +} diff --git a/firmware/generic/src/drivers/timer.h b/firmware/generic/src/drivers/timer.h new file mode 100644 index 0000000..47c4b56 --- /dev/null +++ b/firmware/generic/src/drivers/timer.h @@ -0,0 +1,16 @@ +#include +#define MAX_CB 10 +typedef void (*fptr)(void); +class timer +{ +public: + + timer() {}; + void begin(); + int attach(fptr Callback); + int detach(fptr Callback); + void OnInterrupt(void); + //friend void TIMER6_IRQHandler(void); +private: + fptr cb[MAX_CB]; +}; \ No newline at end of file diff --git a/firmware/generic/src/drivers/usbfs/drv_usb_core.c b/firmware/generic/src/drivers/usbfs/drv_usb_core.c new file mode 100644 index 0000000..b4cff05 --- /dev/null +++ b/firmware/generic/src/drivers/usbfs/drv_usb_core.c @@ -0,0 +1,319 @@ +/*! + \file drv_usb_core.c + \brief USB core driver which can operate in host and device mode + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_core.h" +#include "drv_usb_hw.h" + +/*! + \brief config USB core to soft reset + \param[in] usb_regs: USB core registers + \param[out] none + \retval none +*/ +static void usb_core_reset (usb_core_regs *usb_regs) +{ + /* enable core soft reset */ + usb_regs->gr->GRSTCTL |= GRSTCTL_CSRST; + + /* wait for the core to be soft reset */ + while (usb_regs->gr->GRSTCTL & GRSTCTL_CSRST); + + /* wait for addtional 3 PHY clocks */ + usb_udelay(3); +} + +/*! + \brief config USB core basic + \param[in] usb_basic: pointer to usb capabilities + \param[in] usb_regs: USB core registers + \param[in] usb_core: USB core + \param[out] none + \retval operation status +*/ +usb_status usb_basic_init (usb_core_basic *usb_basic, + usb_core_regs *usb_regs, + usb_core_enum usb_core) +{ + uint32_t i = 0, reg_base = 0; + + /* config USB default transfer mode as FIFO mode */ + usb_basic->transfer_mode = USB_USE_FIFO; + + /* USB default speed is full-speed */ + usb_basic->core_speed = USB_SPEED_FULL; + + usb_basic->core_enum = usb_core; + + switch (usb_core) { + case USB_CORE_ENUM_HS: + reg_base = USBHS_REG_BASE; + + /* set the host channel numbers */ + usb_basic->num_pipe = USBHS_MAX_CHANNEL_COUNT; + + /* set the device endpoint numbers */ + usb_basic->num_ep = USBHS_MAX_EP_COUNT; + +#ifdef USB_ULPI_PHY_ENABLED + usb_basic->phy_itf = USB_ULPI_PHY; +#else + usb_basic->phy_itf = USB_EMBEDDED_PHY; +#endif /* USB_ULPI_PHY_ENABLED */ + +#ifdef USB_HS_INTERNAL_DMA_ENABLED + bp->transfer_mode = USB_USE_DMA; +#endif /* USB_HS_INTERNAL_DMA_ENABLED */ + break; + + case USB_CORE_ENUM_FS: + reg_base = USBFS_REG_BASE; + + /* set the host channel numbers */ + usb_basic->num_pipe = USBFS_MAX_CHANNEL_COUNT; + + /* set the device endpoint numbers */ + usb_basic->num_ep = USBFS_MAX_EP_COUNT; + + /* USBFS core use embedded physical layer */ + usb_basic->phy_itf = USB_EMBEDDED_PHY; + break; + + default: + return USB_FAIL; + } + + usb_basic->sof_enable = USB_SOF_OUTPUT; + usb_basic->low_power = USB_LOW_POWER; + + /* assign main registers address */ + *usb_regs = (usb_core_regs) { + .gr = (usb_gr*) (reg_base + USB_REG_OFFSET_CORE), + .hr = (usb_hr*) (reg_base + USB_REG_OFFSET_HOST), + .dr = (usb_dr*) (reg_base + USB_REG_OFFSET_DEV), + + .HPCS = (uint32_t*) (reg_base + USB_REG_OFFSET_PORT), + .PWRCLKCTL = (uint32_t*) (reg_base + USB_REG_OFFSET_PWRCLKCTL) + }; + + /* assign device endpoint registers address */ + for (i = 0; i < usb_basic->num_ep; i++) { + usb_regs->er_in[i] = (usb_erin *) \ + (reg_base + USB_REG_OFFSET_EP_IN + (i * USB_REG_OFFSET_EP)); + + usb_regs->er_out[i] = (usb_erout *)\ + (reg_base + USB_REG_OFFSET_EP_OUT + (i * USB_REG_OFFSET_EP)); + } + + /* assign host pipe registers address */ + for (i = 0; i < usb_basic->num_pipe; i++) { + usb_regs->pr[i] = (usb_pr *) \ + (reg_base + USB_REG_OFFSET_CH_INOUT + (i * USB_REG_OFFSET_CH)); + + usb_regs->DFIFO[i] = (uint32_t *) \ + (reg_base + USB_DATA_FIFO_OFFSET + (i * USB_DATA_FIFO_SIZE)); + } + + return USB_OK; +} + +/*! + \brief initializes the USB controller registers and + prepares the core device mode or host mode operation + \param[in] bp: usb capabilities + \param[in] core_regs: usb core registers + \param[out] none + \retval operation status +*/ +usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs) +{ + uint32_t reg_value = usb_regs->gr->GCCFG; + + /* disable USB global interrupt */ + usb_regs->gr->GAHBCS &= ~GAHBCS_GINTEN; + + if (USB_ULPI_PHY == usb_basic.phy_itf) { + reg_value &= ~GCCFG_PWRON; + + if (usb_basic.sof_enable) { + reg_value |= GCCFG_SOFOEN; + } + + usb_regs->gr->GCCFG = GCCFG_SOFOEN; + + /* init the ULPI interface */ + usb_regs->gr->GUSBCS &= ~(GUSBCS_EMBPHY | GUSBCS_ULPIEOI); + +#ifdef USBHS_EXTERNAL_VBUS_ENABLED + /* use external VBUS driver */ + usb_regs->gr->GUSBCS |= GUSBCS_ULPIEVD; +#else + /* use internal VBUS driver */ + usb_regs->gr->GUSBCS &= ~GUSBCS_ULPIEVD; +#endif + + /* soft reset the core */ + usb_core_reset (usb_regs); + } else { + usb_regs->gr->GUSBCS |= GUSBCS_EMBPHY; + + /* soft reset the core */ + usb_core_reset (usb_regs); + + /* active the transceiver and enable vbus sensing */ + reg_value = GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; + +#ifndef VBUS_SENSING_ENABLED + reg_value |= GCCFG_VBUSIG; +#endif /* VBUS_SENSING_ENABLED */ + + /* enable SOF output */ + if (usb_basic.sof_enable) { + reg_value |= GCCFG_SOFOEN; + } + + usb_regs->gr->GCCFG = reg_value; + + usb_mdelay(20); + } + + if (USB_USE_DMA == usb_basic.transfer_mode) { + usb_regs->gr->GAHBCS |= GAHBCS_DMAEN; + usb_regs->gr->GAHBCS &= ~GAHBCS_BURST; + usb_regs->gr->GAHBCS |= DMA_INCR8; + } + +#ifdef USE_OTG_MODE + + /* enable USB OTG features */ + usb_regs->gr->GUSBCS |= GUSBCS_HNPCAP | GUSBCS_SRPCAP; + + /* enable the USB wakeup and suspend interrupts */ + usb_regs->gr->GINTF = 0xBFFFFFFFU; + + usb_regs->gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE | \ + GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE; + +#endif /* USE_OTG_MODE */ + + return USB_OK; +} + +/*! + \brief write a packet into the Tx FIFO associated with the endpoint + \param[in] core_regs: usb core registers + \param[in] src_buf: pointer to source buffer + \param[in] fifo_num: FIFO number which is in (0..3) + \param[in] byte_count: packet byte count + \param[out] none + \retval operation status +*/ +usb_status usb_txfifo_write (usb_core_regs *usb_regs, + uint8_t *src_buf, + uint8_t fifo_num, + uint16_t byte_count) +{ + uint32_t word_count = (byte_count + 3U) / 4U; + + __IO uint32_t *fifo = usb_regs->DFIFO[fifo_num]; + + while (word_count-- > 0) { + *fifo = *((__packed uint32_t *)src_buf); + + src_buf += 4U; + } + + return USB_OK; +} + +/*! + \brief read a packet from the Rx FIFO associated with the endpoint + \param[in] core_regs: usb core registers + \param[in] dest_buf: pointer to destination buffer + \param[in] byte_count: packet byte count + \param[out] none + \retval void type pointer +*/ +void *usb_rxfifo_read (usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count) +{ + uint32_t word_count = (byte_count + 3U) / 4U; + + __IO uint32_t *fifo = usb_regs->DFIFO[0]; + + while (word_count-- > 0) { + *(__packed uint32_t *)dest_buf = *fifo; + + dest_buf += 4U; + } + + return ((void *)dest_buf); +} + +/*! + \brief flush a Tx FIFO or all Tx FIFOs + \param[in] core_regs: pointer to usb core registers + \param[in] fifo_num: FIFO number which is in (0..3) + \param[out] none + \retval operation status +*/ +usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num) +{ + usb_regs->gr->GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF; + + /* wait for Tx FIFO flush bit is set */ + while (usb_regs->gr->GRSTCTL & GRSTCTL_TXFF); + + /* wait for 3 PHY clocks*/ + usb_udelay(3); + + return USB_OK; +} + +/*! + \brief flush the entire Rx FIFO + \param[in] core_regs: pointer to usb core registers + \param[out] none + \retval operation status +*/ +usb_status usb_rxfifo_flush (usb_core_regs *usb_regs) +{ + usb_regs->gr->GRSTCTL = GRSTCTL_RXFF; + + /* wait for Rx FIFO flush bit is set */ + while (usb_regs->gr->GRSTCTL & GRSTCTL_RXFF); + + /* wait for 3 PHY clocks */ + usb_udelay(3); + + return USB_OK; +} diff --git a/firmware/generic/src/drivers/usbfs/drv_usb_core.h b/firmware/generic/src/drivers/usbfs/drv_usb_core.h new file mode 100644 index 0000000..70563ec --- /dev/null +++ b/firmware/generic/src/drivers/usbfs/drv_usb_core.h @@ -0,0 +1,117 @@ +/*! + \file drv_usb_core.h + \brief USB core low level driver header file + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_CORE_H +#define __DRV_USB_CORE_H + +#include "drv_usb_regs.h" +#include "usb_ch9_std.h" + +#define USB_FS_EP0_MAX_LEN 64U /* maximum packet size of EndPoint0 */ + +#define HC_MAX_PACKET_COUNT 140U /* maximum packet count */ + +#define EP_ID(x) ((uint8_t)((x) & 0x7FU)) /* endpoint number */ +#define EP_DIR(x) ((uint8_t)((x) >> 7)) /* endpoint direction */ + +enum _usb_eptype { + USB_EPTYPE_CTRL = 0U, /*!< control endpoint type */ + USB_EPTYPE_ISOC = 1U, /*!< isochronous endpoint type */ + USB_EPTYPE_BULK = 2U, /*!< bulk endpoint type */ + USB_EPTYPE_INTR = 3U, /*!< interrupt endpoint type */ + USB_EPTYPE_MASK = 3U, /*!< endpoint type mask */ +}; + +typedef enum +{ + USB_OTG_OK = 0, /*!< USB OTG status OK*/ + USB_OTG_FAIL /*!< USB OTG status fail*/ +} usb_otg_status; + +typedef enum +{ + USB_OK = 0, /*!< USB status OK*/ + USB_FAIL /*!< USB status fail*/ +} usb_status; + +typedef enum +{ + USB_USE_FIFO, /*!< USB use FIFO transfer mode */ + USB_USE_DMA /*!< USB use DMA transfer mode */ +} usb_transfer_mode; + +typedef struct +{ + uint8_t core_enum; /*!< USB core type */ + uint8_t core_speed; /*!< USB core speed */ + uint8_t num_pipe; /*!< USB host channel numbers */ + uint8_t num_ep; /*!< USB device endpoint numbers */ + uint8_t transfer_mode; /*!< USB transfer mode */ + uint8_t phy_itf; /*!< USB core PHY interface */ + uint8_t sof_enable; /*!< USB SOF output */ + uint8_t low_power; /*!< USB low power */ +} usb_core_basic; + +/* function declarations */ + +/* config core capabilities */ +usb_status usb_basic_init (usb_core_basic *usb_basic, + usb_core_regs *usb_regs, + usb_core_enum usb_core); + +/*initializes the USB controller registers and prepares the core device mode or host mode operation*/ +usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs); + +/* read a packet from the Rx FIFO associated with the endpoint */ +void *usb_rxfifo_read (usb_core_regs *core_regs, uint8_t *dest_buf, uint16_t byte_count); + +/* write a packet into the Tx FIFO associated with the endpoint */ +usb_status usb_txfifo_write (usb_core_regs *usb_regs, + uint8_t *src_buf, + uint8_t fifo_num, + uint16_t byte_count); + +/* flush a Tx FIFO or all Tx FIFOs */ +usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num); + +/* flush the entire Rx FIFO */ +usb_status usb_rxfifo_flush (usb_core_regs *usb_regs); + +/* get the global interrupts */ +static inline uint32_t usb_coreintr_get(usb_core_regs *usb_regs) +{ + return usb_regs->gr->GINTEN & usb_regs->gr->GINTF; +} + +#endif /* __DRV_USB_CORE_H */ diff --git a/firmware/generic/src/drivers/usbfs/drv_usb_dev.c b/firmware/generic/src/drivers/usbfs/drv_usb_dev.c new file mode 100644 index 0000000..5988ec5 --- /dev/null +++ b/firmware/generic/src/drivers/usbfs/drv_usb_dev.c @@ -0,0 +1,749 @@ +/*! + \file drv_usb_dev.c + \brief USB device mode low level driver + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +/* endpoint 0 max packet length */ +static const uint8_t EP0_MAXLEN[4] = { + [DSTAT_EM_HS_PHY_30MHZ_60MHZ] = EP0MPL_64, + [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = EP0MPL_64, + [DSTAT_EM_FS_PHY_48MHZ] = EP0MPL_64, + [DSTAT_EM_LS_PHY_6MHZ] = EP0MPL_8 +}; + +#ifdef USB_FS_CORE + +/* USB endpoint Tx FIFO size */ +static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] = +{ + (uint16_t)TX0_FIFO_FS_SIZE, + (uint16_t)TX1_FIFO_FS_SIZE, + (uint16_t)TX2_FIFO_FS_SIZE, + (uint16_t)TX3_FIFO_FS_SIZE +}; + +#elif defined(USB_HS_CORE) + +uint16_t USBHS_TX_FIFO_SIZE[USBHS_MAX_EP_COUNT] = +{ + (uint16_t)TX0_FIFO_HS_SIZE, + (uint16_t)TX1_FIFO_HS_SIZE, + (uint16_t)TX2_FIFO_HS_SIZE, + (uint16_t)TX3_FIFO_HS_SIZE, + (uint16_t)TX4_FIFO_HS_SIZE, + (uint16_t)TX5_FIFO_HS_SIZE +}; + +#endif /* USBFS_CORE */ + +/*! + \brief initialize USB core registers for device mode + \param[in] udev: pointer to usb device + \param[out] none + \retval operation status +*/ +usb_status usb_devcore_init (usb_core_driver *udev) +{ + uint32_t i, ram_addr = 0; + + /* force to peripheral mode */ + udev->regs.gr->GUSBCS &= ~(GUSBCS_FDM | GUSBCS_FHM); + udev->regs.gr->GUSBCS |= GUSBCS_FDM; + // udev->regs.gr->GUSBCS &= ~(GUSBCS_FHM); + + /* restart the Phy Clock (maybe don't need to...) */ + *udev->regs.PWRCLKCTL = 0U; + + /* config periodic frame interval to default value */ + udev->regs.dr->DCFG &= ~DCFG_EOPFT; + udev->regs.dr->DCFG |= FRAME_INTERVAL_80; + + udev->regs.dr->DCFG &= ~DCFG_DS; + +#ifdef USB_FS_CORE + if (udev->bp.core_enum == USB_CORE_ENUM_FS) { + /* set full-speed PHY */ + udev->regs.dr->DCFG |= USB_SPEED_INP_FULL; + + /* set Rx FIFO size */ + udev->regs.gr->GRFLEN = RX_FIFO_FS_SIZE; + + /* set endpoint 0 Tx FIFO length and RAM address */ + udev->regs.gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)TX0_FIFO_FS_SIZE << 16) | \ + ((uint32_t)RX_FIFO_FS_SIZE); + + ram_addr = RX_FIFO_FS_SIZE; + + /* set endpoint 1 to 3's Tx FIFO length and RAM address */ + for (i = 1; i < USBFS_MAX_EP_COUNT; i++) { + ram_addr += USBFS_TX_FIFO_SIZE[i - 1]; + + udev->regs.gr->DIEPTFLEN[i - 1] = ((uint32_t)USBFS_TX_FIFO_SIZE[i] << 16U) | \ + ram_addr; + } + } +#endif + +#ifdef USB_HS_CORE + if (udev->bp.core == USB_CORE_HS) { + if (udev->bp.core_phy == USB_ULPI_PHY) { + udev->regs.dr->DCFG |= USB_SPEED_EXP_HIGH; + } else {/* set High speed phy in Full speed mode */ + udev->regs.dr->DCFG |= USB_SPEED_EXP_FULL; + } + + /* Set Rx FIFO size */ + udev->regs.gr->GRFLEN &= ~GRFLEN_RXFD; + udev->regs.gr->GRFLEN |= RX_FIFO_HS_SIZE; + + /* Set endpoint 0 Tx FIFO length and RAM address */ + udev->regs.gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)TX0_FIFO_HS_SIZE << 16) | \ + RX_FIFO_HS_SIZE; + + ram_addr = RX_FIFO_HS_SIZE; + + /* Set endpoint 1 to 3's Tx FIFO length and RAM address */ + for (i = 1; i < USBHS_MAX_EP_COUNT; i++) { + ram_addr += USBHS_TX_FIFO_SIZE[i - 1]; + + udev->regs.gr->DIEPTFLEN[i - 1] = ((uint32_t)USBHS_TX_FIFO_SIZE[i] << 16) | \ + ram_addr; + } + } +#endif + + /* make sure all FIFOs are flushed */ + + /* flush all Tx FIFOs */ + usb_txfifo_flush (&udev->regs, 0x10); + + /* flush entire Rx FIFO */ + usb_rxfifo_flush (&udev->regs); + + /* clear all pending device interrupts */ + udev->regs.dr->DIEPINTEN = 0U; + udev->regs.dr->DOEPINTEN = 0U; + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + udev->regs.dr->DAEPINTEN = 0U; + + /* configure all IN/OUT endpoints */ + for (i = 0; i < udev->bp.num_ep; i++) { + if (udev->regs.er_in[i]->DIEPCTL & DEPCTL_EPEN) { + udev->regs.er_in[i]->DIEPCTL |= DEPCTL_EPD | DEPCTL_SNAK; + } else { + udev->regs.er_in[i]->DIEPCTL = 0U; + } + + /* set IN endpoint transfer length to 0 */ + udev->regs.er_in[i]->DIEPLEN = 0U; + + /* clear all pending IN endpoint interrupts */ + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + + if (udev->regs.er_out[i]->DOEPCTL & DEPCTL_EPEN) { + udev->regs.er_out[i]->DOEPCTL |= DEPCTL_EPD | DEPCTL_SNAK; + } else { + udev->regs.er_out[i]->DOEPCTL = 0U; + } + + /* set OUT endpoint transfer length to 0 */ + udev->regs.er_out[i]->DOEPLEN = 0U; + + /* clear all pending OUT endpoint interrupts */ + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + usb_devint_enable (udev); + + return USB_OK; +} + +/*! + \brief enable the USB device mode interrupts + \param[in] udev: pointer to usb device + \param[out] none + \retval operation status +*/ +usb_status usb_devint_enable (usb_core_driver *udev) +{ + /* clear any pending USB OTG interrupts */ + udev->regs.gr->GOTGINTF = 0xFFFFFFFFU; + + /* clear any pending interrupts */ + udev->regs.gr->GINTF = 0xBFFFFFFFU; + + /* enable the USB wakeup and suspend interrupts */ + udev->regs.gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; + + /* enable device_mode-related interrupts */ + if (USB_USE_FIFO == udev->bp.transfer_mode) { + udev->regs.gr->GINTEN |= GINTEN_RXFNEIE; + } + udev->regs.gr->GINTEN |= GINTEN_RSTIE | GINTEN_ENUMFIE | GINTEN_IEPIE |\ + GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_MFIE; + +#ifdef VBUS_SENSING_ENABLED + udev->regs.gr->GINTEN |= GINTEN_SESIE | GINTEN_OTGIE; +#endif /* VBUS_SENSING_ENABLED */ + + /* enable USB global interrupt */ + udev->regs.gr->GAHBCS |= GAHBCS_GINTEN; + + return USB_OK; +} + +/*! + \brief config the USB device to be disconnected + \param[in] udev: pointer to usb device + \param[out] none + \retval operation status +*/ +void usb_dev_disconnect (usb_core_driver *udev) +{ + udev->regs.dr->DCTL |= DCTL_SD; +} + +/*! + \brief config the USB device to be connected + \param[in] udev: pointer to usb device + \param[out] none + \retval operation status +*/ +void usb_dev_connect (usb_core_driver *udev) +{ + udev->regs.dr->DCTL &= ~DCTL_SD; +} + +/*! + \brief set the USB device address + \param[in] udev: pointer to usb device + \param[in] dev_addr: device address for setting + \param[out] none + \retval operation status +*/ +void usb_devaddr_set (usb_core_driver *udev, uint8_t dev_addr) +{ + udev->regs.dr->DCFG &= ~DCFG_DAR; + udev->regs.dr->DCFG |= dev_addr << 4; +} + +/*! + \brief active the usb transaction + \param[in] udev: pointer to usb device + \param[in] transc: the usb transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + __IO uint32_t epinten = 0U; + + /* get the endpoint number */ + uint8_t ep_num = transc->ep_addr.num; + + /* enable endpoint interrupt number */ + if (transc->ep_addr.dir) { + reg_addr = &udev->regs.er_in[ep_num]->DIEPCTL; + + epinten = 1 << ep_num; + } else { + reg_addr = &udev->regs.er_out[ep_num]->DOEPCTL; + + epinten = 1 << (16 + ep_num); + } + + /* if the endpoint is not active, need change the endpoint control register */ + if (!(*reg_addr & DEPCTL_EPACT)) { + *reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM); + + /* set endpoint maximum packet length */ + if (0U == ep_num) { + *reg_addr |= EP0_MAXLEN[udev->regs.dr->DSTAT & DSTAT_ES]; + } else { + *reg_addr |= transc->max_len; + } + + /* activate endpoint */ + *reg_addr |= (transc->ep_type << 18) | (ep_num << 22) | DEPCTL_SD0PID | DEPCTL_EPACT; + } + +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED + if ((ep_num == 1) && (udev->bp.core == USB_HS_CORE_ID)) { + udev->regs.dr->DEP1INTEN |= epinten; + } + else +#endif + { + /* enable the interrupts for this endpoint */ + udev->regs.dr->DAEPINTEN |= epinten; + } + + return USB_OK; +} + +/*! + \brief deactive the usb transaction + \param[in] udev: pointer to usb device + \param[in] transc: the usb transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_deactivate(usb_core_driver *udev, usb_transc *transc) +{ + uint32_t epinten = 0U; + + uint8_t ep_num = transc->ep_addr.num; + + /* disable endpoint interrupt number */ + if (transc->ep_addr.dir) { + epinten = 1 << ep_num; + + udev->regs.er_in[ep_num]->DIEPCTL &= ~DEPCTL_EPACT; + } else { + epinten = 1 << (ep_num + 16); + + udev->regs.er_out[ep_num]->DOEPCTL &= ~DEPCTL_EPACT; + } + +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED + if ((ep_num == 1) && (udev->bp.core == USB_CORE_HS)) { + udev->regs.dr->DEP1INTEN &= ~epinten; + } + else +#endif + { + /* disable the interrupts for this endpoint */ + udev->regs.dr->DAEPINTEN &= ~epinten; + } + + return USB_OK; +} + +/*! + \brief configure usb transaction to start IN transfer + \param[in] udev: pointer to usb device + \param[in] transc: the usb IN transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc) +{ + usb_status status = USB_OK; + + uint8_t ep_num = transc->ep_addr.num; + + __IO uint32_t epctl = udev->regs.er_in[ep_num]->DIEPCTL; + __IO uint32_t eplen = udev->regs.er_in[ep_num]->DIEPLEN; + + eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT); + + /* zero length packet or endpoint 0 */ + if (0U == transc->xfer_len) { + /* set transfer packet count to 1 */ + eplen |= 1 << 19; + } else { + /* set transfer packet count */ + if (0U == ep_num) { + transc->xfer_len = USB_MIN(transc->xfer_len, transc->max_len); + + eplen |= 1 << 19; + } else { + eplen |= ((transc->xfer_len - 1 + transc->max_len) / transc->max_len) << 19; + } + + /* set endpoint transfer length */ + eplen |= transc->xfer_len; + + if (transc->ep_type == USB_EPTYPE_ISOC) { + eplen |= DIEPLEN_MCNT; + } + } + + udev->regs.er_in[ep_num]->DIEPLEN = eplen; + + if (USB_USE_DMA == udev->bp.transfer_mode) { + udev->regs.er_in[ep_num]->DIEPDMAADDR = transc->dma_addr; + } + + if (transc->ep_type == USB_EPTYPE_ISOC) { + if (((udev->regs.dr->DSTAT & DSTAT_FNRSOF) >> 8) & 0x1) { + epctl |= DEPCTL_SD1PID; + } else { + epctl |= DEPCTL_SD0PID; + } + } + + /* enable the endpoint and clear the NAK */ + epctl |= DEPCTL_CNAK | DEPCTL_EPEN; + + udev->regs.er_in[ep_num]->DIEPCTL = epctl; + + if (transc->ep_type != USB_EPTYPE_ISOC) { + /* enable the Tx FIFO empty interrupt for this endpoint */ + if (transc->xfer_len > 0) { + udev->regs.dr->DIEPFEINTEN |= 1 << ep_num; + } + } else { + usb_txfifo_write (&udev->regs, transc->xfer_buf, ep_num, transc->xfer_len); + } + + return status; +} + +/*! + \brief configure usb transaction to start OUT transfer + \param[in] udev: pointer to usb device + \param[in] transc: the usb OUT transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc) +{ + usb_status status = USB_OK; + + uint8_t ep_num = transc->ep_addr.num; + + uint32_t epctl = udev->regs.er_out[ep_num]->DOEPCTL; + uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN; + + eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT); + + /* zero length packet or endpoint 0 */ + if ((0U == transc->xfer_len) || (0U == ep_num)) { + /* set the transfer length to max packet size */ + eplen |= transc->max_len; + + /* set the transfer packet count to 1 */ + eplen |= 1U << 19; + } else { + /* configure the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + uint32_t packet_count = (transc->xfer_len + transc->max_len - 1) / transc->max_len; + + eplen |= packet_count << 19; + eplen |= packet_count * transc->max_len; + } + + udev->regs.er_out[ep_num]->DOEPLEN = eplen; + + if (USB_USE_DMA == udev->bp.transfer_mode) { + udev->regs.er_out[ep_num]->DOEPDMAADDR = transc->dma_addr; + } + + if (transc->ep_type == USB_EPTYPE_ISOC) { + if (transc->frame_num) { + epctl |= DEPCTL_SD1PID; + } else { + epctl |= DEPCTL_SD0PID; + } + } + + /* enable the endpoint and clear the NAK */ + epctl |= DEPCTL_EPEN | DEPCTL_CNAK; + + udev->regs.er_out[ep_num]->DOEPCTL = epctl; + + return status; +} + +/*! + \brief set the usb transaction STALL status + \param[in] udev: pointer to usb device + \param[in] transc: the usb transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_stall (usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + uint8_t ep_num = transc->ep_addr.num; + + if (transc->ep_addr.dir) { + reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL); + + /* set the endpoint disable bit */ + if (*reg_addr & DEPCTL_EPEN) { + *reg_addr |= DEPCTL_EPD; + } + } else { + /* set the endpoint stall bit */ + reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL); + } + + /* set the endpoint stall bit */ + *reg_addr |= DEPCTL_STALL; + + return USB_OK; +} + +/*! + \brief clear the usb transaction STALL status + \param[in] udev: pointer to usb device + \param[in] transc: the usb transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_clrstall(usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + uint8_t ep_num = transc->ep_addr.num; + + if (transc->ep_addr.dir) { + reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL); + } else { + reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL); + } + + /* clear the endpoint stall bits */ + *reg_addr &= ~DEPCTL_STALL; + + /* reset data PID of the periodic endpoints */ + if ((transc->ep_type == USB_EPTYPE_INTR) || (transc->ep_type == USB_EPTYPE_BULK)) { + *reg_addr |= DEPCTL_SD0PID; + } + + return USB_OK; +} + +/*! + \brief read device all OUT endpoint interrupt register + \param[in] udev: pointer to usb device + \param[out] none + \retval none +*/ +uint32_t usb_oepintnum_read (usb_core_driver *udev) +{ + uint32_t value = udev->regs.dr->DAEPINT; + + value &= udev->regs.dr->DAEPINTEN; + + return (value & DAEPINT_OEPITB) >> 16; +} + +/*! + \brief read device OUT endpoint interrupt flag register + \param[in] udev: pointer to usb device + \param[in] ep_num: endpoint number + \param[out] none + \retval none +*/ +uint32_t usb_oepintr_read (usb_core_driver *udev, uint8_t ep_num) +{ + uint32_t value = udev->regs.er_out[ep_num]->DOEPINTF; + + value &= udev->regs.dr->DOEPINTEN; + + return value; +} + +/*! + \brief read device all IN endpoint interrupt register + \param[in] udev: pointer to usb device + \param[out] none + \retval none +*/ +uint32_t usb_iepintnum_read (usb_core_driver *udev) +{ + uint32_t value = udev->regs.dr->DAEPINT; + + value &= udev->regs.dr->DAEPINTEN; + + return value & DAEPINT_IEPITB; +} + + +/*! + \brief read device IN endpoint interrupt flag register + \param[in] udev: pointer to usb device + \param[in] ep_num: endpoint number + \param[out] none + \retval none +*/ +uint32_t usb_iepintr_read (usb_core_driver *udev, uint8_t ep_num) +{ + uint32_t value = 0U, fifoemptymask = 0U, commonintmask = 0U; + + commonintmask = udev->regs.dr->DIEPINTEN; + fifoemptymask = udev->regs.dr->DIEPFEINTEN; + + /* check FIFO empty interrupt enable bit */ + commonintmask |= ((fifoemptymask >> ep_num) & 0x1U) << 7; + + value = udev->regs.er_in[ep_num]->DIEPINTF & commonintmask; + + return value; +} + +/*! + \brief configures OUT endpoint 0 to receive SETUP packets + \param[in] udev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_ctlep_startout (usb_core_driver *udev) +{ + /* set OUT endpoint 0 receive length to 24 bytes, 1 packet and 3 setup packets */ + udev->regs.er_out[0]->DOEPLEN = DOEP0_TLEN(8U * 3U) | DOEP0_PCNT(1U) | DOEP0_STPCNT(3U); + + if (USB_USE_DMA == udev->bp.transfer_mode) { + udev->regs.er_out[0]->DOEPDMAADDR = (uint32_t)&udev->dev.control.req; + + /* endpoint enable */ + udev->regs.er_out[0]->DOEPCTL |= DEPCTL_EPACT | DEPCTL_EPEN; + } +} + +/*! + \brief set remote wakeup signalling + \param[in] udev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_rwkup_set (usb_core_driver *udev) +{ + if (udev->dev.pm.dev_remote_wakeup) { + /* enable remote wakeup signaling */ + udev->regs.dr->DCTL |= DCTL_RWKUP; + } +} + +/*! + \brief reset remote wakeup signalling + \param[in] udev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_rwkup_reset (usb_core_driver *udev) +{ + if (udev->dev.pm.dev_remote_wakeup) { + /* disable remote wakeup signaling */ + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + } +} + +/*! + \brief active remote wakeup signalling + \param[in] udev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_rwkup_active (usb_core_driver *udev) +{ + if (udev->dev.pm.dev_remote_wakeup) { + if (udev->regs.dr->DSTAT & DSTAT_SPST) { + if (udev->bp.low_power) { + /* ungate USB core clock */ + *udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK); + } + + /* active remote wakeup signaling */ + udev->regs.dr->DCTL |= DCTL_RWKUP; + + usb_mdelay(5); + + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + } + } +} + +/*! + \brief active USB core clock + \param[in] udev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_clock_active (usb_core_driver *udev) +{ + if (udev->bp.low_power) { + if (udev->regs.dr->DSTAT & DSTAT_SPST) { + /* un-gate USB Core clock */ + *udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK); + } + } +} + +/*! + \brief usb device suspend + \param[in] udev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_dev_suspend (usb_core_driver *udev) +{ + __IO uint32_t devstat = udev->regs.dr->DSTAT; + + if ((udev->bp.low_power) && (devstat & DSTAT_SPST)) { + /* switch-off the USB clocks */ + *udev->regs.PWRCLKCTL |= PWRCLKCTL_SHCLK; + + /* enter DEEP_SLEEP mode with LDO in low power mode */ + pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); + } +} + +/*! + \brief stop the device and clean up fifos + \param[in] udev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_dev_stop (usb_core_driver *udev) +{ + uint32_t i; + + udev->dev.cur_status = 1; + + /* clear all interrupt flag and enable bits */ + for (i = 0; i < udev->bp.num_ep; i++) { + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + udev->regs.dr->DIEPINTEN = 0U; + udev->regs.dr->DOEPINTEN = 0U; + udev->regs.dr->DAEPINTEN = 0U; + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + + /* flush the FIFO */ + usb_rxfifo_flush (&udev->regs); + usb_txfifo_flush (&udev->regs, 0x10); +} diff --git a/firmware/generic/src/drivers/usbfs/drv_usb_dev.h b/firmware/generic/src/drivers/usbfs/drv_usb_dev.h new file mode 100644 index 0000000..6b85712 --- /dev/null +++ b/firmware/generic/src/drivers/usbfs/drv_usb_dev.h @@ -0,0 +1,217 @@ +/*! + \file drv_usb_dev.h + \brief USB device low level driver header file + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_DEV_H +#define __DRV_USB_DEV_H + +#include "drv_usb_core.h" + +enum usb_ctl_status { + USB_CTL_IDLE = 0U, /*!< USB control transfer idle state */ + USB_CTL_DATA_IN, /*!< USB control transfer data in state */ + USB_CTL_LAST_DATA_IN, /*!< USB control transfer last data in state */ + USB_CTL_DATA_OUT, /*!< USB control transfer data out state */ + USB_CTL_LAST_DATA_OUT, /*!< USB control transfer last data out state */ + USB_CTL_STATUS_IN, /*!< USB control transfer status in state*/ + USB_CTL_STATUS_OUT /*!< USB control transfer status out state */ +}; + +#define EP_IN(x) ((uint8_t)(0x80U | (x))) /*!< device IN endpoint */ +#define EP_OUT(x) ((uint8_t)(x)) /*!< device OUT endpoint */ + +/* USB descriptor */ +typedef struct _usb_desc { + uint8_t *dev_desc; /*!< device descriptor */ + uint8_t *config_desc; /*!< config descriptor */ + uint8_t *bos_desc; /*!< BOS descriptor */ + + void* const *strings; /*!< string descriptor */ +} usb_desc; + +/* USB power management */ +typedef struct _usb_pm { + uint8_t power_mode; /*!< power mode */ + uint8_t power_low; /*!< power low */ + uint8_t dev_remote_wakeup; /*!< remote wakeup */ + uint8_t remote_wakeup_on; /*!< remote wakeup on */ +} usb_pm; + +/* USB control information */ +typedef struct _usb_control { + usb_req req; /*!< USB standard device request */ + + uint8_t ctl_state; /*!< USB control transfer state */ + uint8_t ctl_zlp; /*!< zero lenth package */ +} usb_control; + +typedef struct +{ + struct { + uint8_t num: 4; /*!< the endpoint number.it can be from 0 to 6 */ + uint8_t pad: 3; /*!< padding between number and direction */ + uint8_t dir: 1; /*!< the endpoint direction */ + } ep_addr; + + uint8_t ep_type; /*!< USB endpoint type */ + uint8_t ep_stall; /*!< USB endpoint stall status */ + + uint8_t frame_num; /*!< number of frame */ + uint16_t max_len; /*!< Maximum packet lenth */ + + /* transaction level variables */ + uint8_t *xfer_buf; /*!< transmit buffer */ + uint32_t xfer_len; /*!< transmit buffer length */ + uint32_t xfer_count; /*!< transmit buffer count */ + + uint32_t remain_len; /*!< remain packet lenth */ + + uint32_t dma_addr; /*!< DMA address */ +} usb_transc; + +typedef struct _usb_core_driver usb_dev; + +typedef struct _usb_class_core +{ + uint8_t command; /*!< device class request command */ + uint8_t alter_set; /*!< alternative set */ + + uint8_t (*init) (usb_dev *udev, uint8_t config_index); /*!< initialize handler */ + uint8_t (*deinit) (usb_dev *udev, uint8_t config_index); /*!< de-initialize handler */ + + uint8_t (*req_proc) (usb_dev *udev, usb_req *req); /*!< device request handler */ + + uint8_t (*data_in) (usb_dev *udev, uint8_t ep_num); /*!< device data in handler */ + uint8_t (*data_out) (usb_dev *udev, uint8_t ep_num); /*!< device data out handler */ + + uint8_t (*SOF) (usb_dev *udev); /*!< Start of frame handler */ + + uint8_t (*incomplete_isoc_in) (usb_dev *udev); /*!< Incomplete synchronization IN transfer handler */ + uint8_t (*incomplete_isoc_out) (usb_dev *udev); /*!< Incomplete synchronization OUT transfer handler */ +} usb_class_core; + +typedef struct _usb_perp_dev +{ + uint8_t config; /*!< configuration */ + uint8_t dev_addr; /*!< device address */ + + __IO uint8_t cur_status; /*!< current status */ + __IO uint8_t backup_status; /*!< backup status */ + + usb_transc transc_in[USBFS_MAX_TX_FIFOS]; /*!< endpoint IN transaction */ + usb_transc transc_out[USBFS_MAX_TX_FIFOS]; /*!< endpoint OUT transaction */ + + usb_pm pm; /*!< power management */ + usb_desc desc; /*!< USB descriptors */ + usb_control control; /*!< USB control information */ + + usb_class_core *class_core; /*!< class driver */ +} usb_perp_dev; + +typedef struct _usb_core_driver +{ + usb_core_basic bp; /*!< USB basic parameters */ + usb_core_regs regs; /*!< USB registers */ + usb_perp_dev dev; /*!< USB peripheral device */ +} usb_core_driver; + +/* function declarations */ + +/* initialize USB core registers for device mode */ +usb_status usb_devcore_init (usb_core_driver *udev); + +/* enable the USB device mode interrupts */ +usb_status usb_devint_enable (usb_core_driver *udev); + +/* active the usb transaction */ +usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc); + +/* deactive the usb transaction */ +usb_status usb_transc_deactivate (usb_core_driver *udev, usb_transc *transc); + +/* configure usb transaction to start IN transfer */ +usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc); + +/* configure usb transaction to start OUT transfer */ +usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc); + +/* set the usb transaction STALL status */ +usb_status usb_transc_stall (usb_core_driver *udev, usb_transc *transc); + +/* clear the usb transaction STALL status */ +usb_status usb_transc_clrstall (usb_core_driver *udev, usb_transc *transc); + +/* read device all OUT endpoint interrupt register */ +uint32_t usb_oepintnum_read (usb_core_driver *udev); + +/* read device OUT endpoint interrupt flag register */ +uint32_t usb_oepintr_read (usb_core_driver *udev, uint8_t ep_num); + +/* read device all IN endpoint interrupt register */ +uint32_t usb_iepintnum_read (usb_core_driver *udev); + +/* read device IN endpoint interrupt flag register */ +uint32_t usb_iepintr_read (usb_core_driver *udev, uint8_t ep_num); + +/* config the USB device to be disconnected */ +void usb_dev_disconnect (usb_core_driver *udev); + +/* config the USB device to be connected */ +void usb_dev_connect (usb_core_driver *udev); + +/* set the USB device address */ +void usb_devaddr_set (usb_core_driver *pudev, uint8_t dev_addr); + +/* configures OUT endpoint 0 to receive SETUP packets */ +void usb_ctlep_startout (usb_core_driver *udev); + +/* active remote wakeup signalling */ +void usb_rwkup_active (usb_core_driver *udev); + +/* reset remote wakeup signalling */ +void usb_rwkup_reset (usb_core_driver *udev); + +/* set remote wakeup signalling */ +void usb_rwkup_set (usb_core_driver *udev); + +/* active USB core clock */ +void usb_clock_active (usb_core_driver *udev); + +/* usb device suspend */ +void usb_dev_suspend (usb_core_driver *udev); + +/* stop the device and clean up fifos */ +void usb_dev_stop (usb_core_driver *udev); + +#endif /* __DRV_USB_DEV_H */ + diff --git a/firmware/generic/src/drivers/usbfs/drv_usb_hw.h b/firmware/generic/src/drivers/usbfs/drv_usb_hw.h new file mode 100644 index 0000000..058efa8 --- /dev/null +++ b/firmware/generic/src/drivers/usbfs/drv_usb_hw.h @@ -0,0 +1,62 @@ +/*! + \file drv_usb_hw.h + \brief usb hardware configuration header file + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_HW_H +#define __DRV_USB_HW_H + +#include "usb_conf.h" + +/* configure USB clock */ +void usb_rcu_config (void); + +/* configure USB interrupt */ +void usb_intr_config (void); + +/* initializes delay unit using Timer2 */ +void usb_timer_init (void); + +/* delay in micro seconds */ +void usb_udelay (const uint32_t usec); + +/* delay in milli seconds */ +void usb_mdelay (const uint32_t msec); + +#ifdef USE_HOST_MODE +/* configure USB VBus */ + void usb_vbus_config (void); +/* drive usb VBus */ + void usb_vbus_drive (uint8_t State); +#endif /* USE_HOST_MODE */ + +#endif /* __DRV_USB_HW_H */ diff --git a/firmware/generic/src/drivers/usbfs/gd32vf103_hw.c b/firmware/generic/src/drivers/usbfs/gd32vf103_hw.c new file mode 100644 index 0000000..204c678 --- /dev/null +++ b/firmware/generic/src/drivers/usbfs/gd32vf103_hw.c @@ -0,0 +1,206 @@ +/*! + \file gd32vf103_hw.c + \brief USB hardware configuration for GD32VF103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include +#include +#include + + +#define TIM_MSEC_DELAY 0x01 +#define TIM_USEC_DELAY 0x02 + +__IO uint32_t delay_time = 0; +__IO uint32_t timer_prescaler; +__IO uint32_t usbfs_prescaler = 0; + +static void hw_time_set (uint8_t unit); +static void hw_delay (uint32_t ntime, uint8_t unit); + + +/*! + \brief configure USB clock + \param[in] none + \param[out] none + \retval none +*/ +void usb_rcu_config(void) +{ + uint32_t system_clock = rcu_clock_freq_get(CK_SYS); + + if (system_clock == 48000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1; + timer_prescaler = 3; + } else if (system_clock == 72000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1_5; + timer_prescaler = 5; + } else if (system_clock == 96000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV2; + timer_prescaler = 7; + } else { + /* reserved */ + } + + rcu_usb_clock_config(usbfs_prescaler); + rcu_periph_clock_enable(RCU_USBFS); +} + +/*! + \brief configure USB interrupt + \param[in] none + \param[out] none + \retval none +*/ +void usb_intr_config(void) +{ + eclic_irq_enable((uint8_t)USBFS_IRQn, 1, 0); + + /* enable the power module clock */ + rcu_periph_clock_enable(RCU_PMU); + + /* USB wakeup EXTI line configuration */ + exti_interrupt_flag_clear(EXTI_18); + exti_init(EXTI_18, EXTI_INTERRUPT, EXTI_TRIG_RISING); + exti_interrupt_enable(EXTI_18); + + eclic_irq_enable((uint8_t)USBFS_WKUP_IRQn, 3, 0); +} + +/*! + \brief initializes delay unit using Timer2 + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_init (void) +{ + rcu_periph_clock_enable(RCU_TIMER2); + + eclic_irq_enable(TIMER2_IRQn, 2, 0); +} + +/*! + \brief delay in micro seconds + \param[in] usec: value of delay required in micro seconds + \param[out] none + \retval none +*/ +void usb_udelay (const uint32_t usec) +{ + hw_delay(usec, TIM_USEC_DELAY); +} + +/*! + \brief delay in milli seconds + \param[in] msec: value of delay required in milli seconds + \param[out] none + \retval none +*/ +void usb_mdelay (const uint32_t msec) +{ + hw_delay(msec, TIM_MSEC_DELAY); +} + +/*! + \brief time base IRQ + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_irq (void) +{ + if (RESET != timer_flag_get(TIMER2, TIMER_FLAG_UP)){ + timer_flag_clear(TIMER2, TIMER_FLAG_UP); + + if (delay_time > 0x00U){ + delay_time--; + } else { + timer_disable(TIMER2); + } + } +} + +/*! + \brief delay routine based on TIM0 + \param[in] nTime: delay Time + \param[in] unit: delay Time unit = mili sec / micro sec + \param[out] none + \retval none +*/ +static void hw_delay(uint32_t ntime, uint8_t unit) +{ + delay_time = ntime; + + hw_time_set(unit); + + while (0U != delay_time) { + } + + timer_disable(TIMER2); +} + +/*! + \brief configures TIM0 for delay routine based on TIM0 + \param[in] unit: msec /usec + \param[out] none + \retval none +*/ +static void hw_time_set(uint8_t unit) +{ + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER2); + timer_deinit(TIMER2); + + if(TIM_USEC_DELAY == unit) { + timer_initpara.period = 11; + } else if(TIM_MSEC_DELAY == unit) { + timer_initpara.period = 11999; + } + + timer_initpara.prescaler = timer_prescaler; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER2, &timer_initpara); + + timer_update_event_enable(TIMER2); + timer_interrupt_enable(TIMER2,TIMER_INT_UP); + timer_flag_clear(TIMER2, TIMER_FLAG_UP); + timer_update_source_config(TIMER2, TIMER_UPDATE_SRC_GLOBAL); + + /* TIMER2 counter enable */ + timer_enable(TIMER2); +} diff --git a/firmware/generic/src/drivers/usbfs/midi.c b/firmware/generic/src/drivers/usbfs/midi.c new file mode 100644 index 0000000..9778a39 --- /dev/null +++ b/firmware/generic/src/drivers/usbfs/midi.c @@ -0,0 +1,319 @@ +/* + MIT License + + Copyright (c) 2019 nyannkov + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +#include +#include "midi.h" + +typedef enum _Parse_MIDI_Message_Event { + PARSE_MIDI_EVENT_RCV_STS_CH_MSG_1 = 0, + PARSE_MIDI_EVENT_RCV_STS_CH_MSG_2, + PARSE_MIDI_EVENT_RCV_SYS_RT, + PARSE_MIDI_EVENT_RCV_DAT, + PARSE_MIDI_EVENT_RCV_SYS_EX_START, + PARSE_MIDI_EVENT_RCV_SYS_EX_EOX, + NUM_OF_PARSE_MIDI_MESSAGE_EVENT +}Parse_MIDI_Message_Event_t; + +typedef struct _Parse_MIDI_FSM { + Parse_MIDI_Message_State_t next; + void (*pTransStateFunc)(MIDI_Handle_t *phMIDI, uint8_t msg); +}Parse_MIDI_FSM_t; + + +MIDI_Handle_t *MIDI_Alloc(void); +void MIDI_Free(MIDI_Handle_t *phMIDI); + + +static inline Parse_MIDI_Message_Event_t _GetParseMIDIMessageEvent(uint8_t msg) { + + if ( (msg & 0x80) == 0 ) { + return PARSE_MIDI_EVENT_RCV_DAT; + } + else if ( (msg & 0xF0) == 0xF0 ) { + switch ( msg ) { + case 0xF0: + return PARSE_MIDI_EVENT_RCV_SYS_EX_START; + + case 0xF7: + return PARSE_MIDI_EVENT_RCV_SYS_EX_EOX; + + default: + return PARSE_MIDI_EVENT_RCV_SYS_RT; + } + } + else { + + switch ( msg & 0xF0 ) { + case 0x80: + case 0x90: + case 0xA0: + case 0xB0: + case 0xE0: + return PARSE_MIDI_EVENT_RCV_STS_CH_MSG_2; + + case 0xC0: + case 0xD0: + return PARSE_MIDI_EVENT_RCV_STS_CH_MSG_1; + + default: + // unexpected + return PARSE_MIDI_EVENT_RCV_SYS_RT; + } + } + +} + + +static void _StoreChannelMessageStatus(MIDI_Handle_t *phMIDI, uint8_t msg); +static void _StoreChannelMessageData(MIDI_Handle_t *phMIDI, uint8_t msg); +static void _StoreSystemExclusiveMessage(MIDI_Handle_t *phMIDI, uint8_t msg); +static void _ExecChannelMessage1(MIDI_Handle_t *phMIDI, uint8_t msg); +static void _ExecChannelMessage2(MIDI_Handle_t *phMIDI, uint8_t msg); +static void _ExecSystemExclusiveMessage(MIDI_Handle_t *phMIDI, uint8_t msg); + +static const Parse_MIDI_FSM_t _midi_trans_state_tbl[NUM_OF_PARSE_MIDI_MESSAGE_STATE][NUM_OF_PARSE_MIDI_MESSAGE_EVENT] = { + /* IDLE */ + { + {PARSE_MIDI_CH_MSG_1, _StoreChannelMessageStatus}, // RCV_STS_CH_MSG_1 + {PARSE_MIDI_CH_MSG_2_1, _StoreChannelMessageStatus}, // RCV_STS_CH_MSG_2 + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_RT + {PARSE_MIDI_IDLE, NULL}, // RCV_DAT + {PARSE_MIDI_SYS_EX, _StoreSystemExclusiveMessage}, // RCV_SYS_EX_START + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_EX_EOX + }, + /* CH_MSG_1 */ + { + {PARSE_MIDI_IDLE, NULL}, // RCV_STS_CH_MSG_1 + {PARSE_MIDI_IDLE, NULL}, // RCV_STS_CH_MSG_2 + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_RT + {PARSE_MIDI_CH_MSG_RUNNING_1, _ExecChannelMessage1}, // RCV_DAT + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_EX_START + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_EX_EOX + }, + /* CH_MSG_2_1 */ + { + {PARSE_MIDI_IDLE, NULL}, // RCV_STS_CH_MSG_1 + {PARSE_MIDI_IDLE, NULL}, // RCV_STS_CH_MSG_2 + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_RT + {PARSE_MIDI_CH_MSG_2_2, _StoreChannelMessageData}, // RCV_DAT + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_EX_START + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_EX_EOX + }, + /* CH_MSG_2_2 */ + { + {PARSE_MIDI_IDLE, NULL}, // RCV_STS_CH_MSG_1 + {PARSE_MIDI_IDLE, NULL}, // RCV_STS_CH_MSG_2 + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_RT + {PARSE_MIDI_CH_MSG_RUNNING_2, _ExecChannelMessage2}, // RCV_DAT + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_EX_START + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_EX_EOX + }, + /* CH_MSG_RUNNING_1 */ + { + {PARSE_MIDI_CH_MSG_1, _StoreChannelMessageStatus}, // RCV_STS_CH_MSG_1 + {PARSE_MIDI_CH_MSG_2_1, _StoreChannelMessageStatus}, // RCV_STS_CH_MSG_2 + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_RT + {PARSE_MIDI_CH_MSG_RUNNING_1, _ExecChannelMessage1}, // RCV_DAT + {PARSE_MIDI_SYS_EX, NULL}, // RCV_SYS_EX_START + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_EX_EOX + }, + /* CH_MSG_RUNNING_2 */ + { + {PARSE_MIDI_CH_MSG_1, _StoreChannelMessageStatus}, // RCV_STS_CH_MSG_1 + {PARSE_MIDI_CH_MSG_2_1, _StoreChannelMessageStatus}, // RCV_STS_CH_MSG_2 + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_RT + {PARSE_MIDI_CH_MSG_2_2, _StoreChannelMessageData}, // RCV_DAT + {PARSE_MIDI_SYS_EX, NULL}, // RCV_SYS_EX_START + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_EX_EOX + }, + /* PARSE_MIDI_SYS_EX */ + { + {PARSE_MIDI_SYS_EX, _StoreSystemExclusiveMessage}, // RCV_STS_CH_MSG_1 + {PARSE_MIDI_SYS_EX, _StoreSystemExclusiveMessage}, // RCV_STS_CH_MSG_2 + {PARSE_MIDI_SYS_EX, _StoreSystemExclusiveMessage}, // RCV_SYS_RT + {PARSE_MIDI_SYS_EX, _StoreSystemExclusiveMessage}, // RCV_DAT + {PARSE_MIDI_SYS_EX, _StoreSystemExclusiveMessage}, // RCV_SYS_EX_START + {PARSE_MIDI_IDLE, _ExecSystemExclusiveMessage}, // RCV_SYS_EX_EOX + } +}; + + +MIDI_Handle_t *MIDI_Init(const MIDI_Message_Callbacks_t *pcallbacks ) { + + MIDI_Handle_t *phMIDI = NULL; + phMIDI = MIDI_Alloc(); + + if ( phMIDI != NULL ) { + uint32_t i = 0; + phMIDI->chmsg_buf.msg0 = 0; + phMIDI->chmsg_buf.msg1 = 0; + phMIDI->chmsg_buf.msg2 = 0; + phMIDI->chmsg_buf.pad = 0; + phMIDI->sysex_buf.len = 0; + for ( i = 0; i < MAX_SYS_EX_BUF_SIZE; i++ ) { + phMIDI->sysex_buf.msg[i] = 0; + } + + phMIDI->state = PARSE_MIDI_IDLE; + phMIDI->pcallback = pcallbacks; + } + + return phMIDI; +} + +void MIDI_DeInit( MIDI_Handle_t *phMIDI ) { + + if ( phMIDI != NULL ) { + MIDI_Free(phMIDI); + } +} + +int32_t MIDI_Play(MIDI_Handle_t *phMIDI, const uint8_t *midi_msg, size_t len) { + + uint32_t i = 0; + Parse_MIDI_Message_Event_t event = PARSE_MIDI_EVENT_RCV_STS_CH_MSG_1; + const Parse_MIDI_FSM_t *pfsm = NULL; + + for ( i = 0; i < len; i++ ) { + event = _GetParseMIDIMessageEvent(midi_msg[i]); + + pfsm = &_midi_trans_state_tbl[phMIDI->state][event]; + + if ( pfsm->pTransStateFunc != NULL ) { + pfsm->pTransStateFunc(phMIDI, midi_msg[i]); + } + phMIDI->state = pfsm->next; + } + + return 0; +} + +__WEAK__ MIDI_Handle_t *MIDI_Alloc(void) +{ + static MIDI_Handle_t hMIDI; + return &hMIDI; +} + +__WEAK__ void MIDI_Free(MIDI_Handle_t *phMIDI) +{ + (void)phMIDI; +} + +static void _StoreChannelMessageStatus(MIDI_Handle_t *phMIDI, uint8_t msg) { + phMIDI->chmsg_buf.msg0 = msg; +} + +static void _StoreChannelMessageData(MIDI_Handle_t *phMIDI, uint8_t msg) { + phMIDI->chmsg_buf.msg1 = msg; +} + +static void _StoreSystemExclusiveMessage(MIDI_Handle_t *phMIDI, uint8_t msg) { + MIDI_System_Exclusive_Buffer_t *psys_ex_buf = &phMIDI->sysex_buf; + if ( psys_ex_buf->len < MAX_SYS_EX_BUF_SIZE ) { + psys_ex_buf->msg[(psys_ex_buf->len)++] = msg; + } +} + +static void _ExecChannelMessage1(MIDI_Handle_t *phMIDI, uint8_t msg) { + + const MIDI_ChannelVoiceMessage_t *pchvmsg = &phMIDI->pcallback->channel.voice_msg; + + phMIDI->chmsg_buf.msg1 = msg; + + switch (phMIDI->chmsg_buf.msg0 & 0xF0) { + case 0xC0: + if ( pchvmsg->pProgramChange != NULL ) { + pchvmsg->pProgramChange(phMIDI->chmsg_buf.msg0 & 0x0F, phMIDI->chmsg_buf.msg1); + } + break; + + case 0xD0: + if ( pchvmsg->pChannelPressure != NULL ) { + pchvmsg->pChannelPressure(phMIDI->chmsg_buf.msg0 & 0x0F, phMIDI->chmsg_buf.msg1); + } + break; + + default: + break; + } +} + +static void _ExecChannelMessage2(MIDI_Handle_t *phMIDI, uint8_t msg) { + + const MIDI_ChannelVoiceMessage_t *pchvmsg = &phMIDI->pcallback->channel.voice_msg; + phMIDI->chmsg_buf.msg2 = msg; + + switch (phMIDI->chmsg_buf.msg0 & 0xF0) { + case 0x80: + if ( pchvmsg->pNoteOff != NULL ) { + pchvmsg->pNoteOff(phMIDI->chmsg_buf.msg0 & 0x0F, phMIDI->chmsg_buf.msg1, phMIDI->chmsg_buf.msg2); + gpio_bit_set(GPIOA, GPIO_PIN_2); + } + break; + + case 0x90: + if ( pchvmsg->pNoteOn != NULL ) { + pchvmsg->pNoteOn(phMIDI->chmsg_buf.msg0 & 0x0F, phMIDI->chmsg_buf.msg1, phMIDI->chmsg_buf.msg2); + gpio_bit_reset(GPIOA, GPIO_PIN_2); + } + break; + + case 0xA0: + if ( pchvmsg->pPolyphonicKeyPressure != NULL ) { + pchvmsg->pPolyphonicKeyPressure(phMIDI->chmsg_buf.msg0 & 0x0F, phMIDI->chmsg_buf.msg1, phMIDI->chmsg_buf.msg2); + } + break; + + case 0xB0: + if ( pchvmsg->pControlChange != NULL ) { + pchvmsg->pControlChange(phMIDI->chmsg_buf.msg0 & 0x0F, phMIDI->chmsg_buf.msg1, phMIDI->chmsg_buf.msg2); + } + break; + + case 0xE0: + if ( pchvmsg->pPitchBendChange != NULL ) { + pchvmsg->pPitchBendChange(phMIDI->chmsg_buf.msg0 & 0x0F, phMIDI->chmsg_buf.msg1, phMIDI->chmsg_buf.msg2); + } + break; + + default: + break; + } +} + + +static void _ExecSystemExclusiveMessage(MIDI_Handle_t *phMIDI, uint8_t msg) { + + const MIDI_SystemExclusiveMessage_t *psys_ex = &phMIDI->pcallback->system.exclusive_msg; + MIDI_System_Exclusive_Buffer_t *psys_ex_buf = &phMIDI->sysex_buf; + + (void)msg; + + if ( psys_ex->pSystemExclusive != NULL ) { + psys_ex->pSystemExclusive(psys_ex_buf->msg, psys_ex_buf->len); + } + + // clear + psys_ex_buf->len = 0; +} \ No newline at end of file diff --git a/firmware/generic/src/drivers/usbfs/midi.h b/firmware/generic/src/drivers/usbfs/midi.h new file mode 100644 index 0000000..bfa1af6 --- /dev/null +++ b/firmware/generic/src/drivers/usbfs/midi.h @@ -0,0 +1,93 @@ +/* + MIT License + + Copyright (c) 2019 nyannkov + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +#ifndef __MIDI_H__ +#define __MIDI_H__ + +#include "midiconf.h" + +typedef struct _MIDI_Channel_Message_Buffer { + uint8_t msg0; // status byte + uint8_t msg1; // data byte 1 + uint8_t msg2; // data byte 2 + uint8_t pad; // padding +}MIDI_Channel_Message_Buffer_t; + +typedef struct _MIDI_System_Exclusive_Buffer { + uint8_t msg[MAX_SYS_EX_BUF_SIZE]; + size_t len; +}MIDI_System_Exclusive_Buffer_t; + + +typedef enum _Parse_MIDI_Message_State { + PARSE_MIDI_IDLE = 0, + PARSE_MIDI_CH_MSG_1, + PARSE_MIDI_CH_MSG_2_1, + PARSE_MIDI_CH_MSG_2_2, + PARSE_MIDI_CH_MSG_RUNNING_1, + PARSE_MIDI_CH_MSG_RUNNING_2, + PARSE_MIDI_SYS_EX, + NUM_OF_PARSE_MIDI_MESSAGE_STATE +}Parse_MIDI_Message_State_t; + + +typedef struct _MIDI_ChannelVoiceMessage { + void (*pNoteOff)(uint8_t ch, uint8_t kk, uint8_t uu); + void (*pNoteOn)(uint8_t ch, uint8_t kk, uint8_t vv); + void (*pPolyphonicKeyPressure)(uint8_t ch, uint8_t kk, uint8_t vv); + void (*pControlChange)(uint8_t ch, uint8_t cc, uint8_t vv); + void (*pProgramChange)(uint8_t ch, uint8_t pp); + void (*pChannelPressure)(uint8_t ch, uint8_t vv); + void (*pPitchBendChange)(uint8_t ch, uint8_t ll, uint8_t hh); +}MIDI_ChannelVoiceMessage_t; + +typedef struct _MIDI_ChannelMessage { + MIDI_ChannelVoiceMessage_t voice_msg; +}MIDI_ChannelMessage_t; + +typedef struct _MIDI_SystemExclusiveMessage { + void (*pSystemExclusive)(uint8_t *dat, size_t len); +}MIDI_SystemExclusiveMessage_t; + +typedef struct _MIDI_SystemMessage { + MIDI_SystemExclusiveMessage_t exclusive_msg; +}MIDI_SystemMessage_t; + +typedef struct _MIDI_Message_Callbacks { + MIDI_ChannelMessage_t channel; + MIDI_SystemMessage_t system; +}MIDI_Message_Callbacks_t; + +typedef struct _MIDI_Handle { + MIDI_Channel_Message_Buffer_t chmsg_buf; + MIDI_System_Exclusive_Buffer_t sysex_buf; + const MIDI_Message_Callbacks_t *pcallback; + Parse_MIDI_Message_State_t state; +}MIDI_Handle_t; + +extern MIDI_Handle_t *MIDI_Init(const MIDI_Message_Callbacks_t *pcallbacks ); +extern void MIDI_DeInit( MIDI_Handle_t *phMIDI ); +extern int32_t MIDI_Play(MIDI_Handle_t *phMIDI, const uint8_t *midi_msg, size_t len); + +#endif // __MIDI_H__ diff --git a/firmware/generic/src/drivers/usbfs/midi_cdc_core.c b/firmware/generic/src/drivers/usbfs/midi_cdc_core.c new file mode 100644 index 0000000..4307063 --- /dev/null +++ b/firmware/generic/src/drivers/usbfs/midi_cdc_core.c @@ -0,0 +1,430 @@ +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ +#include +#include + +#include +#include +#include +#include "usbd_core.h" +#include "drv_usb_hw.h" +#include "usbd_enum.h" +#include "midi_cdc_desc.h" +#include "midi_cdc_core.h" + + +// usb cdc acm data send buffer page +#define USB_CDC_TX_BUF_PAGE_NUM 2 + +// each usb cdc acm data send buffer size +#ifndef USB_CDC_TX_BUF_SIZE +#define USB_CDC_TX_BUF_SIZE (CDC_ACM_DATA_PACKET_SIZE * 10) +#endif + +#define SEND_ENCAPSULATED_COMMAND 0x00 +#define GET_ENCAPSULATED_RESPONSE 0x01 +#define SET_COMM_FEATURE 0x02 +#define GET_COMM_FEATURE 0x03 +#define CLEAR_COMM_FEATURE 0x04 +#define SET_LINE_CODING 0x20 +#define GET_LINE_CODING 0x21 +#define SET_CONTROL_LINE_STATE 0x22 +#define SEND_BREAK 0x23 +#define NO_CMD 0xFF + +// usb cdc acm data send status +typedef enum +{ + USB_CDC_SEND_STATUS_INIT = 0, + USB_CDC_SEND_STATUS_BUSY, + USB_CDC_SEND_STATUS_FINISHED +}usb_cdc_send_status_t; + +typedef struct +{ + uint32_t dwDTERate; /* data terminal rate */ + uint8_t bCharFormat; /* stop bits */ + uint8_t bParityType; /* parity */ + uint8_t bDataBits; /* data bits */ +}line_coding_struct; + + +static uint32_t cdc_cmd = 0xFFU; +static uint8_t usb_cmd_buffer[CDC_ACM_CMD_PACKET_SIZE]; + + +// current usb cdc acm data send status +static usb_cdc_send_status_t usb_cdc_send_status = USB_CDC_SEND_STATUS_INIT; + +// current usb cdc acm data buffer page +static uint8_t current_buffer_page = 0; + +// current usb cdc acm data buffer position +static uint16_t current_end_position = 0; + +// usb cdc acm data send buffer (double buffer) +static uint8_t usb_cdc_tx_buffer[USB_CDC_TX_BUF_PAGE_NUM][USB_CDC_TX_BUF_SIZE]; + +// usb cdc data receive buffer +uint8_t usb_cdc_receive_buffer[CDC_ACM_DATA_PACKET_SIZE]; + +// usb midi receive buffer +uint8_t usb_midi_receive_buffer[AUDIO_MS_PACKET_SIZE]; + +// receive callback functions +static pf_usb_midi_receive_callback_t usb_midi_recv_cb = (pf_usb_midi_receive_callback_t)0; +static pf_usb_cdc_receive_callback_t usb_cdc_recv_cb = (pf_usb_cdc_receive_callback_t)0; + + +static uint8_t midi_cdc_init(usb_dev *udev, uint8_t config_index); +static uint8_t midi_cdc_deinit(usb_dev *udev, uint8_t config_index); +static uint8_t midi_cdc_req_proc(usb_dev *udev, usb_req *req); +static uint8_t midi_cdc_data_in(usb_dev *udev, uint8_t ep_num); +static uint8_t midi_cdc_data_out(usb_dev *udev, uint8_t ep_num); + + +static uint8_t cdc_acm_req_handler (usb_dev *pudev, usb_req *req); +static uint8_t cdc_acm_EP0_RxReady (usb_dev *pudev); + + +static void start_usb_cdc_send_service_irq(void); + + +static line_coding_struct linecoding = +{ + 115200, /* baud rate */ + 0x00, /* stop bits - 1 */ + 0x00, /* parity - none */ + 0x08 /* num of bits 8 */ +}; + +static usb_class_core class_core = +{ + .command = NO_CMD, /*!< device class request command */ + .alter_set = 0, /*!< alternative set */ + .init = midi_cdc_init, /*!< initialize handler */ + .deinit = midi_cdc_deinit, /*!< de-initialize handler */ + .req_proc = midi_cdc_req_proc, /*!< device request handler */ + .data_in = midi_cdc_data_in, /*!< device data in handler */ + .data_out = midi_cdc_data_out, /*!< device data out handler */ + .SOF = NULL, /*!< Start of frame handler */ + .incomplete_isoc_in = NULL, /*!< Incomplete synchronization IN transfer handler */ + .incomplete_isoc_out = NULL, /*!< Incomplete synchronization OUT transfer handler */ +}; + + +void init_usbd_midi(const pf_usb_midi_receive_callback_t midi_recv_cb) +{ + // register_usb_cdc_receive_callback(cdc_recv_cb); + + register_usb_midi_receive_callback(midi_recv_cb); + + eclic_irq_enable(TIMER2_IRQn, 2, 0); + + /* USB device stack configure */ + usbd_init (&g_midi_cdc_udev, USB_CORE_ENUM_FS, &class_core); + + // start_usb_cdc_send_service_irq(); + + /* USB interrupt configure */ + usb_intr_config(); + + /* check if USB device is enumerated successfully */ + while (g_midi_cdc_udev.dev.cur_status != USBD_CONFIGURED) + { + } +} + +// register a callback function to be called when usb midi message received. +void register_usb_midi_receive_callback(const pf_usb_midi_receive_callback_t callback) +{ + usb_midi_recv_cb = callback; +} + +// register a callback function to be called when usb cdc data received. +void register_usb_cdc_receive_callback(const pf_usb_cdc_receive_callback_t callback) +{ + usb_cdc_recv_cb = callback; +} + +int usb_cdc_printf(const char *format, ...) +{ + int written_num = 0; + size_t max_write_num = 0; + + va_list arg; + va_start(arg, format); + + // entry critical section + eclic_global_interrupt_disable(); + max_write_num = USB_CDC_TX_BUF_SIZE - current_end_position; + written_num = vsnprintf( + (char *)&usb_cdc_tx_buffer[current_buffer_page][current_end_position] + ,max_write_num, format, arg); + + if ( ( 0 < written_num ) && ( written_num < max_write_num ) ) + { + current_end_position += written_num; + } + // leave critical section + eclic_global_interrupt_enable(); + + va_end(arg); + + return 0; +} + +// send data and switch send buffer page. +void usb_cdc_send_service_irq(void) +{ + if (RESET != timer_flag_get(TIMER6, TIMER_FLAG_UP)) + { + if (USBD_CONFIGURED == g_midi_cdc_udev.dev.cur_status) + { + // entry critical section + eclic_global_interrupt_disable(); + if ( usb_cdc_send_status != USB_CDC_SEND_STATUS_BUSY ) + { + if ( current_end_position > 0 ) + { + usb_cdc_send_status = USB_CDC_SEND_STATUS_BUSY; + usbd_ep_send(&g_midi_cdc_udev, CDC_IN_EP, &usb_cdc_tx_buffer[current_buffer_page][0] , current_end_position); + current_end_position = 0; + current_buffer_page++; + if ( current_buffer_page >= USB_CDC_TX_BUF_PAGE_NUM ) + { + current_buffer_page = 0; + } + } + } + // leave critical section + eclic_global_interrupt_enable(); + } + + timer_flag_clear(TIMER6, TIMER_FLAG_UP); + } +} + +static uint8_t midi_cdc_init(usb_dev *udev, uint8_t config_index) +{ + midi_cdc_desc_ep_setup(udev); + + // prepare receive data + usbd_ep_recev(udev, MIDI_OUT_EP, usb_midi_receive_buffer, AUDIO_MS_PACKET_SIZE); + usbd_ep_recev(udev, CDC_OUT_EP, usb_cdc_receive_buffer, CDC_ACM_DATA_PACKET_SIZE); + + return 0; +} + + +static uint8_t midi_cdc_deinit(usb_dev *udev, uint8_t config_index) +{ + midi_cdc_desc_ep_clear(udev); + return 0; +} + + +static uint8_t midi_cdc_req_proc(usb_dev *udev, usb_req *req) +{ + switch (req->wIndex) + { + case AUDIO_AC_ITF_NUMBER: + break; + + case AUDIO_MS_ITF_NUMBER: + break; + + case CDC_CDC_ITF_NUMBER: + cdc_acm_req_handler(udev, req); + break; + + case CDC_DATA_ITF_NUMBER: + break; + + default: + break; + } + return 0; +} + + +static uint8_t midi_cdc_data_in(usb_dev *udev, uint8_t ep_num) +{ + if ((CDC_IN_EP & 0x7F) == ep_num) + { + usb_transc *transc = &udev->dev.transc_in[EP_ID(ep_num)]; + + if ((transc->xfer_len % transc->max_len == 0) && (transc->xfer_len != 0)) + { + usbd_ep_send (udev, ep_num, NULL, 0U); + } + else + { + usb_cdc_send_status = USB_CDC_SEND_STATUS_FINISHED; + } + } + + return 0; +} + + +static uint8_t midi_cdc_data_out(usb_dev *udev, uint8_t ep_num) +{ + uint32_t receive_length = 0U; + + if ((EP0_OUT & 0x7F) == ep_num) + { + cdc_acm_EP0_RxReady (udev); + } + else if ((CDC_OUT_EP & 0x7F) == ep_num) + { + receive_length = usbd_rxcount_get(udev, CDC_OUT_EP); + if ( usb_cdc_recv_cb ) + { + usb_cdc_recv_cb(usb_cdc_receive_buffer, receive_length); + } + usbd_ep_recev(udev, CDC_OUT_EP, usb_cdc_receive_buffer, CDC_ACM_DATA_PACKET_SIZE); + } + else if ((MIDI_OUT_EP & 0x7F) == ep_num) + { + receive_length = usbd_rxcount_get(udev, MIDI_OUT_EP); + if ( usb_midi_recv_cb ) + { + usb_midi_recv_cb(usb_midi_receive_buffer, receive_length); + } + usbd_ep_recev(udev, MIDI_OUT_EP, usb_midi_receive_buffer, AUDIO_MS_PACKET_SIZE); + } + else + { + } + + return 0; +} + +/*! + \brief handle the CDC ACM class-specific requests + \param[in] pudev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_req_handler (usb_dev *pudev, usb_req *req) +{ + switch (req->bRequest) + { + case SEND_ENCAPSULATED_COMMAND: + break; + case GET_ENCAPSULATED_RESPONSE: + break; + case SET_COMM_FEATURE: + break; + case GET_COMM_FEATURE: + break; + case CLEAR_COMM_FEATURE: + break; + case SET_LINE_CODING: + /* set the value of the current command to be processed */ + cdc_cmd = req->bRequest; + /* enable EP0 prepare to receive command data packet */ + pudev->dev.transc_out[0].xfer_buf = usb_cmd_buffer; + pudev->dev.transc_out[0].remain_len = req->wLength; + break; + case GET_LINE_CODING: + usb_cmd_buffer[0] = (uint8_t)(linecoding.dwDTERate); + usb_cmd_buffer[1] = (uint8_t)(linecoding.dwDTERate >> 8); + usb_cmd_buffer[2] = (uint8_t)(linecoding.dwDTERate >> 16); + usb_cmd_buffer[3] = (uint8_t)(linecoding.dwDTERate >> 24); + usb_cmd_buffer[4] = linecoding.bCharFormat; + usb_cmd_buffer[5] = linecoding.bParityType; + usb_cmd_buffer[6] = linecoding.bDataBits; + /* send the request data to the host */ + pudev->dev.transc_in[0].xfer_buf = usb_cmd_buffer; + pudev->dev.transc_in[0].remain_len = req->wLength; + break; + case SET_CONTROL_LINE_STATE: + break; + case SEND_BREAK: + break; + default: + break; + } + + return USBD_OK; +} + +/*! + \brief command data received on control endpoint + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_EP0_RxReady (usb_dev *pudev) +{ + if (NO_CMD != cdc_cmd) { + /* process the command data */ + linecoding.dwDTERate = (uint32_t)(usb_cmd_buffer[0] | + (usb_cmd_buffer[1] << 8) | + (usb_cmd_buffer[2] << 16) | + (usb_cmd_buffer[3] << 24)); + + linecoding.bCharFormat = usb_cmd_buffer[4]; + linecoding.bParityType = usb_cmd_buffer[5]; + linecoding.bDataBits = usb_cmd_buffer[6]; + + cdc_cmd = NO_CMD; + } + + return USBD_OK; +} + +// start usb cdc send service routine. +static void start_usb_cdc_send_service_irq(void) +{ + timer_parameter_struct timer_initpara; + + eclic_irq_enable(TIMER6_IRQn, 2, 0); + + timer_struct_para_init(&timer_initpara); + + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.prescaler = 9599;// 96 MHz/ 9600 = 10 kHz + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 10; + + timer_deinit(TIMER6); + timer_init(TIMER6, &timer_initpara); + + timer_update_event_enable(TIMER6); + timer_interrupt_enable(TIMER6,TIMER_INT_UP); + timer_flag_clear(TIMER6, TIMER_FLAG_UP); + timer_update_source_config(TIMER6, TIMER_UPDATE_SRC_GLOBAL); + + /* TIMER6 counter enable */ + timer_enable(TIMER6); +} + diff --git a/firmware/generic/src/drivers/usbfs/midi_cdc_core.h b/firmware/generic/src/drivers/usbfs/midi_cdc_core.h new file mode 100644 index 0000000..f095b48 --- /dev/null +++ b/firmware/generic/src/drivers/usbfs/midi_cdc_core.h @@ -0,0 +1,46 @@ +/* + MIT License + + Copyright (c) 2020 nyannkov + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ +#ifndef MIDI_CDC_CORE_H +#define MIDI_CDC_CORE_H + +#include +#include + + + + +typedef int32_t (*pf_usb_midi_receive_callback_t)(const uint8_t *recv_msg, size_t len); +typedef int32_t (*pf_usb_cdc_receive_callback_t)(const uint8_t *recv_data, size_t len); + +extern void register_usb_midi_receive_callback(const pf_usb_midi_receive_callback_t callback); +extern void register_usb_cdc_receive_callback(const pf_usb_cdc_receive_callback_t callback); + +extern void init_usbd_midi(const pf_usb_midi_receive_callback_t midi_recv_cb); + +extern void usb_cdc_send_service_irq(void); + +extern int usb_cdc_printf(const char *format, ...); + +#endif/* MIDI_CDC_CORE_H */ + diff --git a/firmware/generic/src/drivers/usbfs/midi_cdc_desc.c b/firmware/generic/src/drivers/usbfs/midi_cdc_desc.c new file mode 100644 index 0000000..4777c3b --- /dev/null +++ b/firmware/generic/src/drivers/usbfs/midi_cdc_desc.c @@ -0,0 +1,386 @@ +/* + MIT License + + Copyright (c) 2020 nyannkov + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ +#include +#include +#include "midi_cdc_desc.h" + +#define USBD_VID 0xaaaa// replace 0xaaaa with your vid +#define USBD_PID 0xbbbb// replace 0xbbbb with your pid + +#define LITTLE_ENDIAN_16(x) (x) + +static const usb_desc_dev device_descriptor = +{ + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, + .bcdUSB = 0x0200, + .bDeviceClass = 0xEF, + .bDeviceSubClass = 0x02, + .bDeviceProtocol = 0x01, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = LITTLE_ENDIAN_16(0x0100), + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM +}; + +static const usb_descriptor_configuration_set_struct configuration_descriptor= +{ + .config = + {/* Configuration 1 */ + .header = + { + .bLength = 0x09, + .bDescriptorType = USB_DESCTYPE_CONFIG, + }, + .wTotalLength = LITTLE_ENDIAN_16(0x00AF), + .bNumInterfaces = 0x04, /* audio 2 + cdc 2 = 4 */ + .bConfigurationValue = 0x01, + .iConfiguration = 0x00, + .bmAttributes = 0xC0, + .bMaxPower = 0x32, + }, + .usb_iad_audio = + {/* Interface Associated Descriptor */ + .bLength = 0x08, + .bDescriptorType = 0x0B, + .bFirstInterface = AUDIO_AC_ITF_NUMBER, + .bInterfaceCount = 0x02, + .bFunctionClass = 0x01, + .bFunctionSubClass = 0x01, + .bFunctionProtocol = 0x00, + .iFunction = 0x02, + }, + .audio = + {/* Audio device */ + .standard_ac_itf = + {/* Standard AC Interface Descriptor */ + .header = + { + .bLength = 0x09, + .bDescriptorType = USB_DESCTYPE_ITF, + }, + .bInterfaceNumber = AUDIO_AC_ITF_NUMBER, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x00, + .bInterfaceClass = 0x01, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x00, + .iInterface = 0x00, + }, + .class_specific_ac_itf = + {/* Class-specific AC Interface Descriptor */ + .bLength = 0x09, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x01, + .bcdADC = LITTLE_ENDIAN_16(0x0100),/* 1.00 */ + .wTotalLength = LITTLE_ENDIAN_16(0x0009), + .bInCollection = 0x01, + .baInterfaceNr = AUDIO_MS_ITF_NUMBER, + }, + .standard_ms_itf = + {/* Standard MS Interface Descriptor */ + .header = + { + .bLength = 0x09, + .bDescriptorType = USB_DESCTYPE_ITF, + }, + .bInterfaceNumber = AUDIO_MS_ITF_NUMBER, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x02, + .bInterfaceClass = 0x01, + .bInterfaceSubClass = 0x03, + .bInterfaceProtocol = 0x00, + .iInterface = 0x00, + }, + .class_specific_ms_itf = + {/* Class-specific MS Interface Descriptor */ + .bLength = 0x07, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x01, + .BcdADC = LITTLE_ENDIAN_16(0x0100), + .wTotalLength = LITTLE_ENDIAN_16(0x0025), + }, + .midi_in_jack_embedded = + {/* MIDI IN Jack Descriptor (Embedded) */ + .bLength = 0x06, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x02, + .bJackType = 0x01,/* embedded */ + .bJackID = 0x01, + .iJack = 0x00, + }, + .midi_in_jack_external = + {/* MIDI In Jack Descriptor (External) */ + .bLength = 0x06, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x02, + .bJackType = 0x02, /* external */ + .bJackID = 0x02, + .iJack = 0x00, + }, + .midi_out_jack_embedded = + {/* MIDI OUT Jack Descriptor (Embedded) */ + .bLength = 0x09, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x03, + .bJackType = 0x01, + .bJackID = 0x03, + .bNtInputPins = 0x01, + .BaSourceID = 0x02, + .BaSourcePin = 0x01, + .iJack = 0x00, + }, + .midi_out_jack_external = + {/* MIDI OUT Jack Descriptor (External) */ + .bLength = 0x09, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x03, + .bJackType = 0x02, + .bJackID = 0x04, + .bNtInputPins = 0x01, + .BaSourceID = 0x01, + .BaSourcePin = 0x01, + .iJack = 0x00, + }, + .bulk_out_ep_desc = + {/* Standard Bulk OUT EndPoint Descriptor */ + .desc_ep = + { + .header = + { + .bLength = 0x09, + .bDescriptorType= 0x05, + }, + .bEndpointAddress = MIDI_OUT_EP, + .bmAttributes = 0x02, + .wMaxPacketSize = LITTLE_ENDIAN_16(AUDIO_MS_PACKET_SIZE), + .bInterval = 0x01, + }, + .bRefresh = 0x00, + .bSynchAddress = 0x00, + }, + .class_specific_ms_bulk_out_ep = + {/* Class-specific Bulk OUT EndPoint Descriptor */ + .bLength = 0x05, + .bDescriptorType = 0x25, + .bDescriptorSubtype = 0x01, + .bNumEmbMIDIJack = 0x01, + .BaAssocJackID = 0x01, + }, + .bulk_in_ep_desc = + {/* Standard Bulk IN EndPoint Descriptor */ + .desc_ep = + { + .header = + { + .bLength = 0x09, + .bDescriptorType= 0x05, + }, + .bEndpointAddress = MIDI_IN_EP, + .bmAttributes = 0x02, + .wMaxPacketSize = LITTLE_ENDIAN_16(AUDIO_MS_PACKET_SIZE), + .bInterval = 0x00, + }, + .bRefresh = 0x00, + .bSynchAddress = 0x00, + }, + .class_specific_ms_bulk_in_ep = + {/* Class-specific Bulk IN EndPoint Descriptor */ + .bLength = 0x05, + .bDescriptorType = 0x25, + .bDescriptorSubtype = 0x01, + .bNumEmbMIDIJack = 0x01, + .BaAssocJackID = 0x03, + }, + }, + .usb_iad_cdc = + {/* Interface Associated Descriptor */ + .bLength = 0x08, + .bDescriptorType = 0x0B, + .bFirstInterface = CDC_CDC_ITF_NUMBER, + .bInterfaceCount = 0x02, + .bFunctionClass = 0x02, + .bFunctionSubClass = 0x02, + .bFunctionProtocol = 0x01, + .iFunction = 0x02, + }, + .cdc = + { + .cdc_cdc_itf = + {/* Interface Descriptor */ + .header = + { + .bLength = 0x09, + .bDescriptorType = 0x04, + }, + .bInterfaceNumber = CDC_CDC_ITF_NUMBER, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x01, + .bInterfaceClass = 0x02, + .bInterfaceSubClass = 0x02, + .bInterfaceProtocol = 0x01, + .iInterface = 0x00, + }, + .header_func_desc = + {/* Header Functional Descriptor */ + .bLength = 0x05, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x00, + .bcdCDC = LITTLE_ENDIAN_16(0x0110), + }, + .call_mng_func_desc = + {/* Call Management Functional Descriptor */ + .bFunctionLength = 0x05, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x01, + .bmCapabilities = 0x00, + .bDataInterface = 0x01, + }, + .acm_func_desc = + {/* ACM Functional Descriptor */ + .bFunctionLength = 0x04, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x02, + .bmCapabilities = 0x02, + }, + .union_func_desc = + {/* Union Functional Descriptor */ + .bFunctionLength = 0x05, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x06, + .bMasterInterface = CDC_CDC_ITF_NUMBER, + .bSlaveInterface0 = CDC_DATA_ITF_NUMBER, + }, + .cmd_ep = + {/* Endpoint Descriptor */ + .header = + { + .bLength = 0x07, + .bDescriptorType = 0x05, + }, + .bEndpointAddress = CDC_CMD_EP, + .bmAttributes = 0x03, + .wMaxPacketSize = LITTLE_ENDIAN_16(CDC_ACM_CMD_PACKET_SIZE), + .bInterval = 0x10, + }, + .cdc_data_itf = + {/* Data Class Interface Descriptor */ + .header = + { + .bLength = 0x09, + .bDescriptorType = 0x04, + }, + .bInterfaceNumber = CDC_DATA_ITF_NUMBER, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x02, + .bInterfaceClass = 0x0A, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, + .iInterface = 0x00, + }, + .end_out = + {/* Endpoint OUT Descriptor */ + .header = + { + .bLength = 0x07, + .bDescriptorType = 0x05, + }, + .bEndpointAddress = CDC_OUT_EP, + .bmAttributes = 0x02, + .wMaxPacketSize = LITTLE_ENDIAN_16(CDC_ACM_DATA_PACKET_SIZE), + .bInterval = 0x00, + }, + .end_in = + {/* Endpoint IN Descriptor */ + .header = + { + .bLength = 0x07, + .bDescriptorType = 0x05, + }, + .bEndpointAddress = CDC_IN_EP, + .bmAttributes = 0x02, + .wMaxPacketSize = LITTLE_ENDIAN_16(CDC_ACM_DATA_PACKET_SIZE), + .bInterval = 0x00, + }, + }, +}; + +static const usb_desc_LANGID usbd_language_id_desc = +{ + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + .wLANGID = ENG_LANGID +}; + +static void* const usbd_strings[] = +{ + [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, + [STR_IDX_MFC] = USBD_STRING_DESC("GigaDevice"), + [STR_IDX_PRODUCT] = USBD_STRING_DESC("nano_midi"), + [STR_IDX_SERIAL] = USBD_STRING_DESC("GD32XXX-3.0.0-7z8x9yer") +}; + +usb_core_driver g_midi_cdc_udev = +{ + .dev = + { + .desc = + { + .dev_desc = (uint8_t *)&device_descriptor, + .config_desc = (uint8_t *)&configuration_descriptor, + .strings = usbd_strings + + } + } +}; + +void midi_cdc_desc_ep_setup(usb_dev *udev) +{ + usbd_ep_setup(udev, &configuration_descriptor.audio.bulk_in_ep_desc.desc_ep); + usbd_ep_setup(udev, &configuration_descriptor.audio.bulk_out_ep_desc.desc_ep); + + usbd_ep_setup(udev, &configuration_descriptor.cdc.end_in); + usbd_ep_setup(udev, &configuration_descriptor.cdc.end_out); + usbd_ep_setup(udev, &configuration_descriptor.cdc.cmd_ep); +} + +void midi_cdc_desc_ep_clear(usb_dev *udev) +{ + usbd_ep_clear(udev, configuration_descriptor.audio.bulk_in_ep_desc.desc_ep.bEndpointAddress); + usbd_ep_clear(udev, configuration_descriptor.audio.bulk_out_ep_desc.desc_ep.bEndpointAddress); + + usbd_ep_clear(udev, configuration_descriptor.cdc.end_in.bEndpointAddress); + usbd_ep_clear(udev, configuration_descriptor.cdc.end_out.bEndpointAddress); + usbd_ep_clear(udev, configuration_descriptor.cdc.cmd_ep.bEndpointAddress); +} diff --git a/firmware/generic/src/drivers/usbfs/midi_cdc_desc.h b/firmware/generic/src/drivers/usbfs/midi_cdc_desc.h new file mode 100644 index 0000000..f868e8b --- /dev/null +++ b/firmware/generic/src/drivers/usbfs/midi_cdc_desc.h @@ -0,0 +1,199 @@ +/* + MIT License + + Copyright (c) 2020 nyannkov + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ +#ifndef __MIDI_CDC_DESC_H__ +#define __MIDI_CDC_DESC_H__ + + +#define CDC_ACM_CMD_PACKET_SIZE 0x0008 // 8 byte +#define CDC_ACM_DATA_PACKET_SIZE 0x0040 // 64 byte +#define AUDIO_MS_PACKET_SIZE 0x0040 // 64 byte + +#pragma pack(1) + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint16_t bcdADC; + uint16_t wTotalLength; + uint8_t bInCollection; + uint8_t baInterfaceNr; +} usb_desc_class_specific_ac_itf;/* 9 byte */ + + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint16_t BcdADC; + uint16_t wTotalLength; +} usb_desc_class_specific_ms_itf;/* 7 byte */ + + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bJackType; + uint8_t bJackID; + uint8_t iJack; +} usb_desc_midi_in_jack_desc; /* 6 byte */ + + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bJackType; + uint8_t bJackID; + uint8_t bNtInputPins; + uint8_t BaSourceID; + uint8_t BaSourcePin; + uint8_t iJack; +} usb_desc_midi_out_jack_desc; /* 9 byte */ + + +typedef struct +{ + usb_desc_ep desc_ep; + uint8_t bRefresh; + uint8_t bSynchAddress; +} usb_desc_ep_audio; /* 9 byte */ + + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bNumEmbMIDIJack; + uint8_t BaAssocJackID; +} usb_desc_class_specific_ms_ep; /* 5 byte */ + + +typedef struct +{ + usb_desc_itf standard_ac_itf; + usb_desc_class_specific_ac_itf class_specific_ac_itf; + usb_desc_itf standard_ms_itf; + usb_desc_class_specific_ms_itf class_specific_ms_itf; + usb_desc_midi_in_jack_desc midi_in_jack_embedded; + usb_desc_midi_in_jack_desc midi_in_jack_external; + usb_desc_midi_out_jack_desc midi_out_jack_embedded; + usb_desc_midi_out_jack_desc midi_out_jack_external; + usb_desc_ep_audio bulk_out_ep_desc; + usb_desc_class_specific_ms_ep class_specific_ms_bulk_out_ep; + usb_desc_ep_audio bulk_in_ep_desc; + usb_desc_class_specific_ms_ep class_specific_ms_bulk_in_ep; +} usb_desc_audio; + + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bFirstInterface; + uint8_t bInterfaceCount; + uint8_t bFunctionClass; + uint8_t bFunctionSubClass; + uint8_t bFunctionProtocol; + uint8_t iFunction; +} usb_desc_iad; /* 8 byte */ + + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint16_t bcdCDC; +} usb_desc_header_func_desc; /* 5 byte */ + + +typedef struct +{ + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmCapabilities; + uint8_t bDataInterface; +} usb_desc_call_mng_func_desc; /* 5 byte */ + + +typedef struct +{ + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmCapabilities; +} usb_desc_acm_func_desc; /* 4 byte */ + + +typedef struct +{ + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bMasterInterface; + uint8_t bSlaveInterface0; +} usb_desc_union_func_desc; /* 5 byte */ + + +typedef struct +{ + usb_desc_itf cdc_cdc_itf; + usb_desc_header_func_desc header_func_desc; + usb_desc_call_mng_func_desc call_mng_func_desc; + usb_desc_acm_func_desc acm_func_desc; + usb_desc_union_func_desc union_func_desc; + usb_desc_ep cmd_ep; + usb_desc_itf cdc_data_itf; + usb_desc_ep end_out; + usb_desc_ep end_in; +} usb_desc_cdc; + + +typedef struct +{ + usb_desc_config config; + usb_desc_iad usb_iad_audio; + usb_desc_audio audio; + usb_desc_iad usb_iad_cdc; + usb_desc_cdc cdc; +} usb_descriptor_configuration_set_struct; + +#pragma pack() + + + +extern usb_core_driver g_midi_cdc_udev; + +extern void midi_cdc_desc_ep_setup(usb_dev *udev); +extern void midi_cdc_desc_ep_clear(usb_dev *udev); + +#endif/*__MIDI_CDC_DESC_H__*/ diff --git a/firmware/generic/src/drivers/usbfs/midiconf.h b/firmware/generic/src/drivers/usbfs/midiconf.h new file mode 100644 index 0000000..d4d9152 --- /dev/null +++ b/firmware/generic/src/drivers/usbfs/midiconf.h @@ -0,0 +1,37 @@ +/* + MIT License + + Copyright (c) 2019 nyannkov + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +#ifndef __MIDICONF_H__ +#define __MIDICONF_H__ + +#include +#include + +#define __WEAK__ __attribute__((weak)) + +#ifndef MAX_SYS_EX_BUF_SIZE +#define MAX_SYS_EX_BUF_SIZE 256 +#endif + +#endif /* __MIDICONF_H__ */ \ No newline at end of file diff --git a/firmware/generic/src/drivers/usbfs/usb_conf.h b/firmware/generic/src/drivers/usbfs/usb_conf.h new file mode 100644 index 0000000..651ba3e --- /dev/null +++ b/firmware/generic/src/drivers/usbfs/usb_conf.h @@ -0,0 +1,75 @@ +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ +#ifndef __USB_CONF_H__ +#define __USB_CONF_H__ + +#include + +#ifdef USE_USB_FS +#define USB_FS_CORE +#endif + +#ifdef USB_FS_CORE + #define RX_FIFO_FS_SIZE 128 + #define TX0_FIFO_FS_SIZE 64 + #define TX1_FIFO_FS_SIZE 128 + #define TX2_FIFO_FS_SIZE 0 + #define TX3_FIFO_FS_SIZE 0 +#endif /* USB_FS_CORE */ + +#define USB_SOF_OUTPUT 1 +#define USB_LOW_POWER 1 + +#if defined ( __GNUC__ ) + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ + +#if defined (__GNUC__) /* GNU Compiler */ + #define __ALIGN_END __attribute__ ((aligned (4))) + #define __ALIGN_BEGIN +#else + #define __ALIGN_END + #if defined (__CC_ARM) /* ARM Compiler */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #elif defined (__TASKING__) /* TASKING Compiler */ + #define __ALIGN_BEGIN __align(4) + #endif /* __CC_ARM */ +#endif /* __GNUC__ */ + + +#endif \ No newline at end of file diff --git a/firmware/generic/src/drivers/usbfs/usb_midi_app.c b/firmware/generic/src/drivers/usbfs/usb_midi_app.c new file mode 100644 index 0000000..7359b86 --- /dev/null +++ b/firmware/generic/src/drivers/usbfs/usb_midi_app.c @@ -0,0 +1,98 @@ +/* + MIT License + + Copyright (c) 2020 nyannkov + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ +#include "usb_midi_app.h" +#include "midi.h" +//#include "mode4_ymf825.h" +//#include "music_box_ymf825.h" +//#include "single_ymz294.h" + + +#include + +#define MAX_MIDI_HANDLE_LIST_COUNT 2 +#define MIDI_HANDLE_FREE 0 +#define MIDI_HANDLE_OCCUPIED 1 + +#define USB_MIDI_APP_ASSERT(cond) + +typedef struct +{ + uint32_t status; + MIDI_Handle_t hMIDI; +} midi_handle_list_t; + +typedef struct _usb_midi_event_packet +{ + uint8_t header; + uint8_t midi[3]; +} usb_midi_event_packet_t; + +typedef struct +{ + MIDI_Handle_t* (*midi_init)(void); + void (*midi_deinit)(MIDI_Handle_t *phMIDI); +} sound_driver_api_t; + +static midi_handle_list_t hmidi_list[MAX_MIDI_HANDLE_LIST_COUNT]; + + +int32_t usb_midi_proc(const uint8_t *mid_msg, size_t len) +{ + gpio_bit_set(GPIOA, GPIO_PIN_1); + if(gpio_input_bit_get(GPIOA, GPIO_PIN_2)){ + gpio_bit_reset(GPIOA, GPIO_PIN_2); + } else{ + gpio_bit_set(GPIOA, GPIO_PIN_2); + } + return 0; +} + + +MIDI_Handle_t *MIDI_Alloc(void) +{ + uint32_t i = 0; + for ( i = 0; i < MAX_MIDI_HANDLE_LIST_COUNT; i++ ) + { + if ( hmidi_list[i].status == MIDI_HANDLE_FREE ) + { + hmidi_list[i].status = MIDI_HANDLE_OCCUPIED; + return &hmidi_list[i].hMIDI; + } + } + return (MIDI_Handle_t * )0; +} + +void MIDI_Free(MIDI_Handle_t *phMIDI) +{ + uint32_t i = 0; + for ( i = 0; i < MAX_MIDI_HANDLE_LIST_COUNT; i++ ) + { + if ( &hmidi_list[i].hMIDI == phMIDI ) + { + hmidi_list[i].status = MIDI_HANDLE_FREE; + break; + } + } +} + diff --git a/firmware/generic/src/drivers/usbfs/usb_midi_app.h b/firmware/generic/src/drivers/usbfs/usb_midi_app.h new file mode 100644 index 0000000..b4dd370 --- /dev/null +++ b/firmware/generic/src/drivers/usbfs/usb_midi_app.h @@ -0,0 +1,43 @@ +/* + MIT License + + Copyright (c) 2020 nyannkov + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ +#ifndef __USB_MIDI_H__ +#define __USB_MIDI_H__ + +#include +#include + +typedef enum +{ + YMF825_SOUND_DRIVER_MODE4 = 0, + YMF825_SOUND_DRIVER_MUSIC_BOX, + NUM_OF_YMF825_SOUND_DRIVER +} ymf825_sound_driver_t; + + +extern void init_usb_midi_app(void); +extern int32_t usb_midi_proc(const uint8_t *mid_msg, size_t len); +extern int32_t switch_ymf825_sound_driver(ymf825_sound_driver_t driver); +extern ymf825_sound_driver_t get_selected_ymf825_sound_driver(void); + +#endif//__USB_MIDI_H__ diff --git a/firmware/generic/src/drivers/usbfs/usbd_conf.h b/firmware/generic/src/drivers/usbfs/usbd_conf.h new file mode 100644 index 0000000..c30e68a --- /dev/null +++ b/firmware/generic/src/drivers/usbfs/usbd_conf.h @@ -0,0 +1,23 @@ +#ifndef __USBD_CONF_H__ +#define __USBD_CONF_H__ + +#include "usb_conf.h" + +#define USBD_CFG_MAX_NUM 1 + + +#define CDC_OUT_EP 0x01U +#define CDC_CMD_EP 0x82U +#define CDC_IN_EP 0x81U + +#define MIDI_OUT_EP 0x02U +#define MIDI_IN_EP 0x83U + +#define AUDIO_AC_ITF_NUMBER 0 +#define AUDIO_MS_ITF_NUMBER 1 +#define CDC_CDC_ITF_NUMBER 2 +#define CDC_DATA_ITF_NUMBER 3 +#define USBD_ITF_MAX_NUM CDC_DATA_ITF_NUMBER + + +#endif//__USBD_CONF_H__ \ No newline at end of file diff --git a/firmware/generic/src/drivers/usbfs/usbd_core.c b/firmware/generic/src/drivers/usbfs/usbd_core.c new file mode 100644 index 0000000..d7a8eae --- /dev/null +++ b/firmware/generic/src/drivers/usbfs/usbd_core.c @@ -0,0 +1,329 @@ +/*! + \file usbd_core.c + \brief USB device mode core functions + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "../Include/usbd_core.h" +#include "../Include/drv_usb_hw.h" + +/* endpoint type */ +const uint32_t ep_type[] = { + [USB_EP_ATTR_CTL] = USB_EPTYPE_CTRL, + [USB_EP_ATTR_BULK] = USB_EPTYPE_BULK, + [USB_EP_ATTR_INT] = USB_EPTYPE_INTR, + [USB_EP_ATTR_ISO] = USB_EPTYPE_ISOC +}; + +/*! + \brief initailizes the USB device-mode stack and load the class driver + \param[in] udev: pointer to USB core instance + \param[in] core: usb core type + \param[in] class_core: class driver + \param[out] none + \retval none +*/ +void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_class_core *class_core) +{ + /* device descriptor, class and user callbacks */ + udev->dev.class_core = class_core; + + /* configure USB capabilites */ + usb_basic_init (&udev->bp, &udev->regs, core); + + /* initailizes the USB core*/ + usb_core_init (udev->bp, &udev->regs); + + /* set device disconnect */ + usbd_disconnect (udev); + + /* initailizes device mode */ + usb_devcore_init (udev); + + /* set device connect */ + usbd_connect (udev); + + udev->dev.cur_status = USBD_DEFAULT; +} + +/*! + \brief endpoint initialization + \param[in] udev: pointer to USB core instance + \param[in] ep_desc: pointer to endpoint descriptor + \param[out] none + \retval none +*/ +uint32_t usbd_ep_setup (usb_core_driver *udev, const usb_desc_ep *ep_desc) +{ + usb_transc *transc; + + uint8_t ep_addr = ep_desc->bEndpointAddress; + uint8_t max_len = ep_desc->wMaxPacketSize; + + /* set endpoint direction */ + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + + transc->ep_addr.dir = 1U; + } else { + transc = &udev->dev.transc_out[ep_addr]; + + transc->ep_addr.dir = 0U; + } + + transc->ep_addr.num = EP_ID(ep_addr); + transc->max_len = max_len; + transc->ep_type = ep_type[ep_desc->bmAttributes & USB_EPTYPE_MASK]; + + /* active USB endpoint function */ + usb_transc_active (udev, transc); + + return 0; +} + +/*! + \brief configure the endpoint when it is disabled + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_clear (usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc; + + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + /* deactive USB endpoint function */ + usb_transc_deactivate (udev, transc); + + return 0; +} + + +/*! + \brief endpoint prepare to receive data + \param[in] udev: pointer to usb core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[in] pbuf: user buffer address pointer + \param[in] len: buffer length + \param[out] none + \retval none +*/ +uint32_t usbd_ep_recev (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len) +{ + usb_transc *transc = &udev->dev.transc_out[EP_ID(ep_addr)]; + + /* setup the transfer */ + transc->xfer_buf = pbuf; + transc->xfer_len = len; + transc->xfer_count = 0; + + if (USB_USE_DMA == udev->bp.transfer_mode) { + transc->dma_addr = (uint32_t)pbuf; + } + + /* start the transfer */ + usb_transc_outxfer (udev, transc); + + return 0; +} + +/*! + \brief endpoint prepare to transmit data + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[in] pbuf: transmit buffer address pointer + \param[in] len: buffer length + \param[out] none + \retval none +*/ +uint32_t usbd_ep_send (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len) +{ + usb_transc *transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + + /* setup the transfer */ + transc->xfer_buf = pbuf; + transc->xfer_len = len; + transc->xfer_count = 0; + + if (USB_USE_DMA == udev->bp.transfer_mode) { + transc->dma_addr = (uint32_t)pbuf; + } + + /* start the transfer */ + usb_transc_inxfer (udev, transc); + + return 0; +} + +/*! + \brief set an endpoint to STALL status + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_stall (usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc = NULL; + + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + transc->ep_stall = 1; + + usb_transc_stall (udev, transc); + + return (0); +} + +/*! + \brief clear endpoint STALLed status + \param[in] udev: pointer to usb core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_stall_clear (usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc = NULL; + + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + transc->ep_stall = 0; + + usb_transc_clrstall (udev, transc); + + return (0); +} + +/*! + \brief flush the endpoint FIFOs + \param[in] udev: pointer to usb core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_fifo_flush (usb_core_driver *udev, uint8_t ep_addr) +{ + if (EP_DIR(ep_addr)) { + usb_txfifo_flush (&udev->regs, EP_ID(ep_addr)); + } else { + usb_rxfifo_flush (&udev->regs); + } + + return (0); +} + +/*! + \brief set USB device address + \param[in] udev: pointer to USB core instance + \param[in] addr: device address to set + \param[out] none + \retval none +*/ +void usbd_addr_set (usb_core_driver *udev, uint8_t addr) +{ + usb_devaddr_set(udev, addr); +} + +/*! + \brief get the received data length + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval USB device operation cur_status +*/ +uint16_t usbd_rxcount_get (usb_core_driver *udev, uint8_t ep_num) +{ + return udev->dev.transc_out[ep_num].xfer_count; +} + +/*! + \brief device connect + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void usbd_connect (usb_core_driver *udev) +{ +#ifndef USE_OTG_MODE + /* connect device */ + usb_dev_connect (udev); + usb_mdelay(3); + +#endif /* USE_OTG_MODE */ +} + +/*! + \brief device disconnect + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void usbd_disconnect (usb_core_driver *udev) +{ +#ifndef USE_OTG_MODE + /* disconnect device for 3ms */ + usb_dev_disconnect (udev); + usb_mdelay(3); +#endif /* USE_OTG_MODE */ +} diff --git a/firmware/generic/src/drivers/usbfs/usbd_core.h b/firmware/generic/src/drivers/usbfs/usbd_core.h new file mode 100644 index 0000000..c4ec47a --- /dev/null +++ b/firmware/generic/src/drivers/usbfs/usbd_core.h @@ -0,0 +1,95 @@ +/*! + \file usbd_core.h + \brief USB device mode core functions protype + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_CORE_H +#define __USBD_CORE_H + + +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +typedef enum +{ + USBD_OK = 0, /*!< status OK */ + USBD_BUSY, /*!< status busy */ + USBD_FAIL, /*!< status fail */ +} usbd_status; + +enum _usbd_status { + USBD_DEFAULT = 1, /*!< default status */ + USBD_ADDRESSED = 2, /*!< address send status */ + USBD_CONFIGURED = 3, /*!< configured status */ + USBD_SUSPENDED = 4 /*!< suspended status */ +}; + +/* function declarations */ + +/* device connect */ +void usbd_connect (usb_core_driver *udev); + +/* device disconnect */ +void usbd_disconnect (usb_core_driver *udev); + +/* set USB device address */ +void usbd_addr_set (usb_core_driver *udev, uint8_t addr); + +/* initailizes the USB device-mode stack and load the class driver */ +void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_class_core *class_core); + +/* endpoint initialization */ +uint32_t usbd_ep_setup (usb_core_driver *udev, const usb_desc_ep *ep_desc); + +/* configure the endpoint when it is disabled */ +uint32_t usbd_ep_clear (usb_core_driver *udev, uint8_t ep_addr); + +/* endpoint prepare to receive data */ +uint32_t usbd_ep_recev (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len); + +/* endpoint prepare to transmit data */ +uint32_t usbd_ep_send (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len); + +/* set an endpoint to STALL status */ +uint32_t usbd_ep_stall (usb_core_driver *udev, uint8_t ep_addr); + +/* clear endpoint STALLed status */ +uint32_t usbd_ep_stall_clear (usb_core_driver *udev, uint8_t ep_addr); + +/* flush the endpoint FIFOs */ +uint32_t usbd_fifo_flush (usb_core_driver *udev, uint8_t ep_addr); + +/* get the received data length */ +uint16_t usbd_rxcount_get (usb_core_driver *udev, uint8_t ep_num); + +#endif /* __USBD_CORE_H */ + diff --git a/firmware/generic/src/main.cpp b/firmware/generic/src/main.cpp new file mode 100644 index 0000000..c123a20 --- /dev/null +++ b/firmware/generic/src/main.cpp @@ -0,0 +1,918 @@ +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| + +// *********************************************************************************** +// LEET modular - a versatile, easy to build, affordable and powerful eurorack module! +// *********************************************************************************** + +// todo: +// * integrate midi to cv code +// * clean up code +// * implement s&h +// * implement vca, attenuverter etc +// * transparent image for dual color intro +// * rainbow intro? +// * why is one ouput affecting the other in calibration manual cv? (variations in AD or vcc -> pots?) +// * move generated contents (python scripts) to external files (with .h) +// * improve potentiometer calibration +// * design and print dual attenuated output (with improved clip) + +// done: +// * implement vcf and a few different filters +// * implement primitive delay +// * add dead zone for pot controling ammount of modulation +// * add logo for playback +// * invert tempo for playback +// * fix levels for am (enabling folding) +// * color code cv and pot levels +// * fix voltage levels for osc, adsr etc (not 20VPP) +// * implement adsr +// * add boot image +// * improve vco implementation (new menu with am,fm etc) +// * change AD range (amplification to allow 16 steps between each note (10V @1920 instead of 2048)) +// * replace qLut with function (divide AD to get index) +// * switch to float xStep? (incl LUTs) +// * add quantization for cv-in +// * add pulsewidth for squarewave +// * add icons to modes +// * clean up code in modules +// * implement tft menu system with encoder interrupt +// * implement potentiometer filtering (running average) +// * replace waveform with 16 bit position (0-65534) +// * implement reliable rotation encoder support +// * implement ADC DMA reading +// * implement tmrIRQ for playback @ 44.1kHz +// * update spi and display to support 240x240 tft with st7789 driver +// * verify ADC resolution +// * optimize display update (remove flickering) + +// note: calibration values for unconnected input (potentiometer calibration): 3238 // target 2473 + +// #define pcb_version 0 // the first 3dpcb version +#define pcb_version 1 // the first pcb version, marked rev 1 (menu and P2,P3 direction changed) + +#include +extern "C" +{ +#include "drivers\SysTick.h" +#include "drivers\led.h" +#include "drivers\display.h" +#include "drivers\spi.h" +#include "drivers\timer.h" +#include "drivers\encoder.h" +#include "drivers\adc.h" +#include "drivers\scope.h" +#include "module_vco.h" +#include "module_noise.h" +#include "module_vcf.h" +#include "module_adsr.h" +#include "module_delay.h" +#include "gd32vf103.h" + extern "C" const uint8_t font[1520]; + extern "C" const float freq[2113]; +} + +timer T; +led LED; +SysTick stk; +display Display; +spi SPI; +encoder enc; +adc ADC; +module_vco vco; +module_noise noise; +module_vcf vcf; +module_adsr adsr; +module_delay delay; +scope ch0(RGBToWord(0xff, 0x00, 0xff)); +scope ch1(RGBToWord(0x00, 0xff, 0xff)); +scope ch0old(RGBToWord(0x00, 0x00, 0x00)); +scope ch1old(RGBToWord(0x00, 0x00, 0x00)); + +// menu structure generated by python script: +const char *menuTxt[] = {"OSC", "< back", "sine am", "sine add", "sine fm", "square am", "square add", "square fm", "square pw", "square 2x", "square 3x", "triangle am", "triangle add", "triangle fm", "triangle saw", "triangle 2x", "triangle 3x", "quantize", "cvout", "Noise", "LFO", "< back", "LFO sine", "LFO square", "LFO triangle", "VCF", "< back", "2 pole v1", "2 pole v2", "4 pole", "test", "VCA", "SnH", "Envelope", " 127)) +// uint8_t moduleMode = mode_triangle_saw; // function of module selected by menu (fixed menu positions > 127)) +// uint8_t moduleMode = mode_ADSR; // function of module selected by menu (fixed menu positions > 127)) +// uint8_t moduleMode = mode_4_pole; // function of module selected by menu (fixed menu positions > 127)) +// uint8_t moduleMode = mode_Delay; // function of module selected by menu (fixed menu positions > 127)) + +volatile int dispPos = 0; // counter for scope column (update screen when dispPos == 240) +uint8_t menuPos = 0; // current menu position (< 127) +uint8_t menuUpd = 1; // signals if menu was updated (=>redraw display) +float phaseC = 0; // phaseCount | stepsize within one period (0-65535). frequenzy = xStep * 44100 / (2*65536) +uint8_t quantized = 0; // quantize CV input of module? +uint8_t cvOut = 0; // use dac0 as cv for vco? +uint8_t scopeTrig = 0; // flag to init scope sampling + +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| + +void rcu_config(void) +{ + rcu_periph_clock_enable(RCU_AF); // GPIO IRQ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_ADC0); + rcu_periph_clock_enable(RCU_DAC); + rcu_periph_clock_enable(RCU_DMA0); + rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV8); // ADC clock = 108MHz / 8 = 13.5MHz(14MHz max.) +} + +void gpio_config(void) +{ + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_0); // ADC ch0 + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_3); // ADC ch1 + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_6); // ADC pot UR + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_7); // ADC pot LR + gpio_init(GPIOB, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_0); // ADC pot LL + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_4); // DAC ch0 + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_5); // DAC ch1 + gpio_init(GPIOB, GPIO_MODE_IPU, GPIO_OSPEED_50MHZ, GPIO_PIN_5); // rotary enc A + gpio_init(GPIOB, GPIO_MODE_IPU, GPIO_OSPEED_50MHZ, GPIO_PIN_6); // rotary enc B + gpio_init(GPIOB, GPIO_MODE_IPU, GPIO_OSPEED_50MHZ, GPIO_PIN_4); // rotary enc C + gpio_init(GPIOC, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13); // red LED + gpio_init(GPIOA, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_1); // green LED + gpio_init(GPIOA, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2); // blue LED +} + +void dma_config(void) +{ + /* ADC_DMA_channel configuration */ + dma_parameter_struct dma_data_parameter; + /* ADC DMA_channel configuration */ + dma_deinit(DMA0, DMA_CH0); + /* initialize DMA single data mode */ + dma_data_parameter.periph_addr = (uint32_t)(&ADC_RDATA(ADC0)); + dma_data_parameter.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_data_parameter.memory_addr = (uint32_t)(&ADC.anRaw); + dma_data_parameter.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_data_parameter.periph_width = DMA_PERIPHERAL_WIDTH_16BIT; + dma_data_parameter.memory_width = DMA_MEMORY_WIDTH_16BIT; + dma_data_parameter.direction = DMA_PERIPHERAL_TO_MEMORY; + dma_data_parameter.number = 5; + dma_data_parameter.priority = DMA_PRIORITY_HIGH; + dma_init(DMA0, DMA_CH0, &dma_data_parameter); + dma_circulation_enable(DMA0, DMA_CH0); + /* enable DMA channel */ + dma_channel_enable(DMA0, DMA_CH0); +} + +void initADC() +{ + /* reset ADC */ + adc_deinit(ADC0); + /* ADC mode config */ + adc_mode_config(ADC_MODE_FREE); // ADC0 and ADC1 work independently + /* ADC data alignment config */ + adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT); + /* Configure word length */ + adc_resolution_config(ADC0, ADC_RESOLUTION_12B); + /* ADC channel length config */ + adc_channel_length_config(ADC0, ADC_REGULAR_CHANNEL, 5); + adc_regular_channel_config(ADC0, 0, ADC_CHANNEL_0, ADC_SAMPLETIME_13POINT5); // ADC left 41.4+12.5=54 cycles =5uS *5=20us => 50.1Hz + adc_regular_channel_config(ADC0, 1, ADC_CHANNEL_3, ADC_SAMPLETIME_13POINT5); // ADC right + adc_regular_channel_config(ADC0, 2, ADC_CHANNEL_6, ADC_SAMPLETIME_13POINT5); // pot0 (UR) + adc_regular_channel_config(ADC0, 3, ADC_CHANNEL_7, ADC_SAMPLETIME_13POINT5); // pot1 (LR) + adc_regular_channel_config(ADC0, 4, ADC_CHANNEL_8, ADC_SAMPLETIME_13POINT5); // pot2 (LL) + /* ADC trigger config */ + adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_NONE); // software trigger + /* ADC external trigger enable */ + adc_external_trigger_config(ADC0, ADC_REGULAR_CHANNEL, ENABLE); + /* ADC discontinuous mode */ + adc_discontinuous_mode_config(ADC0, ADC_REGULAR_CHANNEL, 5); // should it be 4? + /* enable ADC interface */ + adc_enable(ADC0); + stk.delay(1); + /* ADC calibration and reset calibration */ + adc_calibration_enable(ADC0); + stk.delay(1); + /* ADC DMA function enable */ + adc_dma_mode_enable(ADC0); +} + +void initDAC(void) +{ + dac_deinit(); + dac_trigger_source_config(DAC0, DAC_TRIGGER_SOFTWARE); + dac_trigger_enable(DAC0); + dac_wave_mode_config(DAC0, DAC_WAVE_DISABLE); + dac_output_buffer_enable(DAC0); + dac_enable(DAC0); + + dac_trigger_source_config(DAC1, DAC_TRIGGER_SOFTWARE); + dac_trigger_enable(DAC1); + dac_wave_mode_config(DAC1, DAC_WAVE_DISABLE); + dac_output_buffer_enable(DAC1); + dac_enable(DAC1); +} + +void initUART() +{ + /* enable USART clock */ + rcu_periph_clock_enable(RCU_USART0); + /* connect port to USARTx_Tx */ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9); + /* USART configure */ + usart_deinit(USART0); + usart_baudrate_set(USART0, 9600U); + usart_word_length_set(USART0, USART_WL_8BIT); + usart_stop_bit_set(USART0, USART_STB_1BIT); + usart_parity_config(USART0, USART_PM_NONE); + usart_hardware_flow_rts_config(USART0, USART_RTS_DISABLE); + usart_hardware_flow_cts_config(USART0, USART_CTS_DISABLE); + usart_transmit_config(USART0, USART_TRANSMIT_ENABLE); + usart_enable(USART0); +} + +float ad2phase(uint16_t in) +{ + float xTmp; + if (in < 1472) // below -3V + xTmp = 24.135547645748918; + else if (in > 3584) // above 8V + xTmp = 49429.601578493784; + else + { + if (quantized == 0) + xTmp = freq[in - 1472]; + else + { + uint16_t q = (in - 1472 + 8) >> 4; // add 16/2 to quantize between notes + xTmp = freq[q << 4]; + } + } + return (xTmp); +} + +void addScope(uint16_t c0, uint16_t c1, uint8_t trig) +{ + if (dispPos < 240) + { + if (dispPos > 0 || trig == 1) + { + ch0.insert((4095 - c0) / 64); + ch1.insert((4095 - c1) / 64); + dispPos++; + } + } +} + +void dac_out(uint16_t d0, uint16_t d1) +{ + dac_data_set(DAC0, DAC_ALIGN_12B_R, 4095 - d0); // inverted due to inverting op amp + dac_data_set(DAC1, DAC_ALIGN_12B_R, 4095 - d1); // inverted due to inverting op amp + dac_software_trigger_enable(DAC0); + dac_software_trigger_enable(DAC1); +} + +int16_t fold(int16_t tmp) +{ + do + { + if (tmp < 1088) + tmp = (1088 * 2 - tmp); + if (tmp > 3008) + tmp = (3008 * 2 - tmp); + } while (tmp < 1088 || tmp > 3008); + return (tmp); +} + +uint16_t deadzone(uint16_t tmp) +{ + if (tmp < 255) // within? + return (0); // ..yes - return zero + else // .. no + return (tmp - 255); // return value - deadzone +} + +float getPhase() +{ + uint8_t p_note; + uint16_t p_octave; + p_note = deadzone(ADC.anAvg[2]) >> 4; // add deadzone, one octave is 192 AD steps (1V). (4096-1024/16)=192 + p_octave = (ADC.anAvg[4] >> 9) * 192; // 4096/512 => 8 octaves + phaseC = ad2phase(ADC.anAvg[0] + p_octave - (192 << 1) + p_note); // convert CV to logaritmic scale + return (phaseC); +} + +/* potentiometer and I/O mapping + R P2 + P4 P3 + C0 C1 + D0 D1 +*/ + +void OnTimer() +{ + +#if (pcb_version == 1) + ADC.anRaw[2] = 4096 - ADC.anRaw[2]; // pot inverted in this pcb version + ADC.anRaw[3] = 4096 - ADC.anRaw[3]; // pot inverted in this pcb version +#endif + + // static float x; + static uint8_t songPos; // position in song + static uint16_t tCount; // temp for song + static uint8_t prevMode; // + int16_t tmp = 0; + uint32_t cv2; + if (moduleMode == mode_quantize) + { + quantized ^= 1; + moduleMode = prevMode; + } + if (moduleMode == mode_cvout) + { + cvOut ^= 1; + moduleMode = prevMode; + } + + //-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| + switch (moduleMode) + { + case mode_sine_am: // sine (ampitude modulation) + cv2 = ((ADC.anRaw[1] << 2) * ADC.anAvg[3] >> 11); // 0-8192. pot2 (bottom right) sets level for CV2 that attenuates or amplifies amplitude + tmp = 2048 + ((int(vco.sine(getPhase()) - 2048) * cv2) >> 12); // get level from position + tmp = fold(tmp); // fold if outside range + dac_out(cvOut ? ADC.anRaw[0] : tmp, tmp); // output level on DAC1 & DAC0 if ! cvOut (else CV out on DAC0) + addScope(ADC.anRaw[1], tmp * 2 - 2048, vco.phaseTrig); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_sine_add: // sine (sum: in1 is added to the oscillator) + cv2 = ((ADC.anRaw[1] << 2) * ADC.anAvg[3] >> 11); // 0-8192. pot2 (bottom right) sets level for CV2 that attenuates or amplifies amplitude + tmp = (int(vco.sine(getPhase()) + cv2) >> 1); // get level from position + tmp = fold(tmp); // fold if outside range + dac_out(cvOut ? ADC.anRaw[0] : tmp, tmp); // output level on DAC1 & DAC0 if ! cvOut (else CV out on DAC0) + addScope(ADC.anRaw[1], tmp * 2 - 2048, vco.phaseTrig); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_sine_fm: // sine (frequency modulation) + cv2 = (ADC.anRaw[1] * ADC.anAvg[3] >> 12); // 12+12-13=11 (0-2048). pot2 (bottom right) sets level for CV2 that modulates the frequency + tmp = int(vco.sine(getPhase() + cv2 - 1024)); // get level from position (1088-3008 => -5V to +5V) + tmp = fold(tmp); // fold if outside range + dac_out(cvOut ? ADC.anRaw[0] : tmp, tmp); // output level on DAC1 & DAC0 if ! cvOut (else CV out on DAC0) + addScope(ADC.anRaw[1], tmp * 2 - 2048, vco.phaseTrig); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_square_am: // square (amplitude modulation) + cv2 = (ADC.anRaw[1] * ADC.anAvg[3] >> 11); // 0-8192. pot2 (bottom right) sets level for CV2 that attenuates or amplifies amplitude + tmp = 2048 + ((int(vco.square(getPhase(), 32768) - 2048) * cv2) >> 12); // get level from position + dac_out(cvOut ? ADC.anRaw[0] : tmp, tmp); // output level on DAC1 & DAC0 if ! cvOut (else CV out on DAC0) + addScope(ADC.anRaw[1], tmp * 2 - 2048, vco.phaseTrig); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_square_add: // square (sum: in1 is added to the oscillator) + cv2 = (ADC.anRaw[1] * ADC.anAvg[3] >> 11); // 0-8192. pot2 (bottom right) sets level for CV2 that attenuates or amplifies amplitude + tmp = (int(vco.square(getPhase(), 32768) + cv2) >> 1); // get level from position + dac_out(cvOut ? ADC.anRaw[0] : tmp, tmp); // output level on DAC1 & DAC0 if ! cvOut (else CV out on DAC0) + addScope(ADC.anRaw[1], tmp * 2 - 2048, vco.phaseTrig); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_square_fm: // square (frequency modulation) + cv2 = (ADC.anRaw[1] * ADC.anAvg[3] >> 12); // 12+12-8=16 (0-65535). pot2 (bottom right) sets level for CV2 that modulates the frequency + tmp = vco.square(getPhase() + cv2, 32768); // get level from position (50% dyuty cycle) + dac_out(cvOut ? ADC.anRaw[0] : tmp, tmp); // output level on DAC1 & DAC0 if ! cvOut (else CV out on DAC0) + addScope(ADC.anRaw[1], tmp * 2 - 2048, vco.phaseTrig); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_square_pw: // square (pulsewidth modulation) + cv2 = (ADC.anRaw[1] * ADC.anAvg[3] >> 8); // 12+12-8=16 (0-65535). pot2 (bottom right) sets level for CV2 that modulates the pulse width + tmp = vco.square(getPhase(), cv2); // get level from position (50% dyuty cycle) + dac_out(cvOut ? ADC.anRaw[0] : tmp, tmp); // output level on DAC1 & DAC0 if ! cvOut (else CV out on DAC0) + addScope(ADC.anRaw[1], tmp * 2 - 2048, vco.phaseTrig); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_square_2x: // 2 slightly detuned square oscillators + cv2 = (ADC.anRaw[1] * ADC.anAvg[3] >> 18); // 12+12-8=16 (0-65535). pot2 (bottom right) sets level for CV2 that modulates the pulse width + tmp = vco.square2x(getPhase(), cv2); // get level from position (50% dyuty cycle) + dac_out(cvOut ? ADC.anRaw[0] : tmp, tmp); // output level on DAC1 & DAC0 if ! cvOut (else CV out on DAC0) + addScope(ADC.anRaw[1], tmp * 2 - 2048, vco.phaseTrig); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_square_3x: // 3 slightly detuned square oscillators + cv2 = (ADC.anRaw[1] * ADC.anAvg[3] >> 17); // 12+12-8=16 (0-65535). pot2 (bottom right) sets level for CV2 that modulates the pulse width + tmp = vco.square3x(getPhase(), cv2); // get level from position (50% dyuty cycle) + dac_out(cvOut ? ADC.anRaw[0] : tmp, tmp); // output level on DAC1 & DAC0 if ! cvOut (else CV out on DAC0) + addScope(ADC.anRaw[1], tmp * 2 - 2048, vco.phaseTrig); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_triangle_am: // triangle (amplitude modulation) + cv2 = ((ADC.anRaw[1] << 2) * ADC.anAvg[3] >> 11); // 0-8192. pot2 (bottom right) sets level for CV2 that attenuates or amplifies amplitude + tmp = 2048 + ((int(vco.triangle(getPhase(), 32768) - 2048) * cv2) >> 12); // get level from position + tmp = fold(tmp); // fold if outside range + dac_out(cvOut ? ADC.anRaw[0] : tmp, tmp); // output level on DAC1 & DAC0 if ! cvOut (else CV out on DAC0) + addScope(ADC.anRaw[1], tmp * 2 - 2048, vco.phaseTrig); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_triangle_add: // triangle (sum: in1 is added to the oscillator) + cv2 = ((ADC.anRaw[1] << 2) * ADC.anAvg[3] >> 11); // 0-8192. pot2 (bottom right) sets level for CV2 that attenuates or amplifies amplitude + tmp = (int(vco.triangle(getPhase(), 32768) + cv2) >> 1); // get level from position + tmp = fold(tmp); // fold if outside range + dac_out(cvOut ? ADC.anRaw[0] : tmp, tmp); // output level on DAC1 & DAC0 if ! cvOut (else CV out on DAC0) + addScope(ADC.anRaw[1], tmp * 2 - 2048, vco.phaseTrig); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_triangle_fm: // triangle (frequency modulation) + cv2 = (ADC.anRaw[1] * ADC.anAvg[3] >> 8); // 12+12-8=16 (0-65535). pot2 (bottom right) sets level for CV2 that modulates the frequency + tmp = vco.triangle(getPhase() + cv2, 32768); // get level from position (50% dyuty cycle) + dac_out(cvOut ? ADC.anRaw[0] : tmp, tmp); // output level on DAC1 & DAC0 if ! cvOut (else CV out on DAC0) + addScope(ADC.anRaw[1], tmp * 2 - 2048, vco.phaseTrig); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_triangle_saw: // triangle (shape modulation) + cv2 = (ADC.anRaw[1] * ADC.anAvg[3] >> 8); // 12+12-8=16 (0-65535). pot2 (bottom right) sets level for CV2 that modulates the pulse width + if (cv2 > 32767) // prevent wrap around + cv2 = 32767; // .. + cv2 = cv2 * 2; // double value to get full range without modulation signal (pot only) + tmp = vco.triangle(getPhase(), cv2); // get level from position (50% dyuty cycle) + dac_out(cvOut ? ADC.anRaw[0] : tmp, tmp); // output level on DAC1 & DAC0 if ! cvOut (else CV out on DAC0) + addScope(ADC.anRaw[1], tmp * 2 - 2048, vco.phaseTrig); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_triangle_2x: // 2 slightly detuned triangle oscillators + cv2 = (ADC.anRaw[1] * ADC.anAvg[3] >> 18); // 0-256. pot2 (bottom right) sets level for CV2 that attenuates or amplifies amplitude + tmp = vco.triangle2x(getPhase(), cv2); // get level from position + dac_out(cvOut ? ADC.anRaw[0] : tmp, tmp); // output level on DAC1 & DAC0 if ! cvOut (else CV out on DAC0) + addScope(ADC.anRaw[1], tmp * 2 - 2048, vco.phaseTrig); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_triangle_3x: // 3 slightly detuned triangle oscillators + cv2 = (ADC.anRaw[1] * ADC.anAvg[3] >> 17); // 0-256. pot2 (bottom right) sets level for CV2 that attenuates or amplifies amplitude + tmp = vco.triangle3x(getPhase(), cv2); // get level from position + dac_out(cvOut ? ADC.anRaw[0] : tmp, tmp); // output level on DAC1 & DAC0 if ! cvOut (else CV out on DAC0) + addScope(ADC.anRaw[1], tmp * 2 - 2048, vco.phaseTrig); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_Noise: // white noise generator (PRNG) + cv2 = (ADC.anRaw[0] * ADC.anAvg[4] >> 13); // pot2 (bottom right) sets level for CV2 that attenuates or amplifies amplitude + tmp = noise.prng(cv2); // get level from position + dac_out(cvOut ? ADC.anRaw[0] : tmp, tmp); // output level on DAC1 & DAC0 if ! cvOut (else CV out on DAC0) + addScope(ADC.anRaw[1], tmp * 2 - 2048, 1); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_LFO_sine: // LFO sine + cv2 = ((ADC.anRaw[1] << 2) * ADC.anAvg[3] >> 11); // 0-8192. pot2 (bottom right) sets level for CV2 that attenuates or amplifies amplitude + tmp = 2048 + ((int(vco.sine(getPhase() / 512) - 2048) * cv2) >> 12); // get level from position + tmp = fold(tmp); // fold if outside range + dac_out(tmp, tmp); // output level on DAC0 & DAC1 + addScope(ADC.anRaw[1], tmp * 2 - 2048, 1); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_LFO_square: // LFO square + tmp = vco.square(getPhase() / 512, ADC.anAvg[3] << 4); // get level from position + dac_out(tmp, tmp); // output level on DAC0 & DAC1 + addScope(ADC.anRaw[1], tmp * 2 - 2048, 1); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_LFO_triangle: // LFO triangle + tmp = vco.triangle(getPhase() / 512, ADC.anAvg[3] << 4); // get level from position + dac_out(tmp, tmp); // output level on DAC0 & DAC1 + addScope(ADC.anRaw[1], tmp * 2 - 2048, 1); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_4_pole: // VCF (Voltage Controled Filter) + tmp = vcf.r4pole1(ADC.anRaw[0], ADC.anAvg[4], ADC.anAvg[3]); // sample, cutoff, resonance + dac_out(tmp, tmp); // output level on DAC0 & DAC1 + addScope(ADC.anRaw[0], tmp, vcf.phaseTrig); // store levels in scope buffer + break; + + case mode_2_pole_v1: // VCF (Voltage Controled Filter) + tmp = vcf.r2pole1(ADC.anRaw[0], ADC.anAvg[4], ADC.anAvg[3]); // sample, cutoff, resonance + dac_out(tmp, tmp); // output level on DAC0 & DAC1 + addScope(ADC.anRaw[0], tmp, vcf.phaseTrig); // store levels in scope buffer + break; + + case mode_2_pole_v2: // VCF (Voltage Controled Filter) + tmp = vcf.r2pole2(ADC.anRaw[0], ADC.anAvg[4], ADC.anAvg[3]); // sample, cutoff, resonance + dac_out(tmp, tmp); // output level on DAC0 & DAC1 + addScope(ADC.anRaw[0], tmp, vcf.phaseTrig); // store levels in scope buffer + break; + + case mode_test: // VCF (Voltage Controled Filter) + tmp = vcf.test(ADC.anRaw[0], ADC.anAvg[4], ADC.anAvg[3]); // sample, cutoff, resonance + dac_out(tmp, tmp); // output level on DAC0 & DAC1 + addScope(ADC.anRaw[0], tmp, vcf.phaseTrig); // store levels in scope buffer + break; + + case mode_VCA: // VCA (Voltage Controled Amplifier) + cv2 = ((ADC.anRaw[0] * ADC.anRaw[1] * ADC.anAvg[3]) >> 21); // pot2 (bottom right) sets level for CV2 that attenuates or amplifies amplitude + cv2 += (ADC.anAvg[2] >> 1) - 2048; // add offset + dac_out(cv2, cv2); // output level on DAC0 & DAC1 + addScope(ADC.anRaw[0], cv2, 1); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_SnH: // SnH (Sample and Hold) + tmp = vcf.test(ADC.anRaw[0], ADC.anAvg[4], ADC.anAvg[3]); // sample, cutoff, resonance + dac_out(tmp, tmp); // output level on DAC0 & DAC1 + addScope(ADC.anRaw[0], tmp * 2 - 2048, 1); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_ADSR: // adsr + tmp = adsr.int_adsr(ADC.anRaw[0], ADC.anAvg[2] << 1, ADC.anAvg[4] << 1, ADC.anAvg[3] << 2, 0); // trig, A,D,R,!S + cv2 = 2048 + (((tmp - 2048) * (ADC.anRaw[1] - 2048)) >> 9); // + dac_out(tmp, cv2); // output level on DAC0 & DAC1 + break; + + case mode_ADR: // adsr + tmp = adsr.int_adsr(ADC.anRaw[0], ADC.anAvg[2] << 1, ADC.anAvg[4] << 1, ADC.anAvg[3] << 2, 1); // trig, A,D,R,!S + cv2 = 2048 + (((tmp - 2048) * (ADC.anRaw[1] - 2048)) >> 9); // + dac_out(tmp, cv2); // output level on DAC0 & DAC1 + break; + + case mode_Delay: // Delay + tmp = delay.delay(ADC.anRaw[0], ADC.anAvg[4], ADC.anAvg[3]); // sample, mix, length + dac_out(tmp, tmp); // output level on DAC0 & DAC1 + addScope(ADC.anRaw[0], tmp * 2 - 2048, 1); // store levels in scope buffer (amplifies oscillator output 2x) + break; + + case mode_CV_Play: + tCount++; + if (tCount < (4095 - ADC.anAvg[2]) * 5) // genereate trig signal (50% duty) + cv2 = 3008; // 5V trig signal (> 3.3V threshold) + else // no trig + cv2 = 2048; // 0V + if (tCount > (4095 - ADC.anAvg[2]) * 10) // playback speed / tempo + { + tCount = 0; + songPos++; + if (songPos >= 48) + songPos = 0; + } + tmp = song[songPos]; // add pot + quantization? + dac_out(tmp, cv2); // output level on DAC0 & DAC1 + phaseC = 0; // DC => 0Hz + addScope(tmp, cv2, tCount ^ 1); // store levels in scope buffer + break; + + case mode_out_minus10: // callibrate -10V + dac_out(128, 128); // 3840*(-10+10)/20+128 = 128 + phaseC = 0; // DC => 0Hz + addScope(ADC.anRaw[1], tmp, 1); // store levels in scope buffer + break; + + case mode_out_0V: // callibrate 0V + dac_out(2048, 2048); // 3840*(0+10)/20+128 = 2048 + phaseC = 0; // DC => 0Hz + addScope(ADC.anRaw[1], tmp, 1); // store levels in scope buffer + break; + + case mode_out_3V3: // callibrate 3V3 + dac_out(2682, 2682); // 3840*(3.3+10)/20+128 = 2682 + phaseC = 0; // DC => 0Hz + addScope(ADC.anRaw[1], tmp, 1); // store levels in scope buffer + break; + + case mode_out_10V: // callibrate 10V + dac_out(3968, 3968); // 3840*(10+10)/20+128 = 3968 + phaseC = 0; // DC => 0Hz + addScope(ADC.anRaw[1], tmp, 1); // store levels in scope buffer + break; + + case mode_in1_to_out1: // calibrate input (connect out to in and match triangle waveform) + phaseC = 450; // + tmp = vco.triangle(phaseC, ADC.anAvg[3] << 4); // triangle waveform (get level from position) + dac_out(tmp, tmp); // output level on DAC0 & DAC1 + addScope(ADC.anRaw[0] * 2 - 2048, tmp * 2 - 2048, vco.phaseTrig); // store levels in scope buffer + break; + + case mode_in2_to_out1: // calibrate input (connect out to in and match triangle waveform) + phaseC = 450; // + tmp = vco.triangle(phaseC, ADC.anAvg[3] << 4); // triangle waveform (get level from position) + dac_out(tmp, tmp); // output level on DAC0 & DAC1 + addScope(ADC.anRaw[1] * 2 - 2048, tmp * 2 - 2048, vco.phaseTrig); // store levels in scope buffer + break; + + case mode_pass_thru: // pass thru to meassure noise and crosstalk + dac_out(ADC.anRaw[0], ADC.anRaw[1]); // output ADC0 to DAC0 & ACD1 to DAC1 + addScope(ADC.anRaw[0] * 2 - 2048, ADC.anRaw[1] * 2 - 2048, 1); // store levels in scope buffer + break; + + case mode_square_A4: // used to measure frequency accuracy + phaseC = 1299; // 440Hz - A4 concert pitch (midi 69) Should be 2611.2 @ 108MHz -> 44.4KHz + tmp = vco.square(phaseC, 32768); // square waveform (get level from position) + dac_out(tmp, tmp); // output level on DAC0 & DAC1 + addScope(ADC.anRaw[0], tmp, vco.phaseTrig); // store levels in scope buffer + break; + + case mode_manual_sine: + tmp = (ADC.anAvg[2] >> 1) + 1472; // 1472->3520 (not full range:1472->3584) + phaseC = ad2phase(tmp); // convert CV to logaritmic scale + tmp = vco.sine(phaseC); // get level from position + dac_out(tmp, tmp); // output level on DAC0 & DAC1 + addScope(ADC.anAvg[2], tmp, vco.phaseTrig); // store levels in scope buffer + break; + + case mode_manual_CV: // pot 3 controls cv1, pot2 controls cv2 + dac_out(ADC.anAvg[4], ADC.anAvg[3]); // 4095*(10+10)/20 = 4095 + phaseC = 0; // DC => 0Hz + addScope(ADC.anAvg[4], ADC.anAvg[3], 1); // store levels in scope buffer + break; + } + prevMode = moduleMode; + + // LED.green_off(); + + // Running average is done after DAC since it will add jitter due to uneven number of cycles + ADC.anCount++; + ADC.update(0); // ADC0 + ADC.update(1); // ADC1 + ADC.update(2); // pot0 (not inverted anymore) + ADC.update(3); // pot1 (not inverted anymore) + ADC.update(4); // pot2 + + // Start ADC sampling (using DMA) + adc_software_trigger_enable(ADC0, ADC_REGULAR_CHANNEL); // start ADC: DMA => adc_value[] + + // handle menu from rotation encoder + + #if (pcb_version == 0) + #define cw 'W' + #define cc 'C' + #else + #define cw 'C' + #define cc 'W' + #endif + + switch (enc.get()) + { + case 0: + LED.red_off(); + LED.blue_off(); + break; + case cw: // test clockwise (next menu) + LED.red_on(); + menuPos = menuNxt[menuPos]; + menuUpd = 1; + break; + case cc: // test counter clockwise (previous menu) + LED.blue_on(); + menuPos = menuPre[menuPos]; + menuUpd = 1; + break; + case 'S': // test encoder click (menu select) + if (menuSel[menuPos] < 128) + { + menuPos = menuSel[menuPos]; + } + else + moduleMode = menuSel[menuPos]; + menuUpd = 1; // for main loop (update display) + break; + } +} +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| +int main() +{ + SPI.begin(); + LED.begin(); + stk.begin(1000); + rcu_config(); + gpio_config(); + dma_config(); + initADC(); + initDAC(); + // initUART(); + Display.begin(&SPI, font); + Display.showImg(img_1337, sizeof(img_1337), 0, 50, 240, 86, RGBToWord(0x00, 0xff, 0xff)); + Display.showImg(img_modular, sizeof(img_modular), 0, 150, 240, 32, RGBToWord(0xff, 0x00, 0xff)); + stk.delay(2000); + Display.fillRectangle(0, 0, 240, 240, RGBToWord(0x0, 0x0, 0x0)); + Display.drawRectangle(0, 70, 239, 79, RGBToWord(0xff, 0xff, 0xff)); + T.begin(); + T.attach(OnTimer); + uint8_t oldMode = 0; + while (1) + { + if (moduleMode != oldMode) // update display icon + { + switch (moduleMode) + { + case mode_sine_am: + case mode_sine_add: + case mode_sine_fm: + case mode_square_am: + case mode_square_add: + case mode_square_fm: + case mode_square_pw: + case mode_triangle_am: + case mode_triangle_add: + case mode_triangle_fm: + case mode_triangle_saw: + case mode_triangle_2x: + case mode_triangle_3x: + Display.showImg(img_vco, sizeof(img_vco), 0, 0, 240, 60, RGBToWord(0x00, 0xff, 0xff)); + break; + case mode_Noise: + noise.init(Display); + break; + case mode_LFO_sine: + case mode_LFO_square: + case mode_LFO_triangle: + Display.showImg(img_lfo, sizeof(img_lfo), 0, 0, 240, 60, RGBToWord(0x00, 0xff, 0xff)); + break; + case mode_4_pole: + case mode_2_pole_v1: + case mode_2_pole_v2: + case mode_test: + Display.showImg(img_vcf, sizeof(img_vcf), 0, 0, 240, 60, RGBToWord(0x00, 0xff, 0xff)); + break; + case mode_ADSR: + adsr.init(Display); + adsr.draw(Display, ADC.anRaw[0], ADC.anAvg[2], ADC.anAvg[4], ADC.anAvg[3], 0); + case mode_ADR: + adsr.init(Display); + adsr.draw(Display, ADC.anRaw[0], ADC.anAvg[2], ADC.anAvg[4], ADC.anAvg[3], 1); + break; + case mode_VCA: + Display.showImg(img_vca, sizeof(img_vca), 0, 0, 240, 60, RGBToWord(0x00, 0xff, 0xff)); + break; + case mode_SnH: + Display.showImg(img_snh, sizeof(img_snh), 0, 0, 240, 60, RGBToWord(0x00, 0xff, 0xff)); + break; + case mode_Delay: + Display.showImg(img_dly, sizeof(img_dly), 0, 0, 240, 60, RGBToWord(0x00, 0xff, 0xff)); + break; + case mode_CV_Play: + Display.showImg(img_play, sizeof(img_play), 0, 0, 240, 60, RGBToWord(0x00, 0xff, 0xff)); + break; + case mode_out_minus10: + case mode_out_0V: + case mode_out_3V3: + case mode_out_10V: + case mode_in1_to_out1: + case mode_in2_to_out1: + case mode_manual_sine: + case mode_square_A4: + Display.showImg(img_cal, sizeof(img_cal), 0, 0, 240, 60, RGBToWord(0xff, 0x00, 0xff)); + break; + default: + Display.fillRectangle(0, 0, 240, 60, RGBToWord(0x0, 0x0, 0x0)); + break; + } + oldMode = moduleMode; + } + + switch (moduleMode) + { + case mode_ADSR: + adsr.draw(Display, ADC.anRaw[0], ADC.anAvg[2], ADC.anAvg[4], ADC.anAvg[3], 0); // display, gate, A, D, R, !S + break; + case mode_ADR: + adsr.draw(Display, ADC.anRaw[0], ADC.anAvg[2], ADC.anAvg[4], ADC.anAvg[3], 1); // display, gate, A, D, R, !S + break; + } + + if (dispPos >= 240) + { + // show scope + for (uint32_t i = 1; i < SCOPE_BUFFER_SIZE - 1; i++) + { + ch0old.draw1(Display, i); // clear old pixel + ch0.draw1(Display, i); // write new pixel + ch0old.write(i, ch0.read(i)); // save old position + ch1old.draw1(Display, i); + ch1.draw1(Display, i); + ch1old.write(i, ch1.read(i)); + } + dispPos = 0; + + // show AD values + char str[11]; + sprintf(str, "%d", ADC.anAvg[0]); + Display.fillRectangle(130, 160, 40, 16, RGBToWord(0x00, 0x00, 0x00)); + Display.putStr(str, 130 - 9, 160, RGBToWord(0x00, 0x00, 0xff), RGBToWord(0x00, 0x00, 0x00)); + sprintf(str, "%d", ADC.anAvg[1]); + Display.fillRectangle(190, 160, 40, 16, RGBToWord(0x00, 0x00, 0x00)); + Display.putStr(str, 190 - 9, 160, RGBToWord(0x00, 0x00, 0xff), RGBToWord(0x00, 0x00, 0x00)); + if (!quantized || !cvOut) + Display.fillRectangle(190, 180, 40, 16, RGBToWord(0x00, 0x00, 0x00)); + if (quantized) + { + sprintf(str, "Q"); + Display.putStr(str, 190 - 9, 180, RGBToWord(0xff, 0x00, 0x00), RGBToWord(0x00, 0x00, 0x00)); + } + if (cvOut) + { + sprintf(str, "C"); + Display.putStr(str, 210 - 9, 180, RGBToWord(0xff, 0x00, 0xff), RGBToWord(0x00, 0x00, 0x00)); + } + // show pot values + sprintf(str, "%d", ADC.anAvg[2]); + Display.fillRectangle(130, 180, 40, 16, RGBToWord(0x00, 0x00, 0x00)); + Display.putStr(str, 130 - 9, 180, RGBToWord(0x00, 0xff, 0x00), RGBToWord(0x00, 0x00, 0x00)); + sprintf(str, "%d", ADC.anAvg[3]); + Display.fillRectangle(130, 200, 40, 16, RGBToWord(0x00, 0x00, 0x00)); + Display.putStr(str, 130 - 9, 200, RGBToWord(0x00, 0xff, 0x00), RGBToWord(0x00, 0x00, 0x00)); + sprintf(str, "%d", ADC.anAvg[4]); + Display.fillRectangle(130, 220, 40, 16, RGBToWord(0x00, 0x00, 0x00)); + Display.putStr(str, 130 - 9, 220, RGBToWord(0x00, 0xff, 0x00), RGBToWord(0x00, 0x00, 0x00)); + uint16_t freqency = int(phaseC * 44400 / (2 * 65536)); + if (freqency < 1000) + sprintf(str, "%dHz", freqency); + else + sprintf(str, "%d", freqency); + Display.fillRectangle(190, 200, 50, 16, RGBToWord(0x00, 0x00, 0x00)); + Display.putStr(str, 190 - 9, 200, RGBToWord(0xff, 0xff, 0xff), RGBToWord(0x00, 0x00, 0x00)); + sprintf(str, "%d V", (4095 - ADC.anAvg[2]) * 10 / 2048 - 10); + Display.fillRectangle(190, 220, 50, 16, RGBToWord(0x00, 0x00, 0x00)); + Display.putStr(str, 190 - 9, 220, RGBToWord(0xff, 0xff, 0xff), RGBToWord(0x00, 0x00, 0x00)); + } + + // show menu + if (menuUpd != 0) + { + char str[11]; + Display.fillRectangle(18, 160, 110, 20, RGBToWord(0x00, 0x00, 0x00)); + if (menuPos != menuPre[menuPos]) + Display.putStr(menuTxt[menuPre[menuPos]], 10, 160, RGBToWord(0xff, 0xff, 0xff), RGBToWord(0x00, 0x00, 0x00)); + + sprintf(str, ">"); + Display.putStr(str, 0, 180, RGBToWord(0x00, 0xff, 0xff), RGBToWord(0x00, 0x00, 0x00)); + + Display.fillRectangle(18, 180, 110, 20, RGBToWord(0x00, 0x00, 0x00)); + Display.putStr(menuTxt[menuPos], 10, 180, RGBToWord(0x00, 0xff, 0xff), RGBToWord(0x00, 0x00, 0x00)); + if (menuPos != menuNxt[menuPos]) + { + Display.fillRectangle(18, 200, 110, 40, RGBToWord(0x00, 0x00, 0x00)); + Display.putStr(menuTxt[menuNxt[menuPos]], 10, 200, RGBToWord(0xff, 0xff, 0xff), RGBToWord(0x00, 0x00, 0x00)); + if (menuNxt[menuPos] != menuNxt[menuNxt[menuPos]]) + { + Display.fillRectangle(18, 220, 110, 20, RGBToWord(0x00, 0x00, 0x00)); + Display.putStr(menuTxt[menuNxt[menuNxt[menuPos]]], 10, 220, RGBToWord(0xff, 0xff, 0xff), RGBToWord(0x00, 0x00, 0x00)); + } + } + else + { + Display.fillRectangle(18, 200, 110, 40, RGBToWord(0x00, 0x00, 0x00)); // end of menu, clear display + } + menuUpd = 0; + } + } +} +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| \ No newline at end of file diff --git a/firmware/generic/src/module_adsr.cpp b/firmware/generic/src/module_adsr.cpp new file mode 100644 index 0000000..18a909b --- /dev/null +++ b/firmware/generic/src/module_adsr.cpp @@ -0,0 +1,191 @@ +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| +#include "module_adsr.h" +//#include +#include +#include "drivers\display.h" +// compressed image generated with python script (used by init) +const uint8_t img_env[196] = {255, 255, 255, 255, 255, 255, 255, 255, 126, 65, 15, 59, 15, 4, 48, 10, 82, 0, 12, 1, 59, 0, 12, 1, 52, 0, 94, 0, 10, 0, 62, 0, 10, 0, 151, 0, 8, 0, 64, 0, 8, 0, 66, 0, 85, 0, 6, 0, 66, 0, 6, 0, 55, 0, 255, 83, 0, 4, 0, 68, 0, 4, 0, 67, 0, 226, 0, 255, 234, 0, 226, 0, 41, 59, 15, 48, 255, 55, 0, 10, 0, 255, 255, 195, 0, 10, 0, 31, 59, 255, 255, 103, 0, 10, 0, 255, 255, 195, 0, 10, 0, 255, 255, 195, 0, 10, 0, 255, 255, 4, 59, 130, 0, 10, 0, 255, 222, 0, 226, 0, 255, 33, 59, 91, 37, 10, 0, 255, 255, 207, 0, 103, 0, 74, 0, 156, 0, 74, 0, 62, 0, 105, 0, 74, 0, 154, 0, 74, 0, 62, 0, 97, 0, 8, 0, 64, 0, 8, 0, 52, 0, 97, 0, 10, 1, 61, 0, 10, 0, 50, 0, 96, 1, 13, 1, 56, 2, 12, 1, 46, 1, 32, 64, 17, 3, 48, 3, 17, 46, 255, 255, 255, 255, 255, 255, 177}; + +#define black RGBToWord(0x00, 0x00, 0x00) +#define aColor RGBToWord(0xff, 0x00, 0xff) +#define dColor RGBToWord(0xff, 0xff, 0x00) +#define sColor RGBToWord(0xaa, 0xaa, 0xaa) +#define rColor RGBToWord(0x00, 0x55, 0xff) +#define logoColor RGBToWord(0x00, 0xff, 0xff) + +// Generate envelope (ADSR / Attack Decay Sustain Release) waveform. +// All transitions are linear, but could be exponential by altering functions below. +// Operates between 0V to +5V (2048 - 3008) +// Sustain level is fixed to 50% (2.5V or 2528) since there are only three potentiometers avaliable +uint16_t module_adsr::int_adsr(uint16_t gate, uint16_t pot_a, uint16_t pot_d, uint16_t pot_r, uint8_t noSustain) +{ + uint16_t out = 2048; // out level (2048 = 0V) + + if (gate > 2528 && gateCount < 8) + gateCount++; + + if (gateCount == 8 && oldGate == 0) // confirmed rising edge (new envelope) + { + adsrMode = 1; + tCount = 0; + oldGate = 1; + xorGate ^= 1; + } + + if (gate < 2528 && gateCount > -8) + gateCount--; + + if (gateCount == -8 && oldGate == 1) // confirmed falling edge + oldGate = 0; + + tCount++; + + if (adsrMode == 1) // Attack + { + if (tCount < pot_a) + out = tCount * 960 / pot_a + 2048; + else + { + adsrMode = 2; + tCount = 0; + } + } + if (adsrMode == 2) // Decay + { + if (tCount < pot_d) + out = 3008 - tCount * 480 / pot_d; // 3008 - 480 = 2528 => 50% sustain level (2.5V) + else + { + adsrMode = 3; + tCount = 0; + if (noSustain == 1) + adsrMode = 4; // skip sustain (for percussion) + } + } + if (adsrMode == 3) // Sustain + { + if (gateCount > 4 && oldGate == 1) + out = 2528; // 50% sustain level (2.5V) + else + { + adsrMode = 4; + tCount = 0; + } + } + if (adsrMode == 4) // Release + { + if (tCount < pot_r) + out = 2528 - tCount * 480 / pot_r; + else + { + adsrMode = 0; + tCount = 0; + out = 2048; // 0V + } + } + return (out); +} + +void module_adsr::draw(display &disp, uint16_t gate, uint16_t pot_a, uint16_t pot_d, uint16_t pot_r, uint8_t noSustain) +{ + + uint16_t yOffset = 142; + uint16_t height = 64; + uint16_t sh = height >> 1; + uint8_t radius = 4; + uint8_t scale = 5; // scale for potentiometer value to pixels division = 2^scale + static int16_t xOffset, a, d, s, r; + if (xOffset <= 0) + xOffset = 1; + if (gate > 2682) // show trig 3v3 trig level + { + if (xorGate == 0) + disp.fillRectangle(220, 80, 10, 10, RGBToWord(0xff, 0xff, 0x00)); + else + disp.fillRectangle(220, 80, 10, 10, RGBToWord(0x00, 0xff, 0x00)); + disp.putPixel(220, 80, black); + disp.putPixel(220, 89, black); + disp.putPixel(229, 80, black); + disp.putPixel(229, 89, black); + } + + if (pot_a >> scale != a || pot_d >> scale != d || pot_r >> scale != r) + { + // delete previous envelope (lines + circles) + disp.drawLine(xOffset, yOffset, xOffset + a, yOffset - height, black); // A + disp.fillCircle(xOffset + a, yOffset - height, radius, black); + if (a + d < 238 - xOffset) + { + disp.drawLine(xOffset + a, yOffset - height, xOffset + a + d, yOffset - sh, black); // D + disp.fillCircle(xOffset + a + d, yOffset - sh, radius, black); + } + if (a + d + s < 238 - xOffset) + disp.drawLine(xOffset + a + d, yOffset - sh, xOffset + a + d + s, yOffset - sh, black); // S + if (a + d + s + r < 238 - xOffset) + { + disp.drawLine(xOffset + a + d + s, yOffset - sh, xOffset + a + d + s + r, yOffset, black); // R + disp.fillCircle(xOffset + a + d + s + r, yOffset, radius, black); + } + + a = pot_a >> scale; + d = pot_d >> scale; + if (noSustain == 1) + s = 0; + else + s = height >> 1; + r = pot_r >> scale; + xOffset = (240 - a - d - s - r) >> 1; + if (xOffset <= 0) + xOffset = 1; + + // draw new envelope + disp.drawLine(xOffset, yOffset, xOffset + a, yOffset - height, aColor); // A + if (a + d < 238 - xOffset) + disp.drawLine(xOffset + a, yOffset - height, xOffset + a + d, yOffset - sh, dColor); // D + if (a + d + s < 238 - xOffset) + disp.drawLine(xOffset + a + d, yOffset - sh, xOffset + a + d + s, yOffset - sh, sColor); // S + if (a + d + s + r < 238 - xOffset) + disp.drawLine(xOffset + a + d + s, yOffset - sh, xOffset + a + d + s + r, yOffset, rColor); // R + + disp.fillCircle(xOffset + a, yOffset - height, radius - 1, black); + disp.fillCircle(xOffset + a + d + s + r, yOffset, radius - 1, black); + if (a + d < 238 - xOffset) + { + disp.fillCircle(xOffset + a + d, yOffset - sh, radius - 1, black); + disp.drawCircle(xOffset + a + d, yOffset - sh, radius, dColor); + } + if (a + d + s + r < 238 - xOffset) + { + disp.drawCircle(xOffset + a, yOffset - height, radius, aColor); + disp.drawCircle(xOffset + a + d + s + r, yOffset, radius, rColor); + } + + // show pot values + char str[11]; + sprintf(str, "A: %d", pot_a); + disp.fillRectangle(130, 160, 70, 16, black); + disp.putStr(str, 130 - 9, 160, aColor, black); + sprintf(str, "D: %d", pot_d); + disp.fillRectangle(130, 180, 70, 16, black); + disp.putStr(str, 130 - 9, 180, dColor, black); + sprintf(str, "S: 50%%"); + disp.fillRectangle(130, 200, 70, 16, black); + disp.putStr(str, 130 - 9, 200, sColor, black); + sprintf(str, "R: %d", pot_r); + disp.fillRectangle(130, 220, 70, 16, black); + disp.putStr(str, 130 - 9, 220, rColor, black); + } + + if (gate < 2682) // 3V3 trig level + disp.fillRectangle(220, 80, 10, 10, black); +} + +void module_adsr::init(display &disp) +{ + // show logo + disp.showImg(img_env, sizeof(img_env), 0, 0, 240, 60, logoColor); + // clear background + disp.fillRectangle(0, 60, 240, 240 - 60, black); +} + +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| \ No newline at end of file diff --git a/firmware/generic/src/module_adsr.h b/firmware/generic/src/module_adsr.h new file mode 100644 index 0000000..d1c71b6 --- /dev/null +++ b/firmware/generic/src/module_adsr.h @@ -0,0 +1,24 @@ +#ifndef __module_adsr_h +#define __module_adsr_h +extern "C" +{ +#include "drivers/display.h" +} + +class module_adsr +{ +public: + module_adsr(){}; + uint16_t int_adsr(uint16_t gate, uint16_t pot_a, uint16_t pot_d, uint16_t pot_r, uint8_t noSustain); + void draw(display &disp, uint16_t gate, uint16_t pot_a, uint16_t pot_d, uint16_t pot_r, uint8_t noSustain); + void init(display &disp); + +private: + uint16_t tCount; + uint8_t adsrMode; + uint8_t oldGate; + uint8_t xorGate; + int8_t gateCount; + uint16_t a, d, s, r; +}; +#endif \ No newline at end of file diff --git a/firmware/generic/src/module_delay.cpp b/firmware/generic/src/module_delay.cpp new file mode 100644 index 0000000..9459280 --- /dev/null +++ b/firmware/generic/src/module_delay.cpp @@ -0,0 +1,31 @@ +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| +#include "module_delay.h" +extern "C" +{ +#include "gd32vf103.h" +} + +/* potentiometer and I/O mapping + R P2 + P4 P3 + C0 C1 + D0 D1 +*/ + +uint16_t module_delay::delay(uint16_t sample, uint16_t mix, uint16_t length) +{ + + static uint16_t anHistory[4096]; // old readings from the analog input. Uses 8192 bytes of RAM... + static uint16_t anPos = 0; // index of the current reading + uint16_t old; // + uint16_t tmp; // + if (anPos >= 4095) // Are we're at the end of the array ? + anPos = 0; // ...yes, wrap around to the beginning + old = anHistory[anPos]; // get saved sample + tmp = old * mix >> 12; // mix old sample.. + tmp += sample * (4095 - mix) >> 12; // ..with new sample + anHistory[anPos] = tmp; // save new sample + anPos++; // advance to the next position in the array: + return (tmp); // return (mix) +} +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| \ No newline at end of file diff --git a/firmware/generic/src/module_delay.h b/firmware/generic/src/module_delay.h new file mode 100644 index 0000000..77d7581 --- /dev/null +++ b/firmware/generic/src/module_delay.h @@ -0,0 +1,20 @@ +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| +#ifndef __module_delay_h +#define __module_delay_h +extern "C" +{ +#include +} + +class module_delay +{ +public: + module_delay(){}; + uint16_t delay(uint16_t sample, uint16_t mix, uint16_t length); + +private: + uint16_t anHistory[4096]; // old readings from the analog input. Uses 8192 bytes of RAM... + uint16_t anPos; // index of the current reading +}; +#endif +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| \ No newline at end of file diff --git a/firmware/generic/src/module_noise.cpp b/firmware/generic/src/module_noise.cpp new file mode 100644 index 0000000..b4b3309 --- /dev/null +++ b/firmware/generic/src/module_noise.cpp @@ -0,0 +1,37 @@ +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| +#include "module_noise.h" +#include "drivers\display.h" + +// compressed image generated with python script (used by init) +const uint8_t img_rnd[175] = {255, 255, 255, 255, 255, 255, 255, 255, 132, 59, 15, 59, 9, 65, 25, 1, 59, 0, 12, 1, 59, 0, 74, 0, 23, 0, 62, 0, 10, 0, 62, 0, 74, 1, 20, 0, 64, 0, 8, 0, 64, 0, 95, 0, 66, 0, 6, 0, 66, 0, 74, 0, 239, 0, 16, 0, 68, 0, 4, 0, 68, 0, 255, 255, 255, 255, 43, 48, 26, 48, 26, 48, 255, 255, 255, 233, 48, 255, 255, 255, 255, 189, 0, 255, 222, 0, 237, 0, 237, 0, 237, 0, 183, 41, 255, 224, 0, 11, 0, 255, 211, 0, 11, 0, 255, 79, 48, 82, 0, 11, 0, 255, 211, 0, 11, 0, 245, 0, 219, 0, 11, 0, 74, 0, 74, 0, 93, 0, 219, 0, 11, 0, 72, 0, 74, 0, 95, 0, 64, 0, 74, 0, 77, 0, 11, 0, 5, 1, 61, 0, 74, 0, 100, 1, 56, 2, 73, 1, 20, 10, 48, 12, 9, 3, 48, 3, 11, 64, 255, 255, 255, 255, 255, 255, 165}; +#define logoColor RGBToWord(0x00, 0xff, 0xff) +//#define black RGBToWord(0x00, 0x00, 0x00) + +/* potentiometer and I/O mapping + R P2 + P4 P3 + C0 C1 + D0 D1 +*/ + +// simple pseudo random noise generator +uint16_t module_noise::prng(uint16_t volume) +{ + LowBit = Rnd & 1; + Rnd >>= 1; + Rnd ^= LowBit ? 0x80000057ul : 0ul; + if (LowBit) + return (2048+volume); // 2048 = 0V + else + return (2048-volume); +} + +void module_noise::init(display &disp) +{ + Rnd = 4294967294; + // show logo + disp.showImg(img_rnd, sizeof(img_rnd), 0, 0, 240, 60, logoColor); +} + + +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| \ No newline at end of file diff --git a/firmware/generic/src/module_noise.h b/firmware/generic/src/module_noise.h new file mode 100644 index 0000000..a8d7e0b --- /dev/null +++ b/firmware/generic/src/module_noise.h @@ -0,0 +1,18 @@ +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| +#ifndef __module_noise_h +#define __module_noise_h +#include "drivers\display.h" + +class module_noise +{ +public: + module_noise(){}; + uint16_t prng(uint16_t volume); + void init(display &disp); + +private: + uint32_t Rnd; // random seed + uint8_t LowBit; // noise out +}; +#endif +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| \ No newline at end of file diff --git a/firmware/generic/src/module_vcf.cpp b/firmware/generic/src/module_vcf.cpp new file mode 100644 index 0000000..dd58b9c --- /dev/null +++ b/firmware/generic/src/module_vcf.cpp @@ -0,0 +1,234 @@ +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| +#include "module_vcf.h" +extern "C" +{ +#include "gd32vf103.h" +} + +/* potentiometer and I/O mapping + R P2 + P4 P3 + C0 C1 + D0 D1 +*/ + +// 4 pole ladder resonant low pass filter (Karlsen fast ladder) +uint16_t module_vcf::r4pole1(uint16_t sample, uint16_t cutoff, uint16_t resonance) +{ + static int16_t oldOut; + if (sample > 2048 && oldOut < 2048) + phaseTrig = 1; + else + phaseTrig = 0; + oldOut = sample; + + static float buf1, buf2, buf3, buf4, fb, in, cut, q; + in = float(sample - 2048) / 2048; + cut = float(cutoff) / 4096; + q = float(resonance) / 512; // 0 to 64 + fb = buf4; + if (fb > 1) + fb = 1; + if (fb < -1) + fb = -1; + in = in - (fb * q); + buf1 = ((in - buf1) * cut) + buf1; + buf2 = ((buf1 - buf2) * cut) + buf2; + buf3 = ((buf2 - buf3) * cut) + buf3; + buf4 = ((buf3 - buf4) * cut) + buf4; + + filterOut = buf4 * 2048 + 2048; + if (buf4 > 1) + filterOut = 4095; + else if (buf4 < -1) + filterOut = 0; + return (filterOut); +} + +// 2-pole resonant low pass filter (Paul Kellett) +uint16_t module_vcf::r2pole1(uint16_t sample, uint16_t cutoff, uint16_t resonance) +{ + static int16_t oldOut; + if (sample > 2048 && oldOut < 2048) + phaseTrig = 1; + else + phaseTrig = 0; + oldOut = sample; + + static float buf1, buf2, buf3, buf4, fb, in, cut, q; + oldOut = sample; + cut = float(cutoff) / 4096; + q = float(resonance) / 2048; + in = float(sample - 2048) / 2048; + fb = q + q / (1.0 - cut); + buf1 = buf1 + cut * (in - buf1 + fb * (buf1 - buf2)); + if (buf1 > 1) + buf1 = 1; + else if (buf1 < -1) + buf1 = -1; + buf2 = buf2 + cut * (buf1 - buf2); + filterOut = buf2 * 2048 + 2048; + if (buf2 > 1) + filterOut = 4095; + else if (buf2 < -1) + filterOut = 0; + return (filterOut); +} + +// 2-pole resonant low pass filter (BASS) +uint16_t module_vcf::r2pole2(uint16_t sample, uint16_t cutoff, uint16_t resonance) +{ + // F = LPF (cutoff) + // Q = RESONANCE + // q = SCALED_RESONANCE + // buf2 => output + // f = (1 - F) / 2 + Q_offset; + // q = Q - f = Q - (1 - F) / 2 + Q_offset; + + static int16_t oldOut; + if (sample > 2048 && oldOut < 2048) + phaseTrig = 1; + else + phaseTrig = 0; + oldOut = sample; + static float buf1, buf2, buf3, buf4, fb, in, cut, q; + + cut = float(cutoff) / 4096; + q = float(resonance) / 4096; + in = float(sample - 2048) / 2048; + + fb = q - (1 - cut) / 2 + 0; + buf1 += cut * (in - buf1 + fb * 4 * (buf1 - buf2)); + buf2 += cut * (buf1 - buf2); + + filterOut = buf2 * 2048 + 2048; + if (buf2 > 1) + filterOut = 4095; + else if (buf2 < -1) + filterOut = 0; + return (filterOut); +} + +// test for filter development +uint16_t module_vcf::test(uint16_t sample, uint16_t cutoff, uint16_t resonance) +{ + static int16_t oldOut; + if (sample > 2048 && oldOut < 2048) + phaseTrig = 1; + else + phaseTrig = 0; + oldOut = sample; + static float buf1, buf2, buf3, buf4, fb, in, cut, q; + + cut = float(cutoff) / 4096; + q = float(resonance) / 4096; + in = float(sample - 2048) / 2048; + + filterOut = in * 2048 + 2048; + if (buf2 > 1) + filterOut = 4095; + else if (buf2 < -1) + filterOut = 0; + return (filterOut); +} + +/* +// MOOG 4pole 24 db resonant low pass (Stilson/Smith & Timo Tossavainen) +// ***doesnt work*** - takes too long to calculate at 44kHz ;( +uint16_t module_vcf::moog24db(uint16_t sample, uint16_t cutoff, uint16_t resonance) +{ + + static int16_t oldOut; + if (sample > 2048 && oldOut < 2048) + phaseTrig = 1; + else + phaseTrig = 0; + oldOut = sample; + + // Tdouble MoogVCF::run(double input, double fc, double res) + static float in1, in2, in3, in4, buf1, buf2, buf3, buf4, fb, in, cut, q; + + in = float(sample - 2048) / 2048; + cut = float(cutoff) / 3531; // = cutoff*1.16 + q = float(resonance) / 1024; + + fb = q * (1.0 - 0.15 * cut * cut); + in -= buf4 * fb; + in *= 0.35013 * (cut * cut) * (cut * cut); + buf1 = in + 0.3 * in1 + (1 - cut) * buf1; // Pole 1 + in1 = in; + buf2 = buf1 + 0.3 * in2 + (1 - cut) * buf2; // Pole 2 + in2 = buf1; + buf3 = buf2 + 0.3 * in3 + (1 - cut) * buf3; // Pole 3 + in3 = buf2; + buf4 = buf3 + 0.3 * in4 + (1 - cut) * buf4; // Pole 4 + in4 = buf3; + filterOut = buf4 * 2048 + 2048; + if (buf4 > 1) filterOut = 4095; + else if (buf4 < -1) filterOut = 0; + return (filterOut); +} +*/ + +/* +// integer implementation of 2pole filter, without feedback division. fast, but not so good... +uint16_t module_vcf::r2pole3(uint16_t sample, uint16_t cutoff, uint16_t resonance) +{ + static int16_t filterValue; + static int16_t filterOut; + static int16_t out; + static int16_t oldOut; + + if (sample > 2048 && oldOut < 2048) + phaseTrig = 1; + else + phaseTrig = 0; + oldOut = sample; + + resonance = resonance - cutoff; + filterValue += cutoff * (((sample - 2048) >> 4) - (filterValue >> 8) + ((resonance * (filterValue - filterOut)) >> 24)) >> 6; // + filterOut += cutoff * (filterValue - filterOut) >> 14; + + // filterValue += cutoff * (sample - 2048 - filterValue + (resonance * (filterValue - filterOut) >> 14) ) >> 15; // + // filterOut += cutoff * (filterValue - filterOut) >> 13; + out = (filterOut >> 4) + 2048; + out = (out > 4095 ? 4095 : out); + out = (out < 0 ? 0 : out); + return (out); +} +*/ +/* +// Running average analog filter ***works bad, too steep (exponential by nature)***: +static uint16_t anHistory[4096]; // old readings from the analog input. Uses 8192 bytes of RAM... +static uint16_t anPos = 0; // index of the current reading +static uint16_t oldLength; // previous filterlength +static uint32_t anTotal = 0; // running total +uint16_t anAvg = 0; // analog average + +if (newLength > oldLength) // has filterlength increased ? +{ // + for (uint16_t i = oldLength + 1; i <= newLength; i++) // ..yes, update anHistory and anTotal + { + anHistory[i] = anHistory[oldLength]; + anTotal += anHistory[oldLength]; + } +} +else if (newLength < oldLength) // has filterlength decreased ? +{ // + for (uint16_t i = oldLength; i > newLength; i--) // ..yes, update anTotal + { + anTotal -= anHistory[i]; + } +} +if (anPos >= newLength) // Are we're at the end of the array ? + anPos = 0; // ...yes, wrap around to the beginning +anTotal -= anHistory[anPos]; // subtract old reading to be replaced +anHistory[anPos] = sample; // save new sampled value +anTotal += sample; // add sample to anTotal +anPos++; // advance to the next position in the array: +anAvg = anTotal / newLength; // calculate the average: +oldLength = newLength; // +return (anAvg); // return average value +*/ + +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| \ No newline at end of file diff --git a/firmware/generic/src/module_vcf.h b/firmware/generic/src/module_vcf.h new file mode 100644 index 0000000..6b915d6 --- /dev/null +++ b/firmware/generic/src/module_vcf.h @@ -0,0 +1,26 @@ +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| +#ifndef __module_vcf_h +#define __module_vcf_h +extern "C" +{ +#include +} + +class module_vcf +{ +public: + module_vcf(){}; + uint8_t phaseTrig; + int16_t filterValue; + int16_t filterOut; + uint16_t r4pole1(uint16_t sample, uint16_t cutoff, uint16_t resonance); + uint16_t r2pole1(uint16_t sample, uint16_t cutoff, uint16_t resonance); + uint16_t r2pole2(uint16_t sample, uint16_t cutoff, uint16_t resonance); + uint16_t test(uint16_t sample, uint16_t cutoff, uint16_t resonance); + +private: + static float in1, in2, in3, in4, buf1, buf2, buf3, buf4, fb, in, cut, q; + static int16_t oldOut; +}; +#endif +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| \ No newline at end of file diff --git a/firmware/generic/src/module_vco.cpp b/firmware/generic/src/module_vco.cpp new file mode 100644 index 0000000..20a64cf --- /dev/null +++ b/firmware/generic/src/module_vco.cpp @@ -0,0 +1,206 @@ +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| +#include "module_vco.h" +extern "C" +{ +#include "gd32vf103.h" +} + +float module_vco::sine(float xTmp) +{ + if (xTmp > 0) + { + phase += xTmp; + if (phase > 65535) + { + phase -= 65535; + } + if (phase > 32768 && oldPhase < 32768) + phaseTrig = 1; + else + phaseTrig = 0; + oldPhase = phase; + } + return (sin(phase)); +} + + +// square - pw (16 bit) controls pulse width / duty cycle +uint16_t module_vco::square(float xTmp, uint16_t pw) +{ + phase += xTmp; + if (phase > 65535) + { + phase -= 65535; + } + if (phase > 32768 && oldPhase < 32768) + phaseTrig = 1; + else + phaseTrig = 0; + oldPhase = phase; + if (phase > pw) + return (1088); // 1088 = -5V + else + return (3008); // 3008 = +5V +} +// square - pw (16 bit) controls pulse width / duty cycle +uint16_t module_vco::square2x(float xTmp, uint16_t dist) +{ + int16_t out1, out2, out3; + uint16_t pw = 32768; // 50%pw / 2 + phase2 += xTmp; + if (phase2 > 65535) phase2 -= 65535; + if (phase2 > 32768 && oldPhase < 32768) phaseTrig = 1; + else phaseTrig = 0; + oldPhase = phase2; + if (phase2 > pw) out2 = -480; // 1088 = -5V + else out2 = 480; // 3008 = +5V + phase1 += xTmp - dist; + if (phase1 > 65535) phase1 -= 65535; + if (phase1 > pw) out1 = -480; // 10192/88 = -5V + else out1 = 480; // 3008 = +5V + phase3 += xTmp + dist; + if (phase3 > 65535) phase3 -= 65535; + if (phase3 > pw) out3 = -480; // 1088 = -5V + else out3 = 480; // 3008 = +5V + return(2048+out1+out3); +} +// square - pw (16 bit) controls pulse width / duty cycle +uint16_t module_vco::square3x(float xTmp, uint16_t dist) +{ + int16_t out1, out2, out3; + uint16_t pw = 32768; // 50%pw / 2 + phase2 += xTmp; + if (phase2 > 65535) phase2 -= 65535; + if (phase2 > 32768 && oldPhase < 32768) phaseTrig = 1; + else phaseTrig = 0; + oldPhase = phase2; + if (phase2 > pw) out2 = -320; // 1088 = -5V + else out2 = 320; // 3008 = +5V + phase1 += xTmp - dist; + if (phase1 > 65535) phase1 -= 65535; + if (phase1 > pw) out1 = -320; // 10192/88 = -5V + else out1 = 320; // 3008 = +5V + phase3 += xTmp + dist; + if (phase3 > 65535) phase3 -= 65535; + if (phase3 > pw) out3 = -320; // 1088 = -5V + else out3 = 320; // 3008 = +5V + return(2048+out1+out2+out3); +} + +// triangle - shape (16 bit) morphs between reverse saw, triangle and saw (could use bresenham to avoid division...) +uint16_t module_vco::triangle(float xTmp, uint16_t shape) +{ + phase += xTmp; + if (phase > 65535) + { + phase -= 65535; + } + if (phase > 32768 && oldPhase < 32768) + phaseTrig = 1; + else + phaseTrig = 0; + oldPhase = phase; + + if (phase < (65535 - shape)) // 12 bit -> 16 bit + return (4095 - 1088 - (phase * 1920) / (65535 - shape)); // x*4095/(anAvg[2]*16) + else + return (4095 - 1088 - ((65535 - phase) * 1920) / (shape)); +} + + +// triangle - shape (16 bit) morphs between reverse saw, triangle and saw (could use bresenham to avoid division...) +uint16_t module_vco::triangle2x(float xTmp, uint16_t dist) +{ + uint16_t out1,out2,out3; + //uint16_t shape = 32768; // triangle shape (not saw) + uint16_t shape = 65000; // saw shape + phase2 += xTmp; + if (phase2 > 65535) phase2 -= 65535; + if (phase2 > 32768 && oldPhase < 32768) phaseTrig = 1; + else phaseTrig = 0; + oldPhase = phase2; + + if (phase2 < (65535 - shape)) // 12 bit -> 16 bit + out2 = (4095 - 1088 - (phase2 * 1920) / (65535 - shape)); // x*4095/(anAvg[2]*16) + else + out2 = (4095 - 1088 - ((65535 - phase2) * 1920) / (shape)); + + phase1 += xTmp - dist; + if (phase1 > 65535) phase1 -= 65535; + if (phase1 < (65535 - shape)) out1 = (4095 - 1088 - (phase1 * 1920) / (65535 - shape)); + else out1 = (4095 - 1088 - ((65535 - phase1) * 1920) / (shape)); + + phase3 += xTmp + dist; + if (phase3 > 65535) phase3 -= 65535; + if (phase3 < (65535 - shape)) out3 = (4095 - 1088 - (phase3 * 1920) / (65535 - shape)); + else out3 = (4095 - 1088 - ((65535 - phase3) * 1920) / (shape)); + return((out1+out3)>>1); +} + +// triangle - shape (16 bit) morphs between reverse saw, triangle and saw (could use bresenham to avoid division...) +uint16_t module_vco::triangle3x(float xTmp, uint16_t dist) +{ + uint16_t out1,out2,out3; + //uint16_t shape = 32768; // triangle shape (not saw) + uint16_t shape = 65000; // saw shape + phase2 += xTmp; + if (phase2 > 65535) phase2 -= 65535; + if (phase2 > 32768 && oldPhase < 32768) phaseTrig = 1; + else phaseTrig = 0; + oldPhase = phase2; + + if (phase2 < (65535 - shape)) // 12 bit -> 16 bit + out2 = (4095 - 1088 - (phase2 * 1920) / (65535 - shape)); // x*4095/(anAvg[2]*16) + else + out2 = (4095 - 1088 - ((65535 - phase2) * 1920) / (shape)); + + phase1 += xTmp - dist; + if (phase1 > 65535) phase1 -= 65535; + if (phase1 < (65535 - shape)) out1 = (4095 - 1088 - (phase1 * 1920) / (65535 - shape)); + else out1 = (4095 - 1088 - ((65535 - phase1) * 1920) / (shape)); + + phase3 += xTmp + dist; + if (phase3 > 65535) phase3 -= 65535; + if (phase3 < (65535 - shape)) out3 = (4095 - 1088 - (phase3 * 1920) / (65535 - shape)); + else out3 = (4095 - 1088 - ((65535 - phase3) * 1920) / (shape)); + return(((out1+out3)>>1)+out2>>1); +} + +/* +uint16_t module_vco::int_saw(uint16_t x) +{ + uint32_t tmp = 4095 - (x >> 4); // (16 bit -> 12 bit) + return (tmp); +} + +uint16_t module_vco::int_r_saw(uint16_t x) +{ + uint32_t tmp = x >> 4; // (16 bit -> 12 bit) + return (tmp); +} +*/ +float module_vco::sin(float x) +{ +#define PI 3.1415926535897932384626433832795028841971693993751058209749445923078164062 +#define r360 2 * PI +#define r180 PI +#define r90 PI / 2 +#define PIR PI / 32768 // 65536/2 + x = x * PIR; // convert uint16_t to rad + // x = x * PI / 180; // convert degrees to rad + int sign = 1; + if (x > r180) + { + x = r360 - x; + sign = -1; + } + if (x > r90) + { + x = r180 - x; + } + float x2 = x * x; + float y = sign * x * (x2 * (x2 * (42 - x2) - 840) + 5040) / 5040; + y = y * 960 + 2048; // convert from +/-1 to 1088 - 3008 (-5V to +5V) + return (y); +} +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| \ No newline at end of file diff --git a/firmware/generic/src/module_vco.h b/firmware/generic/src/module_vco.h new file mode 100644 index 0000000..c901b36 --- /dev/null +++ b/firmware/generic/src/module_vco.h @@ -0,0 +1,31 @@ +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| +#ifndef __module_vco_h +#define __module_vco_h +extern "C" +{ +#include +} + +class module_vco +{ +public: + module_vco(){}; + uint8_t phaseTrig; + float sine(float xTmp); + // float sine3x(float xTmp, uint16_t dist); + uint16_t square(float xTmp, uint16_t pw); + uint16_t square2x(float xTmp, uint16_t dist); + uint16_t square3x(float xTmp, uint16_t dist); + uint16_t triangle(float xTmp, uint16_t shape); + uint16_t triangle2x(float xTmp, uint16_t dist); + uint16_t triangle3x(float xTmp, uint16_t dist); + // uint16_t int_saw(uint16_t x); + // uint16_t int_r_saw(uint16_t x); + +private: + float phase, phase1, phase2, phase3; + float oldPhase; + float sin(float x); +}; +#endif +//-----10|-------20|-------30|-------40|-------50|-------60|-------70|-------80| \ No newline at end of file diff --git a/firmware/generic/src/workspace.code-workspace b/firmware/generic/src/workspace.code-workspace new file mode 100644 index 0000000..bab1b7f --- /dev/null +++ b/firmware/generic/src/workspace.code-workspace @@ -0,0 +1,8 @@ +{ + "folders": [ + { + "path": ".." + } + ], + "settings": {} +} \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_ADC1_regular_parallel/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_ADC1_regular_parallel/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_ADC1_regular_parallel/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_ADC1_regular_parallel/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_ADC1_regular_parallel/main.c new file mode 100644 index 0000000..5d5920a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_ADC1_regular_parallel/main.c @@ -0,0 +1,222 @@ +/*! + \file main.c + \brief ADC0_ADC1_regular_parallel + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" +#include +#include "gd32vf103v_eval.h" + +uint32_t adc_value[2]; + +void rcu_config(void); +void gpio_config(void); +void dma_config(void); +void timer_config(void); +void adc_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ + +int main(void) +{ + /* system clocks configuration */ + rcu_config(); + /* GPIO configuration */ + gpio_config(); + /* TIMER configuration */ + timer_config(); + /* DMA configuration */ + dma_config(); + /* ADC configuration */ + adc_config(); + + /* enable TIMER1 */ + timer_enable(TIMER1); + + while(1){ + } +} + +/*! + \brief configure the different system clocks + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOA clock */ + rcu_periph_clock_enable(RCU_GPIOA); + /* enable ADC0 clock */ + rcu_periph_clock_enable(RCU_ADC0); + /* enable ADC1 clock */ + rcu_periph_clock_enable(RCU_ADC1); + /* enable DMA0 clock */ + rcu_periph_clock_enable(RCU_DMA0); + /* enable timer1 clock */ + rcu_periph_clock_enable(RCU_TIMER1); + /* config ADC clock */ + rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV8); +} + +/*! + \brief configure the GPIO peripheral + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* config the GPIO as analog mode */ + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_0|GPIO_PIN_3); +} + +/*! + \brief configure the DMA peripheral + \param[in] none + \param[out] none + \retval none +*/ +void dma_config(void) +{ + /* ADC_DMA_channel configuration */ + dma_parameter_struct dma_data_parameter; + + /* ADC DMA_channel configuration */ + dma_deinit(DMA0, DMA_CH0); + + /* initialize DMA data mode */ + dma_data_parameter.periph_addr = (uint32_t)(&ADC_RDATA(ADC0)); + dma_data_parameter.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_data_parameter.memory_addr = (uint32_t)(&adc_value); + dma_data_parameter.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_data_parameter.periph_width = DMA_PERIPHERAL_WIDTH_32BIT; + dma_data_parameter.memory_width = DMA_MEMORY_WIDTH_32BIT; + dma_data_parameter.direction = DMA_PERIPHERAL_TO_MEMORY; + dma_data_parameter.number = 2; + dma_data_parameter.priority = DMA_PRIORITY_HIGH; + dma_init(DMA0, DMA_CH0, &dma_data_parameter); + + dma_circulation_enable(DMA0, DMA_CH0); + + /* enable DMA channel */ + dma_channel_enable(DMA0, DMA_CH0); +} + +/*! + \brief configure the TIMER peripheral + \param[in] none + \param[out] none + \retval none +*/ +void timer_config(void) +{ + timer_oc_parameter_struct timer_ocintpara; + timer_parameter_struct timer_initpara; + + /* TIMER1 configuration */ + timer_struct_para_init(&timer_initpara); + timer_initpara.prescaler = 5399; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 9999; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER1,&timer_initpara); + + /* CH0 configuration in PWM mode1 */ + timer_channel_output_struct_para_init(&timer_ocintpara); + timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocintpara.outputstate = TIMER_CCX_ENABLE; + timer_channel_output_config(TIMER1, TIMER_CH_1, &timer_ocintpara); + + timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, 3999); + timer_channel_output_mode_config(TIMER1, TIMER_CH_1, TIMER_OC_MODE_PWM1); + timer_channel_output_shadow_config(TIMER1, TIMER_CH_1, TIMER_OC_SHADOW_DISABLE); +} + +/*! + \brief configure the ADC peripheral + \param[in] none + \param[out] none + \retval none +*/ +void adc_config(void) +{ + /* reset ADC */ + adc_deinit(ADC0); + adc_deinit(ADC1); + /* ADC mode config */ + adc_mode_config(ADC_DAUL_REGULAL_PARALLEL); + /* ADC continous function enable */ + adc_special_function_config(ADC0, ADC_SCAN_MODE, ENABLE); + adc_special_function_config(ADC1, ADC_SCAN_MODE, ENABLE); + + /* ADC data alignment config */ + adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT); + adc_data_alignment_config(ADC1, ADC_DATAALIGN_RIGHT); + /* ADC channel length config */ + adc_channel_length_config(ADC0, ADC_REGULAR_CHANNEL, 2); + adc_channel_length_config(ADC1, ADC_REGULAR_CHANNEL, 2); + + /* ADC regular channel config */ + adc_regular_channel_config(ADC0, 0, ADC_CHANNEL_0, ADC_SAMPLETIME_55POINT5); + adc_regular_channel_config(ADC0, 1, ADC_CHANNEL_3, ADC_SAMPLETIME_55POINT5); + adc_regular_channel_config(ADC1, 0, ADC_CHANNEL_3, ADC_SAMPLETIME_55POINT5); + adc_regular_channel_config(ADC1, 1, ADC_CHANNEL_0, ADC_SAMPLETIME_55POINT5); + + /* ADC trigger config */ + adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_T1_CH1); + adc_external_trigger_source_config(ADC1, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_NONE); + /* ADC external trigger enable */ + adc_external_trigger_config(ADC0, ADC_REGULAR_CHANNEL, ENABLE); + adc_external_trigger_config(ADC1, ADC_REGULAR_CHANNEL, ENABLE); + + /* enable ADC interface */ + adc_enable(ADC0); + /* ADC calibration and reset calibration */ + adc_calibration_enable(ADC0); + /* enable ADC interface */ + adc_enable(ADC1); + delay_1ms(1); + /* ADC calibration and reset calibration */ + adc_calibration_enable(ADC1); + + /* ADC DMA function enable */ + adc_dma_mode_enable(ADC0); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_ADC1_regular_parallel/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_ADC1_regular_parallel/readme.txt new file mode 100644 index 0000000..9892600 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_ADC1_regular_parallel/readme.txt @@ -0,0 +1,42 @@ +/*! + \file readme.txt + \brief description of the ADC0_ADC1_regular_parallel example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-1.0 board, it shows how to use ADC0 and ADC1 +regular_parallel convert function. PA3 and PA0 are configured in AIN mode. TIMER1_CH1 +is the trigger source of ADC0. ADC1 external trigger chooses none. When the rising edge +of TIMER1_CH1 coming, ADC0 and ADC1 regular channels are triggered at the same time. The +values of ADC0 and ADC1 are transmit to array adc_value[] by DMA. + + We can watch array adc_value[] in debug mode. + \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_ADC1_regular_parallel/systick.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_ADC1_regular_parallel/systick.c new file mode 100644 index 0000000..d891c3b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_ADC1_regular_parallel/systick.c @@ -0,0 +1,57 @@ +/*! + \file systick.c + \brief the systick configuration file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" + +/*! + \brief delay a time in milliseconds + \param[in] count: count in milliseconds + \param[out] none + \retval none +*/ +void delay_1ms(uint32_t count) +{ + uint64_t start_mtime, delta_mtime; + + // Don't start measuruing until we see an mtime tick + uint64_t tmp = get_timer_value(); + do { + start_mtime = get_timer_value(); + } while (start_mtime == tmp); + + do { + delta_mtime = get_timer_value() - start_mtime; + }while(delta_mtime <(SystemCoreClock/4000.0 *count )); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_ADC1_regular_parallel/systick.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_ADC1_regular_parallel/systick.h new file mode 100644 index 0000000..16746e5 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_ADC1_regular_parallel/systick.h @@ -0,0 +1,42 @@ +/*! + \file systick.h + \brief the header file of systick + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef SYS_TICK_H +#define SYS_TICK_H + +#include + +void delay_1ms(uint32_t count); + +#endif /* SYS_TICK_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/gd32vf103_it.c new file mode 100644 index 0000000..adc5762 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/gd32vf103_it.c @@ -0,0 +1,58 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "systick.h" +#include + +#include "gd32vf103_it.h" +#include "gd32vf103v_eval.h" + +extern uint16_t inserted_data[4]; + +/*! + \brief this function handles ADC0 and ADC1 interrupt + \param[in] none + \param[out] none + \retval none +*/ +void ADC0_1_IRQHandler(void) +{ + /* clear the ADC flag */ + adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOIC); + /* read ADC inserted group data register */ + inserted_data[0] = adc_inserted_data_read(ADC0, ADC_INSERTED_CHANNEL_0); + inserted_data[1] = adc_inserted_data_read(ADC0, ADC_INSERTED_CHANNEL_1); + inserted_data[2] = adc_inserted_data_read(ADC0, ADC_INSERTED_CHANNEL_2); + inserted_data[3] = adc_inserted_data_read(ADC0, ADC_INSERTED_CHANNEL_3); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/gd32vf103_it.h new file mode 100644 index 0000000..1523429 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/gd32vf103_it.h @@ -0,0 +1,45 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ + +/* this function handles ADC0 and ADC1 interrupt */ +void ADC0_1_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/main.c new file mode 100644 index 0000000..eefb751 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/main.c @@ -0,0 +1,246 @@ +/*! + \file main.c + \brief ADC EXTI trigger demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" +#include +#include "gd32vf103v_eval.h" + +uint16_t adc_value[4]; +uint16_t inserted_data[4]; + +void rcu_config(void); +void gpio_config(void); +void eclic_config(void); +void exti_config(void); +void adc_config(void); +void dma_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ + +int main(void) +{ + /* system clocks configuration */ + rcu_config(); + /* GPIO configuration */ + gpio_config(); + /* eclic configuration */ + eclic_config(); + /* configure COM port */ + gd_eval_com_init(EVAL_COM0); + /* DMA configuration */ + dma_config(); + /* ADC configuration */ + adc_config(); + /* configure the EXTI peripheral */ + exti_config(); + + while(1){ + delay_1ms(1000); + printf("ADC0 regular channel 0 data = %d \n\r",adc_value[0]); + printf("ADC0 regular channel 1 data = %d \n\r",adc_value[1]); + printf("ADC0 regular channel 2 data = %d \n\r",adc_value[2]); + printf("ADC0 regular channel 3 data = %d \n\r",adc_value[3]); + printf("ADC0 inserted channel 0 data = %d \n\r",inserted_data[0]); + printf("ADC0 inserted channel 1 data = %d \n\r",inserted_data[1]); + printf("ADC0 inserted channel 2 data = %d \n\r",inserted_data[2]); + printf("ADC0 inserted channel 3 data = %d \n\r",inserted_data[3]); + printf("***********************************\n\r"); + } +} + +/*! + \brief configure the different system clocks + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOA clock */ + rcu_periph_clock_enable(RCU_GPIOA); + /* enable GPIOD clock */ + rcu_periph_clock_enable(RCU_GPIOD); + /* enable ADC1 clock */ + rcu_periph_clock_enable(RCU_ADC0); + /* enable DMA0 clock */ + rcu_periph_clock_enable(RCU_DMA0); + /* config ADC clock */ + rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV8); +} + +/*! + \brief configure the GPIO peripheral + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* config the GPIO as analog mode, for ADC */ + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3); + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); +} + +/*! + \brief configure interrupt priority + \param[in] none + \param[out] none + \retval none +*/ +void eclic_config(void) +{ + eclic_global_interrupt_enable(); + eclic_irq_enable(ADC0_1_IRQn, 2, 0); +} + +/*! + \brief configure the EXTI peripheral + \param[in] none + \param[out] none + \retval none +*/ +void exti_config(void) +{ + /* enable the AF clock */ + rcu_periph_clock_enable(RCU_AF); + /* configure pin as input */ + gpio_init(GPIOD, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_15); + /* connect EXTI line to GPIO pin for inserted group */ + gpio_exti_source_select(GPIO_PORT_SOURCE_GPIOD, GPIO_PIN_SOURCE_15); + /* configure EXTI line for inserted group */ + exti_init(EXTI_15, EXTI_EVENT, EXTI_TRIG_RISING); + + /* configure pin as input */ + gpio_init(GPIOD, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_11); + /* connect EXTI line to GPIO pin for inserted group */ + gpio_exti_source_select(GPIO_PORT_SOURCE_GPIOD, GPIO_PIN_SOURCE_11); + /* configure EXTI line for inserted group */ + exti_init(EXTI_11, EXTI_EVENT, EXTI_TRIG_RISING); +} + +/*! + \brief configure the ADC peripheral + \param[in] none + \param[out] none + \retval none +*/ +void adc_config(void) +{ + /* reset ADC */ + adc_deinit(ADC0); + /* ADC mode config */ + adc_mode_config(ADC_MODE_FREE); + /* ADC scan function enable */ + adc_special_function_config(ADC0, ADC_SCAN_MODE, ENABLE); + /* ADC continous function enable */ + adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, DISABLE); + /* ADC data alignment config */ + adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT); + + /* ADC channel length config */ + adc_channel_length_config(ADC0, ADC_INSERTED_CHANNEL, 4); + /* ADC inserted channel config */ + adc_inserted_channel_config(ADC0, 0, ADC_CHANNEL_0, ADC_SAMPLETIME_55POINT5); + adc_inserted_channel_config(ADC0, 1, ADC_CHANNEL_1, ADC_SAMPLETIME_55POINT5); + adc_inserted_channel_config(ADC0, 2, ADC_CHANNEL_2, ADC_SAMPLETIME_55POINT5); + adc_inserted_channel_config(ADC0, 3, ADC_CHANNEL_3, ADC_SAMPLETIME_55POINT5); + /* ADC trigger config */ + adc_external_trigger_source_config(ADC0, ADC_INSERTED_CHANNEL, ADC0_1_EXTTRIG_INSERTED_EXTI_15); + /* ADC external trigger enable */ + adc_external_trigger_config(ADC0, ADC_INSERTED_CHANNEL, ENABLE); + /* clear the ADC flag */ + adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOC); + adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOIC); + /* enable ADC interrupt */ + adc_interrupt_enable(ADC0, ADC_INT_EOIC); + + /* ADC channel length config */ + adc_channel_length_config(ADC0, ADC_REGULAR_CHANNEL, 4); + /* ADC regular channel config */ + adc_regular_channel_config(ADC0, 0, ADC_CHANNEL_4, ADC_SAMPLETIME_55POINT5); + adc_regular_channel_config(ADC0, 1, ADC_CHANNEL_5, ADC_SAMPLETIME_55POINT5); + adc_regular_channel_config(ADC0, 2, ADC_CHANNEL_6, ADC_SAMPLETIME_55POINT5); + adc_regular_channel_config(ADC0, 3, ADC_CHANNEL_7, ADC_SAMPLETIME_55POINT5); + /* ADC trigger config */ + adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_EXTI_11); + adc_external_trigger_config(ADC0, ADC_REGULAR_CHANNEL, ENABLE); + /* ADC DMA function enable */ + adc_dma_mode_enable(ADC0); + + /* enable ADC interface */ + adc_enable(ADC0); + delay_1ms(1); + /* ADC calibration and reset calibration */ + adc_calibration_enable(ADC0); +} + +/*! + \brief configure the DMA peripheral + \param[in] none + \param[out] none + \retval none +*/ +void dma_config(void) +{ + /* ADC_DMA_channel configuration */ + dma_parameter_struct dma_data_parameter; + + /* ADC DMA_channel configuration */ + dma_deinit(DMA0, DMA_CH0); + + /* initialize DMA single data mode */ + dma_data_parameter.periph_addr = (uint32_t)(&ADC_RDATA(ADC0)); + dma_data_parameter.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_data_parameter.memory_addr = (uint32_t)(&adc_value); + dma_data_parameter.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_data_parameter.periph_width = DMA_PERIPHERAL_WIDTH_16BIT; + dma_data_parameter.memory_width = DMA_MEMORY_WIDTH_16BIT; + dma_data_parameter.direction = DMA_PERIPHERAL_TO_MEMORY; + dma_data_parameter.number = 4; + dma_data_parameter.priority = DMA_PRIORITY_HIGH; + dma_init(DMA0, DMA_CH0, &dma_data_parameter); + + /* enable DMA circulation mode */ + dma_circulation_enable(DMA0, DMA_CH0); + + /* enable DMA channel */ + dma_channel_enable(DMA0, DMA_CH0); +} + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/readme.txt new file mode 100644 index 0000000..4246f5f --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/readme.txt @@ -0,0 +1,48 @@ +/*! + \file readme.txt + \brief description of the ADC0 EXTI trigger regular and inserted channel + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-1.0 board, it shows how to convert ADC +regular and inserted group channels using EXTI external trigger. + + The inserted group length is 4, the scan mode is set, every rising edge event of +EXTI15(PD15) will trigger ADC to convert all the channels in the inserted group. +When all inserted group channels are converted, EOIC interrupt will be generated. +The inserted datas are print by USART. + + The regular group length is 4. Every rising edge event of EXTI11(PD11) converts 4 +channels and DMA can be used to transfer the converted data. + + We can watch array adc_value[]/inserted_data[] in debug mode or by COM. + JP5 and JP6 jump to USART. + \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/systick.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/systick.c new file mode 100644 index 0000000..d891c3b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/systick.c @@ -0,0 +1,57 @@ +/*! + \file systick.c + \brief the systick configuration file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" + +/*! + \brief delay a time in milliseconds + \param[in] count: count in milliseconds + \param[out] none + \retval none +*/ +void delay_1ms(uint32_t count) +{ + uint64_t start_mtime, delta_mtime; + + // Don't start measuruing until we see an mtime tick + uint64_t tmp = get_timer_value(); + do { + start_mtime = get_timer_value(); + } while (start_mtime == tmp); + + do { + delta_mtime = get_timer_value() - start_mtime; + }while(delta_mtime <(SystemCoreClock/4000.0 *count )); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/systick.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/systick.h new file mode 100644 index 0000000..9a74c22 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_EXTI_trigger_regular_inserted_channel/systick.h @@ -0,0 +1,42 @@ +/*! + \file systick.h + \brief the header file of systick + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef SYS_TICK_H +#define SYS_TICK_H + +#include + +void delay_1ms(uint32_t count); + +#endif /* SYS_TICK_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/gd32vf103_it.c new file mode 100644 index 0000000..e8faa85 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/gd32vf103_it.c @@ -0,0 +1,55 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_it.h" +#include "systick.h" + +extern uint16_t inserted_data[4]; + +/*! + \brief this function handles ADC0 and ADC1 interrupt + \param[in] none + \param[out] none + \retval none +*/ +void ADC0_1_IRQHandler(void) +{ + /* clear the ADC flag */ + adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOIC); + /* read ADC inserted group data register */ + inserted_data[0] = adc_inserted_data_read(ADC0, ADC_INSERTED_CHANNEL_0); + inserted_data[1] = adc_inserted_data_read(ADC0, ADC_INSERTED_CHANNEL_1); + inserted_data[2] = adc_inserted_data_read(ADC0, ADC_INSERTED_CHANNEL_2); + inserted_data[3] = adc_inserted_data_read(ADC0, ADC_INSERTED_CHANNEL_3); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/gd32vf103_it.h new file mode 100644 index 0000000..1523429 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/gd32vf103_it.h @@ -0,0 +1,45 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ + +/* this function handles ADC0 and ADC1 interrupt */ +void ADC0_1_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/main.c new file mode 100644 index 0000000..1173421 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/main.c @@ -0,0 +1,202 @@ +/*! + \file main.c + \brief TIMER trigger injected channel of ADC + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" +#include +#include "gd32vf103v_eval.h" + +uint16_t inserted_data[4]; + +void rcu_config(void); +void gpio_config(void); +void eclic_config(void); +void timer_config(void); +void adc_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ + +int main(void) +{ + /* system clocks configuration */ + rcu_config(); + /* GPIO configuration */ + gpio_config(); + /* eclic configuration */ + eclic_config(); + /* TIMER configuration */ + timer_config(); + /* ADC configuration */ + adc_config(); + /* configure COM port */ + gd_eval_com_init(EVAL_COM0); + + /* enable TIMER1 */ + timer_enable(TIMER1); + + while(1){ + delay_1ms(1000); + printf("\r\n ADC0 inserted channel 0 data = %d \r\n", inserted_data[0]); + printf("\r\n ADC0 inserted channel 1 data = %d \r\n", inserted_data[1]); + printf("\r\n ADC0 inserted channel 2 data = %d \r\n", inserted_data[2]); + printf("\r\n ADC0 inserted channel 3 data = %d \r\n", inserted_data[3]); + printf("\r\n ***********************************\r\n"); + } +} + +/*! + \brief configure the different system clocks + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOA clock */ + rcu_periph_clock_enable(RCU_GPIOA); + /* enable ADC0 clock */ + rcu_periph_clock_enable(RCU_ADC0); + /* enable timer1 clock */ + rcu_periph_clock_enable(RCU_TIMER1); + /* config ADC clock */ + rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV8); +} + +/*! + \brief configure the GPIO peripheral + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* config the GPIO as analog mode */ + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3); +} + + +/*! + \brief configure the TIMER peripheral + \param[in] none + \param[out] none + \retval none +*/ +void timer_config(void) +{ + timer_oc_parameter_struct timer_ocintpara; + timer_parameter_struct timer_initpara; + + /* deinit a timer */ + timer_deinit(TIMER1); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + /* TIMER1 configuration */ + timer_initpara.prescaler = 5399; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 9999; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER1,&timer_initpara); + + /* CH0 configuration in PWM mode1 */ + timer_channel_output_struct_para_init(&timer_ocintpara); + timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocintpara.outputstate = TIMER_CCX_ENABLE; + timer_channel_output_config(TIMER1, TIMER_CH_0, &timer_ocintpara); + + timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0, 3999); + timer_channel_output_mode_config(TIMER1, TIMER_CH_0, TIMER_OC_MODE_PWM1); + timer_channel_output_shadow_config(TIMER1, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); +} + +/*! + \brief configure the ADC peripheral + \param[in] none + \param[out] none + \retval none +*/ +void adc_config(void) +{ + /* reset ADC */ + adc_deinit(ADC0); + /* ADC mode config */ + adc_mode_config(ADC_MODE_FREE); + /* ADC continous function enable */ + adc_special_function_config(ADC0, ADC_SCAN_MODE, ENABLE); + /* ADC data alignment config */ + adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT); + /* ADC channel length config */ + adc_channel_length_config(ADC0, ADC_INSERTED_CHANNEL, 4); + + /* ADC inserted channel config */ + adc_inserted_channel_config(ADC0, 0, ADC_CHANNEL_0, ADC_SAMPLETIME_55POINT5); + adc_inserted_channel_config(ADC0, 1, ADC_CHANNEL_1, ADC_SAMPLETIME_55POINT5); + adc_inserted_channel_config(ADC0, 2, ADC_CHANNEL_2, ADC_SAMPLETIME_55POINT5); + adc_inserted_channel_config(ADC0, 3, ADC_CHANNEL_3, ADC_SAMPLETIME_55POINT5); + + /* ADC trigger config */ + adc_external_trigger_source_config(ADC0, ADC_INSERTED_CHANNEL, ADC0_1_EXTTRIG_INSERTED_T1_CH0); + + /* ADC external trigger enable */ + adc_external_trigger_config(ADC0, ADC_INSERTED_CHANNEL, ENABLE); + /* clear the ADC flag */ + adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOC); + adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOIC); + /* enable ADC interrupt */ + adc_interrupt_enable(ADC0, ADC_INT_EOIC); + + /* enable ADC interface */ + adc_enable(ADC0); + delay_1ms(1); + /* ADC calibration and reset calibration */ + adc_calibration_enable(ADC0); +} + +/** + \brief configure the nested vectored interrupt controller + \param[in] none + \param[out] none + \retval none + */ +void eclic_config(void) +{ + eclic_global_interrupt_enable(); + eclic_irq_enable(ADC0_1_IRQn, 2, 0); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/readme.txt new file mode 100644 index 0000000..fa0cd10 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/readme.txt @@ -0,0 +1,43 @@ +/*! + \file readme.txt + \brief description of the ADC TIMER trigger injected channel + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-1.0 board, it shows how to convert ADC inserted +group channels continuously using TIMER1 external trigger. + + The inserted group length is 4, the scan mode is set, every compare event will trigger ADC +to convert all the channels in the inserted group. + + We can watch adc_value in debug mode or by COM. + JP5 and JP6 jump to USART. + \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/systick.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/systick.c new file mode 100644 index 0000000..d891c3b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/systick.c @@ -0,0 +1,57 @@ +/*! + \file systick.c + \brief the systick configuration file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" + +/*! + \brief delay a time in milliseconds + \param[in] count: count in milliseconds + \param[out] none + \retval none +*/ +void delay_1ms(uint32_t count) +{ + uint64_t start_mtime, delta_mtime; + + // Don't start measuruing until we see an mtime tick + uint64_t tmp = get_timer_value(); + do { + start_mtime = get_timer_value(); + } while (start_mtime == tmp); + + do { + delta_mtime = get_timer_value() - start_mtime; + }while(delta_mtime <(SystemCoreClock/4000.0 *count )); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/systick.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/systick.h new file mode 100644 index 0000000..9a74c22 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_TIMER1_trigger_inserted_channel/systick.h @@ -0,0 +1,42 @@ +/*! + \file systick.h + \brief the header file of systick + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef SYS_TICK_H +#define SYS_TICK_H + +#include + +void delay_1ms(uint32_t count); + +#endif /* SYS_TICK_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_discontinuous_mode/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_discontinuous_mode/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_discontinuous_mode/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_discontinuous_mode/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_discontinuous_mode/main.c new file mode 100644 index 0000000..cb90663 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_discontinuous_mode/main.c @@ -0,0 +1,194 @@ +/*! + \file main.c + \brief ADC discontinuous mode for regular channel + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" +#include +#include "GD32vf103v_eval.h" + +uint16_t adc_value[8]; + +void rcu_config(void); +void gpio_config(void); +void dma_config(void); +void adc_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* system clocks configuration */ + rcu_config(); + /* GPIO configuration */ + gpio_config(); + /* configure COM port */ + gd_eval_com_init(EVAL_COM0); + /* DMA configuration */ + dma_config(); + /* ADC configuration */ + adc_config(); + + while(1){ + /* delay 1s */ + delay_1ms(1000); + /* ADC software trigger enable */ + adc_software_trigger_enable(ADC0, ADC_REGULAR_CHANNEL); + + printf("\r\n ADC0 regular channel discontinuous mode 1st data: \r\n"); + printf("\r\n ADC0 regular channel 0 data = %d \r\n",adc_value[0]); + printf("\r\n ADC0 regular channel 1 data = %d \r\n",adc_value[1]); + printf("\r\n ADC0 regular channel 2 data = %d \r\n",adc_value[2]); + printf("\r\n ADC0 regular channel discontinuous mode 2st data: \r\n"); + printf("\r\n ADC0 regular channel 3 data = %d \r\n",adc_value[3]); + printf("\r\n ADC0 regular channel 4 data = %d \r\n",adc_value[4]); + printf("\r\n ADC0 regular channel 5 data = %d \r\n",adc_value[5]); + printf("\r\n ADC0 regular channel discontinuous mode 3st data: \r\n"); + printf("\r\n ADC0 regular channel 6 data = %d \r\n",adc_value[6]); + printf("\r\n ADC0 regular channel 7 data = %d \r\n",adc_value[7]); + printf("\r\n ***********************************\r\n"); + } +} + +/*! + \brief configure the different system clocks + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOA clock */ + rcu_periph_clock_enable(RCU_GPIOA); + /* enable ADC0 clock */ + rcu_periph_clock_enable(RCU_ADC0); + /* enable DMA0 clock */ + rcu_periph_clock_enable(RCU_DMA0); + /* config ADC clock */ + rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV8); +} + +/*! + \brief configure the GPIO peripheral + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* config the GPIO as analog mode */ + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3); + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); +} + +/*! + \brief configure the DMA peripheral + \param[in] none + \param[out] none + \retval none +*/ +void dma_config(void) +{ + /* ADC_DMA_channel configuration */ + dma_parameter_struct dma_data_parameter; + + /* ADC DMA_channel configuration */ + dma_deinit(DMA0, DMA_CH0); + + /* initialize DMA single data mode */ + dma_data_parameter.periph_addr = (uint32_t)(&ADC_RDATA(ADC0)); + dma_data_parameter.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_data_parameter.memory_addr = (uint32_t)(&adc_value); + dma_data_parameter.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_data_parameter.periph_width = DMA_PERIPHERAL_WIDTH_16BIT; + dma_data_parameter.memory_width = DMA_MEMORY_WIDTH_16BIT; + dma_data_parameter.direction = DMA_PERIPHERAL_TO_MEMORY; + dma_data_parameter.number = 8; + dma_data_parameter.priority = DMA_PRIORITY_HIGH; + dma_init(DMA0, DMA_CH0, &dma_data_parameter); + + dma_circulation_enable(DMA0, DMA_CH0); + + /* enable DMA channel */ + dma_channel_enable(DMA0, DMA_CH0); +} + +/*! + \brief configure the ADC peripheral + \param[in] none + \param[out] none + \retval none +*/ +void adc_config(void) +{ + /* reset ADC */ + adc_deinit(ADC0); + /* ADC mode config */ + adc_mode_config(ADC_MODE_FREE); + + /* ADC data alignment config */ + adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT); + /* ADC channel length config */ + adc_channel_length_config(ADC0, ADC_REGULAR_CHANNEL, 8); + + /* ADC regular channel config */ + adc_regular_channel_config(ADC0, 0, ADC_CHANNEL_0, ADC_SAMPLETIME_55POINT5); + adc_regular_channel_config(ADC0, 1, ADC_CHANNEL_1, ADC_SAMPLETIME_55POINT5); + adc_regular_channel_config(ADC0, 2, ADC_CHANNEL_2, ADC_SAMPLETIME_55POINT5); + adc_regular_channel_config(ADC0, 3, ADC_CHANNEL_3, ADC_SAMPLETIME_55POINT5); + adc_regular_channel_config(ADC0, 4, ADC_CHANNEL_4, ADC_SAMPLETIME_55POINT5); + adc_regular_channel_config(ADC0, 5, ADC_CHANNEL_5, ADC_SAMPLETIME_55POINT5); + adc_regular_channel_config(ADC0, 6, ADC_CHANNEL_6, ADC_SAMPLETIME_55POINT5); + adc_regular_channel_config(ADC0, 7, ADC_CHANNEL_7, ADC_SAMPLETIME_55POINT5); + + /* ADC trigger config */ + adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_NONE); + adc_external_trigger_config(ADC0, ADC_REGULAR_CHANNEL, ENABLE); + + /* ADC discontinuous mode */ + adc_discontinuous_mode_config(ADC0, ADC_REGULAR_CHANNEL, 3); + + /* enable ADC interface */ + adc_enable(ADC0); + delay_1ms(1); + /* ADC calibration and reset calibration */ + adc_calibration_enable(ADC0); + + /* ADC DMA function enable */ + adc_dma_mode_enable(ADC0); +} + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_discontinuous_mode/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_discontinuous_mode/readme.txt new file mode 100644 index 0000000..51d1232 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_discontinuous_mode/readme.txt @@ -0,0 +1,40 @@ +/*! + \file readme.txt + \brief description of the ADC discontinuous mode example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-1.0 board, it shows how to use the ADC discontinuous +mode. The ADC is configured in discontinuous mode, group length is 8, conversion length is 3, +using software trigger. Every trigger converts 3 channels. + + We can watch array adc_value[] in debug mode or by COM. + JP5 and JP6 jump to USART. \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_discontinuous_mode/systick.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_discontinuous_mode/systick.c new file mode 100644 index 0000000..d891c3b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_discontinuous_mode/systick.c @@ -0,0 +1,57 @@ +/*! + \file systick.c + \brief the systick configuration file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" + +/*! + \brief delay a time in milliseconds + \param[in] count: count in milliseconds + \param[out] none + \retval none +*/ +void delay_1ms(uint32_t count) +{ + uint64_t start_mtime, delta_mtime; + + // Don't start measuruing until we see an mtime tick + uint64_t tmp = get_timer_value(); + do { + start_mtime = get_timer_value(); + } while (start_mtime == tmp); + + do { + delta_mtime = get_timer_value() - start_mtime; + }while(delta_mtime <(SystemCoreClock/4000.0 *count )); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_discontinuous_mode/systick.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_discontinuous_mode/systick.h new file mode 100644 index 0000000..9a74c22 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_discontinuous_mode/systick.h @@ -0,0 +1,42 @@ +/*! + \file systick.h + \brief the header file of systick + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef SYS_TICK_H +#define SYS_TICK_H + +#include + +void delay_1ms(uint32_t count); + +#endif /* SYS_TICK_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_with_DMA/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_with_DMA/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_with_DMA/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_with_DMA/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_with_DMA/main.c new file mode 100644 index 0000000..33510ce --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_with_DMA/main.c @@ -0,0 +1,171 @@ +/*! + \file main.c + \brief ADC_regular_channel_with_DMA + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" +#include +#include "gd32vf103v_eval.h" + +#define BOARD_ADC_CHANNEL ADC_CHANNEL_13 +#define ADC_GPIO_PORT GPIOC +#define ADC_GPIO_PIN GPIO_PIN_3 + +uint16_t adc_value; + +void rcu_config(void); +void gpio_config(void); +void dma_config(void); +void adc_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ + +int main(void) +{ + /* system clocks configuration */ + rcu_config(); + /* GPIO configuration */ + gpio_config(); + /* DMA configuration */ + dma_config(); + /* ADC configuration */ + adc_config(); + + while(1){ + } +} + +/*! + \brief configure the different system clocks + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOA clock */ + rcu_periph_clock_enable(RCU_GPIOC); + /* enable ADC clock */ + rcu_periph_clock_enable(RCU_ADC0); + /* enable DMA0 clock */ + rcu_periph_clock_enable(RCU_DMA0); + /* config ADC clock */ + rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV8); +} + +/*! + \brief configure the GPIO peripheral + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* config the GPIO as analog mode */ + gpio_init(ADC_GPIO_PORT, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, ADC_GPIO_PIN); +} + +/*! + \brief configure the DMA peripheral + \param[in] none + \param[out] none + \retval none +*/ +void dma_config(void) +{ + /* ADC_DMA_channel configuration */ + dma_parameter_struct dma_data_parameter; + + /* ADC DMA_channel configuration */ + dma_deinit(DMA0, DMA_CH0); + + /* initialize DMA single data mode */ + dma_data_parameter.periph_addr = (uint32_t)(&ADC_RDATA(ADC0)); + dma_data_parameter.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_data_parameter.memory_addr = (uint32_t)(&adc_value); + dma_data_parameter.memory_inc = DMA_MEMORY_INCREASE_DISABLE; + dma_data_parameter.periph_width = DMA_PERIPHERAL_WIDTH_16BIT; + dma_data_parameter.memory_width = DMA_MEMORY_WIDTH_16BIT; + dma_data_parameter.direction = DMA_PERIPHERAL_TO_MEMORY; + dma_data_parameter.number = 1; + dma_data_parameter.priority = DMA_PRIORITY_HIGH; + dma_init(DMA0, DMA_CH0, &dma_data_parameter); + dma_circulation_enable(DMA0, DMA_CH0); + + /* enable DMA channel */ + dma_channel_enable(DMA0, DMA_CH0); +} + +/*! + \brief configure the ADC peripheral + \param[in] none + \param[out] none + \retval none +*/ +void adc_config(void) +{ + /* reset ADC */ + adc_deinit(ADC0); + /* ADC mode config */ + adc_mode_config(ADC_MODE_FREE); + /* ADC contineous function enable */ + adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, ENABLE); + /* ADC scan mode disable */ + adc_special_function_config(ADC0, ADC_SCAN_MODE, DISABLE); + /* ADC data alignment config */ + adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT); + /* ADC channel length config */ + adc_channel_length_config(ADC0, ADC_REGULAR_CHANNEL, 1); + + /* ADC regular channel config */ + adc_regular_channel_config(ADC0, 0, BOARD_ADC_CHANNEL, ADC_SAMPLETIME_55POINT5); + /* ADC trigger config */ + adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_NONE); + adc_external_trigger_config(ADC0, ADC_REGULAR_CHANNEL, ENABLE); + + /* enable ADC interface */ + adc_enable(ADC0); + delay_1ms(1); + /* ADC calibration and reset calibration */ + adc_calibration_enable(ADC0); + + /* ADC DMA function enable */ + adc_dma_mode_enable(ADC0); + /* ADC software trigger enable */ + adc_software_trigger_enable(ADC0, ADC_REGULAR_CHANNEL); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_with_DMA/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_with_DMA/readme.txt new file mode 100644 index 0000000..351fc64 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_with_DMA/readme.txt @@ -0,0 +1,44 @@ +/*! + \file readme.txt + \brief description of the ADC regular channel with DMA + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-1.0 board, it shows how to use the ADC to convert +analog signal to digital data through DMA. The ADC is configured in continuous mode, PC3 +is chosen as analog input pin. + + As the ADC convertion begins by software, the converted data from ADC_RDATA register to +SRAM begins continuously. Users can change the VR1 on the GD32VF103V-EVAL board, measure +TP2 pad board, and check if its value matches the converted data through the watch window. + + The analog input pin should configured to AIN mode. + \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_with_DMA/systick.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_with_DMA/systick.c new file mode 100644 index 0000000..bae5ced --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_with_DMA/systick.c @@ -0,0 +1,57 @@ +/*! + \file systick.c + \brief the systick configuration file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" + +/*! + \brief delay a time in milliseconds + \param[in] count: count in milliseconds + \param[out] none + \retval none +*/ +void delay_1ms(uint32_t count) +{ + uint64_t start_mtime, delta_mtime; + + // Don't start measuruing until we see an mtime tick + uint64_t tmp = get_timer_value(); + do { + start_mtime = get_timer_value(); + } while (start_mtime == tmp); + + do { + delta_mtime = get_timer_value() - start_mtime; + }while(delta_mtime <(SystemCoreClock/4000.0 *count )); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_with_DMA/systick.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_with_DMA/systick.h new file mode 100644 index 0000000..9a74c22 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_regular_channel_with_DMA/systick.h @@ -0,0 +1,42 @@ +/*! + \file systick.h + \brief the header file of systick + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef SYS_TICK_H +#define SYS_TICK_H + +#include + +void delay_1ms(uint32_t count); + +#endif /* SYS_TICK_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_temperature_Vref/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_temperature_Vref/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_temperature_Vref/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_temperature_Vref/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_temperature_Vref/main.c new file mode 100644 index 0000000..1a8dacc --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_temperature_Vref/main.c @@ -0,0 +1,137 @@ +/*! + \file main.c + \brief ADC channel of temperature and Vref + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" +#include +#include "gd32vf103v_eval.h" + +float temperature; +float vref_value; + +uint16_t temperature_i; +uint16_t vref_value_i; + +void rcu_config(void); +void adc_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ + +int main(void) +{ + /* system clocks configuration */ + rcu_config(); + /* ADC configuration */ + adc_config(); + /* USART configuration */ + gd_eval_com_init(EVAL_COM0); + + while(1){ + /* ADC software trigger enable */ + adc_software_trigger_enable(ADC0, ADC_INSERTED_CHANNEL); + /* delay a time in milliseconds */ + delay_1ms(2000); + + /* value convert */ + temperature = (1.42 - ADC_IDATA0(ADC0)*3.3/4096) * 1000 / 4.3 + 25; + vref_value = (ADC_IDATA1(ADC0) * 3.3 / 4096); + + temperature_i = (uint16_t)(temperature*1000); + vref_value_i = (uint16_t)(vref_value*1000); + + /* value print */ + printf(" the temperature data is (%d/1000) degrees Celsius\r\n", temperature_i); + printf(" the reference voltage data is (%d/1000)V \r\n", vref_value_i); + printf(" \r\n"); + } + +} + +/*! + \brief configure the different system clocks + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable ADC clock */ + rcu_periph_clock_enable(RCU_ADC0); + /* config ADC clock */ + rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV8); +} + +/*! + \brief configure the ADC peripheral + \param[in] none + \param[out] none + \retval none +*/ +void adc_config(void) +{ + /* reset ADC */ + adc_deinit(ADC0); + /* ADC mode config */ + adc_mode_config(ADC_MODE_FREE); + /* ADC scan function enable */ + adc_special_function_config(ADC0, ADC_SCAN_MODE, ENABLE); + /* ADC data alignment config */ + adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT); + /* ADC temperature and Vrefint enable */ + adc_tempsensor_vrefint_enable(); + + /* ADC channel length config */ + adc_channel_length_config(ADC0, ADC_INSERTED_CHANNEL, 2); + + /* ADC temperature sensor channel config */ + adc_inserted_channel_config(ADC0, 0, ADC_CHANNEL_16, ADC_SAMPLETIME_239POINT5); + /* ADC internal reference voltage channel config */ + adc_inserted_channel_config(ADC0, 1, ADC_CHANNEL_17, ADC_SAMPLETIME_239POINT5); + + /* ADC trigger config */ + adc_external_trigger_source_config(ADC0, ADC_INSERTED_CHANNEL, ADC0_1_EXTTRIG_INSERTED_NONE); + + adc_external_trigger_config(ADC0, ADC_INSERTED_CHANNEL, ENABLE); + + /* enable ADC interface */ + adc_enable(ADC0); + delay_1ms(1); + /* ADC calibration and reset calibration */ + adc_calibration_enable(ADC0); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_temperature_Vref/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_temperature_Vref/readme.txt new file mode 100644 index 0000000..d11062e --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_temperature_Vref/readme.txt @@ -0,0 +1,45 @@ +/*! + \file readme.txt + \brief description of ADC channel of temperature and vref + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-1.0 board, it shows how to use the ADC to +convert analog signal to digital data. The ADC is configured in dependent mode, inner +channel16(temperature sensor channel) and channel17(Vref channel) are chosen as analog +input pin. + + As the ADC convertion begins by software, the converted data in the ADC_IDATAx register, + where the x is 0 to 1. + + We can watch temperature and vref_value in debug mode or by COM. + JP5 and JP6 jump to USART. + \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_temperature_Vref/systick.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_temperature_Vref/systick.c new file mode 100644 index 0000000..d891c3b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_temperature_Vref/systick.c @@ -0,0 +1,57 @@ +/*! + \file systick.c + \brief the systick configuration file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" + +/*! + \brief delay a time in milliseconds + \param[in] count: count in milliseconds + \param[out] none + \retval none +*/ +void delay_1ms(uint32_t count) +{ + uint64_t start_mtime, delta_mtime; + + // Don't start measuruing until we see an mtime tick + uint64_t tmp = get_timer_value(); + do { + start_mtime = get_timer_value(); + } while (start_mtime == tmp); + + do { + delta_mtime = get_timer_value() - start_mtime; + }while(delta_mtime <(SystemCoreClock/4000.0 *count )); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_temperature_Vref/systick.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_temperature_Vref/systick.h new file mode 100644 index 0000000..9a74c22 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC0_temperature_Vref/systick.h @@ -0,0 +1,42 @@ +/*! + \file systick.h + \brief the header file of systick + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef SYS_TICK_H +#define SYS_TICK_H + +#include + +void delay_1ms(uint32_t count); + +#endif /* SYS_TICK_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/gd32vf103_it.c new file mode 100644 index 0000000..c9fd80f --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/gd32vf103_it.c @@ -0,0 +1,54 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "systick.h" +#include "gd32vf103_it.h" +#include "gd32vf103v_eval.h" + +extern int data; + +/*! + \brief this function handles ADC0_1 exception + \param[in] none + \param[out] none + \retval none +*/ +void ADC0_1_IRQHandler(void) +{ + /* clear the ADC interrupt or status flag */ + adc_interrupt_flag_clear(ADC1, ADC_INT_FLAG_WDE); + /* turn on LED2 */ + gd_eval_led_on(LED2); + data = 1; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/gd32vf103_it.h new file mode 100644 index 0000000..d54f28c --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/gd32vf103_it.h @@ -0,0 +1,45 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ + +/* this function handles ADC0_1 exception */ +void ADC0_1_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/main.c new file mode 100644 index 0000000..bfbcfba --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/main.c @@ -0,0 +1,165 @@ +/*! + \file main.c + \brief ADC analog watchdog + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" +#include +#include "gd32vf103v_eval.h" + + +#define BOARD_ADC_CHANNEL ADC_CHANNEL_13 +#define ADC_GPIO_PORT GPIOC +#define ADC_GPIO_PIN GPIO_PIN_3 + +int data; +uint16_t adc_value; + +void rcu_config(void); +void gpio_config(void); +void eclic_config(void); +void adc_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ + +int main(void) +{ + /* system clocks configuration */ + rcu_config(); + /* GPIO configuration */ + gpio_config(); + /* eclic configuration */ + eclic_config(); + /* ADC configuration */ + adc_config(); + + while(1){ + adc_value = adc_regular_data_read(ADC1); + if(1 == data){ + /* turn off LED2 */ + data = 0; + delay_1ms(3000); + gd_eval_led_off(LED2); + } + } +} + +/*! + \brief configure the different system clocks + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOC clock */ + rcu_periph_clock_enable(RCU_GPIOC); + /* enable ADC1 clock */ + rcu_periph_clock_enable(RCU_ADC1); + /* config ADC clock */ + rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV8); +} + +/*! + \brief configure the GPIO peripheral + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* configure led GPIO */ + gd_eval_led_init(LED2); + /* config the GPIO as analog mode */ + gpio_init(ADC_GPIO_PORT, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, ADC_GPIO_PIN); +} + +/*! + \brief configure interrupt priority + \param[in] none + \param[out] none + \retval none +*/ +void eclic_config(void) +{ + eclic_global_interrupt_enable(); + eclic_irq_enable(ADC0_1_IRQn, 2, 0); +} + +/*! + \brief configure the ADC peripheral + \param[in] none + \param[out] none + \retval none +*/ +void adc_config(void) +{ + /* reset ADC */ + adc_deinit(ADC1); + /* ADC mode config */ + adc_mode_config(ADC_MODE_FREE); + /* ADC contineous function enable */ + adc_special_function_config(ADC1, ADC_CONTINUOUS_MODE, ENABLE); + /* ADC data alignment config */ + adc_data_alignment_config(ADC1, ADC_DATAALIGN_RIGHT); + /* ADC channel length config */ + adc_channel_length_config(ADC1, ADC_REGULAR_CHANNEL, 1); + + /* ADC regular channel config */ + adc_regular_channel_config(ADC1, 0, BOARD_ADC_CHANNEL, ADC_SAMPLETIME_55POINT5); + /* ADC trigger config */ + adc_external_trigger_source_config(ADC1, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_NONE); + adc_external_trigger_config(ADC1, ADC_REGULAR_CHANNEL, ENABLE); + + /* ADC analog watchdog threshold config */ + adc_watchdog_threshold_config(ADC1, 0x0400, 0x0A00); + /* ADC analog watchdog single channel config */ + adc_watchdog_single_channel_enable(ADC1, BOARD_ADC_CHANNEL); + /* ADC interrupt config */ + adc_interrupt_flag_clear(ADC1, ADC_INT_FLAG_WDE); + adc_interrupt_enable(ADC1, ADC_INT_WDE); + + /* enable ADC interface */ + adc_enable(ADC1); + delay_1ms(1); + /* ADC calibration and reset calibration */ + adc_calibration_enable(ADC1); + + /* ADC software trigger enable */ + adc_software_trigger_enable(ADC1, ADC_REGULAR_CHANNEL); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/readme.txt new file mode 100644 index 0000000..8b78749 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/readme.txt @@ -0,0 +1,45 @@ +/*! + \file readme.txt + \brief description of the ADC analog watchdog example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-1.0 board, it shows how to use the ADC analog +watchdog to guard continuously an ADC channel. The ADC is configured in continuous mode, +PC3 is chosen as analog input pin. + + Change the VR1 on the GD32VF103V-EVAL-1.0 board, measure TP2 pad on the GD32VF103V-EVAL board, +when the channe113 converted value is over the programmed analog watchdog high threshold (value +0x0A00) or below the analog watchdog low threshold(value 0x0400), an WDE interrupt will occur, +and LED2 will be on. When the channe113 converted value is in safe range(among 0x0400 and 0x0A00), +the LED2 will be off. + + The analog input pin should be configured to AIN mode. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/systick.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/systick.c new file mode 100644 index 0000000..d891c3b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/systick.c @@ -0,0 +1,57 @@ +/*! + \file systick.c + \brief the systick configuration file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" + +/*! + \brief delay a time in milliseconds + \param[in] count: count in milliseconds + \param[out] none + \retval none +*/ +void delay_1ms(uint32_t count) +{ + uint64_t start_mtime, delta_mtime; + + // Don't start measuruing until we see an mtime tick + uint64_t tmp = get_timer_value(); + do { + start_mtime = get_timer_value(); + } while (start_mtime == tmp); + + do { + delta_mtime = get_timer_value() - start_mtime; + }while(delta_mtime <(SystemCoreClock/4000.0 *count )); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/systick.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/systick.h new file mode 100644 index 0000000..9a74c22 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/ADC1_analog_watchdog/systick.h @@ -0,0 +1,42 @@ +/*! + \file systick.h + \brief the header file of systick + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef SYS_TICK_H +#define SYS_TICK_H + +#include + +void delay_1ms(uint32_t count); + +#endif /* SYS_TICK_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Oversample_shift/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Oversample_shift/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Oversample_shift/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Oversample_shift/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Oversample_shift/main.c new file mode 100644 index 0000000..b968611 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Oversample_shift/main.c @@ -0,0 +1,143 @@ +/*! + \file main.c + \brief Oversample_shift + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" +#include +#include "gd32vf103v_eval.h" + +#define BOARD_ADC_CHANNEL ADC_CHANNEL_13 +#define ADC_GPIO_PORT GPIOC +#define ADC_GPIO_PIN GPIO_PIN_3 + +uint16_t adc_value = 0; + +void rcu_config(void); +void gpio_config(void); +void adc_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ + +int main(void) +{ + /* system clocks configuration */ + rcu_config(); + /* GPIO configuration */ + gpio_config(); + /* ADC configuration */ + adc_config(); + /* configures COM port */ + gd_eval_com_init(EVAL_COM0); + + adc_software_trigger_enable(ADC0, ADC_REGULAR_CHANNEL); + + while(1){ + + while(SET != adc_flag_get(ADC0, ADC_FLAG_EOC)); + adc_flag_clear(ADC0, ADC_FLAG_EOC); + + adc_value = ADC_RDATA(ADC0); + printf("16 times sample, 4 bits shift: 0x%x\r\n", adc_value); + delay_1ms(1000); + } +} + +/*! + \brief configure the different system clocks + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOC clock */ + rcu_periph_clock_enable(RCU_GPIOC); + /* enable ADC clock */ + rcu_periph_clock_enable(RCU_ADC0); + /* config ADC clock */ + rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV8); +} + +/*! + \brief configure the GPIO peripheral + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* config the GPIO as analog mode */ + gpio_init(ADC_GPIO_PORT, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, ADC_GPIO_PIN); +} + +/*! + \brief configure the ADC peripheral + \param[in] none + \param[out] none + \retval none +*/ +void adc_config(void) +{ + /* reset ADC */ + adc_deinit(ADC0); + /* ADC mode config */ + adc_mode_config(ADC_MODE_FREE); + /* ADC contineous function enable */ + adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, ENABLE); + /* ADC data alignment config */ + adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT); + /* ADC channel length config */ + adc_channel_length_config(ADC0, ADC_REGULAR_CHANNEL, 1); + + /* ADC regular channel config */ + adc_regular_channel_config(ADC0, 0, BOARD_ADC_CHANNEL, ADC_SAMPLETIME_55POINT5); + /* ADC trigger config */ + adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_NONE); + adc_external_trigger_config(ADC0, ADC_REGULAR_CHANNEL, ENABLE); + + /* 16 times sample, 4 bits shift */ + adc_oversample_mode_config(ADC0, ADC_OVERSAMPLING_ALL_CONVERT, ADC_OVERSAMPLING_SHIFT_4B, ADC_OVERSAMPLING_RATIO_MUL16); + adc_oversample_mode_enable(ADC0); + + /* enable ADC interface */ + adc_enable(ADC0); + delay_1ms(1); + /* ADC calibration and reset calibration */ + adc_calibration_enable(ADC0); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Oversample_shift/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Oversample_shift/readme.txt new file mode 100644 index 0000000..aa7cd57 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Oversample_shift/readme.txt @@ -0,0 +1,42 @@ +/*! + \file readme.txt + \brief description of the ADC oversample shift example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-1.0 board, it shows how to use +the function of oversample and shift. In this demo, 16 times ratio of +oversample and 4 bits shift are configured. PC3(channel13) is chosen as +analog input pin. The ADC conversion begins by software, the converted +data is printed by USART. + + The analog input pin should configured to analog mode. + JP5 and JP6 jump to USART. \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Oversample_shift/systick.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Oversample_shift/systick.c new file mode 100644 index 0000000..7380933 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Oversample_shift/systick.c @@ -0,0 +1,57 @@ +/*! + \file systick.c + \brief the systick configuration file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" + +/*! + \brief delay a time in milliseconds + \param[in] count: count in milliseconds + \param[out] none + \retval none +*/ +void delay_1ms(uint32_t count) +{ + uint64_t start_mtime, delta_mtime; + + // Don't start measuruing until we see an mtime tick + uint64_t tmp = get_timer_value(); + do { + start_mtime = get_timer_value(); + } while (start_mtime == tmp); + + do { + delta_mtime = get_timer_value() - start_mtime; + }while(delta_mtime <(SystemCoreClock/4000.0 *count )); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Oversample_shift/systick.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Oversample_shift/systick.h new file mode 100644 index 0000000..588ca61 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Oversample_shift/systick.h @@ -0,0 +1,42 @@ +/*! + \file systick.h + \brief the header file of systick + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef SYS_TICK_H +#define SYS_TICK_H + +#include + +void delay_1ms(uint32_t count); + +#endif /* SYS_TICK_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Resolution/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Resolution/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Resolution/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Resolution/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Resolution/main.c new file mode 100644 index 0000000..c2f52f9 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Resolution/main.c @@ -0,0 +1,140 @@ +/*! + \file main.c + \brief Resolution + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" +#include +#include "gd32vf103v_eval.h" + +#define BOARD_ADC_CHANNEL ADC_CHANNEL_13 +#define ADC_GPIO_PORT GPIOC +#define ADC_GPIO_PIN GPIO_PIN_3 + +uint16_t adc_value; + +void rcu_config(void); +void gpio_config(void); +void adc_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* system clocks configuration */ + rcu_config(); + /* GPIO configuration */ + gpio_config(); + /* configures COM port */ + gd_eval_com_init(EVAL_COM0); + + /* ADC configuration */ + adc_config(); + adc_software_trigger_enable(ADC0, ADC_REGULAR_CHANNEL); + + while(1){ + while(SET != adc_flag_get(ADC0, ADC_FLAG_EOC)); + adc_flag_clear(ADC0, ADC_FLAG_EOC); + + adc_value = ADC_RDATA(ADC0); + printf("6B: 0x%x\r\n", adc_value); + delay_1ms(500); + } +} + +/*! + \brief configure the different system clocks + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOC clock */ + rcu_periph_clock_enable(RCU_GPIOC); + /* enable ADC clock */ + rcu_periph_clock_enable(RCU_ADC0); + /* config ADC clock */ + rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV8); +} + +/*! + \brief configure the GPIO peripheral + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* config the GPIO as analog mode */ + gpio_init(ADC_GPIO_PORT, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, ADC_GPIO_PIN); +} + +/*! + \brief configure the ADC peripheral + \param[in] none + \param[out] none + \retval none +*/ +void adc_config(void) +{ + /* reset ADC */ + adc_deinit(ADC0); + /* ADC mode config */ + adc_mode_config(ADC_MODE_FREE); + /* ADC resolusion 6B */ + printf("\r\nresolusion 6B:\r\n"); + adc_resolution_config(ADC0, ADC_RESOLUTION_6B); + /* ADC contineous function enable */ + adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, ENABLE); + /* ADC trigger config */ + adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_NONE); + /* ADC data alignment config */ + adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT); + /* ADC channel length config */ + adc_channel_length_config(ADC0, ADC_REGULAR_CHANNEL, 1); + + /* ADC regular channel config */ + adc_regular_channel_config(ADC0, 0, BOARD_ADC_CHANNEL, ADC_SAMPLETIME_55POINT5); + adc_external_trigger_config(ADC0, ADC_REGULAR_CHANNEL, ENABLE); + + /* enable ADC interface */ + adc_enable(ADC0); + delay_1ms(1); + /* ADC calibration and reset calibration */ + adc_calibration_enable(ADC0); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Resolution/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Resolution/readme.txt new file mode 100644 index 0000000..12a1445 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Resolution/readme.txt @@ -0,0 +1,41 @@ +/*! + \file readme.txt + \brief description of the ADC resolution demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-1.0 board, it shows how to use +the function of programmble resolusion. In this demo, 6B resolusion +is configured. PC3(channel13) is chosen as analog input pin. The ADC +conversion begins by software, the converted data is printed by USART. + + The analog input pin should configured to analog mode. + JP5 and JP6 jump to USART. \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Resolution/systick.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Resolution/systick.c new file mode 100644 index 0000000..7380933 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Resolution/systick.c @@ -0,0 +1,57 @@ +/*! + \file systick.c + \brief the systick configuration file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" + +/*! + \brief delay a time in milliseconds + \param[in] count: count in milliseconds + \param[out] none + \retval none +*/ +void delay_1ms(uint32_t count) +{ + uint64_t start_mtime, delta_mtime; + + // Don't start measuruing until we see an mtime tick + uint64_t tmp = get_timer_value(); + do { + start_mtime = get_timer_value(); + } while (start_mtime == tmp); + + do { + delta_mtime = get_timer_value() - start_mtime; + }while(delta_mtime <(SystemCoreClock/4000.0 *count )); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Resolution/systick.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Resolution/systick.h new file mode 100644 index 0000000..588ca61 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/ADC/Resolution/systick.h @@ -0,0 +1,42 @@ +/*! + \file systick.h + \brief the header file of systick + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef SYS_TICK_H +#define SYS_TICK_H + +#include + +void delay_1ms(uint32_t count); + +#endif /* SYS_TICK_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Backup_Data/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Backup_Data/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Backup_Data/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Backup_Data/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Backup_Data/main.c new file mode 100644 index 0000000..b873a2d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Backup_Data/main.c @@ -0,0 +1,148 @@ +/*! + \file main.c + \brief backup data register + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" + +#define BKP_DATA_REG_NUM 42 + +void led_config(void); +void write_backup_register(uint16_t data); +uint32_t check_backup_register(uint16_t data); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* led configuration and turn on all led */ + led_config(); + /* PMU lock enable */ + rcu_periph_clock_enable(RCU_PMU); + /* BKP clock enable */ + rcu_periph_clock_enable(RCU_BKPI); + /* enable write access to the registers in backup domain */ + pmu_backup_write_enable(); + /* clear the bit flag of tamper event */ + bkp_flag_clear(); + + /* check if the POR/PDR reset flag is set */ + if(RESET != rcu_flag_get(RCU_FLAG_PORRST)){ + /* clear the RCU all reset flags */ + rcu_all_reset_flag_clear(); + /* turn on LED3 */ + gd_eval_led_on(LED3); + + /* check if backup data registers has been written */ + if(0x00 == check_backup_register(0x1226)){ + /* Backup data registers values are correct */ + /* turn on LED1 */ + gd_eval_led_on(LED1); + }else{ + /* backup data registers values are not correct or they are not written*/ + /* write data to backup data registers */ + write_backup_register(0x1226); + /* turn on LED2 */ + gd_eval_led_on(LED2); + } + } + /* turn on LED4 */ + gd_eval_led_on(LED4);; + while(1){ + } +} + +/*! + \brief write data to backup DATAx registers + \param[in] data: the data to be written to backup data registers + \arg 0x0000-0xFFFF + \param[out] none + \retval none +*/ +void write_backup_register(uint16_t data) +{ + uint32_t temp = 0; + /* write data to backup registers */ + for (temp = 0; temp < BKP_DATA_REG_NUM; temp++){ + if(temp < 10){ + BKP_DATA0_9(temp) = data + (temp * 0x50); + }else{ + BKP_DATA10_41(temp) = data + (temp * 0x50); + } + } +} + +/*! + \brief check if the backup DATAx registers values are correct or not + \param[in] data: the data to be written to backup data registers + \arg 0x0000-0xFFFF + \param[out] none + \retval the number of data register +*/ +uint32_t check_backup_register(uint16_t data) +{ + uint32_t temp = 0; + /* check the data of backup registers */ + for(temp = 0; temp < BKP_DATA_REG_NUM; temp++){ + if(temp < 10){ + /* get data from data register 0-9 */ + if(data + (temp * 0x50) != BKP_DATA_GET(BKP_DATA0_9(temp))){ + return temp+1; + } + }else{ + /* get data from data register 10-41 */ + if(data + (temp * 0x50) != BKP_DATA_GET(BKP_DATA10_41(temp))){ + return temp+1; + } + } + } + return 0; +} + +/*! + \brief configure led + \param[in] none + \param[out] none + \retval none +*/ +void led_config(void) +{ + gd_eval_led_init(LED1); + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + gd_eval_led_init(LED4); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Backup_Data/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Backup_Data/readme.txt new file mode 100644 index 0000000..e11732b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Backup_Data/readme.txt @@ -0,0 +1,62 @@ +/*! + \file readme.txt + \brief description of the Backup_Data demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to store user data +in the Backup data registers. + As the Backup domain still powered by VBAT when VDD is switched off, its contents +are not lost if a battery is connected to VBAT pin. When JP0 is connected to Vmcu, +the board is powered up, LED2, LED3 and LED4 are on. After an external reset, LED2 +and LED3 are off, LED4 is on. Change JP0 connected to external battery, the board is +executed a power-down and power-up operation, LED1, LED3 and LED4 are on. + + The program behaves as follows: + 1. After startup the program checks if the board has been powered up. If yes, the + values in the BKP data registers are checked: + - if a battery is connected to the VBAT pin, the values in the BKP data registers + are retained + - if no battery is connected to the VBAT pin, the values in the BKP data registers + are lost + 2. After an external reset, the BKP data registers contents are not checked. + + Four LEDs are used to show the system state as follows: + 1. LED3 on / LED1 on: a POR/PDR reset occurred and the values in the BKP data + registers are correct + 2. LED3 on / LED2 on: a POR/PDR reset occurred and the values in the BKP data + registers are not correct or they have not yet been programmed (if it is the + first time the program is executed) + 3. LED3 off / LED1 off / LED3 off: no POR/PDR reset occurred + 4. LED4 on: program running + + BT1 should have a 3.3V battery, JP0 can change the VBAT source. + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Tamper/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Tamper/gd32vf103_it.c new file mode 100644 index 0000000..dfcf293 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Tamper/gd32vf103_it.c @@ -0,0 +1,69 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_it.h" +#include "gd32vf103v_eval.h" + +extern uint32_t is_backup_register_clear(void); + +/*! + \brief this function handles SysTick exception + \param[in] none + \param[out] none + \retval none +*/ +void TAMPER_IRQHandler(void) +{ + if(RESET != bkp_interrupt_flag_get()){ + /* a tamper detection event occurred */ + /* check if backup data registers are cleared */ + if(0 == is_backup_register_clear()){ + /* backup data registers are cleared */ + /* turn on LED3 */ + gd_eval_led_on(LED3); + }else{ + /* backup data registers are not cleared */ + /* turn on LED4 */ + gd_eval_led_on(LED4); + } + /* clear the interrupt bit flag of tamper interrupt */ + bkp_interrupt_flag_clear(); + /* disable the tamper pin */ + bkp_interrupt_disable(); + /* enable the tamper pin */ + bkp_interrupt_enable(); + /* tamper pin active level set */ + bkp_tamper_active_level_set(TAMPER_PIN_ACTIVE_LOW); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Tamper/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Tamper/gd32vf103_it.h new file mode 100644 index 0000000..de12689 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Tamper/gd32vf103_it.h @@ -0,0 +1,44 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ +/* TAMPER handle function */ +void TAMPER_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Tamper/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Tamper/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Tamper/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Tamper/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Tamper/main.c new file mode 100644 index 0000000..17af682 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Tamper/main.c @@ -0,0 +1,177 @@ +/*! + \file main.c + \brief tamper demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" + +#define BKP_DATA_REG_NUM 42 + +void led_config(void); +void write_backup_register(uint16_t data); +uint32_t check_backup_register(uint16_t data); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* led configuration and turn on all led */ + led_config(); + /* ECLIC configuration */ + eclic_global_interrupt_enable(); + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL3_PRIO1); + eclic_irq_enable(TAMPER_IRQn, 1, 0); + /* PMU lock enable */ + rcu_periph_clock_enable(RCU_PMU); + /* BKP clock enable */ + rcu_periph_clock_enable(RCU_BKPI); + + /* enable write access to the registers in backup domain */ + pmu_backup_write_enable(); + /* tamper pin active level set */ + bkp_tamper_active_level_set(TAMPER_PIN_ACTIVE_LOW); + /* tamper detection disable */ + bkp_tamper_detection_disable(); + /* disable the tamper interrupt */ + bkp_interrupt_disable(); + /* clear the bit flag of tamper event */ + bkp_flag_clear(); + /* configure the tamper pin active on low level, and enable the tamper pin */ + bkp_interrupt_enable(); + /* tamper detection enable */ + bkp_tamper_detection_enable(); + /* write data to backup DATAx registers */ + write_backup_register(0x1226); + + /* check if the written data are correct */ + if(0x00 == check_backup_register(0x1226)){ + /* turn on LED1 */ + gd_eval_led_on(LED1); + }else{ + /* turn on LED2 */ + gd_eval_led_on(LED2); + } + while(1){ + } +} + +/*! + \brief write data to backup DATAx registers + \param[in] data: the data to be written to backup data registers + \arg 0x0000-0xFFFF + \param[out] none + \retval none +*/ +void write_backup_register(uint16_t data) +{ + uint32_t temp = 0; + /* write data to backup data registers */ + for (temp = 0; temp < BKP_DATA_REG_NUM; temp++){ + if(temp < 10){ + BKP_DATA0_9(temp) = data + (temp * 0x50); + }else{ + BKP_DATA10_41(temp) = data + (temp * 0x50); + } + } +} + +/*! + \brief check if the backup DATAx registers values are correct or not + \param[in] data: the data to be written to backup data registers + \arg 0x0000-0xFFFF + \param[out] none + \retval the number of data register +*/ +uint32_t check_backup_register(uint16_t data) +{ + uint32_t temp = 0; + /* check the data of backup data registers */ + for(temp = 0; temp < BKP_DATA_REG_NUM; temp++){ + if(temp < 10){ + /* get data from data register 0-9 */ + if(data + (temp * 0x50) != BKP_DATA_GET(BKP_DATA0_9(temp))){ + return temp+1; + } + }else{ + /* get data from data register 10-41 */ + if(data + (temp * 0x50) != BKP_DATA_GET(BKP_DATA10_41(temp))){ + return temp+1; + } + } + } + return 0; +} + +/*! + \brief configure led + \param[in] none + \param[out] none + \retval none +*/ +void led_config(void) +{ + gd_eval_led_init(LED1); + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + gd_eval_led_init(LED4); +} + +/*! + \brief check if the backup data registers are clear or not + \param[in] none + \param[out] none + \retval the number of data register +*/ +uint32_t is_backup_register_clear(void) +{ + uint32_t temp = 0; + + for(temp = 0; temp < BKP_DATA_REG_NUM; temp++){ + if(temp < 10){ + /* check if the data of data register 0-9 is 0x0000 */ + if(0x0000 != BKP_DATA_GET(BKP_DATA0_9(temp))){ + return temp+1; + } + }else{ + /* check if the data of data register 10-41 is 0x0000 */ + if(0x0000 != BKP_DATA_GET(BKP_DATA10_41(temp))){ + return temp+1; + } + } + } + return 0; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Tamper/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Tamper/readme.txt new file mode 100644 index 0000000..df69718 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/BKP/Tamper/readme.txt @@ -0,0 +1,46 @@ +/*! + \file readme.txt + \brief description of tamper demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to write/read data +to/from backup data registers and demonstrates the tamper detection function. In +this demo, the TAMPER pin is configured active on low level. + After system start-up, it writes the data to all backup data registers, then check +whether the data were correctly written. If yes, LED1 is on, otherwise LED2 is on. +When the tamper key(TAMPER pin) is pressed, the backup data registers are reset and +the tamper interrupt is generated. In the corresponding ISR, it checks whether the +backup data registers are cleared or not. If yes, LED3 is on, otherwise LED4 is on. + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_Loopback/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_Loopback/gd32vf103_it.c new file mode 100644 index 0000000..e0e6a78 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_Loopback/gd32vf103_it.c @@ -0,0 +1,96 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_it.h" + +extern ErrStatus test_flag_interrupt; + +/*! + \brief this function handles CAN0 RX1 exception + \param[in] none + \param[out] none + \retval none +*/ +void CAN0_RX1_IRQHandler(void) +{ + can_receive_message_struct receive_message; + /* initialize receive message */ + receive_message.rx_sfid = 0x00; + receive_message.rx_efid = 0x00; + receive_message.rx_ff = 0; + receive_message.rx_dlen = 0; + receive_message.rx_fi = 0; + receive_message.rx_data[0] = 0x00; + receive_message.rx_data[1] = 0x00; + + /* check the receive message */ + can_message_receive(CAN0, CAN_FIFO1, &receive_message); + + if((0x1234 == receive_message.rx_efid) && (CAN_FF_EXTENDED == receive_message.rx_ff) + && (2 == receive_message.rx_dlen) && (0xCADE == (receive_message.rx_data[1]<<8|receive_message.rx_data[0]))){ + test_flag_interrupt = SUCCESS; + }else{ + test_flag_interrupt = ERROR; + } +} + +/*! + \brief this function handles CAN1 RX0 exception + \param[in] none + \param[out] none + \retval none +*/ +void CAN1_RX1_IRQHandler(void) +{ + can_receive_message_struct receive_message; + /* initialize receive message */ + receive_message.rx_sfid = 0x00; + receive_message.rx_efid = 0x00; + receive_message.rx_ff = 0; + receive_message.rx_dlen = 0; + receive_message.rx_fi = 0; + receive_message.rx_data[0] = 0x00; + receive_message.rx_data[1] = 0x00; + + /* check the receive message */ + can_message_receive(CAN1, CAN_FIFO1, &receive_message); + + if((0x1234 == receive_message.rx_efid) && (CAN_FF_EXTENDED == receive_message.rx_ff) + && (2 == receive_message.rx_dlen) && (0xCADE == (receive_message.rx_data[1]<<8|receive_message.rx_data[0]))){ + test_flag_interrupt = SUCCESS; + }else{ + test_flag_interrupt = ERROR; + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_Loopback/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_Loopback/gd32vf103_it.h new file mode 100644 index 0000000..b8aab3a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_Loopback/gd32vf103_it.h @@ -0,0 +1,47 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ +/* CAN0 RX0 handle function */ +void CAN0_RX0_IRQHandler(void); +/* CAN1 RX0 handle function */ +void CAN1_RX0_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_Loopback/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_Loopback/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_Loopback/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_Loopback/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_Loopback/main.c new file mode 100644 index 0000000..98786f8 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_Loopback/main.c @@ -0,0 +1,289 @@ +/*! + \file main.c + \brief communication_Loopback in normal mode + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +/* select CAN */ +#define CAN0_USED +//#define CAN1_USED + +#ifdef CAN0_USED + #define CANX CAN0 +#else + #define CANX CAN1 +#endif + +volatile ErrStatus test_flag; +volatile ErrStatus test_flag_interrupt; + +void clic_config(void); +void led_config(void); +ErrStatus can_loopback(void); +ErrStatus can_loopback_interrupt(void); +void can_loopback_init(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL2_PRIO2); + /* enable CAN clock */ + rcu_periph_clock_enable(RCU_CAN0); + rcu_periph_clock_enable(RCU_CAN1); + + /* configure CLIC */ + clic_config(); + + /* configure leds */ + led_config(); + /* set all the leds off */ + gd_eval_led_off(LED1); + gd_eval_led_off(LED2); + gd_eval_led_off(LED3); + gd_eval_led_off(LED4); + /* loopback of polling */ + test_flag = can_loopback(); + + if(SUCCESS == test_flag){ + /* loopback test is success */ + gd_eval_led_on(LED1); + gd_eval_led_on(LED2); + }else{ + /* loopback test is failed */ + gd_eval_led_off(LED1); + gd_eval_led_off(LED2); + } + /* loopback of interrupt */ + test_flag_interrupt = can_loopback_interrupt(); + + if(SUCCESS == test_flag_interrupt){ + /* interrupt loopback test is success */ + gd_eval_led_on(LED3); + gd_eval_led_on(LED4); + }else{ + /* interrupt loopback test is failed */ + gd_eval_led_off(LED3); + gd_eval_led_off(LED4); + } + while (1); +} + +/*! + \brief function for CAN loopback communication + \param[in] none + \param[out] none + \retval ErrStatus +*/ +ErrStatus can_loopback(void) +{ + can_trasnmit_message_struct transmit_message; + can_receive_message_struct receive_message; + uint32_t timeout = 0xFFFF; + uint8_t transmit_mailbox = 0; + /* initialize CAN */ + can_loopback_init(); + + /* initialize transmit message */ + can_struct_para_init(CAN_TX_MESSAGE_STRUCT, &transmit_message); + transmit_message.tx_sfid = 0x11; + transmit_message.tx_ft = CAN_FT_DATA; + transmit_message.tx_ff = CAN_FF_STANDARD; + transmit_message.tx_dlen = 2; + transmit_message.tx_data[0] = 0xAB; + transmit_message.tx_data[1] = 0xCD; + + /* initialize receive message */ + can_struct_para_init(CAN_RX_MESSAGE_STRUCT, &receive_message); + + /* transmit message */ + transmit_mailbox = can_message_transmit(CANX, &transmit_message); + /* waiting for transmit completed */ + while((CAN_TRANSMIT_OK != can_transmit_states(CANX, transmit_mailbox)) && (0 != timeout)){ + timeout--; + } + timeout = 0xFFFF; + /* waiting for receive completed */ + while((can_receive_message_length_get(CANX, CAN_FIFO1) < 1) && (0 != timeout)){ + timeout--; + } + + /* initialize receive message*/ + receive_message.rx_sfid = 0x00; + receive_message.rx_ff = 0; + receive_message.rx_dlen = 0; + receive_message.rx_data[0] = 0x00; + receive_message.rx_data[1] = 0x00; + can_message_receive(CANX, CAN_FIFO1, &receive_message); + + /* check the receive message */ + if((0x11 == receive_message.rx_sfid) && (CAN_FF_STANDARD == receive_message.rx_ff) + && (2 == receive_message.rx_dlen) && (0xCDAB == (receive_message.rx_data[1]<<8|receive_message.rx_data[0]))){ + return SUCCESS; + }else{ + return ERROR; + } +} + +/*! + \brief function for CAN loopback interrupt communication + \param[in] none + \param[out] none + \retval ErrStatus +*/ +ErrStatus can_loopback_interrupt(void) +{ + can_trasnmit_message_struct transmit_message; + uint32_t timeout = 0x0000FFFF; + + /* initialize CAN and filter */ + can_loopback_init(); + + /* enable CAN receive FIFO1 not empty interrupt */ + can_interrupt_enable(CANX, CAN_INT_RFNE1); + + /* initialize transmit message */ + transmit_message.tx_sfid = 0; + transmit_message.tx_efid = 0x1234; + transmit_message.tx_ff = CAN_FF_EXTENDED; + transmit_message.tx_ft = CAN_FT_DATA; + transmit_message.tx_dlen = 2; + transmit_message.tx_data[0] = 0xDE; + transmit_message.tx_data[1] = 0xCA; + /* transmit a message */ + can_message_transmit(CANX, &transmit_message); + + /* waiting for receive completed */ + while((SUCCESS != test_flag_interrupt) && (0 != timeout)){ + timeout--; + } + if(0 == timeout){ + test_flag_interrupt = ERROR; + } + + /* disable CAN receive FIFO1 not empty interrupt */ + can_interrupt_disable(CANX, CAN_INTEN_RFNEIE1); + + return test_flag_interrupt; +} + +/*! + \brief initialize CAN and filter + \param[in] can_parameter + \arg can_parameter_struct + \param[in] can_filter + \arg can_filter_parameter_struct + \param[out] none + \retval none +*/ +void can_loopback_init(void) +{ + can_parameter_struct can_parameter; + can_filter_parameter_struct can_filter; + + can_struct_para_init(CAN_INIT_STRUCT, &can_parameter); + can_struct_para_init(CAN_FILTER_STRUCT, &can_filter); + + /* initialize CAN register */ + can_deinit(CANX); + + /* initialize CAN */ + can_parameter.time_triggered = DISABLE; + can_parameter.auto_bus_off_recovery = DISABLE; + can_parameter.auto_wake_up = DISABLE; + can_parameter.no_auto_retrans = DISABLE; + can_parameter.rec_fifo_overwrite = DISABLE; + can_parameter.trans_fifo_order = DISABLE; + can_parameter.working_mode = CAN_LOOPBACK_MODE; + /* configure baudrate to 125kbps */ + can_parameter.resync_jump_width = CAN_BT_SJW_1TQ; + can_parameter.time_segment_1 = CAN_BT_BS1_5TQ; + can_parameter.time_segment_2 = CAN_BT_BS2_3TQ; + can_parameter.prescaler = 48; + can_init(CANX, &can_parameter); + + /* initialize filter */ +#ifdef CAN0_USED + /* CAN0 filter number */ + can_filter.filter_number = 0; +#else + /* CAN1 filter number */ + can_filter.filter_number = 15; +#endif + /* initialize filter */ + can_filter.filter_mode = CAN_FILTERMODE_MASK; + can_filter.filter_bits = CAN_FILTERBITS_32BIT; + can_filter.filter_list_high = 0x0000; + can_filter.filter_list_low = 0x0000; + can_filter.filter_mask_high = 0x0000; + can_filter.filter_mask_low = 0x0000; + can_filter.filter_fifo_number = CAN_FIFO1; + can_filter.filter_enable=ENABLE; + can_filter_init(&can_filter); +} + +/*! + \brief configure the nested vectored interrupt controller + \param[in] none + \param[out] none + \retval none +*/ +void clic_config(void) +{ + eclic_global_interrupt_enable(); + /* configure CAN0 CLIC */ + eclic_irq_enable(CAN0_RX1_IRQn,1,0); + /* configure CAN1 CLIC */ + eclic_irq_enable(CAN1_RX1_IRQn,1,0); +} + +/*! + \brief configure the leds + \param[in] none + \param[out] none + \retval none +*/ +void led_config(void) +{ + gd_eval_led_init(LED1); + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + gd_eval_led_init(LED4); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_Loopback/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_Loopback/readme.txt new file mode 100644 index 0000000..4fc2f5c --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_Loopback/readme.txt @@ -0,0 +1,48 @@ +/*! + \file readme.txt + \brief description of the communication_Loopback demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL board, it shows how to set a communication +with the CAN in loopback mode. + + The example first performs a transmission and a reception of a standard data frame +by polling at 125 Kbps.If the received frame is successful, the LED1 and LED2 are on. +Otherwise,the LED1 and LED2 are off. Then, an extended data frame is transmitted at +125 Kbps. Reception is done in the interrupt handler when the message becomes pending +in the FIFO1. If the received frame is successful, the LED3 and LED4 are on. Otherwise, +the LED4 and LED5 are off. + + User can select CAN0 or CAN1 cell using the private defines in main.c. + + JP13,JP4 and JP16 must be fitted. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_CANs/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_CANs/gd32vf103_it.c new file mode 100644 index 0000000..17ae7b6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_CANs/gd32vf103_it.c @@ -0,0 +1,76 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_it.h" + +extern can_receive_message_struct receive_message; +extern FlagStatus can0_receive_flag; +extern FlagStatus can1_receive_flag; +extern FlagStatus can0_error_flag; +extern FlagStatus can1_error_flag; + +/*! + \brief this function handles CAN0 RX0 exception + \param[in] none + \param[out] none + \retval none +*/ +void CAN0_RX0_IRQHandler(void) +{ + /* check the receive message */ + can_message_receive(CAN0, CAN_FIFO0, &receive_message); + + if((0x300>>1 == receive_message.rx_sfid)&&(CAN_FF_STANDARD == receive_message.rx_ff)&&(2 == receive_message.rx_dlen)){ + can0_receive_flag = SET; + }else{ + can0_error_flag = SET; + } +} +/*! + \brief this function handles CAN1 RX0 exception + \param[in] none + \param[out] none + \retval none +*/ +void CAN1_RX0_IRQHandler(void) +{ + /* check the receive message */ + can_message_receive(CAN1, CAN_FIFO0, &receive_message); + + if((0x300>>1 == receive_message.rx_sfid)&&(CAN_FF_STANDARD == receive_message.rx_ff)&&(2 == receive_message.rx_dlen)){ + can1_receive_flag = SET; + }else{ + can1_error_flag = SET; + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_CANs/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_CANs/gd32vf103_it.h new file mode 100644 index 0000000..b8aab3a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_CANs/gd32vf103_it.h @@ -0,0 +1,47 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ +/* CAN0 RX0 handle function */ +void CAN0_RX0_IRQHandler(void); +/* CAN1 RX0 handle function */ +void CAN1_RX0_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_CANs/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_CANs/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_CANs/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_CANs/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_CANs/main.c new file mode 100644 index 0000000..294a5f2 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_CANs/main.c @@ -0,0 +1,301 @@ +/*! + \file main.c + \brief communication_among_CANS in normal mode + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +/* select CAN baudrate */ +/* 1MBps */ +#define CAN_BAUDRATE 1000 +/* 500kBps */ +/* #define CAN_BAUDRATE 500 */ +/* 250kBps */ +/* #define CAN_BAUDRATE 250 */ +/* 125kBps */ +/* #define CAN_BAUDRATE 125 */ +/* 100kBps */ +/* #define CAN_BAUDRATE 100 */ +/* 50kBps */ +/* #define CAN_BAUDRATE 50 */ +/* 20kBps */ +/* #define CAN_BAUDRATE 20 */ + +FlagStatus can0_receive_flag; +FlagStatus can1_receive_flag; +FlagStatus can0_error_flag; +FlagStatus can1_error_flag; +can_parameter_struct can_init_parameter; +can_filter_parameter_struct can_filter_parameter; +can_trasnmit_message_struct transmit_message; +can_receive_message_struct receive_message; + +void clic_config(void); +void led_config(void); +void can_gpio_config(void); +void can_config(can_parameter_struct can_parameter, can_filter_parameter_struct can_filter); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + can0_receive_flag = RESET; + can1_receive_flag = RESET; + can0_error_flag = RESET; + can1_error_flag = RESET; + + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL2_PRIO2); + + /* configure GPIO */ + can_gpio_config(); + + /* configure CLIC */ + clic_config(); + + /* configure USART */ + gd_eval_com_init(EVAL_COM0); + + /* configure Wakeup key or Tamper key */ + gd_eval_key_init(KEY_A, KEY_MODE_GPIO); + gd_eval_key_init(KEY_C, KEY_MODE_GPIO); + + printf("\r\nGD32VF103V dual CAN test, please press A key or C key to start communication!\r\n"); + /* configure leds */ + led_config(); + gd_eval_led_off(LED1); + gd_eval_led_off(LED2); + gd_eval_led_off(LED3); + gd_eval_led_off(LED4); + + /* initialize CAN and filter */ + can_config(can_init_parameter, can_filter_parameter); + /* enable can receive FIFO0 not empty interrupt */ + can_interrupt_enable(CAN0, CAN_INT_RFNE0); + can_interrupt_enable(CAN1, CAN_INT_RFNE0); + + /* initialize transmit message */ + transmit_message.tx_sfid = 0x300>>1; + transmit_message.tx_efid = 0x00; + transmit_message.tx_ft = CAN_FT_DATA; + transmit_message.tx_ff = CAN_FF_STANDARD; + transmit_message.tx_dlen = 2; + + while(1){ + /* test whether the A key is pressed */ + if(0 == gd_eval_key_state_get(KEY_A)){ + transmit_message.tx_data[0] = 0x55; + transmit_message.tx_data[1] = 0xAA; + printf("\r\n can0 transmit data:%x,%x \r\n", transmit_message.tx_data[0], transmit_message.tx_data[1]); + /* transmit message */ + can_message_transmit(CAN0, &transmit_message); + /* waiting for the A key up */ + while(0 == gd_eval_key_state_get(KEY_A)); + } + /* test whether the C key is pressed */ + if(0 == gd_eval_key_state_get(KEY_C)){ + transmit_message.tx_data[0] = 0xAA; + transmit_message.tx_data[1] = 0x55; + printf("\r\n can1 transmit data:%x,%x \r\n", transmit_message.tx_data[0], transmit_message.tx_data[1]); + /* transmit message */ + can_message_transmit(CAN1, &transmit_message); + /* waiting for the C key up */ + while(0 == gd_eval_key_state_get(KEY_C)); + } + /* CAN0 receive data correctly, the received data is printed */ + if(SET == can0_receive_flag){ + can0_receive_flag = RESET; + printf("\r\n can0 receive data:%x,%x \r\n", receive_message.rx_data[0], receive_message.rx_data[1]); + gd_eval_led_toggle(LED1); + } + /* CAN1 receive data correctly, the received data is printed */ + if(SET == can1_receive_flag){ + can1_receive_flag = RESET; + gd_eval_led_toggle(LED3); + printf("\r\n can1 receive data:%x,%x \r\n", receive_message.rx_data[0], receive_message.rx_data[1]); + } + /* CAN0 error */ + if(SET == can0_error_flag){ + can0_error_flag = RESET; + printf("\r\n can0 communication error \r\n"); + } + /* CAN1 error */ + if(SET == can1_error_flag){ + can1_error_flag = RESET; + printf("\r\n can1 communication error \r\n"); + } + } +} + +/*! + \brief initialize CAN and filter + \param[in] can_parameter + \arg can_parameter_struct + \param[in] can_filter + \arg can_filter_parameter_struct + \param[out] none + \retval none +*/ +void can_config(can_parameter_struct can_parameter, can_filter_parameter_struct can_filter) +{ + can_struct_para_init(CAN_INIT_STRUCT, &can_parameter); + can_struct_para_init(CAN_INIT_STRUCT, &can_filter); + /* initialize CAN register */ + can_deinit(CAN0); + can_deinit(CAN1); + + /* initialize CAN parameters */ + can_parameter.time_triggered = DISABLE; + can_parameter.auto_bus_off_recovery = DISABLE; + can_parameter.auto_wake_up = DISABLE; + can_parameter.no_auto_retrans = DISABLE; + can_parameter.rec_fifo_overwrite = DISABLE; + can_parameter.trans_fifo_order = DISABLE; + can_parameter.working_mode = CAN_NORMAL_MODE; + can_parameter.resync_jump_width = CAN_BT_SJW_1TQ; + can_parameter.time_segment_1 = CAN_BT_BS1_5TQ; + can_parameter.time_segment_2 = CAN_BT_BS2_3TQ; + + /* 1MBps */ +#if CAN_BAUDRATE == 1000 + can_parameter.prescaler = 6; + /* 500KBps */ +#elif CAN_BAUDRATE == 500 + can_parameter.prescaler = 12; + /* 250KBps */ +#elif CAN_BAUDRATE == 250 + can_parameter.prescaler = 24; + /* 125KBps */ +#elif CAN_BAUDRATE == 125 + can_parameter.prescaler = 48; + /* 100KBps */ +#elif CAN_BAUDRATE == 100 + can_parameter.prescaler = 60; + /* 50KBps */ +#elif CAN_BAUDRATE == 50 + can_parameter.prescaler = 120; + /* 20KBps */ +#elif CAN_BAUDRATE == 20 + can_parameter.prescaler = 300; +#else + #error "please select list can baudrate in private defines in main.c " +#endif + /* initialize CAN */ + can_init(CAN0, &can_parameter); + can_init(CAN1, &can_parameter); + + /* initialize filter */ + can_filter.filter_number=0; + can_filter.filter_mode = CAN_FILTERMODE_MASK; + can_filter.filter_bits = CAN_FILTERBITS_32BIT; + can_filter.filter_list_high = 0x3000; + can_filter.filter_list_low = 0x0000; + can_filter.filter_mask_high = 0x3000; + can_filter.filter_mask_low = 0x0000; + can_filter.filter_fifo_number = CAN_FIFO0; + can_filter.filter_enable = ENABLE; + + can_filter_init(&can_filter); + + /* CAN1 filter number */ + can_filter.filter_number = 15; + can_filter_init(&can_filter); +} + +/*! + \brief configure the nested vectored interrupt controller + \param[in] none + \param[out] none + \retval none +*/ +void clic_config(void) +{ + eclic_global_interrupt_enable(); + /* configure CAN0 CLIC */ + eclic_irq_enable(CAN0_RX0_IRQn,1,0); + + /* configure CAN1 CLIC */ + eclic_irq_enable(CAN1_RX0_IRQn,2,0); +} + +/*! + \brief configure the leds + \param[in] none + \param[out] none + \retval none +*/ +void led_config(void) +{ + gd_eval_led_init(LED1); + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + gd_eval_led_init(LED4); +} + +/*! + \brief configure GPIO + \param[in] none + \param[out] none + \retval none +*/ +void can_gpio_config(void) +{ + /* enable CAN clock */ + rcu_periph_clock_enable(RCU_CAN0); + rcu_periph_clock_enable(RCU_CAN1); + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_GPIOD); + rcu_periph_clock_enable(RCU_AF); + + /* configure CAN0 GPIO */ + gpio_init(GPIOD,GPIO_MODE_IPU,GPIO_OSPEED_50MHZ,GPIO_PIN_0); + gpio_init(GPIOD,GPIO_MODE_AF_PP,GPIO_OSPEED_50MHZ,GPIO_PIN_1); + gpio_pin_remap_config(GPIO_CAN0_FULL_REMAP,ENABLE); + + /* configure CAN1 GPIO */ + gpio_init(GPIOB,GPIO_MODE_IPU,GPIO_OSPEED_50MHZ,GPIO_PIN_5); + gpio_init(GPIOB,GPIO_MODE_AF_PP,GPIO_OSPEED_50MHZ,GPIO_PIN_6); + gpio_pin_remap_config(GPIO_CAN1_REMAP,ENABLE); +} + +/* retarget the C library printf function to the usart */ +int fputc(int ch, FILE *f) +{ + usart_data_transmit(EVAL_COM0, (uint8_t)ch); + while (RESET == usart_flag_get(EVAL_COM0, USART_FLAG_TBE)); + return ch; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_CANs/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_CANs/readme.txt new file mode 100644 index 0000000..101e0ec --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_CANs/readme.txt @@ -0,0 +1,54 @@ +/*! + \file readme.txt + \brief description of the communication_among_CANS demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL board, it shows how to configure the +CAN0 and CAN1 peripherals to send and receive CAN frames in normal mode. Pressing +KEY_A key or KEY_C key: + + When KEY_A key is pressed, CAN0 sends a message to CAN1 and print it.when CAN1 +receives correctly this message,the receive data will be printedand LED3 toggles +one time. + + When KEY_C key is pressed, CAN1 sends a message to CAN0 and print it. When CAN0 +receives correctly this message,the receive data will be printed and LED1 toggles +one time. + + User can select one from the preconfigured CAN baud rates from the private +defines in main.c. These baudrates is correct only when the system clock frequency +is 108M. + + JP4,JP13 and JP16 must be fitted. + Connect JP14 CAN_L to JP15 CAN_L + Connect JP14 CAN_H to JP15 CAN_H diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_Devices/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_Devices/gd32vf103_it.c new file mode 100644 index 0000000..12813ef --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_Devices/gd32vf103_it.c @@ -0,0 +1,69 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_it.h" + +extern FlagStatus receive_flag; +extern can_receive_message_struct receive_message; + +/*! + \brief this function handles CAN0 RX0 exception + \param[in] none + \param[out] none + \retval none +*/ +void CAN0_RX1_IRQHandler(void) +{ + /* check the receive message */ + can_message_receive(CAN0, CAN_FIFO1, &receive_message); + if((0x321 == receive_message.rx_sfid)&&(CAN_FF_STANDARD == receive_message.rx_ff) && (1 == receive_message.rx_dlen)){ + receive_flag = SET; + } +} + +/*! + \brief this function handles CAN1 RX0 exception + \param[in] none + \param[out] none + \retval none +*/ +void CAN1_RX1_IRQHandler(void) +{ + /* check the receive message */ + can_message_receive(CAN1, CAN_FIFO1, &receive_message); + if((0x321 == receive_message.rx_sfid)&&(CAN_FF_STANDARD == receive_message.rx_ff) && (1 == receive_message.rx_dlen)){ + receive_flag = SET; + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_Devices/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_Devices/gd32vf103_it.h new file mode 100644 index 0000000..b8aab3a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_Devices/gd32vf103_it.h @@ -0,0 +1,47 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ +/* CAN0 RX0 handle function */ +void CAN0_RX0_IRQHandler(void); +/* CAN1 RX0 handle function */ +void CAN1_RX0_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_Devices/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_Devices/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_Devices/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_Devices/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_Devices/main.c new file mode 100644 index 0000000..62db549 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_Devices/main.c @@ -0,0 +1,263 @@ +/*! + \file main.c + \brief communication_among_Devices in normal mode + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +/* select can */ +#define CAN0_USED +//#define CAN1_USED + +#ifdef CAN0_USED + #define CANX CAN0 +#else + #define CANX CAN1 +#endif + +FlagStatus receive_flag; +uint8_t transmit_number = 0x0; +can_receive_message_struct receive_message; +can_trasnmit_message_struct transmit_message; + +void clic_config(void); +void led_config(void); +void gpio_config(void); +void can_networking_init(void); +void delay(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + receive_flag = RESET; + + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL2_PRIO2); + /* configure Tamper key */ + gd_eval_key_init(KEY_CET, KEY_MODE_GPIO); + /* configure GPIO */ + gpio_config(); + /* configure USART */ + gd_eval_com_init(EVAL_COM0); + /* configure CLIC */ + clic_config(); + /* configure leds */ + led_config(); + /* set all leds off */ + gd_eval_led_off(LED1); + gd_eval_led_off(LED2); + gd_eval_led_off(LED3); + gd_eval_led_off(LED4); + /* initialize CAN */ + can_networking_init(); + + /* enable CAN receive FIFO1 not empty interrupt */ + can_interrupt_enable(CANX, CAN_INT_RFNE1); + + /* initialize transmit message */ + can_struct_para_init(CAN_TX_MESSAGE_STRUCT, &transmit_message); + transmit_message.tx_sfid = 0x321; + transmit_message.tx_efid = 0x01; + transmit_message.tx_ft = CAN_FT_DATA; + transmit_message.tx_ff = CAN_FF_STANDARD; + transmit_message.tx_dlen = 1; + printf("\r\nplease press the CET key to transmit data!\r\n"); + + /* initialize receive message */ + can_struct_para_init(CAN_RX_MESSAGE_STRUCT, &receive_message); + + while(1){ + /* waiting for the CET key pressed */ + while(0 == gd_eval_key_state_get(KEY_CET)){ + /* if transmit_number is 0x10, set it to 0x00 */ + if(transmit_number == 0x10){ + transmit_number = 0x00; + }else{ + transmit_message.tx_data[0] = transmit_number++; + printf("\r\ntransmit data: %x\r\n", transmit_message.tx_data[0]); + /* transmit message */ + can_message_transmit(CANX, &transmit_message); + delay(); + /* waiting for CET key up */ + while(0 == gd_eval_key_state_get(KEY_CET)); + } + } + if(SET == receive_flag){ + gd_eval_led_toggle(LED2); + receive_flag = RESET; + printf("\r\nrecive data: %x\r\n", receive_message.rx_data[0]); + } + } +} + +/*! + \brief initialize CAN and filter + \param[in] can_parameter + \arg can_parameter_struct + \param[in] can_filter + \arg can_filter_parameter_struct + \param[out] none + \retval none +*/ +void can_networking_init(void) +{ + can_parameter_struct can_parameter; + can_filter_parameter_struct can_filter; + + can_struct_para_init(CAN_INIT_STRUCT, &can_parameter); + can_struct_para_init(CAN_FILTER_STRUCT, &can_filter); + + /* initialize CAN register */ + can_deinit(CANX); + + /* initialize CAN */ + can_parameter.time_triggered = DISABLE; + can_parameter.auto_bus_off_recovery = DISABLE; + can_parameter.auto_wake_up = DISABLE; + can_parameter.no_auto_retrans = DISABLE; + can_parameter.rec_fifo_overwrite = DISABLE; + can_parameter.trans_fifo_order = DISABLE; + can_parameter.working_mode = CAN_NORMAL_MODE; + can_parameter.resync_jump_width = CAN_BT_SJW_1TQ; + can_parameter.time_segment_1 = CAN_BT_BS1_5TQ; + can_parameter.time_segment_2 = CAN_BT_BS2_3TQ; + /* baudrate 1Mbps */ + can_parameter.prescaler = 6; + can_init(CANX, &can_parameter); + + /* initialize filter */ +#ifdef CAN0_USED + /* CAN0 filter number */ + can_filter.filter_number = 0; +#else + /* CAN1 filter number */ + can_filter.filter_number = 15; +#endif + /* initialize filter */ + can_filter.filter_mode = CAN_FILTERMODE_MASK; + can_filter.filter_bits = CAN_FILTERBITS_32BIT; + can_filter.filter_list_high = 0x0000; + can_filter.filter_list_low = 0x0000; + can_filter.filter_mask_high = 0x0000; + can_filter.filter_mask_low = 0x0000; + can_filter.filter_fifo_number = CAN_FIFO1; + can_filter.filter_enable = ENABLE; + can_filter_init(&can_filter); +} + +/*! + \brief configure the nested vectored interrupt controller + \param[in] none + \param[out] none + \retval none +*/ +void clic_config(void) +{ + eclic_global_interrupt_enable(); +#ifdef CAN0_USED + /* configure CAN0 CLIC */ + eclic_irq_enable(CAN0_RX1_IRQn,1,0); +#else + /* configure CAN1 CLIC */ + eclic_irq_enable(CAN1_RX1_IRQn,1,0); +#endif + +} + +/*! + \brief delay + \param[in] none + \param[out] none + \retval none +*/ +void delay(void) +{ + uint16_t nTime = 0x0000; + + for(nTime = 0; nTime < 0xFFFF; nTime++){ + } +} + +/*! + \brief configure the leds + \param[in] none + \param[out] none + \retval none +*/ +void led_config(void) +{ + gd_eval_led_init(LED1); + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + gd_eval_led_init(LED4); +} + +/*! + \brief configure GPIO + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* enable CAN clock */ + rcu_periph_clock_enable(RCU_CAN0); + rcu_periph_clock_enable(RCU_CAN1); + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_GPIOD); + rcu_periph_clock_enable(RCU_AF); + + /* configure CAN0 GPIO */ + gpio_init(GPIOD,GPIO_MODE_IPU,GPIO_OSPEED_50MHZ,GPIO_PIN_0); + gpio_init(GPIOD,GPIO_MODE_AF_PP,GPIO_OSPEED_50MHZ,GPIO_PIN_1); + gpio_pin_remap_config(GPIO_CAN0_FULL_REMAP,ENABLE); + + /* configure CAN1 GPIO */ + gpio_init(GPIOB,GPIO_MODE_IPU,GPIO_OSPEED_50MHZ,GPIO_PIN_5); + gpio_init(GPIOB,GPIO_MODE_AF_PP,GPIO_OSPEED_50MHZ,GPIO_PIN_6); + gpio_pin_remap_config(GPIO_CAN1_REMAP,ENABLE); +} + +/* retarget the C library printf function to the usart */ +int fputc(int ch, FILE *f) +{ + usart_data_transmit(EVAL_COM0, (uint8_t) ch); + while (RESET == usart_flag_get(EVAL_COM0, USART_FLAG_TBE)); + return ch; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_Devices/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_Devices/readme.txt new file mode 100644 index 0000000..81bc23a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CAN/communication_among_Devices/readme.txt @@ -0,0 +1,49 @@ +/*! + \file readme.txt + \brief description of the communication_among_Devices demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL board, it shows how to configure the CAN +peripheral to send and receive CAN frames in normal mode.The frames are sent and print +transmit data by pressing GET Key. When the frames are received, the receive data +will be printed and the LED2 will toggle. + + This example is tested with at least two GD32VF103V-EVAL boards. The same program example +is loaded in all boards and connect CAN_L and CAN_H pin of CAN0 or CAN1 to bus for sending +and receiving frames. + + User can select CAN0 or CAN1 cell using the private defines in main.c. + + JP4,JP13 and JP16 must be fitted. + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CRC/CRC_calculate/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CRC/CRC_calculate/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CRC/CRC_calculate/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CRC/CRC_calculate/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CRC/CRC_calculate/main.c new file mode 100644 index 0000000..6600787 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CRC/CRC_calculate/main.c @@ -0,0 +1,71 @@ +/*! + \file main.c + \brief CRC calculate demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" +#include + +uint32_t val = 0, valcrc = 0; + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + val = (uint32_t)0xabcd1234; + + /* initialize the LED2 and LED3, turn off them */ + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + gd_eval_led_off(LED2); + gd_eval_led_off(LED3); + rcu_periph_clock_enable(RCU_CRC); + + /* reset the CRC data register and calculate the CRC of the value */ + crc_data_register_reset(); + valcrc = crc_single_data_calculate(val); + + if(0xf7018a40 == valcrc){ + gd_eval_led_on(LED2); + gd_eval_led_on(LED3); + } + + while (1){ + } +} + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CRC/CRC_calculate/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CRC/CRC_calculate/readme.txt new file mode 100644 index 0000000..d95e364 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/CRC/CRC_calculate/readme.txt @@ -0,0 +1,41 @@ +/*! + \file readme.txt + \brief description of CRC example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it shows how to use CRC to +calculate the CRC value. + + In this demo, 1 CRC value is calculated for a 32-bit data. If the result is success, +turn on the LED2 and LED3. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_ADC_convert/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_ADC_convert/gd32vf103_it.c new file mode 100644 index 0000000..82db1f4 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_ADC_convert/gd32vf103_it.c @@ -0,0 +1,54 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_it.h" + +/*! + \brief this function handles ADC interrupt + \param[in] none + \param[out] none + \retval none +*/ +void ADC0_1_IRQHandler(void) +{ + uint16_t adc_value; + if(adc_interrupt_flag_get(ADC0, ADC_INT_FLAG_EOC)){ + adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOC); + adc_value = adc_regular_data_read(ADC0); + + dac_data_set(DAC0, DAC_ALIGN_12B_R, adc_value); + + dac_software_trigger_enable(DAC0); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_ADC_convert/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_ADC_convert/gd32vf103_it.h new file mode 100644 index 0000000..a6510fd --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_ADC_convert/gd32vf103_it.h @@ -0,0 +1,45 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ + +/* this function handles ADC0 and ADC1 interrupt */ +void ADC0_1_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_ADC_convert/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_ADC_convert/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_ADC_convert/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_ADC_convert/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_ADC_convert/main.c new file mode 100644 index 0000000..23bde31 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_ADC_convert/main.c @@ -0,0 +1,155 @@ +/*! + \file main.c + \brief DAC0 ADC convert demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" + +void rcu_config(void); +void gpio_config(void); +void eclic_config(void); +void adc_config(void); +void dac_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + rcu_config(); + gpio_config(); + eclic_config(); + adc_config(); + dac_config(); + + while(1){ + } +} + +/*! + \brief configure the RCU of peripherals + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable the clock of peripherals */ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOC); + rcu_periph_clock_enable(RCU_ADC0); + rcu_periph_clock_enable(RCU_DAC); +} + +/*! + \brief configure the related GPIO + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* config the GPIO as analog mode */ + gpio_init(GPIOC, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_3); + /* once enabled the DAC, the corresponding GPIO pin is connected to the DAC converter automatically */ + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_4); +} + +/*! + \brief configure interrupt priority + \param[in] none + \param[out] none + \retval none +*/ +void eclic_config(void) +{ + eclic_global_interrupt_enable(); + eclic_irq_enable(ADC0_1_IRQn, 2, 0); +} + +/*! + \brief configure the ADC + \param[in] none + \param[out] none + \retval none +*/ +void adc_config(void) +{ + /* ADC continous function enable */ + adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, ENABLE); + /* ADC data alignment config */ + adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT); + /* ADC channel length config */ + adc_channel_length_config(ADC0, ADC_REGULAR_CHANNEL, 1); + /* ADC regular channel config */ + adc_regular_channel_config(ADC0, 0, ADC_CHANNEL_13, ADC_SAMPLETIME_55POINT5); + /* ADC external trigger enable */ + adc_external_trigger_config(ADC0, ADC_REGULAR_CHANNEL, ENABLE); + /* ADC trigger config */ + adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_NONE); + + /* enable ADC interface */ + adc_enable(ADC0); + + /* ADC calibration and reset calibration */ + adc_calibration_enable(ADC0); + + /* ADC interrupt enable */ + adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOC); + adc_interrupt_enable(ADC0, ADC_INT_EOC); + + /* enable ADC software trigger */ + adc_software_trigger_enable(ADC0, ADC_REGULAR_CHANNEL); +} + +/*! + \brief configure the DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_config(void) +{ + dac_deinit(); + /* configure the DAC0 */ + dac_trigger_source_config(DAC0, DAC_TRIGGER_SOFTWARE); + dac_trigger_enable(DAC0); + dac_wave_mode_config(DAC0, DAC_WAVE_DISABLE); + dac_output_buffer_enable(DAC0); + + /* enable DAC0 for DAC0 */ + dac_enable(DAC0); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_ADC_convert/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_ADC_convert/readme.txt new file mode 100644 index 0000000..cec8b5b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_ADC_convert/readme.txt @@ -0,0 +1,37 @@ +/*! + \file readme.txt + \brief description of DAC0_ADC_convert example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it shows how to use DAC0 to generate +a signal from ADC. In the ADC interrupt, ADC data transfer from ADC_RDATA to DAC0_R8DH. +The DAC0 output pin is configured PA4. The signal can be observed through the oscilloscope. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_DMA_convert/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_DMA_convert/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_DMA_convert/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_DMA_convert/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_DMA_convert/main.c new file mode 100644 index 0000000..5ab19fc --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_DMA_convert/main.c @@ -0,0 +1,158 @@ +/*! + \file main.c + \brief DAC0 DMA convert demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" + +#define CONVERT_NUM (10U) +#define DAC0_R8DH_ADDRESS (0x40007410) +const uint8_t convertarr[CONVERT_NUM] = {0x00, 0x33, 0x66, 0x99, 0xCC, 0xFF, 0xCC, 0x99, 0x66, 0x33}; + +void rcu_config(void); +void gpio_config(void); +void dma_config(void); +void dac_config(void); +void timer5_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + rcu_config(); + gpio_config(); + dma_config(); + dac_config(); + timer5_config(); + while (1){ + } +} + +/*! + \brief configure the RCU of peripherals + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable the clock of peripherals */ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_DMA1); + rcu_periph_clock_enable(RCU_DAC); + rcu_periph_clock_enable(RCU_TIMER5); +} + +/*! + \brief configure the related GPIO + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* once enabled the DAC, the corresponding GPIO pin is connected to the DAC converter automatically */ + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_4); +} + +/*! + \brief configure the DMA + \param[in] none + \param[out] none + \retval none +*/ +void dma_config(void) +{ + dma_parameter_struct dma_struct; + /* clear all the interrupt flags */ + dma_flag_clear(DMA1, DMA_CH2, DMA_INTF_GIF); + dma_flag_clear(DMA1, DMA_CH2, DMA_INTF_FTFIF); + dma_flag_clear(DMA1, DMA_CH2, DMA_INTF_HTFIF); + dma_flag_clear(DMA1, DMA_CH2, DMA_INTF_ERRIF); + + /* configure the DMA1 channel 2 */ + dma_struct.periph_addr = DAC0_R8DH_ADDRESS; + dma_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; + dma_struct.memory_addr = (uint32_t)convertarr; + dma_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; + dma_struct.number = CONVERT_NUM; + dma_struct.priority = DMA_PRIORITY_ULTRA_HIGH; + dma_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_struct.direction = DMA_MEMORY_TO_PERIPHERAL; + dma_init(DMA1, DMA_CH2, &dma_struct); + + dma_circulation_enable(DMA1, DMA_CH2); + dma_channel_enable(DMA1, DMA_CH2); +} + +/*! + \brief configure the DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_config(void) +{ + dac_deinit(); + /* configure the DAC0 */ + dac_trigger_source_config(DAC0, DAC_TRIGGER_T5_TRGO); + dac_trigger_enable(DAC0); + dac_wave_mode_config(DAC0, DAC_WAVE_DISABLE); + dac_output_buffer_disable(DAC0); + + /* enable DAC0 and DMA for DAC0 */ + dac_enable(DAC0); + dac_dma_enable(DAC0); +} + +/*! + \brief configure the TIMER5 + \param[in] none + \param[out] none + \retval none +*/ +void timer5_config(void) +{ + /* configure the TIMER5 */ + timer_prescaler_config(TIMER5, 0xF, TIMER_PSC_RELOAD_UPDATE); + timer_autoreload_value_config(TIMER5, 0xFF); + timer_master_output_trigger_source_select(TIMER5, TIMER_TRI_OUT_SRC_UPDATE); + + timer_enable(TIMER5); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_DMA_convert/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_DMA_convert/readme.txt new file mode 100644 index 0000000..a93f015 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_DMA_convert/readme.txt @@ -0,0 +1,38 @@ +/*! + \file readme.txt + \brief description of DAC0_DMA_convert example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it shows how to use DAC0 to generate +a staircase-shaped signal. TIMER5 is chosen to trigger DAC0 and DMA is configured to transfer +data from memory to DAC0_R8DH. The DAC0 output pin is configured PA4. The signal can be +observed through the oscilloscope. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_EXTI_trigger/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_EXTI_trigger/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_EXTI_trigger/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_EXTI_trigger/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_EXTI_trigger/main.c new file mode 100644 index 0000000..9309be7 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_EXTI_trigger/main.c @@ -0,0 +1,126 @@ +/*! + \file main.c + \brief DAC0 in EXTI trigger mode demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" + +void rcu_config(void); +void gpio_config(void); +void dac_config(void); +void exti_line9_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + rcu_config(); + gpio_config(); + dac_config(); + exti_line9_config(); + + while (1){ + } +} + +/*! + \brief configure the EXTI interrupt line 9. PE9 is used for an example. + \param[in] none + \param[out] none + \retval none +*/ +void exti_line9_config(void) +{ + /* enable the key clock */ + rcu_periph_clock_enable(RCU_GPIOE); + rcu_periph_clock_enable(RCU_AF); + + /* configure button pin as input */ + gpio_init(GPIOE, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_9); + + /* connect key EXTI line to key GPIO pin */ + gpio_exti_source_select(GPIO_EVENT_PORT_GPIOE, GPIO_EVENT_PIN_9); + + /* configure key EXTI line */ + exti_init(EXTI_9, EXTI_EVENT, EXTI_TRIG_RISING); + exti_interrupt_flag_clear(EXTI_9); +} + +/*! + \brief configure the RCU of peripherals + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable the clock of peripherals */ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_DAC); +} + +/*! + \brief configure the related GPIO + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* once enabled the DAC, the corresponding GPIO pin is connected to the DAC converter automatically */ + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_4); +} + +/*! + \brief configure the DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_config(void) +{ + dac_deinit(); + /* configure the DAC0 */ + dac_trigger_source_config(DAC0, DAC_TRIGGER_EXTI_9); + dac_trigger_enable(DAC0); + dac_wave_mode_config(DAC0, DAC_WAVE_MODE_LFSR); + dac_lfsr_noise_config(DAC0, DAC_LFSR_BITS11_0); + dac_output_buffer_disable(DAC0); + + /* enable DAC0 and set data */ + dac_enable(DAC0); + dac_data_set(DAC0, DAC_ALIGN_12B_R, 0); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_EXTI_trigger/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_EXTI_trigger/readme.txt new file mode 100644 index 0000000..eb43b14 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_EXTI_trigger/readme.txt @@ -0,0 +1,38 @@ +/*! + \file readme.txt + \brief description of DAC0_EXTI_trigger example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it shows how to use EXTI line 9 +to trigger DAC0. The DAC0 output pin is configured PA4. Connect one key (PA0 for +example) and GPIO PE9 with Dupont line. Press the key (Wakeup for example) for many +times, the variations of the wave can be observed through the oscilloscope. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_LFSR_noise_mode/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_LFSR_noise_mode/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_LFSR_noise_mode/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_LFSR_noise_mode/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_LFSR_noise_mode/main.c new file mode 100644 index 0000000..97c9328 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_LFSR_noise_mode/main.c @@ -0,0 +1,119 @@ +/*! + \file main.c + \brief DAC0 in LFSR noise mode demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" + +void rcu_config(void); +void gpio_config(void); +void dac_config(void); +void timer5_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + rcu_config(); + gpio_config(); + dac_config(); + timer5_config(); + while (1){ + } +} + +/*! + \brief configure the RCU of peripherals + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable the clock of peripherals */ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_DAC); + rcu_periph_clock_enable(RCU_TIMER5); +} + +/*! + \brief configure the related GPIO + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* once enabled the DAC, the corresponding GPIO pin is connected to the DAC converter automatically */ + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_4); +} + +/*! + \brief configure the DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_config(void) +{ + dac_deinit(); + /* configure the DAC0 */ + dac_trigger_source_config(DAC0, DAC_TRIGGER_T5_TRGO); + dac_trigger_enable(DAC0); + dac_wave_mode_config(DAC0, DAC_WAVE_MODE_LFSR); + dac_lfsr_noise_config(DAC0, DAC_LFSR_BITS10_0); + dac_output_buffer_disable(DAC0); + + /* enable DAC0 and set data */ + dac_enable(DAC0); + dac_data_set(DAC0, DAC_ALIGN_12B_R, 0x7F0); +} + +/*! + \brief configure the TIMER5 + \param[in] none + \param[out] none + \retval none +*/ +void timer5_config(void) +{ + /* configure the TIMER5 */ + timer_prescaler_config(TIMER5, 0xF, TIMER_PSC_RELOAD_UPDATE); + timer_autoreload_value_config(TIMER5, 0x1FF); + timer_master_output_trigger_source_select(TIMER5, TIMER_TRI_OUT_SRC_UPDATE); + + timer_enable(TIMER5); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_LFSR_noise_mode/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_LFSR_noise_mode/readme.txt new file mode 100644 index 0000000..c6385a2 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC0_LFSR_noise_mode/readme.txt @@ -0,0 +1,37 @@ +/*! + \file readme.txt + \brief description of DAC0_LFSR_noise_mode example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it shows how to use DAC0 to generate +LFSR noise wave. TIMER5 is chosen to trigger DAC0. The DAC0 output pin is configured PA4. +The LFSR noise wave can be observed through the oscilloscope. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC1_triangle_noise_mode/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC1_triangle_noise_mode/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC1_triangle_noise_mode/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC1_triangle_noise_mode/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC1_triangle_noise_mode/main.c new file mode 100644 index 0000000..4758da0 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC1_triangle_noise_mode/main.c @@ -0,0 +1,119 @@ +/*! + \file main.c + \brief DAC1 in triangle noise mode demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" + +void rcu_config(void); +void gpio_config(void); +void dac_config(void); +void timer6_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + rcu_config(); + gpio_config(); + dac_config(); + timer6_config(); + while (1){ + } +} + +/*! + \brief configure the RCU of peripherals + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable the clock of peripherals */ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_DAC); + rcu_periph_clock_enable(RCU_TIMER6); +} + +/*! + \brief configure the related GPIO + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* once enabled the DAC, the corresponding GPIO pin is connected to the DAC converter automatically */ + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_5); +} + +/*! + \brief configure the DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_config(void) +{ + dac_deinit(); + /* configure the DAC1 */ + dac_trigger_source_config(DAC1, DAC_TRIGGER_T6_TRGO); + dac_trigger_enable(DAC1); + dac_wave_mode_config(DAC1, DAC_WAVE_MODE_TRIANGLE); + dac_triangle_noise_config(DAC1, DAC_TRIANGLE_AMPLITUDE_2047); + dac_output_buffer_disable(DAC1); + + /* enable DAC1 and set data */ + dac_enable(DAC1); + dac_data_set(DAC1, DAC_ALIGN_12B_R, 0x7F0); +} + +/*! + \brief configure the TIMER6 + \param[in] none + \param[out] none + \retval none +*/ +void timer6_config(void) +{ + /* configure the TIMER6 */ + timer_prescaler_config(TIMER6, 0xF, TIMER_PSC_RELOAD_UPDATE); + timer_autoreload_value_config(TIMER6, 0x1FF); + timer_master_output_trigger_source_select(TIMER6, TIMER_TRI_OUT_SRC_UPDATE); + + timer_enable(TIMER6); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC1_triangle_noise_mode/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC1_triangle_noise_mode/readme.txt new file mode 100644 index 0000000..1b23753 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DAC1_triangle_noise_mode/readme.txt @@ -0,0 +1,37 @@ +/*! + \file readme.txt + \brief description of DAC1_triangle_noise_mode example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it shows how to use DAC1 to generate +triangle noise wave. TIMER6 is chosen to trigger DAC1. The DAC1 output pin is configured +PA5. The triangle noise wave can be observed through the oscilloscope. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_independent_trigger_LFSR_noise/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_independent_trigger_LFSR_noise/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_independent_trigger_LFSR_noise/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_independent_trigger_LFSR_noise/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_independent_trigger_LFSR_noise/main.c new file mode 100644 index 0000000..269386d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_independent_trigger_LFSR_noise/main.c @@ -0,0 +1,145 @@ +/*! + \file main.c + \brief DAC concurrent mode independent trigger with different LFSR demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" + +void rcu_config(void); +void gpio_config(void); +void dac_config(void); +void timer5_config(void); +void timer6_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + rcu_config(); + gpio_config(); + dac_config(); + timer5_config(); + timer6_config(); + while (1){ + } +} + +/*! + \brief configure the RCU of peripherals + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable the clock of peripherals */ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_DAC); + rcu_periph_clock_enable(RCU_TIMER5); + rcu_periph_clock_enable(RCU_TIMER6); +} + +/*! + \brief configure the related GPIO + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* once enabled the DAC, the corresponding GPIO pin is connected to the DAC converter automatically */ + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_4 | GPIO_PIN_5); +} + +/*! + \brief configure the DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_config(void) +{ + dac_deinit(); + /* configure the DAC0 */ + dac_trigger_source_config(DAC0, DAC_TRIGGER_T5_TRGO); + dac_trigger_enable(DAC0); + dac_wave_mode_config(DAC0, DAC_WAVE_MODE_LFSR); + dac_lfsr_noise_config(DAC0, DAC_LFSR_BITS9_0); + dac_output_buffer_disable(DAC0); + + /* configure the DAC1 */ + dac_trigger_source_config(DAC1, DAC_TRIGGER_T6_TRGO); + dac_trigger_enable(DAC1); + dac_wave_mode_config(DAC1, DAC_WAVE_MODE_LFSR); + dac_lfsr_noise_config(DAC1, DAC_LFSR_BITS10_0); + dac_output_buffer_disable(DAC1); + + /* enable DAC concurrent mode and set data */ + dac_concurrent_enable(); + dac_concurrent_data_set(DAC_ALIGN_12B_R, 0x7F0, 0x7F0); +} + +/*! + \brief configure the TIMER5 + \param[in] none + \param[out] none + \retval none +*/ +void timer5_config(void) +{ + /* configure the TIMER5 */ + timer_prescaler_config(TIMER5, 0xF, TIMER_PSC_RELOAD_UPDATE); + timer_autoreload_value_config(TIMER5, 0x1FF); + timer_master_output_trigger_source_select(TIMER5, TIMER_TRI_OUT_SRC_UPDATE); + + timer_enable(TIMER5); +} + +/*! + \brief configure the TIMER6 + \param[in] none + \param[out] none + \retval none +*/ +void timer6_config(void) +{ + /* configure the TIMER6 */ + timer_prescaler_config(TIMER6, 0xF, TIMER_PSC_RELOAD_UPDATE); + timer_autoreload_value_config(TIMER6, 0x1FF); + timer_master_output_trigger_source_select(TIMER6, TIMER_TRI_OUT_SRC_UPDATE); + + timer_enable(TIMER6); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_independent_trigger_LFSR_noise/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_independent_trigger_LFSR_noise/readme.txt new file mode 100644 index 0000000..ef3b89a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_independent_trigger_LFSR_noise/readme.txt @@ -0,0 +1,39 @@ +/*! + \file readme.txt + \brief description of DACC_independent_trigger_LFSR_noise example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it shows how to use DAC concurrent mode +independent trigger to generate LFSR noise wave with different configurations. TIMER5 is +chosen to trigger DAC0. TIMER6 is chosen to trigger DAC1. The DAC0 output pin is configured +PA4 and DAC1 output pin is configured PA5. The LFSR noise wave can be observed through the +oscilloscope. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_output_voltage/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_output_voltage/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_output_voltage/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_output_voltage/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_output_voltage/main.c new file mode 100644 index 0000000..efb55be --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_output_voltage/main.c @@ -0,0 +1,106 @@ +/*! + \file main.c + \brief DAC concurrent mode output voltage demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" + +#define DAC_OUT_VAL0 0x7FF0 +#define DAC_OUT_VAL1 0x1FF0 + +void rcu_config(void); +void gpio_config(void); +void dac_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + rcu_config(); + gpio_config(); + dac_config(); + while (1){ + } +} + +/*! + \brief configure the RCU of peripherals + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable the clock of peripherals */ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_DAC); +} + +/*! + \brief configure the related GPIO + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* once enabled the DAC, the corresponding GPIO pin is connected to the DAC converter automatically */ + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_4 | GPIO_PIN_5); +} + +/*! + \brief configure the DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_config(void) +{ + dac_deinit(); + /* configure the DAC0 */ + dac_trigger_disable(DAC0); + dac_wave_mode_config(DAC0, DAC_WAVE_DISABLE); + dac_output_buffer_enable(DAC0); + + /* configure the DAC1 */ + dac_trigger_disable(DAC1); + dac_wave_mode_config(DAC1, DAC_WAVE_DISABLE); + dac_output_buffer_enable(DAC1); + + /* enable DAC concurrent mode and set data */ + dac_concurrent_enable(); + dac_concurrent_data_set(DAC_ALIGN_12B_L, DAC_OUT_VAL0, DAC_OUT_VAL1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_output_voltage/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_output_voltage/readme.txt new file mode 100644 index 0000000..17b92d3 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_output_voltage/readme.txt @@ -0,0 +1,38 @@ +/*! + \file readme.txt + \brief description of DACC_output_voltage example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it shows how to use DAC concurrent mode +output voltage. No trigger source is chosen to trigger DAC. The DAC0 output pin is configured +PA4 and DAC1 output pin is configured PA5. There are two different voltage in PA4 and PA5. The +voltage of PA4 is VREF/2 and the voltage of PA5 is VREF/8. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_simultaneous_trigger_triangle_noise/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_simultaneous_trigger_triangle_noise/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_simultaneous_trigger_triangle_noise/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_simultaneous_trigger_triangle_noise/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_simultaneous_trigger_triangle_noise/main.c new file mode 100644 index 0000000..093e359 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_simultaneous_trigger_triangle_noise/main.c @@ -0,0 +1,126 @@ +/*! + \file main.c + \brief DAC concurrent mode simultaneous trigger with same triangle wave demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" + +void rcu_config(void); +void gpio_config(void); +void dac_config(void); +void timer5_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + rcu_config(); + gpio_config(); + dac_config(); + timer5_config(); + while (1){ + } +} + +/*! + \brief configure the RCU of peripherals + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable the clock of peripherals */ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_DAC); + rcu_periph_clock_enable(RCU_TIMER5); +} + +/*! + \brief configure the related GPIO + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* once enabled the DAC, the corresponding GPIO pin is connected to the DAC converter automatically */ + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_4 | GPIO_PIN_5); +} + +/*! + \brief configure the DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_config(void) +{ + dac_deinit(); + /* configure the DAC0 */ + dac_trigger_source_config(DAC0, DAC_TRIGGER_T5_TRGO); + dac_trigger_enable(DAC0); + dac_wave_mode_config(DAC0, DAC_WAVE_MODE_TRIANGLE); + dac_triangle_noise_config(DAC0, DAC_TRIANGLE_AMPLITUDE_1023); + dac_output_buffer_disable(DAC0); + + /* configure the DAC1 */ + dac_trigger_source_config(DAC1, DAC_TRIGGER_T5_TRGO); + dac_trigger_enable(DAC1); + dac_wave_mode_config(DAC1, DAC_WAVE_MODE_TRIANGLE); + dac_triangle_noise_config(DAC1, DAC_TRIANGLE_AMPLITUDE_1023); + dac_output_buffer_disable(DAC1); + + /* enable DAC concurrent mode and set data */ + dac_concurrent_enable(); + dac_concurrent_data_set(DAC_ALIGN_12B_R, 0x7F0, 0x1F0); +} + +/*! + \brief configure the TIMER5 + \param[in] none + \param[out] none + \retval none +*/ +void timer5_config(void) +{ + /* configure the TIMER5 */ + timer_prescaler_config(TIMER5, 0xF, TIMER_PSC_RELOAD_UPDATE); + timer_autoreload_value_config(TIMER5, 0x1FF); + timer_master_output_trigger_source_select(TIMER5, TIMER_TRI_OUT_SRC_UPDATE); + + timer_enable(TIMER5); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_simultaneous_trigger_triangle_noise/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_simultaneous_trigger_triangle_noise/readme.txt new file mode 100644 index 0000000..2f94488 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_simultaneous_trigger_triangle_noise/readme.txt @@ -0,0 +1,38 @@ +/*! + \file readme.txt + \brief description of DACC_simultaneous_trigger_triangle_noise example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it shows how to use DAC concurrent mode +simultaneous trigger to generate triangle noise wave with same amplitude. TIMER5 is chosen +to trigger DAC0 and DAC1. The DAC0 output pin is configured PA4 and DAC1 output pin is configured +PA5. The triangle noise wave can be observed through the oscilloscope. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_software_trigger_LFSR_noise/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_software_trigger_LFSR_noise/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_software_trigger_LFSR_noise/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_software_trigger_LFSR_noise/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_software_trigger_LFSR_noise/main.c new file mode 100644 index 0000000..6bdbef1 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_software_trigger_LFSR_noise/main.c @@ -0,0 +1,108 @@ +/*! + \file main.c + \brief DAC concurrent mode software trigger LFSR noise wave demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" + +void rcu_config(void); +void gpio_config(void); +void dac_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + rcu_config(); + gpio_config(); + dac_config(); + while (1){ + dac_concurrent_software_trigger_enable(); + } +} + +/*! + \brief configure the RCU of peripherals + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable the clock of peripherals */ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_DAC); +} + +/*! + \brief configure the related GPIO + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* once enabled the DAC, the corresponding GPIO pin is connected to the DAC converter automatically */ + gpio_init(GPIOA, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, GPIO_PIN_4 | GPIO_PIN_5); +} + +/*! + \brief configure the DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_config(void) +{ + dac_deinit(); + /* configure the DAC0 */ + dac_trigger_source_config(DAC0, DAC_TRIGGER_SOFTWARE); + dac_trigger_enable(DAC0); + dac_wave_mode_config(DAC0, DAC_WAVE_MODE_LFSR); + dac_lfsr_noise_config(DAC0, DAC_LFSR_BITS10_0); + dac_output_buffer_disable(DAC0); + + /* configure the DAC1 */ + dac_trigger_source_config(DAC1, DAC_TRIGGER_SOFTWARE); + dac_trigger_enable(DAC1); + dac_wave_mode_config(DAC1, DAC_WAVE_MODE_LFSR); + dac_lfsr_noise_config(DAC1, DAC_LFSR_BITS9_0); + dac_output_buffer_disable(DAC1); + + /* enable DAC concurrent mode and set data */ + dac_concurrent_enable(); + dac_concurrent_data_set(DAC_ALIGN_12B_R, 0x600, 0x500); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_software_trigger_LFSR_noise/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_software_trigger_LFSR_noise/readme.txt new file mode 100644 index 0000000..19c1978 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DAC/DACC_software_trigger_LFSR_noise/readme.txt @@ -0,0 +1,38 @@ +/*! + \file readme.txt + \brief description of DACC_software_trigger_LFSR_noise example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it shows how to use DAC concurrent +mode software trigger to generate LFSR noise wave with different configurations. The +DAC0 output pin is configured PA4 and DAC1 output pin is configured PA5. The LFSR +noise wave can be observed through the oscilloscope. \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DBG/Timer1_stop/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DBG/Timer1_stop/main.c new file mode 100644 index 0000000..cf74600 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DBG/Timer1_stop/main.c @@ -0,0 +1,137 @@ +/*! + \file main.c + \brief debug TIMER0 when the MCU is in debug mode + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" +#include "systick.h" +#include + +void gpio_configuration(void); +void timer_configuration(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ + +int main(void) +{ + dbg_periph_disable(DBG_TIMER1_HOLD); + gpio_configuration(); + gd_eval_led_init(LED2); + timer_configuration(); + + /* keep TIMER1 counter when the mcu is in debug mode */ + dbg_periph_enable(DBG_TIMER1_HOLD); + + while(1){ + /* you can set breakpoint here, then look over the register in TIMER1 */ + delay_1ms(500); + /* you can set breakpoint here, then look over the register in TIMER1 */ + /* toggle LED2 output status every second */ + gd_eval_led_toggle(LED2); + } +} + +/*! + \brief configure the GPIO ports + \param[in] none + \param[out] none + \retval none +*/ +void gpio_configuration(void) +{ + rcu_periph_clock_enable(RCU_AF); + rcu_periph_clock_enable(RCU_GPIOB); + gpio_pin_remap_config(GPIO_TIMER1_FULL_REMAP, ENABLE); + /* configure PB3/PB10/PB11(TIMER1 CH1/CH2/CH3) as alternate function */ + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_3 | GPIO_PIN_10 | GPIO_PIN_11); +} + +/*! + \brief configure the TIMER peripheral + \param[in] none + \param[out] none + \retval none +*/ +void timer_configuration(void) +{ + + /* TIMER1 configuration: generate 3 PWM signals with 3 different duty cycles: + TIMER1CLK = SystemCoreClock / 108 = 1MHz + TIMER1 channel 1 duty cycle = 4000/ 16000 = 25% + TIMER1 channel 2 duty cycle = 8000/ 16000 = 50% + TIMER1 channel 3 duty cycle = 12000/ 16000 = 75% */ + + timer_parameter_struct timer_initpara; + timer_oc_parameter_struct timer_ocintpara; + + rcu_periph_clock_enable(RCU_TIMER1); + + /* TIMER1 configuration */ + timer_deinit(TIMER1); + /* TIMER1 configuration */ + timer_initpara.prescaler = 107; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 15999; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER1, &timer_initpara); + + /* CH1, CH2 and CH3 configuration in PWM mode */ + timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocintpara.outputstate = TIMER_CCX_ENABLE; + timer_channel_output_config(TIMER1, TIMER_CH_1, &timer_ocintpara); + timer_channel_output_config(TIMER1, TIMER_CH_2, &timer_ocintpara); + timer_channel_output_config(TIMER1, TIMER_CH_3, &timer_ocintpara); + + timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, 4000); + timer_channel_output_mode_config(TIMER1, TIMER_CH_1, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER1, TIMER_CH_1, TIMER_OC_SHADOW_DISABLE); + + timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_2, 8000); + timer_channel_output_mode_config(TIMER1, TIMER_CH_2, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER1, TIMER_CH_2, TIMER_OC_SHADOW_DISABLE); + + timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_3, 12000); + timer_channel_output_mode_config(TIMER1, TIMER_CH_3, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER1, TIMER_CH_3, TIMER_OC_SHADOW_DISABLE); + + /* auto-reload preload enable */ + timer_auto_reload_shadow_enable(TIMER1); + timer_enable(TIMER1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DBG/Timer1_stop/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DBG/Timer1_stop/readme.txt new file mode 100644 index 0000000..1b0200c --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DBG/Timer1_stop/readme.txt @@ -0,0 +1,51 @@ +/*! + \file readme.txt + \brief description of the DBG demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows that, when the TIMER1_HOLD +bit in DBG control register(DBG_CTL) is set and the core halted, the TIMER1 counter stop +counting and the PWM outputs of all channels are stopped as well. It's benefit for debuging. + + The TIMER1 counter clock used is 1MHz. +The Three Duty cycles are computed as the following description: +The channel 1 duty cycle is set to 25%. +The channel 2 duty cycle is set to 50%. +The channel 3 duty cycle is set to 75%. + + Connect the TIMER1 pins to an oscilloscope and monitor the different waveforms: +- TIMER1_CH1 pin (PB3) +- TIMER1_CH2 pin (PB10) +- TIMER1_CH3 pin (PB11) + + In debug mode, when the core is stopped, the PWM outputs of all the channels of +TIMER1 will be stopped. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DBG/Timer1_stop/systick.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DBG/Timer1_stop/systick.c new file mode 100644 index 0000000..d891c3b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DBG/Timer1_stop/systick.c @@ -0,0 +1,57 @@ +/*! + \file systick.c + \brief the systick configuration file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" + +/*! + \brief delay a time in milliseconds + \param[in] count: count in milliseconds + \param[out] none + \retval none +*/ +void delay_1ms(uint32_t count) +{ + uint64_t start_mtime, delta_mtime; + + // Don't start measuruing until we see an mtime tick + uint64_t tmp = get_timer_value(); + do { + start_mtime = get_timer_value(); + } while (start_mtime == tmp); + + do { + delta_mtime = get_timer_value() - start_mtime; + }while(delta_mtime <(SystemCoreClock/4000.0 *count )); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DBG/Timer1_stop/systick.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DBG/Timer1_stop/systick.h new file mode 100644 index 0000000..9a74c22 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DBG/Timer1_stop/systick.h @@ -0,0 +1,42 @@ +/*! + \file systick.h + \brief the header file of systick + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef SYS_TICK_H +#define SYS_TICK_H + +#include + +void delay_1ms(uint32_t count); + +#endif /* SYS_TICK_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Flash_to_ram/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Flash_to_ram/gd32vf103_it.c new file mode 100644 index 0000000..ef096c8 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Flash_to_ram/gd32vf103_it.c @@ -0,0 +1,51 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_it.h" + +extern __IO uint32_t g_dmacomplete_flag; + +/*! + \brief this function handles DMA0_Channel0_IRQHandler interrupt + \param[in] none + \param[out] none + \retval none +*/ +void DMA0_Channel0_IRQHandler(void) +{ + if(dma_interrupt_flag_get(DMA0, DMA_CH0, DMA_INT_FLAG_FTF)){ + g_dmacomplete_flag = 1; + dma_interrupt_flag_clear(DMA0, DMA_CH0, DMA_INT_FLAG_G); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Flash_to_ram/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Flash_to_ram/gd32vf103_it.h new file mode 100644 index 0000000..c569dcf --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Flash_to_ram/gd32vf103_it.h @@ -0,0 +1,44 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ +/* DMA0_Channel0 handle function */ +void DMA0_Channel0_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Flash_to_ram/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Flash_to_ram/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Flash_to_ram/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Flash_to_ram/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Flash_to_ram/main.c new file mode 100644 index 0000000..fbfe1fa --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Flash_to_ram/main.c @@ -0,0 +1,241 @@ +/*! + \file main.c + \brief flash to ram demo + + \version 2019-06-05, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" +#include +#include "riscv_encoding.h" + +#define TRANSFER_NUM 0x400 /* configuration value in bytes */ +#define FMC_PAGE_SIZE ((uint16_t)0x800) +#define BANK0_WRITE_START_ADDR ((uint32_t)0x08004000) + +void rcu_config(void); +void config_clic_irqs (void); +void led_config(void); + +__IO uint32_t g_dmacomplete_flag = 0; +uint8_t g_destbuf[TRANSFER_NUM]; +const uint32_t transdata = 0x3210ABCD; +fmc_state_enum fmcstatus = FMC_READY; + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + uint32_t i, count; + uint32_t *ptrd; + uint32_t address = 0x00; + ErrStatus access_flag = SUCCESS; + dma_parameter_struct dma_init_struct; + uint32_t wperror = 0; + + /* system clocks configuration */ + rcu_config(); + /* CLIC configuration */ + config_clic_irqs(); + /* LED configuration */ + led_config() ; + /* unlock the flash bank1 program erase controller */ + fmc_unlock(); + + /* define the number of page to be erased */ + count = TRANSFER_NUM / FMC_PAGE_SIZE; + /* clear all pending flags */ + fmc_flag_clear(FMC_FLAG_PGERR); + fmc_flag_clear(FMC_FLAG_WPERR); + fmc_flag_clear(FMC_FLAG_END); + + /* erase the flash pages */ + for(i = 0; i <= count; i++){ + fmcstatus = fmc_page_erase(BANK0_WRITE_START_ADDR + (FMC_PAGE_SIZE * i)); + wperror += (fmcstatus == FMC_WPERR); + fmc_flag_clear(FMC_FLAG_PGERR); + fmc_flag_clear(FMC_FLAG_WPERR); + fmc_flag_clear(FMC_FLAG_END); + } + + if(wperror != 0){ + while(1); + } + + /* unlock the flash bank1 program erase controller */ + fmc_lock(); + + ptrd = (uint32_t*)BANK0_WRITE_START_ADDR; + count = TRANSFER_NUM / sizeof(*ptrd); + + for(i = 0; i < count; i++){ + if(0xFFFFFFFF != *ptrd){ + access_flag = ERROR; + break; + } + ptrd++; + } + + if(ERROR == access_flag){ + while(1); + } + + /* unlock the flash bank1 program erase controller */ + fmc_unlock(); + /* clear all pending flags */ + fmc_flag_clear(FMC_FLAG_PGERR); + fmc_flag_clear(FMC_FLAG_WPERR); + fmc_flag_clear(FMC_FLAG_END); + + /* program flash bank1 */ + address = BANK0_WRITE_START_ADDR; + wperror = 0; + count = BANK0_WRITE_START_ADDR + TRANSFER_NUM; + + while(address < count){ + fmcstatus = fmc_word_program(address, transdata); + address = address + 4; + wperror += (FMC_WPERR == fmcstatus); + fmc_flag_clear(FMC_FLAG_PGERR); + fmc_flag_clear(FMC_FLAG_WPERR); + fmc_flag_clear(FMC_FLAG_END); + } + + if(wperror != 0){ + while(1); + } + + fmc_lock(); + + memset(g_destbuf ,0 ,TRANSFER_NUM); + + /* DMA0 channel0 initialize */ + dma_deinit(DMA0, DMA_CH0); + dma_struct_para_init(&dma_init_struct); + + dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY; + dma_init_struct.memory_addr = (uint32_t)g_destbuf; + dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; + dma_init_struct.number = TRANSFER_NUM; + dma_init_struct.periph_addr = (uint32_t)BANK0_WRITE_START_ADDR; + dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_ENABLE; + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; + dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH; + dma_init(DMA0, DMA_CH0, &dma_init_struct); + /* DMA0 channel0 mode configuration */ + dma_circulation_disable(DMA0, DMA_CH0); + dma_memory_to_memory_enable(DMA0, DMA_CH0); + /* DMA0 channel0 interrupt configuration */ + dma_interrupt_enable(DMA0, DMA_CH0, DMA_INT_FTF); + /* enable DMA0 transfer */ + dma_channel_enable(DMA0, DMA_CH0); + + /* wait DMA interrupt */ + while(0 == g_dmacomplete_flag); + + /* compare destdata with transdata */ + ptrd = (uint32_t *)g_destbuf; + count = TRANSFER_NUM / sizeof(*ptrd); + + for(i = 0; i < count; i++){ + if(transdata != *ptrd){ + access_flag = ERROR; + break; + } + ptrd++; + } + + /* transfer success */ + if(access_flag != ERROR){ + gd_eval_led_on(LED1); + gd_eval_led_on(LED2); + gd_eval_led_on(LED3); + gd_eval_led_on(LED4); + }else{ + gd_eval_led_on(LED1); + gd_eval_led_on(LED3); + } + + while(1){ + } +} + +/*! + \brief configure LED + \param[in] none + \param[out] none + \retval none +*/ +void led_config(void) +{ + gd_eval_led_init(LED1); + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + gd_eval_led_init(LED4); + + /* LED off */ + gd_eval_led_off(LED1); + gd_eval_led_off(LED2); + gd_eval_led_off(LED3); + gd_eval_led_off(LED4); +} + +/*! + \brief configure the different system clocks + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable DMA clock */ + rcu_periph_clock_enable(RCU_DMA0); +} + +/*! + \brief configure the CLIC + \param[in] none + \param[out] none + \retval none +*/ +void config_clic_irqs (void) +{ + eclic_global_interrupt_enable(); + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL3_PRIO1); + eclic_irq_enable(DMA0_Channel0_IRQn, 1, 1); + +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Flash_to_ram/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Flash_to_ram/readme.txt new file mode 100644 index 0000000..164057c --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Flash_to_ram/readme.txt @@ -0,0 +1,48 @@ +/*! + \file readme.txt + \brief description of the DMA flash to ram example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it provides a description of how to +use DMA0 channel0 to transfer data buffer from FLASH memory to embedded SRAM memory. + + Before programming the flash addresses, an erase operation is performed firstly. +After the erase operation, a comparison between FLASH memory and 0xFFFFFFFF(Reset value) +is done to check that the FLASH memory has been correctly erased. + + Once the erase operation is finished correctly, the programming operation will be +performed by using the fmc_word_program function. The written data is transfered to +embedded SRAM memory by DMA0 Channel0. The transfer is started by enabling the DMA0 Channel0. +At the end of the transfer, a Transfer Complete interrupt is generated since it +is enabled. A comparison between the FLASH memory and embedded SRAM memory is done to +check that all data have been correctly transferred.If the result of comparison is passed, +LED1 to LED4 light up. Otherwise LED1 and LED3 light up. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_ram/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_ram/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_ram/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_ram/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_ram/main.c new file mode 100644 index 0000000..6a845e7 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_ram/main.c @@ -0,0 +1,200 @@ +/*! + \file main.c + \brief ram to ram demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" +#include + +#define DATANUM 16 + +__IO ErrStatus transferflag1 = ERROR; +__IO ErrStatus transferflag2 = ERROR; +__IO ErrStatus transferflag3 = ERROR; +__IO ErrStatus transferflag4 = ERROR; +uint8_t source_address[DATANUM]= {0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08, + 0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10}; +uint8_t destination_address1[DATANUM]; +uint8_t destination_address2[DATANUM]; +uint8_t destination_address3[DATANUM]; +uint8_t destination_address4[DATANUM]; + +void destbuf_init(void); +void led_config(void); +ErrStatus uc_data_compare(uint8_t* src, uint8_t* dst, uint16_t length); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + int i = 0; + dma_parameter_struct dma_init_struct; + + /* enable DMA clock */ + rcu_periph_clock_enable(RCU_DMA0); + /* initialize LED */ + led_config(); + /* all LED off */ + gd_eval_led_off(LED1); + gd_eval_led_off(LED2); + gd_eval_led_off(LED3); + gd_eval_led_off(LED4); + + destbuf_init(); + /* initialize DMA channel1 */ + dma_deinit(DMA0, DMA_CH1); + dma_struct_para_init(&dma_init_struct); + + dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY; + dma_init_struct.memory_addr = (uint32_t)destination_address1; + dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; + dma_init_struct.number = DATANUM; + dma_init_struct.periph_addr = (uint32_t)source_address; + dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_ENABLE; + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; + dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH; + dma_init(DMA0, DMA_CH1, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA0, DMA_CH1); + dma_memory_to_memory_enable(DMA0, DMA_CH1); + + /* initialize DMA channel2 */ + dma_deinit(DMA0, DMA_CH2); + dma_init_struct.memory_addr = (uint32_t)destination_address2; + dma_init(DMA0, DMA_CH2, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA0, DMA_CH2); + dma_memory_to_memory_enable(DMA0, DMA_CH2); + + /* initialize DMA channel3 */ + dma_deinit(DMA0, DMA_CH3); + dma_init_struct.memory_addr = (uint32_t)destination_address3; + dma_init(DMA0, DMA_CH3, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA0, DMA_CH3); + dma_memory_to_memory_enable(DMA0, DMA_CH3); + + /* initialize DMA channel4 */ + dma_deinit(DMA0, DMA_CH4); + dma_init_struct.memory_addr = (uint32_t)destination_address4; + dma_init(DMA0, DMA_CH4, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA0, DMA_CH4); + dma_memory_to_memory_enable(DMA0, DMA_CH4); + + /* enable DMA channel1~channel4 */ + dma_channel_enable(DMA0, DMA_CH1); + dma_channel_enable(DMA0, DMA_CH2); + dma_channel_enable(DMA0, DMA_CH3); + dma_channel_enable(DMA0, DMA_CH4); + + /* wait for DMA transfer complete */ + for(i = 0; i < 200; i++){ + } + /* compare the data of source_address with data of destination_address */ + transferflag1 = uc_data_compare(source_address, destination_address1, DATANUM); + transferflag2 = uc_data_compare(source_address, destination_address2, DATANUM); + transferflag3 = uc_data_compare(source_address, destination_address3, DATANUM); + transferflag4 = uc_data_compare(source_address, destination_address4, DATANUM); + + /* if DMA channel1 transfer success,light LED1 */ + if(SUCCESS == transferflag1){ + gd_eval_led_on(LED1); + } + /* if DMA channel2 transfer success,light LED2 */ + if(SUCCESS == transferflag2){ + gd_eval_led_on(LED2); + } + /* if DMA channel3 transfer success,light LED3 */ + if(SUCCESS == transferflag3){ + gd_eval_led_on(LED3); + } + /* if DMA channel4 transfer success,light LED4 */ + if(SUCCESS == transferflag4){ + gd_eval_led_on(LED4); + } + + while (1); +} + +/*! + \brief initialize destination buffer + \param[in] none + \param[out] none + \retval none +*/ +void destbuf_init(void) +{ + memset(destination_address1, 0, DATANUM); + memset(destination_address2, 0, DATANUM); + memset(destination_address3, 0, DATANUM); + memset(destination_address4, 0, DATANUM); +} + +/*! + \brief LEDs configure + \param[in] none + \param[out] none + \retval none +*/ +void led_config(void) +{ + gd_eval_led_init(LED1); + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + gd_eval_led_init(LED4); +} + +/*! + \brief data compare function + \param[in] src : source data + \param[in] dst : destination data + \param[in] length : the compare data length + \param[out] none + \retval ErrStatus : ERROR or SUCCESS +*/ +ErrStatus uc_data_compare(uint8_t* src, uint8_t* dst, uint16_t length) +{ + while (length--){ + if (*src++ != *dst++){ + return ERROR; + } + } + return SUCCESS; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_ram/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_ram/readme.txt new file mode 100644 index 0000000..fa33b9e --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_ram/readme.txt @@ -0,0 +1,43 @@ +/*! + \file readme.txt + \brief description of DMA ram to ram + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it provides a description +of how to use DMA channel(1 to 4) to transfer data from RAM to RAM.DMA Channel(1 to 4) is +configured to transfer the contents of data buffer stored in "source_address" to the +reception buffer declared in RAM(destination_address1~destination_address4). + + The start of transfer is triggered by software. At the end of the transfer, a comparison +between the source and destination buffers is done to check that all data have been correctly +transferred.If transfer correctly the corresponding LED light.If transfer not correctly,the +corresponding LED is off. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_usart/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_usart/gd32vf103_it.c new file mode 100644 index 0000000..c70f1b0 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_usart/gd32vf103_it.c @@ -0,0 +1,51 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_it.h" + +extern volatile FlagStatus g_transfer_complete; + +/*! + \brief this function handles DMA_Channel3_IRQHandler interrupt + \param[in] none + \param[out] none + \retval none +*/ +void DMA0_Channel3_IRQHandler(void) +{ + if(dma_interrupt_flag_get(DMA0, DMA_CH3, DMA_INT_FLAG_FTF)){ + dma_interrupt_flag_clear(DMA0, DMA_CH3, DMA_INT_FLAG_G); + g_transfer_complete = SET; + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_usart/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_usart/gd32vf103_it.h new file mode 100644 index 0000000..8f0e3e8 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_usart/gd32vf103_it.h @@ -0,0 +1,44 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ +/* DMA0_Channel3 handle function */ +void DMA0_Channel3_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_usart/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_usart/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_usart/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_usart/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_usart/main.c new file mode 100644 index 0000000..9424b42 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_usart/main.c @@ -0,0 +1,130 @@ +/*! + \file main.c + \brief ram to usart demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" +#include +#include "riscv_encoding.h" + +#define USART0_DATA_ADDRESS ((uint32_t)0x40013804) +#define ARRAYNUM(arr_name) (uint32_t)(sizeof(arr_name) / sizeof(*(arr_name))) + +uint8_t welcome[]="hi,this is a example: RAM_TO_USART by DMA !\n"; +volatile FlagStatus g_transfer_complete = RESET; + +void led_config(void); +void config_clic_irqs(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + dma_parameter_struct dma_init_struct; + /* enable DMA clock */ + rcu_periph_clock_enable(RCU_DMA0); + /* USART configure */ + gd_eval_com_init(EVAL_COM0); + /* CLIC configuration */ + config_clic_irqs(); + /* initialize LED */ + led_config(); + /* turn LED1 off */ + gd_eval_led_off(LED1); + + /* initialize DMA channel3 */ + dma_deinit(DMA0, DMA_CH3); + dma_struct_para_init(&dma_init_struct); + + dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; + dma_init_struct.memory_addr = (uint32_t)welcome; + dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; + dma_init_struct.number = ARRAYNUM(welcome); + dma_init_struct.periph_addr = USART0_DATA_ADDRESS; + dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; + dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH; + dma_init(DMA0, DMA_CH3, &dma_init_struct); + + /* configure DMA mode */ + dma_circulation_disable(DMA0, DMA_CH3); + dma_memory_to_memory_disable(DMA0, DMA_CH3); + + /* USART DMA enable for transmission */ + usart_dma_transmit_config(USART0, USART_DENT_ENABLE); + + /* enable DMA transfer complete interrupt */ + dma_interrupt_enable(DMA0, DMA_CH3, DMA_INT_FTF); + + /* enable DMA channel3 */ + dma_channel_enable(DMA0, DMA_CH3); + + /* waiting for the transfer to complete*/ + while(RESET == g_transfer_complete){ + } + + /* light LED1 */ + gd_eval_led_on(LED1); + + while(1); +} + +/*! + \brief LED1 configuration + \param[in] none + \param[out] none + \retval none +*/ +void led_config(void) +{ + gd_eval_led_init(LED1); +} + +/*! + \brief configure the CLIC + \param[in] none + \param[out] none + \retval none +*/ +void config_clic_irqs(void) +{ + eclic_global_interrupt_enable(); + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL3_PRIO1); + eclic_irq_enable(DMA0_Channel3_IRQn, 1, 1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_usart/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_usart/readme.txt new file mode 100644 index 0000000..2b538c6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/DMA/Ram_to_usart/readme.txt @@ -0,0 +1,41 @@ +/*! + \file readme.txt + \brief description of DMA ram to usart + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it provides a description +of how to use DMA channel3 to transfer data from RAM memory to USART0 transmit data +register.The start of transfer is triggered by software. At the end of the transfer, a +transfer complete interrupt is generated since it is enabled. If the DMA transfer +operation is finished correctly, data stored array welcome[] will be transfered +to a serial port tool by USART0 and LED1 light up. + JP5 and JP6 must be jumpped to USART0. \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/exmc_lcd.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/exmc_lcd.c new file mode 100644 index 0000000..8a5b902 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/exmc_lcd.c @@ -0,0 +1,94 @@ +/*! + \file exmc_lcd.c + \brief EXMC LCD driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "exmc_lcd.h" + +/*! + \brief lcd peripheral initialize + \param[in] none + \param[out] none + \retval none +*/ +void exmc_lcd_init(void) +{ + exmc_norsram_parameter_struct lcd_init_struct; + exmc_norsram_timing_parameter_struct lcd_timing_init_struct; + + /* EXMC clock enable */ + rcu_periph_clock_enable(RCU_EXMC); + rcu_periph_clock_enable(RCU_AF); + /* GPIO clock enable */ + rcu_periph_clock_enable(RCU_GPIOD); + rcu_periph_clock_enable(RCU_GPIOE); + + /* configure EXMC_D[0~15]*/ + /* PD14(EXMC_D0), PD15(EXMC_D1),PD0(EXMC_D2), PD1(EXMC_D3), PD8(EXMC_D13), PD9(EXMC_D14), PD10(EXMC_D15) */ + gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1| GPIO_PIN_8 | GPIO_PIN_9 | + GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15); + + /* PE7(EXMC_D4), PE8(EXMC_D5), PE9(EXMC_D6), PE10(EXMC_D7), PE11(EXMC_D8), PE12(EXMC_D9), + PE13(EXMC_D10), PE14(EXMC_D11), PE15(EXMC_D12) */ + gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | + GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | + GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15); + + /* configure PE2(EXMC_A23) */ + gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2); + + /* configure NOE and NWE */ + gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_4 | GPIO_PIN_5); + + /* configure EXMC NE0 */ + gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_7); + + lcd_timing_init_struct.bus_latency = 2; + lcd_timing_init_struct.asyn_data_setuptime = 10; + lcd_timing_init_struct.asyn_address_holdtime = 2; + lcd_timing_init_struct.asyn_address_setuptime = 5; + + lcd_init_struct.norsram_region = EXMC_BANK0_NORSRAM_REGION0; + lcd_init_struct.asyn_wait = DISABLE; + lcd_init_struct.nwait_signal = DISABLE; + lcd_init_struct.memory_write = ENABLE; + lcd_init_struct.nwait_polarity = EXMC_NWAIT_POLARITY_LOW; + lcd_init_struct.databus_width = EXMC_NOR_DATABUS_WIDTH_16B; + lcd_init_struct.memory_type = EXMC_MEMORY_TYPE_SRAM; + lcd_init_struct.address_data_mux = ENABLE; + lcd_init_struct.read_write_timing = &lcd_timing_init_struct; + + exmc_norsram_init(&lcd_init_struct); + + exmc_norsram_enable(EXMC_BANK0_NORSRAM_REGION0); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/exmc_lcd.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/exmc_lcd.h new file mode 100644 index 0000000..89e1340 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/exmc_lcd.h @@ -0,0 +1,41 @@ +/*! + \file exmc_lcd.h + \brief the header file of EXMC LCD driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef EXMC_LCD_H +#define EXMC_LCD_H + +/* lcd peripheral initialize */ +void exmc_lcd_init(void); + +#endif /* EXMC_LCD_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/ili9320.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/ili9320.c new file mode 100644 index 0000000..50ff18d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/ili9320.c @@ -0,0 +1,544 @@ +/*! + \file ili9320.c + \brief LCD driver functions + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + \version 2019-09-18, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "ili9320.h" +#include "ili9320_font.h" + +uint16_t device_code; + +/*! + \brief write data to the selected LCD register + \param[in] register_id: the selected register id + \param[in] value: the register value to be written + \param[out] none + \retval none +*/ + +void lcd_register_write(uint16_t register_id,uint16_t value) +{ + *(__IO uint16_t *) (BANK0_LCD_C)= register_id; + *(__IO uint16_t *) (BANK0_LCD_D)= value; +} + +/*! + \brief read the value of LCD register + \param[in] register_id: the register id + \param[out] none + \retval the register value +*/ +uint16_t lcd_register_read(uint8_t register_id) +{ + uint16_t data; + *(__IO uint16_t *) (BANK0_LCD_C)= register_id; + data = *(__IO uint16_t *) (BANK0_LCD_D); + return data; +} + +/*! + \brief write command to LCD register + \param[in] value: the register value to be written + \param[out] none + \retval none +*/ +void lcd_command_write(uint16_t value) +{ + /* write 16-bit index, then write reg */ + *(__IO uint16_t *) (BANK0_LCD_C) = value; +} + +/*! + \brief prepare to write to the LCD GRAM register(R22h) + \param[in] none + \param[out] none + \retval none +*/ +void lcd_gram_write_prepare(void) +{ + *(__IO uint16_t *) (BANK0_LCD_C) = 0x0022; +} + +/*! + \brief write RGB code to the LCD GRAM register + \param[in] rgb_code: the pixel color in RGB mode (5-6-5) + \param[out] none + \retval none +*/ +void lcd_gram_write(uint16_t rgb_code) +{ + /* write 16-bit GRAM register */ + *(__IO uint16_t *) (BANK0_LCD_D) = rgb_code; +} + +/*! + \brief read data from GRAM + \param[in] none + \param[out] none + \retval GRAM value +*/ +uint16_t lcd_gram_read(void) +{ + uint16_t data; + + /* write GRAM register (R22h) */ + *(__IO uint16_t *) (BANK0_LCD_C) = 0x0022; + /* dummy read (invalid data) */ + data = *(__IO uint16_t *) (BANK0_LCD_D); + + data = *(__IO uint16_t *) (BANK0_LCD_D); + return data; +} + +/*! + \brief initialize the LCD + \param[in] none + \param[out] none + \retval none +*/ +void lcd_init(void) +{ + __IO uint16_t i; + + /* read the LCD controller device code */ + device_code = lcd_register_read(0x0000); + + if(0x8989 == device_code){ // SSD1289 + lcd_register_write(0x0000,0x0001); + lcd_register_write(0x0003,0xA8A4); + lcd_register_write(0x000C,0x0000); + lcd_register_write(0x000D,0x080C); + lcd_register_write(0x000E,0x2B00); + lcd_register_write(0x001E,0x00B0); + lcd_register_write(0x0001,0x2B3F); + lcd_register_write(0x0002,0x0600); + lcd_register_write(0x0010,0x0000); + lcd_register_write(0x0011,0x6070); + lcd_register_write(0x0005,0x0000); + lcd_register_write(0x0006,0x0000); + lcd_register_write(0x0016,0xEF1C); + lcd_register_write(0x0017,0x0003); + lcd_register_write(0x0007,0x0233); + lcd_register_write(0x000B,0x0000); + lcd_register_write(0x000F,0x0000); + lcd_register_write(0x0041,0x0000); + lcd_register_write(0x0042,0x0000); + lcd_register_write(0x0048,0x0000); + lcd_register_write(0x0049,0x013F); + lcd_register_write(0x004A,0x0000); + lcd_register_write(0x004B,0x0000); + lcd_register_write(0x0044,0xEF00); + lcd_register_write(0x0045,0x0000); + lcd_register_write(0x0046,0x013F); + lcd_register_write(0x0030,0x0707); + lcd_register_write(0x0031,0x0204); + lcd_register_write(0x0032,0x0204); + lcd_register_write(0x0033,0x0502); + lcd_register_write(0x0034,0x0507); + lcd_register_write(0x0035,0x0204); + lcd_register_write(0x0036,0x0204); + lcd_register_write(0x0037,0x0502); + lcd_register_write(0x003A,0x0302); + lcd_register_write(0x003B,0x0302); + lcd_register_write(0x0023,0x0000); + lcd_register_write(0x0024,0x0000); + lcd_register_write(0x0025,0x8000); + lcd_register_write(0x004e,0); + lcd_register_write(0x004f,0); + }else if((0x9320 == device_code) || (0x9300 == device_code)){ //ILI9320 + lcd_register_write(0x01,0x0100); //driver output control + lcd_register_write(0x02,0x0700); //lcd driver waveform control + lcd_register_write(0x03,0x1020); //entry mode set + + lcd_register_write(0x04,0x0000); //resizing control + lcd_register_write(0x08,0x0202); //display control 2 + lcd_register_write(0x09,0x0000); //display control 3 + lcd_register_write(0x0a,0x0000); //frame cycle control + lcd_register_write(0x0c,(1<<0)); //extern display interface control 1 + lcd_register_write(0x0d,0x0000); //frame maker position + lcd_register_write(0x0f,0x0000); //extern display interface control 2 + + for(i=50000;i>0;i--); + lcd_register_write(0x07,0x0101); //display control + for(i=50000;i>0;i--); + + lcd_register_write(0x10,(1<<12)|(0<<8)|(1<<7)|(1<<6)|(0<<4)); //power control 1 + lcd_register_write(0x11,0x0007); //power control 2 + lcd_register_write(0x12,(1<<8)|(1<<4)|(0<<0)); //power control 3 + lcd_register_write(0x13,0x0b00); //power control 4 + lcd_register_write(0x29,0x0000); //power control 7 + lcd_register_write(0x2b,(1<<14)|(1<<4)); + lcd_register_write(0x50,0); //set x start + lcd_register_write(0x51,239); //set x end + lcd_register_write(0x52,0); //set y start + lcd_register_write(0x53,319); //set y end + + lcd_register_write(0x60,0x2700); //driver output control + lcd_register_write(0x61,0x0001); //driver output control + lcd_register_write(0x6a,0x0000); //vertical srcoll control + + lcd_register_write(0x80,0x0000); //display position? partial display 1 + lcd_register_write(0x81,0x0000); //ram address start? partial display 1 + lcd_register_write(0x82,0x0000); //ram address end-partial display 1 + lcd_register_write(0x83,0x0000); //display position? partial display 2 + lcd_register_write(0x84,0x0000); //ram address start? partial display 2 + lcd_register_write(0x85,0x0000); //ram address end? partial display 2 + + lcd_register_write(0x90,(0<<7)|(16<<0)); //frame cycle control + lcd_register_write(0x92,0x0000); //panel interface control 2 + lcd_register_write(0x93,0x0001); //panel interface control 3 + lcd_register_write(0x95,0x0110); //frame cycle control + lcd_register_write(0x97,(0<<8)); + lcd_register_write(0x98,0x0000); //frame cycle control + for(i=50000;i>0;i--); + lcd_register_write(0x07,0x0173); + for(i=50000;i>0;i--); + + }else{ + return; + } + + for(i=50000;i>0;i--); +} + +/*! + \brief set the cursor of LCD + \param[in] x: the row-coordinate + \param[in] y: the column-coordinate + \param[out] none + \retval none +*/ +void lcd_cursor_set(uint16_t x,uint16_t y) +{ + lcd_register_write(0x004e,x); + lcd_register_write(0x004f,y); +} + +/*! + \brief clear the LCD screen to the specified color + \param[in] color: specified screen color + \param[out] none + \retval none +*/ +void lcd_clear(uint16_t color) +{ + uint32_t index=0; + if(0x8989 == device_code){ // SSD1289 + lcd_cursor_set(0,0); + /* prepare to write GRAM */ + lcd_gram_write_prepare(); + for(index=0; index LCD_PIXEL_HEIGHT)||(y > LCD_PIXEL_WIDTH)){ + return; + } + if(0x8989 == device_code){ // SSD1289 + lcd_cursor_set(x,y); + lcd_gram_write_prepare(); + lcd_gram_write(point); + }else if((0x9320 == device_code) || (0x9300 == device_code)){ //ILI9320 + lcd_register_write(0x20, x); + lcd_register_write(0x21, y); + lcd_register_write(0x22, point); + } + +} + +/*! + \brief get point GRAM according to the specified position + \param[in] x: the row-coordinate + \param[in] y: the column-coordinate + \param[out] none + \retval GRAM value of point +*/ +uint16_t lcd_point_get(uint16_t x,uint16_t y) +{ + uint16_t data; + + if ((x > LCD_PIXEL_HEIGHT)||(y > LCD_PIXEL_WIDTH)){ + return 0; + } + + lcd_cursor_set(x,y); + data = lcd_gram_read(); + + return data; +} + +/*! + \brief set window area + \param[in] start_x: the start position of row-coordinate + \param[in] start_y: the start position of column-coordinate + \param[in] end_x: the end position of row-coordinate + \param[in] end_y: the end position of column-coordinate + \param[out] none + \retval none +*/ +void lcd_windows_set(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y) +{ + lcd_cursor_set(start_x, start_y); + + lcd_register_write(0x0050, start_x); + lcd_register_write(0x0052, start_y); + lcd_register_write(0x0051, end_x); + lcd_register_write(0x0053, end_y); +} + +/*! + \brief draw a horizontal line on LCD screen + \param[in] x: the row-coordinate + \param[in] start_y: the start column-coordinate + \param[in] end_y: the end column-coordinate + \param[in] color: specified color of the point + \param[in] width: line width + \param[out] none + \retval none +*/ + +void lcd_hline_draw(uint16_t x,uint16_t start_y,uint16_t end_y,uint16_t color,uint16_t width) +{ + uint16_t i, y; + + for (i = 0; i < width; i++) { + uint16_t sx = x + i; + + for (y = start_y; y < end_y; y++) { + lcd_point_set(sx, y, color); + } + } +} + +/*! + \brief draw a vertical line on LCD screen + \param[in] start_x: the start column-coordinate + \param[in] end_x: the end column-coordinate + \param[in] y: the row-coordinate + \param[in] color: specified color of the point + \param[in] width: line width + \param[out] none + \retval none +*/ + +void lcd_vline_draw(uint16_t start_x,uint16_t end_x,uint16_t y,uint16_t color,uint16_t width) +{ + uint16_t i, x; + + for (i = 0; i < width; i++) { + uint16_t sy = y + i; + + for (x = start_x; x < end_x; x++) { + lcd_point_set(x, sy, color); + } + } +} + +/*! + \brief draw a rectangle according to the specified position and color + \param[in] start_x: the start position of row-coordinate + \param[in] start_y: the start position of column-coordinate + \param[in] end_x: the end position of row-coordinate + \param[in] end_y: the end position of column-coordinate + \param[in] point: specified color of the point + \param[out] none + \retval none +*/ +void lcd_rectangle_draw(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t point) +{ + uint16_t x,y; + x=start_x; + y=start_y; + /* draw four lines */ + for(x=start_x;xstart_x;x--){ + lcd_point_set(x,y,point); + } + for(y=end_y;y>start_y;y--){ + lcd_point_set(x,y,point); + } +} + +/*! + \brief fill the specified color to a rectangle + \param[in] start_x: the start position of row-coordinate + \param[in] start_y: the start position of column-coordinate + \param[in] end_x: the end position of row-coordinate + \param[in] end_y: the end position of column-coordinate + \param[in] color: specified color + \param[out] none + \retval none +*/ +void lcd_rectangle_fill(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t color) +{ + uint16_t x, y; + x = start_x; + y = start_y; + + for (x = start_x; x < end_x; x++) { + for (y = start_y; y < end_y; y++) { + lcd_point_set(x, y, color); + } + } +} + +/*! + \brief draw a picture on LCD screen according to the specified position + \param[in] start_x: the start position of row-coordinate + \param[in] start_y: the start position of column-coordinate + \param[in] end_x: the end position of row-coordinate + \param[in] end_y: the end position of column-coordinate + \param[in] pic: the picture pointer + \param[out] none + \retval none +*/ +void lcd_picture_draw(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t *pic) +{ + uint32_t i, total; + uint16_t *picturepointer = pic; + uint16_t x,y; + + x = start_x; + y = start_y; + + total = (end_x - start_x + 1) * (end_y - start_y + 1); + + for(i = 0; i < total; i ++){ + /* set point according to the specified position and color */ + lcd_point_set(x,y,*picturepointer++); + x++; + if(x > end_x){ + y++; + x = start_x; + } + } +} + +/*! + \brief display a char on LCD screen according to the specified position + \param[in] x: the start position of row-coordinate + \param[in] y: the start position of column-coordinate + \param[in] c: the char + \param[in] char_color: the color of char + \param[in] c_format: the structure of char format + font: CHAR_FONT_8_16 or CHAR_FONT_16_24 + direction: CHAR_DIRECTION_HORIZONTAL or CHAR_DIRECTION_VERTICAL + char_color: the color of char + bk_color: the color of background + \param[out] none + \retval none +*/ +void lcd_char_display(uint16_t x,uint16_t y,uint8_t c,char_format_struct c_format) +{ + uint16_t i = 0, j = 0; + uint8_t temp_char = 0; + uint16_t temp_char_16 = 0; + + if(CHAR_FONT_8_16 == c_format.font){ /* 8x16 ASCII */ + for (i = 0; i < 16; i++) { + temp_char = ascii_8x16[((c - 0x20) * 16) + i]; + if(CHAR_DIRECTION_HORIZONTAL == c_format.direction){ + for (j = 0; j < 8; j++) { + if (((temp_char >> (7 - j)) & 0x01) == 0x01) { + /* set point of char */ + lcd_point_set(x - i, y + j, c_format.char_color); + } else { + /* set point of background */ + lcd_point_set(x - i, y + j, c_format.bk_color); + } + } + }else{ + for (j = 0; j < 8; j++) { + if (((temp_char >> (7 - j)) & 0x01) == 0x01) { + /* set point of char */ + lcd_point_set(x + j, y + i, c_format.char_color); + } else { + /* set point of background */ + lcd_point_set(x + j, y + i, c_format.bk_color); + } + } + } + } + }else if(CHAR_FONT_16_24 == c_format.font){ /* 16x24 ASCII */ + for (i = 0; i < 24; i++) { + temp_char_16 = ASCII_Table_16x24[((c - 0x20) * 24) + i]; + if(CHAR_DIRECTION_HORIZONTAL == c_format.direction){ + for (j = 0; j < 16; j++) { + if (((temp_char_16 >> j) & 0x01) == 0x01) { + /* set point of char */ + lcd_point_set(x - i, y + j, c_format.char_color); + } else { + /* set point of background */ + lcd_point_set(x - i, y + j, c_format.bk_color); + } + } + }else{ + for (j = 0; j < 16; j++) { + if (((temp_char_16 >> j) & 0x01) == 0x01) { + /* set point of char */ + lcd_point_set(x + j, y + i, c_format.char_color); + } else { + /* set point of background */ + lcd_point_set(x + j, y + i, c_format.bk_color); + } + } + } + } + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/ili9320.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/ili9320.h new file mode 100644 index 0000000..03908fd --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/ili9320.h @@ -0,0 +1,233 @@ +/*! + \file ili9320.h + \brief LCD driver header file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + \version 2019-09-18, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef ILI9320_H +#define ILI9320_H + +#include "gd32vf103.h" + +#define BANK0_LCD_C ((uint32_t)0x60000000) /*!< LCD register address */ +#define BANK0_LCD_D ((uint32_t)0x61000000) /*!< LCD data address */ + +/* LCD registers */ +#define R0 0x00 +#define R1 0x01 +#define R2 0x02 +#define R3 0x03 +#define R4 0x04 +#define R5 0x05 +#define R6 0x06 +#define R7 0x07 +#define R8 0x08 +#define R9 0x09 +#define R10 0x0A +#define R11 0x0B +#define R12 0x0C +#define R13 0x0D +#define R14 0x0E +#define R15 0x0F +#define R16 0x10 +#define R17 0x11 +#define R18 0x12 +#define R19 0x13 +#define R20 0x14 +#define R21 0x15 +#define R22 0x16 +#define R23 0x17 +#define R24 0x18 +#define R25 0x19 +#define R26 0x1A +#define R27 0x1B +#define R28 0x1C +#define R29 0x1D +#define R30 0x1E +#define R31 0x1F +#define R32 0x20 +#define R33 0x21 +#define R34 0x22 +#define R35 0x23 +#define R36 0x24 +#define R37 0x25 +#define R40 0x28 +#define R41 0x29 +#define R43 0x2B +#define R45 0x2D +#define R48 0x30 +#define R49 0x31 +#define R50 0x32 +#define R51 0x33 +#define R52 0x34 +#define R53 0x35 +#define R54 0x36 +#define R55 0x37 +#define R56 0x38 +#define R57 0x39 +#define R58 0x3A +#define R59 0x3B +#define R60 0x3C +#define R61 0x3D +#define R62 0x3E +#define R63 0x3F +#define R64 0x40 +#define R65 0x41 +#define R66 0x42 +#define R67 0x43 +#define R68 0x44 +#define R69 0x45 +#define R70 0x46 +#define R71 0x47 +#define R72 0x48 +#define R73 0x49 +#define R74 0x4A +#define R75 0x4B +#define R76 0x4C +#define R77 0x4D +#define R78 0x4E +#define R79 0x4F +#define R80 0x50 +#define R81 0x51 +#define R82 0x52 +#define R83 0x53 +#define R96 0x60 +#define R97 0x61 +#define R106 0x6A +#define R118 0x76 +#define R128 0x80 +#define R129 0x81 +#define R130 0x82 +#define R131 0x83 +#define R132 0x84 +#define R133 0x85 +#define R134 0x86 +#define R135 0x87 +#define R136 0x88 +#define R137 0x89 +#define R139 0x8B +#define R140 0x8C +#define R141 0x8D +#define R143 0x8F +#define R144 0x90 +#define R145 0x91 +#define R146 0x92 +#define R147 0x93 +#define R148 0x94 +#define R149 0x95 +#define R150 0x96 +#define R151 0x97 +#define R152 0x98 +#define R153 0x99 +#define R154 0x9A +#define R157 0x9D +#define R192 0xC0 +#define R193 0xC1 +#define R229 0xE5 + +/* LCD color */ +#define WHITE 0xFFFF +#define BLACK 0x0000 +#define GREY 0xF7DE +#define BLUE 0x001F +#define BLUE2 0x051F +#define RED 0xF800 +#define MAGENTA 0xF81F +#define GREEN 0x07E0 +#define CYAN 0x7FFF +#define YELLOW 0xFFE0 + +#define LINE0 0 +#define LINE1 24 +#define LINE2 48 +#define LINE3 72 +#define LINE4 96 +#define LINE5 120 +#define LINE6 144 +#define LINE7 168 +#define LINE8 192 +#define LINE9 216 + +/* char format struct definitions */ +typedef struct +{ + uint16_t font; /*!< the type of font */ + uint16_t direction; /*!< the direction of char */ + uint16_t char_color; /*!< the color of char */ + uint16_t bk_color; /*!< the color of backgroud */ +}char_format_struct; + +#define CHAR_FONT_8_16 ((uint16_t)0x0000U) /*!< the font of char is 8X16 */ +#define CHAR_FONT_16_24 ((uint16_t)0x0001U) /*!< the font of char is 16X24 */ + +#define CHAR_DIRECTION_HORIZONTAL ((uint16_t)0x0000U) /*!< character display direction is horizontal */ +#define CHAR_DIRECTION_VERTICAL ((uint16_t)0x0001U) /*!< character display direction is vertical */ + +#define LCD_PIXEL_WIDTH ((uint16_t)320) +#define LCD_PIXEL_HEIGHT ((uint16_t)240) + +/* initialize the LCD */ +void lcd_init(void); +/* write data to the selected LCD register */ +void lcd_register_write(uint16_t register_id,uint16_t value); +/* read the value of LCD register */ +uint16_t lcd_register_read(uint8_t register_id); +/* write command to LCD register */ +void lcd_command_write (uint16_t value); +/* prepare to write to the LCD GRAM */ +void lcd_gram_write_prepare(void); +/* write RGB code to the LCD GRAM register */ +void lcd_gram_write(uint16_t rgb_code); +/* read data from GRAM */ +uint16_t lcd_gram_read(void); +/* set the cursor of LCD */ +void lcd_cursor_set(uint16_t x,uint16_t y); +/* clear the LCD screen to the specified color */ +void lcd_clear(uint16_t Color); +/* set the point according to the specified position and color */ +void lcd_point_set(uint16_t x,uint16_t y,uint16_t point); +/* get the point according to the specified position */ +uint16_t lcd_point_get(uint16_t x,uint16_t y); +/* set window area */ +void lcd_windows_set(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y); +/* draw a horizontal line on LCD screen */ +void lcd_hline_draw(uint16_t x,uint16_t start_y,uint16_t end_y,uint16_t color,uint16_t width); +/* draw a rectangle according to the specified position and color */ +void lcd_rectangle_draw(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t point); +/* fill the specified color to a rectangle */ +void lcd_rectangle_fill(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t color); +/* draw a picture on LCD screen according to the specified position */ +void lcd_picture_draw(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t *pic); +/* display a char on LCD screen according to the specified position */ +void lcd_char_display(uint16_t x,uint16_t y,uint8_t c,char_format_struct c_format); + +#endif /* ILI9320_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/ili9320_font.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/ili9320_font.h new file mode 100644 index 0000000..5f929c6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/ili9320_font.h @@ -0,0 +1,711 @@ +/*! + \file ili9320_font.h + \brief LCD font header file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" + +/* 8x16 ASCII */ +unsigned char const ascii_8x16[1536] = { +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x18,0x3C,0x3C,0x3C,0x18,0x18,0x18,0x00,0x18,0x18,0x00,0x00,0x00,0x00, +0x00,0x66,0x66,0x66,0x24,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x6C,0x6C,0xFE,0x6C,0x6C,0x6C,0xFE,0x6C,0x6C,0x00,0x00,0x00,0x00, +0x18,0x18,0x7C,0xC6,0xC2,0xC0,0x7C,0x06,0x86,0xC6,0x7C,0x18,0x18,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0xC2,0xC6,0x0C,0x18,0x30,0x60,0xC6,0x86,0x00,0x00,0x00,0x00, +0x00,0x00,0x38,0x6C,0x6C,0x38,0x76,0xDC,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00, +0x00,0x30,0x30,0x30,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x0C,0x18,0x30,0x30,0x30,0x30,0x30,0x30,0x18,0x0C,0x00,0x00,0x00,0x00, +0x00,0x00,0x30,0x18,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x18,0x30,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x66,0x3C,0xFF,0x3C,0x66,0x00,0x00,0x00,0x00,0x00,0x00, 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+0x00,0x00,0x00,0x00,0x10,0x38,0x6C,0xC6,0xC6,0xC6,0xFE,0x00,0x00,0x00,0x00,0x00 +}; + +/* ASCII Table: each character is 16 column (16dots large) + and 24 raw (24 dots high) */ +const uint16_t ASCII_Table_16x24[] = +{ +/** + * @brief Space ' ' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '!' + */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '"' + */ + 0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '#' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60, + 0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318, + 0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000, +/** + * @brief '$' + */ + 0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C, + 0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C, + 0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000, +/** + * @brief '%' + */ + 0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611, + 0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460, + 0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000, +/** + * @brief '&' + */ + 0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0, + 0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06, + 0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ''' + */ + 0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '(' + */ + 0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060, + 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, + 0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000, +/** + * @brief ')' + */ + 0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300, + 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, + 0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000, +/** + * @brief '*' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '+' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ',' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, +/** + * @brief '-' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '.' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '/' + */ + 0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300, + 0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0, + 0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '0' + */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C, + 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '1' + */ + 0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '2' + */ + 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800, + 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, + 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '3' + */ + 0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600, + 0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18, + 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '4' + */ + 0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60, + 0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00, + 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '5' + */ + 0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC, + 0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18, + 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '6' + */ + 0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC, + 0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '7' + */ + 0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380, + 0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030, + 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '8' + */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638, + 0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38, + 0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '9' + */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C, + 0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C, + 0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ':' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ';' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000, +/** + * @brief '<' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0, + 0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '=' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '>' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0, + 0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '?' + */ + 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00, + 0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '@' + */ + 0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411, + 0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004, + 0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'A' + */ + 0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60, + 0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C, + 0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'B' + */ + 0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C, + 0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C, + 0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'C' + */ + 0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006, + 0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C, + 0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'D' + */ + 0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006, + 0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06, + 0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'E' + */ + 0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'F' + */ + 0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'G' + */ + 0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003, + 0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C, + 0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'H' + */ + 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'I' + */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'J' + */ + 0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, + 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738, + 0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'K' + */ + 0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6, + 0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806, + 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'L' + */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'M' + */ + 0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836, + 0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6, + 0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'N' + */ + 0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC, + 0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C, + 0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'O' + */ + 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003, + 0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C, + 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'P' + */ + 0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'Q' + */ + 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003, + 0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C, + 0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'R' + */ + 0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806, + 0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006, + 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'S' + */ + 0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C, + 0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C, + 0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'T' + */ + 0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'U' + */ + 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818, + 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'V' + */ + 0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C, + 0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360, + 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'W' + */ + 0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366, + 0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C, + 0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'X' + */ + 0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0, + 0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C, + 0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'Y' + */ + 0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660, + 0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'Z' + */ + 0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600, + 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006, + 0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '[' + */ + 0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, + 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, + 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000, +/** + * @brief '\' + */ + 0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0, + 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300, + 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ']' + */ + 0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, + 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, + 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000, +/** + * @brief '^' + */ + 0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630, + 0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '_' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ''' + */ + 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'a' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8, + 0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C, + 0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'b' + */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8, + 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38, + 0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'c' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0, + 0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30, + 0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'd' + */ + 0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0, + 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30, + 0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'e' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0, + 0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30, + 0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'f' + */ + 0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'g' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8, + 0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18, + 0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000, +/** + * @brief 'h' + */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8, + 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, + 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'i' + */ + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'j' + */ + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000, +/** + * @brief 'k' + */ + 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C, + 0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C, + 0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'l' + */ + 0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'm' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF, + 0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, + 0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'n' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8, + 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, + 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'o' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0, + 0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30, + 0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'p' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8, + 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38, + 0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000, +/** + * @brief 'q' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0, + 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30, + 0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000, +/** + * @brief 'r' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0, + 0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, + 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 's' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0, + 0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 't' + */ + 0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'u' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818, + 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38, + 0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'v' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18, + 0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360, + 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'w' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1, + 0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C, + 0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'x' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38, + 0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30, + 0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'y' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830, + 0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380, + 0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000, +/** + * @brief 'z' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC, + 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, + 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '{' + */ + 0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000, +/** + * @brief '|' + */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, +/** + * @brief '}' + */ + 0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000, +/** + * @brief '~' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + }; diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/main.c new file mode 100644 index 0000000..120bcdd --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/main.c @@ -0,0 +1,82 @@ +/*! + \file main.c + \brief LCD test demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + \version 2019-09-18, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "exmc_lcd.h" +#include "ili9320.h" +#include "picture.h" + +uint8_t gd_website_string[]={"www.gigadevice.com"}; +char_format_struct char_format; + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + uint16_t i; + + /* configure the EXMC access mode */ + exmc_lcd_init(); + + /* initialize the LCD */ + lcd_init(); + + /* clear the LCD screen */ + lcd_clear(WHITE); + + /* draw the picture of Gigadevice logo */ + lcd_picture_draw(60,100,60+120-1,100+95-1,(uint16_t *)(picture + BMP_HEADSIZE)); + + /* draw a rectangle */ + lcd_rectangle_draw(10,10,230,310,BLUE); + + /* configure char format */ + char_format.char_color = BLUE; + char_format.bk_color = WHITE; + char_format.direction = CHAR_DIRECTION_VERTICAL; + char_format.font = CHAR_FONT_8_16; + + /* draw character on LCD screen */ + for(i = 0; i < sizeof(gd_website_string)-1; i++){ + lcd_char_display((50+8*i), 180+20, *(gd_website_string+i),char_format); + } + + while(1){ + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/picture.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/picture.c new file mode 100644 index 0000000..4b454a7 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/picture.c @@ -0,0 +1,1466 @@ +/*! + \file picture.c + \brief picture file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + \version 2019-09-18, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "picture.h" + +/* the picture of Gigadevice logo */ +/* 120*95 */ +const uint8_t picture[22808] = { 0X00,0X10,0X78,0X00,0X5F,0X00,0X01,0X1B, +0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF, +0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF, +0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF, +0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF, +0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF, +0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF, +0XFF,0XFF,0XFF,0XFF,0XFF,0XF7,0XBF,0XE7,0X7E,0XCF,0XFE,0XAE,0X3D,0X8E,0XFC,0X6D, +0XBC,0X4D,0X7B,0X3D,0X3B,0X35,0X3B,0X2D,0X7B,0X3D,0X7C,0X45,0XBC,0X5D,0X3C,0X76, +0X7D,0X96,0XFE,0XBE,0X7E,0XDF,0XBF,0XEF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF, +0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF, 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a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/picture.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/picture.h new file mode 100644 index 0000000..c25d916 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/picture.h @@ -0,0 +1,44 @@ +/*! + \file picture.h + \brief picture header file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef PICTURE_H +#define PICTURE_H + +#include "gd32vf103.h" + +#define BMP_HEADSIZE (8) + +extern const uint8_t picture[]; + +#endif /* PICTURE_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/readme.txt new file mode 100644 index 0000000..de49140 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/LCD/readme.txt @@ -0,0 +1,40 @@ +/*! + \file readme.txt + \brief description of the EXMC_LCD demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to use EXMC +peripheral to drive LCD. This board uses EXMC_NE0 to support LCD. You can see +GigaDevice logo and website on the LCD screen. + + JP13 and JP14 must be fitted to EXMC. + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/NOR/exmc_norflash.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/NOR/exmc_norflash.c new file mode 100644 index 0000000..7b85989 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/NOR/exmc_norflash.c @@ -0,0 +1,340 @@ +/*! + \file exmc_norflash.c + \brief EXMC NOR Flash(M29W128FH) driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "exmc_norflash.h" + +#define BANK0_NOR1_ADDR ((uint32_t)0x60000000) +#define BANK_NORFLASH_ADDR BANK0_NOR1_ADDR + +#define BLOCKERASE_TIMEOUT ((uint32_t)0x00A00000) +#define CHIPERASE_TIMEOUT ((uint32_t)0x30000000) +#define PROGRAM_TIMEOUT ((uint32_t)0x00001400) + +#define ADDR_SHIFT(A) (BANK_NORFLASH_ADDR + (2 * (A))) +#define NOR_WRITE(Address, Data) (*(__IO uint16_t *)(Address) = (Data)) + +/*! + \brief nor flash peripheral initialize + \param[in] none + \param[out] none + \retval none +*/ +void exmc_norflash_init(void) +{ + exmc_norsram_parameter_struct nor_init_struct; + exmc_norsram_timing_parameter_struct nor_timing_init_struct; + + /* EXMC clock enable */ + rcu_periph_clock_enable(RCU_EXMC); + + /* EXMC enable */ + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_GPIOD); + rcu_periph_clock_enable(RCU_GPIOE); + + /* configure EXMC_D[0~15]*/ + /* PD14(EXMC_D0), PD15(EXMC_D1),PD0(EXMC_D2), PD1(EXMC_D3), PD8(EXMC_D13), PD9(EXMC_D14), PD10(EXMC_D15) */ + gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1| GPIO_PIN_8 | GPIO_PIN_9 | + GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15); + + /* PE7(EXMC_D4), PE8(EXMC_D5), PE9(EXMC_D6), PE10(EXMC_D7), PE11(EXMC_D8), PE12(EXMC_D9), + PE13(EXMC_D10), PE14(EXMC_D11), PE15(EXMC_D12) */ + gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | + GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | + GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15); + + /* PD11(EXMC_A16), PD12(EXMC_A17), PD13(EXMC_A18) */ + gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13); + + /* PE3(EXMC_A19), PE4(EXMC_A20), PE5(EXMC_A21), PE6(EXMC_A22) */ + gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6); + + /* configure PD4(NOE), PD5(NWE), PD7(NE0) */ + gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_7); + + /* configure NADV */ + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_7); + + /* configure NWAIT */ + gpio_init(GPIOD, GPIO_MODE_IPU, GPIO_OSPEED_50MHZ, GPIO_PIN_6); + + nor_timing_init_struct.bus_latency = 1; + nor_timing_init_struct.asyn_data_setuptime = 7; + nor_timing_init_struct.asyn_address_holdtime = 2; + nor_timing_init_struct.asyn_address_setuptime = 6; + + nor_init_struct.norsram_region = EXMC_BANK0_NORSRAM_REGION0; + nor_init_struct.asyn_wait = DISABLE; + nor_init_struct.nwait_signal = DISABLE; + nor_init_struct.memory_write = ENABLE; + nor_init_struct.nwait_polarity = EXMC_NWAIT_POLARITY_LOW; + nor_init_struct.databus_width = EXMC_NOR_DATABUS_WIDTH_16B; + nor_init_struct.memory_type = EXMC_MEMORY_TYPE_NOR; + nor_init_struct.address_data_mux = ENABLE; + nor_init_struct.read_write_timing = &nor_timing_init_struct; + + exmc_norsram_init(&nor_init_struct); + + exmc_norsram_enable(EXMC_BANK0_NORSRAM_REGION0); +} + + +/*! + \brief read NOR memory's manufacturer, device code, block_protection_indicator, block_protection_status + \param[in] nor_id: pointer to a nor_idtypedef structure + \param[out] none + \retval none +*/ +void nor_read_id(nor_id_struct* nor_id) +{ + NOR_WRITE(ADDR_SHIFT(CMD_READID_ADD_1ST), CMD_READID_DATA_1ST); + NOR_WRITE(ADDR_SHIFT(CMD_READID_ADD_2ND), CMD_READID_DATA_2ND); + NOR_WRITE(ADDR_SHIFT(CMD_READID_ADD_3RD), CMD_READID_DATA_3RD); + + /* read NOR Flash ID */ + nor_id->manufacturer_code = *(__IO uint16_t *) ADDR_SHIFT(0x0000); + nor_id->device_code1 = *(__IO uint16_t *) ADDR_SHIFT(0x0001); + nor_id->device_code2 = *(__IO uint16_t *) ADDR_SHIFT(0x000E); + nor_id->device_code3 = *(__IO uint16_t *) ADDR_SHIFT(0x000F); +} + +/*! + \brief erase the specified nor flash block + \param[in] blockaddr: address of the block to be erased + \param[out] none + \retval NOR_SUCCESS,NOR_ERROR,NOR_TIMEOUT +*/ +nor_status_struct nor_eraseblock(uint32_t blockaddr) +{ + NOR_WRITE(ADDR_SHIFT(CMD_BLOCKERASE_ADD_1ST), CMD_BLOCKERASE_DATA_1ST); + NOR_WRITE(ADDR_SHIFT(CMD_BLOCKERASE_ADD_2ND), CMD_BLOCKERASE_DATA_2ND); + NOR_WRITE(ADDR_SHIFT(CMD_BLOCKERASE_ADD_3RD), CMD_BLOCKERASE_DATA_3RD); + NOR_WRITE(ADDR_SHIFT(CMD_BLOCKERASE_ADD_4TH), CMD_BLOCKERASE_DATA_4TH); + NOR_WRITE(ADDR_SHIFT(CMD_BLOCKERASE_ADD_5TH), CMD_BLOCKERASE_DATA_5TH); + NOR_WRITE((BANK_NORFLASH_ADDR + blockaddr), CMD_BLOCKERASE_DATA_6TH); + + return (nor_get_status(BLOCKERASE_TIMEOUT)); +} + +/*! + \brief erase the entire chip + \param[in] none + \param[out] none + \retval NOR_SUCCESS,NOR_ERROR,NOR_TIMEOUT +*/ +nor_status_struct nor_erasechip(void) +{ + NOR_WRITE(ADDR_SHIFT(CMD_CHIPERASE_ADD_1ST), CMD_CHIPERASE_DATA_1ST); + NOR_WRITE(ADDR_SHIFT(CMD_CHIPERASE_ADD_2ND), CMD_CHIPERASE_DATA_2ND); + NOR_WRITE(ADDR_SHIFT(CMD_CHIPERASE_ADD_3RD), CMD_CHIPERASE_DATA_3RD); + NOR_WRITE(ADDR_SHIFT(CMD_CHIPERASE_ADD_4TH), CMD_CHIPERASE_DATA_4TH); + NOR_WRITE(ADDR_SHIFT(CMD_CHIPERASE_ADD_5TH), CMD_CHIPERASE_DATA_5TH); + NOR_WRITE(ADDR_SHIFT(CMD_CHIPERASE_ADD_6TH), CMD_CHIPERASE_DATA_6TH); + + return (nor_get_status(CHIPERASE_TIMEOUT)); +} + +/*! + \brief write a half-word to the specified address of nor flash + \param[in] writeaddr: NOR flash internal address to write to + \param[in] data: data to be written + \param[out] none + \retval NOR_SUCCESS,NOR_ERROR,NOR_TIMEOUT +*/ +nor_status_struct nor_write_halfword(uint32_t writeaddr, uint16_t data) +{ + NOR_WRITE(ADDR_SHIFT(CMD_WRITE_ADD_1ST), CMD_WRITE_DATA_1ST); + NOR_WRITE(ADDR_SHIFT(CMD_WRITE_ADD_2ND), CMD_WRITE_DATA_2ND); + NOR_WRITE(ADDR_SHIFT(CMD_WRITE_ADD_3RD), CMD_WRITE_DATA_3RD); + NOR_WRITE((BANK_NORFLASH_ADDR + writeaddr), data); + + return (nor_get_status(PROGRAM_TIMEOUT)); +} + +/*! + \brief write a half-word buffer to the specified address of nor flash + \param[in] pbuffer: pointer to a half-word buffer + \param[in] writeaddr: NOR flash internal address from which the data will be written + \param[in] halfword_count: count of half words to write + \param[out] none + \retval NOR_SUCCESS,NOR_ERROR,NOR_TIMEOUT +*/ +nor_status_struct nor_write_buffer(uint16_t* pbuffer, uint32_t writeaddr, uint32_t halfword_count) +{ + nor_status_struct status = NOR_ONGOING; + + do{ + /* write data to nor flash */ + status = nor_write_halfword(writeaddr, *pbuffer++); + writeaddr = writeaddr + 2; + halfword_count--; + }while((NOR_SUCCESS == status) && (halfword_count != 0)); + + return (status); +} + +/*! + \brief read a half-word from the specified address of nor flash + \param[in] readaddr: NOR flash internal address to read from + \param[out] none + \retval A half-word read from the nor flash +*/ +uint16_t nor_read_halfword(uint32_t readaddr) +{ + NOR_WRITE(ADDR_SHIFT(CMD_READ_ADD_1ST), CMD_READ_DATA_1ST); + NOR_WRITE(ADDR_SHIFT(CMD_READ_ADD_2ND), CMD_READ_DATA_2ND); + NOR_WRITE((BANK_NORFLASH_ADDR + readaddr), CMD_READ_DATA_3RD); + + return (*(__IO uint16_t *)((BANK_NORFLASH_ADDR + readaddr))); +} + +/*! + \brief read a set of data from the specified address of nor flash + \param[in] pbuffer: pointer to a half-word buffer + \param[in] readaddr: NOR flash internal address to read from + \param[in] halfword_count: count of half words to write + \param[out] none + \retval none +*/ +void nor_readbuffer(uint16_t* pbuffer, uint32_t readaddr, uint32_t halfword_count) +{ + NOR_WRITE(ADDR_SHIFT(CMD_READ_ADD_1ST), CMD_READ_DATA_1ST); + NOR_WRITE(ADDR_SHIFT(CMD_READ_ADD_2ND), CMD_READ_DATA_2ND); + NOR_WRITE((BANK_NORFLASH_ADDR + readaddr), CMD_READ_DATA_3RD); + + for(; halfword_count != 0x00; halfword_count--){ + /* read a halfword from the nor flash */ + *pbuffer++ = *(__IO uint16_t *)((BANK_NORFLASH_ADDR + readaddr)); + readaddr = readaddr + 2; + } +} + +/*! + \brief return the nor flash to read mode and reset the errors in the nor flash status register + \param[in] none + \param[out] none + \retval none +*/ +void nor_reset(void) +{ + NOR_WRITE(ADDR_SHIFT(CMD_RESET_ADD_1ST), CMD_RESET_DATA_1ST); + NOR_WRITE(ADDR_SHIFT(CMD_RESET_ADD_2ND), CMD_RESET_DATA_2ND); + NOR_WRITE(BANK_NORFLASH_ADDR , CMD_RESET_DATA_3RD); +} + +/*! + \brief return the nor flash to read mode + \param[in] none + \param[out] none + \retval none +*/ +void nor_return_to_read_mode(void) +{ + NOR_WRITE(BANK_NORFLASH_ADDR , CMD_RESET_DATA_3RD); +} + +/*! + \brief return the nor flash operation status + \param[in] time_out: NOR flash programming timeout + \param[out] none + \retval none +*/ +nor_status_struct nor_get_status(uint32_t time_out) +{ + uint16_t val1 = 0x00, val2 = 0x00; + nor_status_struct status = NOR_ONGOING; + uint32_t timeout = time_out; + + /* poll on nor flash ready/busy signal */ + while(RESET != (gpio_input_bit_get(GPIOD, GPIO_PIN_6)) && (timeout > 0)){ + timeout--; + } + + timeout = time_out; + + while((gpio_input_bit_get(GPIOD, GPIO_PIN_6) == RESET) && (timeout > 0)){ + timeout--; + } + + /* get the nor flash operation status */ + while((time_out != 0x00) && (status != NOR_SUCCESS)){ + time_out--; + + /* read DQ6 and DQ5 */ + val1 = *(__IO uint16_t *)(BANK_NORFLASH_ADDR ); + val2 = *(__IO uint16_t *)(BANK_NORFLASH_ADDR ); + + if((val1 & 0x0040) == (val2 & 0x0040)) { + return NOR_SUCCESS; + } + + if((val1 & 0x0020) != 0x0020){ + status = NOR_ONGOING; + } + + val1 = *(__IO uint16_t *)(BANK_NORFLASH_ADDR ); + val2 = *(__IO uint16_t *)(BANK_NORFLASH_ADDR ); + + if((val1 & 0x0040) == (val2 & 0x0040)) { + return NOR_SUCCESS; + }else if((val1 & 0x0020) == 0x0020){ + return NOR_ERROR; + } + } + + if(time_out == 0x00){ + status = NOR_TIMEOUT; + } + + return (status); +} + +/*! + \brief fill the buffer with specified value + \param[in] pbuffer: pointer on the buffer to fill + \param[in] buffer_lenght: length of the buffer to fill + \param[in] value: value to fill on the buffer + \param[out] none + \retval none +*/ +void nor_fill_buffer(uint16_t *pbuffer, uint16_t buffer_lenght, uint32_t value) +{ + uint16_t index = 0; + + /* put in global buffer same values */ + for (index = 0; index < buffer_lenght; index++ ){ + pbuffer[index] = value + index; + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/NOR/exmc_norflash.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/NOR/exmc_norflash.h new file mode 100644 index 0000000..e9798a9 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/NOR/exmc_norflash.h @@ -0,0 +1,145 @@ +/*! + \file exmc_norflash.h + \brief the header file of EXMC NOR Flash(M29W128FH) driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" + +#ifndef EXMC_NORFLASH_H +#define EXMC_NORFLASH_H + +/* read id command define */ +#define CMD_READID_ADD_1ST 0x0555 +#define CMD_READID_DATA_1ST 0x00AA +#define CMD_READID_ADD_2ND 0x02AA +#define CMD_READID_DATA_2ND 0x0055 +#define CMD_READID_ADD_3RD 0x0555 +#define CMD_READID_DATA_3RD 0x0090 + +/* block erase command define */ +#define CMD_BLOCKERASE_ADD_1ST 0x0555 +#define CMD_BLOCKERASE_DATA_1ST 0x00AA +#define CMD_BLOCKERASE_ADD_2ND 0x02AA +#define CMD_BLOCKERASE_DATA_2ND 0x0055 +#define CMD_BLOCKERASE_ADD_3RD 0x0555 +#define CMD_BLOCKERASE_DATA_3RD 0x0080 +#define CMD_BLOCKERASE_ADD_4TH 0x0555 +#define CMD_BLOCKERASE_DATA_4TH 0x00AA +#define CMD_BLOCKERASE_ADD_5TH 0x02AA +#define CMD_BLOCKERASE_DATA_5TH 0x0055 +#define CMD_BLOCKERASE_DATA_6TH 0x0030 + +/* chip erase command define */ +#define CMD_CHIPERASE_ADD_1ST 0x0555 +#define CMD_CHIPERASE_DATA_1ST 0x00AA +#define CMD_CHIPERASE_ADD_2ND 0x02AA +#define CMD_CHIPERASE_DATA_2ND 0x0055 +#define CMD_CHIPERASE_ADD_3RD 0x0555 +#define CMD_CHIPERASE_DATA_3RD 0x0080 +#define CMD_CHIPERASE_ADD_4TH 0x0555 +#define CMD_CHIPERASE_DATA_4TH 0x00AA +#define CMD_CHIPERASE_ADD_5TH 0x02AA +#define CMD_CHIPERASE_DATA_5TH 0x0055 +#define CMD_CHIPERASE_ADD_6TH 0x0555 +#define CMD_CHIPERASE_DATA_6TH 0x0010 + +/* reset command define */ +#define CMD_RESET_ADD_1ST 0x0555 +#define CMD_RESET_DATA_1ST 0x00AA +#define CMD_RESET_ADD_2ND 0x02AA +#define CMD_RESET_DATA_2ND 0x0055 +#define CMD_RESET_DATA_3RD 0x00F0 + +/* read command define */ +#define CMD_READ_ADD_1ST 0x0555 +#define CMD_READ_DATA_1ST 0x00AA +#define CMD_READ_ADD_2ND 0x02AA +#define CMD_READ_DATA_2ND 0x0055 +#define CMD_READ_DATA_3RD 0x00F0 + +/* write command define */ +#define CMD_WRITE_ADD_1ST 0x0555 +#define CMD_WRITE_DATA_1ST 0x00AA +#define CMD_WRITE_ADD_2ND 0x02AA +#define CMD_WRITE_DATA_2ND 0x0055 +#define CMD_WRITE_ADD_3RD 0x0555 +#define CMD_WRITE_DATA_3RD 0x00A0 + +/* max read and write address */ +#define NOR_MAX_ADDRESS ((uint32_t)0x01000000) + +/* NOR id structure */ +typedef struct +{ + uint16_t manufacturer_code; + uint16_t device_code1; + uint16_t device_code2; + uint16_t device_code3; +}nor_id_struct; + +/* NOR status */ +typedef enum +{ + NOR_SUCCESS = 0, + NOR_ONGOING, + NOR_ERROR, + NOR_TIMEOUT +}nor_status_struct; + +/* function declarations */ +/* nor flash peripheral initialize */ +void exmc_norflash_init(void); +/* read NOR memory's manufacturer, device code, + block_protection_indicator, block_protection_status */ +void nor_read_id(nor_id_struct* nor_id); +/* erase the specified nor flash block */ +nor_status_struct nor_eraseblock(uint32_t blockaddr); +/* erase the entire chip */ +nor_status_struct nor_erasechip(void); +/* write a half-word to the specified address of nor flash */ +nor_status_struct nor_write_halfword(uint32_t writeaddr, uint16_t data); +/* write a half-word buffer to the specified address of nor flash */ +nor_status_struct nor_write_buffer(uint16_t* pbuffer, uint32_t writeaddr, uint32_t halfword_count); +/* read a half-word from the specified address of nor flash */ +uint16_t nor_read_halfword(uint32_t readaddr); +/* read a set of data from the specified address of nor flash */ +void nor_readbuffer(uint16_t* pbuffer, uint32_t readaddr, uint32_t halfwordcount); +/* return the nor flash to read mode and reset the errors in the nor flash status register */ +void nor_reset(void); +/* return the nor flash operation status */ +nor_status_struct nor_get_status(uint32_t time_out); +/* return the nor flash to read mode */ +void nor_return_to_read_mode(void); +/* fill the buffer with specified value */ +void nor_fill_buffer(uint16_t *pbuffer, uint16_t buffer_lenght, uint32_t value); + +#endif /* EXMC_NORFLASH_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/NOR/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/NOR/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/NOR/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/NOR/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/NOR/main.c new file mode 100644 index 0000000..e6ebdbd --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/NOR/main.c @@ -0,0 +1,132 @@ +/*! + \file main.c + \brief EXMC NOR Flash demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" +#include +#include "exmc_norflash.h" + +/* NOR */ +#define BUFFER_SIZE 10 +#define WRITE_READ_ADDR 0x0000 + +nor_id_struct nor_id; +uint32_t writereadstatus = 0; +uint16_t writebuffer[BUFFER_SIZE]; +uint16_t readbuffer[BUFFER_SIZE]; +nor_status_struct status; + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + uint32_t i = 0; + + /* configure the USART */ + gd_eval_com_init(EVAL_COM0); + /* configure the EXMC access mode */ + exmc_norflash_init(); + /* read nor flash id and printf */ + nor_read_id(&nor_id); + + printf("\r\nread NOR ID"); + + /* print NOR ID */ + printf("\r\nNOR flash ID:0x%X 0x%X 0x%X 0x%X\r\n",nor_id.manufacturer_code,nor_id.device_code1, + nor_id.device_code2,nor_id.device_code3); + nor_return_to_read_mode(); + + /* erase the nor flash block to be written data */ + status = nor_eraseblock(WRITE_READ_ADDR); + if(NOR_SUCCESS == status){ + printf("\r\nerase nor flash block successfully!"); + }else{ + printf("\r\nerase nor flash block failure!"); + while(1); + } + /* read data from nor flash, WRITE_READ_ADDR: the starting address of the read data*/ + nor_readbuffer(readbuffer, WRITE_READ_ADDR, BUFFER_SIZE); + + /* whether address cross-border */ + if((WRITE_READ_ADDR + BUFFER_SIZE ) > NOR_MAX_ADDRESS){ + printf("\n\raddress cross-border\n\r"); + while(1); + } + + /* fill writeBuffer with the specified value */ + nor_fill_buffer(writebuffer, BUFFER_SIZE, 0x0004); + + /* write data to nor flash, WRITE_READ_ADDR: the starting address of the write data */ + status = nor_write_buffer(writebuffer, WRITE_READ_ADDR, BUFFER_SIZE); + if(NOR_SUCCESS == status){ + printf("\r\nwrite data to nor flash block successfully!"); + }else{ + printf("\r\nwrite data to nor flash block failure!"); + + while(1); + } + + /* read data from nor flash, WRITE_READ_ADDR: the starting address of the read data*/ + nor_readbuffer(readbuffer, WRITE_READ_ADDR, BUFFER_SIZE); + + /* read and write data comparison for equality */ + writereadstatus = 0; + for(i = 0x00; i < BUFFER_SIZE; i++){ + if (readbuffer[i] != writebuffer[i]){ + writereadstatus++; + break; + } + } + + printf("\n\rthe result to access the nor flash:\n\r"); + if(writereadstatus == 0) + { + printf("\n\raccess nor flash successfully!\n\r"); + }else{ + printf("\n\raccess nor flash failure!\n\r"); + while(1); + } + + printf("\n\rprintf data to be read: \n\r"); + printf("\n\r"); + for(i = 0; i < BUFFER_SIZE; i++) + { + printf("%d ",readbuffer[i]); + } + while(1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/NOR/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/NOR/readme.txt new file mode 100644 index 0000000..8bfb1bd --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/NOR/readme.txt @@ -0,0 +1,40 @@ +/*! + \file readme.txt + \brief description of the EXMC_NOR demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V board, it shows how to use EXMC peripheral to +control NOR memory. + + This demo shows the write and read data operation process of NOR memory by +EXMC module. If the operation is correct, a success information and the data writed +to the NOR memory. Otherwise, a failure information will be printed out. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/SRAM/exmc_sram.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/SRAM/exmc_sram.c new file mode 100644 index 0000000..3819a32 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/SRAM/exmc_sram.c @@ -0,0 +1,239 @@ +/*! + \file exmc_sram.c + \brief EXMC SRAM(ISSI IS61LV51216) driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "exmc_sram.h" + +#define Bank0_SRAM2_ADDR ((uint32_t)0x60000000) +#define BANK_SRAM_ADDR Bank0_SRAM2_ADDR + +/*! + \brief SRAM peripheral initialize + \param[in] none + \param[out] none + \retval none +*/ +void exmc_sram_init(void) +{ + exmc_norsram_parameter_struct nor_init_struct; + exmc_norsram_timing_parameter_struct nor_timing_init_struct; + + /* EXMC clock enable */ + rcu_periph_clock_enable(RCU_EXMC); + + /* EXMC enable */ + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_GPIOD); + rcu_periph_clock_enable(RCU_GPIOE); + + /* configure EXMC_D[0~15]*/ + /* PD14(EXMC_D0), PD15(EXMC_D1),PD0(EXMC_D2), PD1(EXMC_D3), PD8(EXMC_D13), PD9(EXMC_D14), PD10(EXMC_D15) */ + gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1| GPIO_PIN_8 | GPIO_PIN_9 | + GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15); + + /* PE7(EXMC_D4), PE8(EXMC_D5), PE9(EXMC_D6), PE10(EXMC_D7), PE11(EXMC_D8), PE12(EXMC_D9), + PE13(EXMC_D10), PE14(EXMC_D11), PE15(EXMC_D12) */ + gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | + GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | + GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15); + /* PD11(EXMC_A16), PD12(EXMC_A17), PD13(EXMC_A18) */ + gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13); + + /* configure NOE(PD4),NWE(PD5) and NE0(PD7) */ + gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_7); + + /* configure NBL0(PE0) and NBL1(PE1) */ + gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1); + + /* configure EXMC NADV (PB7) */ + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_7); + + /* configure timing parameter */ + nor_timing_init_struct.bus_latency = 1; + nor_timing_init_struct.asyn_data_setuptime = 7; + nor_timing_init_struct.asyn_address_holdtime = 2; + nor_timing_init_struct.asyn_address_setuptime = 5; + + /* configure EXMC bus parameters */ + nor_init_struct.norsram_region = EXMC_BANK0_NORSRAM_REGION0; + nor_init_struct.asyn_wait = DISABLE; + nor_init_struct.nwait_signal = DISABLE; + nor_init_struct.memory_write = ENABLE; + nor_init_struct.nwait_polarity = EXMC_NWAIT_POLARITY_LOW; + nor_init_struct.databus_width = EXMC_NOR_DATABUS_WIDTH_16B; + nor_init_struct.memory_type = EXMC_MEMORY_TYPE_SRAM; + nor_init_struct.address_data_mux = ENABLE; + nor_init_struct.read_write_timing = &nor_timing_init_struct; + exmc_norsram_init(&nor_init_struct); + + /* enable the EXMC bank0 NORSRAM */ + exmc_norsram_enable(EXMC_BANK0_NORSRAM_REGION0); +} + +/*! + \brief write a Half-word buffer(data is 16 bits) to the EXMC SRAM memory + \param[in] pbuffer : pointer to buffer + \param[in] writeaddr : SRAM memory internal address from which the data will be written + \param[in] num_halfword_write : number of half-words to write + \param[out] none + \retval none +*/ +void exmc_sram_writebuffer_16(uint16_t* pbuffer, uint32_t writeaddr, uint32_t num_halfword_write) +{ + /* while there is data to write */ + for(;num_halfword_write != 0;num_halfword_write--){ + /* transfer data to the memory */ + *(uint16_t *) (BANK_SRAM_ADDR + writeaddr) = *pbuffer++; + + /* increment the address */ + writeaddr += 2; + } +} + +/*! + \brief read a block of 16-bit data from the EXMC SRAM memory + \param[in] pbuffer : pointer to the buffer that receives the data read from the SRAM memory + \param[in] readaddr : SRAM memory internal address to read from + \param[in] num_halfword_read : number of half-words to read + \param[out] none + \retval none +*/ +void exmc_sram_readbuffer_16(uint16_t* pbuffer, uint32_t readaddr, uint32_t num_halfword_read) +{ + /* while there is data to read */ + for(; num_halfword_read != 0; num_halfword_read--) { + /* read a half-word from the memory */ + *pbuffer++ = *(uint16_t*) (BANK_SRAM_ADDR + readaddr); + + /* increment the address */ + readaddr += 2; + } +} + +/*! + \brief write a word buffer(data is 32 bits) to the EXMC SRAM memory + \param[in] pbuffer : pointer to buffer + \param[in] writeaddr : SRAM memory internal address from which the data will be written + \param[in] num_word_write : number of words to write + \param[out] none + \retval none +*/ +void exmc_sram_writebuffer_32(uint32_t* pbuffer, uint32_t writeaddr, uint32_t num_word_write) +{ + /* while there is data to write */ + for(; num_word_write != 0; num_word_write--){ + /* transfer data to the memory */ + *(uint32_t *)(BANK_SRAM_ADDR + writeaddr) = *pbuffer++; + + /* increment the address */ + writeaddr += 4; + } +} + +/*! + \brief read a block of 32-bit data from the EXMC SRAM memory + \param[in] pbuffer : pointer to the buffer that receives the data read from the SRAM memory + \param[in] readaddr : SRAM memory internal address to read from + \param[in] num_word_read : number of words to read + \param[out] none + \retval none +*/ +void exmc_sram_readbuffer_32(uint32_t* pbuffer, uint32_t readaddr, uint32_t num_word_read) +{ + /* while there is data to read */ + for(; num_word_read != 0; num_word_read--){ + /* read a word from the memory */ + *pbuffer++ = *(uint32_t*) (BANK_SRAM_ADDR + readaddr); + + /* increment the address */ + readaddr += 4; + } +} + +/*! + \brief write a Byte buffer(data is 8 bits ) to the EXMC SRAM memory + \param[in] pbuffer : pointer to buffer + \param[in] writeaddr : SRAM memory internal address from which the data will be written + \param[in] num_byte_write : number of bytes to write + \param[out] none + \retval none +*/ +void exmc_sram_writebuffer_8(uint8_t* pbuffer, uint32_t writeaddr, uint32_t num_byte_write) +{ + /* while there is data to write */ + for(; num_byte_write != 0; num_byte_write--){ + /* transfer data to the memory */ + *(uint8_t *) (BANK_SRAM_ADDR + writeaddr) = *pbuffer++; + + /* increment the address*/ + writeaddr += 1; + } +} + +/*! + \brief read a block of 8-bit data from the EXMC SRAM memory + \param[in] pbuffer : pointer to the buffer that receives the data read from the SRAM memory + \param[in] readaddr : SRAM memory internal address to read from + \param[in] num_byte_read : number of bytes to write + \param[out] none + \retval none +*/ +void exmc_sram_readbuffer_8(uint8_t* pbuffer, uint32_t readaddr, uint32_t num_byte_read) +{ + /* while there is data to read */ + for(; num_byte_read != 0; num_byte_read--){ + /* read a byte from the memory */ + *pbuffer++ = *(uint8_t*) (BANK_SRAM_ADDR + readaddr); + + /* increment the address */ + readaddr += 1; + } +} + +/*! + \brief fill the 16-bit buffer with specified value + \param[in] pbuffer: pointer on the buffer to fill + \param[in] buffersize: size of the buffer to fill + \param[in] offset: first value to fill on the buffer + \param[out] none + \retval none +*/ +void fill_buffer_16(uint16_t *pbuffer, uint16_t buffer_lenght, uint16_t offset) +{ + uint16_t index = 0; + + for(index = 0; index < buffer_lenght; index++ ){ + pbuffer[index] = index + offset; + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/SRAM/exmc_sram.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/SRAM/exmc_sram.h new file mode 100644 index 0000000..530f96a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/SRAM/exmc_sram.h @@ -0,0 +1,58 @@ +/*! + \file exmc_sram.h + \brief the header file of EXMC SRAM(ISSI IS61LV51216) driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef EXMC_SRAM_H +#define EXMC_SRAM_H + +#include "gd32vf103.h" + +/* function declarations */ +/* SRAM peripheral initialize */ +void exmc_sram_init(void); +/* write a Half-word buffer(data is 16 bits) to the EXMC SRAM memory */ +void exmc_sram_writebuffer_16(uint16_t* pbuffer, uint32_t writeaddr, uint32_t num_halfword_write); +/* read a block of 16-bit data from the EXMC SRAM memory */ +void exmc_sram_readbuffer_16(uint16_t* pbuffer, uint32_t readaddr, uint32_t num_halfword_read); +/* write a Byte buffer(data is 8 bits ) to the EXMC SRAM memory */ +void exmc_sram_writebuffer_8(uint8_t* pbuffer, uint32_t writeaddr, uint32_t num_byte_write); +/* read a block of 8-bit data from the EXMC SRAM memory */ +void exmc_sram_readbuffer_8(uint8_t* pbuffer, uint32_t readaddr, uint32_t num_byte_read); +/* write a word buffer(data is 32 bits) to the EXMC SRAM memory */ +void exmc_sram_writebuffer_32(uint32_t* pbuffer, uint32_t writeaddr, uint32_t num_word_write); +/* read a block of 32-bit data from the EXMC SRAM memory */ +void exmc_sram_readbuffer_32(uint32_t* pbuffer, uint32_t readaddr, uint32_t num_word_read); +/* fill the 16-bit buffer with specified value */ +void fill_buffer_16(uint16_t *pbuffer, uint16_t buffer_lenght, uint16_t offset); + +#endif /* EXMC_SRAM_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/SRAM/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/SRAM/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/SRAM/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/SRAM/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/SRAM/main.c new file mode 100644 index 0000000..845c412 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/SRAM/main.c @@ -0,0 +1,88 @@ +/*! + \file main.c + \brief EXMC SRAM demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" +#include +#include "exmc_sram.h" + +#define BUFFER_SIZE 4 /*!< write or read buffer size */ +#define WRITE_READ_ADDR 0x0000 /*!< SRAM write or read address */ + +uint16_t txbuffer[BUFFER_SIZE]; +uint16_t rxbuffer[BUFFER_SIZE]; +uint16_t writereadstatus = 0; + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + uint16_t i = 0; + + /* configure the USART */ + gd_eval_com_init(EVAL_COM0); + /* configure the EXMC access mode */ + exmc_sram_init(); + /* fill txbuffer */ + fill_buffer_16(txbuffer, BUFFER_SIZE, 0x1215); + /* write data to SRAM */ + exmc_sram_writebuffer_16(txbuffer, WRITE_READ_ADDR, BUFFER_SIZE); + /* read data from SRAM */ + exmc_sram_readbuffer_16(rxbuffer, WRITE_READ_ADDR, BUFFER_SIZE); + /* compare two buffers */ + for(i = 0;i < BUFFER_SIZE;i++){ + if (rxbuffer[i] != txbuffer[i]){ + writereadstatus ++; + break; + } + } + if(writereadstatus){ + printf("SRAM test failed!\r\n"); + }else{ + printf("SRAM test successed!\r\n"); + printf("the data is:\r\n"); + for(i=0;i < BUFFER_SIZE;i++){ + printf("%6x",rxbuffer[i]); + if(((i+1)%6) == 0){ + printf("\r\n"); + } + } + } + + while(1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/SRAM/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/SRAM/readme.txt new file mode 100644 index 0000000..384f72c --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXMC/SRAM/readme.txt @@ -0,0 +1,41 @@ +/*! + \file readme.txt + \brief description of the EXMC_SRAM demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V board, it shows how to use EXMC peripheral +to control SRAM memory. + + This demo shows the write and read data operation process of SRAM memory by EXMC +module. If the operation is correct, "SRAM test successed!" will be printed and the +data read from the SRAM will be printed out. Otherwise, "SRAM test failed!" will be +printed. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXTI/Key_external_interrupt_mode/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXTI/Key_external_interrupt_mode/gd32vf103_it.c new file mode 100644 index 0000000..508218a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXTI/Key_external_interrupt_mode/gd32vf103_it.c @@ -0,0 +1,55 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_it.h" +#include "gd32vf103v_eval.h" + +/*! + \brief this function handles external lines 10 to 15 interrupt request + \param[in] none + \param[out] none + \retval none +*/ +void EXTI10_15_IRQHandler(void) +{ + if (RESET != exti_interrupt_flag_get(KEY_B_PIN)){ + exti_interrupt_flag_clear(KEY_B_PIN); + + if(RESET == gd_eval_key_state_get(KEY_B_PIN)){ + gd_eval_led_toggle(LED3); + } + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXTI/Key_external_interrupt_mode/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXTI/Key_external_interrupt_mode/gd32vf103_it.h new file mode 100644 index 0000000..e0f9b45 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXTI/Key_external_interrupt_mode/gd32vf103_it.h @@ -0,0 +1,47 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ +/* this function handles external lines 10 to 15 interrupt request */ +void EXTI10_15_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXTI/Key_external_interrupt_mode/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXTI/Key_external_interrupt_mode/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXTI/Key_external_interrupt_mode/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXTI/Key_external_interrupt_mode/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXTI/Key_external_interrupt_mode/main.c new file mode 100644 index 0000000..baff91d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXTI/Key_external_interrupt_mode/main.c @@ -0,0 +1,97 @@ +/*! + \file main.c + \brief the example of EXTI which generates an interrupt request and toggle the LED + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" + +void key_gpio_init(void); +void key_exti_init(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ + +int main(void) +{ + /* initialize the LEDs and turn on LED2 */ + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + gd_eval_led_on(LED2); + + /* initialize the key */ + key_gpio_init(); + key_exti_init(); + + while (1); +} + +/*! + \brief initialize the key GPIO + \param[in] none + \param[out] none + \retval none +*/ +void key_gpio_init(void) +{ + /* enable the key gpio clock */ + rcu_periph_clock_enable(RCU_GPIOC); + /* configure button pin as input */ + gpio_init(GPIOC, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_13); +} + +/*! + \brief initialize the EXTI configuration of the key + \param[in] none + \param[out] none + \retval none +*/ +void key_exti_init(void) +{ + /* enable the AF clock */ + rcu_periph_clock_enable(RCU_AF); + /* enable and set key EXTI interrupt to the specified priority */ + eclic_global_interrupt_enable(); + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL3_PRIO1); + eclic_irq_enable(EXTI10_15_IRQn, 1, 1); + + /* connect key EXTI line to key GPIO pin */ + gpio_exti_source_select(GPIO_PORT_SOURCE_GPIOC, GPIO_PIN_SOURCE_13); + + /* configure key EXTI line */ + exti_init(EXTI_13, EXTI_INTERRUPT, EXTI_TRIG_FALLING); + exti_interrupt_flag_clear(EXTI_13); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXTI/Key_external_interrupt_mode/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXTI/Key_external_interrupt_mode/readme.txt new file mode 100644 index 0000000..fb1a69d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/EXTI/Key_external_interrupt_mode/readme.txt @@ -0,0 +1,43 @@ +/*! + \file readme.txt + \brief description of the EXTI Key example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it shows how to generate +the interrupt request, and toggle the LED. After the system start-up, LED2 is on. +When Key B is pressed, LED3 is toggled, it is switched on; when Key B is pressed +once again, LED3 is toggled, it is switched off. + + On the GD32VF103V-EVAL-V1.0 board, LED1 connected to PC0, LED2 connected to PC2, LED3 +connected to PE0, LED4 connected to PE1. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Erase_Program/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Erase_Program/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Erase_Program/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Erase_Program/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Erase_Program/main.c new file mode 100644 index 0000000..0d2c293 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Erase_Program/main.c @@ -0,0 +1,183 @@ +/*! + \file main.c + \brief main flash program, erase + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" +#include "main.h" + +#define FMC_PAGE_SIZE ((uint16_t)0x400U) +#define FMC_WRITE_START_ADDR ((uint32_t)0x08004000U) +#define FMC_WRITE_END_ADDR ((uint32_t)0x08004800U) + +uint32_t *ptrd; +uint32_t address = 0x00; +uint32_t data0 = 0x01234567U; +led_typedef_enum led_num = LED4; + +/* calculate the num of page to be programmed/erased */ +uint32_t page_num = (FMC_WRITE_END_ADDR - FMC_WRITE_START_ADDR) / FMC_PAGE_SIZE; +/* calculate the num of page to be programmed/erased */ +uint32_t word_num = ((FMC_WRITE_END_ADDR - FMC_WRITE_START_ADDR) >> 2); + +/*! + \brief erase fmc pages from FMC_WRITE_START_ADDR to FMC_WRITE_END_ADDR + \param[in] none + \param[out] none + \retval none +*/ +void fmc_erase_pages(void) +{ + uint32_t erase_counter; + + /* unlock the flash program/erase controller */ + fmc_unlock(); + + /* clear all pending flags */ + fmc_flag_clear(FMC_FLAG_END); + fmc_flag_clear(FMC_FLAG_WPERR); + fmc_flag_clear(FMC_FLAG_PGERR); + + /* erase the flash pages */ + for(erase_counter = 0; erase_counter < page_num; erase_counter++){ + fmc_page_erase(FMC_WRITE_START_ADDR + (FMC_PAGE_SIZE * erase_counter)); + fmc_flag_clear(FMC_FLAG_END); + fmc_flag_clear(FMC_FLAG_WPERR); + fmc_flag_clear(FMC_FLAG_PGERR); + } + + /* lock the main FMC after the erase operation */ + fmc_lock(); +} + +/*! + \brief program fmc word by word from FMC_WRITE_START_ADDR to FMC_WRITE_END_ADDR + \param[in] none + \param[out] none + \retval none +*/ +void fmc_program(void) +{ + /* unlock the flash program/erase controller */ + fmc_unlock(); + + address = FMC_WRITE_START_ADDR; + + /* program flash */ + while(address < FMC_WRITE_END_ADDR){ + fmc_word_program(address, data0); + address += 4; + fmc_flag_clear(FMC_FLAG_END); + fmc_flag_clear(FMC_FLAG_WPERR); + fmc_flag_clear(FMC_FLAG_PGERR); + } + + /* lock the main FMC after the program operation */ + fmc_lock(); +} + +/*! + \brief check fmc erase result + \param[in] none + \param[out] none + \retval none +*/ +void fmc_erase_pages_check(void) +{ + uint32_t i; + + ptrd = (uint32_t *)FMC_WRITE_START_ADDR; + + /* check flash whether has been erased */ + for(i = 0; i < word_num; i++){ + if(0xFFFFFFFF != (*ptrd)){ + led_num = LED2; + gd_eval_led_on(led_num); + break; + }else{ + ptrd++; + } + } +} + +/*! + \brief check fmc program result + \param[in] none + \param[out] none + \retval none +*/ +void fmc_program_check(void) +{ + uint32_t i; + + ptrd = (uint32_t *)FMC_WRITE_START_ADDR; + + /* check flash whether has been programmed */ + for(i = 0; i < word_num; i++){ + if((*ptrd) != data0){ + led_num = LED3; + gd_eval_led_on(led_num); + break; + }else{ + ptrd++; + } + } +} + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* initialize led on the board */ + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + gd_eval_led_init(LED4); + + /* step1: erase pages and check if it is successful. if not, light the LED2 */ + fmc_erase_pages(); + fmc_erase_pages_check(); + + /* step2: program and check if it is successful. if not, light the LED3 */ + fmc_program(); + fmc_program_check(); + + /* if all the operations are successful, light the LED4 */ + gd_eval_led_on(led_num); + + while(1); +} + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Erase_Program/main.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Erase_Program/main.h new file mode 100644 index 0000000..bc70b70 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Erase_Program/main.h @@ -0,0 +1,47 @@ +/*! + \file main.h + \brief the header file of main + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef MAIN_H +#define MAIN_H + +/* erase fmc pages from FMC_WRITE_START_ADDR to FMC_WRITE_END_ADDR */ +void fmc_erase_pages(void); +/* program fmc word by word from FMC_WRITE_START_ADDR to FMC_WRITE_END_ADDR */ +void fmc_program(void); +/* check fmc erase result */ +void fmc_erase_pages_check(void); +/* check fmc program result */ +void fmc_program_check(void); + +#endif diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Erase_Program/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Erase_Program/readme.txt new file mode 100644 index 0000000..dd65db1 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Erase_Program/readme.txt @@ -0,0 +1,46 @@ +/*! + \file readme.txt + \brief description of the Erase_Program example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it provides a description of +how to erase and program flash memory. + + In erasing operation, a comparison between flash memory and 0xffffffff is done to +check whether the flash memory has been correctly erased. If the result is wrong, +LED2 will be on. + + In programming operation, a comparison between flash memory and target data is +done to check whether the flash memory has been correctly programmed. If the result +is wrong, LED3 will be on. + + If all the three operations are successful, LED4 will be on. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Write_Protection/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Write_Protection/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Write_Protection/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Write_Protection/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Write_Protection/main.c new file mode 100644 index 0000000..7e00aa4 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Write_Protection/main.c @@ -0,0 +1,158 @@ +/*! + \file main.c + \brief main flash program, write_protection + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" +#include + +#define FLASH_PAGE_PROGRAM +//#define WRITE_PROTECTION_ENABLE +#define WRITE_PROTECTION_DISABLE + +typedef enum {FAILED = 0, PASSED = !FAILED} test_state; +#define FLASH_PAGE_SIZE ((uint16_t)0x400) +#define FMC_PAGES_PROTECTED (OB_WP_4 | OB_WP_5) + +#define WRITE_START_ADDR ((uint32_t)0x08004000) +#define WRITE_END_ADDR ((uint32_t)0x08010000) + +uint32_t erase_counter = 0x0, address = 0x0; +uint32_t data = 0x5a5a5a5a; +uint32_t wp_value = 0xFFFFFFFF, protected_pages = 0x0; +uint32_t page_number; +__IO fmc_state_enum fmc_state = FMC_READY; +__IO test_state program_state = PASSED; + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* initialize led on the board */ + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + + /* unlock the flash program/erase controller */ + fmc_unlock(); + ob_unlock(); + + fmc_flag_clear(FMC_FLAG_END); + fmc_flag_clear(FMC_FLAG_WPERR); + fmc_flag_clear(FMC_FLAG_PGERR); + + /* get pages write protection status */ + wp_value = ob_write_protection_get(); + +#ifdef WRITE_PROTECTION_DISABLE + /* get pages already write protected */ + protected_pages = ~(wp_value | FMC_PAGES_PROTECTED); + /* check if desired pages are already write protected */ + if((wp_value | (~FMC_PAGES_PROTECTED)) != 0xFFFFFFFF ){ + /* erase all the option Bytes */ + fmc_state = ob_erase(); + + /* check if there is write protected pages */ + if(protected_pages != 0x0){ + /* Restore write protected pages */ + fmc_state = ob_write_protection_enable(protected_pages); + } + /* generate system reset to load the new option byte values */ + eclic_system_reset(); + } +#elif defined WRITE_PROTECTION_ENABLE + /* get current write protected pages and the new pages to be protected */ + protected_pages = (~wp_value) | FMC_PAGES_PROTECTED; + + /* check if desired pages are not yet write protected */ + if(((~wp_value) & FMC_PAGES_PROTECTED )!= FMC_PAGES_PROTECTED){ + + /* erase all the option bytes because if a program operation is + performed on a protected page, the flash memory returns a + protection error */ + fmc_state = ob_erase(); + + /* enable the pages write protection */ + fmc_state = ob_write_protection_enable(protected_pages); + + /* generate system reset to load the new option byte values */ + eclic_system_reset(); + } +#endif /* WRITE_PROTECTION_DISABLE */ + +#ifdef FLASH_PAGE_PROGRAM + /* get the number of pages to be erased */ + page_number = (WRITE_END_ADDR - WRITE_START_ADDR) / FLASH_PAGE_SIZE; + + /* the selected pages are not write protected */ + if(0x00 != (wp_value & FMC_PAGES_PROTECTED)){ + /* clear all pending flags */ + fmc_flag_clear(FMC_FLAG_END); + fmc_flag_clear(FMC_FLAG_WPERR); + fmc_flag_clear(FMC_FLAG_PGERR); + + /* erase the flash pages */ + for(erase_counter = 0; (erase_counter < page_number) && (FMC_READY == fmc_state); erase_counter++){ + fmc_state = fmc_page_erase(WRITE_START_ADDR + (FLASH_PAGE_SIZE * erase_counter)); + } + + /* flash word program of data 0x5a5a5a5a at addresses defined by WRITE_START_ADDR and WRITE_END_ADDR */ + address = WRITE_START_ADDR; + + while((address < WRITE_END_ADDR) && (FMC_READY == fmc_state)){ + fmc_state = fmc_word_program(address, data); + address = address + 4; + } + /* check the correctness of written data */ + address = WRITE_START_ADDR; + + while((address < WRITE_END_ADDR) && (FAILED != program_state)){ + if(REG32(address) != data){ + program_state = FAILED; + } + address += 4; + } + gd_eval_led_on(LED2); + } + else{ + /* error to program the flash: the desired pages are write protected */ + program_state = FAILED; + gd_eval_led_on(LED3); + } +#endif /* FLASH_PAGE_PROGRAM */ + while(1){ + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Write_Protection/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Write_Protection/readme.txt new file mode 100644 index 0000000..df8937d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FMC/Write_Protection/readme.txt @@ -0,0 +1,46 @@ +/*! + \file readme.txt + \brief description of the Write_Protection example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it provides a description of how to +enable and disable the write protection for the embedded flash. + + Uncomment the line "#define WRITE_PROTECTION_ENABLE" and "#define FLASH_PAGE_PROGRAM" +in main.c file, download the program, an error will occur to program the flash and LED3 +will on. + + Uncomment the line "#define WRITE_PROTECTION_DISABLE" and "#define FLASH_PAGE_PROGRAM" +in main.c file, download the program, the flash will be writeen correctly and LED2 will on. + + User can check the value of FMC_WP register to verify if the write protected operation is +successful or not. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/gd32vf103_it.c new file mode 100644 index 0000000..e7a6f3c --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/gd32vf103_it.c @@ -0,0 +1,55 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_it.h" +#include "gd32vf103v_eval.h" + + +/*! + \brief this function handles external lines 10 to 15 interrupt request + \param[in] none + \param[out] none + \retval none +*/ +void EXTI10_15_IRQHandler(void) +{ + /* make sure whether the EXTI Line is interrupted */ + if(RESET != exti_interrupt_flag_get(EXTI_13)){ + /* reload FWDGT counter */ + fwdgt_counter_reload(); + } + + /* clear the interrupt flag bit */ + exti_interrupt_flag_clear(EXTI_13); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/gd32vf103_it.h new file mode 100644 index 0000000..0c96ab1 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/gd32vf103_it.h @@ -0,0 +1,44 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ +/* external lines 10 to 15 interrupt handle function */ +void EXTI10_15_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/main.c new file mode 100644 index 0000000..c9ae4d1 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/main.c @@ -0,0 +1,110 @@ +/*! + \file main.c + \brief FWDGT key demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" +#include "gd32vf103v_eval.h" + +#define BKP_DATA_REG_NUM 42 + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* enable IRC40K */ + rcu_osci_on(RCU_IRC40K); + + /* wait till IRC40K is ready */ + while(SUCCESS != rcu_osci_stab_wait(RCU_IRC40K)){ + } + /* config systick */ + //systick_config(); + /* configure LED */ + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + + /* configure the Tamper key which is used to reload FWDGT */ + gd_eval_key_init(KEY_B, KEY_MODE_EXTI); + delay_1ms(500); + /* confiure FWDGT counter clock: 40KHz(IRC40K) / 64 = 0.625 KHz */ + fwdgt_config(2*500, FWDGT_PSC_DIV64); + /* after 1.6 seconds to generate a reset */ + fwdgt_enable(); + + /* check if the system has resumed from FWDGT reset */ + if(RESET != rcu_flag_get(RCU_FLAG_FWDGTRST)){ + /* turn on LED3 */ + gd_eval_led_on(LED3); + /* clear the FWDGT reset flag */ + rcu_all_reset_flag_clear(); + + while(1){ + } + }else{ + /* turn on LED2 */ + gd_eval_led_on(LED2); + } + while(1){ + } +} + +/*! + \brief check if the backup data registers are clear or not + \param[in] none + \param[out] none + \retval the number of data register +*/ +uint32_t is_backup_register_clear(void) +{ + uint32_t temp = 0; + + for(temp = 0; temp < BKP_DATA_REG_NUM; temp++){ + if(temp < 10){ + /* check if the data of data register 0-9 is 0x0000 */ + if(0x0000 != BKP_DATA_GET(BKP_DATA0_9(temp))){ + return temp+1; + } + }else{ + /* check if the data of data register 10-41 is 0x0000 */ + if(0x0000 != BKP_DATA_GET(BKP_DATA10_41(temp))){ + return temp+1; + } + } + } + return 0; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/readme.txt new file mode 100644 index 0000000..aea41ef --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/readme.txt @@ -0,0 +1,48 @@ +/*! + \file readme.txt + \brief description of the FWDGT_key example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to reload the +FWDGT counter at regulate period using the EXTI interrupt. The FWDGT timeout +is set to 1.6s (the timeout may varies due to IRC40K frequency dispersion). + + An EXTI is connected to a specific GPIO pin and configured to generate an interrupt +on its falling edge: when the EXTI Line interrupt is triggered (by pressing the Key_B +on the board), the corresponding interrupt is served. In the ISR, FWDGT counter is +reloaded). As a result, when the FWDGT counter is reloaded, which prevents any FWDGT +reset, LED2 or LED3 remains illuminated. + + If the EXTI Line interrupt does not occur, the FWDGT counter is not reloaded before +the FWDGT counter reaches 00h, and the FWDGT reset. If the FWDGT reset is generated, +LED2 and LED3 are turned off with the system reset. FWDGTRST flag is set by hardware, +and then LED3 is turned on. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/systick.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/systick.c new file mode 100644 index 0000000..4296e59 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/systick.c @@ -0,0 +1,57 @@ +/*! + \file systick.c + \brief the systick configuration file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" + +/*! + \brief delay a time in milliseconds + \param[in] count: count in milliseconds + \param[out] none + \retval none +*/ +void delay_1ms(uint32_t count) +{ + uint64_t start_mtime, delta_mtime; + + // Don't start measuruing until we see an mtime tick + uint64_t tmp = get_timer_value(); + do { + start_mtime = get_timer_value(); + } while (start_mtime == tmp); + + do { + delta_mtime = get_timer_value() - start_mtime; + }while(delta_mtime <(SystemCoreClock/4000.0 *count )); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/systick.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/systick.h new file mode 100644 index 0000000..9a74c22 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/FWDGT/FWDGT_key/systick.h @@ -0,0 +1,42 @@ +/*! + \file systick.h + \brief the header file of systick + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef SYS_TICK_H +#define SYS_TICK_H + +#include + +void delay_1ms(uint32_t count); + +#endif /* SYS_TICK_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Keyboard_polling_mode/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Keyboard_polling_mode/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Keyboard_polling_mode/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Keyboard_polling_mode/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Keyboard_polling_mode/main.c new file mode 100644 index 0000000..07347b5 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Keyboard_polling_mode/main.c @@ -0,0 +1,75 @@ +/*! + \file main.c + \brief keyboard polling mode + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" +#include "gd32vf103v_eval.h" +#include + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* enable the LED1 clock */ + rcu_periph_clock_enable(RCU_GPIOC); + /* configure LED1 GPIO port */ + gpio_init(GPIOC, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0); + + gpio_bit_reset(GPIOC, GPIO_PIN_0); + + /* enable the KEY_B clock */ + rcu_periph_clock_enable(RCU_GPIOC); + rcu_periph_clock_enable(RCU_AF); + + /* configure button pin as input */ + gpio_init(GPIOC, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_13); + + while(1){ + /* check whether the button is pressed */ + if(RESET == gpio_input_bit_get(GPIOC, GPIO_PIN_13)){ + delay_1ms(100); + + /* check whether the button is pressed */ + if(RESET == gpio_input_bit_get(GPIOC, GPIO_PIN_13)){ + gpio_bit_write(GPIOC, GPIO_PIN_0, (bit_status)(1-gpio_input_bit_get(GPIOC, GPIO_PIN_0))); + } + while(RESET == gpio_input_bit_get(GPIOC, GPIO_PIN_13)){ + } + } + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Keyboard_polling_mode/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Keyboard_polling_mode/readme.txt new file mode 100644 index 0000000..542a0b6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Keyboard_polling_mode/readme.txt @@ -0,0 +1,44 @@ +/*! + \file readme.txt + \brief description of keyboard polling mode example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it provides a description +of how to use Tamper key to control the LED1. The example uses polling mode. + + Press the KEY_B, LED1 will be on. Press the KEY_B again, LED1 will be off. + + On the GD32VF103V-EVAL-V1.0 board, the Tamper key is connected to PA0 and the LED1 +is connected to PC0. + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Keyboard_polling_mode/systick.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Keyboard_polling_mode/systick.c new file mode 100644 index 0000000..83344fa --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Keyboard_polling_mode/systick.c @@ -0,0 +1,57 @@ +/*! + \file systick.c + \brief the systick configuration file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" + +/*! + \brief delay a time in milliseconds + \param[in] count: count in milliseconds + \param[out] none + \retval none +*/ +void delay_1ms(uint32_t count) +{ + uint64_t start_mtime, delta_mtime; + + /* Don't start measuruing until we see an mtime tick */ + uint64_t tmp = get_timer_value(); + do { + start_mtime = get_timer_value(); + } while (start_mtime == tmp); + + do { + delta_mtime = get_timer_value() - start_mtime; + }while(delta_mtime <(SystemCoreClock/4000.0 *count )); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Keyboard_polling_mode/systick.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Keyboard_polling_mode/systick.h new file mode 100644 index 0000000..9a74c22 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Keyboard_polling_mode/systick.h @@ -0,0 +1,42 @@ +/*! + \file systick.h + \brief the header file of systick + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef SYS_TICK_H +#define SYS_TICK_H + +#include + +void delay_1ms(uint32_t count); + +#endif /* SYS_TICK_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Running_led/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Running_led/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Running_led/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Running_led/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Running_led/main.c new file mode 100644 index 0000000..83ba26e --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Running_led/main.c @@ -0,0 +1,79 @@ +/*! + \file main.c + \brief running led + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" +#include "systick.h" +#include + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* enable the LED clock */ + rcu_periph_clock_enable(RCU_GPIOC); + rcu_periph_clock_enable(RCU_GPIOE); + /* configure LED GPIO port */ + gpio_init(GPIOC, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_2); + gpio_init(GPIOE, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1); + + gpio_bit_reset(GPIOC, GPIO_PIN_0 | GPIO_PIN_2); + gpio_bit_reset(GPIOE, GPIO_PIN_0 | GPIO_PIN_1); + + while(1){ + /* turn on LED1, turn off LED4 */ + gpio_bit_set(GPIOC, GPIO_PIN_0); + gpio_bit_reset(GPIOE, GPIO_PIN_1); + delay_1ms(1000); + + /* turn on LED2, turn off LED1 */ + gpio_bit_set(GPIOC, GPIO_PIN_2); + gpio_bit_reset(GPIOC, GPIO_PIN_0); + delay_1ms(1000); + + /* turn on LED3, turn off LED2 */ + gpio_bit_set(GPIOE, GPIO_PIN_0); + gpio_bit_reset(GPIOC, GPIO_PIN_2); + delay_1ms(1000); + + /* turn on LED4, turn off LED3 */ + gpio_bit_set(GPIOE, GPIO_PIN_1); + gpio_bit_reset(GPIOE, GPIO_PIN_0); + delay_1ms(1000); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Running_led/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Running_led/readme.txt new file mode 100644 index 0000000..2ca093d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Running_led/readme.txt @@ -0,0 +1,40 @@ +/*! + \file readme.txt + \brief description of running led example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it provides a description +of Running_led. After system start-up, firstly, LED1 on, then, LED2 on, four +LEDs can light periodically. + + On the GD32VF103V-EVAL-V1.0 board,LED1 connected to PC0, LED2 connected to PC2, LED3 +connected to PE0, LED4 connected to PE1. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Running_led/systick.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Running_led/systick.c new file mode 100644 index 0000000..83344fa --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Running_led/systick.c @@ -0,0 +1,57 @@ +/*! + \file systick.c + \brief the systick configuration file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" + +/*! + \brief delay a time in milliseconds + \param[in] count: count in milliseconds + \param[out] none + \retval none +*/ +void delay_1ms(uint32_t count) +{ + uint64_t start_mtime, delta_mtime; + + /* Don't start measuruing until we see an mtime tick */ + uint64_t tmp = get_timer_value(); + do { + start_mtime = get_timer_value(); + } while (start_mtime == tmp); + + do { + delta_mtime = get_timer_value() - start_mtime; + }while(delta_mtime <(SystemCoreClock/4000.0 *count )); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Running_led/systick.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Running_led/systick.h new file mode 100644 index 0000000..9a74c22 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/GPIO/Running_led/systick.h @@ -0,0 +1,42 @@ +/*! + \file systick.h + \brief the header file of systick + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef SYS_TICK_H +#define SYS_TICK_H + +#include + +void delay_1ms(uint32_t count); + +#endif /* SYS_TICK_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Fast_mode_ plus_communication/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Fast_mode_ plus_communication/gd32vf103_libopt.h new file mode 100644 index 0000000..7863c96 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Fast_mode_ plus_communication/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-09-18, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Fast_mode_ plus_communication/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Fast_mode_ plus_communication/main.c new file mode 100644 index 0000000..ce121df --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Fast_mode_ plus_communication/main.c @@ -0,0 +1,206 @@ +/*! + \file main.c + \brief master receiver and slave transmitter in fast mode plus + + \version 2019-09-18, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +#define I2C0_SLAVE_ADDRESS7 0x82 +#define I2C1_SLAVE_ADDRESS7 0x72 + +uint8_t i2c_transmitter[16]; +uint8_t i2c_receiver[16]; +__IO ErrStatus state = ERROR; + +void rcu_config(void); +void gpio_config(void); +void i2c_config(void); +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint16_t length); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + int i; + + /* initialize led */ + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + /* RCU config */ + rcu_config(); + /* GPIO config */ + gpio_config(); + /* I2C config */ + i2c_config(); + + for(i=0; i<16; i++){ + i2c_transmitter[i] = i + 0x80; + } + /* wait until I2C bus is idle */ + while(i2c_flag_get(I2C0, I2C_FLAG_I2CBSY)); + /* send a start condition to I2C bus */ + i2c_start_on_bus(I2C0); + /* wait until SBSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)); + /* send slave address to I2C bus */ + i2c_master_addressing(I2C0, I2C1_SLAVE_ADDRESS7, I2C_RECEIVER); + /* wait until ADDSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)); + /* clear ADDSEND bit */ + i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); + /* wait until ADDSEND bit is set */ + while(!i2c_flag_get(I2C1, I2C_FLAG_ADDSEND)); + /* clear ADDSEND bit */ + i2c_flag_clear(I2C1, I2C_FLAG_ADDSEND); + + for(i=0; i<15; i++){ + /* send a data byte */ + i2c_data_transmit(I2C1, i2c_transmitter[i]); + /* wait until the transmission data register is empty */ + while(!i2c_flag_get(I2C1, I2C_FLAG_TBE)); + /* wait until the RBNE bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_RBNE)); + /* read a data from I2C_DATA */ + i2c_receiver[i] = i2c_data_receive(I2C0); + } + /* send a NACK for the last data byte */ + i2c_ack_config(I2C0, I2C_ACK_DISABLE); + /* send a data byte */ + i2c_data_transmit(I2C1, i2c_transmitter[i]); + /* wait until the transmission data register is empty */ + while(!i2c_flag_get(I2C1, I2C_FLAG_TBE)); + /* the master doesn't acknowledge for the last byte */ + while(!i2c_flag_get(I2C1, I2C_FLAG_AERR)); + /* send a stop condition to I2C bus */ + i2c_stop_on_bus(I2C0); + /* wait until stop condition generate */ + while(I2C_CTL0(I2C0)&0x0200); + i2c_receiver[i] = i2c_data_receive(I2C0); + i2c_ack_config(I2C0, I2C_ACK_ENABLE); + /* clear the bit of AE */ + i2c_flag_clear(I2C1, I2C_FLAG_AERR); + + /* compare the transmit buffer and the receive buffer */ + state = memory_compare(i2c_transmitter, i2c_receiver, 16); + /* if success, LED2 and LED3 are on */ + if(SUCCESS == state){ + gd_eval_led_on(LED2); + gd_eval_led_on(LED3); + }else{ + /* if failed, LED2 and LED3 are off */ + gd_eval_led_off(LED2); + gd_eval_led_off(LED3); + } + while(1){ + } +} + +/*! + \brief memory compare function + \param[in] src : source data + \param[in] dst : destination data + \param[in] length : the compare data length + \param[out] none + \retval ErrStatus : ERROR or SUCCESS +*/ +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint16_t length) +{ + while(length--){ + if(*src++ != *dst++){ + return ERROR; + } + } + return SUCCESS; +} + +/*! + \brief enable the peripheral clock + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOB clock */ + rcu_periph_clock_enable(RCU_GPIOB); + /* enable I2C1 clock */ + rcu_periph_clock_enable(RCU_I2C1); + /* enable I2C0 clock */ + rcu_periph_clock_enable(RCU_I2C0); +} + +/*! + \brief cofigure the GPIO ports + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* connect PB6 to I2C0_SCL */ + /* connect PB7 to I2C0_SDA */ + /* connect PB10 to I2C1_SCL */ + /* connect PB11 to I2C1_SDA */ + gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_10 | GPIO_PIN_11); +} + +/*! + \brief cofigure the I2C0 and I2C1 interfaces + \param[in] none + \param[out] none + \retval none +*/ +void i2c_config(void) +{ + /* I2C clock configure */ + i2c_clock_config(I2C0, 1000000, I2C_DTCY_16_9); + /* I2C address configure */ + i2c_mode_addr_config(I2C0, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, I2C0_SLAVE_ADDRESS7); + /* enable I2C0 */ + i2c_enable(I2C0); + /* enable acknowledge */ + i2c_ack_config(I2C0, I2C_ACK_ENABLE); + i2c_clock_config(I2C1, 1000000, I2C_DTCY_16_9); + /* I2C address configure */ + i2c_mode_addr_config(I2C1, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, I2C1_SLAVE_ADDRESS7); + /* enable I2C1 */ + i2c_enable(I2C1); + /* enable acknowledge */ + i2c_ack_config(I2C1, I2C_ACK_ENABLE); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Fast_mode_ plus_communication/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Fast_mode_ plus_communication/readme.txt new file mode 100644 index 0000000..a53c266 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Fast_mode_ plus_communication/readme.txt @@ -0,0 +1,44 @@ +/*! + \file readme.txt + \brief description of the master receiver and slave transmitter in fast mode plus + + \version 2019-09-18, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows the I2C programming mode in +master receiving mode and slave transmitting mode. In this demo, I2C0 is operated as +master receiver, I2C1 is operated as slave and the SCL line and SDA line of I2C interface +are controled by the I/O pin PB10 and PB11(or PB6 and PB7) respectively. + + This demo shows the receiving data process of the master and the sending data process +of the slave. If transfer is sucessfully completed, LED2 and LED3 are on. + + We shoud use the jumper to connect the PB6 and PB10. The PB7 and PB11 are connected as well. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver/main.c new file mode 100644 index 0000000..e5f1519 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver/main.c @@ -0,0 +1,187 @@ +/*! + \file main.c + \brief master receiver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +#define I2C_10BIT_ADDRESS 0 + +#define I2C0_OWN_ADDRESS7 0x72 +#define I2C0_SLAVE_ADDRESS7 0x82 +#define I2C0_SLAVE_ADDRESS10 0x0322 + +uint8_t i2c_receiver[16]; + +void rcu_config(void); +void gpio_config(void); +void i2c_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + uint8_t i; + uint8_t slave10_first_byte,slave10_second_byte; + + /* configure USART */ + gd_eval_com_init(EVAL_COM0); + + printf("\r\n I2C Start\n"); + + /* RCU config */ + rcu_config(); + /* GPIO config */ + gpio_config(); + /* I2C config */ + i2c_config(); + + /* wait until I2C bus is idle */ + while(i2c_flag_get(I2C0, I2C_FLAG_I2CBSY)); + /* send a start condition to I2C bus */ + i2c_start_on_bus(I2C0); + /* wait until SBSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)); + +#if I2C_10BIT_ADDRESS + slave10_first_byte = (0xF0) | (uint8_t)((I2C0_SLAVE_ADDRESS10 & 0x0300)>>7); + /* send slave address first byte to I2C bus */ + i2c_master_addressing(I2C0, slave10_first_byte, I2C_TRANSMITTER); + /* wait until ADD10SEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_ADD10SEND)); + /* the second byte contains the remaining 8 bits of the 10-bit address */ + slave10_second_byte = (uint8_t)(I2C0_SLAVE_ADDRESS10 & 0x00FF); + /* send slave address 2nd byte to I2C bus */ + i2c_master_addressing(I2C0, slave10_second_byte, I2C_TRANSMITTER); + /* wait until ADDSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)); + /* clear ADDSEND bit */ + i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); + /* send a start condition to I2C bus */ + i2c_start_on_bus(I2C0); + /* wait until SBSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)); + /* send slave address first byte to I2C bus */ + i2c_master_addressing(I2C0, slave10_first_byte, I2C_RECEIVER); +#else + /* send slave address to I2C bus */ + i2c_master_addressing(I2C0, I2C0_SLAVE_ADDRESS7, I2C_RECEIVER); +#endif + /* wait until ADDSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)); + /* clear ADDSEND bit */ + i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); + + for(i=0; i<16; i++){ + if(13 == i){ + /* wait until the second last data byte is received into the shift register */ + while(!i2c_flag_get(I2C0, I2C_FLAG_BTC)); + /* disable acknowledge */ + i2c_ack_config(I2C0, I2C_ACK_DISABLE); + } + /* wait until the RBNE bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_RBNE)); + /* read a data from I2C_DATA */ + i2c_receiver[i] = i2c_data_receive(I2C0); + } + /* send a stop condition to I2C bus */ + i2c_stop_on_bus(I2C0); + /* wait until stop condition generate */ + while(I2C_CTL0(I2C0)&0x0200); + /* enable acknowledge */ + i2c_ack_config(I2C0, I2C_ACK_ENABLE); + + printf("\r\n I2C SUCCESS\n"); + + while(1){ + } +} + +/*! + \brief enable the peripheral clock + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOB clock */ + rcu_periph_clock_enable(RCU_GPIOB); + /* enable I2C0 clock */ + rcu_periph_clock_enable(RCU_I2C0); +} + +/*! + \brief cofigure the GPIO ports + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* connect PB6 to I2C0_SCL */ + /* connect PB7 to I2C0_SDA */ + gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7); +} + +/*! + \brief cofigure the I2C0 interfaces + \param[in] none + \param[out] none + \retval none +*/ +void i2c_config(void) +{ + /* I2C clock configure */ + i2c_clock_config(I2C0, 400000, I2C_DTCY_2); + /* I2C address configure */ + i2c_mode_addr_config(I2C0, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, I2C0_OWN_ADDRESS7); + /* enable I2C0 */ + i2c_enable(I2C0); + /* enable acknowledge */ + i2c_ack_config(I2C0, I2C_ACK_ENABLE); +} + +/* retarget the C library printf function to the usart */ +int fputc(int ch, FILE *f) +{ + usart_data_transmit(EVAL_COM0, (uint8_t)ch); + while (RESET == usart_flag_get(EVAL_COM0, USART_FLAG_TBE)); + return ch; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver/readme.txt new file mode 100644 index 0000000..7acc7c0 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver/readme.txt @@ -0,0 +1,50 @@ +/*! + \file readme.txt + \brief description of the master receiver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows the I2C programming +mode in master receiving mode. In this demo, I2C0 is operated as master receiver, +and the SCL line and SDA line of I2C0 interface are controled by the I/O pin +PB6 and PB7 respectively. + + This demo shows the receiving data process of the master. And it will store +the received data in the i2c_receiver array. + + This demo doesn't perform the data transfer actually, which is due to no +specific slave.In the specific application, we must send the correct slave +address, and the master and the slave may need to be connected by the jumper +if necessary. When the macro I2C_10BIT_ADDRESS is 1, I2C communicate in 10 bit +addressing mode, otherwise, I2C communicate in 7 bit addressing mode. + + JP16 must be fitted. \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_one_byte/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_one_byte/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_one_byte/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_one_byte/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_one_byte/main.c new file mode 100644 index 0000000..fd5464b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_one_byte/main.c @@ -0,0 +1,138 @@ +/*! + \file main.c + \brief master receiver one byte + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" + +#define I2C0_SLAVE_ADDRESS7 0x72 +#define I2C1_SLAVE_ADDRESS7 0x82 + +uint8_t i2c_receiver[16]; + +void rcu_config(void); +void gpio_config(void); +void i2c_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + int i; + + /* RCU config */ + rcu_config(); + /* GPIO config */ + gpio_config(); + /* I2C config */ + i2c_config(); + + i=0; + /* wait until I2C bus is idle */ + while(i2c_flag_get(I2C0, I2C_FLAG_I2CBSY)); + /* send a start condition to I2C bus */ + i2c_start_on_bus(I2C0); + /* wait until SBSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)); + /* send slave address to I2C bus */ + i2c_master_addressing(I2C0, I2C1_SLAVE_ADDRESS7, I2C_RECEIVER); + /* wait until ADDSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)); + + /* N=1,reset ACKEN bit before clearing ADDRSEND bit */ + i2c_ack_config(I2C0, I2C_ACK_DISABLE); + /* clear ADDSEND bit */ + i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); + /* N=1,send stop condition after clearing ADDRSEND bit */ + i2c_stop_on_bus(I2C0); + /* wait until the RBNE bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_RBNE)); + /* read a data from I2C_DATA */ + i2c_receiver[i++] = i2c_data_receive(I2C0); + + while(I2C_CTL0(I2C0)&0x0200); + /* Enable Acknowledge */ + i2c_ack_config(I2C0, I2C_ACK_ENABLE); + + while(1){ + } +} + +/*! + \brief enable the peripheral clock + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOB clock */ + rcu_periph_clock_enable(RCU_GPIOB); + /* enable I2C0 clock */ + rcu_periph_clock_enable(RCU_I2C0); +} + +/*! + \brief cofigure the GPIO ports + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* connect PB6 to I2C0_SCL */ + /* connect PB7 to I2C0_SDA */ + gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7); +} + +/*! + \brief cofigure the I2C0 interfaces + \param[in] none + \param[out] none + \retval none +*/ +void i2c_config(void) +{ + /* I2C clock configure */ + i2c_clock_config(I2C0, 100000, I2C_DTCY_2); + /* I2C address configure */ + i2c_mode_addr_config(I2C0, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, I2C0_SLAVE_ADDRESS7); + /* enable I2C0 */ + i2c_enable(I2C0); + /* enable acknowledge */ + i2c_ack_config(I2C0, I2C_ACK_ENABLE); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_one_byte/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_one_byte/readme.txt new file mode 100644 index 0000000..9a54052 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_one_byte/readme.txt @@ -0,0 +1,48 @@ +/*! + \file readme.txt + \brief description of the master receiver one byte + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows the I2C programming +mode in master receiving mode which the master only want to receive one byte of +data. In this demo,I2C0 is operated as master receiver,and the SCL line and SDA +line of I2C0 interface are controled by the I/O pin PB6 and PB7 respectively. + + This demo shows the receiving one byte process of the master. And it will store +the received data in the i2c_receiver array. + + This demo doesn't perform the data transfer actually, which is due to no +specific slave.In the specific application, we must send the correct slave +address, and the master and the slave may need to be connected by the jumper +if necessary. + JP16 must be fitted. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter/main.c new file mode 100644 index 0000000..29d3457 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter/main.c @@ -0,0 +1,207 @@ +/*! + \file main.c + \brief master receiver and slave transmitter + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +#define I2C0_SLAVE_ADDRESS7 0x82 +#define I2C1_SLAVE_ADDRESS7 0x72 + +uint8_t i2c_transmitter[16]; +uint8_t i2c_receiver[16]; +ErrStatus state = ERROR; + +void rcu_config(void); +void gpio_config(void); +void i2c_config(void); +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint16_t length); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + int i; + + /* initialize led */ + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + /* RCU config */ + rcu_config(); + /* GPIO config */ + gpio_config(); + /* I2C config */ + i2c_config(); + + for(i=0; i<16; i++){ + i2c_transmitter[i] = i + 0x80; + } + /* wait until I2C bus is idle */ + while(i2c_flag_get(I2C0, I2C_FLAG_I2CBSY)); + /* send a start condition to I2C bus */ + i2c_start_on_bus(I2C0); + /* wait until SBSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)); + /* send slave address to I2C bus */ + i2c_master_addressing(I2C0, I2C1_SLAVE_ADDRESS7, I2C_RECEIVER); + /* wait until ADDSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)); + /* clear ADDSEND bit */ + i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); + /* wait until ADDSEND bit is set */ + while(!i2c_flag_get(I2C1, I2C_FLAG_ADDSEND)); + /* clear ADDSEND bit */ + i2c_flag_clear(I2C1, I2C_FLAG_ADDSEND); + + for(i=0; i<15; i++){ + /* send a data byte */ + i2c_data_transmit(I2C1, i2c_transmitter[i]); + /* wait until the transmission data register is empty */ + while(!i2c_flag_get(I2C1, I2C_FLAG_TBE)); + /* wait until the RBNE bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_RBNE)); + /* read a data from I2C_DATA */ + i2c_receiver[i] = i2c_data_receive(I2C0); + } + /* send a NACK for the last data byte */ + i2c_ack_config(I2C0, I2C_ACK_DISABLE); + /* send a data byte */ + i2c_data_transmit(I2C1, i2c_transmitter[i]); + /* wait until the transmission data register is empty */ + while(!i2c_flag_get(I2C1, I2C_FLAG_TBE)); + /* the master doesn't acknowledge for the last byte */ + while(!i2c_flag_get(I2C1, I2C_FLAG_AERR)); + /* send a stop condition to I2C bus */ + i2c_stop_on_bus(I2C0); + /* wait until stop condition generate */ + while(I2C_CTL0(I2C0)&0x0200); + i2c_receiver[i] = i2c_data_receive(I2C0); + i2c_ack_config(I2C0, I2C_ACK_ENABLE); + /* clear the bit of AE */ + i2c_flag_clear(I2C1, I2C_FLAG_AERR); + + /* compare the transmit buffer and the receive buffer */ + state = memory_compare(i2c_transmitter, i2c_receiver, 16); + /* if success, LED2 and LED3 are on */ + if(SUCCESS == state){ + gd_eval_led_on(LED2); + gd_eval_led_on(LED3); + }else{ + /* if failed, LED2 and LED3 are off */ + gd_eval_led_off(LED2); + gd_eval_led_off(LED3); + } + while(1){ + } +} + +/*! + \brief memory compare function + \param[in] src : source data + \param[in] dst : destination data + \param[in] length : the compare data length + \param[out] none + \retval ErrStatus : ERROR or SUCCESS +*/ +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint16_t length) +{ + while(length--){ + if(*src++ != *dst++){ + return ERROR; + } + } + return SUCCESS; +} + +/*! + \brief enable the peripheral clock + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOB clock */ + rcu_periph_clock_enable(RCU_GPIOB); + /* enable I2C1 clock */ + rcu_periph_clock_enable(RCU_I2C1); + /* enable I2C0 clock */ + rcu_periph_clock_enable(RCU_I2C0); +} + +/*! + \brief cofigure the GPIO ports + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* I2C0 and I2C1 GPIO ports */ + /* connect PB6 to I2C0_SCL */ + /* connect PB7 to I2C0_SDA */ + /* connect PB10 to I2C1_SCL */ + /* connect PB11 to I2C1_SDA */ + gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_10 | GPIO_PIN_11); +} + +/*! + \brief cofigure the I2C0 and I2C1 interfaces + \param[in] none + \param[out] none + \retval none +*/ +void i2c_config(void) +{ + /* I2C clock configure */ + i2c_clock_config(I2C0, 100000, I2C_DTCY_2); + /* I2C address configure */ + i2c_mode_addr_config(I2C0, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, I2C0_SLAVE_ADDRESS7); + /* enable I2C0 */ + i2c_enable(I2C0); + /* enable acknowledge */ + i2c_ack_config(I2C0, I2C_ACK_ENABLE); + i2c_clock_config(I2C1, 100000, I2C_DTCY_2); + /* I2C address configure */ + i2c_mode_addr_config(I2C1, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, I2C1_SLAVE_ADDRESS7); + /* enable I2C1 */ + i2c_enable(I2C1); + /* enable acknowledge */ + i2c_ack_config(I2C1, I2C_ACK_ENABLE); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter/readme.txt new file mode 100644 index 0000000..cf84f61 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter/readme.txt @@ -0,0 +1,47 @@ +/*! + \file readme.txt + \brief description of the master receiver and slave transmitter + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows the I2C programming mode in +master receiving mode and slave transmitting mode. In this demo, I2C0 is operated as +master receiver, I2C1 is operated as slave and the SCL line and SDA line of I2C interface +are controled by the I/O pin PB10 and PB11(or PB6 and PB7) respectively. + + This demo shows the receiving data process of the master and the sending data process +of the slave. If transfer is sucessfully completed, LED2 and LED3 are on. + + We shoud use the jumper to connect the PB6 and PB10. The PB7 and PB11 are connected as well. + + JP16 must be fitted. + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/I2C0_IE.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/I2C0_IE.c new file mode 100644 index 0000000..9b1a6aa --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/I2C0_IE.c @@ -0,0 +1,134 @@ +/*! + \file I2C0_IE.c + \brief I2C0_MasterReceiver interrupt program + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_i2c.h" +#include "I2C_IE.h" + +uint32_t event1; + +/*! + \brief handle I2C0 event interrupt request + \param[in] none + \param[out] none + \retval none +*/ +void I2C0_EventIRQ_Handler(void) +{ + if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_SBSEND)){ + /* the master sends slave address */ + i2c_master_addressing(I2C0, I2C1_SLAVE_ADDRESS7, I2C_RECEIVER); + }else if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_ADDSEND)){ + if((1 == I2C_nBytes)||(2 == I2C_nBytes)){ + /* clear the ACKEN before the ADDSEND is cleared */ + i2c_ack_config(I2C0, I2C_ACK_DISABLE); + /* clear the ADDSEND bit */ + i2c_interrupt_flag_clear(I2C0,I2C_INT_FLAG_ADDSEND); + }else{ + /* clear the ADDSEND bit */ + i2c_interrupt_flag_clear(I2C0,I2C_INT_FLAG_ADDSEND); + } + } + else if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_RBNE)){ + if(I2C_nBytes>0){ + if(3 == I2C_nBytes){ + /* wait until the second last data byte is received into the shift register */ + while(!i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_BTC)); + /* send a NACK for the last data byte */ + i2c_ack_config(I2C0, I2C_ACK_DISABLE); + } + /* read a data byte from I2C_DATA*/ + *i2c_rxbuffer++ = i2c_data_receive(I2C0); + I2C_nBytes--; + if(0 == I2C_nBytes){ + i2c_stop_on_bus(I2C0); + status=SUCCESS; + i2c_ack_config(I2C0, I2C_ACK_ENABLE); + i2c_ackpos_config(I2C0, I2C_ACKPOS_CURRENT); + i2c_interrupt_disable(I2C0, I2C_INT_ERR); + i2c_interrupt_disable(I2C0, I2C_INT_BUF); + i2c_interrupt_disable(I2C0, I2C_INT_EV); + } + } + } +} + +/*! + \brief handle I2C0 error interrupt request + \param[in] none + \param[out] none + \retval none +*/ +void I2C0_ErrorIRQ_Handler(void) +{ + /* no acknowledge received */ + if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_AERR)){ + i2c_interrupt_flag_clear(I2C0, I2C_INT_FLAG_AERR); + } + + /* SMBus alert */ + if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_SMBALT)){ + i2c_interrupt_flag_clear(I2C0, I2C_INT_FLAG_SMBALT); + } + + /* bus timeout in SMBus mode */ + if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_SMBTO)){ + i2c_interrupt_flag_clear(I2C0, I2C_INT_FLAG_SMBTO); + } + + /* over-run or under-run when SCL stretch is disabled */ + if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_OUERR)){ + i2c_interrupt_flag_clear(I2C0, I2C_INT_FLAG_OUERR); + } + + /* arbitration lost */ + if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_LOSTARB)){ + i2c_interrupt_flag_clear(I2C0, I2C_INT_FLAG_LOSTARB); + } + + /* bus error */ + if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_BERR)){ + i2c_interrupt_flag_clear(I2C0, I2C_INT_FLAG_BERR); + } + + /* CRC value doesn't match */ + if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_PECERR)){ + i2c_interrupt_flag_clear(I2C0, I2C_INT_FLAG_PECERR); + } + + /* disable the error interrupt */ + i2c_interrupt_disable(I2C0, I2C_INT_ERR); + i2c_interrupt_disable(I2C0, I2C_INT_BUF); + i2c_interrupt_disable(I2C0, I2C_INT_EV); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/I2C1_IE.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/I2C1_IE.c new file mode 100644 index 0000000..6af60f9 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/I2C1_IE.c @@ -0,0 +1,105 @@ +/*! + \file I2C1_IE.c + \brief I2C1_SlaveTransmitter interrupt program + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_i2c.h" +#include "I2C_IE.h" + +uint32_t event2; + +/*! + \brief handle I2C1 event interrupt request + \param[in] none + \param[out] none + \retval none +*/ +void I2C1_EventIRQ_Handler(void) +{ + if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_ADDSEND)){ + /* clear the ADDSEND bit */ + i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_ADDSEND); + }else if((i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_TBE))&&(!i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_AERR))){ + /* send a data byte */ + i2c_data_transmit(I2C1, *i2c_txbuffer++); + } +} + +/*! + \brief handle I2C1 error interrupt request + \param[in] none + \param[out] none + \retval none +*/ +void I2C1_ErrorIRQ_Handler(void) +{ + /* no acknowledge received */ + if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_AERR)){ + i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_AERR); + } + + /* SMBus alert */ + if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_SMBALT)){ + i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_SMBALT); + } + + /* bus timeout in SMBus mode */ + if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_SMBTO)){ + i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_SMBTO); + } + + /* over-run or under-run when SCL stretch is disabled */ + if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_OUERR)){ + i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_OUERR); + } + + /* arbitration lost */ + if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_LOSTARB)){ + i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_LOSTARB); + } + + /* bus error */ + if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_BERR)){ + i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_BERR); + } + + /* CRC value doesn't match */ + if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_PECERR)){ + i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_PECERR); + } + + /* disable the error interrupt */ + i2c_interrupt_disable(I2C1,I2C_INT_ERR); + i2c_interrupt_disable(I2C1,I2C_INT_BUF); + i2c_interrupt_disable(I2C1,I2C_INT_EV); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/I2C_IE.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/I2C_IE.h new file mode 100644 index 0000000..fb19e1f --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/I2C_IE.h @@ -0,0 +1,59 @@ +/*! + \file I2C_IE.h + \brief The header file of I2C0 and I2C1 interrupt + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef I2C_IE_H +#define I2C_IE_H + +#include "gd32vf103.h" + +#define I2C0_SLAVE_ADDRESS7 0x82 +#define I2C1_SLAVE_ADDRESS7 0x72 + +extern volatile ErrStatus status; +extern volatile uint8_t* i2c_txbuffer; +extern volatile uint8_t* i2c_rxbuffer; +extern volatile uint16_t I2C_nBytes; + +/* function declarations */ +/* handle I2C0 event interrupt request */ +void I2C0_EventIRQ_Handler(void); +/* handle I2C0 error interrupt request */ +void I2C0_ErrorIRQ_Handler(void); +/* handle I2C1 event interrupt request */ +void I2C1_EventIRQ_Handler(void); +/* handle I2C1 error interrupt request */ +void I2C1_ErrorIRQ_Handler(void); + +#endif /* I2C_IE_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/gd32vf103_it.c new file mode 100644 index 0000000..5415d0c --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/gd32vf103_it.c @@ -0,0 +1,81 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_it.h" +#include "I2C_IE.h" + +/*! + \brief this function handles I2C0 event interrupt request exception + \param[in] none + \param[out] none + \retval none +*/ +void I2C0_EV_IRQHandler(void) +{ + I2C0_EventIRQ_Handler(); +} + +/*! + \brief this function handles I2C0 error interrupt request exception + \param[in] none + \param[out] none + \retval none +*/ +void I2C0_ER_IRQHandler(void) +{ + I2C0_ErrorIRQ_Handler(); +} + +/*! + \brief this function handles I2C1 event interrupt request exception + \param[in] none + \param[out] none + \retval none +*/ +void I2C1_EV_IRQHandler(void) +{ + I2C1_EventIRQ_Handler(); +} + +/*! + \brief this function handles I2C1 error interrupt request exception + \param[in] none + \param[out] none + \retval none +*/ +void I2C1_ER_IRQHandler(void) +{ + I2C1_ErrorIRQ_Handler(); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/gd32vf103_it.h new file mode 100644 index 0000000..743acbd --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/gd32vf103_it.h @@ -0,0 +1,51 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ +/* I2C0 event handle function */ +void I2C0_EV_IRQHandler(void); +/* I2C0 error handle function */ +void I2C0_ER_IRQHandler(void); +/* I2C1 event handle function */ +void I2C1_EV_IRQHandler(void); +/* I2C1 error handle function */ +void I2C1_ER_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/main.c new file mode 100644 index 0000000..adec5c0 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/main.c @@ -0,0 +1,205 @@ +/*! + \file main.c + \brief master receiver and slave transmitter interrupt + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" +#include "I2C_IE.h" + +uint8_t i2c_buffer_transmitter[16]; +uint8_t i2c_buffer_receiver[16]; + +volatile uint8_t* i2c_txbuffer; +volatile uint8_t* i2c_rxbuffer; +volatile uint16_t I2C_nBytes; +volatile ErrStatus status; +ErrStatus state = ERROR; + +void rcu_config(void); +void gpio_config(void); +void i2c_config(void); +void i2c_clic_config(void); +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint16_t length); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + int i; + + /* initialize LED2, LED3, as the transfer instruction */ + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + rcu_config(); + gpio_config(); + i2c_config(); + i2c_clic_config(); + + for(i=0; i<16; i++){ + i2c_buffer_transmitter[i] = i + 0x80; + } + /* initialize i2c_txbuffer, i2c_rxbuffer, I2C_nBytes and status */ + i2c_txbuffer = i2c_buffer_transmitter; + i2c_rxbuffer = i2c_buffer_receiver; + I2C_nBytes = 16; + status = ERROR; + + /* enable the I2C0 interrupt */ + i2c_interrupt_enable(I2C0, I2C_INT_ERR); + i2c_interrupt_enable(I2C0, I2C_INT_EV); + i2c_interrupt_enable(I2C0, I2C_INT_BUF); + /* enable the I2C1 interrupt */ + i2c_interrupt_enable(I2C1, I2C_INT_ERR); + i2c_interrupt_enable(I2C1, I2C_INT_EV); + i2c_interrupt_enable(I2C1, I2C_INT_BUF); + if(2 == I2C_nBytes){ + /* send ACK for the next byte */ + i2c_ackpos_config(I2C0, I2C_ACKPOS_NEXT); + } + /* the master waits until the I2C bus is idle */ + while(i2c_flag_get(I2C0, I2C_FLAG_I2CBSY)); + /* the master sends a start condition to I2C bus */ + i2c_start_on_bus(I2C0); + + while(I2C_nBytes>0); + while(SUCCESS != status); + /* if the transfer is successfully completed, LED2 and LED3 is on */ + state = memory_compare(i2c_buffer_transmitter, i2c_buffer_receiver, 16); + if(SUCCESS == state){ + /* if success, LED2 and LED3 are on */ + gd_eval_led_on(LED2); + gd_eval_led_on(LED3); + }else{ + /* if failed, LED2 and LED3 are off */ + gd_eval_led_off(LED2); + gd_eval_led_off(LED3); + } + while(1){ + } +} + +/*! + \brief memory compare function + \param[in] src : source data + \param[in] dst : destination data + \param[in] length : the compare data length + \param[out] none + \retval ErrStatus : ERROR or SUCCESS +*/ +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint16_t length) +{ + while(length--){ + if(*src++ != *dst++){ + return ERROR; + } + } + return SUCCESS; +} + +/*! + \brief enable the peripheral clock + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOB clock */ + rcu_periph_clock_enable(RCU_GPIOB); + /* enable I2C1 clock */ + rcu_periph_clock_enable(RCU_I2C1); + /* enable I2C0 clock */ + rcu_periph_clock_enable(RCU_I2C0); +} + +/*! + \brief cofigure the GPIO ports + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* I2C0 and I2C1 GPIO ports */ + /* connect PB6 to I2C0_SCL */ + /* connect PB7 to I2C0_SDA */ + /* connect PB10 to I2C1_SCL */ + /* connect PB11 to I2C1_SDA */ + gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_10 | GPIO_PIN_11); +} + +/*! + \brief cofigure the I2C0 and I2C1 interfaces + \param[in] none + \param[out] none + \retval none +*/ +void i2c_config(void) +{ + /* I2C clock configure */ + i2c_clock_config(I2C0, 100000, I2C_DTCY_2); + /* I2C address configure */ + i2c_mode_addr_config(I2C0, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, I2C0_SLAVE_ADDRESS7); + /* enable I2C0 */ + i2c_enable(I2C0); + /* enable acknowledge */ + i2c_ack_config(I2C0, I2C_ACK_ENABLE); + i2c_clock_config(I2C1, 100000, I2C_DTCY_2); + /* I2C address configure */ + i2c_mode_addr_config(I2C1, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, I2C1_SLAVE_ADDRESS7); + /* enable I2C1 */ + i2c_enable(I2C1); + /* enable acknowledge */ + i2c_ack_config(I2C1, I2C_ACK_ENABLE); +} + +/*! + \brief cofigure the NVIC peripheral + \param[in] none + \param[out] none + \retval none +*/ +void i2c_clic_config(void) +{ + eclic_global_interrupt_enable(); + eclic_irq_enable(I2C0_EV_IRQn,1,0); + eclic_irq_enable(I2C1_EV_IRQn,2,0); + eclic_irq_enable(I2C0_ER_IRQn,3,0); + eclic_irq_enable(I2C1_ER_IRQn,4,0); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/readme.txt new file mode 100644 index 0000000..a9e0656 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_slave_transmitter_interrupt/readme.txt @@ -0,0 +1,49 @@ +/*! + \file readme.txt + \brief description of the master receiver and slave transmitter interrupt + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to use the I2C +interrupt programming mode in master receiving mode or slave transmitting mode. +In this demo, I2C0 is operated as the master receiver and I2C1 as the slave +transmitter. Moreover,the SCL line and SDA line of I2C0 interface are controled +by the I/O pin PB6 and PB7 respectively. The SCL and SDA of I2C1 are controled +by the pin PB10 and PB11 respectively. + + This demo will send the data of i2c_buffer_transmitter array through I2C1 interface +to the I2C0, and it will store the data received by I2C0 in the i2c_buffer_receiver +array. If transfer is sucessfully completed, LED2 and LED3 are on. + + We shoud use the jumper to connect the PB6 and PB10. The PB7 and PB11 are +connected as well. + JP16 must be fitted. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_two_bytes/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_two_bytes/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_two_bytes/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_two_bytes/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_two_bytes/main.c new file mode 100644 index 0000000..61c7719 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_two_bytes/main.c @@ -0,0 +1,147 @@ +/*! + \file main.c + \brief master receiver two bytes + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" + +#define I2C0_OWN_ADDRESS7 0x72 +#define I2C0_SLAVE_ADDRESS7 0x82 + +uint8_t i2c_receiver[16]; + +void rcu_config(void); +void gpio_config(void); +void i2c_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + int i; + + /* RCU config */ + rcu_config(); + /* GPIO config */ + gpio_config(); + /* I2C config */ + i2c_config(); + + i=0; + /* send a NACK for the next data byte which will be received into the shift register */ + i2c_ackpos_config(I2C0, I2C_ACKPOS_NEXT); + /* wait until I2C bus is idle */ + while(i2c_flag_get(I2C0, I2C_FLAG_I2CBSY)); + /* send a start condition to I2C bus */ + i2c_start_on_bus(I2C0); + /* wait until SBSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)); + /* send slave address to I2C bus */ + i2c_master_addressing(I2C0, I2C0_SLAVE_ADDRESS7, I2C_RECEIVER); + /* disable ACK before clearing ADDSEND bit */ + i2c_ack_config(I2C0, I2C_ACK_DISABLE); + /* wait until ADDSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)); + /* clear ADDSEND bit */ + i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); + /* Wait until the last data byte is received into the shift register */ + while(!i2c_flag_get(I2C0, I2C_FLAG_BTC)); + /* wait until the RBNE bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_RBNE)); + + /* read a data from I2C_DATA */ + i2c_receiver[i++] = i2c_data_receive(I2C0); + /* wait until the RBNE bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_RBNE)); + /* read a data from I2C_DATA */ + i2c_receiver[i++] = i2c_data_receive(I2C0); + /* send a stop condition */ + i2c_stop_on_bus(I2C0); + /* wait until stop condition generate */ + while(I2C_CTL0(I2C0)&0x0200); + i2c_ackpos_config(I2C0, I2C_ACKPOS_CURRENT); + /* enable acknowledge */ + i2c_ack_config(I2C0, I2C_ACK_ENABLE); + + while(1){ + } +} + +/*! + \brief enable the peripheral clock + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOB clock */ + rcu_periph_clock_enable(RCU_GPIOB); + /* enable I2C0 clock */ + rcu_periph_clock_enable(RCU_I2C0); +} + +/*! + \brief cofigure the GPIO ports + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* connect PB6 to I2C0_SCL */ + /* connect PB7 to I2C0_SDA */ + gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7); +} + +/*! + \brief cofigure the I2C0 interfaces + \param[in] none + \param[out] none + \retval none +*/ +void i2c_config(void) +{ + /* I2C clock configure */ + i2c_clock_config(I2C0, 100000, I2C_DTCY_2); + /* I2C address configure */ + i2c_mode_addr_config(I2C0, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, I2C0_OWN_ADDRESS7); + /* enable I2C0 */ + i2c_enable(I2C0); + /* enable acknowledge */ + i2c_ack_config(I2C0, I2C_ACK_ENABLE); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_two_bytes/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_two_bytes/readme.txt new file mode 100644 index 0000000..d2bb491 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_receiver_two_bytes/readme.txt @@ -0,0 +1,49 @@ +/*! + \file readme.txt + \brief description of the master receiver two bytes + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows the I2C programming +mode in master receiving mode which the master only want to receive two bytes of +data. In this demo,I2C0 is operated as master receiver,and the SCL line and SDA +line of I2C0 interface are controled by the I/O pin PB6 and PB7 respectively. + + This demo shows the receiving two bytes process of the master. And it will store +the received data in the i2c_receiver array. + + This demo doesn't perform the data transfer actually, which is due to no +specific slave.In the specific application, we must send the correct slave +address, and the master and the slave may need to be connected by the jumper +if necessary. + + JP16 must be fitted. \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter/main.c new file mode 100644 index 0000000..dcde8c0 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter/main.c @@ -0,0 +1,143 @@ +/*! + \file main.c + \brief master transmitter + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" + +#define I2C0_OWN_ADDRESS7 0x72 +#define I2C0_SLAVE_ADDRESS7 0x82 + +uint8_t i2c_transmitter[16]; + +void rcu_config(void); +void gpio_config(void); +void i2c_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + int i; + + /* RCU config */ + rcu_config(); + /* GPIO config */ + gpio_config(); + /* I2C config */ + i2c_config(); + + for(i=0; i<16; i++){ + i2c_transmitter[i]=i+0x80; + } + + /* wait until I2C bus is idle */ + while(i2c_flag_get(I2C0, I2C_FLAG_I2CBSY)); + /* send a start condition to I2C bus */ + i2c_start_on_bus(I2C0); + /* wait until SBSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)); + /* send slave address to I2C bus */ + i2c_master_addressing(I2C0, I2C0_SLAVE_ADDRESS7, I2C_TRANSMITTER); + /* wait until ADDSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)); + /* clear ADDSEND bit */ + i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); + /* wait until the transmit data buffer is empty */ + while(!i2c_flag_get(I2C0, I2C_FLAG_TBE)); + + for(i=0; i<16; i++){ + /* data transmission */ + i2c_data_transmit(I2C0, i2c_transmitter[i]); + /* wait until the TBE bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_TBE)); + } + /* send a stop condition to I2C bus */ + i2c_stop_on_bus(I2C0); + /* wait until stop condition generate */ + while(I2C_CTL0(I2C0)&0x0200); + + /* infinite loop */ + while(1){ + } +} + +/*! + \brief enable the peripheral clock + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOB clock */ + rcu_periph_clock_enable(RCU_GPIOB); + /* enable I2C0 clock */ + rcu_periph_clock_enable(RCU_I2C0); +} + +/*! + \brief cofigure the GPIO ports + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* I2C0 and I2C1 GPIO ports */ + /* connect PB6 to I2C0_SCL */ + /* connect PB7 to I2C0_SDA */ + gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7); +} + +/*! + \brief cofigure the I2C0 interfaces + \param[in] none + \param[out] none + \retval none +*/ +void i2c_config(void) +{ + /* I2C clock configure */ + i2c_clock_config(I2C0, 100000, I2C_DTCY_2); + /* I2C address configure */ + i2c_mode_addr_config(I2C0, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, I2C0_SLAVE_ADDRESS7); + /* enable I2C0 */ + i2c_enable(I2C0); + /* enable acknowledge */ + i2c_ack_config(I2C0, I2C_ACK_ENABLE); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter/readme.txt new file mode 100644 index 0000000..7eb9baf --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter/readme.txt @@ -0,0 +1,48 @@ +/*! + \file readme.txt + \brief description of the master transmitter + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows the I2C programming +mode in master transmitting mode.In this demo,I2C0 is operated as the master +transmitter, and the SCL line and SDA line of I2C0 interface are controled by +the I/O pin PB6 and PB7 respectively. + + This demo shows the sending process of the master. And it will send the data +in the i2c_transmitter array through I2C0. + + The demo doesn't perform the data transfer actually, which is due to no specific +slave. In the specific application, we must send the correct slave address, and the +master and the slave may need to be connected by the jumper if necessary. + + JP16 must be fitted. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver/main.c new file mode 100644 index 0000000..f6cf71f --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver/main.c @@ -0,0 +1,191 @@ +/*! + \file main.c + \brief master transmitter slave receiver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +#define I2C0_SLAVE_ADDRESS7 0x82 +#define I2C1_SLAVE_ADDRESS7 0x72 + +uint8_t i2c_transmitter[16]; +uint8_t i2c_receiver[16]; +ErrStatus state = ERROR; + +void rcu_config(void); +void gpio_config(void); +void i2c_config(void); +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint16_t length); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + int i; + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + rcu_config(); + gpio_config(); + i2c_config(); + + for(i=0;i<16;i++){ + i2c_transmitter[i]=i+0x80; + } + + /* wait until I2C bus is idle */ + while(i2c_flag_get(I2C0, I2C_FLAG_I2CBSY)); + + /* send a start condition to I2C bus */ + i2c_start_on_bus(I2C0); + + /* wait until SBSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)); + + /* send slave address to I2C bus*/ + i2c_master_addressing(I2C0, I2C1_SLAVE_ADDRESS7, I2C_TRANSMITTER); + + /* wait until ADDSEND bit is set*/ + while(!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)); + while(!i2c_flag_get(I2C1, I2C_FLAG_ADDSEND)); + /* clear ADDSEND bit */ + i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); + i2c_flag_clear(I2C1, I2C_FLAG_ADDSEND); + for(i=0;i<16;i++){ + /* send a data byte */ + i2c_data_transmit(I2C0,i2c_transmitter[i]); + /* wait until the transmission data register is empty*/ + while(!i2c_flag_get(I2C0, I2C_FLAG_TBE)); + /* wait until the RBNE bit is set */ + while(!i2c_flag_get(I2C1, I2C_FLAG_RBNE)); + /* read a data from I2C_DATA */ + i2c_receiver[i] = i2c_data_receive(I2C1); + } + /* send a stop condition to I2C bus*/ + i2c_stop_on_bus(I2C0); + /* wait until stop condition generate */ + while(I2C_CTL0(I2C0)&0x0200); + while(!i2c_flag_get(I2C1, I2C_FLAG_STPDET)); + /* clear the STPDET bit */ + i2c_enable(I2C1); + state = memory_compare(i2c_transmitter, i2c_receiver,16); + if(SUCCESS == state){ + gd_eval_led_on(LED2); + gd_eval_led_on(LED3); + }else{ + gd_eval_led_off(LED2); + gd_eval_led_off(LED3); + } + while(1); +} + +/*! + \brief memory compare function + \param[in] src : source data + \param[in] dst : destination data + \param[in] length : the compare data length + \param[out] none + \retval ErrStatus : ERROR or SUCCESS +*/ +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint16_t length) +{ + while(length--){ + if(*src++ != *dst++){ + return ERROR; + } + } + return SUCCESS; +} + +/*! + \brief enable the peripheral clock + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOB clock */ + rcu_periph_clock_enable(RCU_GPIOB); + /* enable I2C1 clock */ + rcu_periph_clock_enable(RCU_I2C1); + /* enable I2C0 clock */ + rcu_periph_clock_enable(RCU_I2C0); +} + +/*! + \brief cofigure the GPIO ports. + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* I2C0 and I2C1 GPIO ports */ + /* connect PB6 to I2C0_SCL */ + /* connect PB7 to I2C0_SDA */ + /* connect PB10 to I2C1_SCL */ + /* connect PB11 to I2C1_SDA */ + gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_10 | GPIO_PIN_11); +} + +/*! + \brief cofigure the I2C0 and I2C1 interfaces + \param[in] none + \param[out] none + \retval none +*/ +void i2c_config(void) +{ + /* configure I2C0 clock */ + i2c_clock_config(I2C0, 100000, I2C_DTCY_2); + /* configure I2C0 address */ + i2c_mode_addr_config(I2C0, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, I2C0_SLAVE_ADDRESS7); + /* enable I2C0 */ + i2c_enable(I2C0); + /* enable acknowledge */ + i2c_ack_config(I2C0, I2C_ACK_ENABLE); + /* configure I2C1 clock */ + i2c_clock_config(I2C1, 100000, I2C_DTCY_2); + /* configure I2C1 address */ + i2c_mode_addr_config(I2C1, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, I2C1_SLAVE_ADDRESS7); + /* enable I2C1 */ + i2c_enable(I2C1); + /* enable acknowledge */ + i2c_ack_config(I2C1, I2C_ACK_ENABLE); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver/readme.txt new file mode 100644 index 0000000..d0071ec --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver/readme.txt @@ -0,0 +1,48 @@ +/*! + \file readme.txt + \brief description of the master transmitter and slave receiver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows the I2C programming mode in master +transmitter mode and slave receiving mode. In this demo,I2C0 is operated as master transmitter +,I2C1 is operated as slave receiver and the SCL line and SDA line of I2C interface are controled +by the I/O pin PB10 and PB11(or PB6 and PB7) respectively. + + This demo shows the sending data process of the master and the receiving data process of the slave. +If transfer is sucessfully completed, LED2 and LED3 is light. + + We shoud use the jumper to connect the PB6 and PB10. The PB7 and PB11 are connected as well. + + JP16 must be fitted. + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_dma/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_dma/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_dma/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_dma/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_dma/main.c new file mode 100644 index 0000000..9598892 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_dma/main.c @@ -0,0 +1,221 @@ +/*! + \file main.c + \brief master transmitter slave receiver through DMA + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +#define I2C0_SLAVE_ADDRESS7 0x82 +#define I2C1_SLAVE_ADDRESS7 0x72 +#define ARRAYNUM(arr_nanme) (uint32_t)(sizeof(arr_nanme) / sizeof(*(arr_nanme))) +#define I2C0_DATA_ADDRESS 0x40005410 +#define I2C1_DATA_ADDRESS 0x40005810 +#define BUFFER_SIZE (ARRAYNUM(i2c0_buff_tx)-1) + +uint8_t i2c0_buff_tx[] = "I2C DMA test"; +uint8_t i2c1_buff_rx[BUFFER_SIZE]; +__IO ErrStatus state = ERROR; + +void rcu_config(void); +void gpio_config(void); +void i2c_config(void); +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint16_t length); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + dma_parameter_struct dma_init_struct; + + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + rcu_config(); + gpio_config(); + i2c_config(); + + /* initialize DMA channel4 */ + dma_deinit(DMA0, DMA_CH4); + dma_struct_para_init(&dma_init_struct); + + dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY; + dma_init_struct.memory_addr = (uint32_t)i2c1_buff_rx; + dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; + dma_init_struct.number = BUFFER_SIZE; + dma_init_struct.periph_addr = I2C1_DATA_ADDRESS; + dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; + dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH; + dma_init(DMA0, DMA_CH4, &dma_init_struct); + + /* initialize DMA channel5 */ + dma_deinit(DMA0, DMA_CH5); + dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; + dma_init_struct.memory_addr = (uint32_t)i2c0_buff_tx; + dma_init_struct.periph_addr = I2C0_DATA_ADDRESS; + dma_init_struct.priority = DMA_PRIORITY_HIGH; + dma_init(DMA0, DMA_CH5, &dma_init_struct); + + /* wait until I2C bus is idle */ + while(i2c_flag_get(I2C0, I2C_FLAG_I2CBSY)); + + /* send a start condition to I2C bus */ + i2c_start_on_bus(I2C0); + + /* wait until SBSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)); + + /* send slave address to I2C bus*/ + i2c_master_addressing(I2C0, I2C1_SLAVE_ADDRESS7, I2C_TRANSMITTER); + + /* wait until ADDSEND bit is set*/ + while(!i2c_flag_get(I2C1, I2C_FLAG_ADDSEND)); + while(!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)); + /* clear ADDSEND bit */ + i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); + i2c_flag_clear(I2C1, I2C_FLAG_ADDSEND); + + /* enable I2C1 DMA */ + i2c_dma_enable(I2C1, I2C_DMA_ON); + /* enable I2C0 DMA */ + i2c_dma_enable(I2C0, I2C_DMA_ON); + /* enable DMA0 channel4 */ + dma_channel_enable(DMA0, DMA_CH4); + /* enable DMA0 channel5 */ + dma_channel_enable(DMA0, DMA_CH5); + + /* DMA0 channel4 full transfer finish flag */ + while(!dma_flag_get(DMA0, DMA_CH4, DMA_FLAG_FTF)); + /* DMA0 channel5 full transfer finish flag */ + while(!dma_flag_get(DMA0, DMA_CH5, DMA_FLAG_FTF)); + + /* send a stop condition to I2C bus*/ + i2c_stop_on_bus(I2C0); + /* wait until stop condition generate */ + while(I2C_CTL0(I2C0)&0x0200); + while(!i2c_flag_get(I2C1, I2C_FLAG_STPDET)); + /* clear the STPDET bit */ + i2c_enable(I2C1); + state = memory_compare(i2c0_buff_tx, i2c1_buff_rx, BUFFER_SIZE); + if(SUCCESS == state){ + gd_eval_led_on(LED2); + gd_eval_led_on(LED3); + }else{ + gd_eval_led_off(LED2); + gd_eval_led_off(LED3); + } + while(1); +} + +/*! + \brief memory compare function + \param[in] src : source data + \param[in] dst : destination data + \param[in] length : the compare data length + \param[out] none + \retval ErrStatus : ERROR or SUCCESS +*/ +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint16_t length) +{ + while(length--){ + if(*src++ != *dst++){ + return ERROR; + } + } + return SUCCESS; +} + +/*! + \brief enable the peripheral clock + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOB clock */ + rcu_periph_clock_enable(RCU_GPIOB); + /* enable I2C1 clock */ + rcu_periph_clock_enable(RCU_I2C1); + /* enable I2C0 clock */ + rcu_periph_clock_enable(RCU_I2C0); + /* enable DMA0 clock */ + rcu_periph_clock_enable(RCU_DMA0); +} + +/*! + \brief cofigure the GPIO ports. + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* connect PB6 to I2C0_SCL */ + /* connect PB7 to I2C0_SDA */ + /* connect PB10 to I2C1_SCL */ + /* connect PB11 to I2C1_SDA */ + gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_10 | GPIO_PIN_11); +} + +/*! + \brief cofigure the I2C0 and I2C1 interfaces + \param[in] none + \param[out] none + \retval none +*/ +void i2c_config(void) +{ + /* configure I2C0 clock */ + i2c_clock_config(I2C0, 100000, I2C_DTCY_2); + /* configure I2C0 address */ + i2c_mode_addr_config(I2C0, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, I2C0_SLAVE_ADDRESS7); + /* enable I2C0 */ + i2c_enable(I2C0); + /* enable acknowledge */ + i2c_ack_config(I2C0, I2C_ACK_ENABLE); + /* configure I2C1 clock */ + i2c_clock_config(I2C1, 100000, I2C_DTCY_2); + /* configure I2C1 address */ + i2c_mode_addr_config(I2C1, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, I2C1_SLAVE_ADDRESS7); + /* enable I2C1 */ + i2c_enable(I2C1); + /* enable acknowledge */ + i2c_ack_config(I2C1, I2C_ACK_ENABLE); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_dma/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_dma/readme.txt new file mode 100644 index 0000000..e96b771 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_dma/readme.txt @@ -0,0 +1,47 @@ +/*! + \file main.c + \brief master transmitter slave receiver through DMA + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to use DMA channel5 to transimit data +from RAM memory to I2C0 data register and how to use DMA channel4 to receive data from I2C1 data register. + + In this demo, I2C0 is operated as master transmitter ,I2C1 is operated as slave receiver and the SCL +line and SDA line of I2C interface are controled by the I/O pin PB10 and PB11(or PB6 and PB7) respectively. +If transfer is sucessfully completed, LED2 and LED3 is light. + + We shoud use the jumper to connect the PB6 and PB10. The PB7 and PB11 are connected as well. + + JP16 must be fitted. + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/I2C0_IE.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/I2C0_IE.c new file mode 100644 index 0000000..2aacaf3 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/I2C0_IE.c @@ -0,0 +1,119 @@ +/*! + \file I2C0_IE.c + \brief I2C0 master transmitter interrupt program + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_i2c.h" + +#include "../Master_transmitter_slave_receiver_interrupt/I2C_IE.h" + +uint32_t event1; + +/*! + \brief handle I2C0 event interrupt request + \param[in] none + \param[out] none + \retval none +*/ +void I2C0_EventIRQ_Handler(void) +{ + if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_SBSEND)){ + /* send slave address */ + i2c_master_addressing(I2C0, I2C1_SLAVE_ADDRESS7, I2C_TRANSMITTER); + }else if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_ADDSEND)){ + /*clear ADDSEND bit */ + i2c_interrupt_flag_clear(I2C0, I2C_INT_FLAG_ADDSEND); + }else if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_TBE)){ + if(I2C_nBytes>0){ + /* the master sends a data byte */ + i2c_data_transmit(I2C0, *i2c_txbuffer++); + I2C_nBytes--; + }else{ + /* the master sends a stop condition to I2C bus */ + i2c_stop_on_bus(I2C0); + /* disable the I2C0 interrupt */ + i2c_interrupt_disable(I2C0, I2C_INT_ERR); + i2c_interrupt_disable(I2C0, I2C_INT_BUF); + i2c_interrupt_disable(I2C0, I2C_INT_EV); + } + } +} + +/*! + \brief handle I2C0 error interrupt request + \param[in] none + \param[out] none + \retval none +*/ +void I2C0_ErrorIRQ_Handler(void) +{ + /* no acknowledge received */ + if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_AERR)){ + i2c_interrupt_flag_clear(I2C0, I2C_INT_FLAG_AERR); + } + + /* SMBus alert */ + if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_SMBALT)){ + i2c_interrupt_flag_clear(I2C0, I2C_INT_FLAG_SMBALT); + } + + /* bus timeout in SMBus mode */ + if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_SMBTO)){ + i2c_interrupt_flag_clear(I2C0, I2C_INT_FLAG_SMBTO); + } + + /* over-run or under-run when SCL stretch is disabled */ + if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_OUERR)){ + i2c_interrupt_flag_clear(I2C0, I2C_INT_FLAG_OUERR); + } + + /* arbitration lost */ + if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_LOSTARB)){ + i2c_interrupt_flag_clear(I2C0, I2C_INT_FLAG_LOSTARB); + } + + /* bus error */ + if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_BERR)){ + i2c_interrupt_flag_clear(I2C0, I2C_INT_FLAG_BERR); + } + + /* CRC value doesn't match */ + if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_PECERR)){ + i2c_interrupt_flag_clear(I2C0, I2C_INT_FLAG_PECERR); + } + + /* disable the error interrupt */ + i2c_interrupt_disable(I2C0, I2C_INT_ERR); + i2c_interrupt_disable(I2C0, I2C_INT_BUF); + i2c_interrupt_disable(I2C0, I2C_INT_EV); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/I2C1_IE.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/I2C1_IE.c new file mode 100644 index 0000000..409ceaa --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/I2C1_IE.c @@ -0,0 +1,114 @@ +/*! + \file I2C1_IE.c + \brief I2C1 slave receiver interrupt program + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_i2c.h" + +#include "../Master_transmitter_slave_receiver_interrupt/I2C_IE.h" + +uint32_t event2; + +/*! + \brief handle I2C1 event interrupt request + \param[in] none + \param[out] none + \retval none +*/ +void I2C1_EventIRQ_Handler(void) +{ + if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_ADDSEND)){ + /* clear the ADDSEND bit */ + i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_ADDSEND); + }else if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_RBNE)){ + /* if reception data register is not empty ,I2C1 will read a data from I2C_DATA */ + *i2c_rxbuffer++ = i2c_data_receive(I2C1); + }else if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_STPDET)){ + status = SUCCESS; + /* clear the STPDET bit */ + i2c_enable(I2C1); + /* disable I2C1 interrupt */ + i2c_interrupt_disable(I2C1, I2C_INT_ERR); + i2c_interrupt_disable(I2C1, I2C_INT_BUF); + i2c_interrupt_disable(I2C1, I2C_INT_EV); + } +} + +/*! + \brief handle I2C1 error interrupt request + \param[in] none + \param[out] none + \retval none +*/ +void I2C1_ErrorIRQ_Handler(void) +{ + /* no acknowledge received */ + if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_AERR)){ + i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_AERR); + } + + /* SMBus alert */ + if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_SMBALT)){ + i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_SMBALT); + } + + /* bus timeout in SMBus mode */ + if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_SMBTO)){ + i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_SMBTO); + } + + /* over-run or under-run when SCL stretch is disabled */ + if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_OUERR)){ + i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_OUERR); + } + + /* arbitration lost */ + if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_LOSTARB)){ + i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_LOSTARB); + } + + /* bus error */ + if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_BERR)){ + i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_BERR); + } + + /* CRC value doesn't match */ + if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_PECERR)){ + i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_PECERR); + } + + /* disable the error interrupt */ + i2c_interrupt_disable(I2C1, I2C_INT_ERR); + i2c_interrupt_disable(I2C1, I2C_INT_BUF); + i2c_interrupt_disable(I2C1, I2C_INT_EV); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/I2C_IE.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/I2C_IE.h new file mode 100644 index 0000000..7bbde86 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/I2C_IE.h @@ -0,0 +1,60 @@ +/*! + \file I2C1_IE.c + \brief The header file of I2C0 and I2C1 interrupt + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef I2C_IE_H +#define I2C_IE_H + +#include "gd32vf103.h" + +#define I2C0_SLAVE_ADDRESS7 0x82 +#define I2C1_SLAVE_ADDRESS7 0x72 + +extern volatile ErrStatus status; +extern volatile uint8_t* i2c_txbuffer; +extern volatile uint8_t* i2c_rxbuffer; +extern volatile uint16_t I2C_nBytes; + +/* function declarations */ +/* handle I2C0 event interrupt request */ +void I2C0_EventIRQ_Handler(void); +/* handle I2C0 error interrupt request */ +void I2C0_ErrorIRQ_Handler(void); +/* handle I2C1 event interrupt request */ +void I2C1_EventIRQ_Handler(void); +/* handle I2C1 error interrupt request */ +void I2C1_ErrorIRQ_Handler(void); + +#endif /* I2C_IE_H */ + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/gd32vf103_it.c new file mode 100644 index 0000000..a4eee21 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/gd32vf103_it.c @@ -0,0 +1,83 @@ +#include "../Master_transmitter_slave_receiver_interrupt/gd32vf103_it.h" + +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#include "../Master_transmitter_slave_receiver_interrupt/I2C_IE.h" + +/*! + \brief this function handles I2C0 event interrupt request exception + \param[in] none + \param[out] none + \retval none +*/ +void I2C0_EV_IRQHandler(void) +{ + I2C0_EventIRQ_Handler(); +} + +/*! + \brief this function handles I2C0 error interrupt request exception + \param[in] none + \param[out] none + \retval none +*/ +void I2C0_ER_IRQHandler(void) +{ + I2C0_ErrorIRQ_Handler(); +} + +/*! + \brief this function handles I2C1 event interrupt request exception + \param[in] none + \param[out] none + \retval none +*/ +void I2C1_EV_IRQHandler(void) +{ + I2C1_EventIRQ_Handler(); +} + +/*! + \brief this function handles I2C1 error interrupt request exception + \param[in] none + \param[out] none + \retval none +*/ +void I2C1_ER_IRQHandler(void) +{ + I2C1_ErrorIRQ_Handler(); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/gd32vf103_it.h new file mode 100644 index 0000000..7b56750 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/gd32vf103_it.h @@ -0,0 +1,50 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ +/* I2C0 event handle function */ +void I2C0_EV_IRQHandler(void); +/* I2C0 error handle function */ +void I2C0_ER_IRQHandler(void); +/* I2C1 event handle function */ +void I2C1_EV_IRQHandler(void); +/* I2C1 error handle function */ +void I2C1_ER_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/main.c new file mode 100644 index 0000000..f507d3a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/main.c @@ -0,0 +1,208 @@ +/*! + \file main.c + \brief master transmitter slave receiver interrupt + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include + +#include "../Master_transmitter_slave_receiver_interrupt/I2C_IE.h" +#include "gd32vf103v_eval.h" + +uint8_t i2c_buffer_transmitter[16]; +uint8_t i2c_buffer_receiver[16]; + +volatile uint8_t* i2c_txbuffer; +volatile uint8_t* i2c_rxbuffer; +volatile uint16_t I2C_nBytes; +volatile ErrStatus status; +ErrStatus state = ERROR; + +void rcu_config(void); +void gpio_config(void); +void i2c_config(void); +void i2c_clic_config(void); +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint16_t length); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + int i; + + /* initialize LED2, LED3, as the transfer instruction */ + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + rcu_config(); + gpio_config(); + i2c_config(); + i2c_clic_config(); + + for(i=0; i<16; i++){ + i2c_buffer_transmitter[i] = i + 0x80; + } + /* initialize i2c_txbuffer, i2c_rxbuffer, I2C_nBytes and status */ + i2c_txbuffer = i2c_buffer_transmitter; + i2c_rxbuffer = i2c_buffer_receiver; + I2C_nBytes = 16; + status = ERROR; + + /* enable the I2C0 interrupt */ + i2c_interrupt_enable(I2C0, I2C_INT_ERR); + i2c_interrupt_enable(I2C0, I2C_INT_EV); + i2c_interrupt_enable(I2C0, I2C_INT_BUF); + + /* enable the I2C1 interrupt */ + i2c_interrupt_enable(I2C1, I2C_INT_ERR); + i2c_interrupt_enable(I2C1, I2C_INT_EV); + i2c_interrupt_enable(I2C1, I2C_INT_BUF); + + /* the master waits until the I2C bus is idle */ + while(i2c_flag_get(I2C0, I2C_FLAG_I2CBSY)); + + /* the master sends a start condition to I2C bus */ + i2c_start_on_bus(I2C0); + + while((I2C_nBytes>0)); + while(SUCCESS != status); + /* if the transfer is successfully completed, LED2 and LED3 is on */ + state = memory_compare(i2c_buffer_transmitter, i2c_buffer_receiver, 16); + if(SUCCESS == state){ + /* if success, LED2 and LED3 are on */ + gd_eval_led_on(LED2); + gd_eval_led_on(LED3); + }else{ + /* if failed, LED2 and LED3 are off */ + gd_eval_led_off(LED2); + gd_eval_led_off(LED3); + } + while(1){ + } +} + +/*! + \brief memory compare function + \param[in] src : source data + \param[in] dst : destination data + \param[in] length : the compare data length + \param[out] none + \retval ErrStatus : ERROR or SUCCESS +*/ +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint16_t length) +{ + while(length--){ + if(*src++ != *dst++){ + return ERROR; + } + } + return SUCCESS; +} + +/*! + \brief enable the peripheral clock + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOB clock */ + rcu_periph_clock_enable(RCU_GPIOB); + /* enable I2C1 clock */ + rcu_periph_clock_enable(RCU_I2C1); + /* enable I2C0 clock */ + rcu_periph_clock_enable(RCU_I2C0); +} + +/*! + \brief cofigure the GPIO ports. + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* I2C0 and I2C1 GPIO ports */ + /* connect PB6 to I2C0_SCL */ + gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6); + /* connect PB7 to I2C0_SDA */ + gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_7); + /* connect PB10 to I2C1_SCL */ + gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_10); + /* connect PB11 to I2C1_SDA */ + gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_11); +} + +/*! + \brief cofigure the I2C0 and I2C1 interfaces.. + \param[in] none + \param[out] none + \retval none +*/ +void i2c_config(void) +{ + /* I2C clock configure */ + i2c_clock_config(I2C0, 100000, I2C_DTCY_2); + /* I2C address configure */ + i2c_mode_addr_config(I2C0, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, I2C0_SLAVE_ADDRESS7); + /* enable I2C0 */ + i2c_enable(I2C0); + /* enable acknowledge */ + i2c_ack_config(I2C0, I2C_ACK_ENABLE); + i2c_clock_config(I2C1, 100000, I2C_DTCY_2); + /* I2C address configure */ + i2c_mode_addr_config(I2C1, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, I2C1_SLAVE_ADDRESS7); + /* enable I2C1 */ + i2c_enable(I2C1); + /* enable acknowledge */ + i2c_ack_config(I2C1, I2C_ACK_ENABLE); +} + +/*! + \brief cofigure the NVIC peripheral + \param[in] none + \param[out] none + \retval none +*/ +void i2c_clic_config(void) +{ + eclic_global_interrupt_enable(); + eclic_irq_enable(I2C0_EV_IRQn,1,0); + eclic_irq_enable(I2C1_EV_IRQn,2,0); + eclic_irq_enable(I2C0_ER_IRQn,3,0); + eclic_irq_enable(I2C1_ER_IRQn,4,0); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/readme.txt new file mode 100644 index 0000000..55ac1de --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Master_transmitter_slave_receiver_interrupt/readme.txt @@ -0,0 +1,52 @@ +/*! + \file readme.txt + \brief description of the master transmitter and slave receiver interrupt + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to use the I2C +interrupt programming mode in master transmitting mode or slave receiving mode. +In this demo, I2C0 is operated as the master transmitter and I2C1 as the slave +receiver. Moreover,the SCL line and SDA line of I2C0 interface are controled +by the I/O pin PB6 and PB7 respectively. The SCL and SDA of I2C1 are controled +by the pin PB10 and PB11 respectively. + + This demo will send the data of i2c_buffer_transmitter array through I2C1 interface +to the I2C0, and it will store the data received by I2C1 in the i2c_buffer_receiver +array. If transfer is sucessfully completed, LED2 and LED3 are on. + + We shoud use the jumper to connect the PB6 and PB10. The PB7 and PB11 are +connected as well. + + JP16 must be fitted. + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Slave_receiver/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Slave_receiver/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Slave_receiver/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Slave_receiver/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Slave_receiver/main.c new file mode 100644 index 0000000..891e9d8 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Slave_receiver/main.c @@ -0,0 +1,145 @@ +/*! + \file main.c + \brief slave receiver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +#define I2C0_OWN_ADDRESS7 0x82 + +uint8_t i2c_receiver[16]; + +void rcu_config(void); +void gpio_config(void); +void i2c_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + int i; + + /* configure USART */ + gd_eval_com_init(EVAL_COM0); + + printf("\r\n I2C Start\n"); + + /* RCU config */ + rcu_config(); + /* GPIO config */ + gpio_config(); + /* I2C config */ + i2c_config(); + + i=0; + /* wait until ADDSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)); + /* clear ADDSEND bit */ + i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); + printf("\r\n I2C slave receive data: \r\n\n"); + for(i=0; i<16; i++){ + /* wait until the RBNE bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_RBNE)); + + /* read a data byte from I2C_DATA */ + i2c_receiver[i] = i2c_data_receive(I2C0); + } + /* wait until the STPDET bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_STPDET)); + /* clear the STPDET bit */ + i2c_enable(I2C0); + + printf("\r\n I2C SUCCESS\n"); + + while(1){ + } +} + +/*! + \brief enable the peripheral clock + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOB clock */ + rcu_periph_clock_enable(RCU_GPIOB); + /* enable I2C0 clock */ + rcu_periph_clock_enable(RCU_I2C0); +} + +/*! + \brief cofigure the GPIO ports + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* connect PB6 to I2C0_SCL */ + /* connect PB7 to I2C0_SDA */ + gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7); +} + +/*! + \brief cofigure the I2C0 interfaces + \param[in] none + \param[out] none + \retval none +*/ +void i2c_config(void) +{ + /* I2C clock configure */ + i2c_clock_config(I2C0, 100000, I2C_DTCY_2); + /* I2C address configure */ + i2c_mode_addr_config(I2C0, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, I2C0_OWN_ADDRESS7); + /* enable I2C0 */ + i2c_enable(I2C0); + /* enable acknowledge */ + i2c_ack_config(I2C0, I2C_ACK_ENABLE); +} + +/* retarget the C library printf function to the usart */ +int fputc(int ch, FILE *f) +{ + usart_data_transmit(EVAL_COM0, (uint8_t)ch); + while (RESET == usart_flag_get(EVAL_COM0, USART_FLAG_TBE)); + return ch; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Slave_receiver/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Slave_receiver/readme.txt new file mode 100644 index 0000000..486b0e9 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Slave_receiver/readme.txt @@ -0,0 +1,49 @@ +/*! + \file readme.txt + \brief description of the slave receiver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows the I2C programming +mode in slave receiving mode. In this demo, I2C0 is operated as slave receiver, +and the SCL line and SDA line of I2C0 interface are controled by the I/O pin +PB6 and PB7 respectively. + + This demo shows the receving process of the slave. And it will store the +received data in the i2c_receiver array. + + The demo doesn't perform the data transfer actually, which is due to no specific +master.In the specific application, we need config the master to start a data +transmission.In addition,the master and the slave may need to be connected by +the jumper if necessary. + + JP16 must be fitted. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Slave_transmitter/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Slave_transmitter/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Slave_transmitter/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Slave_transmitter/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Slave_transmitter/main.c new file mode 100644 index 0000000..fcb2179 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Slave_transmitter/main.c @@ -0,0 +1,151 @@ +/*! + \file main.c + \brief slave transmitter + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" + +#define I2C_10BIT_ADDRESS 0 + +#define I2C0_OWN_ADDRESS7 0x82 +#define I2C0_SLAVE_ADDRESS7 0x72 +#define I2C0_OWN_ADDRESS10 0x0322 + +uint8_t i2c_transmitter[16]; + +void rcu_config(void); +void gpio_config(void); +void i2c_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + int i; + + /* RCU config */ + rcu_config(); + /* GPIO config */ + gpio_config(); + /* I2C config */ + i2c_config(); + + for(i=0; i<16; i++){ + i2c_transmitter[i] = i+0x80; + } + +#if I2C_10BIT_ADDRESS + /* wait until ADDSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)); + /* clear ADDSEND bit */ + i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); + /* wait until ADDSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)); + /* clear ADDSEND bit */ + i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); +#else + /* wait until ADDSEND bit is set */ + while(!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)); + /* clear ADDSEND bit */ + i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); +#endif + /* wait until the transmission data register is empty */ + while(!i2c_flag_get(I2C0, I2C_FLAG_TBE)); + + for(i=0;i<16;i++){ + /* send a data byte */ + i2c_data_transmit(I2C0, i2c_transmitter[i]); + /* wait until the transmission data register is empty */ + while(!i2c_flag_get(I2C0, I2C_FLAG_TBE)); + } + /* the master doesn't acknowledge for the last byte */ + while(!i2c_flag_get(I2C0, I2C_FLAG_AERR)); + /* clear the bit of AERR */ + i2c_flag_clear(I2C0, I2C_FLAG_AERR); + + while(1){ + } +} + +/*! + \brief enable the peripheral clock + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + /* enable GPIOB clock */ + rcu_periph_clock_enable(RCU_GPIOB); + /* enable I2C0 clock */ + rcu_periph_clock_enable(RCU_I2C0); +} + +/*! + \brief cofigure the GPIO ports + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* connect PB6 to I2C0_SCL */ + /* connect PB7 to I2C0_SDA */ + gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7); +} + +/*! + \brief cofigure the I2C0 interfaces + \param[in] none + \param[out] none + \retval none +*/ +void i2c_config(void) +{ + /* I2C clock configure */ + i2c_clock_config(I2C0, 400000, I2C_DTCY_2); + /* I2C address configure */ +#if I2C_10BIT_ADDRESS + i2c_mode_addr_config(I2C0, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_10BITS, I2C0_OWN_ADDRESS10); +#else + i2c_mode_addr_config(I2C0, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, I2C0_OWN_ADDRESS7); +#endif + /* enable I2C0 */ + i2c_enable(I2C0); + /* enable acknowledge */ + i2c_ack_config(I2C0, I2C_ACK_ENABLE); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Slave_transmitter/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Slave_transmitter/readme.txt new file mode 100644 index 0000000..be9912c --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/I2C/Slave_transmitter/readme.txt @@ -0,0 +1,52 @@ +/*! + \file readme.txt + \brief description of the slave transmitter + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows the I2C programming +mode in slave transmitting mode.In this demo,I2C0 is operated as slave +transmitter,and the SCL line and SDA line of I2C0 interface are controled by +the I/O pin PB6 and PB7 respectively. + + This demo shows the sending data process of the slave. And it will send the +data in the i2c_transmitter array through the I2C0. + + The demo doesn't perform the data transfer actually, which is due to no specific +master.In the specific application, we need config the master to start a data +transmission.In addition,the master and the slave may need to be connected by +the jumper if necessary.When the macro I2C_10BIT_ADDRESS is 1, I2C communicate in +10 bit addressing mode, otherwise, I2C communicate in 7 bit addressing mode. + + JP16 must be fitted. + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/gd32vf103_it.c new file mode 100644 index 0000000..bd781ea --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/gd32vf103_it.c @@ -0,0 +1,62 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_it.h" +#include "gd32vf103v_eval.h" +#include "main.h" + +/*! + \brief this function handles eclic_mtip exception + \param[in] none + \param[out] none + \retval none +*/ +void eclic_mtip_handler(void) +{ + *(uint64_t*)(TIMER_CTRL_ADDR + TIMER_MTIME) = 0; + led_spark(); +} + +/*! + \brief this function handles EXTI10_15 exception + \param[in] none + \param[out] none + \retval none +*/ +void EXTI10_15_IRQHandler(void) +{ + if(SET == exti_interrupt_flag_get(EXTI_13)){ + exti_interrupt_flag_clear(EXTI_13); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/gd32vf103_it.h new file mode 100644 index 0000000..c27b8a1 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/gd32vf103_it.h @@ -0,0 +1,46 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ +/* eclic_mtip handle function */ +void eclic_mtip_handler(void); +/* EXTI10_15 handle function */ +void EXTI10_15_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/main.c new file mode 100644 index 0000000..cd67ffe --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/main.c @@ -0,0 +1,138 @@ +/*! + \file main.c + \brief deepsleep wakeup through exti interrupt + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" +#include "systick.h" +#include "main.h" + +#define BKP_DATA_REG_NUM 42 + +void led_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* configure systick */ + systick_config(); + + /* led config */ + led_config(); + /* clock enable */ + rcu_periph_clock_enable(RCU_PMU); + /* wakeup key config */ + gd_eval_key_init(KEY_A, KEY_MODE_GPIO); + /* tamper key EXTI config */ + gd_eval_key_init(KEY_B, KEY_MODE_EXTI); + /* press wakeup key to enter deepsleep mode and use tamper key generate a exti interrupt to wakeup mcu */ + while(1){ + if(RESET == gpio_input_bit_get(KEY_A_GPIO_PORT, KEY_A_PIN)) + pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); + } +} + +/*! + \brief toggle the led + \param[in] none + \param[out] none + \retval none +*/ +void led_spark(void) +{ + static __IO uint32_t timingdelaylocal = 0; + + if (timingdelaylocal != 0x00){ + /* all the leds on */ + if(timingdelaylocal < 200){ + gd_eval_led_on(LED1); + gd_eval_led_on(LED2); + gd_eval_led_on(LED3); + gd_eval_led_on(LED4); + }else{ + /* all the leds off */ + gd_eval_led_off(LED1); + gd_eval_led_off(LED2); + gd_eval_led_off(LED3); + gd_eval_led_off(LED4); + } + timingdelaylocal--; + }else{ + timingdelaylocal = 400; + } +} + +/*! + \brief check if the backup data registers are clear or not + \param[in] none + \param[out] none + \retval the number of data register +*/ +uint32_t is_backup_register_clear(void) +{ + uint32_t temp = 0; + + for(temp = 0; temp < BKP_DATA_REG_NUM; temp++){ + if(temp < 10){ + /* check if the data of data register 0-9 is 0x0000 */ + if(0x0000 != BKP_DATA_GET(BKP_DATA0_9(temp))){ + return temp+1; + } + }else{ + /* check if the data of data register 10-41 is 0x0000 */ + if(0x0000 != BKP_DATA_GET(BKP_DATA10_41(temp))){ + return temp+1; + } + } + } + return 0; +} + +/*! + \brief led config + \param[in] none + \param[out] none + \retval none +*/ +void led_config(void) +{ + gd_eval_led_init(LED1); + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + gd_eval_led_init(LED4); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/main.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/main.h new file mode 100644 index 0000000..b6c147f --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/main.h @@ -0,0 +1,41 @@ +/*! + \file main.h + \brief the header file of the main + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef MAIN_H +#define MAIN_H + +/* led spark function */ +void led_spark(void); + +#endif /* MAIN_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/readme.txt new file mode 100644 index 0000000..3299df8 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/readme.txt @@ -0,0 +1,39 @@ +/*! + \file readme.txt + \brief description of the deepsleep wakeup through exti demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it shows pmu how to enter deepsleep +mode and wakeup it. Press wakeup key to enter deepsleep mode, led stop flashing. When +you press tamper key to generate an exti interrupt, mcu will be wakeuped from deepsleep +mode, led sparks again. But the led sparks slower, because at this time IRC8M is the system +clock. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/systick.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/systick.c new file mode 100644 index 0000000..f9870b5 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/systick.c @@ -0,0 +1,80 @@ +/*! + \file systick.c + \brief the systick configuration file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" +#include "n200_func.h" + +volatile static uint32_t delay; + +/*! + \brief configure systick + \param[in] none + \param[out] none + \retval none +*/ +void systick_config(void) +{ + eclic_global_interrupt_enable(); + *(uint64_t*)(TIMER_CTRL_ADDR + TIMER_MTIMECMP) = TIMER_FREQ/1000 ; + eclic_irq_enable(CLIC_INT_TMR, 2, 0); + *(uint64_t*)(TIMER_CTRL_ADDR + TIMER_MTIME) = 0; +} + +/*! + \brief delay a time in milliseconds + \param[in] count: count in milliseconds + \param[out] none + \retval none +*/ +void delay_1ms(uint32_t count) +{ + delay = count; + + while(0U != delay){ + } +} + +/*! + \brief delay decrement + \param[in] none + \param[out] none + \retval none +*/ +void delay_decrement(void) +{ + if (0U != delay){ + delay--; + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/systick.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/systick.h new file mode 100644 index 0000000..1ef3c75 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Deepsleep_wakeup_exti/systick.h @@ -0,0 +1,47 @@ +/*! + \file systick.h + \brief the header file of systick + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef SYS_TICK_H +#define SYS_TICK_H + +#include + +/* configure systick */ +void systick_config(void); +/* delay a time in milliseconds */ +void delay_1ms(uint32_t count); +/* delay decrement */ +void delay_decrement(void); + +#endif /* SYS_TICK_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Low_voltage_detector/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Low_voltage_detector/gd32vf103_it.c new file mode 100644 index 0000000..80d56ab --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Low_voltage_detector/gd32vf103_it.c @@ -0,0 +1,50 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_it.h" +#include "gd32vf103v_eval.h" + +/*! + \brief this function handles LVD exception + \param[in] none + \param[out] none + \retval none +*/ +void LVD_IRQHandler(void) +{ + if(RESET != exti_interrupt_flag_get(EXTI_16)){ + gd_eval_led_toggle(LED1); + exti_interrupt_flag_clear(EXTI_16); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Low_voltage_detector/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Low_voltage_detector/gd32vf103_it.h new file mode 100644 index 0000000..6e099ba --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Low_voltage_detector/gd32vf103_it.h @@ -0,0 +1,44 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ +/* LVD handle function */ +void LVD_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Low_voltage_detector/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Low_voltage_detector/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Low_voltage_detector/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Low_voltage_detector/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Low_voltage_detector/main.c new file mode 100644 index 0000000..8be081b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Low_voltage_detector/main.c @@ -0,0 +1,92 @@ +/*! + \file main.c + \brief low voltage detector + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +#define BKP_DATA_REG_NUM 42 + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* configure ECLIC */ + eclic_global_interrupt_enable(); + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL3_PRIO1); + eclic_irq_enable(LVD_IRQn, 1, 0); + /* clock enable */ + rcu_periph_clock_enable(RCU_PMU); + /* initialize LED1 */ + gd_eval_led_init(LED1); + /* turn on LED1*/ + gd_eval_led_on(LED1); + /* configure EXTI_16 */ + exti_init(EXTI_16, EXTI_INTERRUPT, EXTI_TRIG_BOTH); + /* configure the lvd threshold to 2.9v */ + pmu_lvd_select(PMU_LVDT_7); + + while(1){ + } +} + +/*! + \brief check if the backup data registers are clear or not + \param[in] none + \param[out] none + \retval the number of data register +*/ +uint32_t is_backup_register_clear(void) +{ + uint32_t temp = 0; + + for(temp = 0; temp < BKP_DATA_REG_NUM; temp++){ + if(temp < 10){ + /* check if the data of data register 0-9 is 0x0000 */ + if(0x0000 != BKP_DATA_GET(BKP_DATA0_9(temp))){ + return temp+1; + } + }else{ + /* check if the data of data register 10-41 is 0x0000 */ + if(0x0000 != BKP_DATA_GET(BKP_DATA10_41(temp))){ + return temp+1; + } + } + } + return 0; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Low_voltage_detector/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Low_voltage_detector/readme.txt new file mode 100644 index 0000000..b0105a6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Low_voltage_detector/readme.txt @@ -0,0 +1,40 @@ +/*! + \file readme.txt + \brief description of the low voltage detector demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it shows how to use low voltage detector. +If VDD/VDDA is higher or lower than the LVD threshold, then a lvd event will occur. The event +is internally connected to the EXTI line 16 and can generate an interrupt if enabled through +the EXTI registers. Use external power connect 3.3v pin and GND pin of the board , adjust +voltage higher or lower than the LVD threshold 2.9v, LED1 will toggle. + \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Standby_wakeup_pin/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Standby_wakeup_pin/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Standby_wakeup_pin/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Standby_wakeup_pin/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Standby_wakeup_pin/main.c new file mode 100644 index 0000000..7a6fb49 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Standby_wakeup_pin/main.c @@ -0,0 +1,81 @@ +/*! + \file main.c + \brief standby wakeup through wakeup pin + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +void led_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* clock enable */ + rcu_periph_clock_enable(RCU_PMU); + /* led configuration and turn on all led */ + led_config(); + gd_eval_led_on(LED1); + gd_eval_led_on(LED2); + gd_eval_led_on(LED3); + gd_eval_led_on(LED4); + /* tamper key configuration */ + gd_eval_key_init(KEY_B, KEY_MODE_GPIO); + /* wakeup pin enable */ + pmu_wakeup_pin_enable(); + /* press tamper key to enter standby mode and use wakeup key to wakeup mcu */ + while(1){ + if(RESET == gpio_input_bit_get(KEY_B_GPIO_PORT, KEY_B_PIN)){ + pmu_to_standbymode(WFI_CMD); + } + } +} + +/*! + \brief configure led + \param[in] none + \param[out] none + \retval none +*/ +void led_config(void) +{ + gd_eval_led_init(LED1); + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + gd_eval_led_init(LED4); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Standby_wakeup_pin/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Standby_wakeup_pin/readme.txt new file mode 100644 index 0000000..055d041 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/PMU/Standby_wakeup_pin/readme.txt @@ -0,0 +1,40 @@ +/*! + \file readme.txt + \brief description of the standby mode wakeup through wakeup pin demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it shows pmu how to enter standby +mode and wakeup it. Press tamper key enter standby mode, led turn off. When you press +wakeup key, mcu will be wakeuped from standby mode, led will be turn on. when exit from +the standby mode, a power-on reset occurs and the mcu will execute instruction code +from the 0x00000000 address. + \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/gd32vf103_it.c new file mode 100644 index 0000000..5793f8d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/gd32vf103_it.c @@ -0,0 +1,64 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_it.h" +#include "gd32vf103v_eval.h" + +extern __IO uint32_t timedisplay; + +/*! + \brief this function handles RTC global interrupt request + \param[in] none + \param[out] none + \retval none +*/ +void RTC_IRQHandler(void) +{ + if (rtc_flag_get(RTC_FLAG_SECOND) != RESET){ + /* clear the RTC second interrupt flag*/ + rtc_flag_clear(RTC_FLAG_SECOND); + + /* enable time update */ + timedisplay = 1; + + /* wait until last write operation on RTC registers has finished */ + rtc_lwoff_wait(); + /* reset RTC counter when time is 23:59:59 */ + if (rtc_counter_get() == 0x00015180){ + rtc_counter_set(0x0); + /* wait until last write operation on RTC registers has finished */ + rtc_lwoff_wait(); + } + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/gd32vf103_it.h new file mode 100644 index 0000000..c009cbb --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/gd32vf103_it.h @@ -0,0 +1,44 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ +/* RTC global interrupt function */ +void RTC_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/main.c new file mode 100644 index 0000000..cb295f0 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/main.c @@ -0,0 +1,156 @@ +/*! + \file main.c + \brief RTC calendar + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" +#include "rtc.h" +#include + +#define BKP_DATA_REG_NUM 42 + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* COM0 configure */ + gd_eval_com_init(EVAL_COM0); + + /* ECLIC configure */ + eclic_global_interrupt_enable(); + eclic_set_nlbits(ECLIC_GROUP_LEVEL3_PRIO1); + eclic_irq_enable(RTC_IRQn, 1, 0); + + printf( "\r\n This is a RTC demo...... \r\n" ); + + if (bkp_data_read(BKP_DATA_0) != 0xA5A5){ + /* backup data register value is not correct or not yet programmed + (when the first time the program is executed) */ + printf("\r\nThis is a RTC demo!\r\n"); + printf("\r\n\n RTC not yet configured...."); + + /* RTC configuration */ + rtc_configuration(); + + printf("\r\n RTC configured...."); + + /* adjust time by values entred by the user on the hyperterminal */ + time_adjust(); + + bkp_data_write(BKP_DATA_0, 0xA5A5); + }else{ + /* check if the power on reset flag is set */ + if (rcu_flag_get(RCU_FLAG_PORRST) != RESET){ + printf("\r\n\n Power On Reset occurred...."); + }else if (rcu_flag_get(RCU_FLAG_SWRST) != RESET){ + /* check if the pin reset flag is set */ + printf("\r\n\n External Reset occurred...."); + } + + /* allow access to BKP domain */ + rcu_periph_clock_enable(RCU_PMU); + pmu_backup_write_enable(); + + printf("\r\n No need to configure RTC...."); + /* wait for RTC registers synchronization */ + rtc_register_sync_wait(); + + /* enable the RTC second */ + rtc_interrupt_enable(RTC_INT_SECOND); + + /* wait until last write operation on RTC registers has finished */ + rtc_lwoff_wait(); + } + +#ifdef RTCCLOCKOUTPUT_ENABLE + /* enable PMU and BKPI clocks */ + rcu_periph_clock_enable(RCU_BKPI); + rcu_periph_clock_enable(RCU_PMU); + /* allow access to BKP domain */ + pmu_backup_write_enable(); + + /* disable the tamper pin */ + bkp_tamper_detection_disable(); + + /* enable RTC clock output on tamper Pin */ + bkp_rtc_calibration_output_enable(); +#endif + + /* clear reset flags */ + rcu_all_reset_flag_clear(); + + /* display time in infinite loop */ + time_show(); + + while (1){ + } +} + +/*! + \brief check if the backup data registers are clear or not + \param[in] none + \param[out] none + \retval the number of data register +*/ +uint32_t is_backup_register_clear(void) +{ + uint32_t temp = 0; + + for(temp = 0; temp < BKP_DATA_REG_NUM; temp++){ + if(temp < 10){ + /* check if the data of data register 0-9 is 0x0000 */ + if(0x0000 != BKP_DATA_GET(BKP_DATA0_9(temp))){ + return temp+1; + } + }else{ + /* check if the data of data register 10-41 is 0x0000 */ + if(0x0000 != BKP_DATA_GET(BKP_DATA10_41(temp))){ + return temp+1; + } + } + } + return 0; +} + +/* retarget the C library printf function to the USART */ +int fputc(int ch, FILE *f) +{ + usart_data_transmit(EVAL_COM0, (uint8_t)ch); + while(RESET == usart_flag_get(EVAL_COM0, USART_FLAG_TBE)); + + return ch; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/readme.txt new file mode 100644 index 0000000..fc38937 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/readme.txt @@ -0,0 +1,44 @@ +/*! + \file readme.txt + \brief description of calendar demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it explains how to configure the + RTC module. In this demo, RTC peripheral is configured to display calendar. + Select LXTAL as RTC clock source. And the HyperTerminal should be connected to the + evaluation board via COM0. + After start-up,if the BKP data register is written to a key value. If the value + is incorrect, the program will ask to set the time on the HyperTerminal. If the + key value is correct, by the HyperTerminal set time,the calendar will be displayed + on the HyperTerminal. + The RTC module is in the Backup Domain, and is not reset by the system reset. + \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/rtc.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/rtc.c new file mode 100644 index 0000000..b18c151 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/rtc.c @@ -0,0 +1,205 @@ +/*! + \file rtc.c + \brief RTC check and config,time_show and time_adjust function + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "rtc.h" + +/* enter the second interruption,set the second interrupt flag to 1 */ +__IO uint32_t timedisplay; + +/*! + \brief configure the RTC + \param[in] none + \param[out] none + \retval none +*/ +void rtc_configuration(void) +{ + /* enable PMU and BKPI clocks */ + rcu_periph_clock_enable(RCU_BKPI); + rcu_periph_clock_enable(RCU_PMU); + /* allow access to BKP domain */ + pmu_backup_write_enable(); + + /* reset backup domain */ + bkp_deinit(); + + /* enable LXTAL */ + rcu_osci_on(RCU_LXTAL); + /* wait till LXTAL is ready */ + rcu_osci_stab_wait(RCU_LXTAL); + + /* select RCU_LXTAL as RTC clock source */ + rcu_rtc_clock_config(RCU_RTCSRC_LXTAL); + + /* enable RTC Clock */ + rcu_periph_clock_enable(RCU_RTC); + + /* wait for RTC registers synchronization */ + rtc_register_sync_wait(); + + /* wait until last write operation on RTC registers has finished */ + rtc_lwoff_wait(); + + /* enable the RTC second interrupt*/ + rtc_interrupt_enable(RTC_INT_SECOND); + + /* wait until last write operation on RTC registers has finished */ + rtc_lwoff_wait(); + + /* set RTC prescaler: set RTC period to 1s */ + rtc_prescaler_set(32767); + + /* wait until last write operation on RTC registers has finished */ + rtc_lwoff_wait(); +} + +/*! + \brief return the time entered by user, using Hyperterminal + \param[in] none + \param[out] none + \retval current time of RTC counter value +*/ +uint32_t time_regulate(void) +{ + uint32_t tmp_hh = 0xFF, tmp_mm = 0xFF, tmp_ss = 0xFF; + + printf("\r\n==============Time Settings====================================="); + printf("\r\n Please Set Hours"); + + while (tmp_hh == 0xFF){ + tmp_hh = usart_scanf(23); + } + printf(": %d", tmp_hh); + printf("\r\n Please Set Minutes"); + while (tmp_mm == 0xFF){ + tmp_mm = usart_scanf(59); + } + printf(": %d", tmp_mm); + printf("\r\n Please Set Seconds"); + while (tmp_ss == 0xFF){ + tmp_ss = usart_scanf(59); + } + printf(": %d", tmp_ss); + + /* return the value store in RTC counter register */ + return((tmp_hh*3600 + tmp_mm*60 + tmp_ss)); +} + +/*! + \brief adjust time + \param[in] none + \param[out] none + \retval none +*/ +void time_adjust(void) +{ + /* wait until last write operation on RTC registers has finished */ + rtc_lwoff_wait(); + /* change the current time */ + rtc_counter_set(time_regulate()); + /* wait until last write operation on RTC registers has finished */ + rtc_lwoff_wait(); +} + +/*! + \brief display the current time + \param[in] timeVar: RTC counter value + \param[out] none + \retval none +*/ +void time_display(uint32_t timevar) +{ + uint32_t thh = 0, tmm = 0, tss = 0; + + /* compute hours */ + thh = timevar / 3600; + /* compute minutes */ + tmm = (timevar % 3600) / 60; + /* compute seconds */ + tss = (timevar % 3600) % 60; + + printf(" Time: %0.2d:%0.2d:%0.2d\r\n", thh, tmm, tss); +} + +/*! + \brief show the current time (HH:MM:SS) on the Hyperterminal + \param[in] none + \param[out] none + \retval none +*/ +void time_show(void) +{ + printf("\n\r"); + + /* infinite loop */ + while (1){ + /* if 1s has paased */ + if (timedisplay == 1){ + /* display current time */ + time_display(rtc_counter_get()); + timedisplay = 0; + } + } +} + +/*! + \brief get numeric values from the hyperterminal + \param[in] value: input value from the hyperterminal + \param[out] none + \retval input value in BCD mode +*/ +uint8_t usart_scanf(uint32_t value) +{ + uint32_t index = 0; + uint32_t tmp[2] = {0, 0}; + + while (index < 2){ + /* loop until RBNE = 1 */ + while (usart_flag_get(USART0, USART_FLAG_RBNE) == RESET); + tmp[index++] = (usart_data_receive(USART0)); + + if ((tmp[index - 1] < 0x30) || (tmp[index - 1] > 0x39)){ + printf("\n\rPlease enter valid number between 0 and 9\n"); + index--; + } + } + /* calculate the Corresponding value */ + index = (tmp[1] - 0x30) + ((tmp[0] - 0x30) * 10); + /* check */ + if (index > value){ + printf("\n\rPlease enter valid number between 0 and %d\n", value); + return 0xFF; + } + return index; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/rtc.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/rtc.h new file mode 100644 index 0000000..6295f46 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/RTC/Calendar_demo/rtc.h @@ -0,0 +1,49 @@ +/*! + \file rtc.h + \brief headfile of RTC check and config,time_show and time_adjust function + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __RTC_H +#define __RTC_H + +#include "gd32vf103.h" +#include + +void rtc_configuration(void); +uint32_t time_regulate(void); +void time_adjust(void); +void time_display(uint32_t timevar); +void time_show(void); +uint8_t usart_scanf(uint32_t value); + +#endif /* __RTC_H */ + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/I2S_master_transmit_slave_receive_dma/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/I2S_master_transmit_slave_receive_dma/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/I2S_master_transmit_slave_receive_dma/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/I2S_master_transmit_slave_receive_dma/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/I2S_master_transmit_slave_receive_dma/main.c new file mode 100644 index 0000000..fff37bf --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/I2S_master_transmit_slave_receive_dma/main.c @@ -0,0 +1,208 @@ +/*! + \file main.c + \brief I2S master send and slave receive communication use DMA + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" + +#define ARRAYSIZE 10 + +uint16_t i2s1_send_array[ARRAYSIZE] = {0xAAB1, 0xAAB2, 0xAAB3, 0xAAB4, 0xAAB5, 0xAAB6, 0xAAB7, 0xAAB8, 0xAAB9, 0xAABA}; +uint16_t i2s2_receive_array[ARRAYSIZE]; +ErrStatus memory_compare(uint16_t* src, uint16_t* dst, uint8_t length); +uint32_t send_n = 0, receive_n = 0; + +void rcu_config(void); +void gpio_config(void); +void dma_config(void); +void spi_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* initialize the LED */ + gd_eval_led_init(LED2); + + /* peripheral clock enable */ + rcu_config(); + /* GPIO configure */ + gpio_config(); + /* DMA configure */ + dma_config(); + /* SPI configure */ + spi_config(); + /* SPI DMA enable */ + spi_dma_enable(SPI2, SPI_DMA_RECEIVE); + spi_dma_enable(SPI1, SPI_DMA_TRANSMIT); + /* DMA channel enable */ + dma_channel_enable(DMA1, DMA_CH0); + dma_channel_enable(DMA0, DMA_CH4); + /* SPI enable */ + i2s_enable(SPI2); + i2s_enable(SPI1); + + /* wait DMA transmit complete */ + while(!dma_flag_get(DMA0, DMA_CH4, DMA_FLAG_FTF)); + while(!dma_flag_get(DMA1, DMA_CH0, DMA_FLAG_FTF)); + + /* compare receive data with send data */ + if(ERROR != memory_compare(i2s2_receive_array, i2s1_send_array, ARRAYSIZE)){ + gd_eval_led_on(LED2); + }else{ + gd_eval_led_off(LED2); + } + + while(1); +} + +/*! + \brief configure different peripheral clocks + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + rcu_pll2_config(RCU_PLL2_MUL8); + rcu_osci_on(RCU_PLL2_CK); + while((RCU_CTL & RCU_CTL_PLL2STB) == 0){ + } + rcu_i2s1_clock_config(RCU_I2S1SRC_CKPLL2_MUL2); + rcu_i2s2_clock_config(RCU_I2S2SRC_CKPLL2_MUL2); + + rcu_periph_clock_enable(RCU_SPI1); + rcu_periph_clock_enable(RCU_SPI2); + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_GPIOC); + rcu_periph_clock_enable(RCU_AF); + rcu_periph_clock_enable(RCU_DMA0); + rcu_periph_clock_enable(RCU_DMA1); +} + +/*! + \brief configure the GPIO peripheral + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* I2S1 GPIO config: I2S1_WS/PB12, I2S1_CK/PB13, I2S_SD/PB15 */ + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_15); + + /* I2S2 GPIO config: I2S2_WS/PA4, I2S2_CK/PC10, I2S2_SD/PC12 */ + gpio_pin_remap_config(GPIO_SPI2_REMAP, ENABLE); + gpio_init(GPIOC, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_10 | GPIO_PIN_12); + gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_4); +} + +/*! + \brief configure the DMA peripheral + \param[in] none + \param[out] none + \retval none +*/ +void dma_config(void) +{ + dma_parameter_struct dma_init_struct; + + /* SPI1 transmit dma config: DMA0,DMA_CH4 */ + dma_deinit(DMA0, DMA_CH4); + dma_struct_para_init(&dma_init_struct); + + dma_init_struct.periph_addr = (uint32_t)&SPI_DATA(SPI1); + dma_init_struct.memory_addr = (uint32_t)i2s1_send_array; + dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; + dma_init_struct.memory_width = DMA_MEMORY_WIDTH_16BIT; + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_16BIT; + dma_init_struct.priority = DMA_PRIORITY_LOW; + dma_init_struct.number = ARRAYSIZE; + dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_init(DMA0, DMA_CH4, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA0, DMA_CH4); + dma_memory_to_memory_disable(DMA0, DMA_CH4); + + /* SPI2 receive dma config: DMA1-DMA_CH0 */ + dma_deinit(DMA1, DMA_CH0); + dma_init_struct.periph_addr = (uint32_t)&SPI_DATA(SPI2); + dma_init_struct.memory_addr = (uint32_t)i2s2_receive_array; + dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY; + dma_init_struct.priority = DMA_PRIORITY_HIGH; + dma_init(DMA1, DMA_CH0, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA1, DMA_CH0); + dma_memory_to_memory_disable(DMA1, DMA_CH0); +} + +/*! + \brief configure the SPI peripheral + \param[in] none + \param[out] none + \retval none +*/ +void spi_config(void) +{ + spi_i2s_deinit(SPI1); + spi_i2s_deinit(SPI2); + + i2s_init(SPI1, I2S_MODE_MASTERTX, I2S_STD_PHILLIPS, I2S_CKPL_LOW); + i2s_psc_config(SPI1, I2S_AUDIOSAMPLE_44K, I2S_FRAMEFORMAT_DT16B_CH16B, I2S_MCKOUT_DISABLE); + + i2s_init(SPI2, I2S_MODE_SLAVERX, I2S_STD_PHILLIPS, I2S_CKPL_LOW); + i2s_psc_config(SPI2, I2S_AUDIOSAMPLE_44K, I2S_FRAMEFORMAT_DT16B_CH16B, I2S_MCKOUT_DISABLE); +} + +/*! + \brief memory compare function + \param[in] src: source data pointer + \param[in] dst: destination data pointer + \param[in] length: the compare data length + \param[out] none + \retval ErrStatus : ERROR or SUCCESS +*/ +ErrStatus memory_compare(uint16_t* src, uint16_t* dst, uint8_t length) +{ + while(length--){ + if(*src++ != *dst++) + return ERROR; + } + return SUCCESS; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/I2S_master_transmit_slave_receive_dma/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/I2S_master_transmit_slave_receive_dma/readme.txt new file mode 100644 index 0000000..651364d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/I2S_master_transmit_slave_receive_dma/readme.txt @@ -0,0 +1,41 @@ +/*! + \file readme.txt + \brief description of I2S master send and slave receive communication use DMA demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it shows I2S1 master send and I2S2 slave +receive communication by using DMA mode. After the communication is complete, if data received +is equal to data transmitted, led2 turns on, if not led2 turns off. + + Connect I2S1 WS PIN(PB12) to I2S2 WS PIN(PA4). + Connect I2S1 CK PIN(PB13) to I2S2 CK PIN(PC10). + Connect I2S1 SD PIN(PB15) to I2S2 SD PIN(PC12). \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_dma/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_dma/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_dma/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_dma/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_dma/main.c new file mode 100644 index 0000000..b7a3ad3 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_dma/main.c @@ -0,0 +1,255 @@ +/*! + \file main.c + \brief SPI fullduplex communication use DMA + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" + +#define ARRAYSIZE 10 + +uint8_t spi0_send_array[ARRAYSIZE] = {0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA}; +uint8_t spi2_send_array[ARRAYSIZE] = {0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA}; +uint8_t spi0_receive_array[ARRAYSIZE]; +uint8_t spi2_receive_array[ARRAYSIZE]; +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint8_t length); + +uint32_t send_n = 0, receive_n = 0; + +void rcu_config(void); +void gpio_config(void); +void dma_config(void); +void spi_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* initialize the LEDs */ + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + + /* peripheral clock enable */ + rcu_config(); + /* GPIO configure */ + gpio_config(); + /* DMA configure */ + dma_config(); + /* SPI configure */ + spi_config(); + + /* SPI enable */ + spi_enable(SPI2); + spi_enable(SPI0); + + /* DMA channel enable */ + dma_channel_enable(DMA0, DMA_CH1); + dma_channel_enable(DMA0, DMA_CH2); + dma_channel_enable(DMA1, DMA_CH0); + dma_channel_enable(DMA1, DMA_CH1); + + /* SPI DMA enable */ + spi_dma_enable(SPI2, SPI_DMA_TRANSMIT); + spi_dma_enable(SPI2, SPI_DMA_RECEIVE); + spi_dma_enable(SPI0, SPI_DMA_TRANSMIT); + spi_dma_enable(SPI0, SPI_DMA_RECEIVE); + + /* wait dma transmit complete */ + while(!dma_flag_get(DMA0, DMA_CH2, DMA_FLAG_FTF)); + while(!dma_flag_get(DMA1, DMA_CH1, DMA_FLAG_FTF)); + while(!dma_flag_get(DMA0, DMA_CH1, DMA_FLAG_FTF)); + while(!dma_flag_get(DMA1, DMA_CH0, DMA_FLAG_FTF)); + + /* compare receive data with send data */ + if(ERROR !=memory_compare(spi2_receive_array, spi0_send_array, ARRAYSIZE)){ + gd_eval_led_on(LED2); + }else{ + gd_eval_led_off(LED2); + } + + if(ERROR !=memory_compare(spi0_receive_array, spi2_send_array, ARRAYSIZE)){ + gd_eval_led_on(LED3); + }else{ + gd_eval_led_off(LED3); + } + + while(1); +} + +/*! + \brief configure different peripheral clocks + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOC); + rcu_periph_clock_enable(RCU_AF); + rcu_periph_clock_enable(RCU_DMA0); + rcu_periph_clock_enable(RCU_DMA1); + rcu_periph_clock_enable(RCU_SPI0); + rcu_periph_clock_enable(RCU_SPI2); +} + +/*! + \brief configure the GPIO peripheral + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* SPI0 GPIO config:SCK/PA5, MISO/PA6, MOSI/PA7 */ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_7); + gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6); + + /* SPI2 GPIO config:SCK/PC10, MISO/PC11, MOSI/PC12 */ + gpio_pin_remap_config(GPIO_SPI2_REMAP, ENABLE); + gpio_init(GPIOC, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_10 | GPIO_PIN_12); + gpio_init(GPIOC, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_11); +} + +/*! + \brief configure the DMA peripheral + \param[in] none + \param[out] none + \retval none +*/ +void dma_config(void) +{ + dma_parameter_struct dma_init_struct; + + /* SPI0 transmit dma config:DMA0-DMA_CH2 */ + dma_deinit(DMA0, DMA_CH2); + dma_struct_para_init(&dma_init_struct); + + dma_init_struct.periph_addr = (uint32_t)&SPI_DATA(SPI0); + dma_init_struct.memory_addr = (uint32_t)spi0_send_array; + dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; + dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; + dma_init_struct.priority = DMA_PRIORITY_LOW; + dma_init_struct.number = ARRAYSIZE; + dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_init(DMA0, DMA_CH2, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA0, DMA_CH2); + dma_memory_to_memory_disable(DMA0, DMA_CH2); + + /* SPI0 receive dma config:DMA0-DMA_CH1 */ + dma_deinit(DMA0, DMA_CH1); + dma_init_struct.periph_addr = (uint32_t)&SPI_DATA(SPI0); + dma_init_struct.memory_addr = (uint32_t)spi0_receive_array; + dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY; + dma_init_struct.priority = DMA_PRIORITY_HIGH; + dma_init(DMA0, DMA_CH1, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA0, DMA_CH1); + dma_memory_to_memory_disable(DMA0, DMA_CH1); + + /* SPI2 transmit dma config:DMA1,DMA_CH1 */ + dma_deinit(DMA1, DMA_CH1); + dma_init_struct.periph_addr = (uint32_t)&SPI_DATA(SPI2); + dma_init_struct.memory_addr = (uint32_t)spi2_send_array; + dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; + dma_init_struct.priority = DMA_PRIORITY_MEDIUM; + dma_init(DMA1, DMA_CH1, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA1, DMA_CH1); + dma_memory_to_memory_disable(DMA1, DMA_CH1); + + /* SPI2 receive dma config:DMA1,DMA_CH0 */ + dma_deinit(DMA1, DMA_CH0); + dma_init_struct.periph_addr = (uint32_t)&SPI_DATA(SPI2); + dma_init_struct.memory_addr = (uint32_t)spi2_receive_array; + dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY; + dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH; + dma_init(DMA1, DMA_CH0, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA1, DMA_CH0); + dma_memory_to_memory_disable(DMA1, DMA_CH0); +} + +/*! + \brief configure the SPI peripheral + \param[in] none + \param[out] none + \retval none +*/ +void spi_config(void) +{ + spi_parameter_struct spi_init_struct; + /* deinitilize SPI and the parameters */ + spi_i2s_deinit(SPI0); + spi_i2s_deinit(SPI2); + spi_struct_para_init(&spi_init_struct); + + /* SPI0 parameter config */ + spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_init_struct.device_mode = SPI_MASTER; + spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT; + spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; + spi_init_struct.nss = SPI_NSS_SOFT; + spi_init_struct.prescale = SPI_PSC_8; + spi_init_struct.endian = SPI_ENDIAN_MSB; + spi_init(SPI0, &spi_init_struct); + + /* SPI2 parameter config */ + spi_init_struct.device_mode = SPI_SLAVE; + spi_init_struct.nss = SPI_NSS_SOFT; + spi_init(SPI2, &spi_init_struct); + +} + +/*! + \brief memory compare function + \param[in] src: source data pointer + \param[in] dst: destination data pointer + \param[in] length: the compare data length + \param[out] none + \retval ErrStatus : ERROR or SUCCESS +*/ +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint8_t length) +{ + while(length--){ + if(*src++ != *dst++) + return ERROR; + } + return SUCCESS; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_dma/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_dma/readme.txt new file mode 100644 index 0000000..9a6049d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_dma/readme.txt @@ -0,0 +1,43 @@ +/*! + \file readme.txt + \brief description of the master and slave fullduplex communication use dma demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it shows SPI0 and SPI2 fullduplex +communication use DMA mode.After the communicate is complete,if receive data is equal to +send data,led2 and led3 turn on, if not led2 and led3 turn off. + + Connect SPI0 SCK PIN(PA5) to SPI2 SCK PIN(PC10). + Connect SPI0 MISO PIN(PA6) to SPI2 MISO PIN(PC11). + Connect SPI0 MOSI PIN(PA7) to SPI2 MOSI PIN(PC12). + + JP12 and JP13 must be jumpped to SPI. \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_nssp_mode/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_nssp_mode/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_nssp_mode/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_nssp_mode/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_nssp_mode/main.c new file mode 100644 index 0000000..3e95281 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_nssp_mode/main.c @@ -0,0 +1,255 @@ +/*! + \file main.c + \brief SPI master and slave fullduplex communication with nssp mode + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" + +#define ARRAYSIZE 10 + +uint8_t spi0_send_array[ARRAYSIZE] = {0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA}; +uint8_t spi1_send_array[ARRAYSIZE] = {0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA}; +uint8_t spi0_receive_array[ARRAYSIZE]; +uint8_t spi1_receive_array[ARRAYSIZE]; +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint8_t length); +uint32_t send_n = 0, receive_n = 0; + +void rcu_config(void); +void gpio_config(void); +void dma_config(void); +void spi_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* initialize the LEDs */ + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + + /* peripheral clock enable */ + rcu_config(); + /* GPIO configure */ + gpio_config(); + /* DMA configure */ + dma_config(); + /* SPI configure */ + spi_config(); + + spi_nss_output_enable(SPI0); + /* SPI NSSP mode enable */ + spi_nssp_mode_enable(SPI0); + + /* SPI enable */ + spi_enable(SPI1); + spi_enable(SPI0); + + /* DMA channel enable */ + dma_channel_enable(DMA0,DMA_CH1); + dma_channel_enable(DMA0,DMA_CH2); + dma_channel_enable(DMA0,DMA_CH3); + dma_channel_enable(DMA0,DMA_CH4); + + /* SPI DMA enable */ + spi_dma_enable(SPI1, SPI_DMA_TRANSMIT); + spi_dma_enable(SPI1, SPI_DMA_RECEIVE); + spi_dma_enable(SPI0, SPI_DMA_TRANSMIT); + spi_dma_enable(SPI0, SPI_DMA_RECEIVE); + + /* wait dma transmit complete */ + while(!dma_flag_get(DMA0,DMA_CH2,DMA_FLAG_FTF)); + while(!dma_flag_get(DMA0,DMA_CH4,DMA_FLAG_FTF)); + while(!dma_flag_get(DMA0,DMA_CH3,DMA_FLAG_FTF)); + while(!dma_flag_get(DMA0,DMA_CH1,DMA_FLAG_FTF)); + + /* compare receive data with send data */ + if(ERROR != memory_compare(spi1_receive_array, spi0_send_array, ARRAYSIZE)){ + gd_eval_led_on(LED2); + }else{ + gd_eval_led_off(LED2); + } + if(ERROR != memory_compare(spi0_receive_array, spi1_send_array, ARRAYSIZE)){ + gd_eval_led_on(LED3); + }else{ + gd_eval_led_off(LED3); + } + + while(1); +} + +/*! + \brief configure different peripheral clocks + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_DMA0); + rcu_periph_clock_enable(RCU_SPI0); + rcu_periph_clock_enable(RCU_SPI1); +} + +/*! + \brief configure the GPIO peripheral + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* SPI0 GPIO config: NSS/PA4, SCK/PA5, MOSI/PA7 */ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_7); + /* SPI0 GPIO config: MISO/PA6 */ + gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6); + + /* SPI1 GPIO config: NSS/PB12, SCK/PB13, MOSI/PB15 */ + gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_12 | GPIO_PIN_13 |GPIO_PIN_15); + /* SPI1 GPIO config: MISO/PB14 */ + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_14); +} + +/*! + \brief configure the DMA peripheral + \param[in] none + \param[out] none + \retval none +*/ +void dma_config(void) +{ + dma_parameter_struct dma_init_struct; + + /* SPI0 transmit dma config:DMA0,DMA_CH2 */ + dma_deinit(DMA0, DMA_CH2); + dma_struct_para_init(&dma_init_struct); + + dma_init_struct.periph_addr = (uint32_t)&SPI_DATA(SPI0); + dma_init_struct.memory_addr = (uint32_t)spi0_send_array; + dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; + dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; + dma_init_struct.priority = DMA_PRIORITY_LOW; + dma_init_struct.number = ARRAYSIZE; + dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_init(DMA0, DMA_CH2, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA0, DMA_CH2); + dma_memory_to_memory_disable(DMA0, DMA_CH2); + + /* SPI0 receive dma config:DMA0,DMA_CH1 */ + dma_deinit(DMA0, DMA_CH1); + dma_init_struct.periph_addr = (uint32_t)&SPI_DATA(SPI0); + dma_init_struct.memory_addr = (uint32_t)spi0_receive_array; + dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY; + dma_init_struct.priority = DMA_PRIORITY_HIGH; + dma_init(DMA0, DMA_CH1, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA0, DMA_CH1); + dma_memory_to_memory_disable(DMA0, DMA_CH1); + + /* SPI1 transmit dma config:DMA0,DMA_CH4 */ + dma_deinit(DMA0, DMA_CH4); + dma_init_struct.periph_addr = (uint32_t)&SPI_DATA(SPI1); + dma_init_struct.memory_addr = (uint32_t)spi1_send_array; + dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; + dma_init_struct.priority = DMA_PRIORITY_MEDIUM; + dma_init(DMA0, DMA_CH4, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA0, DMA_CH4); + dma_memory_to_memory_disable(DMA0, DMA_CH4); + + /* SPI1 receive dma config:DMA0,DMA_CH3 */ + dma_deinit(DMA0, DMA_CH3); + dma_init_struct.periph_addr = (uint32_t)&SPI_DATA(SPI1); + dma_init_struct.memory_addr = (uint32_t)spi1_receive_array; + dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY; + dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH; + dma_init(DMA0, DMA_CH3, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA0, DMA_CH3); + dma_memory_to_memory_disable(DMA0, DMA_CH3); +} + +/*! + \brief configure the SPI peripheral + \param[in] none + \param[out] none + \retval none +*/ +void spi_config(void) +{ + spi_parameter_struct spi_init_struct; + /* deinitilize SPI and the parameters */ + spi_i2s_deinit(SPI0); + spi_i2s_deinit(SPI1); + spi_struct_para_init(&spi_init_struct); + + /* SPI0 parameter config */ + spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_init_struct.device_mode = SPI_MASTER; + spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT; + spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE; + spi_init_struct.nss = SPI_NSS_HARD; + spi_init_struct.prescale = SPI_PSC_16; + spi_init_struct.endian = SPI_ENDIAN_MSB; + spi_init(SPI0, &spi_init_struct); + + /* SPI1 parameter config */ + spi_init_struct.device_mode = SPI_SLAVE; + spi_init_struct.nss = SPI_NSS_HARD; + spi_init(SPI1, &spi_init_struct); +} + +/*! + \brief memory compare function + \param[in] src: source data pointer + \param[in] dst: destination data pointer + \param[in] length: the compare data length + \param[out] none + \retval ErrStatus : ERROR or SUCCESS +*/ +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint8_t length) +{ + while(length--){ + if(*src++ != *dst++) + return ERROR; + } + return SUCCESS; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_nssp_mode/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_nssp_mode/readme.txt new file mode 100644 index 0000000..e42c3aa --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_nssp_mode/readme.txt @@ -0,0 +1,42 @@ +/*! + \file readme.txt + \brief description of the master and slave fullduplex communication with nssp mode + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V, it shows SPI0 and SPI1 fullduplex +communication with nssp mode. After the communicate is complete, if the receive data +equals to send data, LED2 and LED3 turn on, if not, LED2 and LED3 turn off. + + Connect SPI0 NSS PIN(PA4) to SPI1 NSS PIN(PB12) + Connect SPI0 SCK PIN(PA5) to SPI1 SCK PIN(PB13) + Connect SPI0 MISO PIN(PA6) to SPI1 MISO PIN(PB14) + Connect SPI0 MOSI PIN(PA7) to SPI1 MOSI PIN(PB15) \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_polling/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_polling/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_polling/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_polling/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_polling/main.c new file mode 100644 index 0000000..379d4a9 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_polling/main.c @@ -0,0 +1,179 @@ +/*! + \file main.c + \brief SPI fullduplex communication use polling mode + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" + +#define ARRAYSIZE 10 + +uint32_t send_n = 0, receive_n = 0; +uint8_t spi0_send_array[ARRAYSIZE] = {0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA}; +uint8_t spi2_send_array[ARRAYSIZE] = {0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA}; +uint8_t spi0_receive_array[ARRAYSIZE]; +uint8_t spi2_receive_array[ARRAYSIZE]; +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint8_t length); + +void rcu_config(void); +void gpio_config(void); +void spi_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* initialize the LEDs */ + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + /* peripheral clock enable */ + rcu_config(); + /* GPIO configure */ + gpio_config(); + /* SPI configure */ + spi_config(); + /* SPI enable */ + spi_enable(SPI2); + spi_enable(SPI0); + + /* wait for transmit complete */ + while(send_n < ARRAYSIZE){ + while(RESET == spi_i2s_flag_get(SPI2, SPI_FLAG_TBE)); + spi_i2s_data_transmit(SPI2, spi2_send_array[send_n]); + while(RESET == spi_i2s_flag_get(SPI0, SPI_FLAG_TBE)); + spi_i2s_data_transmit(SPI0, spi0_send_array[send_n++]); + while(RESET == spi_i2s_flag_get(SPI2, SPI_FLAG_RBNE)); + spi2_receive_array[receive_n] = spi_i2s_data_receive(SPI2); + while(RESET == spi_i2s_flag_get(SPI0, SPI_FLAG_RBNE)); + spi0_receive_array[receive_n++] = spi_i2s_data_receive(SPI0); + } + + /* compare receive data with send data */ + if(ERROR != memory_compare(spi2_receive_array, spi0_send_array, ARRAYSIZE)){ + gd_eval_led_on(LED2); + }else{ + gd_eval_led_off(LED2); + } + + if(ERROR != memory_compare(spi0_receive_array, spi2_send_array, ARRAYSIZE)){ + gd_eval_led_on(LED3); + }else{ + gd_eval_led_off(LED3); + } + + while(1); +} + +/*! + \brief configure different peripheral clocks + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOC); + rcu_periph_clock_enable(RCU_AF); + rcu_periph_clock_enable(RCU_SPI0); + rcu_periph_clock_enable(RCU_SPI2); +} + +/*! + \brief configure the GPIO peripheral + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* SPI0 GPIO config:SCK/PA5, MISO/PA6, MOSI/PA7 */ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_7); + gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6); + + /* SPI2 GPIO config:SCK/PC10, MISO/PC11, MOSI/PC12 */ + gpio_pin_remap_config(GPIO_SPI2_REMAP, ENABLE); + gpio_init(GPIOC, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_10 | GPIO_PIN_12); + gpio_init(GPIOC, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_11); +} + +/*! + \brief configure the SPI peripheral + \param[in] none + \param[out] none + \retval none +*/ +void spi_config(void) +{ + spi_parameter_struct spi_init_struct; + /* deinitilize SPI and the parameters */ + spi_i2s_deinit(SPI0); + spi_i2s_deinit(SPI2); + spi_struct_para_init(&spi_init_struct); + + /* SPI0 parameter config */ + spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_init_struct.device_mode = SPI_MASTER; + spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT; + spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; + spi_init_struct.nss = SPI_NSS_SOFT; + spi_init_struct.prescale = SPI_PSC_8; + spi_init_struct.endian = SPI_ENDIAN_MSB; + spi_init(SPI0, &spi_init_struct); + + /* SPI2 parameter config */ + spi_init_struct.device_mode = SPI_SLAVE; + spi_init_struct.nss = SPI_NSS_SOFT; + spi_init(SPI2, &spi_init_struct); + +} + +/*! + \brief memory compare function + \param[in] src: source data pointer + \param[in] dst: destination data pointer + \param[in] length: the compare data length + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint8_t length) +{ + while(length--){ + if(*src++ != *dst++) + return ERROR; + } + return SUCCESS; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_polling/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_polling/readme.txt new file mode 100644 index 0000000..4e38401 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_polling/readme.txt @@ -0,0 +1,41 @@ +/*! + \file readme.txt + \brief description of the master and slave fullduplex communication use polling demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it shows SPI0 and SPI2 fullduplex +communication use polling mode.After the communicate is complete,if receive data is equal +to send data, led2 and led3 turn on, if not led2 and led3 turn off. + + Connect SPI0 SCK PIN(PA5) TO SPI2 SCK PIN(PC10). + Connect SPI0 MISO PIN(PA6) TO SPI2 MISO PIN(PC11). + Connect SPI0 MOSI PIN(PA7) TO SPI2 MOSI PIN(PC12). \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_ti_mode/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_ti_mode/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_ti_mode/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_ti_mode/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_ti_mode/main.c new file mode 100644 index 0000000..5a2e629 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_ti_mode/main.c @@ -0,0 +1,257 @@ +/*! + \file main.c + \brief SPI master and slave fullduplex communication with ti mode + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" + +#define ARRAYSIZE 10 + +uint8_t spi0_send_array[ARRAYSIZE] = {0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA}; +uint8_t spi1_send_array[ARRAYSIZE] = {0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA}; +uint8_t spi0_receive_array[ARRAYSIZE]; +uint8_t spi1_receive_array[ARRAYSIZE]; +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint8_t length); +uint32_t send_n = 0, receive_n = 0; + +void rcu_config(void); +void gpio_config(void); +void dma_config(void); +void spi_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* initialize the LEDs */ + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + + /* peripheral clock enable */ + rcu_config(); + /* GPIO config */ + gpio_config(); + /* DMA config */ + dma_config(); + /* SPI config */ + spi_config(); + + /* SPI ti mode enable */ + spi_ti_mode_enable(SPI1); + spi_ti_mode_enable(SPI0); + + /* SPI enable */ + spi_enable(SPI1); + spi_enable(SPI0); + + /* DMA channel enable */ + dma_channel_enable(DMA0, DMA_CH1); + dma_channel_enable(DMA0, DMA_CH2); + dma_channel_enable(DMA0, DMA_CH3); + dma_channel_enable(DMA0, DMA_CH4); + + /* SPI DMA enable */ + spi_dma_enable(SPI1, SPI_DMA_TRANSMIT); + spi_dma_enable(SPI1, SPI_DMA_RECEIVE); + spi_dma_enable(SPI0, SPI_DMA_TRANSMIT); + spi_dma_enable(SPI0, SPI_DMA_RECEIVE); + + /* wait dma transmit complete */ + while(!dma_flag_get(DMA0,DMA_CH2,DMA_FLAG_FTF)); + while(!dma_flag_get(DMA0,DMA_CH4,DMA_FLAG_FTF)); + while(!dma_flag_get(DMA0,DMA_CH3,DMA_FLAG_FTF)); + while(!dma_flag_get(DMA0,DMA_CH1,DMA_FLAG_FTF)); + + /* compare receive data with send data */ + if(ERROR != memory_compare(spi1_receive_array, spi0_send_array, ARRAYSIZE)){ + gd_eval_led_on(LED2); + }else{ + gd_eval_led_off(LED2); + } + if(ERROR != memory_compare(spi0_receive_array, spi1_send_array, ARRAYSIZE)){ + gd_eval_led_on(LED3); + }else{ + gd_eval_led_off(LED3); + } + + while(1); +} + +/*! + \brief configure different peripheral clocks + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_DMA0); + rcu_periph_clock_enable(RCU_SPI0); + rcu_periph_clock_enable(RCU_SPI1); +} + +/*! + \brief configure the GPIO peripheral + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* SPI0 GPIO config: NSS/PA4, SCK/PA5, MOSI/PA7 */ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_7); + /* SPI0 GPIO config: MISO/PA6 */ + gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6); + + /* SPI1 GPIO config: NSS/PB12, SCK/PB13, MOSI/PB15 */ + gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_12 | GPIO_PIN_13 |GPIO_PIN_15); + /* SPI1 GPIO config: MISO/PB14 */ + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_14); +} + +/*! + \brief configure the DMA peripheral + \param[in] none + \param[out] none + \retval none +*/ +void dma_config(void) +{ + dma_parameter_struct dma_init_struct; + + /* SPI0 transmit dma config:DMA0,DMA_CH2 */ + dma_deinit(DMA0, DMA_CH2); + dma_struct_para_init(&dma_init_struct); + + dma_init_struct.periph_addr = (uint32_t)&SPI_DATA(SPI0); + dma_init_struct.memory_addr = (uint32_t)spi0_send_array; + dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; + dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; + dma_init_struct.priority = DMA_PRIORITY_LOW; + dma_init_struct.number = ARRAYSIZE; + dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_init(DMA0, DMA_CH2, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA0, DMA_CH2); + dma_memory_to_memory_disable(DMA0, DMA_CH2); + + /* SPI0 receive dma config:DMA0,DMA_CH1 */ + dma_deinit(DMA0, DMA_CH1); + dma_init_struct.periph_addr = (uint32_t)&SPI_DATA(SPI0); + dma_init_struct.memory_addr = (uint32_t)spi0_receive_array; + dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY; + dma_init_struct.priority = DMA_PRIORITY_HIGH; + dma_init(DMA0, DMA_CH1, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA0, DMA_CH1); + dma_memory_to_memory_disable(DMA0, DMA_CH1); + + /* SPI1 transmit dma config:DMA0,DMA_CH4 */ + dma_deinit(DMA0, DMA_CH4); + dma_init_struct.periph_addr = (uint32_t)&SPI_DATA(SPI1); + dma_init_struct.memory_addr = (uint32_t)spi1_send_array; + dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; + dma_init_struct.priority = DMA_PRIORITY_MEDIUM; + dma_init(DMA0, DMA_CH4, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA0, DMA_CH4); + dma_memory_to_memory_disable(DMA0, DMA_CH4); + + /* SPI1 receive dma config:DMA0,DMA_CH3 */ + dma_deinit(DMA0, DMA_CH3); + dma_init_struct.periph_addr = (uint32_t)&SPI_DATA(SPI1); + dma_init_struct.memory_addr = (uint32_t)spi1_receive_array; + dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY; + dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH; + dma_init(DMA0, DMA_CH3, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA0, DMA_CH3); + dma_memory_to_memory_disable(DMA0, DMA_CH3); +} + +/*! + \brief configure the SPI peripheral + \param[in] none + \param[out] none + \retval none +*/ +void spi_config(void) +{ + spi_parameter_struct spi_init_struct; + /* deinitilize SPI and the parameters */ + spi_i2s_deinit(SPI0); + spi_i2s_deinit(SPI1); + spi_struct_para_init(&spi_init_struct); + + /* SPI0 parameter config */ + spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_init_struct.device_mode = SPI_MASTER; + spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT; + spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; + spi_init_struct.nss = SPI_NSS_HARD; + spi_init_struct.prescale = SPI_PSC_16; + spi_init_struct.endian = SPI_ENDIAN_MSB; + spi_init(SPI0, &spi_init_struct); + + /* SPI1 parameter config */ + spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_init_struct.device_mode = SPI_SLAVE; + spi_init_struct.nss = SPI_NSS_HARD; + spi_init_struct.prescale = SPI_PSC_16; + spi_init(SPI1, &spi_init_struct); +} + +/*! + \brief memory compare function + \param[in] src: source data pointer + \param[in] dst: destination data pointer + \param[in] length: the compare data length + \param[out] none + \retval ErrStatus : ERROR or SUCCESS +*/ +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint8_t length) +{ + while(length--){ + if(*src++ != *dst++) + return ERROR; + } + return SUCCESS; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_ti_mode/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_ti_mode/readme.txt new file mode 100644 index 0000000..8556320 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_slave_fullduplex_ti_mode/readme.txt @@ -0,0 +1,42 @@ +/*! + \file readme.txt + \brief description of the master and slave fullduplex communication with ti mode + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V, it shows SPI0 and SPI1 fullduplex +communication with ti mode. After the communication is complete, if the receive data +equals to the send data, LED1 and LED2 turn on, if not, LED1 and LED2 turn off. + + Connect SPI0 NSS PIN(PA4) to SPI1 NSS PIN(PB12) + Connect SPI0 SCK PIN(PA5) to SPI1 SCK PIN(PB13) + Connect SPI0 MISO PIN(PA6) to SPI1 MISO PIN(PB14) + Connect SPI0 MOSI PIN(PA7) to SPI1 MOSI PIN(PB15) \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_transmit_slave_receive_interrupt/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_transmit_slave_receive_interrupt/gd32vf103_it.c new file mode 100644 index 0000000..7e8241a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_transmit_slave_receive_interrupt/gd32vf103_it.c @@ -0,0 +1,78 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_it.h" + +#define ARRAYSIZE 10 + +extern uint8_t spi0_send_array[]; +extern uint8_t spi2_receive_array[]; +extern uint32_t send_n , receive_n ; + +/*! + \brief this function handles SPI0 Handler exception + \param[in] none + \param[out] none + \retval none +*/ +void SPI0_IRQHandler(void) +{ + if(RESET != spi_i2s_interrupt_flag_get(SPI0, SPI_I2S_INT_FLAG_TBE)){ + /* send data */ + while(RESET == spi_i2s_flag_get(SPI0, SPI_FLAG_TBE)); + spi_i2s_data_transmit(SPI0, spi0_send_array[send_n++]); + + if(ARRAYSIZE == send_n){ + spi_i2s_interrupt_disable(SPI0, SPI_I2S_INT_TBE); + } + } +} + +/*! + \brief this function handles SPI2 Handler exception + \param[in] none + \param[out] none + \retval none +*/ +void SPI2_IRQHandler(void) +{ + /* receive data */ + if(RESET != spi_i2s_interrupt_flag_get(SPI2, SPI_I2S_INT_FLAG_RBNE)){ + spi2_receive_array[receive_n++] = spi_i2s_data_receive(SPI2); + } + + if(ARRAYSIZE == receive_n){ + spi_i2s_interrupt_disable(SPI2, SPI_I2S_INT_RBNE); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_transmit_slave_receive_interrupt/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_transmit_slave_receive_interrupt/gd32vf103_it.h new file mode 100644 index 0000000..4e7fee6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_transmit_slave_receive_interrupt/gd32vf103_it.h @@ -0,0 +1,46 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ +/* SPI0 handle function */ +void SPI0_IRQHandler(void); +/* SPI2 handle function */ +void SPI2_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_transmit_slave_receive_interrupt/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_transmit_slave_receive_interrupt/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_transmit_slave_receive_interrupt/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_transmit_slave_receive_interrupt/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_transmit_slave_receive_interrupt/main.c new file mode 100644 index 0000000..71984ea --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_transmit_slave_receive_interrupt/main.c @@ -0,0 +1,171 @@ +/*! + \file main.c + \brief master send and slave receive data use interrupt mode + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" + +#define ARRAYSIZE 10 +__IO uint32_t send_n = 0, receive_n = 0; +uint8_t spi0_send_array[ARRAYSIZE] = {0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA}; +uint8_t spi2_receive_array[ARRAYSIZE]; +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint8_t length); + +void rcu_config(void); +void gpio_config(void); +void spi_config(void); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* initialize the LED */ + gd_eval_led_init(LED2); + + /* ECLIC configure */ + eclic_global_interrupt_enable(); + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL3_PRIO1); + eclic_irq_enable(SPI0_IRQn,1,0); + eclic_irq_enable(SPI2_IRQn,2,0); + + /* peripheral clock enable */ + rcu_config(); + /* GPIO configure */ + gpio_config(); + /* SPI configure */ + spi_config(); + /* SPI interrupt enable */ + spi_i2s_interrupt_enable(SPI0, SPI_I2S_INT_TBE); + spi_i2s_interrupt_enable(SPI2, SPI_I2S_INT_RBNE); + + /* SPI enable */ + spi_enable(SPI2); + spi_enable(SPI0); + + /* wait transmit complete */ + while(receive_n < ARRAYSIZE); + + /* compare receive data with send data */ + if(memory_compare(spi2_receive_array, spi0_send_array, ARRAYSIZE)){ + gd_eval_led_on(LED2); + }else{ + gd_eval_led_off(LED2); + } + + while(1); + +} + +/*! + \brief configure different peripheral clocks + \param[in] none + \param[out] none + \retval none +*/ +void rcu_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOC); + rcu_periph_clock_enable(RCU_AF); + rcu_periph_clock_enable(RCU_SPI0); + rcu_periph_clock_enable(RCU_SPI2); +} + +/*! + \brief configure the GPIO peripheral + \param[in] none + \param[out] none + \retval none +*/ +void gpio_config(void) +{ + /* SPI0 GPIO config:SCK/PA5, MOSI/PA7 */ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_7); + + /* SPI2 GPIO config:SCK/PC10, MISO/PC11 */ + gpio_pin_remap_config(GPIO_SPI2_REMAP, ENABLE); + gpio_init(GPIOC, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_10 | GPIO_PIN_11); +} + +/*! + \brief configure the SPI peripheral + \param[in] none + \param[out] none + \retval none +*/ +void spi_config(void) +{ + spi_parameter_struct spi_init_struct; + /* deinitilize SPI and the parameters */ + spi_i2s_deinit(SPI0); + spi_i2s_deinit(SPI2); + spi_struct_para_init(&spi_init_struct); + + /* configure SPI0 parameter */ + spi_init_struct.trans_mode = SPI_TRANSMODE_BDTRANSMIT; + spi_init_struct.device_mode = SPI_MASTER; + spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT; + spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; + spi_init_struct.nss = SPI_NSS_SOFT; + spi_init_struct.prescale = SPI_PSC_8; + spi_init_struct.endian = SPI_ENDIAN_MSB; + spi_init(SPI0, &spi_init_struct); + + /* configure SPI2 parameter */ + spi_init_struct.trans_mode = SPI_TRANSMODE_BDRECEIVE; + spi_init_struct.device_mode = SPI_SLAVE; + spi_init_struct.nss = SPI_NSS_SOFT; + spi_init(SPI2, &spi_init_struct); + +} + +/*! + \brief memory compare function + \param[in] src: source data pointer + \param[in] dst: destination data pointer + \param[in] length: the compare data length + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint8_t length) +{ + while(length--){ + if(*src++ != *dst++) + return ERROR; + } + return SUCCESS; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_transmit_slave_receive_interrupt/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_transmit_slave_receive_interrupt/readme.txt new file mode 100644 index 0000000..f65a606 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/SPI/SPI_master_transmit_slave_receive_interrupt/readme.txt @@ -0,0 +1,41 @@ +/*! + \file readme.txt + \brief description of the master transmit and slave receive through interrupt demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it shows master send data and +slave receive data use intterupt mode. + After the communicate is complete,if receive data is equal to send data,led2 turns +on,if not led2 turns off. + + Connect SPI0 SCK PIN(PA5) to SPI2 SCK PIN(PC10). + Connect SPI0 MOSI PIN(PA7) to SPI2 MISO PIN(PC11). \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_6-steps/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_6-steps/gd32vf103_it.c new file mode 100644 index 0000000..1107826 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_6-steps/gd32vf103_it.c @@ -0,0 +1,167 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_it.h" +#include "systick.h" + +__IO uint32_t step = 1; + + +/*! + \brief this function handles TIMER0 interrupt request + \param[in] none + \param[out] none + \retval none +*/ +void TIMER0_TRG_CMT_IRQHandler(void) +{ + /* clear TIMER interrupt flag */ + timer_interrupt_flag_clear(TIMER0,TIMER_INT_CMT); + + switch(step){ + /* next step: step 2 configuration .A-C` breakover---------------------------- */ + case 1: + /* channel0 configuration */ + timer_channel_output_mode_config(TIMER0, TIMER_CH_0, TIMER_OC_MODE_PWM0); + timer_channel_output_state_config(TIMER0, TIMER_CH_0, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_0, TIMER_CCXN_DISABLE); + + /* channel1 configuration */ + timer_channel_output_state_config(TIMER0, TIMER_CH_1, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_1, TIMER_CCXN_DISABLE); + + /* channel2 configuration */ + timer_channel_output_mode_config(TIMER0, TIMER_CH_2, TIMER_OC_MODE_PWM0); + timer_channel_output_state_config(TIMER0, TIMER_CH_2, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_2, TIMER_CCXN_ENABLE); + + step++; + break; + + /* next step: step 3 configuration .B-C` breakover---------------------------- */ + case 2: + /* channel0 configuration */ + timer_channel_output_state_config(TIMER0, TIMER_CH_0, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_0, TIMER_CCXN_DISABLE); + + /* channel1 configuration */ + timer_channel_output_mode_config(TIMER0, TIMER_CH_1, TIMER_OC_MODE_PWM0); + timer_channel_output_state_config(TIMER0, TIMER_CH_1, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_1, TIMER_CCXN_DISABLE); + + /* channel2 configuration */ + timer_channel_output_mode_config(TIMER0, TIMER_CH_2, TIMER_OC_MODE_PWM0); + timer_channel_output_state_config(TIMER0, TIMER_CH_2, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_2, TIMER_CCXN_ENABLE); + + step++; + break; + + /* next step: step 4 configuration .B-A` breakover---------------------------- */ + case 3: + /* channel0 configuration */ + timer_channel_output_mode_config(TIMER0, TIMER_CH_0, TIMER_OC_MODE_PWM0); + timer_channel_output_state_config(TIMER0, TIMER_CH_0, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_0, TIMER_CCXN_ENABLE); + + /* channel1 configuration */ + timer_channel_output_mode_config(TIMER0, TIMER_CH_1, TIMER_OC_MODE_PWM0); + timer_channel_output_state_config(TIMER0, TIMER_CH_1, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_1, TIMER_CCXN_DISABLE); + + /* channel2 configuration */ + timer_channel_output_state_config(TIMER0, TIMER_CH_2, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_2, TIMER_CCXN_DISABLE); + + step++; + break; + + /* next step: step 5 configuration .C-A` breakover---------------------------- */ + case 4: + /* channel0 configuration */ + timer_channel_output_mode_config(TIMER0, TIMER_CH_0, TIMER_OC_MODE_PWM0); + timer_channel_output_state_config(TIMER0, TIMER_CH_0, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_0, TIMER_CCXN_ENABLE); + + /* channel1 configuration */ + timer_channel_output_state_config(TIMER0, TIMER_CH_1, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_1, TIMER_CCXN_DISABLE); + + /* channel2 configuration */ + timer_channel_output_mode_config(TIMER0, TIMER_CH_2, TIMER_OC_MODE_PWM0); + timer_channel_output_state_config(TIMER0, TIMER_CH_2, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_2, TIMER_CCXN_DISABLE); + + step++; + break; + + /* next step: step 6 configuration .C-B` breakover---------------------------- */ + case 5: + /* channel0 configuration */ + timer_channel_output_state_config(TIMER0, TIMER_CH_0, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_0, TIMER_CCXN_DISABLE); + + /* channel1 configuration */ + timer_channel_output_mode_config(TIMER0, TIMER_CH_1, TIMER_OC_MODE_PWM0); + timer_channel_output_state_config(TIMER0, TIMER_CH_1, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_1, TIMER_CCXN_ENABLE); + + /* channel2 configuration */ + timer_channel_output_mode_config(TIMER0, TIMER_CH_2, TIMER_OC_MODE_PWM0); + timer_channel_output_state_config(TIMER0, TIMER_CH_2, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_2, TIMER_CCXN_DISABLE); + + step++; + break; + + /* next step: step 1 configuration .A-B` breakover---------------------------- */ + case 6: + /* channel0 configuration */ + timer_channel_output_mode_config(TIMER0, TIMER_CH_0, TIMER_OC_MODE_PWM0); + timer_channel_output_state_config(TIMER0, TIMER_CH_0, TIMER_CCX_ENABLE); + timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_0, TIMER_CCXN_DISABLE); + + /* channel1 configuration */ + timer_channel_output_mode_config(TIMER0, TIMER_CH_1, TIMER_OC_MODE_PWM0); + timer_channel_output_state_config(TIMER0, TIMER_CH_1, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_1, TIMER_CCXN_ENABLE); + + /* channel2 configuration */ + timer_channel_output_state_config(TIMER0, TIMER_CH_2, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_2, TIMER_CCXN_DISABLE); + + step = 1; + break; + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_6-steps/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_6-steps/gd32vf103_it.h new file mode 100644 index 0000000..6cfa6cc --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_6-steps/gd32vf103_it.h @@ -0,0 +1,45 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* Core Timer handle function */ +void clic_mtip_handler(void); +/*TIMER0 handle function*/ +void TIMER0_BRK_UP_TRG_COM_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_6-steps/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_6-steps/main.c new file mode 100644 index 0000000..6aac1a2 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_6-steps/main.c @@ -0,0 +1,175 @@ +/*! + \file main.c + \brief TIMER0 6-steps demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" +#include "systick.h" +#include + +/* configure the GPIO ports */ +void gpio_config(void); +/* configure the GPIO ports */ +void timer_config(void); + +/** + \brief configure the GPIO ports + \param[in] none + \param[out] none + \retval none + */ +void gpio_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_AF); + + /*configure PA8/PA9/PA10(TIMER0/CH0/CH1/CH2) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_8); + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9); + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_10); + + /*configure PB13/PB14/PB15(TIMER0/CH0N/CH1N/CH2N) as alternate function*/ + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13); + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_14); + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_15); + + /*configure PB12(TIMER0 BKIN) as alternate function*/ + gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_12); +} + +/** + \brief configure the TIMER peripheral + \param[in] none + \param[out] none + \retval none + */ +void timer_config(void) +{ + /* ----------------------------------------------------------------------- + TIMER0 configuration: + generate 3 complementary PWM signal. + TIMER0CLK is fixed to systemcoreclock, the TIMER0 prescaler is equal to 108 + so the TIMER0 counter clock used is 1MHz. + insert a dead time equal to (64 + 36) * 2 / systemcoreclock =1.85us + configure the break feature, active at low level, and using the automatic + output enable feature. + use the locking parameters level 0. + ----------------------------------------------------------------------- */ + timer_oc_parameter_struct timer_ocinitpara; + timer_parameter_struct timer_initpara; + timer_break_parameter_struct timer_breakpara; + + rcu_periph_clock_enable(RCU_TIMER0); + + timer_deinit(TIMER0); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + /* TIMER0 configuration */ + timer_initpara.prescaler = 107; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 599; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER0, &timer_initpara); + + /* initialize TIMER channel output parameter struct */ + timer_channel_output_struct_para_init(&timer_ocinitpara); + /* CH0/CH0N, CH1/CH1N and CH2/CH2N configuration in timing mode */ + timer_ocinitpara.outputstate = TIMER_CCX_ENABLE; + timer_ocinitpara.outputnstate = TIMER_CCXN_ENABLE; + timer_ocinitpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocinitpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocinitpara.ocidlestate = TIMER_OC_IDLE_STATE_HIGH; + timer_ocinitpara.ocnidlestate = TIMER_OCN_IDLE_STATE_HIGH; + + timer_channel_output_config(TIMER0, TIMER_CH_0, &timer_ocinitpara); + timer_channel_output_config(TIMER0, TIMER_CH_1, &timer_ocinitpara); + timer_channel_output_config(TIMER0, TIMER_CH_2, &timer_ocinitpara); + + timer_channel_output_pulse_value_config(TIMER0,TIMER_CH_0,299); + timer_channel_output_mode_config(TIMER0, TIMER_CH_0, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_0, TIMER_OC_SHADOW_ENABLE); + + timer_channel_output_pulse_value_config(TIMER0,TIMER_CH_1,299); + timer_channel_output_mode_config(TIMER0, TIMER_CH_1, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_1, TIMER_OC_SHADOW_ENABLE); + + timer_channel_output_pulse_value_config(TIMER0,TIMER_CH_2,299); + timer_channel_output_mode_config(TIMER0, TIMER_CH_2, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_2, TIMER_OC_SHADOW_ENABLE); + + /* initialize TIMER break parameter struct */ + timer_break_struct_para_init(&timer_breakpara); + /* automatic output enable, break, dead time and lock configuration*/ + timer_breakpara.runoffstate = TIMER_ROS_STATE_ENABLE; + timer_breakpara.ideloffstate = TIMER_IOS_STATE_ENABLE ; + timer_breakpara.deadtime = 1; + timer_breakpara.breakpolarity = TIMER_BREAK_POLARITY_LOW; + timer_breakpara.outputautostate = TIMER_OUTAUTO_ENABLE; + timer_breakpara.protectmode = TIMER_CCHP_PROT_OFF; + timer_breakpara.breakstate = TIMER_BREAK_ENABLE; + timer_break_config(TIMER0, &timer_breakpara); + + /* TIMER0 primary output function enable */ + timer_primary_output_config(TIMER0, ENABLE); + + /* TIMER0 channel control update interrupt enable */ + timer_interrupt_enable(TIMER0, TIMER_INT_CMT); + /* TIMER0 break interrupt disable */ + timer_interrupt_disable(TIMER0, TIMER_INT_BRK); + + /* TIMER0 counter enable */ + timer_enable(TIMER0); +} + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + gpio_config(); + eclic_global_interrupt_enable(); + eclic_set_nlbits(ECLIC_GROUP_LEVEL3_PRIO1); + eclic_irq_enable(TIMER0_TRG_CMT_IRQn, 6,1); + timer_config(); + + while(1){ + delay_1ms(10); + timer_event_software_generate(TIMER0,TIMER_EVENT_SRC_CMTG); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_6-steps/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_6-steps/readme.txt new file mode 100644 index 0000000..389c8a5 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_6-steps/readme.txt @@ -0,0 +1,57 @@ +/*! + \file readme.txt + \brief description of the TIMER0 6-steps demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to configure the +TIMER0 peripheral to generate three complementary TIMER0 signals(for BLDC) with dead +time. + + TIMER0CLK is fixed to systemcoreclock, the TIMER0 prescaler is equal to 108 so the +TIMER0 counter clock used is 1MHz. + + Channel change sequence: + AB`->AC`->BC`->BA`->CA`->CB` +step1: 1-0 0-1 0-0 (CH0-CH0N CH1-CH1N CH2-CH2N) +step2: 1-0 0-0 0-1 (CH0-CH0N CH1-CH1N CH2-CH2N) +step3: 0-0 1-0 0-1 (CH0-CH0N CH1-CH1N CH2-CH2N) +step4: 0-1 1-0 0-0 (CH0-CH0N CH1-CH1N CH2-CH2N) +step5: 0-1 0-0 1-0 (CH0-CH0N CH1-CH1N CH2-CH2N) +step6: 0-0 0-1 1-0 (CH0-CH0N CH1-CH1N CH2-CH2N) + + Connect the TIMER0 pins to an oscilloscope to monitor the different waveforms: + - TIMER0_CH0 pin(PA8) + - TIMER0_CH0N pin(PB13) + - TIMER0_CH1 pin(PA9) + - TIMER0_CH1N pin(PB14) + - TIMER0_CH2 pin(PA10) + - TIMER0_CH2N pin(PB15) diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_6-steps/systick.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_6-steps/systick.c new file mode 100644 index 0000000..7e217cd --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_6-steps/systick.c @@ -0,0 +1,58 @@ +/*! + \file systick.c + \brief the systick configuration file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" + + +/*! + \brief delay a time in milliseconds + \param[in] count: count in milliseconds + \param[out] none + \retval none +*/ +void delay_1ms(uint32_t count) +{ + uint64_t start_mtime, delta_mtime; + + // Don't start measuruing until we see an mtime tick + uint64_t tmp = get_timer_value(); + do { + start_mtime = get_timer_value(); + } while (start_mtime == tmp); + + do { + delta_mtime = get_timer_value() - start_mtime; + }while(delta_mtime < (SystemCoreClock/4000.0*count )); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_6-steps/systick.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_6-steps/systick.h new file mode 100644 index 0000000..cb47e4e --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_6-steps/systick.h @@ -0,0 +1,45 @@ +/*! + \file systick.h + \brief the header file of systick + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef SYSTICK_H +#define SYSTICK_H + +#include + +/* configure systick */ +void systick_config(void); +/* delay a time in milliseconds */ +void delay_1ms(uint32_t count); + +#endif /* SYSTICK_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_complementarysignals/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_complementarysignals/main.c new file mode 100644 index 0000000..32afd2a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_complementarysignals/main.c @@ -0,0 +1,147 @@ +/*! + \file main.c + \brief TIMER0 complementary signals demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +/* configure the GPIO ports */ +void gpio_config(void); +/* configure the TIMER peripheral */ +void timer_config(void); + +/** + \brief configure the GPIO ports + \param[in] none + \param[out] none + \retval none + */ +void gpio_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_AF); + + /*configure PA8/PA9/PA10(TIMER0/CH0/CH1/CH2) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_8); + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9); + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_10); + + /*configure PB13/PB14/PB15(TIMER0/CH0N/CH1N/CH2N) as alternate function*/ + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13); + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_14); + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_15); +} + +/** + \brief configure the TIMER peripheral + \param[in] none + \param[out] none + \retval none + */ +void timer_config(void) +{ +/* ----------------------------------------------------------------------- + TIMER0 configuration to: + generate 3 complementary PWM signals with 3 different duty cycles: + TIMER0CLK is fixed to systemcoreclock, the TIMER0 prescaler is equal to 5400 so the + TIMER0 counter clock used is 20KHz and the PWM frequency is 1.25Hz. + the three duty cycles are computed as the following description: + the channel 0 duty cycle is set to 25% so channel 1N is set to 75%. + the channel 1 duty cycle is set to 50% so channel 2N is set to 50%. + the channel 2 duty cycle is set to 75% so channel 3N is set to 25%. + ----------------------------------------------------------------------- */ + timer_oc_parameter_struct timer_ocinitpara; + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER0); + + timer_deinit(TIMER0); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + /* TIMER0 configuration */ + timer_initpara.prescaler = 5399; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 15999; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER0, &timer_initpara); + + /* initialize TIMER channel output parameter struct */ + timer_channel_output_struct_para_init(&timer_ocinitpara); + /* CH1, CH2 and CH3 configuration in PWM mode */ + timer_ocinitpara.outputstate = TIMER_CCX_ENABLE; + timer_ocinitpara.outputnstate = TIMER_CCXN_ENABLE; + timer_ocinitpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocinitpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocinitpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + timer_ocinitpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + + timer_channel_output_config(TIMER0, TIMER_CH_0, &timer_ocinitpara); + timer_channel_output_config(TIMER0, TIMER_CH_1, &timer_ocinitpara); + timer_channel_output_config(TIMER0, TIMER_CH_2, &timer_ocinitpara); + + timer_channel_output_pulse_value_config(TIMER0,TIMER_CH_0,3999); + timer_channel_output_mode_config(TIMER0, TIMER_CH_0, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); + + timer_channel_output_pulse_value_config(TIMER0,TIMER_CH_1,7999); + timer_channel_output_mode_config(TIMER0, TIMER_CH_1, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_1, TIMER_OC_SHADOW_DISABLE); + + timer_channel_output_pulse_value_config(TIMER0,TIMER_CH_2,11999); + timer_channel_output_mode_config(TIMER0, TIMER_CH_2, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_2, TIMER_OC_SHADOW_DISABLE); + + timer_primary_output_config(TIMER0, ENABLE); + + /* auto-reload preload enable */ + timer_auto_reload_shadow_enable(TIMER0); + timer_enable(TIMER0); +} + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + gpio_config(); + timer_config(); + + while (1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_complementarysignals/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_complementarysignals/readme.txt new file mode 100644 index 0000000..9397113 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_complementarysignals/readme.txt @@ -0,0 +1,51 @@ +/*! + \file readme.txt + \brief description of the TIMER0 complementary signals demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to configure the +TIMER0 peripheral to generate three complementary TIMER0 signals. TIMER0CLK is fixed +to systemcoreclock, the TIMER0 prescaler is equal to 5400, so the TIMER0 counter clock +used is 20KHz and the PWM frequency is 1.25Hz. + + The Three duty cycles are computed as the following description: + The channel 0 duty cycle is set to 25% so channel 0N is set to 75%. + The channel 1 duty cycle is set to 50% so channel 1N is set to 50%. + The channel 2 duty cycle is set to 75% so channel 2N is set to 25%. + + Connect the TIMER0 pins to an oscilloscope to monitor the different waveforms: + - TIMER0_CH0 pin(PA8) + - TIMER0_CH0N pin(PB13) + - TIMER0_CH1 pin(PA9) + - TIMER0_CH1N pin(PB14) + - TIMER0_CH2 pin(PA10) + - TIMER0_CH2N pin(PB15) diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_deadtime_break/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_deadtime_break/main.c new file mode 100644 index 0000000..45e4e18 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_deadtime_break/main.c @@ -0,0 +1,157 @@ +/*! + \file main.c + \brief TIMER0 deadtime break demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +/* configure the GPIO ports */ +void gpio_config(void); +/* configure the TIMER peripheral */ +void timer_config(void); + +/** + \brief configure the GPIO ports + \param[in] none + \param[out] none + \retval none + */ +void gpio_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_AF); + + /*configure PA8(TIMER0 CH0) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_8); + + /*configure PB13(TIMER0 CH0N) as alternate function*/ + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13); + + /*configure PB12(TIMER0 BKIN) as alternate function*/ + gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_12); +} + +/** + \brief configure the TIMER peripheral + \param[in] none + \param[out] none + \retval none + */ +void timer_config(void) +{ + /* ----------------------------------------------------------------------- + TIMER0 configuration: + generate 1 complementary PWM signal. + TIMER0CLK is fixed to systemcoreclock, the TIMER0 prescaler is equal to 108 so the + TIMER0 counter clock used is 1MHz. + the duty cycle is computed as the following description: + the channel 0 duty cycle is set to 25% so channel 0N is set to 75%. + + insert a dead time equal to ((32+31)*16*4)/systemcoreclock = 37.3us + + configure the break feature, active at high level, and using the automatic + output enable feature. + + use the locking parameters level1. + ----------------------------------------------------------------------- */ + timer_oc_parameter_struct timer_ocinitpara; + timer_parameter_struct timer_initpara; + timer_break_parameter_struct timer_breakpara; + + rcu_periph_clock_enable(RCU_TIMER0); + + timer_deinit(TIMER0); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + /* TIMER0 configuration */ + timer_initpara.prescaler = 107; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 1599; + timer_initpara.clockdivision = TIMER_CKDIV_DIV4; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER0, &timer_initpara); + + /* initialize TIMER channel output parameter struct */ + timer_channel_output_struct_para_init(&timer_ocinitpara); + /* CH0/CH0N configuration in PWM mode0 */ + timer_ocinitpara.outputstate = TIMER_CCX_ENABLE; + timer_ocinitpara.outputnstate = TIMER_CCXN_ENABLE; + timer_ocinitpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocinitpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocinitpara.ocidlestate = TIMER_OC_IDLE_STATE_HIGH; + timer_ocinitpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + + timer_channel_output_config(TIMER0, TIMER_CH_0, &timer_ocinitpara); + + timer_channel_output_pulse_value_config(TIMER0,TIMER_CH_0,399); + timer_channel_output_mode_config(TIMER0, TIMER_CH_0, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); + + /* configure TIMER break function */ + timer_break_struct_para_init(&timer_breakpara); + /* automatic output enable, break, dead time and lock configuration*/ + timer_breakpara.runoffstate = TIMER_ROS_STATE_DISABLE; + timer_breakpara.ideloffstate = TIMER_IOS_STATE_DISABLE ; + timer_breakpara.deadtime = 255; + timer_breakpara.breakpolarity = TIMER_BREAK_POLARITY_LOW; + timer_breakpara.outputautostate = TIMER_OUTAUTO_ENABLE; + timer_breakpara.protectmode = TIMER_CCHP_PROT_0; + timer_breakpara.breakstate = TIMER_BREAK_ENABLE; + timer_break_config(TIMER0, &timer_breakpara); + + /* TIMER0 primary output function enable */ + timer_primary_output_config(TIMER0, ENABLE); + + /* auto-reload preload enable */ + timer_auto_reload_shadow_enable(TIMER0); + + /* TIMER0 counter enable */ + timer_enable(TIMER0); +} + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + gpio_config(); + timer_config(); + + while (1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_deadtime_break/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_deadtime_break/readme.txt new file mode 100644 index 0000000..7889961 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_deadtime_break/readme.txt @@ -0,0 +1,58 @@ +/*! + \file readme.txt + \brief description of the TIMER0 deadtime break demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to configure the +TIMER0 peripheral to generate complementary signals, to insert a defined dead time +value, to use the break feature and to lock the desired parameters. + + TIMER0CLK is fixed to systemcoreclock, the TIMER0 prescaler is equal to 107 ,so +the TIMER0 counter clock used is 1MHz. + + The duty cycle is computed as the following description: +the channel 0(PA8) duty cycle is set to 25% so channel 0N(PB13) is set to 75%. + + Insert a dead time equal to ((32 + 31) * 16 * 4) / systemcoreclock = 37.3us + + Configure the break feature, active at Low level(with GND), and using the automatic +output enable feature. + + Use the Locking parameters level1. + + Connect the TIMER0 pins to an oscilloscope to monitor the different waveforms: + - TIMER0_CH0 pin (PA8) + - TIMER0_CH0N pin (PB13) + + Connect one key's pin (PB14 for example) and TIMER0_BRKIN pin PB12 with Dupont +line. Press the key (User Key for example), the break of the wave can be observed +through the oscilloscope. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_dma/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_dma/main.c new file mode 100644 index 0000000..cb4badd --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_dma/main.c @@ -0,0 +1,177 @@ +/*! + \file main.c + \brief TIMER0 dma demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +#define TIMER0_CH0CV_OFFSET (0x34) +#define TIMER0_CH0CV_ADDR (TIMER0 + TIMER0_CH0CV_OFFSET) +#define TRANSFER_NUM (3) +uint16_t buffer[TRANSFER_NUM] = {249,499,749}; + +/* configure the GPIO ports */ +void gpio_config(void); +/* configure the TIMER peripheral */ +void timer_config(void); +/* configure the DMA peripheral */ +void dma_config(void); + +/** + \brief configure the GPIO ports + \param[in] none + \param[out] none + \retval none + */ +void gpio_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_AF); + + /*configure PA8(TIMER0 CH0) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_8); +} + +/** + \brief configure the DMA peripheral + \param[in] none + \param[out] none + \retval none + */ +void dma_config(void) +{ + dma_parameter_struct dma_init_struct; + + /* enable DMA clock */ + rcu_periph_clock_enable(RCU_DMA0); + + /* initialize DMA channel 4 */ + dma_deinit(DMA0, DMA_CH4); + + /* DMA channel 4 initialize */ + dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; + dma_init_struct.memory_addr = (uint32_t)buffer; + dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_init_struct.memory_width = DMA_MEMORY_WIDTH_16BIT; + dma_init_struct.number = TRANSFER_NUM; + dma_init_struct.periph_addr = (uint32_t)TIMER0_CH0CV_ADDR; + dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_16BIT; + dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH; + dma_init(DMA0, DMA_CH4, &dma_init_struct); + + /* DMA0 channel 4 mode configuration */ + dma_circulation_enable(DMA0, DMA_CH4); + dma_memory_to_memory_disable(DMA0, DMA_CH4); + + /* enable DMA channel5 */ + dma_channel_enable(DMA0, DMA_CH4); +} + +/** + \brief configure the TIMER peripheral + \param[in] none + \param[out] none + \retval none + */ +void timer_config(void) +{ + /* TIMER0 DMA Transfer example ------------------------------------------------- + TIMER0CLK = 108 MHz, Prescaler = 108 + TIMER0 counter clock = systemcoreclock/108 = 1MHz. + + the objective is to configure TIMER0 channel 1 to generate PWM + signal with a frequency equal to 1KHz and a variable duty cycle(25%, 50%, 75%) that + is changed by the DMA after a specific number of update DMA request. + + the number of this repetitive requests is defined by the TIMER0 repetition counter, + each 2 update requests, the TIMER0 Channel 0 duty cycle changes to the next new + value defined by the buffer . + -----------------------------------------------------------------------------*/ + timer_oc_parameter_struct timer_ocinitpara; + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER0); + + timer_deinit(TIMER0); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + /* TIMER0 configuration */ + timer_initpara.prescaler = 107; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 999; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 1; + timer_init(TIMER0, &timer_initpara); + + /* initialize TIMER channel output parameter struct */ + timer_channel_output_struct_para_init(&timer_ocinitpara); + /* CH0 configuration in PWM1 mode */ + timer_ocinitpara.outputstate = TIMER_CCX_ENABLE; + timer_ocinitpara.outputnstate = TIMER_CCXN_DISABLE; + timer_ocinitpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocinitpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocinitpara.ocidlestate = TIMER_OC_IDLE_STATE_HIGH; + timer_ocinitpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + timer_channel_output_config(TIMER0, TIMER_CH_0, &timer_ocinitpara); + + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_0, buffer[0]); + timer_channel_output_mode_config(TIMER0, TIMER_CH_0, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); + + /* TIMER0 primary output enable */ + timer_primary_output_config(TIMER0, ENABLE); + /* TIMER0 update DMA request enable */ + timer_dma_enable(TIMER0, TIMER_DMA_UPD); + /* auto-reload preload enable */ + timer_auto_reload_shadow_enable(TIMER0); + + /* TIMER0 counter enable */ + timer_enable(TIMER0); +} + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + gpio_config(); + dma_config(); + timer_config(); + + while (1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_dma/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_dma/readme.txt new file mode 100644 index 0000000..21df2d9 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_dma/readme.txt @@ -0,0 +1,48 @@ +/*! + \file readme.txt + \brief description of the TIMER0 DMA demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to +use DMA with TIMER0 update request to transfer data from memory +to TIMER0 capture compare register 0. + + TIMER0CLK is fixed to systemcoreclock, the TIMER0 prescaler is equal to 108 +so the TIMER0 counter clock used is 1MHz. + + The objective is to configure TIMER0 channel 0(PA8) to generate PWM signal with +a frequency equal to 1KHz and a variable duty cycle(25%,50%,75%) that is changed +by the DMA after a specific number of Update DMA request. + + The number of this repetitive requests is defined by the TIMER0 repetition counter, +each 2 update requests, the TIMER0 Channel 0 duty cycle changes to the next new +value defined by the buffer. \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_dma_burst/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_dma_burst/main.c new file mode 100644 index 0000000..8de8ad5 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_dma_burst/main.c @@ -0,0 +1,210 @@ +/*! + \file main.c + \brief TIMER0 dma burst demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +#define TIMER0_DMATB_OFFSET (0x4C) /* TIMER0_DMATB address offset */ +#define TIMER0_DMATB_ADDR (TIMER0 + TIMER0_DMATB_OFFSET) /* TIMER0_DMATB address */ +#define TRANSFER_NUM (8) + +uint16_t buffer[TRANSFER_NUM] = {99,199,299,399,499,599,699,799}; + +/* configure the GPIO ports */ +void gpio_config(void); +/* configure the TIMER peripheral */ +void timer_config(void); +/* configure the DMA peripheral */ +void dma_config(void); + +/** + \brief configure the GPIO ports + \param[in] none + \param[out] none + \retval none + */ +void gpio_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_AF); + + /*configure PA8(TIMER0 CH0) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_8); + + /*configure PA9(TIMER0 CH1) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9); + + /*configure PA10(TIMER0 CH2) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_10); + + /*configure PA11(TIMER0 CH3) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_11); +} + +/** + \brief configure the DMA peripheral + \param[in] none + \param[out] none + \retval none + */ +void dma_config(void) +{ + dma_parameter_struct dma_init_struct; + + /* enable DMA clock */ + rcu_periph_clock_enable(RCU_DMA0); + + /* initialize DMA channel5 */ + dma_deinit(DMA0, DMA_CH4); + + /* DMA channel 4 initialize */ + dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; + dma_init_struct.memory_addr = (uint32_t)buffer; + dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_init_struct.memory_width = DMA_MEMORY_WIDTH_16BIT; + dma_init_struct.number = TRANSFER_NUM; + dma_init_struct.periph_addr = (uint32_t)TIMER0_DMATB_ADDR; + dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_16BIT; + dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH; + dma_init(DMA0, DMA_CH4, &dma_init_struct); + + /* DMA0 channel 4 mode configuration */ + dma_circulation_enable(DMA0, DMA_CH4); + dma_memory_to_memory_disable(DMA0, DMA_CH4); + + /* enable DMA channel4 */ + dma_channel_enable(DMA0, DMA_CH4); +} + +/** + \brief configure the TIMER peripheral + \param[in] none + \param[out] none + \retval none + */ +void timer_config(void) +{ + /* TIMER0 DMA transfer example ------------------------------------------------- + TIMER0CLK = 108 MHz, prescaler = 108 + TIMER0 counter clock = systemcoreclock/108 = 1MHz. + + The objective is to configure TIMER0 channel 0~3(PA8~PA11) to generate PWM signal. + capture compare register 0~3 are to be updated twice per circle.On the first update + DMA request, data1 is transferred to CH0CV, data2 is transferred to CH1CV, data3 is + transferred to CH2CV, data4 is transferred to CH3CV and duty cycle(10%, 20%, 30%, 40%). + On the second update DMA request, data5 is transferred to CH0CV, data6 is transferred + to CH1CV, data7 is transferred to CH2CV, data8 is transferred to CH3CV and duty cycle + (50%, 60%, 70%, 80%). + -----------------------------------------------------------------------------*/ + timer_oc_parameter_struct timer_ocinitpara; + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER0); + + timer_deinit(TIMER0); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + /* TIMER0 configuration */ + timer_initpara.prescaler = 107; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 999; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER0, &timer_initpara); + + /* initialize TIMER channel output parameter struct */ + timer_channel_output_struct_para_init(&timer_ocinitpara); + timer_ocinitpara.outputstate = TIMER_CCX_ENABLE; + timer_ocinitpara.outputnstate = TIMER_CCXN_DISABLE; + timer_ocinitpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocinitpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocinitpara.ocidlestate = TIMER_OC_IDLE_STATE_HIGH; + timer_ocinitpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + + timer_channel_output_config(TIMER0, TIMER_CH_0, &timer_ocinitpara); + timer_channel_output_config(TIMER0, TIMER_CH_1, &timer_ocinitpara); + timer_channel_output_config(TIMER0, TIMER_CH_2, &timer_ocinitpara); + timer_channel_output_config(TIMER0, TIMER_CH_3, &timer_ocinitpara); + + /* CH0 configuration in PWM0 mode */ + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_0, buffer[0]); + timer_channel_output_mode_config(TIMER0, TIMER_CH_0, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); + + /* CH1 configuration in PWM0 mode */ + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_1, buffer[0]); + timer_channel_output_mode_config(TIMER0, TIMER_CH_1, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_1, TIMER_OC_SHADOW_DISABLE); + + /* CH2 configuration in PWM0 mode */ + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_2, buffer[0]); + timer_channel_output_mode_config(TIMER0, TIMER_CH_2, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_2, TIMER_OC_SHADOW_DISABLE); + + /* CH3 configuration in PWM0 mode */ + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_3, buffer[0]); + timer_channel_output_mode_config(TIMER0, TIMER_CH_3, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_3, TIMER_OC_SHADOW_DISABLE); + + /* TIMER0 primary output enable */ + timer_primary_output_config(TIMER0, ENABLE); + + /* TIMER0 update DMA request enable */ + timer_dma_transfer_config(TIMER0, TIMER_DMACFG_DMATA_CH0CV, TIMER_DMACFG_DMATC_4TRANSFER); + timer_dma_enable(TIMER0, TIMER_DMA_UPD); + + /* auto-reload preload enable */ + timer_auto_reload_shadow_enable(TIMER0); + + /* TIMER0 counter enable */ + timer_enable(TIMER0); +} + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + gpio_config(); + dma_config(); + timer_config(); + + while (1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_dma_burst/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_dma_burst/readme.txt new file mode 100644 index 0000000..bc739aa --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER0_dma_burst/readme.txt @@ -0,0 +1,48 @@ +/*! + \file readme.txt + \brief description of the TIMER0 DMA burst demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to use DMA with +TIMER0 update request to transfer data from memory to TIMER0 capture compare +register 0~3. + + TIMER0CLK is fixed to systemcoreclock, the TIMER0 prescaler is equal to 108 +so the TIMER0 counter clock used is 1MHz. + + The objective is to configure TIMER0 channel 0~3(PA8~PA11) to generate PWM signal. +capture compare register 0~3 are to be updated twice per circle. On the first update +DMA request, data1 is transferred to CH0CV, data2 is transferred to CH1CV, data3 is +transferred to CH2CV, data4 is transferred to CH3CV and duty cycle(10%, 20%, 30%, 40%). +On the second update DMA request, data5 is transferred to CH0CV, data6 is transferred +to CH1CV, data7 is transferred to CH2CV, data8 is transferred to CH3CV and duty cycle +(50%, 60%, 70%, 80%). diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_exttrigger/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_exttrigger/main.c new file mode 100644 index 0000000..c699c2b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_exttrigger/main.c @@ -0,0 +1,142 @@ +/*! + \file main.c + \brief TIMER1 external trigger demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +/* configure the GPIO ports */ +void gpio_config(void); +/* configure the TIMER peripheral */ +void timer_config(void); + +/** + \brief configure the GPIO ports + \param[in] none + \param[out] none + \retval none + */ +void gpio_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_AF); + + /*configure PA2(TIMER1 CH2) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2); + + /*configure PA0(TIMER1 CH0) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_0); +} + +/** + \brief configure the TIMER peripheral + \param[in] none + \param[out] none + \retval none + */ +void timer_config(void) +{ + /* TIMER with an external trigger ------------------------------------- + TIMER1 is configured as slave timer for an external trigger connected + to TIMER1 CI0 pin : + - The TIMER1 CI0FE0 is used as trigger input + - rising edge is used to start the TIMER1: event mode. + - TIMER1 CH2 is used PWM Mode 0. + the starts of the TIMER1 counter are controlled by the + external trigger. + -------------------------------------------------------------------- */ + timer_oc_parameter_struct timer_ocinitpara; + timer_parameter_struct timer_initpara; + timer_ic_parameter_struct timer_icinitpara; + + rcu_periph_clock_enable(RCU_TIMER1); + + timer_deinit(TIMER1); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + /* TIMER1 configuration */ + timer_initpara.prescaler = 239; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 7999; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER1, &timer_initpara); + + /* initialize TIMER channel output parameter struct */ + timer_channel_output_struct_para_init(&timer_ocinitpara); + /* CH2 configuration in OC PWM0 mode */ + timer_ocinitpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocinitpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocinitpara.outputstate = TIMER_CCX_ENABLE; + timer_ocinitpara.outputnstate = TIMER_CCXN_DISABLE; + timer_ocinitpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + timer_ocinitpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + timer_channel_output_config(TIMER1, TIMER_CH_2, &timer_ocinitpara); + + timer_channel_output_pulse_value_config(TIMER1,TIMER_CH_2,3999); + timer_channel_output_mode_config(TIMER1, TIMER_CH_2, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER1, TIMER_CH_2, TIMER_OC_SHADOW_DISABLE); + + /* initialize TIMER channel input parameter struct */ + timer_channel_input_struct_para_init(&timer_icinitpara); + /* TIMER1 CH0 input capture configuration */ + timer_icinitpara.icpolarity = TIMER_IC_POLARITY_RISING; + timer_icinitpara.icselection = TIMER_IC_SELECTION_DIRECTTI; + timer_icinitpara.icprescaler = TIMER_IC_PSC_DIV1; + timer_icinitpara.icfilter = 0x02; + timer_input_capture_config(TIMER1, TIMER_CH_0, &timer_icinitpara); + + /* slave mode selection: TIMER1 */ + /* TIMER1 input trigger: external trigger connected to CI0 */ + timer_input_trigger_source_select(TIMER1, TIMER_SMCFG_TRGSEL_CI0FE0); + timer_slave_mode_select(TIMER1, TIMER_SLAVE_MODE_EVENT); + + /* auto-reload preload enable */ + timer_auto_reload_shadow_enable(TIMER1); +} + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + gpio_config(); + timer_config(); + + while (1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_exttrigger/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_exttrigger/readme.txt new file mode 100644 index 0000000..788212d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_exttrigger/readme.txt @@ -0,0 +1,46 @@ +/*! + \file readme.txt + \brief description of the TIMER1 external trigger demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to start TIMER +peripherals with an external trigger. + + TIMER1 is configured as slave timer for an external trigger connected to TIMER1 +CI0 pin: + - The TIMER1 CI0FE0 is used as trigger input. + - Rising edge is used to start the TIMER1: event mode. + - TIMER1 CH2(PA2) is used PWM Mode 0. + The starts of the TIMER1 counter are controlled by the external trigger. + + Connect the TIMER1 CH0(PA0) pin to +3V3 on the board as a external trigger with a +rising edge. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_ocactive/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_ocactive/main.c new file mode 100644 index 0000000..ccdf763 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_ocactive/main.c @@ -0,0 +1,135 @@ +/*! + \file main.c + \brief TIMER1 oc active demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +void gpio_config(void); +void timer_config(void); + +/** + \brief configure the GPIO ports + \param[in] none + \param[out] none + \retval none + */ +void gpio_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_AF); + + /*Configure PA0/PA1/PA2(TIMER1 CH0/CH1/CH2) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0); + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_1); + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2); +} + +/** + \brief configure the TIMER peripheral + \param[in] none + \param[out] none + \retval none + */ +void timer_config(void) +{ + /* --------------------------------------------------------------- + TIMER1 Configuration: + TIMER1CLK = SystemCoreClock / 10800 = 10K, + And generate 3 signals with 3 different delays: + TIMER1_CH0 delay = 4000/10000 = 0.4s + TIMER1_CH1 delay = 8000/10000 = 0.8s + TIMER1_CH2 delay = 12000/10000 = 1.2s + --------------------------------------------------------------- */ + timer_oc_parameter_struct timer_ocinitpara; + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER1); + + timer_deinit(TIMER1); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + /* TIMER1 configuration */ + timer_initpara.prescaler = 10799; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 65535; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER1, &timer_initpara); + + /* initialize TIMER channel output parameter struct */ + timer_channel_output_struct_para_init(&timer_ocinitpara); + /* CH0,CH1 and CH2 configuration in OC active mode */ + timer_ocinitpara.outputstate = TIMER_CCX_ENABLE; + timer_ocinitpara.outputnstate = TIMER_CCXN_DISABLE; + timer_ocinitpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocinitpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocinitpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + timer_ocinitpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + + timer_channel_output_config(TIMER1, TIMER_CH_0, &timer_ocinitpara); + timer_channel_output_config(TIMER1, TIMER_CH_1, &timer_ocinitpara); + timer_channel_output_config(TIMER1, TIMER_CH_2, &timer_ocinitpara); + + /* CH0 configuration in OC active mode */ + timer_channel_output_pulse_value_config(TIMER1,TIMER_CH_0,3999); + timer_channel_output_mode_config(TIMER1, TIMER_CH_0, TIMER_OC_MODE_ACTIVE); + timer_channel_output_shadow_config(TIMER1, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); + + /* CH1 configuration in OC active mode */ + timer_channel_output_pulse_value_config(TIMER1,TIMER_CH_1,7999); + timer_channel_output_mode_config(TIMER1, TIMER_CH_1, TIMER_OC_MODE_ACTIVE); + timer_channel_output_shadow_config(TIMER1, TIMER_CH_1, TIMER_OC_SHADOW_DISABLE); + + /* CH2 configuration in OC active mode */ + timer_channel_output_pulse_value_config(TIMER1,TIMER_CH_2,11999); + timer_channel_output_mode_config(TIMER1, TIMER_CH_2, TIMER_OC_MODE_ACTIVE); + timer_channel_output_shadow_config(TIMER1, TIMER_CH_2, TIMER_OC_SHADOW_DISABLE); + + timer_enable(TIMER1); +} + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + gpio_config(); + timer_config(); + + while (1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_ocactive/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_ocactive/readme.txt new file mode 100644 index 0000000..183226e --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_ocactive/readme.txt @@ -0,0 +1,52 @@ +/*! + \file readme.txt + \brief description of the TIMER1 OC active demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to configure the +TIMER peripheral to generate three different signals with three different delays. + + The TIMxCLK frequency is set to systemcoreclock, the prescaler is 10800 +so the TIMER1 counter clock is 10KHz. + + And generate 3 signals with 3 different delays: + TIMER1_CH0 delay = 4000/10K = 0.4s + TIMER1_CH1 delay = 8000/10K = 0.8s + TIMER1_CH2 delay = 12000/10K = 1.2s + + Connect the TIMER1 pins to leds and reset the board to watch the signal: + - TIMER1_CH0 pin (PA0) + - TIMER1_CH1 pin (PA1) + - TIMER1_CH2 pin (PA2) + - LED3 pin (PC2) + - LED4 pin (PE0) + - LED5 pin (PE1) diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_ocinactive/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_ocinactive/gd32vf103_it.c new file mode 100644 index 0000000..8e11247 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_ocinactive/gd32vf103_it.c @@ -0,0 +1,60 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + + +/** + * @brief This function handles TIMER1 interrupt request. + * @param None + * @retval None + */ +void TIMER1_IRQHandler(void) +{ + if(SET == timer_interrupt_flag_get(TIMER1, TIMER_INT_FLAG_CH0)){ + /* clear channel 0 interrupt bit */ + timer_interrupt_flag_clear(TIMER1, TIMER_INT_FLAG_CH0); + gd_eval_led_off(LED2); + }else if(SET == timer_interrupt_flag_get(TIMER1, TIMER_INT_FLAG_CH1)){ + /* clear channel 1 interrupt bit */ + timer_interrupt_flag_clear(TIMER1, TIMER_INT_FLAG_CH1); + gd_eval_led_off(LED3); + }else if(SET == timer_interrupt_flag_get(TIMER1, TIMER_INT_FLAG_CH2)){ + /* clear channel 2 interrupt bit */ + timer_interrupt_flag_clear(TIMER1, TIMER_INT_FLAG_CH2); + gd_eval_led_off(LED4); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_ocinactive/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_ocinactive/main.c new file mode 100644 index 0000000..52a4083 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_ocinactive/main.c @@ -0,0 +1,152 @@ +/*! + \file main.c + \brief TIMER1 oc inactive demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +/* configure the GPIO ports */ +void gpio_config(void); +/* configure the TIMER peripheral */ +void timer_config(void); + +/** + \brief configure the GPIO ports + \param[in] none + \param[out] none + \retval none + */ +void gpio_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_AF); + + /*Configure PA0/PA1/PA2(TIMER1 CH0/CH1/CH2) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0); + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_1); + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2); +} + + +/** + \brief configure the TIMER peripheral + \param[in] none + \param[out] none + \retval none + */ +void timer_config(void) +{ + /* --------------------------------------------------------------- + TIMER1 Configuration: + TIMER1CLK = SystemCoreClock / 54000 = 2KHz, + And generate 3 signals with 3 different delays: + TIMER1_CH0 delay = 2000/2000 = 1s + TIMER1_CH1 delay = 4000/2000 = 2s + TIMER1_CH2 delay = 6000/2000 = 3s + --------------------------------------------------------------- */ + timer_oc_parameter_struct timer_ocinitpara; + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER1); + + timer_deinit(TIMER1); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + /* TIMER1 configuration */ + timer_initpara.prescaler = 53999; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 10000; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER1, &timer_initpara); + + /* initialize TIMER channel output parameter struct */ + timer_channel_output_struct_para_init(&timer_ocinitpara); + /* CH0,CH1 and CH2 configuration in OC inactive mode */ + timer_ocinitpara.outputstate = TIMER_CCX_ENABLE; + timer_ocinitpara.outputnstate = TIMER_CCXN_DISABLE; + timer_ocinitpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocinitpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocinitpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + timer_ocinitpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + + timer_channel_output_config(TIMER1, TIMER_CH_0, &timer_ocinitpara); + timer_channel_output_config(TIMER1, TIMER_CH_1, &timer_ocinitpara); + timer_channel_output_config(TIMER1, TIMER_CH_2, &timer_ocinitpara); + + /* CH0 configuration in OC inactive mode */ + timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0, 2000); + timer_channel_output_mode_config(TIMER1, TIMER_CH_0, TIMER_OC_MODE_INACTIVE); + timer_channel_output_shadow_config(TIMER1, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); + + /* CH1 configuration in OC inactive mode */ + timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, 4000); + timer_channel_output_mode_config(TIMER1, TIMER_CH_1, TIMER_OC_MODE_INACTIVE); + timer_channel_output_shadow_config(TIMER1, TIMER_CH_1, TIMER_OC_SHADOW_DISABLE); + + /* CH2 configuration in OC inactive mode */ + timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_2, 6000); + timer_channel_output_mode_config(TIMER1, TIMER_CH_2, TIMER_OC_MODE_INACTIVE); + timer_channel_output_shadow_config(TIMER1, TIMER_CH_2, TIMER_OC_SHADOW_DISABLE); + + timer_interrupt_enable(TIMER1, TIMER_INT_CH0 | TIMER_INT_CH1 | TIMER_INT_CH2); + + gd_eval_led_on(LED2); + gd_eval_led_on(LED3); + gd_eval_led_on(LED4); + + timer_enable(TIMER1); +} + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + gd_eval_led_init(LED4); + + gpio_config(); + eclic_global_interrupt_enable(); + eclic_set_nlbits(ECLIC_GROUP_LEVEL3_PRIO1); + eclic_irq_enable(TIMER1_IRQn,1,0); + timer_config(); + + while (1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_ocinactive/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_ocinactive/readme.txt new file mode 100644 index 0000000..bb8ea36 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_ocinactive/readme.txt @@ -0,0 +1,52 @@ +/*! + \file readme.txt + \brief description of the TIMER1 OC inactive demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to configure the +TIMER peripheral to generate three different signals with three different delays. + + The TIMxCLK frequency is set to systemcoreclock, the prescaler is 54000, so the +TIMER1 counter clock is 2KHz. + + And generate 3 signals with 3 different delays: + TIMER1_CH0 delay = 2000/2000 = 1s. + TIMER1_CH1 delay = 4000/2000 = 2s. + TIMER1_CH2 delay = 6000/2000 = 3s. + + So PA0 is reset after a delay equal to 1s, PA1 is reset after a delay equal to 2s, +and PA2 is reset after a delay equal to 3s. + + While the counter is lower than the TIMER_CHxCV registers values, which determines +the output delay, the LED2, LED3 and LED4 are turned on. When the counter value reaches +the TIMER_CHxCV registers values, the channel output compare interrupts are generated, +and in the handler routine, these LEDs are turned off. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_octoggle/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_octoggle/main.c new file mode 100644 index 0000000..4e44f1c --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_octoggle/main.c @@ -0,0 +1,122 @@ +/*! + \file main.c + \brief TIMER1 oc toggle demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +/* configure the GPIO ports */ +void gpio_config(void); +/* configure the TIMER peripheral */ +void timer_config(void); + +/** + \brief configure the GPIO ports + \param[in] none + \param[out] none + \retval none + */ +void gpio_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_AF); + + /*configure PA1(TIMER1 CH1) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_1); +} + +/** + \brief configure the timer peripheral + \param[in] none + \param[out] none + \retval none + */ +void timer_config(void) +{ + /* --------------------------------------------------------------------------- + TIMER1 configuration: output compare toggle mode: + TIMER1CLK = systemcoreclock / 5400 = 20K, + CH1 update rate = TIMER1 counter clock / CH1VAL = 20000/4000 = 5 Hz + ----------------------------------------------------------------------------*/ + timer_oc_parameter_struct timer_ocinitpara; + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER1); + + timer_deinit(TIMER1); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + /* TIMER1 configuration */ + timer_initpara.prescaler = 5399; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 3999; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER1,&timer_initpara); + + /* initialize TIMER channel output parameter struct */ + timer_channel_output_struct_para_init(&timer_ocinitpara); + /* CH1 configuration in OC TOGGLE mode */ + timer_ocinitpara.outputstate = TIMER_CCX_ENABLE; + timer_ocinitpara.outputnstate = TIMER_CCXN_DISABLE; + timer_ocinitpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocinitpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocinitpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + timer_ocinitpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + + timer_channel_output_config(TIMER1, TIMER_CH_1, &timer_ocinitpara); + + timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, 3999); + timer_channel_output_mode_config(TIMER1, TIMER_CH_1, TIMER_OC_MODE_TOGGLE); + timer_channel_output_shadow_config(TIMER1, TIMER_CH_1, TIMER_OC_SHADOW_DISABLE); + + /* auto-reload preload enable */ + timer_auto_reload_shadow_enable(TIMER1); + timer_enable(TIMER1); +} + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + gpio_config(); + timer_config(); + + while (1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_octoggle/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_octoggle/readme.txt new file mode 100644 index 0000000..4b6e94e --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_octoggle/readme.txt @@ -0,0 +1,45 @@ +/*! + \file readme.txt + \brief description of the TIMER1 OC toggle demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to configure the +TIMER peripheral to generate the toggle signal. + + The TIMxCLK frequency is set to systemcoreclock, the prescaler is 5400 +so the TIMER1 counter clock is 20KHz. + + TIMER1 configuration: CH1 output compare toggle mode: +CH1 update rate = TIMER1 counter clock / CH1CC = 20000/4000 = 5 Hz. + + Connect the TIMER1 CH1(PA1) to an oscilloscope to monitor waveform. + \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_pwmout/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_pwmout/main.c new file mode 100644 index 0000000..4780d44 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_pwmout/main.c @@ -0,0 +1,139 @@ +/*! + \file main.c + \brief TIMER1 PWM output demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +void gpio_config(void); +void timer_config(void); + +/** + \brief configure the GPIO ports + \param[in] none + \param[out] none + \retval none + */ +void gpio_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_AF); + + /*Configure PA1 PA2 PA3(TIMER1 CH1 CH2 CH3) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_1); + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2); + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_3); +} + +/** + \brief configure the TIMER peripheral + \param[in] none + \param[out] none + \retval none + */ +void timer_config(void) +{ + /* ----------------------------------------------------------------------- + TIMER1 configuration: generate 3 PWM signals with 3 different duty cycles: + TIMER1CLK = SystemCoreClock / 108 = 1MHz + + TIMER1 channel1 duty cycle = (4000/ 16000)* 100 = 25% + TIMER1 channel2 duty cycle = (8000/ 16000)* 100 = 50% + TIMER1 channel3 duty cycle = (12000/ 16000)* 100 = 75% + ----------------------------------------------------------------------- */ + timer_oc_parameter_struct timer_ocinitpara; + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER1); + + timer_deinit(TIMER1); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + /* TIMER1 configuration */ + timer_initpara.prescaler = 107; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 15999; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER1, &timer_initpara); + + /* initialize TIMER channel output parameter struct */ + timer_channel_output_struct_para_init(&timer_ocinitpara); + /* CH0, CH1 and CH2 configuration in PWM mode */ + timer_ocinitpara.outputstate = TIMER_CCX_ENABLE; + timer_ocinitpara.outputnstate = TIMER_CCXN_DISABLE; + timer_ocinitpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocinitpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocinitpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + timer_ocinitpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + + timer_channel_output_config(TIMER1,TIMER_CH_1,&timer_ocinitpara); + timer_channel_output_config(TIMER1,TIMER_CH_2,&timer_ocinitpara); + timer_channel_output_config(TIMER1,TIMER_CH_3,&timer_ocinitpara); + + /* CH1 configuration in PWM mode1,duty cycle 25% */ + timer_channel_output_pulse_value_config(TIMER1,TIMER_CH_1,3999); + timer_channel_output_mode_config(TIMER1,TIMER_CH_1,TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER1,TIMER_CH_1,TIMER_OC_SHADOW_DISABLE); + + /* CH2 configuration in PWM mode1,duty cycle 50% */ + timer_channel_output_pulse_value_config(TIMER1,TIMER_CH_2,7999); + timer_channel_output_mode_config(TIMER1,TIMER_CH_2,TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER1,TIMER_CH_2,TIMER_OC_SHADOW_DISABLE); + + /* CH3 configuration in PWM mode1,duty cycle 75% */ + timer_channel_output_pulse_value_config(TIMER1,TIMER_CH_3,11999); + timer_channel_output_mode_config(TIMER1,TIMER_CH_3,TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER1,TIMER_CH_3,TIMER_OC_SHADOW_DISABLE); + + /* auto-reload preload enable */ + timer_auto_reload_shadow_enable(TIMER1); + /* auto-reload preload enable */ + timer_enable(TIMER1); +} + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + gpio_config(); + timer_config(); + + while (1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_pwmout/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_pwmout/readme.txt new file mode 100644 index 0000000..1783f26 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_pwmout/readme.txt @@ -0,0 +1,48 @@ +/*! + \file readme.txt + \brief description of the TIMER1 PWM output demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to configure the +TIMER peripheral in PWM (Pulse Width Modulation) mode. + + The TIMxCLK frequency is set to systemcoreclock, the prescaler is 108 so the +TIMER1 counter clock is 1MHz. + + TIMER1 Channel1 duty cycle = (4000/ 16000)* 100 = 25%. + TIMER1 Channel2 duty cycle = (8000/ 16000)* 100 = 50%. + TIMER1 Channel3 duty cycle = (12000/ 16000)* 100 = 75%. + + Connect the TIMER1 pins to an oscilloscope to monitor the different waveforms: + - TIMER1_CH1 pin (PA1) + - TIMER1_CH2 pin (PA2) + - TIMER1_CH3 pin (PA3) diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_singlepulse/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_singlepulse/main.c new file mode 100644 index 0000000..15dddf8 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_singlepulse/main.c @@ -0,0 +1,147 @@ +/*! + \file main.c + \brief TIMER1 single pulse demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +/* configure the GPIO ports */ +void gpio_config(void); +/* configure the TIMER peripheral */ +void timer_config(void); + +/** + \brief configure the GPIO ports + \param[in] none + \param[out] none + \retval none + */ +void gpio_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_AF); + + /*configure PA0/PA1(TIMER1 CH0/CH1) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_0); + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_1); +} + +/** + \brief configure the TIMER peripheral + \param[in] none + \param[out] none + \retval none + */ +void timer_config(void) +{ + /* ----------------------------------------------------------------------- + TIMER1 configuration: single pulse mode + the external signal is connected to TIMER1 CH0 pin(PA0) and the falling + edge is used as active edge. + the single pulse signal is output on TIMER1 CH1 pin(PA1). + + the TIMER1CLK frequency is set to systemcoreclock,the prescaler is + 6,so the TIMER1 counter clock is 18MHz. + + single pulse value = (TIMER1_Period - TIMER1_Pulse) / TIMER1 counter clock + = (65535 - 11535) / 18MHz = 3 ms. + ----------------------------------------------------------------------- */ + timer_oc_parameter_struct timer_ocinitpara; + timer_parameter_struct timer_initpara; + timer_ic_parameter_struct timer_icinitpara; + + rcu_periph_clock_enable(RCU_TIMER1); + + timer_deinit(TIMER1); + + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + /* TIMER1 configuration */ + timer_initpara.prescaler = 5; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 65535; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER1, &timer_initpara); + + /* auto-reload preload disable */ + timer_auto_reload_shadow_disable(TIMER1); + + /* initialize TIMER channel output parameter struct */ + timer_channel_output_struct_para_init(&timer_ocinitpara); + /* CH1 configuration in OC PWM mode 1 */ + timer_ocinitpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocinitpara.outputstate = TIMER_CCX_ENABLE; + timer_ocinitpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocinitpara.outputnstate = TIMER_CCXN_DISABLE; + timer_ocinitpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + timer_ocinitpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + timer_channel_output_config(TIMER1, TIMER_CH_1, &timer_ocinitpara); + + timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, 11535); + timer_channel_output_mode_config(TIMER1, TIMER_CH_1, TIMER_OC_MODE_PWM1); + timer_channel_output_shadow_config(TIMER1, TIMER_CH_1, TIMER_OC_SHADOW_DISABLE); + + /* initialize TIMER channel input parameter struct */ + timer_channel_input_struct_para_init(&timer_icinitpara); + /* TIMER1 CH0 input capture configuration */ + timer_icinitpara.icpolarity = TIMER_IC_POLARITY_FALLING; + timer_icinitpara.icselection = TIMER_IC_SELECTION_DIRECTTI; + timer_icinitpara.icprescaler = TIMER_IC_PSC_DIV1; + timer_icinitpara.icfilter = 0x00; + timer_input_capture_config(TIMER1, TIMER_CH_0, &timer_icinitpara); + + /* single pulse mode selection */ + timer_single_pulse_mode_config(TIMER1, TIMER_SP_MODE_SINGLE); + + /* slave mode selection : TIMER1 */ + /* TIMER1 input trigger : external trigger connected to CI0 */ + timer_input_trigger_source_select(TIMER1, TIMER_SMCFG_TRGSEL_CI0FE0); + timer_slave_mode_select(TIMER1, TIMER_SLAVE_MODE_EVENT); +} + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + gpio_config(); + timer_config(); + + while (1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_singlepulse/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_singlepulse/readme.txt new file mode 100644 index 0000000..19bec0a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_singlepulse/readme.txt @@ -0,0 +1,50 @@ +/*! + \file readme.txt + \brief description of the TIMER1 single pulse demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to configure +the TIMER1 peripheral in single pulse mode. + The external signal is connected to TIMER1 CH0 pin(PA0) and the falling edge is +used as active edge. + + The single pulse signal is output on TIMER1 CH1 pin(PA1). + + The TIMER1CLK frequency is set to systemcoreclock,the prescaler is 6,so the +TIMER1 counter clock is 18MHz. + + single pulse value = (TIMER1_period - TIMER1_pulse) / TIMER1 counter clock + = (65535 - 11535) / 18MHz = 3 ms. + + Connect the TIMER1 CH1 pin (PA1) to an oscilloscope to monitor the waveform. +Connect the TIMER1 CH0 pin (PA0) to KEY_TAMPER(PC13),When KEY_TAMPER is pressed, +a single pulse is generated on TIMER1 CH1 pin. \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_timebase/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_timebase/gd32vf103_it.c new file mode 100644 index 0000000..8246b29 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_timebase/gd32vf103_it.c @@ -0,0 +1,49 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" + +/** + * @brief This function handles TIMER1 interrupt request. + * @param None + * @retval None + */ +void TIMER1_IRQHandler(void) +{ + if(SET == timer_interrupt_flag_get(TIMER1, TIMER_INT_CH0)){ + /* clear channel 0 interrupt bit */ + timer_interrupt_flag_clear(TIMER1, TIMER_INT_CH0); + gd_eval_led_toggle(LED2); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_timebase/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_timebase/main.c new file mode 100644 index 0000000..7044ccf --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_timebase/main.c @@ -0,0 +1,124 @@ +/*! + \file main.c + \brief TIMER1 oc timebase demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +/* configure the GPIO ports */ +void gpio_config(void); +/* configure the TIMER peripheral */ +void timer_config(void); + + +/** + \brief configure the GPIO ports + \param[in] none + \param[out] none + \retval none + */ +void gpio_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_AF); + + /*Configure PA0(TIMER1 CH0) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0); +} + + +/** + \brief configure the TIMER peripheral + \param[in] none + \param[out] none + \retval none + */ +void timer_config(void) +{ + /* ---------------------------------------------------------------------------- + TIMER1 Configuration: + TIMER1CLK = SystemCoreClock/5400 = 20KHz. + TIMER1 configuration is timing mode, and the timing is 0.2s(4000/20000 = 0.2s). + CH0 update rate = TIMER1 counter clock/CH0CV = 20000/4000 = 5Hz. + ---------------------------------------------------------------------------- */ + timer_oc_parameter_struct timer_ocinitpara; + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER1); + + timer_deinit(TIMER1); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + /* TIMER1 configuration */ + timer_initpara.prescaler = 5399; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 4000; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_init(TIMER1, &timer_initpara); + + /* initialize TIMER channel output parameter struct */ + timer_channel_output_struct_para_init(&timer_ocinitpara); + /* CH0,CH1 and CH2 configuration in OC timing mode */ + timer_ocinitpara.outputstate = TIMER_CCX_ENABLE; + timer_ocinitpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocinitpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + timer_channel_output_config(TIMER1, TIMER_CH_0, &timer_ocinitpara); + + /* CH0 configuration in OC timing mode */ + timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0, 2000); + timer_channel_output_mode_config(TIMER1, TIMER_CH_0, TIMER_OC_MODE_TIMING); + timer_channel_output_shadow_config(TIMER1, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); + + timer_interrupt_enable(TIMER1, TIMER_INT_CH0); + timer_enable(TIMER1); +} + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + gd_eval_led_init(LED2); + + gpio_config(); + eclic_global_interrupt_enable(); + eclic_set_nlbits(ECLIC_GROUP_LEVEL3_PRIO1); + eclic_irq_enable(TIMER1_IRQn,1,0); + timer_config(); + while (1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_timebase/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_timebase/readme.txt new file mode 100644 index 0000000..c8493a0 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER1_timebase/readme.txt @@ -0,0 +1,47 @@ +/*! + \file readme.txt + \brief description of the TIMER1 timebase demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to configure the +TIMER peripheral in timing mode with the corresponding interrupt request for channel 0 +in order to generate a time base. + + The TIMxCLK frequency is set to systemcoreclock, the prescaler is 5400, so the TIMER1 +counter clock is 20KHz. + + TIMER1 configuration is timing mode, and the timing is 0.2s(4000/20000 = 0.2s), and +the CH0 update rate = TIMER1 counter clock/CH0CV = 20000/4000 = 5Hz. + + Enable the channel 0 interrupt, so the TIMER1 generates an interrupt each 0.2s, in +the handler routine, LED1 is toggled each 0.2s. + \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_inputcapture/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_inputcapture/gd32vf103_it.c new file mode 100644 index 0000000..3c8103a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_inputcapture/gd32vf103_it.c @@ -0,0 +1,74 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include + +uint16_t readvalue1 = 0, readvalue2 = 0; +uint16_t ccnumber = 0; +uint32_t count = 0; +float fre = 0; + +/** + * @brief This function handles TIMER2 interrupt request. + * @param None + * @retval None + */ +void TIMER2_IRQHandler(void) +{ + if(SET == timer_interrupt_flag_get(TIMER2,TIMER_INT_FLAG_CH0)){ + /* clear channel 0 interrupt bit */ + timer_interrupt_flag_clear(TIMER2,TIMER_INT_FLAG_CH0); + + if(0 == ccnumber){ + /* read channel 0 capture value */ + readvalue1 = timer_channel_capture_value_register_read(TIMER2, TIMER_CH_0); + ccnumber = 1; + }else if(1 == ccnumber){ + /* read channel 0 capture value */ + readvalue2 = timer_channel_capture_value_register_read(TIMER2, TIMER_CH_0); + + if(readvalue2 > readvalue1){ + count = (readvalue2 - readvalue1); + }else{ + count = ((0xFFFF - readvalue1) + readvalue2); + } + + fre = (float)1000000 / count; + printf("the frequence is %d\n\r",(uint16_t)fre); + + ccnumber = 0; + } + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_inputcapture/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_inputcapture/main.c new file mode 100644 index 0000000..d65db81 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_inputcapture/main.c @@ -0,0 +1,126 @@ +/*! + \file main.c + \brief TIMER2 input capture demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +/* configure the GPIO ports */ +void gpio_configuration(void); +/* configure the TIMER peripheral */ +void timer_configuration(void); + +/** + \brief configure the GPIO ports + \param[in] none + \param[out] none + \retval none + */ +void gpio_configuration(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_AF); + + /*configure PA6(TIMER2 CH0) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6); +} + + + +/** + \brief configure the TIMER peripheral + \param[in] none + \param[out] none + \retval none + */ +void timer_configuration(void) +{ + /* TIMER2 configuration: input capture mode ------------------- + the external signal is connected to TIMER2 CH0 pin(PA6) + the rising edge is used as active edge + the TIMER2 CH0CV is used to compute the frequency value + ------------------------------------------------------------ */ + timer_ic_parameter_struct timer_icinitpara; + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER2); + + timer_deinit(TIMER2); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + /* TIMER2 configuration */ + timer_initpara.prescaler = 107; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 65535; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER2,&timer_initpara); + + /* TIMER2 configuration */ + /* initialize TIMER channel input parameter struct */ + timer_channel_input_struct_para_init(&timer_icinitpara); + /* TIMER2 CH0 input capture configuration */ + timer_icinitpara.icpolarity = TIMER_IC_POLARITY_RISING; + timer_icinitpara.icselection = TIMER_IC_SELECTION_DIRECTTI; + timer_icinitpara.icprescaler = TIMER_IC_PSC_DIV1; + timer_icinitpara.icfilter = 0x0; + timer_input_capture_config(TIMER2,TIMER_CH_0,&timer_icinitpara); + + /* auto-reload preload enable */ + timer_auto_reload_shadow_enable(TIMER2); + /* clear channel 0 interrupt bit */ + timer_interrupt_flag_clear(TIMER2,TIMER_INT_FLAG_CH0); + /* channel 0 interrupt enable */ + timer_interrupt_enable(TIMER2,TIMER_INT_CH0); + + /* TIMER2 counter enable */ + timer_enable(TIMER2); +} + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + gpio_configuration(); + gd_eval_com_init(EVAL_COM0); + eclic_global_interrupt_enable(); + eclic_set_nlbits(ECLIC_GROUP_LEVEL3_PRIO1); + eclic_irq_enable(TIMER2_IRQn,1,0); + timer_configuration(); + while (1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_inputcapture/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_inputcapture/readme.txt new file mode 100644 index 0000000..83451e0 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_inputcapture/readme.txt @@ -0,0 +1,56 @@ +/*! + \file readme.txt + \brief description of the TIMER2 input capture demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows TIMER peripheral to +measure the frequency of an external signal. + + The TIMxCLK frequency is set to systemcoreclock,the prescaler is 108 so +the TIMER2 counter clock is 1MHz. + + The external signal is connected to TIMER2 CH0 pin (PA6). + The amplitude of the external signal is better to be set as 3.3V. + The rising edge is used as active edge. + The TIMER2 CH0CV is used to compute the frequency value. + + The available frequence of the input signal is ranging from 16Hz to 20KHz. +You can use USART to watch the frequency of the input signal.The USART is +configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + + JP4 must be jumpped to USART. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_pwminputcapture/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_pwminputcapture/gd32vf103_it.c new file mode 100644 index 0000000..bc5a317 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_pwminputcapture/gd32vf103_it.c @@ -0,0 +1,82 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_it.h" +#include + +uint32_t ic1value = 0,ic2value = 0; +uint16_t dutycycle = 0; +float frequency = 0; +bool data_valid = FALSE; + +/** + * @brief this function handles TIMER2 interrupt request + * @param None + * @retval None + */ +void TIMER2_IRQHandler(void) +{ + if(SET == timer_interrupt_flag_get(TIMER2,TIMER_INT_CH0)){ + /* clear channel 0 interrupt bit */ + timer_interrupt_flag_clear(TIMER2,TIMER_INT_CH0); + /* read channel 0 capture value */ + ic1value = timer_channel_capture_value_register_read(TIMER2, TIMER_CH_0) + 1; + + if(0 != ic1value){ + /* read channel 1 capture value */ + ic2value = timer_channel_capture_value_register_read(TIMER2, TIMER_CH_1) + 1; + + /* calculate the duty cycle value */ + dutycycle = (ic2value * 100) / ic1value; + /* calculate the frequency value */ + frequency = (float)1000000U / ic1value; + + if(TRUE == data_valid) + { + /* print valid data */ + + printf("the dutycycle is %d\n",dutycycle); + printf("the frequence is %d\n",(uint16_t)frequency); + }else{ + /* discard the first data */ + /* the first number is inaccurate */ + data_valid = TRUE; + } + }else{ + /* reset the data */ + dutycycle = 0; + frequency = 0; + } + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_pwminputcapture/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_pwminputcapture/gd32vf103_it.h new file mode 100644 index 0000000..1adff88 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_pwminputcapture/gd32vf103_it.h @@ -0,0 +1,43 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef gd32vf103_IT_H +#define gd32vf103_IT_H + +#include "gd32vf103.h" + +/* TIMER2 handle function */ +void TIMER2_IRQHandler(void); + +#endif /* gd32vf103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_pwminputcapture/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_pwminputcapture/main.c new file mode 100644 index 0000000..6f00781 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_pwminputcapture/main.c @@ -0,0 +1,143 @@ +/*! + \file main.c + \brief TIMER2 PWM input capture demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +/* configure the GPIO ports */ +void gpio_configuration(void); +/* configure the TIMER peripheral */ +void timer_configuration(void); +/* retarget the C library printf function to the USART */ +int fputc(int ch, FILE *f); + +/* retarget the C library printf function to the USART */ +int fputc(int ch, FILE *f) +{ + usart_data_transmit(EVAL_COM1, (uint8_t)ch); + while(RESET == usart_flag_get(EVAL_COM1, USART_FLAG_TBE)); + return ch; +} + +/** + \brief configure the GPIO ports + \param[in] none + \param[out] none + \retval none + */ +void gpio_configuration(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_AF); + + /*configure PA6(TIMER2 CH0) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6); +} + +/** + \brief configure the TIMER peripheral + \param[in] none + \param[out] none + \retval none + */ +void timer_configuration(void) +{ + /* TIMER2 configuration: PWM input mode ------------------------ + the external signal is connected to TIMER2 CH0 pin(PA6) + the rising edge is used as active edge + the TIMER2 CH0CV is used to compute the frequency value + the TIMER2 CH1CV is used to compute the duty cycle value + ------------------------------------------------------------ */ + timer_ic_parameter_struct timer_icinitpara; + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER2); + + timer_deinit(TIMER2); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + /* TIMER2 configuration */ + timer_initpara.prescaler = 107; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 65535; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER2, &timer_initpara); + + /* TIMER2 configuration */ + /* initialize TIMER channel input parameter struct */ + timer_channel_input_struct_para_init(&timer_icinitpara); + /* TIMER2 CH0 PWM input capture configuration */ + timer_icinitpara.icpolarity = TIMER_IC_POLARITY_RISING; + timer_icinitpara.icselection = TIMER_IC_SELECTION_DIRECTTI; + timer_icinitpara.icprescaler = TIMER_IC_PSC_DIV1; + timer_icinitpara.icfilter = 0x0; + timer_input_pwm_capture_config(TIMER2, TIMER_CH_0, &timer_icinitpara); + + /* slave mode selection: TIMER2 */ + timer_input_trigger_source_select(TIMER2, TIMER_SMCFG_TRGSEL_CI0FE0); + timer_slave_mode_select(TIMER2, TIMER_SLAVE_MODE_RESTART); + + /* select the master slave mode */ + timer_master_slave_mode_config(TIMER2, TIMER_MASTER_SLAVE_MODE_ENABLE); + /* auto-reload preload enable */ + timer_auto_reload_shadow_enable(TIMER2); + /* clear channel 0 interrupt bit */ + timer_interrupt_flag_clear(TIMER2,TIMER_INT_CH0); + /* channel 0 interrupt enable */ + timer_interrupt_enable(TIMER2, TIMER_INT_CH0); + + /* TIMER2 counter enable */ + timer_enable(TIMER2); +} + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + gpio_configuration(); + gd_eval_com_init(EVAL_COM0); + eclic_global_interrupt_enable(); + eclic_set_nlbits(ECLIC_GROUP_LEVEL3_PRIO1); + eclic_irq_enable(TIMER2_IRQn,1,0); + timer_configuration(); + + while (1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_pwminputcapture/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_pwminputcapture/readme.txt new file mode 100644 index 0000000..1a1b56c --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMER2_pwminputcapture/readme.txt @@ -0,0 +1,56 @@ +/*! + \file readme.txt + \brief description of the TIMER2 PWM input capture demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to use the TIMER +peripheral to measure the frequency and duty cycle of an external signal. + + The TIMxCLK frequency is set to systemcoreclock, the prescaler is 108 so the +TIMER2 counter clock is 1MHz. + + The external signal is connected to TIMER2 CH0 pin (PA6). + The rising edge is used as active edge. + The TIMER2 CH0CV is used to compute the frequency value. + The TIMER2 CH1CV is used to compute the duty cycle value. + + The available frequence of the input signal is ranging from 16Hz to 20KHz. +You can use USART to watch the frequency and duty cycle of the input signal. +The USART is configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + + JP4 must be jumpped to USART. \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMERs_cascadesynchro/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMERs_cascadesynchro/main.c new file mode 100644 index 0000000..33cfc33 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMERs_cascadesynchro/main.c @@ -0,0 +1,222 @@ +/*! + \file main.c + \brief TIMERs cascade synchro demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +/* configure the GPIO ports */ +void gpio_config(void); +/* configure the TIMER peripheral */ +void timer_config(void); + +/** + \brief configure the GPIO ports + \param[in] none + \param[out] none + \retval none + */ +void gpio_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_AF); + + /*configure PA6(TIMER2 CH0) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_6); + + /*configure PA0(TIMER1 CH0) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0); + + /*configure PA8(TIMER0 CH0) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_8); +} + +/** + \brief configure the TIMER peripheral + \param[in] none + \param[out] none + \retval none + */ +void timer_config(void) +{ + /* timers synchronisation in cascade mode ---------------------------- + 1/TIMER1 is configured as master timer: + - PWM mode is used + - The TIMER1 update event is used as trigger output + + 2/TIMER2 is slave for TIMER1 and master for TIMER0, + - PWM mode is used + - The ITR1(TIMER1) is used as input trigger + - external clock mode is used,the counter counts on the rising edges of + the selected trigger. + - the TIMER2 update event is used as trigger output. + + 3/TIMER0 is slave for TIMER2, + - PWM mode is used + - The ITR2(TIMER2) is used as input trigger + - external clock mode is used,the counter counts on the rising edges of + the selected trigger. + -------------------------------------------------------------------- */ + timer_oc_parameter_struct timer_ocinitpara; + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER0); + rcu_periph_clock_enable(RCU_TIMER1); + rcu_periph_clock_enable(RCU_TIMER2); + + /* TIMER1 configuration */ + timer_deinit(TIMER1); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + timer_initpara.prescaler = 5399; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 3999; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER1,&timer_initpara); + + /* initialize TIMER channel output parameter struct */ + timer_channel_output_struct_para_init(&timer_ocinitpara); + /* CH1 configuration in PWM1 mode */ + timer_ocinitpara.outputstate = TIMER_CCX_ENABLE; + timer_ocinitpara.outputnstate = TIMER_CCXN_DISABLE; + timer_ocinitpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocinitpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocinitpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + timer_ocinitpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + timer_channel_output_config(TIMER1, TIMER_CH_0, &timer_ocinitpara); + + timer_channel_output_pulse_value_config(TIMER1,TIMER_CH_0,1999); + timer_channel_output_mode_config(TIMER1,TIMER_CH_0,TIMER_OC_MODE_PWM1); + timer_channel_output_shadow_config(TIMER1,TIMER_CH_0,TIMER_OC_SHADOW_DISABLE); + + /* auto-reload preload enable */ + timer_auto_reload_shadow_enable(TIMER1); + /* select the master slave mode */ + timer_master_slave_mode_config(TIMER1, TIMER_MASTER_SLAVE_MODE_ENABLE); + /* TIMER1 update event is used as trigger output */ + timer_master_output_trigger_source_select(TIMER1, TIMER_TRI_OUT_SRC_UPDATE); + + /* TIMER2 configuration */ + timer_deinit(TIMER2); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + timer_initpara.prescaler = 0; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 1; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER2, &timer_initpara); + + /* initialize TIMER channel output parameter struct */ + timer_channel_output_struct_para_init(&timer_ocinitpara); + /* CH0 configuration in PWM1 mode */ + timer_ocinitpara.outputstate = TIMER_CCX_ENABLE; + timer_ocinitpara.outputnstate = TIMER_CCXN_DISABLE; + timer_ocinitpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocinitpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocinitpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + timer_ocinitpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + timer_channel_output_config(TIMER2, TIMER_CH_0, &timer_ocinitpara); + + timer_channel_output_pulse_value_config(TIMER2, TIMER_CH_0, 1); + timer_channel_output_mode_config(TIMER2,TIMER_CH_0,TIMER_OC_MODE_PWM1); + timer_channel_output_shadow_config(TIMER2, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); + + /* auto-reload preload enable */ + timer_auto_reload_shadow_enable(TIMER2); + /* slave mode selection: TIMER2 */ + timer_slave_mode_select(TIMER2, TIMER_SLAVE_MODE_EXTERNAL0); + timer_input_trigger_source_select(TIMER2, TIMER_SMCFG_TRGSEL_ITI1); + /* select the master slave mode */ + timer_master_slave_mode_config(TIMER2, TIMER_MASTER_SLAVE_MODE_ENABLE); + /* TIMER2 update event is used as trigger output */ + timer_master_output_trigger_source_select(TIMER2, TIMER_TRI_OUT_SRC_UPDATE); + + /* TIMER0 configuration */ + timer_deinit(TIMER0); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + timer_initpara.prescaler = 0; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 1; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER0, &timer_initpara); + + /* initialize TIMER channel output parameter struct */ + timer_channel_output_struct_para_init(&timer_ocinitpara); + /* CH0 configuration in PWM1 mode */ + timer_ocinitpara.outputstate = TIMER_CCX_ENABLE; + timer_ocinitpara.outputnstate = TIMER_CCXN_DISABLE; + timer_ocinitpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocinitpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocinitpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + timer_ocinitpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + timer_channel_output_config(TIMER0, TIMER_CH_0, &timer_ocinitpara); + + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_0, 1); + timer_channel_output_mode_config(TIMER0,TIMER_CH_0,TIMER_OC_MODE_PWM1); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); + + /* auto-reload preload enable */ + timer_auto_reload_shadow_enable(TIMER0); + /* TIMER0 output enable */ + timer_primary_output_config(TIMER0, ENABLE); + /* slave mode selection: TIMER0 */ + timer_slave_mode_select(TIMER0, TIMER_SLAVE_MODE_EXTERNAL0); + timer_input_trigger_source_select(TIMER0, TIMER_SMCFG_TRGSEL_ITI2); + + /* TIMER counter enable */ + timer_enable(TIMER1); + timer_enable(TIMER2); + timer_enable(TIMER0); +} + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + gpio_config(); + timer_config(); + + while (1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMERs_cascadesynchro/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMERs_cascadesynchro/readme.txt new file mode 100644 index 0000000..f22da52 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMERs_cascadesynchro/readme.txt @@ -0,0 +1,74 @@ +/*! + \file readme.txt + \brief description of the TIMERs cascade synchro demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to synchronize +TIMER peripherals in cascade mode. + + In this example three timers are used: + 1/TIMER1 is configured as master timer: + - PWM mode is used + - The TIMER1 update event is used as trigger output + + 2/TIMER2 is slave for TIMER1 and master for TIMER0, + - PWM mode is used + - The ITR0(TIMER1) is used as input trigger + - External clock mode is used,the counter counts on the rising edges of + the selected trigger. + - The TIMER2 update event is used as trigger output. + + 3/TIMER0 is slave for TIMER2, + - PWM mode is used + - The ITR1(TIMER2) is used as input trigger + - External clock mode is used,the counter counts on the rising edges of + the selected trigger. + + The TIMERxCLK is fixed to 108 MHz, the TIMER1 counter clock is : +108MHz/5400= 20 KHz. + + The master timer TIMER1 is running at TIMER1 frequency : + TIMER1 frequency = (TIMER1 counter clock)/ (TIMER1 period + 1) = 5 Hz +and the duty cycle = TIMER1_CH0CC/(TIMER1_CAR + 1) = 50% + + The TIMER2 is running: + - At (TIMER1 frequency)/ (TIMER2 period + 1) = 2.5 Hz and a duty cycle + equal to TIMER2_CH0CC/(TIMER2_CAR + 1) = 50% + + The TIMER0 is running: + - At (TIMER2 frequency)/ (TIMER0 period + 1) = 1.25 Hz and a duty cycle + equal to TIMER0_CH0CC/(TIMER0_CAR + 1) = 50% + + Connect the three pins to a logic analyzer to monitor the different waveforms: + - TIMER1_CH0 pin (PA0) + - TIMER2_CH0 pin (PA6) + - TIMER0_CH0 pin (PA8) diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMERs_parallelsynchro/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMERs_parallelsynchro/main.c new file mode 100644 index 0000000..55ee4b9 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMERs_parallelsynchro/main.c @@ -0,0 +1,221 @@ +/*! + \file main.c + \brief TIMERs parallel synchro demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +/* configure the GPIO ports */ +void gpio_config(void); +/* configure the TIMER peripheral */ +void timer_config(void); + +/** + \brief configure the GPIO ports + \param[in] none + \param[out] none + \retval none + */ +void gpio_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_AF); + + /*configure PA0(TIMER1 CH0) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0); + + /*configure PA6(TIMER2 CH0) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_6); + + /*configure PA8(TIMER0 CH0) as alternate function*/ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_8); +} + +/** + \brief configure the TIMER peripheral + \param[in] none + \param[out] none + \retval none + */ +void timer_config(void) +{ + /* timers synchronisation in parallel mode ---------------------------- + 1/TIMER1 is configured as master timer: + - PWM mode is used. + - The TIMER1 update event is used as trigger output. + + 2/TIMER2 is slave for TIMER1, + - PWM mode is used. + - The ITR1(TIMER1) is used as input trigger. + - external clock mode is used, the counter counts on the rising edges of + the selected trigger. + + 3/TIMER0 is slave for TIMER1, + - PWM mode is used. + - The ITR1(TIMER1) is used as input trigger. + - external clock mode is used, the counter counts on the rising edges of + the selected trigger. + -------------------------------------------------------------------- */ + timer_oc_parameter_struct timer_ocinitpara; + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER0); + rcu_periph_clock_enable(RCU_TIMER1); + rcu_periph_clock_enable(RCU_TIMER2); + + /* TIMER1 configuration */ + timer_deinit(TIMER1); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + timer_initpara.prescaler = 5399; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 3999; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER1, &timer_initpara); + + /* initialize TIMER channel output parameter struct */ + timer_channel_output_struct_para_init(&timer_ocinitpara); + /* CH1 configuration in PWM0 mode */ + timer_ocinitpara.outputstate = TIMER_CCX_ENABLE; + timer_ocinitpara.outputnstate = TIMER_CCXN_DISABLE; + timer_ocinitpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocinitpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocinitpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + timer_ocinitpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + timer_channel_output_config(TIMER1, TIMER_CH_0, &timer_ocinitpara); + + timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0, 2000); + timer_channel_output_mode_config(TIMER1, TIMER_CH_0, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER1, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); + + /* auto-reload preload enable */ + timer_auto_reload_shadow_enable(TIMER1); + /* select the master slave mode */ + timer_master_slave_mode_config(TIMER1, TIMER_MASTER_SLAVE_MODE_ENABLE); + /* TIMER1 update event is used as trigger output */ + timer_master_output_trigger_source_select(TIMER1, TIMER_TRI_OUT_SRC_UPDATE); + + /* TIMER2 configuration */ + timer_deinit(TIMER2); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + timer_initpara.prescaler = 0; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 1; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER2, &timer_initpara); + + /* initialize TIMER channel output parameter struct */ + timer_channel_output_struct_para_init(&timer_ocinitpara); + /* CH0 configuration in PWM mode 0 */ + timer_ocinitpara.outputstate = TIMER_CCX_ENABLE; + timer_ocinitpara.outputnstate = TIMER_CCXN_DISABLE; + timer_ocinitpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocinitpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocinitpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + timer_ocinitpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + timer_channel_output_config(TIMER2, TIMER_CH_0, &timer_ocinitpara); + + timer_channel_output_pulse_value_config(TIMER2, TIMER_CH_0, 1); + timer_channel_output_mode_config(TIMER2, TIMER_CH_0, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER2, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); + + /* auto-reload preload enable */ + timer_auto_reload_shadow_enable(TIMER2); + /* slave mode selection: TIMER2 */ + timer_slave_mode_select(TIMER2, TIMER_SLAVE_MODE_EXTERNAL0); + timer_input_trigger_source_select(TIMER2, TIMER_SMCFG_TRGSEL_ITI1); + /* select the master slave mode */ + timer_master_slave_mode_config(TIMER2, TIMER_MASTER_SLAVE_MODE_ENABLE); + /* TIMER2 update event is used as trigger output */ + timer_master_output_trigger_source_select(TIMER2, TIMER_TRI_OUT_SRC_UPDATE); + + /* TIMER0 configuration */ + timer_deinit(TIMER0); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + timer_initpara.prescaler = 0; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 1; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER0, &timer_initpara); + + /* initialize TIMER channel output parameter struct */ + timer_channel_output_struct_para_init(&timer_ocinitpara); + /* CH0 configuration in PWM0 mode */ + timer_ocinitpara.outputstate = TIMER_CCX_ENABLE; + timer_ocinitpara.outputnstate = TIMER_CCXN_DISABLE; + timer_ocinitpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocinitpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocinitpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + timer_ocinitpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + timer_channel_output_config(TIMER0, TIMER_CH_0, &timer_ocinitpara); + + timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_0, 1); + timer_channel_output_mode_config(TIMER0, TIMER_CH_0, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(TIMER0, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); + + /* auto-reload preload enable */ + timer_auto_reload_shadow_enable(TIMER0); + /* TIMER0 output enable */ + timer_primary_output_config(TIMER0, ENABLE); + /* slave mode selection: TIMER0 */ + timer_slave_mode_select(TIMER0, TIMER_SLAVE_MODE_EXTERNAL0); + timer_input_trigger_source_select(TIMER0, TIMER_SMCFG_TRGSEL_ITI1); + + /* TIMER counter enable */ + timer_enable(TIMER1); + timer_enable(TIMER2); + timer_enable(TIMER0); +} + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + gpio_config(); + timer_config(); + + while (1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMERs_parallelsynchro/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMERs_parallelsynchro/readme.txt new file mode 100644 index 0000000..3667f3d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/TIMER/TIMERs_parallelsynchro/readme.txt @@ -0,0 +1,69 @@ +/*! + \file readme.txt + \brief description of the TIMERs parallel synchro demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to synchronize +TIMER peripherals in parallel mode. + + In this example three timers are used: + 1/TIMER1 is configured as master timer: + - PWM mode is used. + - The TIMER1 update event is used as trigger output. + + 2/TIMER2 is slave for TIMER1, + - PWM mode is used. + - The ITR1(TIMER1) is used as input trigger. + - external clock mode is used, the counter counts on the rising edges of + the selected trigger. + + 3/TIMER0 is slave for TIMER1, + - PWM mode is used. + - The ITR1(TIMER1) is used as input trigger. + - external clock mode is used, the counter counts on the rising edges of + the selected trigger. + + The TIMERxCLK is fixed to 108 MHz, the TIMER1 counter clock is: +108MHz/5400= 20KHz. + + The master timer TIMER1 CH0(PA0) is running at TIMER1 frequency: + TIMER1 frequency = (TIMER1 counter clock)/ (TIMER1 period + 1) = 5 Hz +and the duty cycle = TIMER1_CH0CV/(TIMER1_CAR + 1) = 50% + + The TIMER2 CH0(PA6) is running: + - At (TIMER1 frequency)/ (TIMER2 period + 1) = 2.5 Hz and a duty cycle + equal to TIMER2_CH0CV/(TIMER2_CAR + 1) = 50% + + The TIMER0 CH0(PA8) is running: + - At (TIMER1 frequency)/ (TIMER0 period + 1) = 2.5 Hz and a duty cycle + equal to TIMER2_CH0CV/(TIMER2_CAR + 1) = 50% + \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver/main.c new file mode 100644 index 0000000..a370a01 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver/main.c @@ -0,0 +1,103 @@ +/*! + \file main.c + \brief USART DMA transmitter receiver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +uint8_t rxbuffer[10]; +uint8_t txbuffer[] = "\n\rUSART DMA receive and transmit example, please input 10 bytes:\n\r"; +#define ARRAYNUM(arr_name) (uint32_t)(sizeof(arr_name) / sizeof(*(arr_name))) + +/*! + \brief main function + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + dma_parameter_struct dma_init_struct; + /* enable DMA0 */ + rcu_periph_clock_enable(RCU_DMA0); + /* initialize USART */ + gd_eval_com_init(EVAL_COM0); + /* deinitialize DMA channel3(USART0 tx) */ + dma_deinit(DMA0, DMA_CH3); + dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; + dma_init_struct.memory_addr = (uint32_t)txbuffer; + dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; + dma_init_struct.number = ARRAYNUM(txbuffer); + dma_init_struct.periph_addr = (uint32_t)&USART_DATA(USART0); + dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; + dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH; + dma_init(DMA0, DMA_CH3, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA0, DMA_CH3); + /* enable DMA channel3 */ + dma_channel_enable(DMA0, DMA_CH3); + + /* USART DMA enable for transmission and reception */ + usart_dma_transmit_config(USART0, USART_DENT_ENABLE); + usart_dma_receive_config(USART0, USART_DENR_ENABLE); + + /* wait DMA Channel transfer complete */ + while(RESET == dma_flag_get(DMA0, DMA_CH3, DMA_FLAG_FTF)); + while(1){ + /* deinitialize DMA channel4 (USART0 rx) */ + dma_deinit(DMA0, DMA_CH4); + dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY; + dma_init_struct.memory_addr = (uint32_t)rxbuffer; + dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; + dma_init_struct.number = 10; + dma_init_struct.periph_addr = (uint32_t)&USART_DATA(USART0); + dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; + dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH; + dma_init(DMA0, DMA_CH4, &dma_init_struct); + /* configure DMA mode */ + dma_circulation_disable(DMA0, DMA_CH4); + /* enable DMA channel4 */ + dma_channel_enable(DMA0, DMA_CH4); + + /* wait DMA channel transfer complete */ + while(RESET == dma_flag_get(DMA0, DMA_CH4, DMA_FLAG_FTF)); + printf("\n\r%s\n\r", rxbuffer); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver/readme.txt new file mode 100644 index 0000000..94fb58d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver/readme.txt @@ -0,0 +1,43 @@ +/*! + \file readme.txt + \brief USART DMA transmitter receiver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to use the USART +DMA transmit and receive. + + Firstly, the USART sends the strings to the hyperterminal and then loops waiting for +receiving max 10 bytes data from the hyperterminal.If the number of data you enter +equal with or more than 10 bytes, USART will send 10 bytes to the hyperterminal. + + JP5 and JP6 must be fitted. + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver_interrupt/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver_interrupt/gd32vf103_it.c new file mode 100644 index 0000000..b77d974 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver_interrupt/gd32vf103_it.c @@ -0,0 +1,66 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_it.h" +#include "gd32vf103v_eval.h" + +extern FlagStatus g_transfer_complete; + +/*! + \brief this function handles DMA0_Channel3_IRQHandler interrupt + \param[in] none + \param[out] none + \retval none +*/ +void DMA0_Channel3_IRQHandler(void) +{ + if(dma_interrupt_flag_get(DMA0, DMA_CH3, DMA_INT_FLAG_FTF)){ + dma_interrupt_flag_clear(DMA0, DMA_CH3, DMA_INT_FLAG_G); + g_transfer_complete = SET; + } +} + +/*! + \brief this function handles DMA0_Channel4_IRQHandler interrupt + \param[in] none + \param[out] none + \retval none +*/ +void DMA0_Channel4_IRQHandler(void) +{ + if(dma_interrupt_flag_get(DMA0, DMA_CH4, DMA_INT_FLAG_FTF)){ + dma_interrupt_flag_clear(DMA0, DMA_CH4, DMA_INT_FLAG_G); + g_transfer_complete = SET; + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver_interrupt/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver_interrupt/gd32vf103_it.h new file mode 100644 index 0000000..24800b9 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver_interrupt/gd32vf103_it.h @@ -0,0 +1,46 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ +/* this function handles DMA0_Channel3_IRQHandler interrupt */ +void DMA0_Channel3_IRQHandler(void); +/* this function handles DMA0_Channel4_IRQHandler interrupt */ +void DMA0_Channel4_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver_interrupt/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver_interrupt/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver_interrupt/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver_interrupt/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver_interrupt/main.c new file mode 100644 index 0000000..ae18029 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver_interrupt/main.c @@ -0,0 +1,125 @@ +/*! + \file main.c + \brief transmit/receive data using DMA interrupt + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" + +#define ARRAYNUM(arr_nanme) (uint32_t)(sizeof(arr_nanme) / sizeof(*(arr_nanme))) + +__IO FlagStatus g_transfer_complete = RESET; +uint8_t rxbuffer[10]; +uint8_t txbuffer[] = "\n\rUSART DMA interrupt receive and transmit example, please input 10 bytes:\n\r"; + +/*! + \brief main function + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + dma_parameter_struct dma_init_struct; + /* enable DMA0 clock */ + rcu_periph_clock_enable(RCU_DMA0); + /* initialize USART */ + gd_eval_com_init(EVAL_COM0); + /*configure DMA0 interrupt*/ + eclic_global_interrupt_enable(); + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL3_PRIO1); + eclic_irq_enable(DMA0_Channel3_IRQn, 1, 0); + eclic_irq_enable(DMA0_Channel4_IRQn, 2, 0); + + /* deinitialize DMA channel3(USART0 tx) */ + dma_deinit(DMA0, DMA_CH3); + dma_struct_para_init(&dma_init_struct); + + dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; + dma_init_struct.memory_addr = (uint32_t)txbuffer; + dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; + dma_init_struct.number = ARRAYNUM(txbuffer); + dma_init_struct.periph_addr = (uint32_t)&USART_DATA(USART0); + dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; + dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH; + dma_init(DMA0, DMA_CH3, &dma_init_struct); + + /* deinitialize DMA channel4 (USART0 rx) */ + dma_deinit(DMA0, DMA_CH4); + dma_struct_para_init(&dma_init_struct); + + dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY; + dma_init_struct.memory_addr = (uint32_t)rxbuffer; + dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; + dma_init_struct.number = 10; + dma_init_struct.periph_addr = (uint32_t)&USART_DATA(USART0); + dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + dma_init_struct.memory_width = DMA_PERIPHERAL_WIDTH_8BIT; + dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH; + dma_init(DMA0, DMA_CH4, &dma_init_struct); + + /* configure DMA mode */ + dma_circulation_disable(DMA0, DMA_CH3); + dma_memory_to_memory_disable(DMA0, DMA_CH3); + dma_circulation_disable(DMA0, DMA_CH4); + dma_memory_to_memory_disable(DMA0, DMA_CH4); + + /* USART DMA0 enable for reception */ + usart_dma_receive_config(USART0, USART_DENR_ENABLE); + /* enable DMA0 channel4 transfer complete interrupt */ + dma_interrupt_enable(DMA0, DMA_CH4, DMA_INT_FTF); + /* enable DMA0 channel4 */ + dma_channel_enable(DMA0, DMA_CH4); + /* USART DMA0 enable for transmission */ + usart_dma_transmit_config(USART0, USART_DENT_ENABLE); + /* enable DMA0 channel3 transfer complete interrupt */ + dma_interrupt_enable(DMA0, DMA_CH3, DMA_INT_FTF); + /* enable DMA0 channel3 */ + dma_channel_enable(DMA0, DMA_CH3); + + /* waiting for the transfer to complete*/ + while(RESET == g_transfer_complete); + + g_transfer_complete = RESET; + + /* waiting for the transfer to complete*/ + while(RESET == g_transfer_complete); + + printf("\n\r%s\n\r", rxbuffer); + while(1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver_interrupt/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver_interrupt/readme.txt new file mode 100644 index 0000000..dd061a7 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/DMA_transmitter&receiver_interrupt/readme.txt @@ -0,0 +1,44 @@ +/*! + \file readme.txt + \brief description of transmit/receive data using DMA interrupt + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it provides a description +of how to use DMA channel3 to transmit data from RAM memory to USART data +register and how to use DMA channel4 to receive data from USART data register +to RAM memory. + + Firstly, the USART sends the strings to the hyperterminal and then waiting for +receiving max 10 bytes data from the hyperterminal. If the number of data you enter +equal with or more than 10 bytes, USART will send 10 bytes to the hyperterminal. + + JP5 and JP6 must be fitted. \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Half_duplex_transmitter&receiver/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Half_duplex_transmitter&receiver/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Half_duplex_transmitter&receiver/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Half_duplex_transmitter&receiver/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Half_duplex_transmitter&receiver/main.c new file mode 100644 index 0000000..695c8d6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Half_duplex_transmitter&receiver/main.c @@ -0,0 +1,179 @@ +/*! + \file main.c + \brief USART half-duplex transmitter and receiver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +#define ARRAYNUM(arr_nanme) (uint32_t)(sizeof(arr_nanme) / sizeof(*(arr_nanme))) +#define TRANSMIT_SIZE0 (ARRAYNUM(transmitter_buffer0)) +#define TRANSMIT_SIZE1 (ARRAYNUM(transmitter_buffer1)) + +uint8_t transmitter_buffer0[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F}; +uint8_t transmitter_buffer1[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F}; +uint8_t receiver_buffer0[TRANSMIT_SIZE1]; +uint8_t receiver_buffer1[TRANSMIT_SIZE0]; +uint8_t transfersize0 = TRANSMIT_SIZE0; +uint8_t transfersize1 = TRANSMIT_SIZE1; +__IO uint8_t txcount0 = 0; +__IO uint16_t rxcount0 = 0; +__IO uint8_t txcount1 = 0; +__IO uint16_t rxcount1 = 0; +ErrStatus state1 = ERROR; +ErrStatus state2 = ERROR; + +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint16_t length); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + + /* enable USART and GPIOA clock */ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_USART0); + rcu_periph_clock_enable(RCU_USART1); + + /* configure USART0 Tx as alternate function push-pull */ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9); + /* configure USART1 Tx as alternate function push-pull */ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2); + /* configure the USART0 Tx pin and USART1 Tx pin */ + + /* USART0 and USART1 baudrate configuration */ + usart_baudrate_set(USART0, 115200); + usart_baudrate_set(USART1, 115200); + + /* enable USART0 half duplex mode*/ + usart_halfduplex_enable(USART0); + /* enable USART1 half duplex mode*/ + usart_halfduplex_enable(USART1); + + /* configure USART transmitter */ + usart_transmit_config(USART0, USART_TRANSMIT_ENABLE); + usart_transmit_config(USART1, USART_TRANSMIT_ENABLE); + + /* configure USART receiver */ + usart_receive_config(USART0, USART_RECEIVE_ENABLE); + usart_receive_config(USART1, USART_RECEIVE_ENABLE); + + /* enable USART */ + usart_enable(USART0); + usart_enable(USART1); + + /* clear the USART1 data register */ + usart_data_receive(USART1); + /* USART0 transmit and USART1 receive */ + while(transfersize0--) + { + /* wait until end of transmit */ + while(RESET == usart_flag_get(USART0, USART_FLAG_TBE)); + usart_data_transmit(USART0, transmitter_buffer0[txcount0++]); + + while(RESET == usart_flag_get(USART1, USART_FLAG_RBNE)); + /* store the received byte in the receiver_buffer1 */ + receiver_buffer1[rxcount0++] = usart_data_receive(USART1); + } + /* clear the USART0 data register */ + usart_data_receive(USART0); + /* USART1 transmit and USART0 receive */ + while(transfersize1--) + { + /* wait until end of transmit */ + while(RESET == usart_flag_get(USART1, USART_FLAG_TBE)); + usart_data_transmit(USART1, transmitter_buffer1[txcount1++]); + + while(RESET == usart_flag_get(USART0, USART_FLAG_RBNE)); + /* store the received byte in the receiver_buffer0 */ + receiver_buffer0[rxcount1++] = usart_data_receive(USART0); + } + + /* compare the received data with the send ones */ + state1 = memory_compare(transmitter_buffer0, receiver_buffer1, TRANSMIT_SIZE0); + state2 = memory_compare(transmitter_buffer1, receiver_buffer0, TRANSMIT_SIZE1); + if(SUCCESS == state1){ + /* if the data transmitted from USART0 and received by USART1 are the same */ + gd_eval_led_on(LED2); + }else{ + /* if the data transmitted from USART0 and received by USART1 are not the same */ + gd_eval_led_off(LED2); + } + if(SUCCESS == state2){ + /* if the data transmitted from USART1 and received by USART0 are the same */ + gd_eval_led_on(LED3); + }else{ + /* if the data transmitted from USART1 and received by USART0 are not the same */ + gd_eval_led_off(LED3); + } + while(1){ + } +} + +/*! + \brief memory compare function + \param[in] src: source data + \param[in] dst: destination data + \param[in] length: the compare data length + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint16_t length) +{ + while(length--){ + if(*src++ != *dst++){ + return ERROR; + } + } + return SUCCESS; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Half_duplex_transmitter&receiver/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Half_duplex_transmitter&receiver/readme.txt new file mode 100644 index 0000000..98d562f --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Half_duplex_transmitter&receiver/readme.txt @@ -0,0 +1,43 @@ +/*! + \file readme.txt + \brief description of the USART HalfDuplex + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it provides a basic communication +USART0 whith USART1 in Half-Duplex mode. + + The transmitter_buffer0 and transmitter_buffer1 are sent by USART0 and USART1 respectively and +displayed in HyperTerminal. If the data received by USART0 is equal to transmitter_buffer1, LED2 +is turned on. If the data received by USART1 is equal to transmitter_buffer0, LED3 is turned on. + + connect USART0_Tx(PA9) to USART1_Tx(PA2) + JP5 and JP6 must be fitted. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Printf/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Printf/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Printf/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Printf/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Printf/main.c new file mode 100644 index 0000000..360f212 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Printf/main.c @@ -0,0 +1,82 @@ +/*! + \file main.c + \brief USART printf + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* enable GPIO clock */ + rcu_periph_clock_enable(RCU_GPIOA); + + /* enable USART clock */ + rcu_periph_clock_enable(RCU_USART0); + + /* connect port to USARTx_Tx */ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9); + + /* connect port to USARTx_Rx */ + gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_10); + + /* USART configure */ + usart_deinit(USART0); + usart_baudrate_set(USART0, 115200U); + usart_word_length_set(USART0, USART_WL_8BIT); + usart_stop_bit_set(USART0, USART_STB_1BIT); + usart_parity_config(USART0, USART_PM_NONE); + usart_hardware_flow_rts_config(USART0, USART_RTS_DISABLE); + usart_hardware_flow_cts_config(USART0, USART_CTS_DISABLE); + usart_receive_config(USART0, USART_RECEIVE_ENABLE); + usart_transmit_config(USART0, USART_TRANSMIT_ENABLE); + usart_enable(USART0); + + printf("a usart transmit test example!\n"); + while(1); +} + +/* retarget the C library printf function to the USART */ +int _put_char(int ch) +{ + usart_data_transmit(USART0, (uint8_t) ch ); + while ( usart_flag_get(USART0, USART_FLAG_TBE)== RESET){ + } + + return ch; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Printf/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Printf/readme.txt new file mode 100644 index 0000000..09116ba --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Printf/readme.txt @@ -0,0 +1,46 @@ +/*! + \file readme.txt + \brief description of the USART printf + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to retarget the C +library printf function to the USART. + + The USARTx is configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + + JP5 and JP6 must be fitted. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Synchronous/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Synchronous/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Synchronous/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Synchronous/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Synchronous/main.c new file mode 100644 index 0000000..da08d1e --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Synchronous/main.c @@ -0,0 +1,250 @@ +/*! + \file main.c + \brief USART synchronous + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" +#include + +#define txbuffer_size1 (countof(txbuffer1) - 1) +#define txbuffer_size2 (countof(txbuffer2) - 1) +#define DYMMY_BYTE 0x00000000 +#define countof(a) (sizeof(a) / sizeof(*(a))) + +uint8_t txbuffer1[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F}; +uint8_t txbuffer2[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F}; +uint8_t rxbuffer1[txbuffer_size2]; +uint8_t rxbuffer2[txbuffer_size1]; +__IO uint8_t data_read1 = txbuffer_size2; +__IO uint8_t data_read2 = txbuffer_size1; +__IO uint8_t tx_counter1 = 0, rx_counter1 = 0; +__IO uint8_t tx_counter2 = 0, rx_counter2 = 0; +__IO ErrStatus state1 = ERROR; +__IO ErrStatus state2 = ERROR; + +void usart_config(void); +void spi_config(void); +void led_init(void); +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint16_t length); + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* initialize leds */ + led_init(); + /* turn off LED1~4 */ + gd_eval_led_off(LED1); + gd_eval_led_off(LED2); + gd_eval_led_off(LED3); + gd_eval_led_off(LED4); + + /* configure USART */ + usart_config(); + + /* configure SPI */ + spi_config(); + + while(data_read2--){ + while(RESET == usart_flag_get(USART0, USART_FLAG_TBE)){ + } + /* write one byte in the USART0 data register */ + usart_data_transmit(USART0, txbuffer1[tx_counter1++]); + /* wait until end of transmit */ + while(RESET == usart_flag_get(USART0, USART_FLAG_TC)){ + } + /* wait the byte is entirely received by SPI0 */ + while(RESET == spi_i2s_flag_get(SPI0, SPI_FLAG_RBNE)){ + } + /* store the received byte in the rxbuffer2 */ + rxbuffer2[rx_counter2++] = spi_i2s_data_receive(SPI0); + } + + /* clear the USART0 data register */ + usart_data_receive(USART0); + + while(data_read1--){ + /* wait until end of transmit */ + while(RESET == spi_i2s_flag_get(SPI0, SPI_FLAG_TBE)){ + } + /* write one byte in the SPI0 transmit data register */ + spi_i2s_data_transmit(SPI0, txbuffer2[tx_counter2++]); + + /* send a dummy byte to generate clock to slave */ + usart_data_transmit(USART0, DYMMY_BYTE); + /* wait until end of transmit */ + while(RESET == usart_flag_get(USART0, USART_FLAG_TC)){ + } + /* wait the byte is entirely received by USART0 */ + while(RESET == usart_flag_get(USART0, USART_FLAG_RBNE)){ + } + /* store the received byte in the rxbuffer1 */ + rxbuffer1[rx_counter1++] = usart_data_receive(USART0); + } + + /* check the received data with the send ones */ + state1 = memory_compare(txbuffer1, rxbuffer2, txbuffer_size1); + state2 = memory_compare(txbuffer2, rxbuffer1, txbuffer_size2); + + if(SUCCESS == state1){ + /* if the data transmitted from USART0 and received by SPI0 are the same */ + gd_eval_led_on(LED1); + gd_eval_led_on(LED3); + }else{ + /* if the data transmitted from USART0 and received by SPI0 are not the same */ + gd_eval_led_off(LED1); + gd_eval_led_off(LED3); + } + if(SUCCESS == state2){ + /* if the data transmitted from SPI0 and received by USART0 are the same */ + gd_eval_led_on(LED2); + gd_eval_led_on(LED4); + }else{ + /* if the data transmitted from SPI0 and received by USART0 are not the same */ + gd_eval_led_off(LED2); + gd_eval_led_off(LED4); + } + while(1){ + } +} +/*! + \brief configure USART + \param[in] none + \param[out] none + \retval none +*/ +void usart_config(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_USART0); + rcu_periph_clock_enable(RCU_AF); + + /* configure USART Tx as alternate function push-pull */ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9|GPIO_PIN_8); + gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_10); + + /* configure USART synchronous mode */ + usart_synchronous_clock_enable(USART0); + usart_synchronous_clock_config(USART0, USART_CLEN_EN, USART_CPH_2CK, USART_CPL_HIGH); + + usart_baudrate_set(USART0, 115200); + /* configure USART transmitter */ + usart_transmit_config(USART0, USART_TRANSMIT_ENABLE); + /* configure USART receiver */ + usart_receive_config(USART0, USART_RECEIVE_ENABLE); + /* enable USART */ + usart_enable(USART0); +} + +/*! + \brief configure SPI + \param[in] none + \param[out] none + \retval none +*/ +void spi_config(void) +{ + spi_parameter_struct spi_init_parameter; + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_SPI0); + rcu_periph_clock_enable(RCU_AF); + + spi_i2s_deinit(SPI0); + + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_10MHZ, GPIO_PIN_5 | GPIO_PIN_6); + gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_10MHZ, GPIO_PIN_7); + + /* configure SPI0 */ + spi_init_parameter.device_mode = SPI_SLAVE; + spi_init_parameter.trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_init_parameter.frame_size = SPI_FRAMESIZE_8BIT; + spi_init_parameter.nss = SPI_NSS_SOFT; + spi_init_parameter.endian = SPI_ENDIAN_LSB; + spi_init_parameter.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; + spi_init_parameter.prescale = SPI_PSC_32; + spi_init(SPI0, &spi_init_parameter); + + /* SPI0 enable */ + spi_enable(SPI0); +} + +/*! + \brief initialize leds + \param[in] none + \param[out] none + \retval none +*/ +void led_init(void) +{ + gd_eval_led_init(LED1); + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + gd_eval_led_init(LED4); + +} + +/*! + \brief memory compare function + \param[in] src: source data + \param[in] dst: destination data + \param[in] length: the compare data length + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint16_t length) +{ + while(length--){ + if(*src++ != *dst++){ + return ERROR; + } + } + return SUCCESS; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Synchronous/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Synchronous/readme.txt new file mode 100644 index 0000000..8cc35cb --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Synchronous/readme.txt @@ -0,0 +1,47 @@ +/*! + \file readme.txt + \brief USART synchronous + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it provides a basic +communication between USART0 (Synchronous mode) and SPI0. First, USART0 +transmit a series of data to SPI0, then SPI0 transmit a series of data +to USART0. Compare the transmitted data and the received data. If the +data transmitted from USART0 and received by SPI0 are the same, LED1 and +LED3 will on, otherwise off. If the data transmitted from SPI0 and +received by USART0 are the same, LED2 and LED4 will on, otherwise off. + + connect SPI0 SCK pin(PA5) TO USART0_CK pin(PA8) + connect SPI0 MISO pin(PA6) TO USART0_RX pin(PA10) + connect SPI0 MOSI pin(PA7) TO USART0_TX pin(PA9) + JP5 and JP6 must be fitted. + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Transmitter&receiver_interrupt/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Transmitter&receiver_interrupt/gd32vf103_it.c new file mode 100644 index 0000000..ded0b43 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Transmitter&receiver_interrupt/gd32vf103_it.c @@ -0,0 +1,67 @@ +/*! + \file gd32vf103_it.c + \brief interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_it.h" +#include "gd32vf103v_eval.h" + +extern uint8_t tx_size; +extern uint8_t rx_size; +extern __IO uint8_t txcount; +extern __IO uint16_t rxcount; +extern uint8_t rxbuffer[32]; +extern uint8_t txbuffer[]; + +/*! + \brief this function handles USART RBNE interrupt request and TBE interrupt request + \param[in] none + \param[out] none + \retval none +*/ +void USART0_IRQHandler(void) +{ + if(RESET != usart_interrupt_flag_get(USART0, USART_INT_FLAG_RBNE)){ + /* receive data */ + rxbuffer[rxcount++] = usart_data_receive(USART0); + if(rxcount == rx_size){ + usart_interrupt_disable(USART0, USART_INT_RBNE); + } + } + if(RESET != usart_interrupt_flag_get(USART0, USART_INT_FLAG_TBE)){ + /* transmit data */ + usart_data_transmit(USART0, txbuffer[txcount++]); + if(txcount == tx_size){ + usart_interrupt_disable(USART0, USART_INT_TBE); + } + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Transmitter&receiver_interrupt/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Transmitter&receiver_interrupt/gd32vf103_it.h new file mode 100644 index 0000000..0bec519 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Transmitter&receiver_interrupt/gd32vf103_it.h @@ -0,0 +1,44 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ +/* this function handles USART RBNE interrupt request and TBE interrupt request */ +void USART0_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Transmitter&receiver_interrupt/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Transmitter&receiver_interrupt/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Transmitter&receiver_interrupt/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Transmitter&receiver_interrupt/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Transmitter&receiver_interrupt/main.c new file mode 100644 index 0000000..3e3b758 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Transmitter&receiver_interrupt/main.c @@ -0,0 +1,79 @@ +/*! + \file main.c + \brief USART transmit and receive interrupt + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include +#include "gd32vf103v_eval.h" + +#define ARRAYNUM(arr_nanme) (uint32_t)(sizeof(arr_nanme) / sizeof(*(arr_nanme))) +#define TRANSMIT_SIZE (ARRAYNUM(txbuffer) - 1) + +uint8_t txbuffer[] = "\n\rUSART interrupt test\n\r"; +uint8_t rxbuffer[32]; +uint8_t tx_size = TRANSMIT_SIZE; +uint8_t rx_size = 32; +__IO uint8_t txcount = 0; +__IO uint16_t rxcount = 0; + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* USART interrupt configuration */ + eclic_global_interrupt_enable(); + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL3_PRIO1); + eclic_irq_enable(USART0_IRQn, 1, 0); + /* configure COM0 */ + gd_eval_com_init(EVAL_COM0); + /* enable USART TBE interrupt */ + usart_interrupt_enable(USART0, USART_INT_TBE); + + /* wait until USART send the transmitter_buffer */ + while(txcount < tx_size); + + while(RESET == usart_flag_get(USART0, USART_FLAG_TC)); + + usart_interrupt_enable(USART0, USART_INT_RBNE); + + /* wait until USART receive the receiver_buffer */ + while(rxcount < rx_size); + if(rxcount == rx_size) + printf("\n\rUSART receive successfully!\n\r"); + while(1); +} + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Transmitter&receiver_interrupt/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Transmitter&receiver_interrupt/readme.txt new file mode 100644 index 0000000..6c04532 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USART/Transmitter&receiver_interrupt/readme.txt @@ -0,0 +1,43 @@ +/*! + \file readme.txt + \brief description of the USART transmit and receive interrupt + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows how to use the USART +transmit and receive interrupts to communicate with the hyperterminal. + + Firstly, the USART sends the strings to the hyperterminal and still waits for +receiving data from the hyperterminal. Only the number of data you enter is equal +to or more than 32 bytes, USART will send strings: "USART receive successfully!" +(the reception is stopped when this maximum receive value is reached). + JP5 and JP6 must be fitted. + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Eclipse/usbd_audio/.cproject b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Eclipse/usbd_audio/.cproject new file mode 100644 index 0000000..5177991 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Eclipse/usbd_audio/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Eclipse/usbd_audio/.project b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Eclipse/usbd_audio/.project new file mode 100644 index 0000000..7cf1add --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Eclipse/usbd_audio/.project @@ -0,0 +1,608 @@ + + + usbd_audio + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Examples + 2 + virtual:/virtual + + + Firmware + 2 + virtual:/virtual + + + Utilities + 2 + virtual:/virtual + + + Examples/USBFS + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral + 2 + virtual:/virtual + + + Firmware/GD32VF103_usbfs_driver + 2 + virtual:/virtual + + + Firmware/RISCV + 2 + virtual:/virtual + + + Utilities/gd32vf103v_eval.c + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_eval.c + + + Utilities/gd32vf103v_eval.h + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_eval.h + + + Examples/USBFS/USB_Device + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Include + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Source + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/gd32vf103.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/gd32vf103.h + + + Firmware/GD32VF103_standard_peripheral/system_gd32vf103.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/system_gd32vf103.h + + + Firmware/GD32VF103_usbfs_driver/Include + 2 + virtual:/virtual + + + Firmware/GD32VF103_usbfs_driver/Source + 2 + virtual:/virtual + + + Firmware/RISCV/drivers + 2 + virtual:/virtual + + + Firmware/RISCV/env_Eclipse + 2 + virtual:/virtual + + + Firmware/RISCV/stubs + 2 + virtual:/virtual + + + Examples/USBFS/USB_Device/Audio + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_core.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_core.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_dev.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_dev.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_hw.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_hw.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_regs.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_regs.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usbd_int.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usbd_int.h + + + Firmware/GD32VF103_usbfs_driver/Include/usb_ch9_std.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usb_ch9_std.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbd_core.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbd_core.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbd_enum.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbd_enum.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbd_transc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbd_transc.h + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usb_core.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_core.c + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usb_dev.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_dev.c + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usbd_int.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usbd_int.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbd_core.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbd_core.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbd_enum.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbd_enum.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbd_transc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbd_transc.c + + + Firmware/RISCV/drivers/n200_eclic.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_eclic.h + + + Firmware/RISCV/drivers/n200_func.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_func.c + + + Firmware/RISCV/drivers/n200_func.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_func.h + + + Firmware/RISCV/drivers/n200_timer.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_timer.h + + + Firmware/RISCV/drivers/riscv_bits.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_bits.h + + + Firmware/RISCV/drivers/riscv_const.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_const.h + + + Firmware/RISCV/drivers/riscv_encoding.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_encoding.h + + + Firmware/RISCV/env_Eclipse/GD32VF103xB.lds + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/GD32VF103xB.lds + + + Firmware/RISCV/env_Eclipse/entry.S + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/entry.S + + + Firmware/RISCV/env_Eclipse/handlers.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/handlers.c + + + Firmware/RISCV/env_Eclipse/init.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/init.c + + + Firmware/RISCV/env_Eclipse/start.S + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/start.S + + + Firmware/RISCV/env_Eclipse/your_printf.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/your_printf.c + + + Firmware/RISCV/stubs/_exit.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/_exit.c + + + Firmware/RISCV/stubs/close.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/close.c + + + Firmware/RISCV/stubs/fstat.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/fstat.c + + + Firmware/RISCV/stubs/isatty.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/isatty.c + + + Firmware/RISCV/stubs/lseek.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/lseek.c + + + Firmware/RISCV/stubs/read.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/read.c + + + Firmware/RISCV/stubs/sbrk.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/sbrk.c + + + Firmware/RISCV/stubs/stub.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/stub.h + + + Firmware/RISCV/stubs/write.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/write.c + + + Firmware/RISCV/stubs/write_hex.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/write_hex.c + + + Examples/USBFS/USB_Device/Audio/Include + 2 + virtual:/virtual + + + Examples/USBFS/USB_Device/Audio/Source + 2 + virtual:/virtual + + + Examples/USBFS/USB_Device/Audio/Include/audio_core.h + 1 + PARENT-2-PROJECT_LOC/Include/audio_core.h + + + Examples/USBFS/USB_Device/Audio/Include/gd32vf103_audio_codec.h + 1 + PARENT-2-PROJECT_LOC/Include/gd32vf103_audio_codec.h + + + Examples/USBFS/USB_Device/Audio/Include/gd32vf103_it.h + 1 + PARENT-2-PROJECT_LOC/Include/gd32vf103_it.h + + + Examples/USBFS/USB_Device/Audio/Include/gd32vf103_libopt.h + 1 + PARENT-2-PROJECT_LOC/Include/gd32vf103_libopt.h + + + Examples/USBFS/USB_Device/Audio/Include/usb_conf.h + 1 + PARENT-2-PROJECT_LOC/Include/usb_conf.h + + + Examples/USBFS/USB_Device/Audio/Include/usbd_audio_out_if.h + 1 + PARENT-2-PROJECT_LOC/Include/usbd_audio_out_if.h + + + Examples/USBFS/USB_Device/Audio/Include/usbd_conf.h + 1 + PARENT-2-PROJECT_LOC/Include/usbd_conf.h + + + Examples/USBFS/USB_Device/Audio/Source/app.c + 1 + PARENT-2-PROJECT_LOC/Source/app.c + + + Examples/USBFS/USB_Device/Audio/Source/audio_core.c + 1 + PARENT-2-PROJECT_LOC/Source/audio_core.c + + + Examples/USBFS/USB_Device/Audio/Source/gd32vf103_audio_codec.c + 1 + PARENT-2-PROJECT_LOC/Source/gd32vf103_audio_codec.c + + + Examples/USBFS/USB_Device/Audio/Source/gd32vf103_hw.c + 1 + PARENT-2-PROJECT_LOC/Source/gd32vf103_hw.c + + + Examples/USBFS/USB_Device/Audio/Source/gd32vf103_it.c + 1 + PARENT-2-PROJECT_LOC/Source/gd32vf103_it.c + + + Examples/USBFS/USB_Device/Audio/Source/system_gd32vf103.c + 1 + PARENT-2-PROJECT_LOC/Source/system_gd32vf103.c + + + Examples/USBFS/USB_Device/Audio/Source/usbd_audio_out_if.c + 1 + PARENT-2-PROJECT_LOC/Source/usbd_audio_out_if.c + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Eclipse/usbd_audio/.settings/language.settings.xml b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Eclipse/usbd_audio/.settings/language.settings.xml new file mode 100644 index 0000000..69533d1 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Eclipse/usbd_audio/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/audio_core.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/audio_core.h new file mode 100644 index 0000000..74d2a3b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/audio_core.h @@ -0,0 +1,262 @@ +/*! + \file audio_core.h + \brief the header file of USB audio device class core functions + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef AUDIO_CORE_H +#define AUDIO_CORE_H + +#include "usbd_enum.h" +#include "usb_ch9_std.h" +#include "usbd_transc.h" + +#define USB_SPEAKER_CONFIG_DESC_SIZE 109 +#define FORMAT_24BIT(X) (uint8_t)(X);(uint8_t)(X >> 8);(uint8_t)(X >> 16) + +/* AudioFreq * DataSize (2 bytes) * NumChannels (Stereo: 2) */ +#define AUDIO_OUT_PACKET (uint32_t)(((USBD_AUDIO_FREQ * 2 * 2) / 1000)) + +/* Number of sub-packets in the audio transfer buffer. You can modify this value but always make sure + that it is an even number and higher than 3 */ +#define OUT_PACKET_NUM 4 + +/* Total size of the audio transfer buffer */ +#define TOTAL_OUT_BUF_SIZE ((uint32_t)(AUDIO_OUT_PACKET * OUT_PACKET_NUM)) + +#define AUDIO_CONFIG_DESC_SIZE 109 +#define AUDIO_INTERFACE_DESC_SIZE 9 +#define USB_AUDIO_DESC_SIZ 0x09 +#define AUDIO_STANDARD_ENDPOINT_DESC_SIZE 0x09 +#define AUDIO_STREAMING_ENDPOINT_DESC_SIZE 0x07 + +#define AUDIO_DESCRIPTOR_TYPE 0x21 +#define USB_DEVICE_CLASS_AUDIO 0x01 +#define AUDIO_SUBCLASS_AUDIOCONTROL 0x01 +#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02 +#define AUDIO_PROTOCOL_UNDEFINED 0x00 +#define AUDIO_STREAMING_GENERAL 0x01 +#define AUDIO_STREAMING_FORMAT_TYPE 0x02 + +/* Audio Descriptor Types */ +#define AUDIO_INTERFACE_DESCRIPTOR_TYPE 0x24 +#define AUDIO_ENDPOINT_DESCRIPTOR_TYPE 0x25 + +/* Audio Control Interface Descriptor Subtypes */ +#define AUDIO_CONTROL_HEADER 0x01 +#define AUDIO_CONTROL_INPUT_TERMINAL 0x02 +#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03 +#define AUDIO_CONTROL_FEATURE_UNIT 0x06 + +#define AUDIO_INPUT_TERMINAL_DESC_SIZE 0x0C +#define AUDIO_OUTPUT_TERMINAL_DESC_SIZE 0x09 +#define AUDIO_STREAMING_INTERFACE_DESC_SIZE 0x07 + +#define AUDIO_CONTROL_MUTE 0x0001 + +#define AUDIO_FORMAT_TYPE_I 0x01 +#define AUDIO_FORMAT_TYPE_III 0x03 + +#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01 +#define AUDIO_ENDPOINT_GENERAL 0x01 + +#define AUDIO_REQ_GET_CUR 0x81 +#define AUDIO_REQ_SET_CUR 0x01 +#define NO_CMD 0xFF + +#define AUDIO_OUT_STREAMING_CTRL 0x02 + +#define DEVICE_ID (0x40022100) + +#define PACKET_SIZE(freq) ((freq * 2) * 2 / 1000) + +#define AUDIO_PACKET_SIZE(frq) (uint8_t)(PACKET_SIZE(frq) & 0xFF), \ + (uint8_t)((PACKET_SIZE(frq) >> 8) & 0xFF) + +#define SAMPLE_FREQ(frq) (uint8_t)(frq), (uint8_t)((frq >> 8)), \ + (uint8_t)((frq >> 16)) + + +#pragma pack(1) + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint8_t bDescriptorSubtype; /*!< HEADER descriptor subtype */ + uint16_t bcdADC; /*!< Audio 1.0 */ + uint16_t wTotalLength; /*!< Total number of bytes returned */ + uint8_t bInCollection; /*!< One OUT AudioStreaming interface in the Collection */ + uint8_t baInterfaceNr; /*!< Interface number of the OUT AudioStreaming interface in the Collection */ +} usb_descriptor_AC_interface_struct; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint8_t bDescriptorSubtype; /*!< AS_GENERAL subtype */ + uint8_t bTerminalLink; /*!< Terminal ID of the Input Terminal, associated with this inetrface */ + uint8_t bDelay; /*!< Total interface delay, expressed in frames */ + uint16_t wFormatTag; /*!< PCM Format */ +} usb_descriptor_AS_interface_struct; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint8_t bDescriptorSubtype; /*!< INPUT_TERMINAL descriptor subtype */ + uint8_t bTerminalID; /*!< ID of this Input Terminal */ + uint16_t wTerminalType; /*!< Terminal Type */ + uint8_t bAssocTerminal; /*!< No association */ + uint8_t bNrChannels; /*!< Signal path */ + uint16_t wChannelConfig; /*!< The Front channel */ + uint8_t iChannelNames; /*!< Unused */ + uint8_t iTerminal; /*!< Index of a string descriptor,describing the Input Terminal */ +} usb_descriptor_input_terminal_struct; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint8_t bDescriptorSubtype; /*!< OUT_TERMINAL descriptor subtype */ + uint8_t bTerminalID; /*!< ID of this Input Terminal */ + uint16_t wTerminalType; /*!< Headphones Terminal Type */ + uint8_t bAssocTerminal; /*!< No association */ + uint8_t bSourceID; /*!< From Feature Unit ID2 */ + uint8_t iTerminal; /*!< Index of a string descriptor,describing the Output Terminal */ +} usb_descriptor_output_terminal_struct; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint8_t bDescriptorSubtype; /*!< FEATURE_UNIT descriptor subtype */ + uint8_t bUnitID; /*!< ID of this Feature Uint */ + uint8_t bSourceID; /*!< The ID of the Entity to which this Feature Unit is connected */ + uint8_t bControlSize; /*!< 2bytes for each element of the bmaControls array */ + uint8_t bmaControls0; /*!< Mute Control on Master Channel */ + uint8_t bmaControls1; /*!< Volume Control on Center Front channel */ + uint8_t iFeature; /*!< Index of a string descriptor, describing the Feature Unit */ +} usb_descriptor_mono_feature_unit_struct; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint8_t bDescriptorSubtype; /*!< FEATURE_UNIT descriptor subtype */ + uint8_t bUnitID; /*!< ID of this Feature Uint */ + uint8_t bSourceID; /*!< The ID of the Entity to which this Feature Unit is connected */ + uint8_t bControlSize; /*!< 2bytes for each element of the bmaControls array */ + uint16_t bmaControls0; /*!< Mute Control on Master Channel */ + uint16_t bmaControls1; /*!< Volume Control on Left Front channel */ + uint16_t bmaControls2; /*!< Volume Control on Right Front channel */ + uint8_t iFeature; /*!< Index of a string descriptor, describing the Feature Unit */ +} usb_descriptor_stereo_feature_unit_struct; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint8_t bDescriptorSubtype; /*!< FORMAT_TYPE subtype */ + uint8_t bFormatType; /*!< The index of FORMAT_TYPE */ + uint8_t bNrChannels; /*!< The number of channel */ + uint8_t bSubFrameSize; /*!< Two bytes per audio subframe */ + uint8_t bBitResolution; /*!< The bits number per sample */ + uint8_t bSamFreqType; /*!< One frequency supported */ + uint8_t bSamFreq[3]; /*!< The frequency of sampling */ +} usb_descriptor_format_type_struct; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint8_t bEndpointAddress; /*!< logical address of the endpoint */ + uint8_t bmAttributes; /*!< endpoint attributes */ + uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */ + uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */ + uint8_t bRefresh; /*!< Unused */ + uint8_t bSynchAddress; /*!< Unused */ +} usb_descriptor_std_endpoint_struct; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint8_t bDescriptorSubtype; /*!< AS_ENDPOINT subtype */ + uint8_t bmAttributes; /*!< endpoint attributes */ + uint8_t bLockDelayUnits; /*!< Unused */ + uint16_t wLockDelay; /*!< Unused */ +} usb_descriptor_AS_endpoint_struct; + +#pragma pack() + +/* USB configuration descriptor struct */ +typedef struct +{ + usb_desc_config Config; + usb_desc_itf Speaker_Std_Interface; + usb_descriptor_AC_interface_struct Speaker_AC_Interface; + usb_descriptor_input_terminal_struct Speaker_IN_Terminal; + usb_descriptor_mono_feature_unit_struct Speaker_Feature_Unit; + usb_descriptor_output_terminal_struct Speaker_OUT_Terminal; + usb_desc_itf Speaker_Std_AS_Interface_ZeroBand; + usb_desc_itf Speaker_Std_AS_Interface_Opera; + usb_descriptor_AS_interface_struct Speaker_AS_Interface; + usb_descriptor_format_type_struct Speaker_Format_TypeI; + usb_descriptor_std_endpoint_struct Speaker_Std_Endpoint; + usb_descriptor_AS_endpoint_struct Speaker_AS_Endpoint; +} usb_descriptor_configuration_set_struct; + +/* AUDIO_FOPS_TypeDef definitions */ +typedef struct _Audio_Fops +{ + uint8_t (*Init) (uint32_t AudioFreq, uint32_t Volume, uint32_t options); + uint8_t (*DeInit) (uint32_t options); + uint8_t (*AudioCmd) (uint8_t* pbuf, uint32_t size, uint8_t cmd); + uint8_t (*VolumeCtl) (uint8_t vol); + uint8_t (*MuteCtl) (uint8_t cmd); + uint8_t (*PeriodicTC) (uint8_t cmd); + uint8_t (*GetState) (void); +}AUDIO_FOPS_TypeDef; + +extern usb_class_core usbd_audio_cb; +extern uint8_t usbd_serial_string[USB_SERIAL_STRING_SIZE]; +extern void* const usbd_strings[USB_STRING_COUNT]; +extern const usb_desc_dev device_descripter; +extern const usb_descriptor_configuration_set_struct configuration_descriptor; + +uint8_t audio_init (usb_dev *pudev, uint8_t config_index); +uint8_t audio_deinit (usb_dev *pudev, uint8_t config_index); +uint8_t audio_req_handler (usb_dev *pudev, usb_req *req); +uint8_t audio_data_in_handler (usb_dev *pudev, uint8_t ep_id); +uint8_t audio_data_out_handler (usb_dev *pudev, uint8_t ep_id); + +#endif diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/gd32vf103_audio_codec.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/gd32vf103_audio_codec.h new file mode 100644 index 0000000..251d08f --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/gd32vf103_audio_codec.h @@ -0,0 +1,215 @@ +/*! + \file gd32vf103_audio_codec.h + \brief the audio codec low layer driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __GD32VF103_AUDIO_CODEC_H +#define __GD32VF103_AUDIO_CODEC_H + +#include "gd32vf103.h" + +/* CONFIGURATION: Audio Codec Driver Configuration parameters */ +//#define AUDIO_USE_MACROS + +/* Audio Transfer mode (DMA, Interrupt or Polling) */ +#define AUDIO_MAL_MODE_NORMAL /* Uncomment this line to enable the audio + Transfer using DMA */ +/* #define AUDIO_MAL_MODE_CIRCULAR */ /* Uncomment this line to enable the audio + Transfer using DMA */ + +/* For the DMA modes select the interrupt that will be used */ +/* #define AUDIO_MAL_DMA_IT_TC_EN */ /* Uncomment this line to enable DMA Transfer Complete interrupt */ +/* #define AUDIO_MAL_DMA_IT_HT_EN */ /* Uncomment this line to enable DMA Half Transfer Complete interrupt */ +/* #define AUDIO_MAL_DMA_IT_TE_EN */ /* Uncomment this line to enable DMA Transfer Error interrupt */ + +/* #define USE_DMA_PAUSE_FEATURE *//* Uncomment this line to enable the use of DMA Pause Feature + When this define is enabled, the Pause function will + just pause/resume the DMA without need to reinitialize the + DMA structure. In this case, the buffer pointer should remain + available after resume. */ + +/* Select the interrupt preemption priority and subpriority for the DMA interrupt */ +#define EVAL_AUDIO_IRQ_PREPRIO 0 /* Select the preemption priority level(0 is the highest) */ +#define EVAL_AUDIO_IRQ_SUBRIO 0 /* Select the sub-priority level (0 is the highest) */ + +/* Uncomment the following line to use the default Codec_TIMEOUT_UserCallback() + function implemented in gd3210c_audio_codec.c file. + Codec_TIMEOUT_UserCallback() function is called whenever a timeout condition + occurs during communication (waiting on an event that doesn't occur, bus + errors, busy devices ...). */ +/* #define USE_DEFAULT_TIMEOUT_CALLBACK */ + + +/* OPTIONAL Configuration defines parameters */ + +/* Uncomment defines below to select standard for audio communication between Codec and I2S peripheral */ +/* #define I2S_STANDARD_PHILLIPS */ +/* #define I2S_STANDARD_MSB */ +#define I2S_STANDARD_LSB + +/* Uncomment the defines below to select if the Master clock mode should be enabled or not */ +#define CODEC_MCLK_ENABLED +/* #deine CODEC_MCLK_DISABLED */ + +/* Uncomment this line to enable verifying data sent to codec after each write operation */ +/* #define VERIFY_WRITTENDATA */ + +/* Hardware Configuration defines parameters */ + +/* I2S peripheral configuration defines */ +#define CODEC_I2S SPI1 +#define CODEC_I2S_CLK RCU_SPI1 +#define CODEC_I2S_ADDRESS 0x4000380C +#define CODEC_I2S_IRQ SPI1_IRQn +#define CODEC_I2S_GPIO1_CLOCK RCU_GPIOB +#define CODEC_I2S_GPIO2_CLOCK RCU_GPIOC +#define CODEC_I2S_WS_PIN GPIO_PIN_12 +#define CODEC_I2S_SCK_PIN GPIO_PIN_13 +#define CODEC_I2S_SD_PIN GPIO_PIN_15 +#define CODEC_I2S_MCK_PIN GPIO_PIN_6 +#define CODEC_I2S_GPIO GPIOB +#define CODEC_I2S_MCK_GPIO GPIOC + +/* I2S DMA Stream definitions */ +#define AUDIO_MAL_DMA_CLOCK RCU_DMA0 +#define AUDIO_MAL_DMA_CHANNEL DMA_CH4 +#define AUDIO_MAL_DMA_IRQ DMA0_Channel4_IRQn +#define AUDIO_MAL_DMA_FLAG_ALL DMA_FLAG_G +#define AUDIO_MAL_DMA_PERIPH_DATA_SIZE DMA_PERIPHERALDATASIZE_HALFWORD +#define AUDIO_MAL_DMA_MEM_DATA_SIZE DMA_MEMORYDATASIZE_HALFWORD +#define DMA_MAX_SZE 0xFFFF +#define AUDIO_MAL_DMA DMA0 + +#define Audio_MAL_IRQHandler DMA0_Channel4_IRQHandler + +/* SPI peripheral configuration defines (control interface of the audio codec) */ +#define CODEC_SPI SPI0 +#define CODEC_SPI_CLK RCU_SPI0 +#define CODEC_SPI_GPIO_CLOCK RCU_GPIOA +#define CODEC_SPI_GPIO_AF GPIO_AF +#define CODEC_SPI_GPIO GPIOA +#define CODEC_SPI_SCL_PIN GPIO_PIN_5 +#define CODEC_SPI_SDA_PIN GPIO_PIN_7 +#define CODEC_SPI_SEL_PIN GPIO_PIN_4 + +/* Maximum Timeout values for flags and events waiting loops. These timeouts are + not based on accurate values, they just guarantee that the application will + not remain stuck if the I2C communication is corrupted. + You may modify these timeout values depending on CPU frequency and application + conditions (interrupts routines ...) */ +#define CODEC_FLAG_TIMEOUT ((uint32_t)0x1000) +#define CODEC_LONG_TIMEOUT ((uint32_t)(300 * CODEC_FLAG_TIMEOUT)) + +/* Audio Codec User defines */ + +/* Codec output DEVICE */ +#define OUTPUT_DEVICE_SPEAKER 1 +#define OUTPUT_DEVICE_HEADPHONE 2 +#define OUTPUT_DEVICE_BOTH 3 +#define OUTPUT_DEVICE_AUTO 4 + +/* Volume Levels values */ +#define DEFAULT_VOLMIN 0x00 +#define DEFAULT_VOLMAX 0xFF +#define DEFAULT_VOLSTEP 0x04 + +#define AUDIO_PAUSE 0 +#define AUDIO_RESUME 1 + +/* Codec POWER DOWN modes */ +#define CODEC_PDWN_HW 1 +#define CODEC_PDWN_SW 2 + +/* MUTE commands */ +#define AUDIO_MUTE_ON 1 +#define AUDIO_MUTE_OFF 0 + +#define VOLUME_CONVERT(x) ((Volume > 100)? 100:((uint8_t)((Volume * 255) / 100))) +#define DMA_MAX(x) (((x) <= DMA_MAX_SZE)? (x):DMA_MAX_SZE) + + +/* Generic functions */ +uint32_t EVAL_AUDIO_Init (uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq); +uint32_t EVAL_AUDIO_DeInit (void); +uint32_t EVAL_AUDIO_Play (uint16_t* pBuffer, uint32_t Size); +uint32_t EVAL_AUDIO_PauseResume (uint32_t Cmd, uint32_t Addr, uint32_t Size); +uint32_t EVAL_AUDIO_Stop (uint32_t CodecPowerDown_Mode); +uint32_t EVAL_AUDIO_VolumeCtl (uint8_t Volume); +uint32_t EVAL_AUDIO_Mute (uint32_t Command); + +/* Audio Codec functions */ + +/* High Layer codec functions */ +uint32_t Codec_Init (uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq); +uint32_t Codec_DeInit (void); +uint32_t Codec_Play (void); +uint32_t Codec_PauseResume (uint32_t Cmd); +uint32_t Codec_Stop (uint32_t Cmd); +uint32_t Codec_VolumeCtrl (uint8_t Volume); +uint32_t Codec_Mute (uint32_t Cmd); +uint32_t Codec_SwitchOutput (uint8_t Output); + +/* MAL (Media Access Layer) functions */ +void Audio_MAL_Init (void); +void Audio_MAL_DeInit (void); +void Audio_MAL_Play (uint32_t Addr, uint32_t Size); +void Audio_MAL_PauseResume (uint32_t Cmd, uint32_t Addr, uint32_t Size); +void Audio_MAL_Stop (void); + +/* User Callbacks: user has to implement these functions in his code if they are needed. */ + +/* This function is called when the requested data has been completely transferred. + In Normal mode (when the define AUDIO_MAL_MODE_NORMAL is enabled) this function + is called at the end of the whole audio file. + In circular mode (when the define AUDIO_MAL_MODE_CIRCULAR is enabled) this + function is called at the end of the current buffer transmission. */ +void EVAL_AUDIO_TransferComplete_CallBack(uint32_t pBuffer, uint32_t Size); + +/* This function is called when half of the requested buffer has been transferred + This callback is useful in Circular mode only (when AUDIO_MAL_MODE_CIRCULAR + define is enabled)*/ +void EVAL_AUDIO_HalfTransfer_CallBack(uint32_t pBuffer, uint32_t Size); + +/* This function is called when an Interrupt due to transfer error on or peripheral + error occurs. */ +void EVAL_AUDIO_Error_CallBack(void* pData); + +/* Codec_TIMEOUT_UserCallback() function is called whenever a timeout condition + occurs during communication (waiting on an event that doesn't occur, bus + errors, busy devices ...) on the Codec control interface (I2C). + You can use the default timeout callback implementation by uncommenting the + define USE_DEFAULT_TIMEOUT_CALLBACK in audio_codec.h file. + Typically the user implementation of this callback should reset I2C peripheral + and re-initialize communication or in worst case reset all the application. */ +uint32_t Codec_TIMEOUT_UserCallback(void); + +#endif /* __GD32VF103_USB_AUDIOCODEC_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/gd32vf103_it.h new file mode 100644 index 0000000..cc50acf --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/gd32vf103_it.h @@ -0,0 +1,54 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "usbd_core.h" + +/* function declarations */ +/* this function handles USB wakeup interrupt handler */ +void USBFS_WKUP_IRQHandler(void); +/* this function handles USBFS IRQ Handler */ +void USBFS_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/gd32vf103_libopt.h new file mode 100644 index 0000000..60680cf --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/usb_conf.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/usb_conf.h new file mode 100644 index 0000000..b7e6ac6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/usb_conf.h @@ -0,0 +1,121 @@ +/*! + \file usb_ch9_std.h + \brief USBFS driver basic configuration + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_CONF_H +#define __USB_CONF_H + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" + +#include + +#ifdef USE_USB_FS + #define USB_FS_CORE +#endif + +#ifdef USE_USB_HS + #define USB_HS_CORE +#endif + +#ifdef USB_FS_CORE + #define RX_FIFO_FS_SIZE 128 + #define TX0_FIFO_FS_SIZE 64 + #define TX1_FIFO_FS_SIZE 128 + #define TX2_FIFO_FS_SIZE 0 + #define TX3_FIFO_FS_SIZE 0 +#endif /* USB_FS_CORE */ + +#ifdef USB_HS_CORE + #define RX_FIFO_HS_SIZE 512 + #define TX0_FIFO_HS_SIZE 128 + #define TX1_FIFO_HS_SIZE 372 + #define TX2_FIFO_HS_SIZE 0 + #define TX3_FIFO_HS_SIZE 0 + #define TX4_FIFO_HS_SIZE 0 + #define TX5_FIFO_HS_SIZE 0 + + #ifdef USE_ULPI_PHY + #define USB_OTG_ULPI_PHY_ENABLED + #endif + + #ifdef USE_EMBEDDED_PHY + #define USB_OTG_EMBEDDED_PHY_ENABLED + #endif + + #define USB_OTG_HS_INTERNAL_DMA_ENABLED + #define USB_OTG_HS_DEDICATED_EP1_ENABLED +#endif /* USB_HS_CORE */ + +#define USB_SOF_OUTPUT 1 +#define USB_LOW_POWER 1 + +//#define VBUS_SENSING_ENABLED + +//#define USE_HOST_MODE +#define USE_DEVICE_MODE +//#define USE_OTG_MODE + +#ifndef USB_FS_CORE + #ifndef USB_HS_CORE + #error "USB_HS_CORE or USB_FS_CORE should be defined" + #endif +#endif + +#ifndef USE_DEVICE_MODE + #ifndef USE_HOST_MODE + #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" + #endif +#endif + +#ifndef USE_USB_HS + #ifndef USE_USB_FS + #error "USE_USB_HS or USE_USB_FS should be defined" + #endif +#endif + +/****************** C Compilers dependant keywords ****************************/ +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined (__GNUC__) /* GNU Compiler */ + #define __ALIGN_END __attribute__ ((aligned(4))) + #define __ALIGN_BEGIN + #endif /* __GNUC__ */ +#else + #define __ALIGN_BEGIN + #define __ALIGN_END +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + + +#endif /* __USB_CONF_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/usbd_audio_out_if.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/usbd_audio_out_if.h new file mode 100644 index 0000000..8fd93b2 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/usbd_audio_out_if.h @@ -0,0 +1,93 @@ +/*! + \file usbd_audio_out_if.h + \brief header file for the usbd_audio_out_if.c file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __GD32VF103_USBD_AUDIO_OUT_IF_H +#define __GD32VF103_USBD_AUDIO_OUT_IF_H + +/* Includes ------------------------------------------------------------------*/ +#include "gd32vf103_audio_codec.h" +#include "audio_core.h" + +/** @addtogroup GD32VF103_Firmware + * @{ + */ + +/** @addtogroup USB_OTG_FS + * @{ + */ + +/** @addtogroup USB_OTG_FS_Device_Class_Library + * @{ + */ + +/** @defgroup USBD_AUDIO + * @{ + */ + +/** @defgroup USBD_AUDIO_Core_Exported_Defines + * @{ + */ + +/* Audio Commands enmueration */ +typedef enum +{ + AUDIO_CMD_PLAY = 1, + AUDIO_CMD_PAUSE, + AUDIO_CMD_STOP, +}AUDIO_CMD_TypeDef; + +/* Mute commands */ +#define AUDIO_MUTE 0x01 +#define AUDIO_UNMUTE 0x00 + +/* Functions return value */ +#define AUDIO_OK 0x00 +#define AUDIO_FAIL 0xFF + +/* Audio Machine States */ +#define AUDIO_STATE_INACTIVE 0x00 +#define AUDIO_STATE_ACTIVE 0x01 +#define AUDIO_STATE_PLAYING 0x02 +#define AUDIO_STATE_PAUSED 0x03 +#define AUDIO_STATE_STOPPED 0x04 +#define AUDIO_STATE_ERROR 0x05 + + +/** @defgroup USBD_AUDIO_CORE_Exported_Variables + * @{ + */ +extern AUDIO_FOPS_TypeDef AUDIO_OUT_fops; + +#endif /* __GD32VF103_USBD_AUDIO_OUT_IF_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/usbd_conf.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/usbd_conf.h new file mode 100644 index 0000000..f7ff9b9 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Include/usbd_conf.h @@ -0,0 +1,74 @@ +/*! + \file usbd_conf.h + \brief the header file of USBHS device-mode configuration + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_CONF_H +#define USBD_CONF_H + +#include "usb_conf.h" + +#define USBD_CFG_MAX_NUM 1 +#define USBD_ITF_MAX_NUM 1 +#define USB_STR_DESC_MAX_SIZE 64 + +/* USB feature -- Self Powered */ +//#define USBD_SELF_POWERED + +/* USB user string supported */ +/* #define USB_SUPPORT_USER_STRING_DESC */ + +//#define USBD_DYNAMIC_DESCRIPTOR_CHANGE_ENABLED + + #define USBD_AUDIO_FREQ 16000 /* Audio frequency in Hz for GD32VF103 devices family when 25MHz HSE value + is used. */ + +/* Maximum number of supported media (Flash) */ +#define MAX_USED_MEMORY_MEDIA 1 + +#define USB_STRING_COUNT 6 + +/* Audio endpoint define */ +#define AUDIO_TOTAL_IF_NUM 0x02 +#define AUDIO_OUT_EP EP1_OUT +#define AUDIO_IN_EP EP2_IN + +#define USB_SERIAL_STRING_SIZE 0x06 +#define DEVICE_ID (0x40022100) + +#define DEFAULT_VOLUME 65 /* Default volume in % (Mute=0%, Max = 100%) in Logarithmic values. + To get accurate volume variations, it is possible to use a logarithmic + coversion table to convert from percentage to logarithmic law. + In order to keep this example code simple, this conversion is not used.*/ + + +#endif /* USBD_CONF_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/app.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/app.c new file mode 100644 index 0000000..cb7fad5 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/app.c @@ -0,0 +1,82 @@ +/*! + \file app.c + \brief USB main routine for Audio device + + \version 2019-6-5, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "audio_core.h" +#include +#include +#include + +usb_core_driver USB_OTG_dev = +{ + .dev = { + .desc = { + .dev_desc = (uint8_t *)&device_descripter, + .config_desc = (uint8_t *)&configuration_descriptor, + .strings = usbd_strings, + } + } +}; + +/*! + \brief main routine will construct a USB keyboard + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + eclic_global_interrupt_enable(); + + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL2_PRIO2); + + /* configure USB clock */ + usb_rcu_config(); + + /* timer nvic initialization */ + usb_timer_init(); + + /* USB device stack configure */ + usbd_init (&USB_OTG_dev, USB_CORE_ENUM_FS, &usbd_audio_cb); + + /* USB interrupt configure */ + usb_intr_config(); + + /* check if USB device is enumerated successfully */ + while (USB_OTG_dev.dev.cur_status != USBD_CONFIGURED) { + } + + while (1) { + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/audio_core.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/audio_core.c new file mode 100644 index 0000000..7e41311 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/audio_core.c @@ -0,0 +1,621 @@ +/*! + \file audio_core.c + \brief USB audio device class core functions + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_audio_out_if.h" +#include "audio_core.h" + +#define USBD_VID 0x0483 +#define USBD_PID 0x5730 + +/* Main Buffer for Audio Data Out transfers and its relative pointers */ +uint8_t IsocOutBuff [TOTAL_OUT_BUF_SIZE * 2]; +uint8_t* IsocOutWrPtr = IsocOutBuff; +uint8_t* IsocOutRdPtr = IsocOutBuff; + +/* AUDIO Requests management functions */ +static void AUDIO_Req_GetCurrent (usb_dev *pudev, usb_req *req); +static void AUDIO_Req_SetCurrent (usb_dev *pudev, usb_req *req); +static uint8_t USBD_AUDIO_DataOut (usb_dev *pudev, uint8_t EpID); +static uint8_t USBD_AUDIO_EP0_RxReady (usb_dev *pudev); +static uint8_t USBD_AUDIO_SOF (usb_dev *pudev); +static void USBD_AUDIO_SetInterface(usb_dev *pudev, usb_req *req); +static void USBD_AUDIO_GetInterface(usb_dev *pudev, usb_req *req); + +/* Main Buffer for Audio Control Rrequests transfers and its relative variables */ +uint8_t AudioCtl[64]; +uint8_t AudioCtlCmd = 0; +uint8_t AudioCtlUnit = 0; +uint32_t AudioCtlLen = 0; + +static uint32_t PlayFlag = 0; + +static __IO uint32_t USBD_AUDIO_AltSet = 0; + +/* note:it should use the c99 standard when compiling the below codes */ +/* USB standard device descriptor */ +const usb_desc_dev device_descripter = +{ + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, + .bcdUSB = 0x0200, + .bDeviceClass = 0x00, + .bDeviceSubClass = 0x00, + .bDeviceProtocol = 0x00, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM +}; + +/* USB device configuration descriptor */ +const usb_descriptor_configuration_set_struct configuration_descriptor = +{ + .Config = + { + .header = + { + .bLength = USB_CFG_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = USB_SPEAKER_CONFIG_DESC_SIZE, + .bNumInterfaces = 0x02, + .bConfigurationValue = 0x01, + .iConfiguration = 0x00, + .bmAttributes = 0xC0, + .bMaxPower = 0x32 + }, + + .Speaker_Std_Interface = + { + .header = + { + .bLength = USB_ITF_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x00, + .bInterfaceClass = 0x01, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x00, + .iInterface = 0x00 + }, + + .Speaker_AC_Interface = + { + .header = + { + .bLength = sizeof(usb_descriptor_AC_interface_struct), + .bDescriptorType = 0x24 + }, + .bDescriptorSubtype = 0x01, + .bcdADC = 0x0100, + .wTotalLength = 0x0027, + .bInCollection = 0x01, + .baInterfaceNr = 0x01 + }, + + .Speaker_IN_Terminal = + { + .header = + { + .bLength = sizeof(usb_descriptor_input_terminal_struct), + .bDescriptorType = 0x24 + }, + .bDescriptorSubtype = 0x02, + .bTerminalID = 0x01, + .wTerminalType = 0x0101, + .bAssocTerminal = 0x00, + .bNrChannels = 0x01, + .wChannelConfig = 0x0000, + .iChannelNames = 0x00, + .iTerminal = 0x00 + }, + + .Speaker_Feature_Unit = + { + .header = + { + .bLength = sizeof(usb_descriptor_mono_feature_unit_struct), + .bDescriptorType = 0x24 + }, + .bDescriptorSubtype = AUDIO_CONTROL_FEATURE_UNIT, + .bUnitID = AUDIO_OUT_STREAMING_CTRL, + .bSourceID = 0x01, + .bControlSize = 0x01, + .bmaControls0 = AUDIO_CONTROL_MUTE, + .bmaControls1 = 0x00, + .iFeature = 0x00 + }, + + .Speaker_OUT_Terminal = + { + .header = + { + .bLength = sizeof(usb_descriptor_output_terminal_struct), + .bDescriptorType = AUDIO_INTERFACE_DESCRIPTOR_TYPE + }, + .bDescriptorSubtype = AUDIO_CONTROL_OUTPUT_TERMINAL, + .bTerminalID = 0x03, + .wTerminalType = 0x0301, + .bAssocTerminal = 0x00, + .bSourceID = 0x02, + .iTerminal = 0x00 + }, + + .Speaker_Std_AS_Interface_ZeroBand = + { + .header = + { + .bLength = USB_ITF_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x01, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x00, + .bInterfaceClass = USB_DEVICE_CLASS_AUDIO, + .bInterfaceSubClass = AUDIO_SUBCLASS_AUDIOSTREAMING, + .bInterfaceProtocol = AUDIO_PROTOCOL_UNDEFINED, + .iInterface = 0x00 + }, + + .Speaker_Std_AS_Interface_Opera = + { + .header = + { + .bLength = USB_ITF_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x01, + .bAlternateSetting = 0x01, + .bNumEndpoints = 0x01, + .bInterfaceClass = USB_DEVICE_CLASS_AUDIO, + .bInterfaceSubClass = AUDIO_SUBCLASS_AUDIOSTREAMING, + .bInterfaceProtocol = AUDIO_PROTOCOL_UNDEFINED, + .iInterface = 0x00 + }, + + .Speaker_AS_Interface = + { + .header = + { + .bLength = sizeof(usb_descriptor_AS_interface_struct), + .bDescriptorType = AUDIO_INTERFACE_DESCRIPTOR_TYPE + }, + .bDescriptorSubtype = AUDIO_STREAMING_GENERAL, + .bTerminalLink = 0x01, + .bDelay = 0x01, + .wFormatTag = 0x0001, + }, + + .Speaker_Format_TypeI = + { + .header = + { + .bLength = sizeof(usb_descriptor_format_type_struct), + .bDescriptorType = AUDIO_INTERFACE_DESCRIPTOR_TYPE + }, + .bDescriptorSubtype = AUDIO_STREAMING_FORMAT_TYPE, + .bFormatType = AUDIO_FORMAT_TYPE_III, + .bNrChannels = 0x02, + .bSubFrameSize = 0x02, + .bBitResolution = 0x10, + .bSamFreqType = 0x01, + .bSamFreq[0]= (uint8_t)USBD_AUDIO_FREQ, + .bSamFreq[1]= USBD_AUDIO_FREQ >> 8, + .bSamFreq[2]= USBD_AUDIO_FREQ >> 16 + }, + + .Speaker_Std_Endpoint = + { + .header = + { + .bLength = sizeof(usb_descriptor_std_endpoint_struct), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = AUDIO_OUT_EP, + .bmAttributes = USB_ENDPOINT_TYPE_ISOCHRONOUS, + .wMaxPacketSize = PACKET_SIZE(USBD_AUDIO_FREQ), + .bInterval = 0x01, + .bRefresh = 0x00, + .bSynchAddress = 0x00 + }, + + .Speaker_AS_Endpoint = + { + .header = + { + .bLength = sizeof(usb_descriptor_AS_endpoint_struct), + .bDescriptorType = AUDIO_ENDPOINT_DESCRIPTOR_TYPE + }, + .bDescriptorSubtype = AUDIO_ENDPOINT_GENERAL, + .bmAttributes = 0x00, + .bLockDelayUnits = 0x00, + .wLockDelay = 0x0000, + } +}; + +/* USB language ID Descriptor */ +const usb_desc_LANGID usbd_language_id_desc = +{ + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + .wLANGID = ENG_LANGID +}; + +/* USB serial string */ +uint8_t usbd_serial_string[USB_SERIAL_STRING_SIZE] = +{ + USB_SERIAL_STRING_SIZE, + USB_DESCTYPE_STR, +}; + +__ALIGN_BEGIN void* const usbd_strings[] __ALIGN_END = +{ + [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, + [STR_IDX_MFC] = USBD_STRING_DESC("GD32_Microelectronics"), + [STR_IDX_PRODUCT] = USBD_STRING_DESC("GD32 Audio in FS Mode"), + [STR_IDX_SERIAL] = USBD_STRING_DESC("GD32VF103-1.0.0-6f7e8dma"), +}; + +/*! + \brief initialize the AUDIO device + \param[in] pudev: pointer to usb device instance + \param[in] config_index: configuration index + \param[out] none + \retval usb device operation status +*/ +uint8_t audio_init (usb_dev *pudev, uint8_t config_index) +{ + /* initialize Rx endpoint */ + usbd_ep_setup(pudev, (const usb_desc_ep *)&(configuration_descriptor.Speaker_Std_Endpoint)); + + /* Initialize the Audio output Hardware layer */ + if (AUDIO_OUT_fops.Init(USBD_AUDIO_FREQ, DEFAULT_VOLUME, 0) != USBD_OK) + { + return USBD_FAIL; + } + + /* Prepare Out endpoint to receive audio data */ + usbd_ep_recev (pudev, AUDIO_OUT_EP, (uint8_t*)IsocOutBuff, AUDIO_OUT_PACKET); + + return USBD_OK; +} + +/*! + \brief de-initialize the AUDIO device + \param[in] pudev: pointer to usb device instance + \param[in] config_index: configuration index + \param[out] none + \retval usb device operation status +*/ +uint8_t audio_deinit (usb_dev *pudev, uint8_t config_index) +{ + /* deinitialize AUDIO endpoints */ + usbd_ep_clear(pudev, AUDIO_OUT_EP); + + /* DeInitialize the Audio output Hardware layer */ + if (AUDIO_OUT_fops.DeInit(0) != USBD_OK) + { + return USBD_FAIL; + } + + return USBD_OK; +} + +/*! + \brief handle the AUDIO class-specific requests + \param[in] pudev: pointer to usb device instance + \param[in] req: device class-specific request + \param[out] none + \retval usb device operation status +*/ +uint8_t audio_req_handler (usb_dev *pudev, usb_req *req) +{ + switch (req->bmRequestType & USB_REQTYPE_MASK) { + case USB_REQTYPE_CLASS: + switch (req->bRequest) { + case AUDIO_REQ_GET_CUR: + AUDIO_Req_GetCurrent(pudev, req); + break; + + case AUDIO_REQ_SET_CUR: + AUDIO_Req_SetCurrent(pudev, req); + break; + + default: + usbd_enum_error (pudev, req); + return USBD_FAIL; + } + + case USB_REQTYPE_STRD: + /* standard device request */ + switch(req->bRequest) { + case USB_GET_INTERFACE: + USBD_AUDIO_GetInterface(pudev, req); + break; + + case USB_SET_INTERFACE: + USBD_AUDIO_SetInterface(pudev, req); + break; + + default: + break; + } + break; + + default: + break; + } + + return USBD_OK; +} + +/*! + \brief handle data stage + \param[in] pudev: pointer to usb device instance + \param[in] rx_tx: the flag of Rx or Tx + \param[in] ep_id: the endpoint ID + \param[out] none + \retval usb device operation status +*/ +uint8_t audio_data_in_handler (usb_dev *pudev, uint8_t ep_id) +{ + if ((AUDIO_IN_EP & 0x7F) == ep_id) { + return USBD_OK; + } + return USBD_FAIL; +} + +uint8_t audio_data_out_handler (usb_dev *pudev, uint8_t ep_id) +{ + if ((EP0_OUT & 0x7F) == ep_id) { + + USBD_AUDIO_EP0_RxReady(pudev); + return USBD_OK; + } else if ((AUDIO_OUT_EP & 0x7F) == ep_id) { + + USBD_AUDIO_DataOut(pudev, ep_id); + return USBD_OK; + } + return USBD_FAIL; +} + +/** + * @brief Handles the Audio Out data stage. + * @param pudev: pointer to usb device instance + * @param EpID: endpoint identifer + * @retval usb device operation status + */ +static uint8_t USBD_AUDIO_DataOut (usb_dev *pudev, uint8_t EpID) +{ + if (EpID == AUDIO_OUT_EP) + { + /* Increment the Buffer pointer or roll it back when all buffers are full */ + if (IsocOutWrPtr >= (IsocOutBuff + (AUDIO_OUT_PACKET * OUT_PACKET_NUM))) + { + /* All buffers are full: roll back */ + IsocOutWrPtr = IsocOutBuff; + } + else + { + /* Increment the buffer pointer */ + IsocOutWrPtr += AUDIO_OUT_PACKET; + } + + /* Toggle the frame index */ + pudev->dev.transc_out[EpID].frame_num = + (pudev->dev.transc_out[EpID].frame_num)? 0:1; + + /* Prepare Out endpoint to receive next audio packet */ + usbd_ep_recev (pudev, AUDIO_OUT_EP, (uint8_t*)(IsocOutWrPtr), AUDIO_OUT_PACKET); + + /* Trigger the start of streaming only when half buffer is full */ + if ((PlayFlag == 0) && (IsocOutWrPtr >= (IsocOutBuff + ((AUDIO_OUT_PACKET * OUT_PACKET_NUM) / 2)))) + { + /* Enable start of Streaming */ + PlayFlag = 1; + } + } + + return USBD_OK; +} + +/** + * @brief Handles audio control requests data. + * @param pudev: pointer to usb device instance + * @retval usb device operation status + */ +static uint8_t USBD_AUDIO_EP0_RxReady (usb_dev *pudev) +{ + /* Check if an AudioControl request has been issued */ + if (AudioCtlCmd == AUDIO_REQ_SET_CUR) + {/* In this driver, to simplify code, only SET_CUR request is managed */ + + /* Check for which addressed unit the AudioControl request has been issued */ + if (AudioCtlUnit == AUDIO_OUT_STREAMING_CTRL) + {/* In this driver, to simplify code, only one unit is manage */ + + /* Call the audio interface mute function */ + AUDIO_OUT_fops.MuteCtl(AudioCtl[0]); + + /* Reset the AudioCtlCmd variable to prevent re-entering this function */ + AudioCtlCmd = 0; + AudioCtlLen = 0; + } + } + + return USBD_OK; +} + +/** + * @brief Handles the SOF event (data buffer update and synchronization). + * @param pudev: pointer to usb device instance + * @retval usb device operation status + */ +static uint8_t USBD_AUDIO_SOF (usb_dev *pudev) +{ + /* Check if there are available data in stream buffer. + In this function, a single variable (PlayFlag) is used to avoid software delays. + The play operation must be executed as soon as possible after the SOF detection. */ + if (PlayFlag) + { + /* Start playing received packet */ + AUDIO_OUT_fops.AudioCmd((uint8_t*)(IsocOutRdPtr), /* Samples buffer pointer */ + AUDIO_OUT_PACKET, /* Number of samples in Bytes */ + AUDIO_CMD_PLAY); /* Command to be processed */ + + /* Increment the Buffer pointer or roll it back when all buffers all full */ + if (IsocOutRdPtr >= (IsocOutBuff + (AUDIO_OUT_PACKET * OUT_PACKET_NUM))) + { + /* Roll back to the start of buffer */ + IsocOutRdPtr = IsocOutBuff; + } + else + { + /* Increment to the next sub-buffer */ + IsocOutRdPtr += AUDIO_OUT_PACKET; + } + + /* If all available buffers have been consumed, stop playing */ + if (IsocOutRdPtr == IsocOutWrPtr) + { + /* Pause the audio stream */ + AUDIO_OUT_fops.AudioCmd((uint8_t*)(IsocOutBuff), /* Samples buffer pointer */ + AUDIO_OUT_PACKET, /* Number of samples in Bytes */ + AUDIO_CMD_PAUSE); /* Command to be processed */ + + /* Stop entering play loop */ + PlayFlag = 0; + + /* Reset buffer pointers */ + IsocOutRdPtr = IsocOutBuff; + IsocOutWrPtr = IsocOutBuff; + } + } + + return USBD_OK; +} + +/** + * @brief Handle standard device request--Get Interface + * @param pudev: pointer to usb device instance + * @param req: standard device request + * @retval usb device operation status + */ +static void USBD_AUDIO_GetInterface (usb_dev *pudev, usb_req *req) +{ + pudev->dev.transc_in[0].xfer_buf = (uint8_t *)&USBD_AUDIO_AltSet; + pudev->dev.transc_in[0].remain_len = 1; + usbd_ctl_send(pudev); +} + +/** + * @brief Handle standard device request--Set Interface + * @param pudev: pointer to usb device instance + * @param req: standard device request + * @retval usb device operation status + */ +static void USBD_AUDIO_SetInterface (usb_dev *pudev, usb_req *req) +{ + if ((uint8_t)(req->wValue) < AUDIO_TOTAL_IF_NUM) + { + USBD_AUDIO_AltSet = (uint8_t)(req->wValue); + } + else + { + usbd_ep_stall(pudev,0x80); + usbd_ep_stall(pudev,0x00); + usb_ctlep_startout(pudev); + } +} + +/** + * @brief Handles the GET_CUR Audio control request. + * @param pudev: pointer to usb device instance + * @param req: setup class request + * @retval usb device operation status + */ +static void AUDIO_Req_GetCurrent(usb_dev *pudev, usb_req *req) +{ + /* Send the current mute state */ + pudev->dev.transc_in[0].xfer_buf = AudioCtl; + pudev->dev.transc_in[0].remain_len = req->wLength; + usbd_ctl_send(pudev); +} + +/** + * @brief Handles the SET_CUR Audio control request. + * @param pudev: pointer to usb device instance + * @param req: setup class request + * @retval usb device operation status + */ +static void AUDIO_Req_SetCurrent(usb_dev *pudev, usb_req *req) +{ + if (req->wLength) + { + /* Prepare the reception of the buffer over EP0 */ + pudev->dev.transc_out[0].xfer_buf = AudioCtl; + pudev->dev.transc_out[0].remain_len = req->wLength; + usbd_ctl_recev(pudev); + + /* Set the global variables indicating current request and its length + to the function usbd_audio_EP0_RxReady() which will process the request */ + AudioCtlCmd = AUDIO_REQ_SET_CUR; /* Set the request value */ + AudioCtlLen = req->wLength; /* Set the request data length */ + AudioCtlUnit = BYTE_HIGH(req->wIndex); /* Set the request target unit */ + } +} + +usb_class_core usbd_audio_cb = { + .command = NO_CMD, + .alter_set = 0, + + .init = audio_init, + .deinit = audio_deinit, + .req_proc = audio_req_handler, + .data_in = audio_data_in_handler, + .data_out = audio_data_out_handler, + .SOF = USBD_AUDIO_SOF +}; diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/gd32vf103_audio_codec.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/gd32vf103_audio_codec.c new file mode 100644 index 0000000..f1ef163 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/gd32vf103_audio_codec.c @@ -0,0 +1,935 @@ +/*! + \file gd3210c_audio_codec.c + \brief This file includes the low layer driver for CS43L22 Audio Codec + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "gd32vf103_audio_codec.h" +/* Private define ------------------------------------------------------------*/ + +/* Mask for the bit EN of the I2S CFGR register */ +#define I2S_ENABLE_MASK (0x0400) + +/* Delay for the Codec to be correctly reset */ +#define CODEC_RESET_DELAY (0x4FFF) + +/* Codec audio Standards */ +#ifdef I2S_STANDARD_PHILLIPS + #define CODEC_STANDARD 0x04 + #define I2S_STANDARD I2S_STD_PHILLIPS +#elif defined(I2S_STANDARD_MSB) + #define CODEC_STANDARD 0x00 + #define I2S_STANDARD I2S_STD_MSB +#elif defined(I2S_STANDARD_LSB) + #define CODEC_STANDARD 0x08 + #define I2S_STANDARD I2S_STD_LSB +#else + #error "Error: No audio communication standard selected !" +#endif /* I2S_STANDARD */ + +/* The 7 bits Codec adress (sent through I2C interface) */ +#define CODEC_ADDRESS 0x94 /* b00100111 */ + +/* Private variables ---------------------------------------------------------*/ +/* This structure is declared glabal because it is handled by two different functions */ +static dma_parameter_struct DMA_InitStructure; +static uint8_t OutputDev = 0; + +uint32_t AudioTotalSize = 0xFFFF; /* This variable holds the total size of the audio file */ +uint32_t AudioRemSize = 0xFFFF; /* This variable holds the remaining data in audio file */ +uint16_t *CurrentPos; /* This variable holds the current poisition of audio pointer */ +uint32_t I2S_AudioFreq = 0; + + +/* Private functions ---------------------------------------------------------*/ + +/* Audio Codec functions */ + +/* Low layer codec functions */ +static void Codec_CtrlInterface_Init (void); +static void Codec_CtrlInterface_DeInit (void); +static void Codec_AudioInterface_Init (uint32_t AudioFreq); +static void Codec_AudioInterface_DeInit (void); +static void Codec_Reset (void); +static uint32_t Codec_WriteRegister (uint32_t RegisterAddr, uint32_t RegisterValue); +static void Codec_GPIO_Init (void); +static void Codec_GPIO_DeInit (void); +static void Delay (__IO uint32_t nCount); + + +/** + * @brief Configure the audio peripherals. + * @param OutputDevice: + * This parameter can be any one of the following values: + * @arg OUTPUT_DEVICE_SPEAKER + * @arg OUTPUT_DEVICE_HEADPHONE + * @arg OUTPUT_DEVICE_BOTH + * @arg OUTPUT_DEVICE_AUTO + * @param Volume: Initial volume level (from 0 (Mute) to 100 (Max)) + * @param AudioFreq: Audio frequency used to paly the audio stream. + * @retval 0 if correct communication, else wrong communication + */ +uint32_t EVAL_AUDIO_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq) +{ + /* Perform low layer Codec initialization */ + if (Codec_Init(OutputDevice, VOLUME_CONVERT(Volume), AudioFreq) != 0) + { + return 1; + } + else + { + /* I2S data transfer preparation: + Prepare the Media to be used for the audio transfer from memory to I2S peripheral */ + Audio_MAL_Init(); + + /* Return 0 when all operations are OK */ + return 0; + } +} + +/** + * @brief Dinitializes all the resources used by the codec (those initialized + * by EVAL_AUDIO_Init() function) EXCEPT the I2C resources since they are + * used by the IOExpander as well (and eventually other modules). + * @param None. + * @retval 0 if correct communication, else wrong communication + */ +uint32_t EVAL_AUDIO_DeInit(void) +{ + /* DeInitialize the Media layer */ + Audio_MAL_DeInit(); + + /* DeInitialize Codec */ + Codec_DeInit(); + + return 0; +} + +/** + * @brief Starts playing audio stream from a data buffer for a determined size. + * @param pBuffer: Pointer to the buffer + * @param Size: Number of audio data BYTES. + * @retval OK if correct communication, else wrong communication + */ +uint32_t EVAL_AUDIO_Play(uint16_t* pBuffer, uint32_t Size) +{ + /* Set the total number of data to be played (count in half-word) */ + AudioTotalSize = Size/2; + + /* Call the audio Codec Play function */ + Codec_Play(); + + /* Update the Media layer and enable it for play */ + Audio_MAL_Play((uint32_t)pBuffer, (uint32_t)(DMA_MAX(AudioTotalSize / 2))); + + /* Update the remaining number of data to be played */ + AudioRemSize = (Size/2) - DMA_MAX(AudioTotalSize); + + /* Update the current audio pointer position */ + CurrentPos = pBuffer + DMA_MAX(AudioTotalSize); + + return 0; +} + +/** + * @brief This function Pauses or Resumes the audio file stream. In case + * of using DMA, the DMA Pause feature is used. In all cases the I2S + * peripheral is disabled. + * @WARNING When calling EVAL_AUDIO_PauseResume() function for pause, only + * this function should be called for resume (use of EVAL_AUDIO_Play() + * function for resume could lead to unexpected behaviour). + * @param Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different + * from 0) to resume. + * @param Addr: Address from/at which the audio stream should resume/pause. + * @param Size: Number of data to be configured for next resume. + * @retval o if correct communication, else wrong communication + */ +uint32_t EVAL_AUDIO_PauseResume(uint32_t Cmd, uint32_t Addr, uint32_t Size) +{ + if (Cmd != AUDIO_PAUSE) + { + /* Call the Media layer pause/resume function */ + Audio_MAL_PauseResume(Cmd, Addr, Size); + + /* Call the Audio Codec Pause/Resume function */ + if (Codec_PauseResume(Cmd) != 0) + { + return 1; + } + else + { + return 0; + } + } + else + { + /* Call the Audio Codec Pause/Resume function */ + if (Codec_PauseResume(Cmd) != 0) + { + return 1; + } + else + { + /* Call the Media layer pause/resume function */ + Audio_MAL_PauseResume(Cmd, Addr, Size); + + /* Return 0 if all operations are OK */ + return 0; + } + } +} + +/** + * @brief Stops audio playing and Power down the Audio Codec. + * @param Option: + * This parameter can be any one of the following values: + * @arg CODEC_PDWN_SW for software power off (by writing registers) + Then no need to reconfigure the Codec after power on. + * @arg CODEC_PDWN_HW completely shut down the codec (physically). Then need + * to reconfigure the Codec after power on. + * @retval 0 if correct communication, else wrong communication + */ +uint32_t EVAL_AUDIO_Stop(uint32_t Option) +{ + /* Call Audio Codec Stop function */ + if (Codec_Stop(Option) != 0) + { + return 1; + } + else + { + /* Call Media layer Stop function */ + Audio_MAL_Stop(); + + /* Update the remaining data number */ + AudioRemSize = AudioTotalSize; + + /* Return 0 when all operations are correctly done */ + return 0; + } +} + +/** + * @brief Controls the current audio volume level. + * @param Volume: Volume level to be set in percentage from 0% to 100% (0 for + * Mute and 100 for Max volume level). + * @retval 0 if correct communication, else wrong communication + */ +uint32_t EVAL_AUDIO_VolumeCtl(uint8_t Volume) +{ + /* Call the codec volume control function with converted volume value */ + return (Codec_VolumeCtrl(VOLUME_CONVERT(Volume))); +} + +/** + * @brief Enable or disable the MUTE mode by software + * @param Cmd: could be AUDIO_MUTE_ON to mute sound or AUDIO_MUTE_OFF to + * unmute the codec and restore previous volume level. + * @retval o if correct communication, else wrong communication + */ +uint32_t EVAL_AUDIO_Mute(uint32_t Cmd) +{ + /* Call the Codec Mute function */ + return (Codec_Mute(Cmd)); +} + +/** + * @brief This function handles main Media layer interrupt. + * @param None. + * @retval 0 if correct communication, else wrong communication + */ +void Audio_MAL_IRQHandler(void) +{ +#ifndef AUDIO_MAL_MODE_NORMAL + uint16_t *pAddr = (uint16_t *)CurrentPos; + uint32_t Size = AudioRemSize; +#endif /* AUDIO_MAL_MODE_NORMAL */ +} + +/* CS43L22 Audio Codec Control Functions */ + +/** + * @brief Initializes the audio codec and all related interfaces (control + * interface: I2C and audio interface: I2S) + * @param OutputDevice: + * This parameter can be any one of the following values: + * @arg OUTPUT_DEVICE_SPEAKER + * @arg OUTPUT_DEVICE_HEADPHONE + * @arg OUTPUT_DEVICE_BOTH + * @arg OUTPUT_DEVICE_AUTO + * @param Volume: Initial volume level (from 0 (Mute) to 100 (Max)) + * @param AudioFreq: Audio frequency used to paly the audio stream. + * @retval 0 if correct communication, else wrong communication + */ +uint32_t Codec_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq) +{ + uint32_t counter = 0; + + /* Configure the Codec related IOs */ + Codec_GPIO_Init(); + + /* Reset the Codec Registers */ + Codec_Reset(); + + /* Initialize the Control interface of the Audio Codec */ + Codec_CtrlInterface_Init(); + + /* Keep Codec powered OFF */ + counter += Codec_WriteRegister(0x02, 0x01); + + switch (OutputDevice) + { + case OUTPUT_DEVICE_SPEAKER: + counter += Codec_WriteRegister(0x04, 0xFA); /* SPK always ON & HP always OFF */ + OutputDev = 0xFA; + break; + + case OUTPUT_DEVICE_HEADPHONE: + counter += Codec_WriteRegister(0x04, 0xAF); /* SPK always OFF & HP always ON */ + OutputDev = 0xAF; + break; + + case OUTPUT_DEVICE_BOTH: + counter += Codec_WriteRegister(0x04, 0xAA); /* SPK always ON & HP always ON */ + OutputDev = 0xAA; + break; + + case OUTPUT_DEVICE_AUTO: + counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */ + OutputDev = 0x05; + break; + + default: + counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */ + OutputDev = 0x05; + break; + } + + /* Clock configuration: Auto detection */ + counter += Codec_WriteRegister(0x05, 0x81); + + /* Set the Slave Mode and the audio Standard */ + counter += Codec_WriteRegister(0x06, CODEC_STANDARD); + + /* Set the Master volume */ + Codec_VolumeCtrl(Volume); + + /* If the Speaker is enabled, set the Mono mode and volume attenuation level */ + if (OutputDevice != OUTPUT_DEVICE_HEADPHONE) + { + /* Set the Speaker Mono mode */ + counter += Codec_WriteRegister(0x0F , 0x06); + + /* Set the Speaker attenuation level */ + counter += Codec_WriteRegister(0x24, 0x00); + counter += Codec_WriteRegister(0x25, 0x00); + } + + /* Power on the Codec */ + counter += Codec_WriteRegister(0x02, 0x9E); + + /* Additional configuration for the CODEC. These configurations are done to reduce + the time needed for the Codec to power off. If these configurations are removed, + then a long delay should be added between powering off the Codec and switching + off the I2S peripheral MCLK clock (which is the operating clock for Codec). + If this delay is not inserted, then the codec will not shut down propoerly and + it results in high noise after shut down. */ + + /* Disable the analog soft ramp */ + counter += Codec_WriteRegister(0x0A, 0x00); + + /* Disable the digital soft ramp */ + counter += Codec_WriteRegister(0x0E, 0x04); + + /* Disable the limiter attack level */ + counter += Codec_WriteRegister(0x27, 0x00); + + /* Adjust Bass and Treble levels */ + counter += Codec_WriteRegister(0x1F, 0x0F); + + /* Adjust PCM volume level */ + counter += Codec_WriteRegister(0x1A, 0x0A); + counter += Codec_WriteRegister(0x1B, 0x0A); + + /* Configure the I2S peripheral */ + Codec_AudioInterface_Init(AudioFreq); + + /* Return communication control value */ + return counter; +} + +/** + * @brief Restore the audio codec state to default state and free all used + * resources. + * @param None. + * @retval 0 if correct communication, else wrong communication + */ +uint32_t Codec_DeInit(void) +{ + uint32_t counter = 0; + + /* Reset the Codec Registers */ + Codec_Reset(); + + /* Keep Codec powered OFF */ + counter += Codec_WriteRegister(0x02, 0x01); + + /* Deinitialize all use GPIOs */ + Codec_GPIO_DeInit(); + + /* Disable the Codec control interface */ + Codec_CtrlInterface_DeInit(); + + /* Deinitialize the Codec audio interface (I2S) */ + Codec_AudioInterface_DeInit(); + + /* Return communication control value */ + return counter; +} + +/** + * @brief Start the audio Codec play feature. + * For this codec no Play options are required. + * @param None. + * @retval 0 if correct communication, else wrong communication + */ +uint32_t Codec_Play(void) +{ + /* No actions required on Codec level for play command */ + + /* Return communication control value */ + return 0; +} + +/** + * @brief Pauses and resumes playing on the audio codec. + * @param Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different + * from 0) to resume. + * @retval 0 if correct communication, else wrong communication + */ +uint32_t Codec_PauseResume(uint32_t Cmd) +{ + uint32_t counter = 0; + + /* Pause the audio file playing */ + if (Cmd == AUDIO_PAUSE) + { + /* Mute the output first */ + counter += Codec_Mute(AUDIO_MUTE_ON); + + /* Put the Codec in Power save mode */ + counter += Codec_WriteRegister(0x02, 0x01); + } + else /* AUDIO_RESUME */ + { + /* Unmute the output first */ + counter += Codec_Mute(AUDIO_MUTE_OFF); + + counter += Codec_WriteRegister(0x04, OutputDev); + + /* Exit the Power save mode */ + counter += Codec_WriteRegister(0x02, 0x9E); + } + + return counter; +} + +/** + * @brief Stops audio Codec playing. It powers down the codec. + * @param CodecPdwnMode: + * This parameter can be any one of the following values: + * @arg CODEC_PDWN_SW: only mutes the audio codec. When resuming from this + * mode the codec keeps the prvious initialization (no need to re-Initialize + * the codec registers) + * @arg CODEC_PDWN_HW: Physically power down the codec. When resuming from this + * mode, the codec is set to default configuration (user should re-Initialize + * the codec in order to play again the audio stream). + * @retval 0 if correct communication, else wrong communication + */ +uint32_t Codec_Stop(uint32_t CodecPdwnMode) +{ + uint32_t counter = 0; + + /* Mute the output first */ + Codec_Mute(AUDIO_MUTE_ON); + + if (CodecPdwnMode == CODEC_PDWN_SW) + { + /* Power down the DAC and the speaker (PMDAC and PMSPK bits)*/ + counter += Codec_WriteRegister(0x02, 0x9F); + } + else /* CODEC_PDWN_HW */ + { + /* Power down the DAC components */ + counter += Codec_WriteRegister(0x02, 0x9F); + + /* Wait at least 100ms */ + Delay(0xFFF); + + /* Reset The pin */ + //IOE_WriteIOPin(AUDIO_RESET_PIN, BitReset); + } + + return counter; +} + +/** + * @brief Highers or Lowers the codec volume level. + * @param Volume: a byte value from 0 to 255 (refer to codec registers + * description for more details). + * @retval 0 if correct communication, else wrong communication + */ +uint32_t Codec_VolumeCtrl(uint8_t Volume) +{ + uint32_t counter = 0; + + if (Volume > 0xE6) + { + /* Set the Master volume */ + counter += Codec_WriteRegister(0x20, Volume - 0xE7); + counter += Codec_WriteRegister(0x21, Volume - 0xE7); + } + else + { + /* Set the Master volume */ + counter += Codec_WriteRegister(0x20, Volume + 0x19); + counter += Codec_WriteRegister(0x21, Volume + 0x19); + } + + return counter; +} + +/** + * @brief Enables or disables the mute feature on the audio codec. + * @param Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the + * mute mode. + * @retval 0 if correct communication, else wrong communication + */ +uint32_t Codec_Mute(uint32_t Cmd) +{ + uint32_t counter = 0; + + /* Set the Mute mode */ + if (Cmd == AUDIO_MUTE_ON) + { + counter += Codec_WriteRegister(0x04, 0xFF); + + //counter += Codec_WriteRegister(0x0D, 0x63); + //counter += Codec_WriteRegister(0x0F, 0xF6); + } + else /* AUDIO_MUTE_OFF Disable the Mute */ + { + counter += Codec_WriteRegister(0x04, OutputDev); + + //counter += Codec_WriteRegister(0x0D, 0x60); + //counter += Codec_WriteRegister(0x0F, 0x06); + } + + return counter; +} + +/** + * @brief Resets the audio codec. It restores the default configuration of the + * codec (this function shall be called before initializing the codec). + * @note This function calls an external driver function: The IO Expander driver. + * @param None. + * @retval 0 if correct communication, else wrong communication + */ +static void Codec_Reset(void) +{ + /* Configure the IO Expander (to use the Codec Reset pin mapped on the IOExpander) */ + //IOE_Config(); + + /* Power Down the codec */ + //IOE_WriteIOPin(AUDIO_RESET_PIN, BitReset); + + /* wait for a delay to insure registers erasing */ + //Delay(CODEC_RESET_DELAY); + + /* Power on the codec */ + //IOE_WriteIOPin(AUDIO_RESET_PIN, BitSet); +} + +/** + * @brief Switch dynamically (while audio file is played) the output target (speaker or headphone). + * @note This function modifies a global variable of the audio codec driver: OutputDev. + * @param None. + * @retval 0 if correct communication, else wrong communication + */ +uint32_t Codec_SwitchOutput(uint8_t Output) +{ + uint8_t counter = 0; + + switch (Output) + { + case OUTPUT_DEVICE_SPEAKER: + counter += Codec_WriteRegister(0x04, 0xFA); /* SPK always ON & HP always OFF */ + OutputDev = 0xFA; + break; + + case OUTPUT_DEVICE_HEADPHONE: + counter += Codec_WriteRegister(0x04, 0xAF); /* SPK always OFF & HP always ON */ + OutputDev = 0xAF; + break; + + case OUTPUT_DEVICE_BOTH: + counter += Codec_WriteRegister(0x04, 0xAA); /* SPK always ON & HP always ON */ + OutputDev = 0xAA; + break; + + case OUTPUT_DEVICE_AUTO: + counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */ + OutputDev = 0x05; + break; + + default: + counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */ + OutputDev = 0x05; + break; + } + + return counter; +} + +/** + * @brief Writes a Byte to a given register into the audio codec through the + control interface (I2C) + * @param RegisterAddr: The address (location) of the register to be written. + * @param RegisterValue: the Byte value to be written into destination register. + * @retval 0 if correct communication, else wrong communication + */ +static uint32_t Codec_WriteRegister(uint32_t RegisterAddr, uint32_t RegisterValue) +{ + uint32_t result = 0; + + /* Return the verifying value: 0 (Passed) or 1 (Failed) */ + return result; +} + +/** + * @brief Initializes the Audio Codec control interface (I2C). + * @param None. + * @retval None. + */ +static void Codec_CtrlInterface_Init(void) +{ + +} + +/** + * @brief Restore the Audio Codec control interface to its default state. + * This function doesn't de-initialize the I2C because the I2C peripheral + * may be used by other modules. + * @param None. + * @retval None. + */ +static void Codec_CtrlInterface_DeInit(void) +{ + /* Disable the I2C peripheral */ + /* This step is not done here because the I2C interface can be used by other modules */ + /* I2C_DeInit(CODEC_I2C); */ +} + +/** + * @brief Initializes the Audio Codec audio interface (I2S) + * @note This function assumes that the I2S input clock (through PLL_R in + * Devices RevA/Z and through dedicated PLLI2S_R in Devices RevB/Y) + * is already configured and ready to be used. + * @param AudioFreq: Audio frequency to be configured for the I2S peripheral. + * @retval None. + */ +static void Codec_AudioInterface_Init(uint32_t AudioFreq) +{ + I2S_AudioFreq = AudioFreq; + + /* Enable the CODEC_I2S peripheral clock */ + rcu_periph_clock_enable(CODEC_I2S_CLK); + + /* CODEC_I2S peripheral configuration */ + spi_i2s_deinit(CODEC_I2S); + + /* CODEC_I2S peripheral configuration */ + i2s_psc_config(CODEC_I2S, AudioFreq, I2S_FRAMEFORMAT_DT16B_CH16B, +#ifdef CODEC_MCLK_ENABLED + I2S_MCKOUT_ENABLE +#elif defined(CODEC_MCLK_DISABLED) + I2S_MCKOUT_DISABLE +#endif + ); + + i2s_init(CODEC_I2S, I2S_MODE_MASTERTX, I2S_STD_LSB, I2S_CKPL_LOW); + + /* Enable the I2S DMA TX request */ + spi_dma_enable(CODEC_I2S, SPI_DMA_TRANSMIT); + /* The I2S peripheral will be enabled only in the EVAL_AUDIO_Play() function + or by user functions if DMA mode not enabled */ +} + +/** + * @brief Restores the Audio Codec audio interface to its default state. + * @param None. + * @retval None. + */ +static void Codec_AudioInterface_DeInit(void) +{ + /* Disable the CODEC_I2S peripheral (in case it hasn't already been disabled) */ + i2s_disable(CODEC_I2S); + + /* Deinitialize the CODEC_I2S peripheral */ + spi_i2s_deinit(CODEC_I2S); + + /* Disable the CODEC_I2S peripheral clock */ + rcu_periph_clock_disable(CODEC_I2S_CLK); +} + +/** + * @brief Initializes IOs used by the Audio Codec (on the control and audio + * interfaces). + * @param None. + * @retval None. + */ +static void Codec_GPIO_Init(void) +{ + /* enable the clock */ + rcu_periph_clock_enable(RCU_AF); + rcu_periph_clock_enable(CODEC_I2S_GPIO1_CLOCK); + rcu_periph_clock_enable(CODEC_I2S_GPIO2_CLOCK); + rcu_periph_clock_enable(CODEC_SPI_CLK); + + /* CODEC_I2C SCL and SDA pins configuration */ + gpio_init(CODEC_SPI_GPIO, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, CODEC_SPI_SCL_PIN | CODEC_SPI_SDA_PIN); + + /* CODEC_I2S pins configuraiton: WS, SCK and SD pins */ + gpio_init(CODEC_I2S_GPIO, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, CODEC_I2S_WS_PIN | CODEC_I2S_SCK_PIN | CODEC_I2S_SD_PIN); + +#ifdef CODEC_MCLK_ENABLED + /* CODEC_I2S pins configuraiton: MCK pin */ + gpio_init(CODEC_I2S_MCK_GPIO, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, CODEC_I2S_MCK_PIN); +#endif /* CODEC_MCLK_ENABLED */ +} + +/** + * @brief Restores the IOs used by the Audio Codec interface to their default + * state + * @param None. + * @retval None. + */ +static void Codec_GPIO_DeInit(void) +{ + /* Deinitialize all the GPIOs used by the driver (EXCEPT the I2C IOs since + they are used by the IOExpander as well) */ + gpio_init(CODEC_I2S_GPIO, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, CODEC_I2S_WS_PIN | CODEC_I2S_SCK_PIN | CODEC_I2S_SD_PIN); + +#ifdef CODEC_MCLK_ENABLED + /* CODEC_I2S pins deinitialization: MCK pin */ + gpio_init(CODEC_I2S_MCK_GPIO, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, CODEC_I2S_MCK_PIN); +#endif /* CODEC_MCLK_ENABLED */ +} + +/** + * @brief Inserts a delay time (not accurate timing). + * @param nCount: specifies the delay time length. + * @retval None. + */ +static void Delay( __IO uint32_t nCount) +{ + for (; nCount != 0; nCount--); +} + +#ifdef USE_DEFAULT_TIMEOUT_CALLBACK +/** + * @brief Basic management of the timeout situation. + * @param None. + * @retval None. + */ +uint32_t Codec_TIMEOUT_UserCallback(void) +{ + /* Block communication and all processes */ + while (1) + { + } +} +#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */ + +/* Audio MAL Interface Control Functions */ + +/** + * @brief Initializes and prepares the Media to perform audio data transfer + * from Media to the I2S peripheral. + * @param None. + * @retval None. + */ +void Audio_MAL_Init(void) +{ + /* Enable the DMA clock */ + rcu_periph_clock_enable(AUDIO_MAL_DMA_CLOCK); + + /* Configure the DMA Stream */ + dma_channel_enable(AUDIO_MAL_DMA, AUDIO_MAL_DMA_CHANNEL); + dma_deinit(AUDIO_MAL_DMA, AUDIO_MAL_DMA_CHANNEL); + + /* Set the parameters to be configured */ + DMA_InitStructure.periph_addr = CODEC_I2S_ADDRESS; + DMA_InitStructure.memory_addr = (uint32_t)0;/* This field will be configured in play function */ + DMA_InitStructure.direction = DMA_MEMORY_TO_PERIPHERAL; + DMA_InitStructure.number = (uint32_t)0xFFFE;/* This field will be configured in play function */ + DMA_InitStructure.periph_inc = DMA_PERIPH_INCREASE_DISABLE; + DMA_InitStructure.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + DMA_InitStructure.periph_width = DMA_PERIPHERAL_WIDTH_16BIT; + DMA_InitStructure.memory_width = DMA_MEMORY_WIDTH_16BIT; + +#ifdef AUDIO_MAL_MODE_NORMAL + dma_circulation_disable(AUDIO_MAL_DMA, AUDIO_MAL_DMA_CHANNEL); +#elif defined(AUDIO_MAL_MODE_CIRCULAR) + dma_circulation_enable(AUDIO_MAL_DMA, AUDIO_MAL_DMA_CHANNEL); +#else + #error "AUDIO_MAL_MODE_NORMAL or AUDIO_MAL_MODE_CIRCULAR should be selected !!" +#endif /* AUDIO_MAL_MODE_NORMAL */ + + DMA_InitStructure.priority = DMA_PRIORITY_HIGH; + dma_init(AUDIO_MAL_DMA, AUDIO_MAL_DMA_CHANNEL, &DMA_InitStructure); + + /* Enable the I2S DMA request */ + spi_dma_enable(CODEC_I2S, SPI_DMA_TRANSMIT); +} + +/** + * @brief Restore default state of the used Media. + * @param None. + * @retval None. + */ +void Audio_MAL_DeInit(void) +{ + /* Disable the DMA Channel before the deinit */ + dma_channel_disable(AUDIO_MAL_DMA, AUDIO_MAL_DMA_CHANNEL); + + /* Dinitialize the DMA Channel */ + dma_deinit(AUDIO_MAL_DMA, AUDIO_MAL_DMA_CHANNEL); + + /* The DMA clock is not disabled, since it can be used by other streams */ +} + +/** + * @brief Starts playing audio stream from the audio Media. + * @param Addr: Pointer to the audio stream buffer + * @param Size: Number of data in the audio stream buffer + * @retval None. + */ +void Audio_MAL_Play(uint32_t Addr, uint32_t Size) +{ + /* Enable the I2S DMA Stream*/ + dma_channel_disable(AUDIO_MAL_DMA, AUDIO_MAL_DMA_CHANNEL); + + /* Clear the Interrupt flag */ + dma_interrupt_flag_clear(AUDIO_MAL_DMA, AUDIO_MAL_DMA_CHANNEL, DMA_INT_FLAG_FTF); + + /* Configure the buffer address and size */ + DMA_InitStructure.memory_addr = (uint32_t)Addr; + DMA_InitStructure.number = (uint32_t)(Size*2); + + /* Configure the DMA Stream with the new parameters */ + dma_init(AUDIO_MAL_DMA, AUDIO_MAL_DMA_CHANNEL, &DMA_InitStructure); + + /* Enable the I2S DMA Stream*/ + dma_channel_enable(AUDIO_MAL_DMA, AUDIO_MAL_DMA_CHANNEL); + + /* If the I2S peripheral is still not enabled, enable it */ + if ((SPI_I2SCTL(CODEC_I2S) & I2S_ENABLE_MASK) == 0) + { + i2s_enable(CODEC_I2S); + } +} + +/** + * @brief Pauses or Resumes the audio stream playing from the Media. + * @param Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different + * from 0) to resume. + * @param Addr: Address from/at which the audio stream should resume/pause. + * @param Size: Number of data to be configured for next resume. + * @retval None. + */ +void Audio_MAL_PauseResume(uint32_t Cmd, uint32_t Addr, uint32_t Size) +{ + /* Pause the audio file playing */ + if (Cmd == AUDIO_PAUSE) + { + /* Stop the current DMA request by resetting the I2S cell */ + Codec_AudioInterface_DeInit(); + + /* Re-configure the I2S interface for the next resume operation */ + Codec_AudioInterface_Init(I2S_AudioFreq); + + /* Disable the DMA Stream */ + dma_channel_disable(AUDIO_MAL_DMA, AUDIO_MAL_DMA_CHANNEL); + + /* Clear the Interrupt flag */ + dma_flag_clear(AUDIO_MAL_DMA, AUDIO_MAL_DMA_CHANNEL, AUDIO_MAL_DMA_FLAG_ALL); + } + else /* AUDIO_RESUME */ + { + /* Configure the buffer address and size */ + DMA_InitStructure.memory_addr = (uint32_t)Addr; + DMA_InitStructure.number = (uint32_t)(Size*2); + + /* Configure the DMA Stream with the new parameters */ + dma_init(AUDIO_MAL_DMA, AUDIO_MAL_DMA_CHANNEL, &DMA_InitStructure); + + /* Enable the I2S DMA Stream*/ + dma_channel_enable(AUDIO_MAL_DMA, AUDIO_MAL_DMA_CHANNEL); + + /* If the I2S peripheral is still not enabled, enable it */ + if ((SPI_I2SCTL(CODEC_I2S) & I2S_ENABLE_MASK) == 0) + { + i2s_enable(CODEC_I2S); + } + } +} + +/** + * @brief Stops audio stream playing on the used Media. + * @param None. + * @retval None. + */ +void Audio_MAL_Stop(void) +{ + /* Stop the Transfer on the I2S side: Stop and disable the DMA stream */ + dma_channel_disable(AUDIO_MAL_DMA, AUDIO_MAL_DMA_CHANNEL); + + /* Clear all the DMA flags for the next transfer */ + dma_flag_clear(AUDIO_MAL_DMA, AUDIO_MAL_DMA_CHANNEL, AUDIO_MAL_DMA_FLAG_ALL); + + /* Stop the current DMA request by resetting the I2S cell */ + Codec_AudioInterface_DeInit(); + + /* Re-configure the I2S interface for the next paly operation */ + Codec_AudioInterface_Init(I2S_AudioFreq); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/gd32vf103_hw.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/gd32vf103_hw.c new file mode 100644 index 0000000..204c678 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/gd32vf103_hw.c @@ -0,0 +1,206 @@ +/*! + \file gd32vf103_hw.c + \brief USB hardware configuration for GD32VF103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include +#include +#include + + +#define TIM_MSEC_DELAY 0x01 +#define TIM_USEC_DELAY 0x02 + +__IO uint32_t delay_time = 0; +__IO uint32_t timer_prescaler; +__IO uint32_t usbfs_prescaler = 0; + +static void hw_time_set (uint8_t unit); +static void hw_delay (uint32_t ntime, uint8_t unit); + + +/*! + \brief configure USB clock + \param[in] none + \param[out] none + \retval none +*/ +void usb_rcu_config(void) +{ + uint32_t system_clock = rcu_clock_freq_get(CK_SYS); + + if (system_clock == 48000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1; + timer_prescaler = 3; + } else if (system_clock == 72000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1_5; + timer_prescaler = 5; + } else if (system_clock == 96000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV2; + timer_prescaler = 7; + } else { + /* reserved */ + } + + rcu_usb_clock_config(usbfs_prescaler); + rcu_periph_clock_enable(RCU_USBFS); +} + +/*! + \brief configure USB interrupt + \param[in] none + \param[out] none + \retval none +*/ +void usb_intr_config(void) +{ + eclic_irq_enable((uint8_t)USBFS_IRQn, 1, 0); + + /* enable the power module clock */ + rcu_periph_clock_enable(RCU_PMU); + + /* USB wakeup EXTI line configuration */ + exti_interrupt_flag_clear(EXTI_18); + exti_init(EXTI_18, EXTI_INTERRUPT, EXTI_TRIG_RISING); + exti_interrupt_enable(EXTI_18); + + eclic_irq_enable((uint8_t)USBFS_WKUP_IRQn, 3, 0); +} + +/*! + \brief initializes delay unit using Timer2 + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_init (void) +{ + rcu_periph_clock_enable(RCU_TIMER2); + + eclic_irq_enable(TIMER2_IRQn, 2, 0); +} + +/*! + \brief delay in micro seconds + \param[in] usec: value of delay required in micro seconds + \param[out] none + \retval none +*/ +void usb_udelay (const uint32_t usec) +{ + hw_delay(usec, TIM_USEC_DELAY); +} + +/*! + \brief delay in milli seconds + \param[in] msec: value of delay required in milli seconds + \param[out] none + \retval none +*/ +void usb_mdelay (const uint32_t msec) +{ + hw_delay(msec, TIM_MSEC_DELAY); +} + +/*! + \brief time base IRQ + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_irq (void) +{ + if (RESET != timer_flag_get(TIMER2, TIMER_FLAG_UP)){ + timer_flag_clear(TIMER2, TIMER_FLAG_UP); + + if (delay_time > 0x00U){ + delay_time--; + } else { + timer_disable(TIMER2); + } + } +} + +/*! + \brief delay routine based on TIM0 + \param[in] nTime: delay Time + \param[in] unit: delay Time unit = mili sec / micro sec + \param[out] none + \retval none +*/ +static void hw_delay(uint32_t ntime, uint8_t unit) +{ + delay_time = ntime; + + hw_time_set(unit); + + while (0U != delay_time) { + } + + timer_disable(TIMER2); +} + +/*! + \brief configures TIM0 for delay routine based on TIM0 + \param[in] unit: msec /usec + \param[out] none + \retval none +*/ +static void hw_time_set(uint8_t unit) +{ + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER2); + timer_deinit(TIMER2); + + if(TIM_USEC_DELAY == unit) { + timer_initpara.period = 11; + } else if(TIM_MSEC_DELAY == unit) { + timer_initpara.period = 11999; + } + + timer_initpara.prescaler = timer_prescaler; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER2, &timer_initpara); + + timer_update_event_enable(TIMER2); + timer_interrupt_enable(TIMER2,TIMER_INT_UP); + timer_flag_clear(TIMER2, TIMER_FLAG_UP); + timer_update_source_config(TIMER2, TIMER_UPDATE_SRC_GLOBAL); + + /* TIMER2 counter enable */ + timer_enable(TIMER2); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/gd32vf103_it.c new file mode 100644 index 0000000..f46e7c3 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/gd32vf103_it.c @@ -0,0 +1,96 @@ +/*! + \file gd32vf103_it.c + \brief main interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usbd_int.h" +#include "drv_usb_hw.h" +#include "gd32vf103_it.h" + +extern usb_core_driver USB_OTG_dev; +extern uint32_t usbfs_prescaler; + +extern void usb_timer_irq (void); + +/*! + \brief this function handles USBD interrupt + \param[in] none + \param[out] none + \retval none +*/ +void USBFS_IRQHandler (void) +{ + usbd_isr (&USB_OTG_dev); +} + +/*! + \brief this function handles EXTI0_IRQ Handler + \param[in] none + \param[out] none + \retval none +*/ +void EXTI0_IRQHandler(void) +{ + +} + +/*! + \brief this function handles USBD wakeup interrupt request. + \param[in] none + \param[out] none + \retval none +*/ +void USBFS_WKUP_IRQHandler(void) +{ + if (USB_OTG_dev.bp.low_power) { + SystemInit(); + + rcu_usb_clock_config(usbfs_prescaler); + + rcu_periph_clock_enable(RCU_USBFS); + + usb_clock_active(&USB_OTG_dev); + } + + exti_interrupt_flag_clear(EXTI_18); +} + +/*! + \brief this function handles Timer0 updata interrupt request. + \param[in] none + \param[out] none + \retval none +*/ +void TIMER2_IRQHandler(void) +{ + usb_timer_irq(); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/system_gd32vf103.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/system_gd32vf103.c new file mode 100644 index 0000000..05e5205 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/system_gd32vf103.c @@ -0,0 +1,998 @@ +/*! + \file system_gd32vf103.h + \brief RISC-V Device Peripheral Access Layer Source File for + GD32VF103 Device Series + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32vf103.h" + +/* system frequency define */ +#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ + +/* select a system clock by uncommenting the following line */ +/* use IRC8M */ +//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000) + +/********************************************************************/ +//#define __SYSTEM_CLOCK_HXTAL (HXTAL_VALUE) +//#define __SYSTEM_CLOCK_24M_PLL_HXTAL (uint32_t)(24000000) +/********************************************************************/ + +//#define __SYSTEM_CLOCK_36M_PLL_HXTAL (uint32_t)(36000000) +//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_56M_PLL_HXTAL (uint32_t)(56000000) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000) +//#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) + +#define SEL_IRC8M 0x00U +#define SEL_HXTAL 0x01U +#define SEL_PLL 0x02U + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_48M_PLL_IRC8M +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M; +static void system_clock_48m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M; +static void system_clock_72m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M; +static void system_clock_108m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; +static void system_clock_hxtal(void); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_24M_PLL_HXTAL; +static void system_clock_24m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_36M_PLL_HXTAL; +static void system_clock_36m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL; +static void system_clock_48m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_56M_PLL_HXTAL; +static void system_clock_56m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; +static void system_clock_72m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL; +static void system_clock_96m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; +static void system_clock_108m_hxtal(void); +#else +uint32_t SystemCoreClock = IRC8M_VALUE; +#endif /* __SYSTEM_CLOCK_48M_PLL_IRC8M */ + +/* configure the system clock */ +static void system_clock_config(void); + +/*! + \brief configure the system clock + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_config(void) +{ +#ifdef __SYSTEM_CLOCK_HXTAL + system_clock_hxtal(); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) + system_clock_24m_hxtal(); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) + system_clock_36m_hxtal(); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) + system_clock_48m_hxtal(); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) + system_clock_56m_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) + system_clock_72m_hxtal(); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) + system_clock_96m_hxtal(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) + system_clock_108m_hxtal(); + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) + system_clock_48m_irc8m(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) + system_clock_72m_irc8m(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) + system_clock_108m_irc8m(); +#endif /* __SYSTEM_CLOCK_HXTAL */ +} + +/*! + \brief setup the microcontroller system, initialize the system + \param[in] none + \param[out] none + \retval none +*/ +void SystemInit(void) +{ + /* reset the RCC clock configuration to the default reset state */ + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL); + + /* reset HXTALEN, CKMEN, PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); + + /* Reset HXTALBPS bit */ + RCU_CTL &= ~(RCU_CTL_HXTALBPS); + + /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */ + + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | + RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4); + RCU_CFG1 = 0x00000000U; + + /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + /* disable all interrupts */ + RCU_INT = 0x00FF0000U; + + /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ + system_clock_config(); +} + +/*! + \brief update the SystemCoreClock with current core clock retrieved from cpu registers + \param[in] none + \param[out] none + \retval none +*/ +void SystemCoreClockUpdate(void) +{ + uint32_t scss; + uint32_t pllsel, predv0sel, pllmf, ck_src; + uint32_t predv0, predv1, pll1mf; + + scss = GET_BITS(RCU_CFG0, 2, 3); + + switch (scss) + { + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + SystemCoreClock = IRC8M_VALUE; + break; + + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + SystemCoreClock = HXTAL_VALUE; + break; + + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + + + if(RCU_PLLSRC_IRC8M_DIV2 == pllsel){ + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE / 2U; + }else{ + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + + predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); + + /* source clock use PLL1 */ + if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ + predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; + pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; + if(17U == pll1mf){ + pll1mf = 20U; + } + ck_src = (ck_src / predv1) * pll1mf; + } + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; + ck_src /= predv0; + } + + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + + if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ + pllmf |= 0x10U; + } + + if(pllmf >= 15U){ + pllmf += 1U; + }else{ + pllmf += 2U; + } + + SystemCoreClock = ck_src * pllmf; + + if(15U == pllmf){ + /* PLL source clock multiply by 6.5 */ + SystemCoreClock = ck_src * 6U + ck_src / 2U; + } + + break; + + /* IRC8M is selected as CK_SYS */ + default: + SystemCoreClock = IRC8M_VALUE; + break; + } +} + +#ifdef __SYSTEM_CLOCK_HXTAL +/*! + \brief configure the system clock to HXTAL + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + + /* wait until HXTAL is selected as system clock */ + while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +/*! + \brief configure the system clock to 24M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_24m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 6 = 24 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +/*! + \brief configure the system clock to 36M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_36m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 9 = 36 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +/*! + \brief configure the system clock to 48M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12); + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +/*! + \brief configure the system clock to 56M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_56m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 14 = 56 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL14); + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +/*! + \brief configure the system clock to 72M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18); + + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +/*! + \brief configure the system clock to 96M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_96m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + if(HXTAL_VALUE==25000000){ + + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +/*! + \brief configure the system clock to 108M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ + +static void system_clock_108m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PREDV1_DIV5 | RCU_PLL1_MUL8 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL2EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){ + } + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 | RCU_PREDV1_DIV2 | RCU_PLL1_MUL20 | RCU_PLL2_MUL20); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } + + /* enable PLL2 */ + RCU_CTL |= RCU_CTL_PLL2EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){ + } + + } + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) +/*! + \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL12; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +/*! + \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL18; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +/*! + \brief configure the system clock to 108M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL27; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#endif diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/usbd_audio_out_if.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/usbd_audio_out_if.c new file mode 100644 index 0000000..8739f73 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/Source/usbd_audio_out_if.c @@ -0,0 +1,288 @@ +/*! + \file usbd_audio_out_if.c + \brief This file provides the Audio Out (palyback) interface API + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "audio_core.h" +#include "usbd_audio_out_if.h" + +/** @addtogroup GD32VF103_Firmware + * @{ + */ + +/** @addtogroup USB_OTG_FS + * @{ + */ + +/** @addtogroup USB_OTG_FS_Device_Class_Library + * @{ + */ + +/** @defgroup USBD_AUDIO + * @{ + */ +static uint8_t Init (uint32_t AudioFreq, uint32_t Volume, uint32_t Options); +static uint8_t DeInit (uint32_t Options); +static uint8_t AudioCmd (uint8_t* pbuf, uint32_t Size, uint8_t Cmd); +static uint8_t VolumeCtl (uint8_t Vol); +static uint8_t MuteCtl (uint8_t Cmd); +static uint8_t PeriodicTC (uint8_t Cmd); +static uint8_t GetState (void); + +/** @defgroup USBD_AUDIO_out_if_Private_Variables + * @{ + */ +AUDIO_FOPS_TypeDef AUDIO_OUT_fops = +{ + Init, + DeInit, + AudioCmd, + VolumeCtl, + MuteCtl, + PeriodicTC, + GetState +}; + +static uint8_t AudioState = AUDIO_STATE_INACTIVE; + +/** + * @} + */ + +/** @defgroup USBD_AUDIO_out_if_Private_Functions + * @{ + */ + +/** + * @brief Initialize and configures all required resources for audio play function. + * @param AudioFreq: Statrtup audio frequency. + * @param Volume: Startup volume to be set. + * @param options: specific options passed to low layer function. + * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. + */ +static uint8_t Init (uint32_t AudioFreq, uint32_t Volume, uint32_t options) +{ + static uint32_t Initialized = 0; + + /* Check if the low layer has already been initialized */ + if (Initialized == 0) + { + /* Call low layer function */ + if (EVAL_AUDIO_Init(OUTPUT_DEVICE_AUTO, Volume, AudioFreq) != 0) + { + AudioState = AUDIO_STATE_ERROR; + return AUDIO_FAIL; + } + + /* Set the Initialization flag to prevent reinitializing the interface again */ + Initialized = 1; + } + + /* Update the Audio state machine */ + AudioState = AUDIO_STATE_ACTIVE; + + return AUDIO_OK; +} + +/** + * @brief Free all resources used by low layer and stops audio-play function. + * @param Options: options passed to low layer function. + * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. + */ +static uint8_t DeInit (uint32_t Options) +{ + /* Update the Audio state machine */ + AudioState = AUDIO_STATE_INACTIVE; + + return AUDIO_OK; +} + +/** + * @brief Play, Stop, Pause or Resume current file. + * @param pbuf: address from which file shoud be played. + * @param Size: size of the current buffer/file. + * @param Cmd: command to be executed, can be: + AUDIO_CMD_PLAY + AUDIO_CMD_PAUSE + AUDIO_CMD_RESUME + AUDIO_CMD_STOP. + * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. + */ +static uint8_t AudioCmd (uint8_t* pbuf, uint32_t Size, uint8_t Cmd) +{ + /* Check the current state */ + if ((AudioState == AUDIO_STATE_INACTIVE) || (AudioState == AUDIO_STATE_ERROR)) + { + AudioState = AUDIO_STATE_ERROR; + + return AUDIO_FAIL; + } + + switch (Cmd) + { + /* Process the PLAY command ----------------------------*/ + case AUDIO_CMD_PLAY: + /* If current state is Active or Stopped */ + if ((AudioState == AUDIO_STATE_ACTIVE) || \ + (AudioState == AUDIO_STATE_STOPPED) || \ + (AudioState == AUDIO_STATE_PLAYING)) + { + Audio_MAL_Play((uint32_t)pbuf, (Size/2)); + AudioState = AUDIO_STATE_PLAYING; + + return AUDIO_OK; + } + /* If current state is Paused */ + else if (AudioState == AUDIO_STATE_PAUSED) + { + if (EVAL_AUDIO_PauseResume(AUDIO_RESUME, (uint32_t)pbuf, (Size/2)) != 0) + { + AudioState = AUDIO_STATE_ERROR; + + return AUDIO_FAIL; + } + else + { + AudioState = AUDIO_STATE_PLAYING; + + return AUDIO_OK; + } + } + else /* Not allowed command */ + { + return AUDIO_FAIL; + } + + /* Process the STOP command ----------------------------*/ + case AUDIO_CMD_STOP: + if (AudioState != AUDIO_STATE_PLAYING) + { + /* Unsupported command */ + + return AUDIO_FAIL; + } + else if (EVAL_AUDIO_Stop(CODEC_PDWN_SW) != 0) + { + AudioState = AUDIO_STATE_ERROR; + + return AUDIO_FAIL; + } + else + { + AudioState = AUDIO_STATE_STOPPED; + + return AUDIO_OK; + } + + /* Process the PAUSE command ---------------------------*/ + case AUDIO_CMD_PAUSE: + if (AudioState != AUDIO_STATE_PLAYING) + { + /* Unsupported command */ + return AUDIO_FAIL; + } + else if (EVAL_AUDIO_PauseResume(AUDIO_PAUSE, (uint32_t)pbuf, (Size/2)) != 0) + { + AudioState = AUDIO_STATE_ERROR; + + return AUDIO_FAIL; + } + else + { + AudioState = AUDIO_STATE_PAUSED; + + return AUDIO_OK; + } + + /* Unsupported command ---------------------------------*/ + default: + return AUDIO_FAIL; + } +} + +/** + * @brief Set the volume level in % + * @param Vol: volume level to be set in % (from 0% to 100%) + * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. + */ +static uint8_t VolumeCtl (uint8_t Vol) +{ + /* Call low layer volume setting function */ + if (EVAL_AUDIO_VolumeCtl(Vol) != 0) + { + AudioState = AUDIO_STATE_ERROR; + + return AUDIO_FAIL; + } + + return AUDIO_OK; +} + +/** + * @brief Mute or Unmute the audio current output + * @param Cmd: can be 0 to unmute, or 1 to mute. + * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. + */ +static uint8_t MuteCtl (uint8_t Cmd) +{ + /* Call low layer mute setting function */ + if (EVAL_AUDIO_Mute(Cmd) != 0) + { + AudioState = AUDIO_STATE_ERROR; + + return AUDIO_FAIL; + } + + return AUDIO_OK; +} + +/** + * @brief + * @param Cmd + * @param + * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. + */ +static uint8_t PeriodicTC (uint8_t Cmd) +{ + return AUDIO_OK; +} + +/** + * @brief Return the current state of the audio machine + * @param None + * @retval Current State. + */ +static uint8_t GetState (void) +{ + return AudioState; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/readme.txt new file mode 100644 index 0000000..c90a696 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/Audio/readme.txt @@ -0,0 +1,65 @@ +/*! + \file readme.txt + \brief This file provides the Audio Out (palyback) interface API + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + @brief + The Audio device example allows device to communicate with host (PC) as USB headphone + using isochronous pipe for audio data transfer along with some control commands (i.e. + Mute). + It follows the "Universal Serial Bus Device Class Definition for Audio Devices + Release 1.0 March 18, 1998" defined by the USB Implementers Forum for reprogramming + an application through USB-FS-Device. + Following this specification, it is possible to manage only Full Speed USB mode + (High Speed is not supported). + + This class is natively supported by most Operating Systems (no need for specific + driver setup). + + This example uses the I2S interface to stream audio data from USB Host to the audio + codec implemented on the evaluation board. Then audio stream is output to the Headphone. + + For the GD32VF103V-EVAL-V1.0 board, it possible to use one of the two quartz belwo: + - 14.7456MHz which provides best audio quality + - Standard 25MHz which provides lesser quality. + + The device supports one audio frequency (the host driver manages the sampling rate + conversion from original audio file sampling rate to the sampling rate supported + by the device). It is possible to configure this audio frequency by modifying the + usbd_conf.h file (define USBD_AUDIO_FREQ). It is advised to set high frequencies + to guarantee a high audio quality. + It is also possible to modify the default volume through define DEFAULT_VOLUME in file + usbd_conf.h. + +@note: The audio frequencies leading to non integer number of data (44.1KHz, 22.05KHz, + 11.025KHz...) will not allow an optimum audio quality since one data will be lost + every two/more frames. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Eclipse/cdc_acm/.cproject b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Eclipse/cdc_acm/.cproject new file mode 100644 index 0000000..15589a0 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Eclipse/cdc_acm/.cproject @@ -0,0 +1,202 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Eclipse/cdc_acm/.project b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Eclipse/cdc_acm/.project new file mode 100644 index 0000000..25a36f7 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Eclipse/cdc_acm/.project @@ -0,0 +1,618 @@ + + + cdc_acm + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Examples + 2 + virtual:/virtual + + + Firmware + 2 + virtual:/virtual + + + Utilities + 2 + virtual:/virtual + + + Examples/USBFS + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral + 2 + virtual:/virtual + + + Firmware/GD32VF103_usbfs_driver + 2 + virtual:/virtual + + + Firmware/RISCV + 2 + virtual:/virtual + + + Utilities/gd32vf103v_eval.c + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_eval.c + + + Utilities/gd32vf103v_eval.h + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_eval.h + + + Examples/USBFS/USB_Device + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Include + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Source + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/gd32vf103.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/gd32vf103.h + + + Firmware/GD32VF103_standard_peripheral/system_gd32vf103.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/system_gd32vf103.h + + + Firmware/GD32VF103_usbfs_driver/Include + 2 + virtual:/virtual + + + Firmware/GD32VF103_usbfs_driver/Source + 2 + virtual:/virtual + + + Firmware/RISCV/drivers + 2 + virtual:/virtual + + + Firmware/RISCV/env_Eclipse + 2 + virtual:/virtual + + + Firmware/RISCV/stubs + 2 + virtual:/virtual + + + Examples/USBFS/USB_Device/CDC_ACM + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_core.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_core.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_dev.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_dev.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_host.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_host.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_hw.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_hw.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_regs.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_regs.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usbd_int.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usbd_int.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usbh_int.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usbh_int.h + + + Firmware/GD32VF103_usbfs_driver/Include/usb_ch9_std.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usb_ch9_std.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbd_core.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbd_core.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbd_enum.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbd_enum.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbd_transc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbd_transc.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbh_core.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbh_core.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbh_enum.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbh_enum.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbh_pipe.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbh_pipe.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbh_transc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbh_transc.h + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usb_core.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_core.c + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usb_dev.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_dev.c + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usbd_int.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usbd_int.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbd_core.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbd_core.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbd_enum.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbd_enum.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbd_transc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbd_transc.c + + + Firmware/RISCV/drivers/n200_eclic.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_eclic.h + + + Firmware/RISCV/drivers/n200_func.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_func.c + + + Firmware/RISCV/drivers/n200_func.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_func.h + + + Firmware/RISCV/drivers/n200_timer.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_timer.h + + + Firmware/RISCV/drivers/riscv_bits.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_bits.h + + + Firmware/RISCV/drivers/riscv_const.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_const.h + + + Firmware/RISCV/drivers/riscv_encoding.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_encoding.h + + + Firmware/RISCV/env_Eclipse/GD32VF103xB.lds + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/GD32VF103xB.lds + + + Firmware/RISCV/env_Eclipse/entry.S + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/entry.S + + + Firmware/RISCV/env_Eclipse/handlers.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/handlers.c + + + Firmware/RISCV/env_Eclipse/init.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/init.c + + + Firmware/RISCV/env_Eclipse/start.S + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/start.S + + + Firmware/RISCV/env_Eclipse/your_printf.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/your_printf.c + + + Firmware/RISCV/stubs/_exit.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/_exit.c + + + Firmware/RISCV/stubs/close.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/close.c + + + Firmware/RISCV/stubs/fstat.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/fstat.c + + + Firmware/RISCV/stubs/isatty.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/isatty.c + + + Firmware/RISCV/stubs/lseek.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/lseek.c + + + Firmware/RISCV/stubs/read.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/read.c + + + Firmware/RISCV/stubs/sbrk.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/sbrk.c + + + Firmware/RISCV/stubs/stub.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/stub.h + + + Firmware/RISCV/stubs/write.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/write.c + + + Firmware/RISCV/stubs/write_hex.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/write_hex.c + + + Examples/USBFS/USB_Device/CDC_ACM/Include + 2 + virtual:/virtual + + + Examples/USBFS/USB_Device/CDC_ACM/Source + 2 + virtual:/virtual + + + Examples/USBFS/USB_Device/CDC_ACM/Include/cdc_acm_core.h + 1 + PARENT-2-PROJECT_LOC/Include/cdc_acm_core.h + + + Examples/USBFS/USB_Device/CDC_ACM/Include/gd32vf103_it.h + 1 + PARENT-2-PROJECT_LOC/Include/gd32vf103_it.h + + + Examples/USBFS/USB_Device/CDC_ACM/Include/gd32vf103_libopt.h + 1 + PARENT-2-PROJECT_LOC/Include/gd32vf103_libopt.h + + + Examples/USBFS/USB_Device/CDC_ACM/Include/usb_conf.h + 1 + PARENT-2-PROJECT_LOC/Include/usb_conf.h + + + Examples/USBFS/USB_Device/CDC_ACM/Include/usbd_conf.h + 1 + PARENT-2-PROJECT_LOC/Include/usbd_conf.h + + + Examples/USBFS/USB_Device/CDC_ACM/Source/app.c + 1 + PARENT-2-PROJECT_LOC/Source/app.c + + + Examples/USBFS/USB_Device/CDC_ACM/Source/cdc_acm_core.c + 1 + PARENT-2-PROJECT_LOC/Source/cdc_acm_core.c + + + Examples/USBFS/USB_Device/CDC_ACM/Source/gd32vf103_hw.c + 1 + PARENT-2-PROJECT_LOC/Source/gd32vf103_hw.c + + + Examples/USBFS/USB_Device/CDC_ACM/Source/gd32vf103_it.c + 1 + PARENT-2-PROJECT_LOC/Source/gd32vf103_it.c + + + Examples/USBFS/USB_Device/CDC_ACM/Source/system_gd32vf103.c + 1 + PARENT-2-PROJECT_LOC/Source/system_gd32vf103.c + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Eclipse/cdc_acm/.settings/language.settings.xml b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Eclipse/cdc_acm/.settings/language.settings.xml new file mode 100644 index 0000000..d2e02ec --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Eclipse/cdc_acm/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Include/cdc_acm_core.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Include/cdc_acm_core.h new file mode 100644 index 0000000..96c2111 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Include/cdc_acm_core.h @@ -0,0 +1,133 @@ +/*! + \file cdc_acm_core.h + \brief the header file of IAP driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef CDC_ACM_CORE_H +#define CDC_ACM_CORE_H + +#include "usbd_enum.h" +#include "usb_ch9_std.h" +#include "usbd_transc.h" + + +#define USB_DESCTYPE_CS_INTERFACE 0x24 +#define USB_CDC_ACM_CONFIG_DESC_SIZE 0x43 + +#define CDC_ACM_DESC_SIZE 0x3A + +#define CDC_ACM_DESC_TYPE 0x21 + +#define SEND_ENCAPSULATED_COMMAND 0x00 +#define GET_ENCAPSULATED_RESPONSE 0x01 +#define SET_COMM_FEATURE 0x02 +#define GET_COMM_FEATURE 0x03 +#define CLEAR_COMM_FEATURE 0x04 +#define SET_LINE_CODING 0x20 +#define GET_LINE_CODING 0x21 +#define SET_CONTROL_LINE_STATE 0x22 +#define SEND_BREAK 0x23 +#define NO_CMD 0xFF + +#pragma pack(1) + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: header function descriptor */ + uint16_t bcdCDC; /*!< bcdCDC: low byte of spec release number (CDC1.10) */ +} usb_descriptor_header_function_struct; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: call management function descriptor */ + uint8_t bmCapabilities; /*!< bmCapabilities: D0 is reset, D1 is ignored */ + uint8_t bDataInterface; /*!< bDataInterface: 1 interface used for call management */ +} usb_descriptor_call_managment_function_struct; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: abstract control management desc */ + uint8_t bmCapabilities; /*!< bmCapabilities: D1 */ +} usb_descriptor_acm_function_struct; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: union func desc */ + uint8_t bMasterInterface; /*!< bMasterInterface: communication class interface */ + uint8_t bSlaveInterface0; /*!< bSlaveInterface0: data class interface */ +} usb_descriptor_union_function_struct; + +#pragma pack() + +typedef struct +{ + usb_desc_config config; + usb_desc_itf cdc_loopback_interface; + usb_descriptor_header_function_struct cdc_loopback_header; + usb_descriptor_call_managment_function_struct cdc_loopback_call_managment; + usb_descriptor_acm_function_struct cdc_loopback_acm; + usb_descriptor_union_function_struct cdc_loopback_union; + usb_desc_ep cdc_loopback_cmd_endpoint; + usb_desc_itf cdc_loopback_data_interface; + usb_desc_ep cdc_loopback_out_endpoint; + usb_desc_ep cdc_loopback_in_endpoint; +} usb_descriptor_configuration_set_struct; + +extern void* const usbd_strings[USB_STRING_COUNT]; +extern const usb_desc_dev device_descriptor; +extern usb_descriptor_configuration_set_struct configuration_descriptor; + +extern usb_class_core usbd_cdc_cb; + +/* function declarations */ +/* initialize the CDC ACM device */ +uint8_t cdc_acm_init(usb_dev *pudev, uint8_t config_index); +/* de-initialize the CDC ACM device */ +uint8_t cdc_acm_deinit(usb_dev *pudev, uint8_t config_index); +/* handle the CDC ACM class-specific requests */ +uint8_t cdc_acm_req_handler(usb_dev *pudev, usb_req *req); +/* handle CDC ACM data */ +uint8_t cdc_acm_data_in_handler(usb_dev *pudev, uint8_t ep_id); +uint8_t cdc_acm_data_out_handler(usb_dev *pudev, uint8_t ep_id); + +/* receive CDC ACM data */ +void cdc_acm_data_receive(usb_dev *pudev); +/* send CDC ACM data */ +void cdc_acm_data_send(usb_dev *pudev, uint32_t data_len); +/* command data received on control endpoint */ +uint8_t cdc_acm_EP0_RxReady(usb_dev *pudev); + +#endif /* CDC_ACM_CORE_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Include/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Include/gd32vf103_it.h new file mode 100644 index 0000000..cc50acf --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Include/gd32vf103_it.h @@ -0,0 +1,54 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "usbd_core.h" + +/* function declarations */ +/* this function handles USB wakeup interrupt handler */ +void USBFS_WKUP_IRQHandler(void); +/* this function handles USBFS IRQ Handler */ +void USBFS_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Include/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Include/gd32vf103_libopt.h new file mode 100644 index 0000000..60680cf --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Include/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Include/usb_conf.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Include/usb_conf.h new file mode 100644 index 0000000..b36f0be --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Include/usb_conf.h @@ -0,0 +1,121 @@ +/*! + \file usb_conf.h + \brief USBFS driver basic configuration + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_CONF_H +#define __USB_CONF_H + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" + +#include + +#ifdef USE_USB_FS + #define USB_FS_CORE +#endif + +#ifdef USE_USB_HS + #define USB_HS_CORE +#endif + +#ifdef USB_FS_CORE + #define RX_FIFO_FS_SIZE 128 + #define TX0_FIFO_FS_SIZE 64 + #define TX1_FIFO_FS_SIZE 128 + #define TX2_FIFO_FS_SIZE 0 + #define TX3_FIFO_FS_SIZE 0 +#endif /* USB_FS_CORE */ + +#ifdef USB_HS_CORE + #define RX_FIFO_HS_SIZE 512 + #define TX0_FIFO_HS_SIZE 128 + #define TX1_FIFO_HS_SIZE 372 + #define TX2_FIFO_HS_SIZE 0 + #define TX3_FIFO_HS_SIZE 0 + #define TX4_FIFO_HS_SIZE 0 + #define TX5_FIFO_HS_SIZE 0 + + #ifdef USE_ULPI_PHY + #define USB_OTG_ULPI_PHY_ENABLED + #endif + + #ifdef USE_EMBEDDED_PHY + #define USB_OTG_EMBEDDED_PHY_ENABLED + #endif + + #define USB_OTG_HS_INTERNAL_DMA_ENABLED + #define USB_OTG_HS_DEDICATED_EP1_ENABLED +#endif /* USB_HS_CORE */ + +#define USB_SOF_OUTPUT 1 +#define USB_LOW_POWER 1 + +//#define VBUS_SENSING_ENABLED + +//#define USE_HOST_MODE +#define USE_DEVICE_MODE +//#define USE_OTG_MODE + +#ifndef USB_FS_CORE + #ifndef USB_HS_CORE + #error "USB_HS_CORE or USB_FS_CORE should be defined" + #endif +#endif + +#ifndef USE_DEVICE_MODE + #ifndef USE_HOST_MODE + #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" + #endif +#endif + +#ifndef USE_USB_HS + #ifndef USE_USB_FS + #error "USE_USB_HS or USE_USB_FS should be defined" + #endif +#endif + +/****************** C Compilers dependant keywords ****************************/ +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined (__GNUC__) /* GNU Compiler */ + #define __ALIGN_END __attribute__ ((aligned(4))) + #define __ALIGN_BEGIN + #endif /* __GNUC__ */ +#else + #define __ALIGN_BEGIN + #define __ALIGN_END +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + + +#endif /* __USB_CONF_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Include/usbd_conf.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Include/usbd_conf.h new file mode 100644 index 0000000..087f5a4 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Include/usbd_conf.h @@ -0,0 +1,55 @@ +/*! + \file usbd_conf.h + \brief the header file of USB device-mode configuration + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_CONF_H +#define __USBD_CONF_H + +#include "usb_conf.h" + +#define USBD_CFG_MAX_NUM 1 +#define USBD_ITF_MAX_NUM 1 + +#define USB_STR_DESC_MAX_SIZE 64 + +#define USB_STRING_COUNT 4U + +/* endpoint count used by the CDC ACM device */ +#define CDC_ACM_CMD_EP EP2_IN +#define CDC_ACM_DATA_IN_EP EP1_IN +#define CDC_ACM_DATA_OUT_EP EP3_OUT + +#define CDC_ACM_CMD_PACKET_SIZE 8 +#define CDC_ACM_DATA_PACKET_SIZE 64 + +#endif /* __USBD_CONF_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Source/app.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Source/app.c new file mode 100644 index 0000000..4b9ff25 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Source/app.c @@ -0,0 +1,98 @@ +/*! + \file main.c + \brief USB CDC ACM device + + \version 2019-6-5, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#include "drv_usb_hw.h" +#include "cdc_acm_core.h" +#include +#include +#include + + +extern uint8_t packet_sent, packet_receive; +extern uint32_t receive_length; + +usb_core_driver USB_OTG_dev = +{ + .dev = { + .desc = { + .dev_desc = (uint8_t *)&device_descriptor, + .config_desc = (uint8_t *)&configuration_descriptor, + .strings = usbd_strings, + } + } +}; + + +/*! + \brief main routine will construct a USB keyboard + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + eclic_global_interrupt_enable(); + + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL2_PRIO2); + + usb_rcu_config(); + + usb_timer_init(); + + usb_intr_config(); + + usbd_init (&USB_OTG_dev, USB_CORE_ENUM_FS, &usbd_cdc_cb); + + /* check if USB device is enumerated successfully */ + while (USBD_CONFIGURED != USB_OTG_dev.dev.cur_status) { + } + + while (1) { + if (USBD_CONFIGURED == USB_OTG_dev.dev.cur_status) { + if (1 == packet_receive && 1 == packet_sent) { + packet_sent = 0; + /* receive datas from the host when the last packet datas have sent to the host */ + cdc_acm_data_receive(&USB_OTG_dev); + } else { + if (0 != receive_length) { + /* send receive datas */ + cdc_acm_data_send(&USB_OTG_dev, receive_length); + receive_length = 0; + } + } + } + } +} + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Source/cdc_acm_core.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Source/cdc_acm_core.c new file mode 100644 index 0000000..4a3b59a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Source/cdc_acm_core.c @@ -0,0 +1,441 @@ +/*! + \file cdc_acm_core.c + \brief CDC ACM driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "cdc_acm_core.h" + + +#define USBD_VID 0x28e9 +#define USBD_PID 0x018a + +static uint32_t cdc_cmd = 0xFFU; + +uint8_t usb_data_buffer[CDC_ACM_DATA_PACKET_SIZE]; +uint8_t usb_cmd_buffer[CDC_ACM_CMD_PACKET_SIZE]; + +__IO uint8_t packet_sent = 1U; +__IO uint8_t packet_receive = 1U; +__IO uint32_t receive_length = 0U; + +//usbd_int_cb_struct *usbd_int_fops = NULL; + +typedef struct +{ + uint32_t dwDTERate; /* data terminal rate */ + uint8_t bCharFormat; /* stop bits */ + uint8_t bParityType; /* parity */ + uint8_t bDataBits; /* data bits */ +}line_coding_struct; + +line_coding_struct linecoding = +{ + 115200, /* baud rate */ + 0x00, /* stop bits - 1 */ + 0x00, /* parity - none */ + 0x08 /* num of bits 8 */ +}; + +/* note:it should use the C99 standard when compiling the below codes */ +/* USB standard device descriptor */ +const usb_desc_dev device_descriptor = +{ + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, + .bcdUSB = 0x0200, + .bDeviceClass = 0x02, + .bDeviceSubClass = 0x00, + .bDeviceProtocol = 0x00, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM +}; + +/* USB device configuration descriptor */ +usb_descriptor_configuration_set_struct configuration_descriptor = +{ + .config = + { + .header = + { + .bLength = USB_CFG_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = USB_CDC_ACM_CONFIG_DESC_SIZE, + .bNumInterfaces = 0x02, + .bConfigurationValue = 0x01, + .iConfiguration = 0x00, + .bmAttributes = 0x80, + .bMaxPower = 0x32 + }, + + .cdc_loopback_interface = + { + .header = + { + .bLength = USB_ITF_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x01, + .bInterfaceClass = 0x02, + .bInterfaceSubClass = 0x02, + .bInterfaceProtocol = 0x01, + .iInterface = 0x00 + }, + + .cdc_loopback_header = + { + .header = + { + .bLength = sizeof(usb_descriptor_header_function_struct), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x00, + .bcdCDC = 0x0110 + }, + + .cdc_loopback_call_managment = + { + .header = + { + .bLength = sizeof(usb_descriptor_call_managment_function_struct), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x01, + .bmCapabilities = 0x00, + .bDataInterface = 0x01 + }, + + .cdc_loopback_acm = + { + .header = + { + .bLength = sizeof(usb_descriptor_acm_function_struct), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x02, + .bmCapabilities = 0x02, + }, + + .cdc_loopback_union = + { + .header = + { + .bLength = sizeof(usb_descriptor_union_function_struct), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x06, + .bMasterInterface = 0x00, + .bSlaveInterface0 = 0x01, + }, + + .cdc_loopback_cmd_endpoint = + { + .header = + { + .bLength = USB_EP_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = CDC_ACM_CMD_EP, + .bmAttributes = 0x03, + .wMaxPacketSize = CDC_ACM_CMD_PACKET_SIZE, + .bInterval = 0x0A + }, + + .cdc_loopback_data_interface = + { + .header = + { + .bLength = USB_ITF_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x01, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x02, + .bInterfaceClass = 0x0A, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, + .iInterface = 0x00 + }, + + .cdc_loopback_out_endpoint = + { + .header = + { + .bLength = USB_EP_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = CDC_ACM_DATA_OUT_EP, + .bmAttributes = 0x02, + .wMaxPacketSize = CDC_ACM_DATA_PACKET_SIZE, + .bInterval = 0x00 + }, + + .cdc_loopback_in_endpoint = + { + .header = + { + .bLength = USB_EP_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = CDC_ACM_DATA_IN_EP, + .bmAttributes = 0x02, + .wMaxPacketSize = CDC_ACM_DATA_PACKET_SIZE, + .bInterval = 0x00 + } +}; + +/* USB language ID Descriptor */ +const usb_desc_LANGID usbd_language_id_desc = +{ + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + .wLANGID = ENG_LANGID +}; + +void* const usbd_strings[] = +{ + [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, + [STR_IDX_MFC] = USBD_STRING_DESC("GigaDevice"), + [STR_IDX_PRODUCT] = USBD_STRING_DESC("GD32 USB CDC ACM in FS Mode"), + [STR_IDX_SERIAL] = USBD_STRING_DESC("GD32XXX-3.0.0-7z8x9yer") +}; + +/*! + \brief initialize the CDC ACM device + \param[in] pudev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +uint8_t cdc_acm_init (usb_dev *pudev, uint8_t config_index) +{ + /* initialize the data Tx/Rx endpoint */ + usbd_ep_setup(pudev, &(configuration_descriptor.cdc_loopback_in_endpoint)); + usbd_ep_setup(pudev, &(configuration_descriptor.cdc_loopback_out_endpoint)); + + /* initialize the command Tx endpoint */ + usbd_ep_setup(pudev, &(configuration_descriptor.cdc_loopback_cmd_endpoint)); + + return USBD_OK; +} + +/*! + \brief de-initialize the CDC ACM device + \param[in] pudev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +uint8_t cdc_acm_deinit (usb_dev *pudev, uint8_t config_index) +{ + /* deinitialize the data Tx/Rx endpoint */ + usbd_ep_clear(pudev, CDC_ACM_DATA_IN_EP); + usbd_ep_clear(pudev, CDC_ACM_DATA_OUT_EP); + + /* deinitialize the command Tx endpoint */ + usbd_ep_clear(pudev, CDC_ACM_CMD_EP); + + return USBD_OK; +} + +/*! + \brief handle CDC ACM data + \param[in] pudev: pointer to USB device instance + \param[in] rx_tx: data transfer direction: + \arg USBD_TX + \arg USBD_RX + \param[in] ep_id: endpoint identifier + \param[out] none + \retval USB device operation status +*/ +uint8_t cdc_acm_data_out_handler (usb_dev *pudev, uint8_t ep_id) +{ + if ((EP0_OUT & 0x7F) == ep_id) + { + cdc_acm_EP0_RxReady (pudev); + } + else if ((CDC_ACM_DATA_OUT_EP & 0x7F) == ep_id) + { + packet_receive = 1; + receive_length = usbd_rxcount_get(pudev, CDC_ACM_DATA_OUT_EP); + + return USBD_OK; + } + return USBD_FAIL; +} + +uint8_t cdc_acm_data_in_handler (usb_dev *pudev, uint8_t ep_id) +{ + if ((CDC_ACM_DATA_IN_EP & 0x7F) == ep_id) + { + usb_transc *transc = &pudev->dev.transc_in[EP_ID(ep_id)]; + + if ((transc->xfer_len % transc->max_len == 0) && (transc->xfer_len != 0)) { + usbd_ep_send (pudev, ep_id, NULL, 0U); + } else { + packet_sent = 1; + } + return USBD_OK; + } + return USBD_FAIL; +} + + +/*! + \brief handle the CDC ACM class-specific requests + \param[in] pudev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +uint8_t cdc_acm_req_handler (usb_dev *pudev, usb_req *req) +{ + switch (req->bRequest) + { + case SEND_ENCAPSULATED_COMMAND: + break; + case GET_ENCAPSULATED_RESPONSE: + break; + case SET_COMM_FEATURE: + break; + case GET_COMM_FEATURE: + break; + case CLEAR_COMM_FEATURE: + break; + case SET_LINE_CODING: + /* set the value of the current command to be processed */ + cdc_cmd = req->bRequest; + /* enable EP0 prepare to receive command data packet */ + pudev->dev.transc_out[0].xfer_buf = usb_cmd_buffer; + pudev->dev.transc_out[0].remain_len = req->wLength; + break; + case GET_LINE_CODING: + usb_cmd_buffer[0] = (uint8_t)(linecoding.dwDTERate); + usb_cmd_buffer[1] = (uint8_t)(linecoding.dwDTERate >> 8); + usb_cmd_buffer[2] = (uint8_t)(linecoding.dwDTERate >> 16); + usb_cmd_buffer[3] = (uint8_t)(linecoding.dwDTERate >> 24); + usb_cmd_buffer[4] = linecoding.bCharFormat; + usb_cmd_buffer[5] = linecoding.bParityType; + usb_cmd_buffer[6] = linecoding.bDataBits; + /* send the request data to the host */ + pudev->dev.transc_in[0].xfer_buf = usb_cmd_buffer; + pudev->dev.transc_in[0].remain_len = req->wLength; + break; + case SET_CONTROL_LINE_STATE: + break; + case SEND_BREAK: + break; + default: + break; + } + + return USBD_OK; +} + +/*! + \brief receive CDC ACM data + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +void cdc_acm_data_receive(usb_dev *pudev) +{ + packet_receive = 0; + + usbd_ep_recev(pudev, CDC_ACM_DATA_OUT_EP, (uint8_t*)(usb_data_buffer), CDC_ACM_DATA_PACKET_SIZE); +} + +/*! + \brief send CDC ACM data + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +void cdc_acm_data_send (usb_dev *pudev, uint32_t data_len) +{ + /* limit the transfer data length */ + if (data_len <= CDC_ACM_DATA_PACKET_SIZE) { + packet_sent = 0; + usbd_ep_send(pudev, CDC_ACM_DATA_IN_EP, (uint8_t*)(usb_data_buffer), data_len); + } +} + +/*! + \brief command data received on control endpoint + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +uint8_t cdc_acm_EP0_RxReady (usb_dev *pudev) +{ + if (NO_CMD != cdc_cmd) { + /* process the command data */ + linecoding.dwDTERate = (uint32_t)(usb_cmd_buffer[0] | + (usb_cmd_buffer[1] << 8) | + (usb_cmd_buffer[2] << 16) | + (usb_cmd_buffer[3] << 24)); + + linecoding.bCharFormat = usb_cmd_buffer[4]; + linecoding.bParityType = usb_cmd_buffer[5]; + linecoding.bDataBits = usb_cmd_buffer[6]; + + cdc_cmd = NO_CMD; + } + + return USBD_OK; +} + + +usb_class_core usbd_cdc_cb = { + .command = NO_CMD, + .alter_set = 0, + + .init = cdc_acm_init, + .deinit = cdc_acm_deinit, + .req_proc = cdc_acm_req_handler, + .data_in = cdc_acm_data_in_handler, + .data_out = cdc_acm_data_out_handler +}; diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Source/gd32vf103_hw.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Source/gd32vf103_hw.c new file mode 100644 index 0000000..204c678 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Source/gd32vf103_hw.c @@ -0,0 +1,206 @@ +/*! + \file gd32vf103_hw.c + \brief USB hardware configuration for GD32VF103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include +#include +#include + + +#define TIM_MSEC_DELAY 0x01 +#define TIM_USEC_DELAY 0x02 + +__IO uint32_t delay_time = 0; +__IO uint32_t timer_prescaler; +__IO uint32_t usbfs_prescaler = 0; + +static void hw_time_set (uint8_t unit); +static void hw_delay (uint32_t ntime, uint8_t unit); + + +/*! + \brief configure USB clock + \param[in] none + \param[out] none + \retval none +*/ +void usb_rcu_config(void) +{ + uint32_t system_clock = rcu_clock_freq_get(CK_SYS); + + if (system_clock == 48000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1; + timer_prescaler = 3; + } else if (system_clock == 72000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1_5; + timer_prescaler = 5; + } else if (system_clock == 96000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV2; + timer_prescaler = 7; + } else { + /* reserved */ + } + + rcu_usb_clock_config(usbfs_prescaler); + rcu_periph_clock_enable(RCU_USBFS); +} + +/*! + \brief configure USB interrupt + \param[in] none + \param[out] none + \retval none +*/ +void usb_intr_config(void) +{ + eclic_irq_enable((uint8_t)USBFS_IRQn, 1, 0); + + /* enable the power module clock */ + rcu_periph_clock_enable(RCU_PMU); + + /* USB wakeup EXTI line configuration */ + exti_interrupt_flag_clear(EXTI_18); + exti_init(EXTI_18, EXTI_INTERRUPT, EXTI_TRIG_RISING); + exti_interrupt_enable(EXTI_18); + + eclic_irq_enable((uint8_t)USBFS_WKUP_IRQn, 3, 0); +} + +/*! + \brief initializes delay unit using Timer2 + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_init (void) +{ + rcu_periph_clock_enable(RCU_TIMER2); + + eclic_irq_enable(TIMER2_IRQn, 2, 0); +} + +/*! + \brief delay in micro seconds + \param[in] usec: value of delay required in micro seconds + \param[out] none + \retval none +*/ +void usb_udelay (const uint32_t usec) +{ + hw_delay(usec, TIM_USEC_DELAY); +} + +/*! + \brief delay in milli seconds + \param[in] msec: value of delay required in milli seconds + \param[out] none + \retval none +*/ +void usb_mdelay (const uint32_t msec) +{ + hw_delay(msec, TIM_MSEC_DELAY); +} + +/*! + \brief time base IRQ + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_irq (void) +{ + if (RESET != timer_flag_get(TIMER2, TIMER_FLAG_UP)){ + timer_flag_clear(TIMER2, TIMER_FLAG_UP); + + if (delay_time > 0x00U){ + delay_time--; + } else { + timer_disable(TIMER2); + } + } +} + +/*! + \brief delay routine based on TIM0 + \param[in] nTime: delay Time + \param[in] unit: delay Time unit = mili sec / micro sec + \param[out] none + \retval none +*/ +static void hw_delay(uint32_t ntime, uint8_t unit) +{ + delay_time = ntime; + + hw_time_set(unit); + + while (0U != delay_time) { + } + + timer_disable(TIMER2); +} + +/*! + \brief configures TIM0 for delay routine based on TIM0 + \param[in] unit: msec /usec + \param[out] none + \retval none +*/ +static void hw_time_set(uint8_t unit) +{ + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER2); + timer_deinit(TIMER2); + + if(TIM_USEC_DELAY == unit) { + timer_initpara.period = 11; + } else if(TIM_MSEC_DELAY == unit) { + timer_initpara.period = 11999; + } + + timer_initpara.prescaler = timer_prescaler; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER2, &timer_initpara); + + timer_update_event_enable(TIMER2); + timer_interrupt_enable(TIMER2,TIMER_INT_UP); + timer_flag_clear(TIMER2, TIMER_FLAG_UP); + timer_update_source_config(TIMER2, TIMER_UPDATE_SRC_GLOBAL); + + /* TIMER2 counter enable */ + timer_enable(TIMER2); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Source/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Source/gd32vf103_it.c new file mode 100644 index 0000000..8cae80e --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Source/gd32vf103_it.c @@ -0,0 +1,96 @@ +/*! + \file gd32vf103_it.c + \brief main interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usbd_int.h" +#include "drv_usb_hw.h" +#include "gd32vf103_it.h" + +extern usb_core_driver USB_OTG_dev; +extern uint32_t usbfs_prescaler; + +extern void usb_timer_irq(void); + +/*! + \brief this function handles USBD interrupt + \param[in] none + \param[out] none + \retval none +*/ +void USBFS_IRQHandler (void) +{ + usbd_isr (&USB_OTG_dev); +} + +/*! + \brief this function handles EXTI0_IRQ Handler + \param[in] none + \param[out] none + \retval none +*/ +void EXTI0_IRQHandler(void) +{ + +} + +/*! + \brief this function handles USBD wakeup interrupt request. + \param[in] none + \param[out] none + \retval none +*/ +void USBFS_WKUP_IRQHandler(void) +{ + if (USB_OTG_dev.bp.low_power) { + SystemInit(); + + rcu_usb_clock_config(usbfs_prescaler); + + rcu_periph_clock_enable(RCU_USBFS); + + usb_clock_active(&USB_OTG_dev); + } + + exti_interrupt_flag_clear(EXTI_18); +} + +/*! + \brief this function handles Timer0 updata interrupt request. + \param[in] none + \param[out] none + \retval none +*/ +void TIMER2_IRQHandler(void) +{ + usb_timer_irq(); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Source/system_gd32vf103.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Source/system_gd32vf103.c new file mode 100644 index 0000000..05e5205 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/Source/system_gd32vf103.c @@ -0,0 +1,998 @@ +/*! + \file system_gd32vf103.h + \brief RISC-V Device Peripheral Access Layer Source File for + GD32VF103 Device Series + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32vf103.h" + +/* system frequency define */ +#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ + +/* select a system clock by uncommenting the following line */ +/* use IRC8M */ +//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000) + +/********************************************************************/ +//#define __SYSTEM_CLOCK_HXTAL (HXTAL_VALUE) +//#define __SYSTEM_CLOCK_24M_PLL_HXTAL (uint32_t)(24000000) +/********************************************************************/ + +//#define __SYSTEM_CLOCK_36M_PLL_HXTAL (uint32_t)(36000000) +//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_56M_PLL_HXTAL (uint32_t)(56000000) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000) +//#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) + +#define SEL_IRC8M 0x00U +#define SEL_HXTAL 0x01U +#define SEL_PLL 0x02U + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_48M_PLL_IRC8M +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M; +static void system_clock_48m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M; +static void system_clock_72m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M; +static void system_clock_108m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; +static void system_clock_hxtal(void); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_24M_PLL_HXTAL; +static void system_clock_24m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_36M_PLL_HXTAL; +static void system_clock_36m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL; +static void system_clock_48m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_56M_PLL_HXTAL; +static void system_clock_56m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; +static void system_clock_72m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL; +static void system_clock_96m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; +static void system_clock_108m_hxtal(void); +#else +uint32_t SystemCoreClock = IRC8M_VALUE; +#endif /* __SYSTEM_CLOCK_48M_PLL_IRC8M */ + +/* configure the system clock */ +static void system_clock_config(void); + +/*! + \brief configure the system clock + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_config(void) +{ +#ifdef __SYSTEM_CLOCK_HXTAL + system_clock_hxtal(); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) + system_clock_24m_hxtal(); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) + system_clock_36m_hxtal(); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) + system_clock_48m_hxtal(); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) + system_clock_56m_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) + system_clock_72m_hxtal(); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) + system_clock_96m_hxtal(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) + system_clock_108m_hxtal(); + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) + system_clock_48m_irc8m(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) + system_clock_72m_irc8m(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) + system_clock_108m_irc8m(); +#endif /* __SYSTEM_CLOCK_HXTAL */ +} + +/*! + \brief setup the microcontroller system, initialize the system + \param[in] none + \param[out] none + \retval none +*/ +void SystemInit(void) +{ + /* reset the RCC clock configuration to the default reset state */ + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL); + + /* reset HXTALEN, CKMEN, PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); + + /* Reset HXTALBPS bit */ + RCU_CTL &= ~(RCU_CTL_HXTALBPS); + + /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */ + + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | + RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4); + RCU_CFG1 = 0x00000000U; + + /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + /* disable all interrupts */ + RCU_INT = 0x00FF0000U; + + /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ + system_clock_config(); +} + +/*! + \brief update the SystemCoreClock with current core clock retrieved from cpu registers + \param[in] none + \param[out] none + \retval none +*/ +void SystemCoreClockUpdate(void) +{ + uint32_t scss; + uint32_t pllsel, predv0sel, pllmf, ck_src; + uint32_t predv0, predv1, pll1mf; + + scss = GET_BITS(RCU_CFG0, 2, 3); + + switch (scss) + { + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + SystemCoreClock = IRC8M_VALUE; + break; + + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + SystemCoreClock = HXTAL_VALUE; + break; + + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + + + if(RCU_PLLSRC_IRC8M_DIV2 == pllsel){ + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE / 2U; + }else{ + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + + predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); + + /* source clock use PLL1 */ + if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ + predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; + pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; + if(17U == pll1mf){ + pll1mf = 20U; + } + ck_src = (ck_src / predv1) * pll1mf; + } + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; + ck_src /= predv0; + } + + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + + if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ + pllmf |= 0x10U; + } + + if(pllmf >= 15U){ + pllmf += 1U; + }else{ + pllmf += 2U; + } + + SystemCoreClock = ck_src * pllmf; + + if(15U == pllmf){ + /* PLL source clock multiply by 6.5 */ + SystemCoreClock = ck_src * 6U + ck_src / 2U; + } + + break; + + /* IRC8M is selected as CK_SYS */ + default: + SystemCoreClock = IRC8M_VALUE; + break; + } +} + +#ifdef __SYSTEM_CLOCK_HXTAL +/*! + \brief configure the system clock to HXTAL + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + + /* wait until HXTAL is selected as system clock */ + while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +/*! + \brief configure the system clock to 24M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_24m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 6 = 24 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +/*! + \brief configure the system clock to 36M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_36m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 9 = 36 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +/*! + \brief configure the system clock to 48M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12); + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +/*! + \brief configure the system clock to 56M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_56m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 14 = 56 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL14); + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +/*! + \brief configure the system clock to 72M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18); + + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +/*! + \brief configure the system clock to 96M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_96m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + if(HXTAL_VALUE==25000000){ + + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +/*! + \brief configure the system clock to 108M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ + +static void system_clock_108m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PREDV1_DIV5 | RCU_PLL1_MUL8 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL2EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){ + } + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 | RCU_PREDV1_DIV2 | RCU_PLL1_MUL20 | RCU_PLL2_MUL20); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } + + /* enable PLL2 */ + RCU_CTL |= RCU_CTL_PLL2EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){ + } + + } + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) +/*! + \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL12; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +/*! + \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL18; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +/*! + \brief configure the system clock to 108M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL27; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#endif diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/readme.txt new file mode 100644 index 0000000..461a43d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/CDC_ACM/readme.txt @@ -0,0 +1,56 @@ +/*! + \file readme.txt + \brief description of the USB CDC_ACM demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board,it provides a description of + how to use the USBFS. + + The target of this example is to read data from and write data to USB devices using +the CDC protocol. + + It makes the USB device look like a serial port (NO serial cable connectors: You +can see the data transferred to and from via USB instead of USB-to-USART bridge connection). + + This example loops back the contents of a text file over usb port. To run the example, +Type a message using the Pc's keyboard. Any data that shows in HyperTerminal is received +from the device. + + This CDC_ACM Demo provides the firmware examples for the GD32VF103V families. + + - OUT transfers (receive the data from the PC to GD32): + When a packet is received from the PC on the OUT pipe (EP3),by calling cdc_acm_data_receive() + it will be stored in the usb_data_buffer[]. + + - IN transfers (to send the data received from the GD32 to the PC): + When a packet is sent from the GD32 on the IN pipe (EP1), by calling cdc_acm_data_send(), + put the data into the usb_data_buffer[] buffer for sending data to the host. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Eclipse/usbd_dfu/.cproject b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Eclipse/usbd_dfu/.cproject new file mode 100644 index 0000000..c2537dc --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Eclipse/usbd_dfu/.cproject @@ -0,0 +1,202 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Eclipse/usbd_dfu/.project b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Eclipse/usbd_dfu/.project new file mode 100644 index 0000000..6901089 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Eclipse/usbd_dfu/.project @@ -0,0 +1,608 @@ + + + usbd_dfu + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Examples + 2 + virtual:/virtual + + + Firmware + 2 + virtual:/virtual + + + Utilities + 2 + virtual:/virtual + + + Examples/USBFS + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral + 2 + virtual:/virtual + + + Firmware/GD32VF103_usbfs_driver + 2 + virtual:/virtual + + + Firmware/RISCV + 2 + virtual:/virtual + + + Utilities/gd32vf103v_eval.c + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_eval.c + + + Utilities/gd32vf103v_eval.h + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_eval.h + + + Examples/USBFS/USB_Device + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Include + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Source + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/gd32vf103.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/gd32vf103.h + + + Firmware/GD32VF103_standard_peripheral/system_gd32vf103.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/system_gd32vf103.h + + + Firmware/GD32VF103_usbfs_driver/Include + 2 + virtual:/virtual + + + Firmware/GD32VF103_usbfs_driver/Source + 2 + virtual:/virtual + + + Firmware/RISCV/drivers + 2 + virtual:/virtual + + + Firmware/RISCV/env_Eclipse + 2 + virtual:/virtual + + + Firmware/RISCV/stubs + 2 + virtual:/virtual + + + Examples/USBFS/USB_Device/DFU + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_core.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_core.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_dev.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_dev.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_hw.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_hw.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_regs.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_regs.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usbd_int.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usbd_int.h + + + Firmware/GD32VF103_usbfs_driver/Include/usb_ch9_std.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usb_ch9_std.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbd_core.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbd_core.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbd_enum.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbd_enum.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbd_transc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbd_transc.h + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usb_core.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_core.c + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usb_dev.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_dev.c + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usbd_int.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usbd_int.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbd_core.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbd_core.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbd_enum.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbd_enum.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbd_transc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbd_transc.c + + + Firmware/RISCV/drivers/n200_eclic.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_eclic.h + + + Firmware/RISCV/drivers/n200_func.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_func.c + + + Firmware/RISCV/drivers/n200_func.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_func.h + + + Firmware/RISCV/drivers/n200_timer.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_timer.h + + + Firmware/RISCV/drivers/riscv_bits.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_bits.h + + + Firmware/RISCV/drivers/riscv_const.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_const.h + + + Firmware/RISCV/drivers/riscv_encoding.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_encoding.h + + + Firmware/RISCV/env_Eclipse/GD32VF103xB.lds + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/GD32VF103xB.lds + + + Firmware/RISCV/env_Eclipse/entry.S + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/entry.S + + + Firmware/RISCV/env_Eclipse/handlers.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/handlers.c + + + Firmware/RISCV/env_Eclipse/init.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/init.c + + + Firmware/RISCV/env_Eclipse/start.S + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/start.S + + + Firmware/RISCV/env_Eclipse/your_printf.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/your_printf.c + + + Firmware/RISCV/stubs/_exit.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/_exit.c + + + Firmware/RISCV/stubs/close.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/close.c + + + Firmware/RISCV/stubs/fstat.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/fstat.c + + + Firmware/RISCV/stubs/isatty.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/isatty.c + + + Firmware/RISCV/stubs/lseek.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/lseek.c + + + Firmware/RISCV/stubs/read.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/read.c + + + Firmware/RISCV/stubs/sbrk.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/sbrk.c + + + Firmware/RISCV/stubs/stub.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/stub.h + + + Firmware/RISCV/stubs/write.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/write.c + + + Firmware/RISCV/stubs/write_hex.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/write_hex.c + + + Examples/USBFS/USB_Device/DFU/Include + 2 + virtual:/virtual + + + Examples/USBFS/USB_Device/DFU/Source + 2 + virtual:/virtual + + + Examples/USBFS/USB_Device/DFU/Include/dfu_core.h + 1 + PARENT-2-PROJECT_LOC/Include/dfu_core.h + + + Examples/USBFS/USB_Device/DFU/Include/dfu_mal.h + 1 + PARENT-2-PROJECT_LOC/Include/dfu_mal.h + + + Examples/USBFS/USB_Device/DFU/Include/flash_if.h + 1 + PARENT-2-PROJECT_LOC/Include/flash_if.h + + + Examples/USBFS/USB_Device/DFU/Include/gd32vf103_it.h + 1 + PARENT-2-PROJECT_LOC/Include/gd32vf103_it.h + + + Examples/USBFS/USB_Device/DFU/Include/gd32vf103_libopt.h + 1 + PARENT-2-PROJECT_LOC/Include/gd32vf103_libopt.h + + + Examples/USBFS/USB_Device/DFU/Include/usb_conf.h + 1 + PARENT-2-PROJECT_LOC/Include/usb_conf.h + + + Examples/USBFS/USB_Device/DFU/Include/usbd_conf.h + 1 + PARENT-2-PROJECT_LOC/Include/usbd_conf.h + + + Examples/USBFS/USB_Device/DFU/Source/app.c + 1 + PARENT-2-PROJECT_LOC/Source/app.c + + + Examples/USBFS/USB_Device/DFU/Source/dfu_core.c + 1 + PARENT-2-PROJECT_LOC/Source/dfu_core.c + + + Examples/USBFS/USB_Device/DFU/Source/dfu_mal.c + 1 + PARENT-2-PROJECT_LOC/Source/dfu_mal.c + + + Examples/USBFS/USB_Device/DFU/Source/flash_if.c + 1 + PARENT-2-PROJECT_LOC/Source/flash_if.c + + + Examples/USBFS/USB_Device/DFU/Source/gd32vf103_hw.c + 1 + PARENT-2-PROJECT_LOC/Source/gd32vf103_hw.c + + + Examples/USBFS/USB_Device/DFU/Source/gd32vf103_it.c + 1 + PARENT-2-PROJECT_LOC/Source/gd32vf103_it.c + + + Examples/USBFS/USB_Device/DFU/Source/system_gd32vf103.c + 1 + PARENT-2-PROJECT_LOC/Source/system_gd32vf103.c + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Eclipse/usbd_dfu/.settings/language.settings.xml b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Eclipse/usbd_dfu/.settings/language.settings.xml new file mode 100644 index 0000000..f0951a1 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Eclipse/usbd_dfu/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/dfu_core.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/dfu_core.h new file mode 100644 index 0000000..05bb6d2 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/dfu_core.h @@ -0,0 +1,162 @@ +/*! + \file usbd_hid_core.h + \brief the header file of USB DFU device class core functions + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef DFU_CORE_H +#define DFU_CORE_H + +#include "usbd_enum.h" +#include "usb_ch9_std.h" +#include "usbd_transc.h" + +/* manifestation State */ +#define MANIFEST_COMPLETE 0x00 +#define MANIFEST_IN_PROGRESS 0x01 + +#define USB_DFU_DESC_SIZE 9 + +/* special commands with download request */ +#define GET_COMMANDS 0x00 +#define SET_ADDRESS_POINTER 0x21 +#define ERASE 0x41 +#define NO_CMD 0xFF + +/* memory operation command */ +#define CMD_ERASE 0 +#define CMD_WRITE 1 + +#define FLASH_ERASE_TIMEOUT 60 +#define FLASH_WRITE_TIMEOUT 80 + +/* bit detach capable = bit 3 in bmAttributes field */ +#define DFU_DETACH_MASK (uint8_t)(0x10) + +#define USB_SERIAL_STRING_SIZE 0x06 +#define DEVICE_ID (0x40022100) + +#define USB_DFU_CONFIG_DESC_SIZE (18 + (9 * USBD_ITF_MAX_NUM)) +#define DFU_DESC_TYPE 0x21 +#define FLASH_IF_STRING "@Internal Flash /0x08000000/16*002Ka,112*002Kg" + +/* DFU device state defines */ +typedef enum +{ + STATE_appIDLE = 0x00, + STATE_appDETACH, + STATE_dfuIDLE, + STATE_dfuDNLOAD_SYNC, + STATE_dfuDNBUSY, + STATE_dfuDNLOAD_IDLE, + STATE_dfuMANIFEST_SYNC, + STATE_dfuMANIFEST, + STATE_dfuMANIFEST_WAIT_RESET, + STATE_dfuUPLOAD_IDLE, + STATE_dfuERROR +}dfu_state_enum; + +/* DFU device status defines */ +typedef enum +{ + STATUS_OK = 0x00, + STATUS_errTARGET, + STATUS_errFILE, + STATUS_errWRITE, + STATUS_errERASE, + STATUS_errCHECK_ERASED, + STATUS_errPROG, + STATUS_errVERIFY, + STATUS_errADDRESS, + STATUS_errNOTDONE, + STATUS_errFIRMWARE, + STATUS_errVENDOR, + STATUS_errUSBR, + STATUS_errPOR, + STATUS_errUNKNOWN, + STATUS_errSTALLEDPKT +}dfu_status_enum; + +/* DFU class-specific requests */ +typedef enum +{ + DFU_DETACH = 0, + DFU_DNLOAD, + DFU_UPLOAD, + DFU_GETSTATUS, + DFU_CLRSTATUS, + DFU_GETSTATE, + DFU_ABORT, + DFU_REQ_MAX +}dfu_requests_enum; + +#pragma pack(1) + +/* USB dfu function descriptor struct */ +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bmAttributes; /*!< DFU attributes */ + uint16_t wDetachTimeOut; /*!< time, in milliseconds, that the device will wait after receipt of the DFU_DETACH request. If */ + uint16_t wTransferSize; /*!< maximum number of bytes that the device can accept per control-write transaction */ + uint16_t bcdDFUVersion; /*!< numeric expression identifying the version of the DFU Specification release. */ +} usb_dfu_function_descriptor_struct; + +#pragma pack() + +/* USB configuration descriptor struct */ +typedef struct +{ + usb_desc_config Config; + usb_desc_itf DFU_Interface; + usb_dfu_function_descriptor_struct DFU_Function_Desc; +} usb_descriptor_configuration_set_struct; + +typedef void (*pAppFunction) (void); + +extern void* const usbd_strings[USB_STRING_COUNT]; +extern const usb_desc_dev device_descripter; +extern const usb_descriptor_configuration_set_struct configuration_descriptor; + +extern usb_class_core usbd_dfu_cb; + +/* function declarations */ +/* initialize the MSC device */ +uint8_t dfu_init (usb_dev *pudev, uint8_t config_index); +/* de-initialize the MSC device */ +uint8_t dfu_deinit (usb_dev *pudev, uint8_t config_index); +/* handle the MSC class-specific requests */ +uint8_t dfu_req_handler (usb_dev *pudev, usb_req *req); +/* handle data Stage */ +uint8_t dfu_data_in_handler (usb_dev *pudev, uint8_t ep_num); +uint8_t dfu_data_out_handler (usb_dev *pudev, uint8_t ep_num); + +#endif /* DFU_CORE_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/dfu_mal.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/dfu_mal.h new file mode 100644 index 0000000..f252fbe --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/dfu_mal.h @@ -0,0 +1,78 @@ +/*! + \file usbd_dfu_mal.h + \brief USB DFU device media access layer header file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_DFU_MAL_H +#define USBD_DFU_MAL_H + +#include "usb_conf.h" +#include "usbd_conf.h" + +typedef struct _DFU_MAL_PROPERTY +{ + const uint8_t* pStrDesc; + uint8_t (*pMAL_Init) (void); + uint8_t (*pMAL_DeInit) (void); + uint8_t (*pMAL_Erase) (uint32_t Addr); + uint8_t (*pMAL_Write) (uint32_t Addr, uint32_t Len); + uint8_t* (*pMAL_Read) (uint32_t Addr, uint32_t Len); + uint8_t (*pMAL_CheckAdd) (uint32_t Addr); + const uint32_t EraseTimeout; + const uint32_t WriteTimeout; +} +DFU_MAL_Property_TypeDef; + +typedef enum +{ + MAL_OK = 0, + MAL_FAIL +} MAL_Status; + +#define _1st_BYTE(x) (uint8_t)((x) & 0xFF) /*!< addressing cycle 1st byte */ +#define _2nd_BYTE(x) (uint8_t)(((x) & 0xFF00) >> 8) /*!< addressing cycle 2nd byte */ +#define _3rd_BYTE(x) (uint8_t)(((x) & 0xFF0000) >> 16) /*!< addressing cycle 3rd byte */ + +#define SET_POLLING_TIMEOUT(x) buffer[1] = _1st_BYTE(x);\ + buffer[2] = _2nd_BYTE(x);\ + buffer[3] = _3rd_BYTE(x); + +uint8_t DFU_MAL_Init (void); +uint8_t DFU_MAL_DeInit (void); +uint8_t DFU_MAL_Erase (uint32_t Addr); +uint8_t DFU_MAL_Write (uint32_t Addr, uint32_t Len); +uint8_t* DFU_MAL_Read (uint32_t Addr, uint32_t Len); +uint8_t DFU_MAL_GetStatus (uint32_t Addr, uint8_t Cmd, uint8_t *buffer); + +extern uint8_t MAL_Buffer[TRANSFER_SIZE]; + +#endif /* USBD_DFU_MAL_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/flash_if.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/flash_if.h new file mode 100644 index 0000000..af53c09 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/flash_if.h @@ -0,0 +1,53 @@ +/*! + \file flash_if.h + \brief USB DFU device flash interface header file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef FLASH_IF_H +#define FLASH_IF_H + +#include "dfu_mal.h" + +#define FLASH_START_ADDR 0x08000000 + +#define OB_RDPT 0x1FFFF800 + +#define MAL_MASK_OB 0xFFFFFF00 + +#define FLASH_END_ADDR 0x08040000 +#define FLASH_IF_STRING "@Internal Flash /0x08000000/16*002Ka,112*002Kg" + +extern DFU_MAL_Property_TypeDef DFU_Flash_cb; + +extern fmc_state_enum Option_Byte_Write(uint32_t Mem_Add,uint8_t* data); + +#endif /* FLASH_IF_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/gd32vf103_it.h new file mode 100644 index 0000000..cc50acf --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/gd32vf103_it.h @@ -0,0 +1,54 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "usbd_core.h" + +/* function declarations */ +/* this function handles USB wakeup interrupt handler */ +void USBFS_WKUP_IRQHandler(void); +/* this function handles USBFS IRQ Handler */ +void USBFS_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/gd32vf103_libopt.h new file mode 100644 index 0000000..60680cf --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/usb_conf.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/usb_conf.h new file mode 100644 index 0000000..b36f0be --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/usb_conf.h @@ -0,0 +1,121 @@ +/*! + \file usb_conf.h + \brief USBFS driver basic configuration + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_CONF_H +#define __USB_CONF_H + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" + +#include + +#ifdef USE_USB_FS + #define USB_FS_CORE +#endif + +#ifdef USE_USB_HS + #define USB_HS_CORE +#endif + +#ifdef USB_FS_CORE + #define RX_FIFO_FS_SIZE 128 + #define TX0_FIFO_FS_SIZE 64 + #define TX1_FIFO_FS_SIZE 128 + #define TX2_FIFO_FS_SIZE 0 + #define TX3_FIFO_FS_SIZE 0 +#endif /* USB_FS_CORE */ + +#ifdef USB_HS_CORE + #define RX_FIFO_HS_SIZE 512 + #define TX0_FIFO_HS_SIZE 128 + #define TX1_FIFO_HS_SIZE 372 + #define TX2_FIFO_HS_SIZE 0 + #define TX3_FIFO_HS_SIZE 0 + #define TX4_FIFO_HS_SIZE 0 + #define TX5_FIFO_HS_SIZE 0 + + #ifdef USE_ULPI_PHY + #define USB_OTG_ULPI_PHY_ENABLED + #endif + + #ifdef USE_EMBEDDED_PHY + #define USB_OTG_EMBEDDED_PHY_ENABLED + #endif + + #define USB_OTG_HS_INTERNAL_DMA_ENABLED + #define USB_OTG_HS_DEDICATED_EP1_ENABLED +#endif /* USB_HS_CORE */ + +#define USB_SOF_OUTPUT 1 +#define USB_LOW_POWER 1 + +//#define VBUS_SENSING_ENABLED + +//#define USE_HOST_MODE +#define USE_DEVICE_MODE +//#define USE_OTG_MODE + +#ifndef USB_FS_CORE + #ifndef USB_HS_CORE + #error "USB_HS_CORE or USB_FS_CORE should be defined" + #endif +#endif + +#ifndef USE_DEVICE_MODE + #ifndef USE_HOST_MODE + #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" + #endif +#endif + +#ifndef USE_USB_HS + #ifndef USE_USB_FS + #error "USE_USB_HS or USE_USB_FS should be defined" + #endif +#endif + +/****************** C Compilers dependant keywords ****************************/ +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined (__GNUC__) /* GNU Compiler */ + #define __ALIGN_END __attribute__ ((aligned(4))) + #define __ALIGN_BEGIN + #endif /* __GNUC__ */ +#else + #define __ALIGN_BEGIN + #define __ALIGN_END +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + + +#endif /* __USB_CONF_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/usbd_conf.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/usbd_conf.h new file mode 100644 index 0000000..4ac3cdd --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Include/usbd_conf.h @@ -0,0 +1,73 @@ +/*! + \file usbd_conf.h + \brief the header file of USBHS device-mode configuration + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_CONF_H +#define USBD_CONF_H + +#include "usb_conf.h" + +#define USBD_CFG_MAX_NUM 1 +#define USBD_ITF_MAX_NUM 1 +#define USB_STR_DESC_MAX_SIZE 64 + +/* USB feature -- Self Powered */ +//#define USBD_SELF_POWERED + +/* USB user string supported */ +/* #define USB_SUPPORT_USER_STRING_DESC */ + +//#define USBD_DYNAMIC_DESCRIPTOR_CHANGE_ENABLED + +/* Maximum number of supported media (Flash) */ +#define MAX_USED_MEMORY_MEDIA 1 + +#define USB_STRING_COUNT 6 + +/* DFU maximum data packet size */ +#define TRANSFER_SIZE 2048 + +/* memory address from where user application will be loaded, which represents + the dfu code protected against write and erase operations.*/ +#define APP_LOADED_ADDR 0x08010000 + +/* Make sure the corresponding memory where the DFU code should not be loaded + cannot be erased or overwritten by DFU application. */ +#define IS_PROTECTED_AREA(addr) (uint8_t)(((addr >= 0x08000000) && (addr < (APP_LOADED_ADDR)))? 1 : 0) + +/* DFU endpoint define */ +#define DFU_IN_EP EP0_IN +#define DFU_OUT_EP EP0_OUT + + +#endif /* USBD_CONF_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/app.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/app.c new file mode 100644 index 0000000..6585ab1 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/app.c @@ -0,0 +1,117 @@ +/*! + \file app.c + \brief USB main routine for DFU + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "dfu_core.h" +#include +#include +#include +#include "riscv_encoding.h" + +pAppFunction Application; + +usb_core_driver USB_OTG_dev = +{ + .dev = { + .desc = { + .dev_desc = (uint8_t *)&device_descripter, + .config_desc = (uint8_t *)&configuration_descriptor, + .strings = usbd_strings, + } + } +}; + +extern uint8_t usbd_serial_string[]; +void serial_string_create(void); + +/*! + \brief main routine will construct a USB keyboard + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + eclic_global_interrupt_enable(); + + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL2_PRIO2); + + /* configure tamper key to run firmware */ + gd_eval_key_init(KEY_A, KEY_MODE_GPIO); + + usb_timer_init(); + + /* tamper key must be pressed on GD32207I-EVAL when power on */ + if (0 == gd_eval_key_state_get(KEY_A)) { + /* test if user code is programmed starting from address 0x08010000 */ + if (0x0001AAB1 == (*(__IO uint32_t*)APP_LOADED_ADDR)) { + clear_csr(mstatus, MSTATUS_MIE); + asm volatile ("jr %0 " :: "r"(APP_LOADED_ADDR)); + } + } + + /* configure USB clock */ + usb_rcu_config(); + + serial_string_create(); + + usb_intr_config(); + + usbd_init (&USB_OTG_dev, USB_CORE_ENUM_FS, &usbd_dfu_cb); + + /* check if USB device is enumerated successfully */ + while (USB_OTG_dev.dev.cur_status != USBD_CONFIGURED) { + } + + while (1) { + } +} + +/*! + \brief create the serial number string descriptor + \param[in] none + \param[out] none + \retval none +*/ +void serial_string_create (void) +{ + uint32_t device_serial = *(uint32_t*)DEVICE_ID; + + if(0 != device_serial) { + usbd_serial_string[2] = (uint8_t)device_serial; + usbd_serial_string[3] = (uint8_t)(device_serial >> 8); + usbd_serial_string[4] = (uint8_t)(device_serial >> 16); + usbd_serial_string[5] = (uint8_t)(device_serial >> 24); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/dfu_core.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/dfu_core.c new file mode 100644 index 0000000..ba69bc0 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/dfu_core.c @@ -0,0 +1,720 @@ +/*! + \file dfu_core.c + \brief USB DFU device class core functions + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "dfu_core.h" +#include "dfu_mal.h" +#include "drv_usb_hw.h" + +#define USBD_VID 0x28e9 +#define USBD_PID 0x0189 + +/* DFU requests management functions */ +static void DFU_Req_DETACH (usb_dev *pudev, usb_req *req); +static void DFU_Req_DNLOAD (usb_dev *pudev, usb_req *req); +static void DFU_Req_UPLOAD (usb_dev *pudev, usb_req *req); +static void DFU_Req_GETSTATUS (usb_dev *pudev); +static void DFU_Req_CLRSTATUS (usb_dev *pudev); +static void DFU_Req_GETSTATE (usb_dev *pudev); +static void DFU_Req_ABORT (usb_dev *pudev); +static void DFU_LeaveDFUMode (usb_dev *pudev); + +static uint8_t dfu_getstatus_complete (usb_dev *pudev); + +/* data management variables */ +extern const uint8_t* USBD_DFU_StringDesc[]; +extern uint8_t MAL_Buffer[]; + +/* state machine variables */ +uint8_t DeviceState = STATE_dfuIDLE; +uint8_t DeviceStatus[6] = +{ + STATUS_OK, /* bStatus: device status is OK */ + 0x00, /* bwPollTimeout: 0ms */ + 0x00, + 0x00, + STATE_dfuIDLE, /* bState: device state is dfuIDLE */ + 0x00 /* iString: index is 0 */ +}; + +uint32_t Manifest_State = MANIFEST_COMPLETE; + +/* data management variables */ +static uint16_t BlockNum = 0; +static uint16_t Length = 0; +static uint32_t BaseAddress = APP_LOADED_ADDR; /*!< user application base address to erase, program or read */ +static __IO uint32_t USBD_DFU_AltSet = 0; + +/* note:it should use the c99 standard when compiling the below codes */ +/* USB standard device descriptor */ +const usb_desc_dev device_descripter = +{ + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, + .bcdUSB = 0x0200, + .bDeviceClass = 0x00, + .bDeviceSubClass = 0x00, + .bDeviceProtocol = 0x00, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM +}; + +/* USB device configuration descriptor */ +const usb_descriptor_configuration_set_struct configuration_descriptor = +{ + .Config = + { + .header = + { + .bLength = USB_CFG_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = USB_DFU_CONFIG_DESC_SIZE, + .bNumInterfaces = 0x01, + .bConfigurationValue = 0x01, + .iConfiguration = 0x00, + .bmAttributes = 0x80, + .bMaxPower = 0x32 + }, + + .DFU_Interface = + { + .header = + { + .bLength = USB_ITF_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x00, + .bInterfaceClass = 0xFE, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x02, + .iInterface = 0x05 + }, + + .DFU_Function_Desc = + { + .header = + { + .bLength = sizeof(usb_dfu_function_descriptor_struct), + .bDescriptorType = DFU_DESC_TYPE + }, + .bmAttributes = 0x0B, + .wDetachTimeOut = 0x00FF, + .wTransferSize = TRANSFER_SIZE, + .bcdDFUVersion = 0x011A, + }, +}; + +/* USB language ID descriptor */ +const usb_desc_LANGID usbd_language_id_desc = +{ + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + .wLANGID = ENG_LANGID +}; + +/* USB serial string */ +uint8_t usbd_serial_string[USB_SERIAL_STRING_SIZE] = +{ + USB_SERIAL_STRING_SIZE, + USB_DESCTYPE_STR, +}; + +void* const usbd_strings[] = +{ + [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, + [STR_IDX_MFC] = USBD_STRING_DESC("GigaDevice"), + [STR_IDX_PRODUCT] = USBD_STRING_DESC("GD32 USB DFU in FS Mode"), + [STR_IDX_SERIAL] = usbd_serial_string, + [STR_IDX_CONFIG] = USBD_STRING_DESC("GD32 USB CONFIG"), + [STR_IDX_ITF] = USBD_STRING_DESC("@Internal Flash /0x08000000/16*002Ka,112*002Kg") + +}; + +/*! + \brief initialize the MSC device + \param[in] pudev: pointer to usb device instance + \param[in] config_index: configuration index + \param[out] none + \retval usb device operation status +*/ +uint8_t dfu_init (usb_dev *pudev, uint8_t config_index) +{ + /* initilialize the MAL(media access layer) */ + DFU_MAL_Init(); + + return USBD_OK; +} + +/*! + \brief de-initialize the MSC device + \param[in] pudev: pointer to usb device instance + \param[in] config_index: configuration index + \param[out] none + \retval usb device operation status +*/ +uint8_t dfu_deinit (usb_dev *pudev, uint8_t config_index) +{ + /* restore default state */ + DeviceState = STATE_dfuIDLE; + DeviceStatus[0] = STATUS_OK; + DeviceStatus[4] = DeviceState; + BlockNum = 0; + Length = 0; + + /* deinitilialize the MAL(media access layer) */ + DFU_MAL_DeInit(); + + return USBD_OK; +} + +/*! + \brief handle the MSC class-specific requests + \param[in] pudev: pointer to usb device instance + \param[in] req: device class-specific request + \param[out] none + \retval usb device operation status +*/ +uint8_t dfu_req_handler (usb_dev *pudev, usb_req *req) +{ + uint16_t len = 0; + uint8_t *pbuf = NULL; + + switch (req->bmRequestType & USB_REQTYPE_MASK) { + case USB_REQTYPE_CLASS: + switch (req->bRequest) { + case DFU_DNLOAD: + DFU_Req_DNLOAD(pudev, req); + break; + + case DFU_UPLOAD: + DFU_Req_UPLOAD(pudev, req); + break; + + case DFU_GETSTATUS: + DFU_Req_GETSTATUS(pudev); + break; + + case DFU_CLRSTATUS: + DFU_Req_CLRSTATUS(pudev); + break; + + case DFU_GETSTATE: + DFU_Req_GETSTATE(pudev); + break; + + case DFU_ABORT: + DFU_Req_ABORT(pudev); + break; + + case DFU_DETACH: + DFU_Req_DETACH(pudev, req); + break; + + default: + usbd_enum_error(pudev, req); + return USBD_FAIL; + } + break; + case USB_REQTYPE_STRD: + /* standard device request */ + switch (req->bRequest) { + case USB_GET_DESCRIPTOR: + if ((req->wValue >> 8) == DFU_DESC_TYPE) { + pbuf = (uint8_t*)(&configuration_descriptor.DFU_Function_Desc); + len = USB_MIN(USB_DFU_DESC_SIZE, req->wLength); + } + + pudev->dev.transc_in[0].xfer_buf = pbuf; + pudev->dev.transc_in[0].remain_len = len; + break; + case USB_GET_INTERFACE: + pudev->dev.transc_in[0].xfer_buf = (uint8_t *)&USBD_DFU_AltSet; + pudev->dev.transc_in[0].remain_len = 1; + break; + case USB_SET_INTERFACE: + USBD_DFU_AltSet = (uint8_t)(req->wValue); + usbd_ctl_status_send(pudev); + break; + default: + break; + } + break; + default: + break; + } + + return USBD_OK; +} + +/*! + \brief handle data Stage + \param[in] pudev: pointer to usb device instance + \param[in] rx_tx: the flag of Rx or Tx + \param[in] ep_id: the endpoint ID + \param[out] none + \retval usb device operation status +*/ +uint8_t dfu_data_in_handler (usb_dev *pudev, uint8_t ep_num) +{ + if ((DFU_IN_EP & 0x7F) == ep_num) { + dfu_getstatus_complete(pudev); + + return USBD_OK; + } else { + return USBD_FAIL; + } +} + +uint8_t dfu_data_out_handler (usb_dev *pudev, uint8_t ep_num) +{ + if (DFU_OUT_EP == ep_num) { + return USBD_OK; + } else { + return USBD_FAIL; + } +} + +/*! + \brief handle data IN stage in control endpoint 0 + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval usb device operation status +*/ +static uint8_t dfu_getstatus_complete (usb_dev *pudev) +{ + uint32_t Addr; + usb_req req; + + if (DeviceState == STATE_dfuDNBUSY) { + /* decode the special command*/ + if (BlockNum == 0) { + if ((MAL_Buffer[0] == GET_COMMANDS) && (Length == 1)) { + } else if ((MAL_Buffer[0] == SET_ADDRESS_POINTER) && (Length == 5)) { + BaseAddress = MAL_Buffer[1]; + BaseAddress += MAL_Buffer[2] << 8; + BaseAddress += MAL_Buffer[3] << 16; + BaseAddress += MAL_Buffer[4] << 24; + } else if ((MAL_Buffer[0] == ERASE) && (Length == 5)) { + BaseAddress = MAL_Buffer[1]; + BaseAddress += MAL_Buffer[2] << 8; + BaseAddress += MAL_Buffer[3] << 16; + BaseAddress += MAL_Buffer[4] << 24; + DFU_MAL_Erase(BaseAddress); + } else { + /* call the error management function (command will be NACKed) */ + req.bmRequestType = 0; + req.wLength = 1; + usbd_enum_error (pudev, &req); + } + /* regular download command */ + } else if (BlockNum > 1) { + /* decode the required address */ + Addr = ((BlockNum - 2) * TRANSFER_SIZE) + BaseAddress; + + /* preform the write operation */ + DFU_MAL_Write(Addr, Length); + BlockNum = 0; + } + + Length = 0; + + /* update the state machine */ + DeviceState = STATE_dfuDNLOAD_SYNC; + DeviceStatus[4] = DeviceState; + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; + + return USBD_OK; + /* manifestation in progress*/ + } else if (DeviceState == STATE_dfuMANIFEST) { + /* start leaving DFU mode */ + DFU_LeaveDFUMode(pudev); + } + + return USBD_OK; +} + +/*! + \brief handle the DFU_DETACH request + \param[in] pudev: pointer to usb device instance + \param[in] req: DFU class request + \param[out] none + \retval usb device operation status +*/ +static void DFU_Req_DETACH(usb_dev *pudev, usb_req *req) +{ + switch (DeviceState) { + case STATE_dfuIDLE: + case STATE_dfuDNLOAD_SYNC: + case STATE_dfuDNLOAD_IDLE: + case STATE_dfuMANIFEST_SYNC: + case STATE_dfuUPLOAD_IDLE: + /* update the state machine */ + DeviceState = STATE_dfuIDLE; + DeviceStatus[0] = STATUS_OK; + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; /* bwPollTimeout = 0ms */ + DeviceStatus[4] = DeviceState; + DeviceStatus[5] = 0; /* iString */ + BlockNum = 0; + Length = 0; + break; + + default: + break; + } + + /* check the detach capability in the DFU functional descriptor */ + if (configuration_descriptor.DFU_Function_Desc.wDetachTimeOut & DFU_DETACH_MASK) { + /* perform an Attach-Detach operation on USB bus */ + /* perform an unconnected operation on USB bus */ + usb_dev_disconnect(pudev); + + /* perform an connected operation on USB bus */ + usb_dev_connect(pudev); + } else { + /* wait for the period of time specified in detach request */ + usb_mdelay (req->wValue); + } +} + +/*! + \brief handle the DFU_DNLOAD request + \param[in] pudev: pointer to usb device instance + \param[in] req: DFU class request + \param[out] none + \retval usb device operation status +*/ +static void DFU_Req_DNLOAD(usb_dev *pudev, usb_req *req) +{ + /* data setup request */ + if (req->wLength > 0) { + if ((DeviceState == STATE_dfuIDLE) || (DeviceState == STATE_dfuDNLOAD_IDLE)) { + /* update the global length and block number */ + BlockNum = req->wValue; + Length = req->wLength; + + /* update the state machine */ + DeviceState = STATE_dfuDNLOAD_SYNC; + DeviceStatus[4] = DeviceState; + + /* prepare the reception of the buffer over EP0 */ + pudev->dev.transc_out[0].xfer_buf = (uint8_t*)MAL_Buffer; + pudev->dev.transc_out[0].remain_len = Length; + usbd_ctl_recev(pudev); + /* unsupported state */ + } else { + /* call the error management function (command will be nacked */ + usbd_enum_error (pudev, req); + } + /* 0 data DNLOAD request */ + } else { + /* end of DNLOAD operation*/ + if (DeviceState == STATE_dfuDNLOAD_IDLE || DeviceState == STATE_dfuIDLE) { + Manifest_State = MANIFEST_IN_PROGRESS; + DeviceState = STATE_dfuMANIFEST_SYNC; + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; + DeviceStatus[4] = DeviceState; + } else { + usbd_enum_error (pudev, req); + } + } +} + +/*! + \brief handles the DFU UPLOAD request. + \param[in] pudev: pointer to usb device instance + \param[in] req: DFU class request + \param[out] none + \retval none +*/ +static void DFU_Req_UPLOAD(usb_dev *pudev, usb_req *req) +{ + uint8_t *Phy_Addr = NULL; + uint32_t Addr = 0; + + /* data setup request */ + if (req->wLength > 0) { + if ((DeviceState == STATE_dfuIDLE) || (DeviceState == STATE_dfuUPLOAD_IDLE)) { + /* update the global langth and block number */ + BlockNum = req->wValue; + Length = req->wLength; + + /* set device poll timeout */ + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; + + /* DFU Get Command */ + if (BlockNum == 0) { + /* update the state machine */ + DeviceState = (Length > 3)? STATE_dfuIDLE : STATE_dfuUPLOAD_IDLE; + DeviceStatus[4] = DeviceState; + + /* store the values of all supported commands */ + MAL_Buffer[0] = GET_COMMANDS; + MAL_Buffer[1] = SET_ADDRESS_POINTER; + MAL_Buffer[2] = ERASE; + + /* send the status data over EP0 */ + pudev->dev.transc_in[0].xfer_buf = (uint8_t *)(&(MAL_Buffer[0])); + pudev->dev.transc_in[0].remain_len = 3; + usbd_ctl_send(pudev); + } else if (BlockNum > 1) { + DeviceState = STATE_dfuUPLOAD_IDLE ; + DeviceStatus[4] = DeviceState; + /* change is accelerated */ + Addr = ((BlockNum - 2) * TRANSFER_SIZE) + BaseAddress; + + /* return the physical address where data are stored */ + Phy_Addr = DFU_MAL_Read(Addr, Length); + + /* send the status data over EP0 */ + pudev->dev.transc_in[0].xfer_buf = Phy_Addr; + pudev->dev.transc_in[0].remain_len = Length; + usbd_ctl_send(pudev); + /* unsupported wBlockNum */ + } else { + DeviceState = STATUS_errSTALLEDPKT; + DeviceStatus[4] = DeviceState; + + usbd_enum_error (pudev, req); + } + } else { + Length = 0; + BlockNum = 0; + + usbd_enum_error (pudev, req); + } + } else { + DeviceState = STATE_dfuIDLE; + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; + DeviceStatus[4] = DeviceState; + } +} + +/*! + \brief handle the DFU_GETSTATUS request + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void DFU_Req_GETSTATUS(usb_dev *pudev) +{ + switch (DeviceState) { + case STATE_dfuDNLOAD_SYNC: + if (Length != 0) { + DeviceState = STATE_dfuDNBUSY; + DeviceStatus[4] = DeviceState; + + if (BlockNum == 0) { + if (MAL_Buffer[0] == ERASE) { + DFU_MAL_GetStatus(BaseAddress, CMD_ERASE, DeviceStatus); + } else { + DFU_MAL_GetStatus(BaseAddress, CMD_WRITE, DeviceStatus); + } + } + /* (wlength==0)*/ + } else { + DeviceState = STATE_dfuDNLOAD_IDLE; + DeviceStatus[4] = DeviceState; + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; + } + break; + + case STATE_dfuMANIFEST_SYNC: + if (Manifest_State == MANIFEST_IN_PROGRESS) { + DeviceState = STATE_dfuMANIFEST; + DeviceStatus[4] = DeviceState; + DeviceStatus[1] = 1; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; + /* bwPollTimeout = 1ms */ + } else if ((Manifest_State == MANIFEST_COMPLETE) && \ + (configuration_descriptor.DFU_Function_Desc.bmAttributes & 0x04)) { + DeviceState = STATE_dfuIDLE; + DeviceStatus[4] = DeviceState; + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; + } + break; + + default: + break; + } + + /* send the status data of DFU interface to host over EP0 */ + pudev->dev.transc_in[0].xfer_buf = (uint8_t *)(&(DeviceStatus[0])); + pudev->dev.transc_in[0].remain_len = 6; + usbd_ctl_send(pudev); +} + +/*! + \brief handle the DFU_CLRSTATUS request + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void DFU_Req_CLRSTATUS(usb_dev *pudev) +{ + if (DeviceState == STATE_dfuERROR) { + DeviceState = STATE_dfuIDLE; + DeviceStatus[0] = STATUS_OK; + } else { + /*State Error*/ + DeviceState = STATE_dfuERROR; + DeviceStatus[0] = STATUS_errUNKNOWN; + } + + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; /* bwPollTimeout = 0ms */ + DeviceStatus[4] = DeviceState; + DeviceStatus[5] = 0; /* iString: index = 0 */ +} + +/*! + \brief handle the DFU_GETSTATE request + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void DFU_Req_GETSTATE(usb_dev *pudev) +{ + /* send the current state of the DFU interface to host */ + pudev->dev.transc_in[0].xfer_buf = &DeviceState; + pudev->dev.transc_in[0].remain_len = 1; + usbd_ctl_send(pudev); +} + +/*! + \brief handle the DFU_ABORT request + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void DFU_Req_ABORT(usb_dev *pudev) +{ + switch (DeviceState) { + case STATE_dfuIDLE: + case STATE_dfuDNLOAD_SYNC: + case STATE_dfuDNLOAD_IDLE: + case STATE_dfuMANIFEST_SYNC: + case STATE_dfuUPLOAD_IDLE: + DeviceState = STATE_dfuIDLE; + DeviceStatus[0] = STATUS_OK; + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; /* bwPollTimeout = 0ms */ + DeviceStatus[4] = DeviceState; + DeviceStatus[5] = 0; /* iString: index = 0 */ + BlockNum = 0; + Length = 0; + break; + + default: + break; + } +} + +/*! + \brief leave DFU mode and reset device to jump to user loaded code + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval none +*/ +void DFU_LeaveDFUMode(usb_dev *pudev) +{ + Manifest_State = MANIFEST_COMPLETE; + + DeviceStatus[1] = 0; + DeviceStatus[2] = 0; + DeviceStatus[3] = 0; + + if (configuration_descriptor.DFU_Function_Desc.bmAttributes & 0x04) { + DeviceState = STATE_dfuMANIFEST_SYNC; + DeviceStatus[4] = DeviceState; + + return; + } else { + DeviceState = STATE_dfuMANIFEST_WAIT_RESET; + DeviceStatus[4] = DeviceState; + + /* disconnect the USB device */ + usb_dev_disconnect(pudev); + + /* deinitilialize the MAL(Media Access Layer) */ + DFU_MAL_DeInit(); + + /* generate system reset to allow jumping to the user code */ + eclic_system_reset(); + + /* this instruction will not be reached (system reset) */ + return; + } +} + +usb_class_core usbd_dfu_cb = { + .command = NO_CMD, + .alter_set = 0, + + .init = dfu_init, + .deinit = dfu_deinit, + .req_proc = dfu_req_handler, + .data_in = dfu_data_in_handler, + .data_out = dfu_data_out_handler +}; diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/dfu_mal.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/dfu_mal.c new file mode 100644 index 0000000..f374bb6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/dfu_mal.c @@ -0,0 +1,242 @@ +/*! + \file usbd_dfu_mal.c + \brief USB DFU device media access layer functions + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "dfu_mal.h" +#include "flash_if.h" +#include "drv_usb_hw.h" +#include "usbd_transc.h" + +extern usb_core_driver USB_OTG_dev; + +/* the reference tables of global memories callback and string descriptors. + to add a new memory, you can do as follows: + 1. modify the value of MAX_USED_MEDIA in usbd_dfu_mal.h + 2. add the pointer to the callback structure in this table + 3. add the pointer to the memory string descriptor in usbd_dfu_StringDesc table + no other operation is required. + */ +DFU_MAL_Property_TypeDef* tMALTab[MAX_USED_MEMORY_MEDIA] = { + &DFU_Flash_cb +}; + +/* the list of memory interface string descriptor pointers. this list + can be updated whenever a memory has to be added or removed */ +const uint8_t* USBD_DFU_StringDesc[MAX_USED_MEMORY_MEDIA] = +{ + (const uint8_t *)FLASH_IF_STRING +}; + +/* memory buffer for downloaded data */ +uint8_t MAL_Buffer[TRANSFER_SIZE]; + +static uint8_t DFU_MAL_CheckAddr (uint32_t Addr); + +/*! + \brief initialize the memory media on the GD32 + \param[in] none + \param[out] none + \retval MAL_OK +*/ +uint8_t DFU_MAL_Init (void) +{ + uint32_t memIdx = 0; + + /* initialize all supported memory medias */ + for (memIdx = 0; memIdx < MAX_USED_MEMORY_MEDIA; memIdx++) { + /* check if the memory media exists */ + if (tMALTab[memIdx]->pMAL_Init != NULL) { + tMALTab[memIdx]->pMAL_Init(); + } + } + + return MAL_OK; +} + +/*! + \brief deinitialize the memory media on the GD32 + \param[in] none + \param[out] none + \retval MAL_OK +*/ +uint8_t DFU_MAL_DeInit (void) +{ + uint32_t memIdx = 0; + + /* deinitializes all supported memory medias */ + for (memIdx = 0; memIdx < MAX_USED_MEMORY_MEDIA; memIdx++) { + /* check if the memory media exists */ + if (tMALTab[memIdx]->pMAL_DeInit != NULL) { + tMALTab[memIdx]->pMAL_DeInit(); + } + } + + return MAL_OK; +} + +/*! + \brief Erase a memory sector + \param[in] Addr: memory sector address/code + \param[out] none + \retval MAL_OK if all operations are OK, MAL_FAIL else +*/ +uint8_t DFU_MAL_Erase (uint32_t Addr) +{ + uint32_t memIdx = DFU_MAL_CheckAddr(Addr); + + /* check if the address is in protected area */ + if (IS_PROTECTED_AREA(Addr)) { + return MAL_FAIL; + } + + if (memIdx < MAX_USED_MEMORY_MEDIA) { + /* check if the operation is supported */ + if (tMALTab[memIdx]->pMAL_Erase != NULL) { + return tMALTab[memIdx]->pMAL_Erase(Addr); + } else { + return MAL_FAIL; + } + } else { + return MAL_FAIL; + } +} + +/*! + \brief write data to sectors of memory + \param[in] Addr: sector address/code + \param[in] Len: length of data to be written (in bytes) + \param[out] none + \retval MAL_OK if all operations are OK, MAL_FAIL else +*/ +uint8_t DFU_MAL_Write (uint32_t Addr, uint32_t Len) +{ + uint32_t memIdx = DFU_MAL_CheckAddr(Addr); + + /* check if the address is in protected area */ + if (IS_PROTECTED_AREA(Addr)) { + return MAL_FAIL; + } + + if ((Addr & MAL_MASK_OB) == OB_RDPT) { + usbd_ctl_status_recev (&USB_OTG_dev); + usb_mdelay(100); + Option_Byte_Write(Addr,MAL_Buffer); + eclic_system_reset(); + return MAL_OK; + } + + if (memIdx < MAX_USED_MEMORY_MEDIA) { + /* check if the operation is supported */ + if (tMALTab[memIdx]->pMAL_Write != NULL) { + return tMALTab[memIdx]->pMAL_Write(Addr, Len); + } else { + return MAL_FAIL; + } + } else { + return MAL_FAIL; + } +} + +/*! + \brief Read data from sectors of memory + \param[in] Addr: sector address/code + \param[in] Len: length of data to be written (in bytes) + \param[out] none + \retval Pointer to buffer +*/ +uint8_t* DFU_MAL_Read (uint32_t Addr, uint32_t Len) +{ + uint32_t memIdx = 0; + + if (Addr != OB_RDPT) { + memIdx = DFU_MAL_CheckAddr(Addr); + } + + if (memIdx < MAX_USED_MEMORY_MEDIA) { + /* check if the operation is supported */ + if (tMALTab[memIdx]->pMAL_Read != NULL) { + return tMALTab[memIdx]->pMAL_Read(Addr, Len); + } else { + return MAL_Buffer; + } + } else { + return MAL_Buffer; + } +} + +/*! + \brief get the status of a given memory and store in buffer + \param[in] Addr: sector address/code (allow to determine which memory will be addressed) + \param[in] Cmd: 0 for erase and 1 for write + \param[in] buffer: pointer to the buffer where the status data will be stored + \param[out] none + \retval MAL_OK if all operations are OK, MAL_FAIL else +*/ +uint8_t DFU_MAL_GetStatus (uint32_t Addr, uint8_t Cmd, uint8_t *buffer) +{ + uint32_t memIdx = DFU_MAL_CheckAddr(Addr); + + if (memIdx < MAX_USED_MEMORY_MEDIA) { + if (Cmd & 0x01) { + SET_POLLING_TIMEOUT(tMALTab[memIdx]->WriteTimeout); + } else { + SET_POLLING_TIMEOUT(tMALTab[memIdx]->EraseTimeout); + } + + return MAL_OK; + } else { + return MAL_FAIL; + } +} + +/*! + \brief Check the address is supported + \param[in] Addr: Sector address/code (allow to determine which memory will be addressed) + \param[out] none + \retval Index of the addressed memory +*/ +static uint8_t DFU_MAL_CheckAddr (uint32_t Addr) +{ + uint32_t memIdx = 0; + + /* check with all supported memories */ + for (memIdx = 0; memIdx < MAX_USED_MEMORY_MEDIA; memIdx++) { + /* if the check address is supported, return the memory index */ + if (tMALTab[memIdx]->pMAL_CheckAdd(Addr) == MAL_OK) { + return memIdx; + } + } + + /* if there is no memory found, return MAX_USED_MEDIA */ + return (MAX_USED_MEMORY_MEDIA); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/flash_if.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/flash_if.c new file mode 100644 index 0000000..9267b72 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/flash_if.c @@ -0,0 +1,209 @@ +/*! + \file usbd_flash_if.c + \brief USB DFU device flash interface functions + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + \version 2019-09-20, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "flash_if.h" +#include "dfu_mal.h" + +static uint8_t Flash_If_Init (void); +static uint8_t Flash_If_DeInit (void); +static uint8_t Flash_If_Erase (uint32_t Addr); +static uint8_t Flash_If_Write (uint32_t Addr, uint32_t Len); +static uint8_t* Flash_If_Read (uint32_t Addr, uint32_t Len); +static uint8_t Flash_If_CheckAddr (uint32_t Addr); + +/* USBD_DFU_FlashIf_Private_Variables */ +DFU_MAL_Property_TypeDef DFU_Flash_cb = +{ + (const uint8_t *)FLASH_IF_STRING, + + Flash_If_Init, + Flash_If_DeInit, + Flash_If_Erase, + Flash_If_Write, + Flash_If_Read, + Flash_If_CheckAddr, + 60, /* flash erase timeout in ms */ + 80 /* flash programming timeout in ms (80us * ram buffer size (1024 bytes) */ +}; + +/*! + \brief option Byte write routine. + \param[in] none + \param[out] none + \retval the state of the FMC after write option Byte operation +*/ +fmc_state_enum Option_Byte_Write(uint32_t Mem_Add,uint8_t* data) +{ + uint8_t index; + fmc_state_enum status ; + + /* unlock the flash program erase controller */ + fmc_unlock(); + + /* clear pending flags */ + fmc_flag_clear(FMC_FLAG_PGERR | FMC_FLAG_WPERR | FMC_FLAG_END); + + status = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* Authorize the small information block programming */ + ob_unlock(); + + /* start erase the option byte */ + FMC_CTL |= FMC_CTL_OBER; + FMC_CTL |= FMC_CTL_START; + + status = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + FMC_CTL &= ~FMC_CTL_OBER; + /* set the OBPG bit */ + FMC_CTL |= FMC_CTL_OBPG; + + /*OptionBytes always have 16Bytes*/ + for(index = 0;index<15;index=index+2) + { + *(__IO uint16_t*)Mem_Add = data[index]&0xff; + + Mem_Add = Mem_Add + 2; + + status = fmc_ready_wait(FMC_TIMEOUT_COUNT); + } + + /* if the program operation is completed, disable the OPTPG Bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + + fmc_lock(); + + return status; +} + +/*! + \brief flash memory interface initialization routine. + \param[in] none + \param[out] none + \retval MAL_OK if the operation is right, MAL_FAIL else +*/ +static uint8_t Flash_If_Init (void) +{ + /* unlock the internal flash */ + fmc_unlock(); + + return MAL_OK; +} + +/*! + \brief flash memory interface deinitialization routine. + \param[in] none + \param[out] none + \retval MAL_OK if all operation is right, MAL_FAIL else +*/ +static uint8_t Flash_If_DeInit (void) +{ + /* lock the internal flash */ + fmc_lock(); + + return MAL_OK; +} + +/*! + \brief erase flash sector + \param[in] Addr: address to be written to. + \param[out] none + \retval MAL_OK +*/ +static uint8_t Flash_If_Erase (uint32_t Addr) +{ + fmc_page_erase(Addr); + + return MAL_OK; +} + +/*! + \brief flash memory write routine + \param[in] Addr: address to be written to + \param[in] Len: length of data to be written (in bytes). + \param[out] none + \retval MAL_OK +*/ +static uint8_t Flash_If_Write (uint32_t Addr, uint32_t Len) +{ + uint32_t idx = 0; + + /* unlock the flash program erase controller */ + fmc_unlock(); + + /* not an aligned data */ + if (Len & 0x03) { + for (idx = Len; idx < ((Len & 0xFFFC) + 4); idx++) { + MAL_Buffer[idx] = 0xFF; + } + } + + /* data received are word multiple */ + for (idx = 0; idx < Len; idx += 4) { + fmc_word_program(Addr, *(uint32_t *)(MAL_Buffer + idx)); + Addr += 4; + } + + fmc_lock(); + + return MAL_OK; +} + +/*! + \brief flash memory read routine + \param[in] Addr: address to be read from + \param[in] Len: length of data to be read (in bytes) + \param[out] none + \retval Pointer to the physical address where data should be read +*/ +static uint8_t *Flash_If_Read (uint32_t Addr, uint32_t Len) +{ + return (uint8_t *)(Addr); +} + +/*! + \brief check if the address is an allowed address for this memory + \param[in] Addr: address to be checked. + \param[out] none + \retval MAL_OK if the address is allowed, MAL_FAIL else. +*/ +static uint8_t Flash_If_CheckAddr (uint32_t Addr) +{ + if ((Addr >= FLASH_START_ADDR) && (Addr < FLASH_END_ADDR)) { + return MAL_OK; + } else { + return MAL_FAIL; + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/gd32vf103_hw.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/gd32vf103_hw.c new file mode 100644 index 0000000..204c678 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/gd32vf103_hw.c @@ -0,0 +1,206 @@ +/*! + \file gd32vf103_hw.c + \brief USB hardware configuration for GD32VF103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include +#include +#include + + +#define TIM_MSEC_DELAY 0x01 +#define TIM_USEC_DELAY 0x02 + +__IO uint32_t delay_time = 0; +__IO uint32_t timer_prescaler; +__IO uint32_t usbfs_prescaler = 0; + +static void hw_time_set (uint8_t unit); +static void hw_delay (uint32_t ntime, uint8_t unit); + + +/*! + \brief configure USB clock + \param[in] none + \param[out] none + \retval none +*/ +void usb_rcu_config(void) +{ + uint32_t system_clock = rcu_clock_freq_get(CK_SYS); + + if (system_clock == 48000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1; + timer_prescaler = 3; + } else if (system_clock == 72000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1_5; + timer_prescaler = 5; + } else if (system_clock == 96000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV2; + timer_prescaler = 7; + } else { + /* reserved */ + } + + rcu_usb_clock_config(usbfs_prescaler); + rcu_periph_clock_enable(RCU_USBFS); +} + +/*! + \brief configure USB interrupt + \param[in] none + \param[out] none + \retval none +*/ +void usb_intr_config(void) +{ + eclic_irq_enable((uint8_t)USBFS_IRQn, 1, 0); + + /* enable the power module clock */ + rcu_periph_clock_enable(RCU_PMU); + + /* USB wakeup EXTI line configuration */ + exti_interrupt_flag_clear(EXTI_18); + exti_init(EXTI_18, EXTI_INTERRUPT, EXTI_TRIG_RISING); + exti_interrupt_enable(EXTI_18); + + eclic_irq_enable((uint8_t)USBFS_WKUP_IRQn, 3, 0); +} + +/*! + \brief initializes delay unit using Timer2 + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_init (void) +{ + rcu_periph_clock_enable(RCU_TIMER2); + + eclic_irq_enable(TIMER2_IRQn, 2, 0); +} + +/*! + \brief delay in micro seconds + \param[in] usec: value of delay required in micro seconds + \param[out] none + \retval none +*/ +void usb_udelay (const uint32_t usec) +{ + hw_delay(usec, TIM_USEC_DELAY); +} + +/*! + \brief delay in milli seconds + \param[in] msec: value of delay required in milli seconds + \param[out] none + \retval none +*/ +void usb_mdelay (const uint32_t msec) +{ + hw_delay(msec, TIM_MSEC_DELAY); +} + +/*! + \brief time base IRQ + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_irq (void) +{ + if (RESET != timer_flag_get(TIMER2, TIMER_FLAG_UP)){ + timer_flag_clear(TIMER2, TIMER_FLAG_UP); + + if (delay_time > 0x00U){ + delay_time--; + } else { + timer_disable(TIMER2); + } + } +} + +/*! + \brief delay routine based on TIM0 + \param[in] nTime: delay Time + \param[in] unit: delay Time unit = mili sec / micro sec + \param[out] none + \retval none +*/ +static void hw_delay(uint32_t ntime, uint8_t unit) +{ + delay_time = ntime; + + hw_time_set(unit); + + while (0U != delay_time) { + } + + timer_disable(TIMER2); +} + +/*! + \brief configures TIM0 for delay routine based on TIM0 + \param[in] unit: msec /usec + \param[out] none + \retval none +*/ +static void hw_time_set(uint8_t unit) +{ + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER2); + timer_deinit(TIMER2); + + if(TIM_USEC_DELAY == unit) { + timer_initpara.period = 11; + } else if(TIM_MSEC_DELAY == unit) { + timer_initpara.period = 11999; + } + + timer_initpara.prescaler = timer_prescaler; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER2, &timer_initpara); + + timer_update_event_enable(TIMER2); + timer_interrupt_enable(TIMER2,TIMER_INT_UP); + timer_flag_clear(TIMER2, TIMER_FLAG_UP); + timer_update_source_config(TIMER2, TIMER_UPDATE_SRC_GLOBAL); + + /* TIMER2 counter enable */ + timer_enable(TIMER2); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/gd32vf103_it.c new file mode 100644 index 0000000..f46e7c3 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/gd32vf103_it.c @@ -0,0 +1,96 @@ +/*! + \file gd32vf103_it.c + \brief main interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usbd_int.h" +#include "drv_usb_hw.h" +#include "gd32vf103_it.h" + +extern usb_core_driver USB_OTG_dev; +extern uint32_t usbfs_prescaler; + +extern void usb_timer_irq (void); + +/*! + \brief this function handles USBD interrupt + \param[in] none + \param[out] none + \retval none +*/ +void USBFS_IRQHandler (void) +{ + usbd_isr (&USB_OTG_dev); +} + +/*! + \brief this function handles EXTI0_IRQ Handler + \param[in] none + \param[out] none + \retval none +*/ +void EXTI0_IRQHandler(void) +{ + +} + +/*! + \brief this function handles USBD wakeup interrupt request. + \param[in] none + \param[out] none + \retval none +*/ +void USBFS_WKUP_IRQHandler(void) +{ + if (USB_OTG_dev.bp.low_power) { + SystemInit(); + + rcu_usb_clock_config(usbfs_prescaler); + + rcu_periph_clock_enable(RCU_USBFS); + + usb_clock_active(&USB_OTG_dev); + } + + exti_interrupt_flag_clear(EXTI_18); +} + +/*! + \brief this function handles Timer0 updata interrupt request. + \param[in] none + \param[out] none + \retval none +*/ +void TIMER2_IRQHandler(void) +{ + usb_timer_irq(); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/system_gd32vf103.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/system_gd32vf103.c new file mode 100644 index 0000000..05e5205 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/Source/system_gd32vf103.c @@ -0,0 +1,998 @@ +/*! + \file system_gd32vf103.h + \brief RISC-V Device Peripheral Access Layer Source File for + GD32VF103 Device Series + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32vf103.h" + +/* system frequency define */ +#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ + +/* select a system clock by uncommenting the following line */ +/* use IRC8M */ +//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000) + +/********************************************************************/ +//#define __SYSTEM_CLOCK_HXTAL (HXTAL_VALUE) +//#define __SYSTEM_CLOCK_24M_PLL_HXTAL (uint32_t)(24000000) +/********************************************************************/ + +//#define __SYSTEM_CLOCK_36M_PLL_HXTAL (uint32_t)(36000000) +//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_56M_PLL_HXTAL (uint32_t)(56000000) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000) +//#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) + +#define SEL_IRC8M 0x00U +#define SEL_HXTAL 0x01U +#define SEL_PLL 0x02U + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_48M_PLL_IRC8M +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M; +static void system_clock_48m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M; +static void system_clock_72m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M; +static void system_clock_108m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; +static void system_clock_hxtal(void); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_24M_PLL_HXTAL; +static void system_clock_24m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_36M_PLL_HXTAL; +static void system_clock_36m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL; +static void system_clock_48m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_56M_PLL_HXTAL; +static void system_clock_56m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; +static void system_clock_72m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL; +static void system_clock_96m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; +static void system_clock_108m_hxtal(void); +#else +uint32_t SystemCoreClock = IRC8M_VALUE; +#endif /* __SYSTEM_CLOCK_48M_PLL_IRC8M */ + +/* configure the system clock */ +static void system_clock_config(void); + +/*! + \brief configure the system clock + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_config(void) +{ +#ifdef __SYSTEM_CLOCK_HXTAL + system_clock_hxtal(); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) + system_clock_24m_hxtal(); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) + system_clock_36m_hxtal(); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) + system_clock_48m_hxtal(); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) + system_clock_56m_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) + system_clock_72m_hxtal(); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) + system_clock_96m_hxtal(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) + system_clock_108m_hxtal(); + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) + system_clock_48m_irc8m(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) + system_clock_72m_irc8m(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) + system_clock_108m_irc8m(); +#endif /* __SYSTEM_CLOCK_HXTAL */ +} + +/*! + \brief setup the microcontroller system, initialize the system + \param[in] none + \param[out] none + \retval none +*/ +void SystemInit(void) +{ + /* reset the RCC clock configuration to the default reset state */ + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL); + + /* reset HXTALEN, CKMEN, PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); + + /* Reset HXTALBPS bit */ + RCU_CTL &= ~(RCU_CTL_HXTALBPS); + + /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */ + + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | + RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4); + RCU_CFG1 = 0x00000000U; + + /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + /* disable all interrupts */ + RCU_INT = 0x00FF0000U; + + /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ + system_clock_config(); +} + +/*! + \brief update the SystemCoreClock with current core clock retrieved from cpu registers + \param[in] none + \param[out] none + \retval none +*/ +void SystemCoreClockUpdate(void) +{ + uint32_t scss; + uint32_t pllsel, predv0sel, pllmf, ck_src; + uint32_t predv0, predv1, pll1mf; + + scss = GET_BITS(RCU_CFG0, 2, 3); + + switch (scss) + { + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + SystemCoreClock = IRC8M_VALUE; + break; + + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + SystemCoreClock = HXTAL_VALUE; + break; + + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + + + if(RCU_PLLSRC_IRC8M_DIV2 == pllsel){ + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE / 2U; + }else{ + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + + predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); + + /* source clock use PLL1 */ + if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ + predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; + pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; + if(17U == pll1mf){ + pll1mf = 20U; + } + ck_src = (ck_src / predv1) * pll1mf; + } + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; + ck_src /= predv0; + } + + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + + if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ + pllmf |= 0x10U; + } + + if(pllmf >= 15U){ + pllmf += 1U; + }else{ + pllmf += 2U; + } + + SystemCoreClock = ck_src * pllmf; + + if(15U == pllmf){ + /* PLL source clock multiply by 6.5 */ + SystemCoreClock = ck_src * 6U + ck_src / 2U; + } + + break; + + /* IRC8M is selected as CK_SYS */ + default: + SystemCoreClock = IRC8M_VALUE; + break; + } +} + +#ifdef __SYSTEM_CLOCK_HXTAL +/*! + \brief configure the system clock to HXTAL + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + + /* wait until HXTAL is selected as system clock */ + while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +/*! + \brief configure the system clock to 24M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_24m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 6 = 24 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +/*! + \brief configure the system clock to 36M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_36m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 9 = 36 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +/*! + \brief configure the system clock to 48M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12); + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +/*! + \brief configure the system clock to 56M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_56m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 14 = 56 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL14); + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +/*! + \brief configure the system clock to 72M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18); + + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +/*! + \brief configure the system clock to 96M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_96m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + if(HXTAL_VALUE==25000000){ + + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +/*! + \brief configure the system clock to 108M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ + +static void system_clock_108m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PREDV1_DIV5 | RCU_PLL1_MUL8 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL2EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){ + } + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 | RCU_PREDV1_DIV2 | RCU_PLL1_MUL20 | RCU_PLL2_MUL20); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } + + /* enable PLL2 */ + RCU_CTL |= RCU_CTL_PLL2EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){ + } + + } + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) +/*! + \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL12; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +/*! + \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL18; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +/*! + \brief configure the system clock to 108M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL27; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#endif diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/readme.txt new file mode 100644 index 0000000..5a34bcc --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/DFU/readme.txt @@ -0,0 +1,58 @@ +/*! + \file readme.txt + \brief description of the USB DFU demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board,it presents the implementation +of a device firmware upgrade (DFU) capability in the GD32 USB device. + + It follows the DFU class specification defined by the USB Implementers Forum for +reprogramming an application through USBFS. + + The DFU principle is particularly well suited to USBFS applications that +need to be reprogrammed in the field. + + To test the demo, you need a configuration hex image or bin image . The hex image +and the bin image should set application address at 0x8010000. + + You need install the corresponding GD DFU Driver with your PC operation system. + + Once the configuration *.hex image is generated, it can be downloaded into +internal flash memory using the GD tool "GD MCU Dfu Tool" available for download +from www.gd32mcu.21ic.com. + + The GD tool "GD MCU Dfu Tool" also can operate the option Byte. + + The supported memory for this example is the internal flash memory, you can also +add a new memory interface if you have extral memory. + +After each device reset, hold down the key A on the GD32VF103V-EVAL board. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Eclipse/in_application_program/.cproject b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Eclipse/in_application_program/.cproject new file mode 100644 index 0000000..a69de3d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Eclipse/in_application_program/.cproject @@ -0,0 +1,259 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Eclipse/in_application_program/.project b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Eclipse/in_application_program/.project new file mode 100644 index 0000000..5a6f5ea --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Eclipse/in_application_program/.project @@ -0,0 +1,588 @@ + + + in_application_program + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Examples + 2 + virtual:/virtual + + + Firmware + 2 + virtual:/virtual + + + Utilities + 2 + virtual:/virtual + + + Examples/USBFS + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral + 2 + virtual:/virtual + + + Firmware/GD32VF103_usbfs_driver + 2 + virtual:/virtual + + + Firmware/RISCV + 2 + virtual:/virtual + + + Utilities/gd32vf103v_eval.c + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_eval.c + + + Utilities/gd32vf103v_eval.h + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_eval.h + + + Examples/USBFS/USB_Device + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Include + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Source + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/gd32vf103.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/gd32vf103.h + + + Firmware/GD32VF103_standard_peripheral/system_gd32vf103.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/system_gd32vf103.h + + + Firmware/GD32VF103_usbfs_driver/Include + 2 + virtual:/virtual + + + Firmware/GD32VF103_usbfs_driver/Source + 2 + virtual:/virtual + + + Firmware/RISCV/drivers + 2 + virtual:/virtual + + + Firmware/RISCV/env_Eclipse + 2 + virtual:/virtual + + + Firmware/RISCV/stubs + 2 + virtual:/virtual + + + Examples/USBFS/USB_Device/HID_IAP + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_core.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_core.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_dev.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_dev.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_hw.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_hw.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_regs.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_regs.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usbd_int.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usbd_int.h + + + Firmware/GD32VF103_usbfs_driver/Include/usb_ch9_std.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usb_ch9_std.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbd_core.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbd_core.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbd_enum.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbd_enum.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbd_transc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbd_transc.h + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usb_core.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_core.c + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usb_dev.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_dev.c + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usbd_int.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usbd_int.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbd_core.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbd_core.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbd_enum.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbd_enum.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbd_transc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbd_transc.c + + + Firmware/RISCV/drivers/n200_eclic.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_eclic.h + + + Firmware/RISCV/drivers/n200_func.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_func.c + + + Firmware/RISCV/drivers/n200_func.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_func.h + + + Firmware/RISCV/drivers/n200_timer.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_timer.h + + + Firmware/RISCV/drivers/riscv_bits.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_bits.h + + + Firmware/RISCV/drivers/riscv_const.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_const.h + + + Firmware/RISCV/drivers/riscv_encoding.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_encoding.h + + + Firmware/RISCV/env_Eclipse/GD32VF103xB.lds + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/GD32VF103xB.lds + + + Firmware/RISCV/env_Eclipse/entry.S + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/entry.S + + + Firmware/RISCV/env_Eclipse/handlers.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/handlers.c + + + Firmware/RISCV/env_Eclipse/init.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/init.c + + + Firmware/RISCV/env_Eclipse/start.S + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/start.S + + + Firmware/RISCV/env_Eclipse/your_printf.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/your_printf.c + + + Firmware/RISCV/stubs/_exit.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/_exit.c + + + Firmware/RISCV/stubs/close.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/close.c + + + Firmware/RISCV/stubs/fstat.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/fstat.c + + + Firmware/RISCV/stubs/isatty.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/isatty.c + + + Firmware/RISCV/stubs/lseek.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/lseek.c + + + Firmware/RISCV/stubs/read.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/read.c + + + Firmware/RISCV/stubs/sbrk.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/sbrk.c + + + Firmware/RISCV/stubs/stub.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/stub.h + + + Firmware/RISCV/stubs/write.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/write.c + + + Firmware/RISCV/stubs/write_hex.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/write_hex.c + + + Examples/USBFS/USB_Device/HID_IAP/Include + 2 + virtual:/virtual + + + Examples/USBFS/USB_Device/HID_IAP/Source + 2 + virtual:/virtual + + + Examples/USBFS/USB_Device/HID_IAP/Include/gd32vf103_it.h + 1 + PARENT-2-PROJECT_LOC/Include/gd32vf103_it.h + + + Examples/USBFS/USB_Device/HID_IAP/Include/gd32vf103_libopt.h + 1 + PARENT-2-PROJECT_LOC/Include/gd32vf103_libopt.h + + + Examples/USBFS/USB_Device/HID_IAP/Include/iap_core.h + 1 + PARENT-2-PROJECT_LOC/Include/iap_core.h + + + Examples/USBFS/USB_Device/HID_IAP/Include/usb_conf.h + 1 + PARENT-2-PROJECT_LOC/Include/usb_conf.h + + + Examples/USBFS/USB_Device/HID_IAP/Include/usbd_conf.h + 1 + PARENT-2-PROJECT_LOC/Include/usbd_conf.h + + + Examples/USBFS/USB_Device/HID_IAP/Source/app.c + 1 + PARENT-2-PROJECT_LOC/Source/app.c + + + Examples/USBFS/USB_Device/HID_IAP/Source/gd32vf103_hw.c + 1 + PARENT-2-PROJECT_LOC/Source/gd32vf103_hw.c + + + Examples/USBFS/USB_Device/HID_IAP/Source/gd32vf103_it.c + 1 + PARENT-2-PROJECT_LOC/Source/gd32vf103_it.c + + + Examples/USBFS/USB_Device/HID_IAP/Source/iap_core.c + 1 + PARENT-2-PROJECT_LOC/Source/iap_core.c + + + Examples/USBFS/USB_Device/HID_IAP/Source/system_gd32vf103.c + 1 + PARENT-2-PROJECT_LOC/Source/system_gd32vf103.c + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Eclipse/in_application_program/.settings/language.settings.xml b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Eclipse/in_application_program/.settings/language.settings.xml new file mode 100644 index 0000000..f4c6cd1 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Eclipse/in_application_program/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Include/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Include/gd32vf103_it.h new file mode 100644 index 0000000..cc50acf --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Include/gd32vf103_it.h @@ -0,0 +1,54 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "usbd_core.h" + +/* function declarations */ +/* this function handles USB wakeup interrupt handler */ +void USBFS_WKUP_IRQHandler(void); +/* this function handles USBFS IRQ Handler */ +void USBFS_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Include/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Include/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Include/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Include/iap_core.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Include/iap_core.h new file mode 100644 index 0000000..c936c24 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Include/iap_core.h @@ -0,0 +1,115 @@ +/*! + \file iap_core.h + \brief the header file of IAP driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef IAP_CORE_H +#define IAP_CORE_H + +#include "usbd_enum.h" +#include "usb_ch9_std.h" +#include "usbd_transc.h" + +#define IAP_CONFIG_DESC_SIZE 9 +#define USB_SERIAL_STRING_SIZE 0x06 + +#define DEVICE_ID (0x40022100) + +#define IAP_REPORT_DESC_SIZE 35 +#define IAP_CONFIG_SET_DESC_SIZE 41 + +#define HID_DESCTYPE 0x21 +#define HID_REPORT_DESCTYPE 0x22 + +#define GET_REPORT 0x01 +#define GET_IDLE 0x02 +#define GET_PROTOCOL 0x03 +#define SET_REPORT 0x09 +#define SET_IDLE 0x0A +#define SET_PROTOCOL 0x0B +#define NO_CMD 0xFF + +/* special commands with download request */ +#define IAP_OPTION_BYTE1 0x01 +#define IAP_ERASE 0x02 +#define IAP_DNLOAD 0x03 +#define IAP_LEAVE 0x04 +#define IAP_GETBIN_ADDRESS 0x05 +#define IAP_OPTION_BYTE2 0x06 + + +typedef void (*pAppFunction) (void); + +#pragma pack(1) + +typedef struct +{ + usb_desc_header header; /*!< regular descriptor header containing the descriptor's type and length */ + + uint16_t bcdHID; /*!< BCD encoded version that the HID descriptor and device complies to */ + uint8_t bCountryCode; /*!< country code of the localized device, or zero if universal */ + uint8_t bNumDescriptors; /*!< total number of HID report descriptors for the interface */ + uint8_t bDescriptorType; /*!< type of HID report */ + uint16_t wDescriptorLength; /*!< length of the associated HID report descriptor, in bytes */ +} usb_hid_descriptor_hid_struct; + +#pragma pack() + +typedef struct +{ + usb_desc_config Config; + usb_desc_itf HID_Interface; + usb_hid_descriptor_hid_struct HID_VendorHID; + usb_desc_ep HID_ReportINEndpoint; + usb_desc_ep HID_ReportOUTEndpoint; +} usb_descriptor_configuration_set_struct; + +extern void* const usbd_strings[USB_STRING_COUNT]; +extern const usb_desc_dev device_descripter; +extern const usb_descriptor_configuration_set_struct configuration_descriptor; + +extern usb_class_core usbd_hid_cb; + +/* function declarations */ +/* initialize the HID device */ +uint8_t iap_init (usb_dev *pudev, uint8_t config_index); +/* de-initialize the HID device */ +uint8_t iap_deinit (usb_dev *pudev, uint8_t config_index); +/* handle the HID class-specific requests */ +uint8_t iap_req_handler (usb_dev *pudev, usb_req *req); +/* handle data stage */ +uint8_t iap_data_handler (usb_dev *pudev, uint8_t ep_id); + +/* send iap report */ +uint8_t iap_report_send (usb_dev *pudev, uint8_t *report, uint16_t Len); + +#endif /* IAP_CORE_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Include/usb_conf.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Include/usb_conf.h new file mode 100644 index 0000000..b36f0be --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Include/usb_conf.h @@ -0,0 +1,121 @@ +/*! + \file usb_conf.h + \brief USBFS driver basic configuration + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_CONF_H +#define __USB_CONF_H + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" + +#include + +#ifdef USE_USB_FS + #define USB_FS_CORE +#endif + +#ifdef USE_USB_HS + #define USB_HS_CORE +#endif + +#ifdef USB_FS_CORE + #define RX_FIFO_FS_SIZE 128 + #define TX0_FIFO_FS_SIZE 64 + #define TX1_FIFO_FS_SIZE 128 + #define TX2_FIFO_FS_SIZE 0 + #define TX3_FIFO_FS_SIZE 0 +#endif /* USB_FS_CORE */ + +#ifdef USB_HS_CORE + #define RX_FIFO_HS_SIZE 512 + #define TX0_FIFO_HS_SIZE 128 + #define TX1_FIFO_HS_SIZE 372 + #define TX2_FIFO_HS_SIZE 0 + #define TX3_FIFO_HS_SIZE 0 + #define TX4_FIFO_HS_SIZE 0 + #define TX5_FIFO_HS_SIZE 0 + + #ifdef USE_ULPI_PHY + #define USB_OTG_ULPI_PHY_ENABLED + #endif + + #ifdef USE_EMBEDDED_PHY + #define USB_OTG_EMBEDDED_PHY_ENABLED + #endif + + #define USB_OTG_HS_INTERNAL_DMA_ENABLED + #define USB_OTG_HS_DEDICATED_EP1_ENABLED +#endif /* USB_HS_CORE */ + +#define USB_SOF_OUTPUT 1 +#define USB_LOW_POWER 1 + +//#define VBUS_SENSING_ENABLED + +//#define USE_HOST_MODE +#define USE_DEVICE_MODE +//#define USE_OTG_MODE + +#ifndef USB_FS_CORE + #ifndef USB_HS_CORE + #error "USB_HS_CORE or USB_FS_CORE should be defined" + #endif +#endif + +#ifndef USE_DEVICE_MODE + #ifndef USE_HOST_MODE + #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" + #endif +#endif + +#ifndef USE_USB_HS + #ifndef USE_USB_FS + #error "USE_USB_HS or USE_USB_FS should be defined" + #endif +#endif + +/****************** C Compilers dependant keywords ****************************/ +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined (__GNUC__) /* GNU Compiler */ + #define __ALIGN_END __attribute__ ((aligned(4))) + #define __ALIGN_BEGIN + #endif /* __GNUC__ */ +#else + #define __ALIGN_BEGIN + #define __ALIGN_END +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + + +#endif /* __USB_CONF_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Include/usbd_conf.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Include/usbd_conf.h new file mode 100644 index 0000000..86c418f --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Include/usbd_conf.h @@ -0,0 +1,68 @@ +/*! + \file usbd_conf.h + \brief the header file of USBFS device-mode configuration + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBFS_CONF_H +#define USBFS_CONF_H + +#include "usb_conf.h" + +#define USBD_CFG_MAX_NUM 1 +#define USBD_ITF_MAX_NUM 1 +#define USB_STR_DESC_MAX_SIZE 64 + +#define USB_STRING_COUNT 4 + +#define IAP_IN_EP EP1_IN +#define IAP_OUT_EP EP1_OUT + +#define IAP_IN_PACKET 24 +#define IAP_OUT_PACKET 64 + +#define TRANSFER_SIZE 62 + +#define PAGE_SIZE 1024 /* MCU page size */ + +/* maximum number of supported memory media (Flash, RAM or EEPROM and so on) */ +#define MAX_USED_MEMORY_MEDIA 1 + +/* memory address from where user application will be loaded, which represents + the DFU code protected against write and erase operations.*/ +#define APP_LOADED_ADDR 0x08010000 + +/* make sure the corresponding memory where the DFU code should not be loaded + cannot be erased or overwritten by DFU application. */ +#define IS_PROTECTED_AREA(addr) (uint8_t)(((addr >= 0x08000000) && \ + (addr < (APP_LOADED_ADDR)))? 1 : 0) + +#endif /* USBD_CONF_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Source/app.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Source/app.c new file mode 100644 index 0000000..12f49a1 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Source/app.c @@ -0,0 +1,119 @@ +/*! + \file app.c + \brief USB main routine for HID IAP + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "iap_core.h" +#include +#include +#include +#include "riscv_encoding.h" + + +usb_core_driver USB_OTG_dev = +{ + .dev = { + .desc = { + .dev_desc = (uint8_t *)&device_descripter, + .config_desc = (uint8_t *)&configuration_descriptor, + .strings = usbd_strings, + } + } +}; + +pAppFunction application; + +extern uint8_t usbd_serial_string[]; +void serial_string_create(void); + + +/*! + \brief main routine will construct a USB keyboard + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + eclic_global_interrupt_enable(); + + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL2_PRIO2); + + /* configure Tamper key to run firmware */ + gd_eval_key_init(KEY_A, KEY_MODE_GPIO); + + usb_timer_init(); + + /* tamper key must be pressed on GD32350R-EVAL when power on */ + if (0 == gd_eval_key_state_get(KEY_A)) { + /* test if user code is programmed starting from address 0x08010000 */ + if (0x0001AAB1 == (*(__IO uint32_t*)APP_LOADED_ADDR)) { + clear_csr(mstatus, MSTATUS_MIE); + asm volatile ("jr %0 " :: "r"(APP_LOADED_ADDR)); + } + } + + /* configure USB clock */ + usb_rcu_config(); + + serial_string_create(); + + usb_intr_config(); + + usbd_init (&USB_OTG_dev, USB_CORE_ENUM_FS, &usbd_hid_cb); + + /* check if USB device is enumerated successfully */ + while (USB_OTG_dev.dev.cur_status != USBD_CONFIGURED) { + } + + while (1) { + } +} + +/*! + \brief create the serial number string descriptor + \param[in] none + \param[out] none + \retval none +*/ +void serial_string_create (void) +{ + uint32_t device_serial = *(uint32_t*)DEVICE_ID; + + if (0 != device_serial) { + usbd_serial_string[2] = (uint8_t)device_serial; + usbd_serial_string[3] = (uint8_t)(device_serial >> 8); + usbd_serial_string[4] = (uint8_t)(device_serial >> 16); + usbd_serial_string[5] = (uint8_t)(device_serial >> 24); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Source/gd32vf103_hw.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Source/gd32vf103_hw.c new file mode 100644 index 0000000..2378125 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Source/gd32vf103_hw.c @@ -0,0 +1,205 @@ +/*! + \file gd32vf103_hw.c + \brief USB hardware configuration for GD32VF103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include +#include +#include + + +#define TIM_MSEC_DELAY 0x01 +#define TIM_USEC_DELAY 0x02 + +__IO uint32_t delay_time = 0; +__IO uint32_t timer_prescaler; +__IO uint32_t usbfs_prescaler = 0; + +static void hw_time_set (uint8_t unit); +static void hw_delay (uint32_t ntime, uint8_t unit); + + +/*! + \brief configure USB clock + \param[in] none + \param[out] none + \retval none +*/ +void usb_rcu_config(void) +{ + uint32_t system_clock = rcu_clock_freq_get(CK_SYS); + + if (system_clock == 48000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1; + timer_prescaler = 3; + } else if (system_clock == 72000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1_5; + timer_prescaler = 5; + } else if (system_clock == 96000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV2; + timer_prescaler = 7; + } else { + /* reserved */ + } + + rcu_usb_clock_config(usbfs_prescaler); + rcu_periph_clock_enable(RCU_USBFS); +} + +/*! + \brief configure USB interrupt + \param[in] none + \param[out] none + \retval none +*/ +void usb_intr_config(void) +{ + eclic_irq_enable((uint8_t)USBFS_IRQn, 1, 0); + + /* enable the power module clock */ + rcu_periph_clock_enable(RCU_PMU); + + /* USB wakeup EXTI line configuration */ + exti_interrupt_flag_clear(EXTI_18); + exti_init(EXTI_18, EXTI_INTERRUPT, EXTI_TRIG_RISING); + exti_interrupt_enable(EXTI_18); + + eclic_irq_enable((uint8_t)USBFS_WKUP_IRQn, 3, 0); +} + +/*! + \brief initializes delay unit using Timer2 + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_init (void) +{ + rcu_periph_clock_enable(RCU_TIMER2); + eclic_irq_enable(TIMER2_IRQn, 2, 0); +} + +/*! + \brief delay in micro seconds + \param[in] usec: value of delay required in micro seconds + \param[out] none + \retval none +*/ +void usb_udelay (const uint32_t usec) +{ + hw_delay(usec, TIM_USEC_DELAY); +} + +/*! + \brief delay in milli seconds + \param[in] msec: value of delay required in milli seconds + \param[out] none + \retval none +*/ +void usb_mdelay (const uint32_t msec) +{ + hw_delay(msec, TIM_MSEC_DELAY); +} + +/*! + \brief time base IRQ + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_irq (void) +{ + if (RESET != timer_flag_get(TIMER2, TIMER_FLAG_UP)){ + timer_flag_clear(TIMER2, TIMER_FLAG_UP); + + if (delay_time > 0x00U){ + delay_time--; + } else { + timer_disable(TIMER2); + } + } +} + +/*! + \brief delay routine based on TIM0 + \param[in] nTime: delay Time + \param[in] unit: delay Time unit = mili sec / micro sec + \param[out] none + \retval none +*/ +static void hw_delay(uint32_t ntime, uint8_t unit) +{ + delay_time = ntime; + + hw_time_set(unit); + + while (0U != delay_time) { + } + + timer_disable(TIMER2); +} + +/*! + \brief configures TIM0 for delay routine based on TIM0 + \param[in] unit: msec /usec + \param[out] none + \retval none +*/ +static void hw_time_set(uint8_t unit) +{ + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER2); + timer_deinit(TIMER2); + + if(TIM_USEC_DELAY == unit) { + timer_initpara.period = 11; + } else if(TIM_MSEC_DELAY == unit) { + timer_initpara.period = 11999; + } + + timer_initpara.prescaler = timer_prescaler; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER2, &timer_initpara); + + timer_update_event_enable(TIMER2); + timer_interrupt_enable(TIMER2,TIMER_INT_UP); + timer_flag_clear(TIMER2, TIMER_FLAG_UP); + timer_update_source_config(TIMER2, TIMER_UPDATE_SRC_GLOBAL); + + /* TIMER2 counter enable */ + timer_enable(TIMER2); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Source/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Source/gd32vf103_it.c new file mode 100644 index 0000000..8cae80e --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Source/gd32vf103_it.c @@ -0,0 +1,96 @@ +/*! + \file gd32vf103_it.c + \brief main interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usbd_int.h" +#include "drv_usb_hw.h" +#include "gd32vf103_it.h" + +extern usb_core_driver USB_OTG_dev; +extern uint32_t usbfs_prescaler; + +extern void usb_timer_irq(void); + +/*! + \brief this function handles USBD interrupt + \param[in] none + \param[out] none + \retval none +*/ +void USBFS_IRQHandler (void) +{ + usbd_isr (&USB_OTG_dev); +} + +/*! + \brief this function handles EXTI0_IRQ Handler + \param[in] none + \param[out] none + \retval none +*/ +void EXTI0_IRQHandler(void) +{ + +} + +/*! + \brief this function handles USBD wakeup interrupt request. + \param[in] none + \param[out] none + \retval none +*/ +void USBFS_WKUP_IRQHandler(void) +{ + if (USB_OTG_dev.bp.low_power) { + SystemInit(); + + rcu_usb_clock_config(usbfs_prescaler); + + rcu_periph_clock_enable(RCU_USBFS); + + usb_clock_active(&USB_OTG_dev); + } + + exti_interrupt_flag_clear(EXTI_18); +} + +/*! + \brief this function handles Timer0 updata interrupt request. + \param[in] none + \param[out] none + \retval none +*/ +void TIMER2_IRQHandler(void) +{ + usb_timer_irq(); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Source/iap_core.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Source/iap_core.c new file mode 100644 index 0000000..88cdc62 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Source/iap_core.c @@ -0,0 +1,594 @@ +/*! + \file iap_core.c + \brief IAP driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "iap_core.h" + +#define USBD_VID 0x28E9 +#define USBD_PID 0x028B + +uint8_t report_buf[IAP_OUT_PACKET + 1]; +uint8_t option_byte[IAP_IN_PACKET] = {0}; + +/* state machine variables */ +uint8_t device_status[IAP_IN_PACKET] = {0}; +uint8_t bin_address[IAP_IN_PACKET] = {0}; + +uint8_t usbd_customhid_report_id = 0; +uint8_t flag = 0; + +static uint32_t usbd_customhid_altset = 0; +static uint32_t usbd_customhid_protocol = 0; +static uint32_t usbd_customhid_idlestate = 0; + +static uint16_t transfer_times = 0; +static uint16_t page_count = 0; +static uint32_t file_length = 0; +static uint32_t base_address = APP_LOADED_ADDR; + + +/* Note:it should use the C99 standard when compiling the below codes */ +/* USB standard device descriptor */ +__ALIGN_BEGIN const usb_desc_dev device_descripter __ALIGN_END = +{ + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, + .bcdUSB = 0x0200, + .bDeviceClass = 0x00, + .bDeviceSubClass = 0x00, + .bDeviceProtocol = 0x00, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM +}; + +__ALIGN_BEGIN const usb_descriptor_configuration_set_struct configuration_descriptor __ALIGN_END = +{ + .Config = + { + .header = + { + .bLength = USB_CFG_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = IAP_CONFIG_SET_DESC_SIZE, + .bNumInterfaces = 0x01, + .bConfigurationValue = 0x01, + .iConfiguration = 0x00, + .bmAttributes = 0x80, + .bMaxPower = 0x32 + }, + + .HID_Interface = + { + .header = + { + .bLength = USB_ITF_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x02, + .bInterfaceClass = 0x03, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, + .iInterface = 0x00 + }, + + .HID_VendorHID = + { + .header = + { + .bLength = sizeof(usb_hid_descriptor_hid_struct), + .bDescriptorType = HID_DESCTYPE + }, + .bcdHID = 0x0111, + .bCountryCode = 0x00, + .bNumDescriptors = 0x01, + .bDescriptorType = HID_REPORT_DESCTYPE, + .wDescriptorLength = IAP_REPORT_DESC_SIZE, + }, + + .HID_ReportINEndpoint = + { + .header = + { + .bLength = USB_EP_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = IAP_IN_EP, + .bmAttributes = 0x03, + .wMaxPacketSize = IAP_IN_PACKET, + .bInterval = 0x20 + }, + + .HID_ReportOUTEndpoint = + { + .header = + { + .bLength = USB_EP_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = IAP_OUT_EP, + .bmAttributes = 0x03, + .wMaxPacketSize = IAP_OUT_PACKET, + .bInterval = 0x20 + } +}; + +/* USB language ID Descriptor */ +__ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = +{ + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + .wLANGID = ENG_LANGID +}; + +/* USB serial string */ +__ALIGN_BEGIN uint8_t usbd_serial_string[USB_SERIAL_STRING_SIZE] __ALIGN_END = +{ + USB_SERIAL_STRING_SIZE, /* bLength */ + USB_DESCTYPE_STR, /* bDescriptorType */ +}; + +__ALIGN_BEGIN void* const usbd_strings[] __ALIGN_END = +{ + [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, + [STR_IDX_MFC] = USBD_STRING_DESC("GigaDevice"), + [STR_IDX_PRODUCT] = USBD_STRING_DESC("GD32 USB IAP in FS Mode"), + [STR_IDX_SERIAL] = usbd_serial_string +}; + +/* USB custom HID device report descriptor */ +__ALIGN_BEGIN const uint8_t iap_report_descriptor[IAP_REPORT_DESC_SIZE] __ALIGN_END = +{ + 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */ + 0x09, 0x00, /* USAGE (Custom Device) */ + 0xa1, 0x01, /* COLLECTION (Application) */ + + /* IAP command and data */ + 0x85, 0x01, /* REPORT_ID (0x01) */ + 0x09, 0x01, /* USAGE (IAP command) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0xff, /* LOGICAL_MAXIMUM (255) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, 0x3f, /* REPORT_COUNT(63) */ + 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ + + /* device status and option byte */ + 0x85, 0x02, /* REPORT_ID (0x02) */ + 0x09, 0x02, /* USAGE (Status and option byte) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0xff, /* LOGICAL_MAXIMUM (255) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, 0x17, /* REPORT_COUNT (23) */ + 0x81, 0x82, /* INPUT (Data,Var,Abs,Vol) */ + + 0xc0 /* END_COLLECTION */ +}; + +/* IAP requests management functions */ +static void iap_req_erase (usb_dev *pudev); +static void iap_req_dnload (usb_dev *pudev); +static void iap_req_optionbyte(usb_dev *pudev, uint8_t option_ID); +static void iap_req_leave (usb_dev *pudev); +static void iap_address_send (usb_dev *pudev); + +static void iap_data_write (uint8_t *data, uint32_t addr, uint32_t len); + +/*! + \brief initialize the HID device + \param[in] pudev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +uint8_t iap_init (usb_dev *pudev, uint8_t config_index) +{ + /* initialize Tx endpoint */ + usbd_ep_setup(pudev, &(configuration_descriptor.HID_ReportINEndpoint)); + + /* initialize Rx endpoint */ + usbd_ep_setup(pudev, &(configuration_descriptor.HID_ReportOUTEndpoint)); + + /* unlock the internal flash */ + fmc_unlock(); + + /* prepare receive Data */ + usbd_ep_recev(pudev, IAP_OUT_EP, report_buf, IAP_OUT_PACKET); + + return USBD_OK; +} + +/*! + \brief de-initialize the HID device + \param[in] pudev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +uint8_t iap_deinit (usb_dev *pudev, uint8_t config_index) +{ + /* deinitialize HID endpoints */ + usbd_ep_clear (pudev, IAP_IN_EP); + usbd_ep_clear (pudev, IAP_OUT_EP); + + /* lock the internal flash */ + fmc_lock(); + + return USBD_OK; +} + +/*! + \brief handle the HID class-specific requests + \param[in] pudev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +uint8_t iap_req_handler (usb_dev *pudev, usb_req *req) +{ + uint16_t len = 0; + uint8_t *pbuf = NULL; + uint8_t USBD_CUSTOMHID_Report_LENGTH = 0; + + switch (req->bmRequestType & USB_REQTYPE_MASK) { + case USB_REQTYPE_CLASS: + switch (req->bRequest) { + case GET_REPORT: + /* no use for this driver */ + break; + case GET_IDLE: + pudev->dev.transc_in[0].xfer_buf = (uint8_t *)&usbd_customhid_idlestate; + pudev->dev.transc_in[0].remain_len = 1; + break; + case GET_PROTOCOL: + pudev->dev.transc_in[0].xfer_buf = (uint8_t *)&usbd_customhid_protocol; + pudev->dev.transc_in[0].remain_len = 1; + break; + case SET_REPORT: + flag = 1; + usbd_customhid_report_id = (uint8_t)(req->wValue); + USBD_CUSTOMHID_Report_LENGTH = (uint8_t)(req->wLength); + pudev->dev.transc_out[0].xfer_buf = report_buf; + pudev->dev.transc_out[0].remain_len = USBD_CUSTOMHID_Report_LENGTH; + break; + case SET_IDLE: + usbd_customhid_idlestate = (uint8_t)(req->wValue >> 8); + break; + case SET_PROTOCOL: + usbd_customhid_protocol = (uint8_t)(req->wValue); + break; + default: + usbd_enum_error (pudev, req); + return USBD_FAIL; + } + break; + case USB_REQTYPE_STRD: + /* standard device request */ + switch(req->bRequest) { + case USB_GET_DESCRIPTOR: + switch(req->wValue >> 8) { + case HID_REPORT_DESCTYPE: + len = USB_MIN(IAP_REPORT_DESC_SIZE, req->wLength); + pbuf = (uint8_t *)iap_report_descriptor; + break; + case HID_DESCTYPE: + len = USB_MIN(IAP_CONFIG_DESC_SIZE, req->wLength); + pbuf = (uint8_t *)(&(configuration_descriptor.HID_VendorHID)); + break; + default: + break; + } + pudev->dev.transc_in[0].xfer_buf = pbuf; + pudev->dev.transc_in[0].remain_len = len; + break; + case USB_GET_INTERFACE: + pudev->dev.transc_in[0].xfer_buf = (uint8_t *)&usbd_customhid_altset; + pudev->dev.transc_in[0].remain_len = 1; + break; + case USB_SET_INTERFACE: + usbd_customhid_altset = (uint8_t)(req->wValue); + break; + default: + break; + } + break; + } + + return USBD_OK; +} + +/*! + \brief handle data stage + \param[in] pudev: pointer to USB device instance + \param[in] rx_tx: data transfer direction: + \arg USBD_TX + \arg USBD_RX + \param[in] ep_id: endpoint identifier + \param[out] none + \retval USB device operation status +*/ +uint8_t iap_data_in_handler (usb_dev *pudev, uint8_t ep_id) +{ + if((IAP_IN_EP & 0x7F) == ep_id) { + return USBD_OK; + } + return USBD_FAIL; +} + +uint8_t iap_data_out_handler (usb_dev *pudev, uint8_t ep_id) +{ + if (IAP_OUT_EP == ep_id) { + switch (report_buf[0]) { + case 0x01: + switch(report_buf[1]) { + case IAP_DNLOAD: + iap_req_dnload(pudev); + break; + case IAP_ERASE: + iap_req_erase(pudev); + break; + case IAP_OPTION_BYTE1: + iap_req_optionbyte(pudev, 0x01); + break; + case IAP_LEAVE: + iap_req_leave(pudev); + break; + case IAP_GETBIN_ADDRESS: + iap_address_send(pudev); + break; + case IAP_OPTION_BYTE2: + iap_req_optionbyte(pudev, 0x02); + break; + default: + usbd_enum_error(pudev, NULL); + return USBD_FAIL; + } + break; + default: + break; + } + + usbd_ep_recev(pudev, IAP_OUT_EP, report_buf, IAP_OUT_PACKET); + + return USBD_OK; + } + + return USBD_FAIL; +} + +/*! + \brief send iap report + \param[in] pudev: pointer to USB device instance + \param[in] report: pointer to HID report + \param[in] len: data length + \param[out] none + \retval USB device operation status +*/ +uint8_t iap_report_send (usb_dev *pudev, uint8_t *report, uint16_t len) +{ + usbd_ep_send (pudev, IAP_IN_EP, report, len); + + return USBD_OK; +} + +/*! + \brief handle the IAP_DNLOAD request + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void iap_req_dnload(usb_dev *pudev) +{ + if (0 != transfer_times) { + if (1 == transfer_times) { + iap_data_write(&report_buf[2], base_address, file_length % TRANSFER_SIZE); + + device_status[0] = 0x02; + device_status[1] = 0x02; + iap_report_send (pudev, device_status, IAP_IN_PACKET); + } else { + iap_data_write(&report_buf[2], base_address, TRANSFER_SIZE); + + base_address += TRANSFER_SIZE; + } + + transfer_times --; + } +} + +/*! + \brief handle the IAP_ERASE request + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void iap_req_erase(usb_dev *pudev) +{ + uint32_t i = 0, addr = 0; + + /* get base address to erase */ + base_address = report_buf[2]; + base_address |= report_buf[3] << 8; + base_address |= report_buf[4] << 16; + base_address |= report_buf[5] << 24; + + page_count = report_buf[6]; + + /* get file length */ + file_length = report_buf[7]; + file_length |= report_buf[8] << 8; + file_length |= report_buf[9] << 16; + file_length |= report_buf[10] << 24; + + transfer_times = file_length / TRANSFER_SIZE + 1; + + /* check if the address is in protected area */ + if (IS_PROTECTED_AREA(base_address)) { + return; + } + + addr = base_address; + + /* unlock the flash program erase controller */ + fmc_unlock(); + + for (i = 0; i < page_count; i ++) { + /* call the standard flash erase-page function */ + fmc_page_erase(addr); + + addr += PAGE_SIZE; + } + + fmc_lock(); + + device_status[0] = 0x02; + device_status[1] = 0x01; + + usbd_ep_send(pudev, IAP_IN_EP, device_status, IAP_IN_PACKET); +} + +/*! + \brief handle the IAP_OPTION_BYTE request + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void iap_req_optionbyte(usb_dev *pudev, uint8_t option_ID) +{ + uint8_t i = 0; + uint32_t address = 0; + + option_byte[0] = 0x02; + + if (option_ID == 0x01) { + address = 0x1FFFF800; + } else { + return; + } + + for (i = 1; i < 17; i++) { + option_byte[i] = *(uint8_t *)address; + address++; + } + + iap_report_send (pudev, option_byte, IAP_IN_PACKET); +} + +/*! + \brief handle the IAP_LEAVE request + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void iap_req_leave(usb_dev *pudev) +{ + /* lock the internal flash */ + fmc_lock(); + + /* generate system reset to allow jumping to the user code */ + eclic_system_reset(); +} + +/*! + \brief handle the IAP_SEND_ADDRESS request + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void iap_address_send(usb_dev *pudev) +{ + bin_address[0] = 0x02; + + bin_address[1] = (uint8_t)(APP_LOADED_ADDR); + bin_address[2] = (uint8_t)(APP_LOADED_ADDR >> 8); + bin_address[3] = (uint8_t)(APP_LOADED_ADDR >> 16); + bin_address[4] = (uint8_t)(APP_LOADED_ADDR >> 24); + + iap_report_send (pudev, bin_address, IAP_IN_PACKET); +} + +/*! + \brief write data to sectors of memory + \param[in] data: data to be written + \param[in] addr: sector address/code + \param[in] len: length of data to be written (in bytes) + \param[out] none + \retval MAL_OK if all operations are OK, MAL_FAIL else +*/ +static void iap_data_write (uint8_t *data, uint32_t addr, uint32_t len) +{ + uint32_t idx = 0; + + /* check if the address is in protected area */ + if (IS_PROTECTED_AREA(addr)) { + return; + } + + /* unlock the flash program erase controller */ + fmc_unlock(); + + /* data received are word multiple */ + for (idx = 0; idx < len; idx += 2) { + if (FMC_READY == fmc_halfword_program(addr, *(uint16_t *)(data + idx))) { + addr += 2; + } else { + while(1); + } + } + + fmc_lock(); +} + +usb_class_core usbd_hid_cb = { + .command = NO_CMD, + .alter_set = 0, + + .init = iap_init, + .deinit = iap_deinit, + .req_proc = iap_req_handler, + .data_in = iap_data_in_handler, + .data_out = iap_data_out_handler +}; diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Source/system_gd32vf103.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Source/system_gd32vf103.c new file mode 100644 index 0000000..05e5205 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/Source/system_gd32vf103.c @@ -0,0 +1,998 @@ +/*! + \file system_gd32vf103.h + \brief RISC-V Device Peripheral Access Layer Source File for + GD32VF103 Device Series + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32vf103.h" + +/* system frequency define */ +#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ + +/* select a system clock by uncommenting the following line */ +/* use IRC8M */ +//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000) + +/********************************************************************/ +//#define __SYSTEM_CLOCK_HXTAL (HXTAL_VALUE) +//#define __SYSTEM_CLOCK_24M_PLL_HXTAL (uint32_t)(24000000) +/********************************************************************/ + +//#define __SYSTEM_CLOCK_36M_PLL_HXTAL (uint32_t)(36000000) +//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_56M_PLL_HXTAL (uint32_t)(56000000) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000) +//#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) + +#define SEL_IRC8M 0x00U +#define SEL_HXTAL 0x01U +#define SEL_PLL 0x02U + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_48M_PLL_IRC8M +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M; +static void system_clock_48m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M; +static void system_clock_72m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M; +static void system_clock_108m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; +static void system_clock_hxtal(void); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_24M_PLL_HXTAL; +static void system_clock_24m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_36M_PLL_HXTAL; +static void system_clock_36m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL; +static void system_clock_48m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_56M_PLL_HXTAL; +static void system_clock_56m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; +static void system_clock_72m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL; +static void system_clock_96m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; +static void system_clock_108m_hxtal(void); +#else +uint32_t SystemCoreClock = IRC8M_VALUE; +#endif /* __SYSTEM_CLOCK_48M_PLL_IRC8M */ + +/* configure the system clock */ +static void system_clock_config(void); + +/*! + \brief configure the system clock + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_config(void) +{ +#ifdef __SYSTEM_CLOCK_HXTAL + system_clock_hxtal(); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) + system_clock_24m_hxtal(); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) + system_clock_36m_hxtal(); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) + system_clock_48m_hxtal(); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) + system_clock_56m_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) + system_clock_72m_hxtal(); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) + system_clock_96m_hxtal(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) + system_clock_108m_hxtal(); + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) + system_clock_48m_irc8m(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) + system_clock_72m_irc8m(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) + system_clock_108m_irc8m(); +#endif /* __SYSTEM_CLOCK_HXTAL */ +} + +/*! + \brief setup the microcontroller system, initialize the system + \param[in] none + \param[out] none + \retval none +*/ +void SystemInit(void) +{ + /* reset the RCC clock configuration to the default reset state */ + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL); + + /* reset HXTALEN, CKMEN, PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); + + /* Reset HXTALBPS bit */ + RCU_CTL &= ~(RCU_CTL_HXTALBPS); + + /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */ + + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | + RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4); + RCU_CFG1 = 0x00000000U; + + /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + /* disable all interrupts */ + RCU_INT = 0x00FF0000U; + + /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ + system_clock_config(); +} + +/*! + \brief update the SystemCoreClock with current core clock retrieved from cpu registers + \param[in] none + \param[out] none + \retval none +*/ +void SystemCoreClockUpdate(void) +{ + uint32_t scss; + uint32_t pllsel, predv0sel, pllmf, ck_src; + uint32_t predv0, predv1, pll1mf; + + scss = GET_BITS(RCU_CFG0, 2, 3); + + switch (scss) + { + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + SystemCoreClock = IRC8M_VALUE; + break; + + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + SystemCoreClock = HXTAL_VALUE; + break; + + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + + + if(RCU_PLLSRC_IRC8M_DIV2 == pllsel){ + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE / 2U; + }else{ + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + + predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); + + /* source clock use PLL1 */ + if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ + predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; + pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; + if(17U == pll1mf){ + pll1mf = 20U; + } + ck_src = (ck_src / predv1) * pll1mf; + } + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; + ck_src /= predv0; + } + + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + + if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ + pllmf |= 0x10U; + } + + if(pllmf >= 15U){ + pllmf += 1U; + }else{ + pllmf += 2U; + } + + SystemCoreClock = ck_src * pllmf; + + if(15U == pllmf){ + /* PLL source clock multiply by 6.5 */ + SystemCoreClock = ck_src * 6U + ck_src / 2U; + } + + break; + + /* IRC8M is selected as CK_SYS */ + default: + SystemCoreClock = IRC8M_VALUE; + break; + } +} + +#ifdef __SYSTEM_CLOCK_HXTAL +/*! + \brief configure the system clock to HXTAL + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + + /* wait until HXTAL is selected as system clock */ + while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +/*! + \brief configure the system clock to 24M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_24m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 6 = 24 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +/*! + \brief configure the system clock to 36M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_36m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 9 = 36 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +/*! + \brief configure the system clock to 48M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12); + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +/*! + \brief configure the system clock to 56M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_56m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 14 = 56 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL14); + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +/*! + \brief configure the system clock to 72M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18); + + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +/*! + \brief configure the system clock to 96M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_96m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + if(HXTAL_VALUE==25000000){ + + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +/*! + \brief configure the system clock to 108M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ + +static void system_clock_108m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PREDV1_DIV5 | RCU_PLL1_MUL8 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL2EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){ + } + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 | RCU_PREDV1_DIV2 | RCU_PLL1_MUL20 | RCU_PLL2_MUL20); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } + + /* enable PLL2 */ + RCU_CTL |= RCU_CTL_PLL2EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){ + } + + } + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) +/*! + \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL12; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +/*! + \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL18; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +/*! + \brief configure the system clock to 108M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL27; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#endif diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/readme.txt new file mode 100644 index 0000000..e4d66dc --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_IAP/readme.txt @@ -0,0 +1,52 @@ +/*! + \file readme.txt + \brief description of the USB HID IAP demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board,it provides a description of +how to use the USBFS peripheral. + + The GD32 device is enumerated as an USB Custom HID device for IAP, that uses the +native PC Host HID driver. + + To test the demo, you need a configuration hex image or bin image. The hex image +or the bin image should set application address at 0x8010000. + + To test the demo, you need to: + - Download the "USB IAP Client" PC applet + - Start the "USB IAP Client" PC applet and connect GD32 USB to PC (Note: maybe + the driver installion is failed in the first time, try reseating again.) + - The device should be detected and shown in the PC applet + - Select the hex image and download it to the flash + - After each device reset, the mcu will enter IAP mode + - After each device reset, hold down the key A on the GD32VF103V-EVAL board + to run the new application diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Eclipse/usbd_mouse/.cproject b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Eclipse/usbd_mouse/.cproject new file mode 100644 index 0000000..9b899dc --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Eclipse/usbd_mouse/.cproject @@ -0,0 +1,209 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Eclipse/usbd_mouse/.project b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Eclipse/usbd_mouse/.project new file mode 100644 index 0000000..ed55170 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Eclipse/usbd_mouse/.project @@ -0,0 +1,603 @@ + + + usbd_mouse + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Examples + 2 + virtual:/virtual + + + Firmware + 2 + virtual:/virtual + + + Utilities + 2 + virtual:/virtual + + + Examples/USBFS + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral + 2 + virtual:/virtual + + + Firmware/GD32VF103_usbfs_driver + 2 + virtual:/virtual + + + Firmware/RISCV + 2 + virtual:/virtual + + + Utilities/gd32vf103v_eval.c + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_eval.c + + + Utilities/gd32vf103v_eval.h + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_eval.h + + + Examples/USBFS/USB_Device + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Include + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Source + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/gd32vf103.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/gd32vf103.h + + + Firmware/GD32VF103_standard_peripheral/system_gd32vf103.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/system_gd32vf103.h + + + Firmware/GD32VF103_usbfs_driver/Include + 2 + virtual:/virtual + + + Firmware/GD32VF103_usbfs_driver/Source + 2 + virtual:/virtual + + + Firmware/RISCV/drivers + 2 + virtual:/virtual + + + Firmware/RISCV/env_Eclipse + 2 + virtual:/virtual + + + Firmware/RISCV/stubs + 2 + virtual:/virtual + + + Examples/USBFS/USB_Device/HID_Mouse + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_core.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_core.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_dev.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_dev.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_hw.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_hw.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_regs.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_regs.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usbd_int.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usbd_int.h + + + Firmware/GD32VF103_usbfs_driver/Include/usb_ch9_std.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usb_ch9_std.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbd_core.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbd_core.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbd_enum.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbd_enum.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbd_transc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbd_transc.h + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usb_core.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_core.c + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usb_dev.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_dev.c + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usbd_int.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usbd_int.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbd_core.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbd_core.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbd_enum.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbd_enum.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbd_transc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbd_transc.c + + + Firmware/RISCV/drivers/n200_eclic.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_eclic.h + + + Firmware/RISCV/drivers/n200_func.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_func.c + + + Firmware/RISCV/drivers/n200_func.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_func.h + + + Firmware/RISCV/drivers/n200_timer.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_timer.h + + + Firmware/RISCV/drivers/riscv_bits.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_bits.h + + + Firmware/RISCV/drivers/riscv_const.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_const.h + + + Firmware/RISCV/drivers/riscv_encoding.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_encoding.h + + + Firmware/RISCV/env_Eclipse/GD32VF103xB.lds + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/GD32VF103xB.lds + + + Firmware/RISCV/env_Eclipse/entry.S + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/entry.S + + + Firmware/RISCV/env_Eclipse/handlers.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/handlers.c + + + Firmware/RISCV/env_Eclipse/init.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/init.c + + + Firmware/RISCV/env_Eclipse/start.S + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/start.S + + + Firmware/RISCV/env_Eclipse/your_printf.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/your_printf.c + + + Firmware/RISCV/stubs/_exit.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/_exit.c + + + Firmware/RISCV/stubs/close.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/close.c + + + Firmware/RISCV/stubs/fstat.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/fstat.c + + + Firmware/RISCV/stubs/isatty.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/isatty.c + + + Firmware/RISCV/stubs/lseek.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/lseek.c + + + Firmware/RISCV/stubs/read.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/read.c + + + Firmware/RISCV/stubs/sbrk.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/sbrk.c + + + Firmware/RISCV/stubs/stub.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/stub.h + + + Firmware/RISCV/stubs/write.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/write.c + + + Firmware/RISCV/stubs/write_hex.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/write_hex.c + + + Examples/USBFS/USB_Device/HID_Mouse/Include + 2 + virtual:/virtual + + + Examples/USBFS/USB_Device/HID_Mouse/Source + 2 + virtual:/virtual + + + Examples/USBFS/USB_Device/HID_Mouse/Include/gd32vf103_it.h + 1 + PARENT-2-PROJECT_LOC/Include/gd32vf103_it.h + + + Examples/USBFS/USB_Device/HID_Mouse/Include/gd32vf103_libopt.h + 1 + PARENT-2-PROJECT_LOC/Include/gd32vf103_libopt.h + + + Examples/USBFS/USB_Device/HID_Mouse/Include/standard_hid_core.h + 1 + PARENT-2-PROJECT_LOC/Include/standard_hid_core.h + + + Examples/USBFS/USB_Device/HID_Mouse/Include/systick.h + 1 + PARENT-2-PROJECT_LOC/Include/systick.h + + + Examples/USBFS/USB_Device/HID_Mouse/Include/usb_conf.h + 1 + PARENT-2-PROJECT_LOC/Include/usb_conf.h + + + Examples/USBFS/USB_Device/HID_Mouse/Include/usb_hid.h + 1 + PARENT-2-PROJECT_LOC/Include/usb_hid.h + + + Examples/USBFS/USB_Device/HID_Mouse/Include/usbd_conf.h + 1 + PARENT-2-PROJECT_LOC/Include/usbd_conf.h + + + Examples/USBFS/USB_Device/HID_Mouse/Source/app.c + 1 + PARENT-2-PROJECT_LOC/Source/app.c + + + Examples/USBFS/USB_Device/HID_Mouse/Source/gd32vf103_hw.c + 1 + PARENT-2-PROJECT_LOC/Source/gd32vf103_hw.c + + + Examples/USBFS/USB_Device/HID_Mouse/Source/gd32vf103_it.c + 1 + PARENT-2-PROJECT_LOC/Source/gd32vf103_it.c + + + Examples/USBFS/USB_Device/HID_Mouse/Source/standard_hid_core.c + 1 + PARENT-2-PROJECT_LOC/Source/standard_hid_core.c + + + Examples/USBFS/USB_Device/HID_Mouse/Source/system_gd32vf103.c + 1 + PARENT-2-PROJECT_LOC/Source/system_gd32vf103.c + + + Examples/USBFS/USB_Device/HID_Mouse/Source/systick.c + 1 + PARENT-2-PROJECT_LOC/Source/systick.c + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Eclipse/usbd_mouse/.settings/language.settings.xml b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Eclipse/usbd_mouse/.settings/language.settings.xml new file mode 100644 index 0000000..5a45c33 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Eclipse/usbd_mouse/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/gd32vf103_it.h new file mode 100644 index 0000000..99bf030 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/gd32vf103_it.h @@ -0,0 +1,63 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "usbd_core.h" + +typedef enum { + JOY_NONE = 0, + JOY_SEL, + JOY_UP, + JOY_DOWN, + JOY_LEFT, + JOY_RIGHT +} joystate_enum; + +/* function declarations */ +/* this function handles USB wakeup interrupt handler */ +void USBFS_WKUP_IRQHandler(void); +/* this function handles USBFS IRQ Handler */ +void USBFS_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/gd32vf103_libopt.h new file mode 100644 index 0000000..60680cf --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/standard_hid_core.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/standard_hid_core.h new file mode 100644 index 0000000..65d5912 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/standard_hid_core.h @@ -0,0 +1,56 @@ +/*! + \file standard_hid_core.h + \brief definitions for HID core + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __STANDARD_HID_CORE_H +#define __STANDARD_HID_CORE_H + +#include "usbd_enum.h" +#include "usb_hid.h" + +#define USB_HID_CONFIG_DESC_LEN 0x22U +#define USB_HID_REPORT_DESC_LEN 0x4AU + +#define NO_CMD 0xFFU + +extern void* const usbd_hid_strings[USB_STRING_COUNT]; +extern const usb_desc_dev hid_dev_desc; +extern const usb_hid_desc_config_set hid_config_desc; +extern usb_class_core usbd_hid_cb; + +/* function declarations */ + +/* send keyboard report */ +uint8_t hid_report_send (usb_dev *pudev, uint8_t *report, uint16_t len); + +#endif /* __STANDARD_HID_CORE_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/systick.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/systick.h new file mode 100644 index 0000000..a82b0b5 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/systick.h @@ -0,0 +1,44 @@ +/*! + \file systick.h + \brief the header file of systick + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef SYS_TICK_H +#define SYS_TICK_H + +#include + +void systick_config(void); + +#endif /* SYS_TICK_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/usb_conf.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/usb_conf.h new file mode 100644 index 0000000..b36f0be --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/usb_conf.h @@ -0,0 +1,121 @@ +/*! + \file usb_conf.h + \brief USBFS driver basic configuration + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_CONF_H +#define __USB_CONF_H + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" + +#include + +#ifdef USE_USB_FS + #define USB_FS_CORE +#endif + +#ifdef USE_USB_HS + #define USB_HS_CORE +#endif + +#ifdef USB_FS_CORE + #define RX_FIFO_FS_SIZE 128 + #define TX0_FIFO_FS_SIZE 64 + #define TX1_FIFO_FS_SIZE 128 + #define TX2_FIFO_FS_SIZE 0 + #define TX3_FIFO_FS_SIZE 0 +#endif /* USB_FS_CORE */ + +#ifdef USB_HS_CORE + #define RX_FIFO_HS_SIZE 512 + #define TX0_FIFO_HS_SIZE 128 + #define TX1_FIFO_HS_SIZE 372 + #define TX2_FIFO_HS_SIZE 0 + #define TX3_FIFO_HS_SIZE 0 + #define TX4_FIFO_HS_SIZE 0 + #define TX5_FIFO_HS_SIZE 0 + + #ifdef USE_ULPI_PHY + #define USB_OTG_ULPI_PHY_ENABLED + #endif + + #ifdef USE_EMBEDDED_PHY + #define USB_OTG_EMBEDDED_PHY_ENABLED + #endif + + #define USB_OTG_HS_INTERNAL_DMA_ENABLED + #define USB_OTG_HS_DEDICATED_EP1_ENABLED +#endif /* USB_HS_CORE */ + +#define USB_SOF_OUTPUT 1 +#define USB_LOW_POWER 1 + +//#define VBUS_SENSING_ENABLED + +//#define USE_HOST_MODE +#define USE_DEVICE_MODE +//#define USE_OTG_MODE + +#ifndef USB_FS_CORE + #ifndef USB_HS_CORE + #error "USB_HS_CORE or USB_FS_CORE should be defined" + #endif +#endif + +#ifndef USE_DEVICE_MODE + #ifndef USE_HOST_MODE + #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" + #endif +#endif + +#ifndef USE_USB_HS + #ifndef USE_USB_FS + #error "USE_USB_HS or USE_USB_FS should be defined" + #endif +#endif + +/****************** C Compilers dependant keywords ****************************/ +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined (__GNUC__) /* GNU Compiler */ + #define __ALIGN_END __attribute__ ((aligned(4))) + #define __ALIGN_BEGIN + #endif /* __GNUC__ */ +#else + #define __ALIGN_BEGIN + #define __ALIGN_END +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + + +#endif /* __USB_CONF_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/usb_hid.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/usb_hid.h new file mode 100644 index 0000000..c105cf5 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/usb_hid.h @@ -0,0 +1,83 @@ +/*! + \file usb_hid.h + \brief definitions for the USB HID class + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_HID_H +#define __USB_HID_H + +#include "usb_ch9_std.h" + +#define USB_HID_CLASS 0x03U + +#define USB_DESCTYPE_HID 0x21U +#define USB_DESCTYPE_REPORT 0x22U + +/* HID subclass code */ +#define USB_HID_SUBCLASS_BOOT_ITF 0x01U + +/* HID protocol codes */ +#define USB_HID_PROTOCOL_KEYBOARD 0x01U +#define USB_HID_PROTOCOL_MOUSE 0x02U + +#define GET_REPORT 0x01U +#define GET_IDLE 0x02U +#define GET_PROTOCOL 0x03U +#define SET_REPORT 0x09U +#define SET_IDLE 0x0AU +#define SET_PROTOCOL 0x0BU + +#pragma pack(1) + +typedef struct +{ + usb_desc_header header; /*!< regular descriptor header containing the descriptor's type and length */ + + uint16_t bcdHID; /*!< BCD encoded version that the HID descriptor and device complies to */ + uint8_t bCountryCode; /*!< country code of the localized device, or zero if universal */ + uint8_t bNumDescriptors; /*!< total number of HID report descriptors for the interface */ + uint8_t bDescriptorType; /*!< type of HID report */ + uint16_t wDescriptorLength; /*!< length of the associated HID report descriptor, in bytes */ +} usb_desc_hid; + +#pragma pack() + +typedef struct +{ + usb_desc_config config; + usb_desc_itf hid_itf; + usb_desc_hid hid_vendor; + usb_desc_ep hid_epin; + usb_desc_ep hid_epout; +}usb_hid_desc_config_set; + +#endif /* __USB_HID_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/usbd_conf.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/usbd_conf.h new file mode 100644 index 0000000..b301a26 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Include/usbd_conf.h @@ -0,0 +1,54 @@ +/*! + \file usbd_conf.h + \brief the header file of USB device-mode configuration + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_CONF_H +#define USBD_CONF_H + +#include "usb_conf.h" + +#define USBD_CFG_MAX_NUM 1 +#define USBD_ITF_MAX_NUM 1 + +#define USB_STR_DESC_MAX_SIZE 64 + +#define USB_STRING_COUNT 4U + +/* endpoint count used by the HID device */ +#define HID_IN_EP EP1_IN +#define HID_OUT_EP EP1_OUT + +#define HID_IN_PACKET 8 +#define HID_OUT_PACKET 8 + +#endif /* USBD_CONF_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Source/app.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Source/app.c new file mode 100644 index 0000000..312398d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Source/app.c @@ -0,0 +1,102 @@ +/*! + \file main.c + \brief USB main routine for HID device(USB keyboard) + + \version 2019-6-5, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "standard_hid_core.h" +#include +#include +#include +#include "systick.h" + +usb_core_driver USB_OTG_dev = { + .dev = { + .desc = { + .dev_desc = (uint8_t *)&hid_dev_desc, + .config_desc = (uint8_t *)&hid_config_desc, + .strings = usbd_hid_strings, + } + } +}; + +void key_config(void); + +/** + * @brief Main routine will construct a USB virtual ComPort device + * @param None + * @retval None + */ +int main(void) +{ + eclic_global_interrupt_enable(); + + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL2_PRIO2); + + usb_rcu_config(); + + usb_timer_init(); + + /* configure key */ + key_config(); + + systick_config(); + + usb_intr_config(); + + usbd_init (&USB_OTG_dev, USB_CORE_ENUM_FS, &usbd_hid_cb); + + /* check if USB device is enumerated successfully */ + while (USBD_CONFIGURED != USB_OTG_dev.dev.cur_status) { + } + + while (1) + { + } +} + +/*! + \brief configure key + \param[in] none + \param[out] none + \retval none +*/ +void key_config(void) +{ + gd_eval_key_init(KEY_A, KEY_MODE_GPIO); + gd_eval_key_init(KEY_B, KEY_MODE_GPIO); + gd_eval_key_init(KEY_C, KEY_MODE_GPIO); + gd_eval_key_init(KEY_D, KEY_MODE_GPIO); + + gd_eval_key_init(KEY_CET, KEY_MODE_EXTI); + eclic_irq_enable(KEY_CET_EXTI_IRQn, 2, 0); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Source/gd32vf103_hw.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Source/gd32vf103_hw.c new file mode 100644 index 0000000..d312458 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Source/gd32vf103_hw.c @@ -0,0 +1,207 @@ +/*! + \file gd32vf103_hw.c + \brief USB hardware configuration for GD32VF103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "n200_func.h" +#include +#include +#include + + +#define TIM_MSEC_DELAY 0x01 +#define TIM_USEC_DELAY 0x02 + +__IO uint32_t delay_time = 0; +__IO uint32_t timer_prescaler; +__IO uint32_t usbfs_prescaler = 0; + +static void hw_time_set (uint8_t unit); +static void hw_delay (uint32_t ntime, uint8_t unit); + + +/*! + \brief configure USB clock + \param[in] none + \param[out] none + \retval none +*/ +void usb_rcu_config(void) +{ + uint32_t system_clock = rcu_clock_freq_get(CK_SYS); + + if (system_clock == 48000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1; + timer_prescaler = 3; + } else if (system_clock == 72000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1_5; + timer_prescaler = 5; + } else if (system_clock == 96000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV2; + timer_prescaler = 7; + } else { + /* reserved */ + } + + rcu_usb_clock_config(usbfs_prescaler); + rcu_periph_clock_enable(RCU_USBFS); +} + +/*! + \brief configure USB interrupt + \param[in] none + \param[out] none + \retval none +*/ +void usb_intr_config(void) +{ + eclic_irq_enable((uint8_t)USBFS_IRQn, 1, 0); + + /* enable the power module clock */ + rcu_periph_clock_enable(RCU_PMU); + + /* USB wakeup EXTI line configuration */ + exti_interrupt_flag_clear(EXTI_18); + exti_init(EXTI_18, EXTI_INTERRUPT, EXTI_TRIG_RISING); + exti_interrupt_enable(EXTI_18); + + eclic_irq_enable((uint8_t)USBFS_WKUP_IRQn, 3, 0); +} + +/*! + \brief initializes delay unit using Timer2 + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_init (void) +{ + rcu_periph_clock_enable(RCU_TIMER2); + + eclic_irq_enable(TIMER2_IRQn, 3, 0); +} + +/*! + \brief delay in micro seconds + \param[in] usec: value of delay required in micro seconds + \param[out] none + \retval none +*/ +void usb_udelay (const uint32_t usec) +{ + hw_delay(usec, TIM_USEC_DELAY); +} + +/*! + \brief delay in milli seconds + \param[in] msec: value of delay required in milli seconds + \param[out] none + \retval none +*/ +void usb_mdelay (const uint32_t msec) +{ + hw_delay(msec, TIM_MSEC_DELAY); +} + +/*! + \brief time base IRQ + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_irq (void) +{ + if (RESET != timer_flag_get(TIMER2, TIMER_FLAG_UP)){ + timer_flag_clear(TIMER2, TIMER_FLAG_UP); + + if (delay_time > 0x00U){ + delay_time--; + } else { + timer_disable(TIMER2); + } + } +} + +/*! + \brief delay routine based on TIM0 + \param[in] nTime: delay Time + \param[in] unit: delay Time unit = mili sec / micro sec + \param[out] none + \retval none +*/ +static void hw_delay(uint32_t ntime, uint8_t unit) +{ + delay_time = ntime; + + hw_time_set(unit); + + while (0U != delay_time) { + } + + timer_disable(TIMER2); +} + +/*! + \brief configures TIM0 for delay routine based on TIM0 + \param[in] unit: msec /usec + \param[out] none + \retval none +*/ +static void hw_time_set(uint8_t unit) +{ + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER2); + timer_deinit(TIMER2); + + if(TIM_USEC_DELAY == unit) { + timer_initpara.period = 11; + } else if(TIM_MSEC_DELAY == unit) { + timer_initpara.period = 11999; + } + + timer_initpara.prescaler = timer_prescaler; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER2, &timer_initpara); + + timer_update_event_enable(TIMER2); + timer_interrupt_enable(TIMER2,TIMER_INT_UP); + timer_flag_clear(TIMER2, TIMER_FLAG_UP); + timer_update_source_config(TIMER2, TIMER_UPDATE_SRC_GLOBAL); + + /* TIMER2 counter enable */ + timer_enable(TIMER2); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Source/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Source/gd32vf103_it.c new file mode 100644 index 0000000..b94ee67 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Source/gd32vf103_it.c @@ -0,0 +1,205 @@ +/*! + \file gd32vf103_it.c + \brief main interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usbd_int.h" +#include "drv_usb_hw.h" +#include "gd32vf103_it.h" +#include "standard_hid_core.h" +#include "gd32vf103v_eval.h" + +#define CURSOR_STEP 5 + +extern usb_core_driver USB_OTG_dev; +extern uint32_t usbfs_prescaler; + +void usb_timer_irq(void); +static uint8_t joystate_get(void); +static uint8_t* usbd_mice_pos_get(void); + +/*! + \brief this function handles Core timer Handler + \param[in] none + \param[out] none + \retval none +*/ +void eclic_mtip_handler(void) +{ + uint8_t* buf; + + *(uint64_t*)(TIMER_CTRL_ADDR + TIMER_MTIME) = 0; + + buf = usbd_mice_pos_get(); + + if ((buf[1] != 0) || (buf[2] != 0)) { + hid_report_send(&USB_OTG_dev, buf, 4); + } +} + +/*! + \brief this function handles USBD interrupt + \param[in] none + \param[out] none + \retval none +*/ +void USBFS_IRQHandler (void) +{ + usbd_isr (&USB_OTG_dev); +} + +/*! + \brief this function handles EXTI4_IRQ Handler + \param[in] none + \param[out] none + \retval none +*/ +void EXTI4_IRQHandler(void) +{ + if (exti_interrupt_flag_get(KEY_CET_EXTI_LINE) != RESET) { + if (USB_OTG_dev.dev.pm.dev_remote_wakeup) { + SystemInit(); + + rcu_usb_clock_config(usbfs_prescaler); + + rcu_periph_clock_enable(RCU_USBFS); + + usb_clock_active(&USB_OTG_dev); + + usb_rwkup_set(&USB_OTG_dev); + + usb_mdelay(5U); + + usb_rwkup_reset(&USB_OTG_dev); + + USB_OTG_dev.dev.cur_status = USB_OTG_dev.dev.backup_status; + + USB_OTG_dev.dev.pm.dev_remote_wakeup = 0U; + } + + /* clear the exti line pending bit */ + exti_interrupt_flag_clear(KEY_CET_EXTI_LINE); + } +} + +/*! + \brief this function handles USBD wakeup interrupt request. + \param[in] none + \param[out] none + \retval none +*/ +void USBFS_WKUP_IRQHandler(void) +{ + if (USB_OTG_dev.bp.low_power) { + SystemInit(); + + rcu_usb_clock_config(usbfs_prescaler); + + rcu_periph_clock_enable(RCU_USBFS); + + usb_clock_active(&USB_OTG_dev); + } + + exti_interrupt_flag_clear(EXTI_18); +} + +/*! + \brief this function handles Timer2 updata interrupt request. + \param[in] none + \param[out] none + \retval none +*/ +void TIMER2_IRQHandler(void) +{ + usb_timer_irq(); +} + +/*! + \brief get joystick state + \param[in] none + \param[out] none + \retval state +*/ +static uint8_t joystate_get(void) +{ + if (0 == gd_eval_key_state_get(KEY_A)) { + return JOY_UP; + } else if (0 == gd_eval_key_state_get(KEY_B)) { + return JOY_LEFT; + } else if (0 == gd_eval_key_state_get(KEY_C)) { + return JOY_DOWN; + } else if (0 == gd_eval_key_state_get(KEY_D)) { + return JOY_RIGHT; + } else { + return JOY_NONE; + } +} + +/*! + \brief get mice position + \param[in] none + \param[out] none + \retval the value of position +*/ +static uint8_t* usbd_mice_pos_get(void) +{ + int8_t x = 0, y = 0; + static uint8_t mice_buf[4] = {0,0,0,0}; + + switch (joystate_get()) { + case JOY_UP: + y = -CURSOR_STEP; + break; + + case JOY_DOWN: + y = CURSOR_STEP; + break; + + case JOY_LEFT: + x = -CURSOR_STEP; + break; + + case JOY_RIGHT: + x = CURSOR_STEP; + break; + + default: + break; + } + + mice_buf[0] = 0; + mice_buf[1] = x; + mice_buf[2] = y; + mice_buf[3] = 0; + + return mice_buf; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Source/standard_hid_core.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Source/standard_hid_core.c new file mode 100644 index 0000000..52e0816 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Source/standard_hid_core.c @@ -0,0 +1,326 @@ +/*! + \file standard_hid_core.c + \brief HID class driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "standard_hid_core.h" + +#define USBD_VID 0x28e9 +#define USBD_PID 0x0380 + +static uint32_t usbd_hid_protocol = 0; +static uint32_t usbd_hid_idlestate = 0; +__IO uint8_t prev_transfer_complete = 1; + +/* Note:it should use the C99 standard when compiling the below codes */ +/* USB standard device descriptor */ +const usb_desc_dev hid_dev_desc = +{ + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, + .bcdUSB = 0x0200U, + .bDeviceClass = 0x00U, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM +}; + +const usb_hid_desc_config_set hid_config_desc = +{ + .config = + { + .header = + { + .bLength = USB_CFG_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = USB_HID_CONFIG_DESC_LEN, + .bNumInterfaces = 0x01U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0xA0U, + .bMaxPower = 0x32U + }, + + .hid_itf = + { + .header = + { + .bLength = USB_ITF_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x01U, + .bInterfaceClass = USB_HID_CLASS, + .bInterfaceSubClass = USB_HID_SUBCLASS_BOOT_ITF, + .bInterfaceProtocol = USB_HID_PROTOCOL_MOUSE, + .iInterface = 0x00U + }, + + .hid_vendor = + { + .header = + { + .bLength = sizeof(usb_desc_hid), + .bDescriptorType = USB_DESCTYPE_HID + }, + .bcdHID = 0x0111U, + .bCountryCode = 0x00U, + .bNumDescriptors = 0x01U, + .bDescriptorType = USB_DESCTYPE_REPORT, + .wDescriptorLength = USB_HID_REPORT_DESC_LEN, + }, + + .hid_epin = + { + .header = + { + .bLength = USB_EP_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = HID_IN_EP, + .bmAttributes = USB_EP_ATTR_INT, + .wMaxPacketSize = HID_IN_PACKET, + .bInterval = 0x01U, + } +}; + +/* USB language ID Descriptor */ +const usb_desc_LANGID usbd_language_id_desc = +{ + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + .wLANGID = ENG_LANGID +}; + +void *const usbd_hid_strings[] = +{ + [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, + [STR_IDX_MFC] = USBD_STRING_DESC("GigaDevice"), + [STR_IDX_PRODUCT] = USBD_STRING_DESC("GD32 USB Mouse in FS Mode"), + [STR_IDX_SERIAL] = USBD_STRING_DESC("GD32VF103-V1.0.0-3a4b5ed") +}; + +const uint8_t hid_report_desc[USB_HID_REPORT_DESC_LEN] = +{ + 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */ + 0x09, 0x02, /* USAGE (Mouse) */ + 0xa1, 0x01, /* COLLECTION (Application) */ + 0x09, 0x01, /* USAGE (Pointer) */ + + 0xa1, 0x00, /* COLLECTION (Physical) */ + 0x05, 0x09, /* USAGE_PAGE (Button) */ + 0x19, 0x01, /* USAGE_MINIMUM (1) */ + 0x29, 0x03, /* USAGE_MAXIMUM (3) */ + + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x95, 0x03, /* REPORT_COUNT (3) */ + 0x75, 0x01, /* REPORT_SIZE (1) */ + 0x81, 0x02, /* INPUT (Data,Var,Abs) */ + + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x75, 0x05, /* REPORT_SIZE (5) */ + 0x81, 0x01, /* INPUT (Cnst,Var,Abs) */ + + 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */ + 0x09, 0x30, /* USAGE (X) */ + 0x09, 0x31, /* USAGE (Y) */ + 0x09, 0x38, /* USAGE (Wheel) */ + + 0x15, 0x81, /* LOGICAL_MINIMUM (81) */ + 0x25, 0x7F, /* LOGICAL_MAXIMUM (7F) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, 0x03, /* REPORT_COUNT (3) */ + 0x81, 0x06, /* INPUT (Data,Ary,Abs) */ + 0xc0, /* END_COLLECTION */ + + 0x09, 0x3c, /* USAGE (Motion Wakeup) */ + 0x05, 0xff, /* USAGE PAGE (vendor defined) */ + 0x09, 0x01, /* USAGE(01) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x01, /* REPORT_SIZE (1) */ + 0x95, 0x02, /* REPORT_COUNT (2) */ + 0xb1, 0x22, /* Feature (var) */ + 0x75, 0x06, /* REPORT_SIZE (6) */ + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0xb1, 0x01, /* Feature (cnst) */ + 0xc0 +}; + +/* local function prototypes ('static') */ +static uint8_t hid_init (usb_dev *udev, uint8_t config_index); +static uint8_t hid_deinit (usb_dev *udev, uint8_t config_index); +static uint8_t hid_req (usb_dev *udev, usb_req *req); +static uint8_t hid_data_in (usb_dev *udev, uint8_t ep_num); + +usb_class_core usbd_hid_cb = { + .command = NO_CMD, + .alter_set = 0, + + .init = hid_init, + .deinit = hid_deinit, + .req_proc = hid_req, + .data_in = hid_data_in +}; + + +/*! + \brief initialize the HID device + \param[in] pudev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t hid_init (usb_dev *udev, uint8_t config_index) +{ + /* Initialize the data Tx endpoint */ + usbd_ep_setup (udev, &(hid_config_desc.hid_epin)); + + return USBD_OK; +} + +/*! + \brief de-initialize the HID device + \param[in] pudev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t hid_deinit (usb_dev *pudev, uint8_t config_index) +{ + /* deinitialize HID endpoints */ + usbd_ep_clear(pudev, HID_IN_EP); + + return USBD_OK; +} + +/*! + \brief handle the HID class-specific requests + \param[in] pudev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t hid_req (usb_dev *pudev, usb_req *req) +{ + usb_transc *transc = &pudev->dev.transc_in[0]; + + switch (req->bRequest) { + case GET_REPORT: + /* no use for this driver */ + break; + + case GET_IDLE: + transc->xfer_buf = (uint8_t *)&usbd_hid_idlestate; + transc->remain_len = 1; + break; + + case GET_PROTOCOL: + transc->xfer_buf = (uint8_t *)&usbd_hid_protocol; + transc->remain_len = 1; + break; + + case SET_REPORT: + /* no use for this driver */ + break; + + case SET_IDLE: + usbd_hid_idlestate = (uint8_t)(req->wValue >> 8); + break; + + case SET_PROTOCOL: + usbd_hid_protocol = (uint8_t)(req->wValue); + break; + + case USB_GET_DESCRIPTOR: + if (USB_DESCTYPE_REPORT == (req->wValue >> 8)) { + transc->remain_len = USB_MIN(USB_HID_REPORT_DESC_LEN, req->wLength); + transc->xfer_buf = (uint8_t *)hid_report_desc; + return REQ_SUPP; + } + break; + + default: + break; + } + + return USBD_OK; +} + +/*! + \brief handle data stage + \param[in] pudev: pointer to USB device instance + \param[in] ep_num: endpoint identifier + \param[out] none + \retval USB device operation status +*/ +static uint8_t hid_data_in (usb_dev *pudev, uint8_t ep_num) +{ + prev_transfer_complete = 1; + return USBD_OK; +} + +/*! + \brief send keyboard report + \param[in] pudev: pointer to USB device instance + \param[in] report: pointer to HID report + \param[in] len: data length + \param[out] none + \retval USB device operation status +*/ +uint8_t hid_report_send (usb_dev *pudev, uint8_t *report, uint16_t len) +{ + if (pudev->dev.cur_status == USBD_CONFIGURED) { + if(1 == prev_transfer_complete){ + prev_transfer_complete = 0; + usbd_ep_send(pudev, HID_IN_EP, report, len); + } + } + + return USBD_OK; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Source/system_gd32vf103.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Source/system_gd32vf103.c new file mode 100644 index 0000000..05e5205 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Source/system_gd32vf103.c @@ -0,0 +1,998 @@ +/*! + \file system_gd32vf103.h + \brief RISC-V Device Peripheral Access Layer Source File for + GD32VF103 Device Series + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32vf103.h" + +/* system frequency define */ +#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ + +/* select a system clock by uncommenting the following line */ +/* use IRC8M */ +//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000) + +/********************************************************************/ +//#define __SYSTEM_CLOCK_HXTAL (HXTAL_VALUE) +//#define __SYSTEM_CLOCK_24M_PLL_HXTAL (uint32_t)(24000000) +/********************************************************************/ + +//#define __SYSTEM_CLOCK_36M_PLL_HXTAL (uint32_t)(36000000) +//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_56M_PLL_HXTAL (uint32_t)(56000000) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000) +//#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) + +#define SEL_IRC8M 0x00U +#define SEL_HXTAL 0x01U +#define SEL_PLL 0x02U + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_48M_PLL_IRC8M +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M; +static void system_clock_48m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M; +static void system_clock_72m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M; +static void system_clock_108m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; +static void system_clock_hxtal(void); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_24M_PLL_HXTAL; +static void system_clock_24m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_36M_PLL_HXTAL; +static void system_clock_36m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL; +static void system_clock_48m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_56M_PLL_HXTAL; +static void system_clock_56m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; +static void system_clock_72m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL; +static void system_clock_96m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; +static void system_clock_108m_hxtal(void); +#else +uint32_t SystemCoreClock = IRC8M_VALUE; +#endif /* __SYSTEM_CLOCK_48M_PLL_IRC8M */ + +/* configure the system clock */ +static void system_clock_config(void); + +/*! + \brief configure the system clock + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_config(void) +{ +#ifdef __SYSTEM_CLOCK_HXTAL + system_clock_hxtal(); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) + system_clock_24m_hxtal(); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) + system_clock_36m_hxtal(); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) + system_clock_48m_hxtal(); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) + system_clock_56m_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) + system_clock_72m_hxtal(); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) + system_clock_96m_hxtal(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) + system_clock_108m_hxtal(); + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) + system_clock_48m_irc8m(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) + system_clock_72m_irc8m(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) + system_clock_108m_irc8m(); +#endif /* __SYSTEM_CLOCK_HXTAL */ +} + +/*! + \brief setup the microcontroller system, initialize the system + \param[in] none + \param[out] none + \retval none +*/ +void SystemInit(void) +{ + /* reset the RCC clock configuration to the default reset state */ + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL); + + /* reset HXTALEN, CKMEN, PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); + + /* Reset HXTALBPS bit */ + RCU_CTL &= ~(RCU_CTL_HXTALBPS); + + /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */ + + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | + RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4); + RCU_CFG1 = 0x00000000U; + + /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + /* disable all interrupts */ + RCU_INT = 0x00FF0000U; + + /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ + system_clock_config(); +} + +/*! + \brief update the SystemCoreClock with current core clock retrieved from cpu registers + \param[in] none + \param[out] none + \retval none +*/ +void SystemCoreClockUpdate(void) +{ + uint32_t scss; + uint32_t pllsel, predv0sel, pllmf, ck_src; + uint32_t predv0, predv1, pll1mf; + + scss = GET_BITS(RCU_CFG0, 2, 3); + + switch (scss) + { + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + SystemCoreClock = IRC8M_VALUE; + break; + + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + SystemCoreClock = HXTAL_VALUE; + break; + + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + + + if(RCU_PLLSRC_IRC8M_DIV2 == pllsel){ + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE / 2U; + }else{ + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + + predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); + + /* source clock use PLL1 */ + if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ + predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; + pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; + if(17U == pll1mf){ + pll1mf = 20U; + } + ck_src = (ck_src / predv1) * pll1mf; + } + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; + ck_src /= predv0; + } + + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + + if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ + pllmf |= 0x10U; + } + + if(pllmf >= 15U){ + pllmf += 1U; + }else{ + pllmf += 2U; + } + + SystemCoreClock = ck_src * pllmf; + + if(15U == pllmf){ + /* PLL source clock multiply by 6.5 */ + SystemCoreClock = ck_src * 6U + ck_src / 2U; + } + + break; + + /* IRC8M is selected as CK_SYS */ + default: + SystemCoreClock = IRC8M_VALUE; + break; + } +} + +#ifdef __SYSTEM_CLOCK_HXTAL +/*! + \brief configure the system clock to HXTAL + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + + /* wait until HXTAL is selected as system clock */ + while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +/*! + \brief configure the system clock to 24M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_24m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 6 = 24 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +/*! + \brief configure the system clock to 36M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_36m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 9 = 36 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +/*! + \brief configure the system clock to 48M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12); + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +/*! + \brief configure the system clock to 56M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_56m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 14 = 56 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL14); + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +/*! + \brief configure the system clock to 72M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18); + + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +/*! + \brief configure the system clock to 96M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_96m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + if(HXTAL_VALUE==25000000){ + + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +/*! + \brief configure the system clock to 108M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ + +static void system_clock_108m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PREDV1_DIV5 | RCU_PLL1_MUL8 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL2EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){ + } + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 | RCU_PREDV1_DIV2 | RCU_PLL1_MUL20 | RCU_PLL2_MUL20); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } + + /* enable PLL2 */ + RCU_CTL |= RCU_CTL_PLL2EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){ + } + + } + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) +/*! + \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL12; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +/*! + \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL18; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +/*! + \brief configure the system clock to 108M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL27; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#endif diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Source/systick.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Source/systick.c new file mode 100644 index 0000000..f2a4aae --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/Source/systick.c @@ -0,0 +1,47 @@ +/*! + \file systick.c + \brief the systick configuration file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" + +void systick_config(void) +{ + eclic_global_interrupt_enable(); + *(uint64_t*)(TIMER_CTRL_ADDR + TIMER_MTIMECMP) = TIMER_FREQ / 100; + eclic_set_nlbits(ECLIC_GROUP_LEVEL2_PRIO2); + eclic_irq_enable(CLIC_INT_TMR, 3, 3); + *(uint64_t*)(TIMER_CTRL_ADDR + TIMER_MTIME) = 0; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/readme.txt new file mode 100644 index 0000000..6a3d357 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/HID_Mouse/readme.txt @@ -0,0 +1,64 @@ +/*! + \file readme.txt + \brief description of the USB HID device(USB-Keyboard) demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it provides a description of +how to use the USB_FS device application based on the Human Interface Device (HID). + + The Full Speed (FS) USB module uses a 48MHz clock, which is generated +from an integrated PLL. + + The GD32 device is enumerated as an USB mice, that uses the native PC Host +HID driver to which the GD32VF103V-EVAL-V1.0 board is connected. + + The USB mice use four key(A key, B key, C key and D key) to move the cursor. + + This demo supports remote wakeup (which is the ability of a USB device to +bring a suspended bus back to the active condition), and the CET key is +used as the remote wakeup source. + + In order to test USB remote wakeup function, you can do as follows: + - Manually switch PC to standby mode + + - Wait for PC to fully enter the standby mode + + - Push the CET key + + - If PC is ON, remote wakeup is OK, else failed + + In order to make the program work, you must do the following: + - Open your preferred toolchain + + - Rebuild all files and load your image into target memory + + - Run the application diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Eclipse/usbd_msc/.cproject b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Eclipse/usbd_msc/.cproject new file mode 100644 index 0000000..4119fc0 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Eclipse/usbd_msc/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Eclipse/usbd_msc/.project b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Eclipse/usbd_msc/.project new file mode 100644 index 0000000..5482046 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Eclipse/usbd_msc/.project @@ -0,0 +1,653 @@ + + + usbd_msc + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Examples + 2 + virtual:/virtual + + + Firmware + 2 + virtual:/virtual + + + Utilities + 2 + virtual:/virtual + + + Examples/USBFS + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral + 2 + virtual:/virtual + + + Firmware/GD32VF103_usbfs_driver + 2 + virtual:/virtual + + + Firmware/RISCV + 2 + virtual:/virtual + + + Utilities/gd32vf103v_eval.c + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_eval.c + + + Utilities/gd32vf103v_eval.h + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_eval.h + + + Examples/USBFS/USB_Device + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Include + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Source + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/gd32vf103.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/gd32vf103.h + + + Firmware/GD32VF103_standard_peripheral/system_gd32vf103.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/system_gd32vf103.h + + + Firmware/GD32VF103_usbfs_driver/Include + 2 + virtual:/virtual + + + Firmware/GD32VF103_usbfs_driver/Source + 2 + virtual:/virtual + + + Firmware/RISCV/drivers + 2 + virtual:/virtual + + + Firmware/RISCV/env_Eclipse + 2 + virtual:/virtual + + + Firmware/RISCV/stubs + 2 + virtual:/virtual + + + Examples/USBFS/USB_Device/MSC_Internal_flash + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_core.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_core.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_dev.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_dev.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_hw.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_hw.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_regs.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_regs.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usbd_int.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usbd_int.h + + + Firmware/GD32VF103_usbfs_driver/Include/usb_ch9_std.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usb_ch9_std.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbd_core.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbd_core.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbd_enum.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbd_enum.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbd_transc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbd_transc.h + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usb_core.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_core.c + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usb_dev.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_dev.c + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usbd_int.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usbd_int.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbd_core.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbd_core.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbd_enum.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbd_enum.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbd_transc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbd_transc.c + + + Firmware/RISCV/drivers/n200_eclic.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_eclic.h + + + Firmware/RISCV/drivers/n200_func.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_func.c + + + Firmware/RISCV/drivers/n200_func.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_func.h + + + Firmware/RISCV/drivers/n200_timer.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_timer.h + + + Firmware/RISCV/drivers/riscv_bits.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_bits.h + + + Firmware/RISCV/drivers/riscv_const.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_const.h + + + Firmware/RISCV/drivers/riscv_encoding.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_encoding.h + + + Firmware/RISCV/env_Eclipse/GD32VF103xB.lds + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/GD32VF103xB.lds + + + Firmware/RISCV/env_Eclipse/entry.S + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/entry.S + + + Firmware/RISCV/env_Eclipse/handlers.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/handlers.c + + + Firmware/RISCV/env_Eclipse/init.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/init.c + + + Firmware/RISCV/env_Eclipse/start.S + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/start.S + + + Firmware/RISCV/env_Eclipse/your_printf.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/your_printf.c + + + Firmware/RISCV/stubs/_exit.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/_exit.c + + + Firmware/RISCV/stubs/close.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/close.c + + + Firmware/RISCV/stubs/fstat.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/fstat.c + + + Firmware/RISCV/stubs/isatty.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/isatty.c + + + Firmware/RISCV/stubs/lseek.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/lseek.c + + + Firmware/RISCV/stubs/read.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/read.c + + + Firmware/RISCV/stubs/sbrk.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/sbrk.c + + + Firmware/RISCV/stubs/stub.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/stub.h + + + Firmware/RISCV/stubs/write.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/write.c + + + Firmware/RISCV/stubs/write_hex.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/write_hex.c + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Include + 2 + virtual:/virtual + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Source + 2 + virtual:/virtual + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Include/flash_msd.h + 1 + PARENT-2-PROJECT_LOC/Include/flash_msd.h + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Include/gd32vf103_it.h + 1 + PARENT-2-PROJECT_LOC/Include/gd32vf103_it.h + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Include/gd32vf103_libopt.h + 1 + PARENT-2-PROJECT_LOC/Include/gd32vf103_libopt.h + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Include/msc_bbb.h + 1 + PARENT-2-PROJECT_LOC/Include/msc_bbb.h + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Include/msc_scsi.h + 1 + PARENT-2-PROJECT_LOC/Include/msc_scsi.h + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usb_conf.h + 1 + PARENT-2-PROJECT_LOC/Include/usb_conf.h + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usb_msc.h + 1 + PARENT-2-PROJECT_LOC/Include/usb_msc.h + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_conf.h + 1 + PARENT-2-PROJECT_LOC/Include/usbd_conf.h + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_bbb.h + 1 + PARENT-2-PROJECT_LOC/Include/usbd_msc_bbb.h + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_core.h + 1 + PARENT-2-PROJECT_LOC/Include/usbd_msc_core.h + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_data.h + 1 + PARENT-2-PROJECT_LOC/Include/usbd_msc_data.h + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_mem.h + 1 + PARENT-2-PROJECT_LOC/Include/usbd_msc_mem.h + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_scsi.h + 1 + PARENT-2-PROJECT_LOC/Include/usbd_msc_scsi.h + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Source/app.c + 1 + PARENT-2-PROJECT_LOC/Source/app.c + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Source/flash_msd.c + 1 + PARENT-2-PROJECT_LOC/Source/flash_msd.c + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Source/gd32vf103_hw.c + 1 + PARENT-2-PROJECT_LOC/Source/gd32vf103_hw.c + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Source/gd32vf103_it.c + 1 + PARENT-2-PROJECT_LOC/Source/gd32vf103_it.c + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Source/system_gd32vf103.c + 1 + PARENT-2-PROJECT_LOC/Source/system_gd32vf103.c + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_msc_bbb.c + 1 + PARENT-2-PROJECT_LOC/Source/usbd_msc_bbb.c + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_msc_core.c + 1 + PARENT-2-PROJECT_LOC/Source/usbd_msc_core.c + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_msc_data.c + 1 + PARENT-2-PROJECT_LOC/Source/usbd_msc_data.c + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_msc_scsi.c + 1 + PARENT-2-PROJECT_LOC/Source/usbd_msc_scsi.c + + + Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_storage_msd.c + 1 + PARENT-2-PROJECT_LOC/Source/usbd_storage_msd.c + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Eclipse/usbd_msc/.settings/language.settings.xml b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Eclipse/usbd_msc/.settings/language.settings.xml new file mode 100644 index 0000000..c57dc40 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Eclipse/usbd_msc/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/flash_msd.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/flash_msd.h new file mode 100644 index 0000000..a7629ba --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/flash_msd.h @@ -0,0 +1,52 @@ +/*! + \file flash_msd.h + \brief the header file of flash_msd.c + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef FLASH_ACCESS_H +#define FLASH_ACCESS_H + +#include "stdlib.h" +#include "usb_conf.h" + +#define ISFLASH_BLOCK_SIZE 1024 +#define ISFLASH_BLOCK_NUM 64 + +/* function declarations */ +/* initialize the nand flash */ +uint32_t flash_init (void); +/* read data from multiple blocks of nand flash */ +uint32_t flash_multi_blocks_read (uint8_t* pBuf, uint32_t read_addr, uint16_t block_size, uint32_t block_num); +/* write data to multiple blocks of flash */ +uint32_t flash_multi_blocks_write (uint8_t* pBuf, uint32_t write_addr, uint16_t block_size, uint32_t block_num); + +#endif /* FLASH_ACCESS_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/gd32vf103_it.h new file mode 100644 index 0000000..4fa49f1 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/gd32vf103_it.h @@ -0,0 +1,54 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "usbd_core.h" + +/* function declarations */ +/* this function handles USB wakeup interrupt handler */ +void USBFS_WKUP_IRQHandler(void); +/* this function handles USBFS IRQ Handler */ +void USBFS_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/msc_bbb.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/msc_bbb.h new file mode 100644 index 0000000..0e2e171 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/msc_bbb.h @@ -0,0 +1,69 @@ +/*! + \file msc_bbb.h + \brief definitions for the USB MSC BBB(bulk/bulk/bulk) protocol + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __MSC_BBB_H +#define __MSC_BBB_H + +#include "usb_ch9_std.h" + +#define BBB_CBW_SIGNATURE 0x43425355U +#define BBB_CSW_SIGNATURE 0x53425355U +#define BBB_CBW_LENGTH 31U +#define BBB_CSW_LENGTH 13U + +typedef struct { + uint32_t dCBWSignature; + uint32_t dCBWTag; + uint32_t dCBWDataTransferLength; + uint8_t bmCBWFlags; + uint8_t bCBWLUN; + uint8_t bCBWCBLength; + uint8_t CBWCB[16]; +}msc_bbb_cbw; + +typedef struct { + uint32_t dCSWSignature; + uint32_t dCSWTag; + uint32_t dCSWDataResidue; + uint8_t bCSWStatus; +}msc_bbb_csw; + +/* CSW command status */ +enum msc_csw_status { + CSW_CMD_PASSED = 0, + CSW_CMD_FAILED, + CSW_PHASE_ERROR +}; + +#endif /* __MSC_BBB_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/msc_scsi.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/msc_scsi.h new file mode 100644 index 0000000..359aea6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/msc_scsi.h @@ -0,0 +1,117 @@ +/*! + \file msc_scsi.h + \brief definitions for the USB MSC SCSI commands + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __MSC_SCSI_H +#define __MSC_SCSI_H + +#include "usb_ch9_std.h" + +/* SCSI commands */ +#define SCSI_FORMAT_UNIT 0x04U +#define SCSI_INQUIRY 0x12U +#define SCSI_MODE_SELECT6 0x15U +#define SCSI_MODE_SELECT10 0x55U +#define SCSI_MODE_SENSE6 0x1AU +#define SCSI_READ_TOC_DATA 0x43U +#define SCSI_MODE_SENSE10 0x5AU +#define SCSI_ALLOW_MEDIUM_REMOVAL 0x1EU +#define SCSI_READ6 0x08U +#define SCSI_READ10 0x28U +#define SCSI_READ12 0xA8U +#define SCSI_READ16 0x88U + +#define SCSI_READ_CAPACITY10 0x25U +#define SCSI_READ_CAPACITY16 0x9EU + +#define SCSI_REQUEST_SENSE 0x03U +#define SCSI_START_STOP_UNIT 0x1BU +#define SCSI_TEST_UNIT_READY 0x00U +#define SCSI_WRITE6 0x0AU +#define SCSI_WRITE10 0x2AU +#define SCSI_WRITE12 0xAAU +#define SCSI_WRITE16 0x8AU + +#define SCSI_VERIFY10 0x2FU +#define SCSI_VERIFY12 0xAFU +#define SCSI_VERIFY16 0x8FU + +#define SCSI_SEND_DIAGNOSTIC 0x1DU +#define SCSI_READ_FORMAT_CAPACITIES 0x23U + +#define INVALID_CDB 0x20U +#define INVALID_FIELED_IN_COMMAND 0x24U +#define PARAMETER_LIST_LENGTH_ERROR 0x1AU +#define INVALID_FIELD_IN_PARAMETER_LIST 0x26U +#define ADDRESS_OUT_OF_RANGE 0x21U +#define MEDIUM_NOT_PRESENT 0x3AU +#define MEDIUM_HAVE_CHANGED 0x28U +#define WRITE_PROTECTED 0x27U +#define UNRECOVERED_READ_ERROR 0x11U +#define WRITE_FAULT 0x03U + +#define READ_FORMAT_CAPACITY_DATA_LEN 0x0CU +#define READ_CAPACITY10_DATA_LEN 0x08U +#define MODE_SENSE10_DATA_LEN 0x08U +#define MODE_SENSE6_DATA_LEN 0x04U +#define READ_TOC_CMD_LEN 0x14U +#define REQUEST_SENSE_DATA_LEN 0x12U +#define STANDARD_INQUIRY_DATA_LEN 0x24U +#define BLKVFY 0x04U + +enum sense_state { + NO_SENSE = 0U, + RECOVERED_ERROR, + NOT_READY, + MEDIUM_ERROR, + HARDWARE_ERROR, + ILLEGAL_REQUEST, + UNIT_ATTENTION, + DATA_PROTECT, + BLANK_CHECK, + VENDOR_SPECIFIC, + COPY_ABORTED, + ABORTED_COMMAND, + RESERVED, + VOLUME_OVERFLOW, + MISCOMPARE +}; + +typedef struct { + uint8_t SenseKey; + uint32_t Information; + uint8_t ASC; + uint8_t ASCQ; +} msc_scsi_sense; + +#endif /* __MSC_SCSI_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usb_conf.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usb_conf.h new file mode 100644 index 0000000..b36f0be --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usb_conf.h @@ -0,0 +1,121 @@ +/*! + \file usb_conf.h + \brief USBFS driver basic configuration + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_CONF_H +#define __USB_CONF_H + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" + +#include + +#ifdef USE_USB_FS + #define USB_FS_CORE +#endif + +#ifdef USE_USB_HS + #define USB_HS_CORE +#endif + +#ifdef USB_FS_CORE + #define RX_FIFO_FS_SIZE 128 + #define TX0_FIFO_FS_SIZE 64 + #define TX1_FIFO_FS_SIZE 128 + #define TX2_FIFO_FS_SIZE 0 + #define TX3_FIFO_FS_SIZE 0 +#endif /* USB_FS_CORE */ + +#ifdef USB_HS_CORE + #define RX_FIFO_HS_SIZE 512 + #define TX0_FIFO_HS_SIZE 128 + #define TX1_FIFO_HS_SIZE 372 + #define TX2_FIFO_HS_SIZE 0 + #define TX3_FIFO_HS_SIZE 0 + #define TX4_FIFO_HS_SIZE 0 + #define TX5_FIFO_HS_SIZE 0 + + #ifdef USE_ULPI_PHY + #define USB_OTG_ULPI_PHY_ENABLED + #endif + + #ifdef USE_EMBEDDED_PHY + #define USB_OTG_EMBEDDED_PHY_ENABLED + #endif + + #define USB_OTG_HS_INTERNAL_DMA_ENABLED + #define USB_OTG_HS_DEDICATED_EP1_ENABLED +#endif /* USB_HS_CORE */ + +#define USB_SOF_OUTPUT 1 +#define USB_LOW_POWER 1 + +//#define VBUS_SENSING_ENABLED + +//#define USE_HOST_MODE +#define USE_DEVICE_MODE +//#define USE_OTG_MODE + +#ifndef USB_FS_CORE + #ifndef USB_HS_CORE + #error "USB_HS_CORE or USB_FS_CORE should be defined" + #endif +#endif + +#ifndef USE_DEVICE_MODE + #ifndef USE_HOST_MODE + #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" + #endif +#endif + +#ifndef USE_USB_HS + #ifndef USE_USB_FS + #error "USE_USB_HS or USE_USB_FS should be defined" + #endif +#endif + +/****************** C Compilers dependant keywords ****************************/ +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined (__GNUC__) /* GNU Compiler */ + #define __ALIGN_END __attribute__ ((aligned(4))) + #define __ALIGN_BEGIN + #endif /* __GNUC__ */ +#else + #define __ALIGN_BEGIN + #define __ALIGN_END +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + + +#endif /* __USB_CONF_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usb_msc.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usb_msc.h new file mode 100644 index 0000000..485e747 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usb_msc.h @@ -0,0 +1,66 @@ +/*! + \file usb_msc.h + \brief definitions for the USB MSC class + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_MSC_H +#define __USB_MSC_H + +#include "usb_ch9_std.h" + +/* mass storage device class code */ +#define USB_CLASS_MSC 0x08U + +/* mass storage subclass code */ +#define USB_MSC_SUBCLASS_RBC 0x01U +#define USB_MSC_SUBCLASS_ATAPI 0x02U +#define USB_MSC_SUBCLASS_UFI 0x04U +#define USB_MSC_SUBCLASS_SCSI 0x06U +#define USB_MSC_SUBCLASS_LOCKABLE 0x07U +#define USB_MSC_SUBCLASS_IEEE1667 0x08U + +/* mass storage interface class control protocol codes */ +#define USB_MSC_PROTOCOL_CBI 0x00U +#define USB_MSC_PROTOCOL_CBI_ALT 0x01U +#define USB_MSC_PROTOCOL_BBB 0x50U + +/* mass storage request codes */ +#define USB_MSC_REQ_CODES_ADSC 0x00U +#define USB_MSC_REQ_CODES_GET 0xFCU +#define USB_MSC_REQ_CODES_PUT 0xFDU +#define USB_MSC_REQ_CODES_GML 0xFEU +#define USB_MSC_REQ_CODES_BOMSR 0xFFU + +#define BBB_GET_MAX_LUN 0xFEU +#define BBB_RESET 0xFFU + +#endif /* __USB_MSC_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_conf.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_conf.h new file mode 100644 index 0000000..6c05633 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_conf.h @@ -0,0 +1,64 @@ +/*! + \file usbd_conf.h + \brief USB device-mode configuration header file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBD_CONF_H +#define USBD_CONF_H + +#include "usb_conf.h" + +#define USBD_CFG_MAX_NUM 1 +#define USBD_ITF_MAX_NUM 1 +#define USB_STR_DESC_MAX_SIZE 64 + +#define USB_STRING_COUNT 4 + +/* Class Layer Parameter */ +#define MSC_IN_EP EP1_IN +#define MSC_OUT_EP EP1_OUT + +#ifdef USE_USB_HS + #ifdef USE_ULPI_PHY + #define MSC_DATA_PACKET_SIZE 512 + #else + #define MSC_DATA_PACKET_SIZE 64 + #endif +#else /*USE_USB_OTG_FS*/ + #define MSC_DATA_PACKET_SIZE 64 +#endif + +#define MSC_MEDIA_PACKET_SIZE 4096 + +#define MEM_LUN_NUM 1 + +#endif /* USBD_CONF_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_bbb.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_bbb.h new file mode 100644 index 0000000..67af299 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_bbb.h @@ -0,0 +1,86 @@ +/*! + \file usbd_msc_bbb.h + \brief the header file of the usbd_msc_bot.c file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_MSC_BBB_H +#define __USBD_MSC_BBB_H + +#include "usbd_core.h" +#include "msc_bbb.h" + +/* MSC BBB state */ +enum msc_bbb_state { + BBB_IDLE = 0, /*!< idle state */ + BBB_DATA_OUT, /*!< data OUT state */ + BBB_DATA_IN, /*!< data IN state */ + BBB_LAST_DATA_IN, /*!< last data IN state */ + BBB_SEND_DATA /*!< send immediate data state */ +}; + +/* MSC BBB status */ +enum msc_bbb_status { + BBB_STATUS_NORMAL = 0, /*!< normal status */ + BBB_STATUS_RECOVERY, /*!< recovery status*/ + BBB_STATUS_ERROR /*!< error status */ +}; + +extern uint8_t msc_bbb_data[]; + +extern uint8_t msc_bbb_state; +extern uint16_t msc_bbb_datalen; + +extern msc_bbb_cbw bbb_cbw; +extern msc_bbb_csw bbb_csw; + +/* initialize the bbb process */ +void msc_bbb_init (usb_core_driver *pudev); + +/* reset the BBB machine */ +void msc_bbb_reset (usb_core_driver *pudev); + +/* de-initialize the BBB machine */ +void msc_bbb_deinit (usb_core_driver *pudev); + +/* handle BBB data IN stage */ +void msc_bbb_data_in (usb_core_driver *pudev, uint8_t ep_num); + +/* handle BBB data OUT stage */ +void msc_bbb_data_out (usb_core_driver *pudev, uint8_t ep_num); + +/* send the CSW(command status wrapper) */ +void msc_bbb_csw_send (usb_core_driver *pudev, uint8_t ep_num); + +/* complete the clear feature request */ +void msc_bbb_clrfeature (usb_core_driver *pudev, uint8_t ep_num); + +#endif /* __USBD_MSC_BOT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_core.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_core.h new file mode 100644 index 0000000..1624305 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_core.h @@ -0,0 +1,63 @@ +/*! + \file usbd_msc_core.h + \brief the header file of USB MSC device class core functions + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_MSC_CORE_H +#define __USBD_MSC_CORE_H + +#include "usbd_conf.h" +#include "usbd_core.h" +#include "usb_msc.h" + +#define USB_MSC_CONFIG_DESC_SIZE 32U + +#define MSC_EPIN_SIZE MSC_DATA_PACKET_SIZE +#define MSC_EPOUT_SIZE MSC_DATA_PACKET_SIZE + +/* USB configuration descriptor structure */ +typedef struct +{ + usb_desc_config config; + + usb_desc_itf msc_itf; + usb_desc_ep msc_epin; + usb_desc_ep msc_epout; +} usb_desc_config_set; + +extern void* const usbd_msc_strings[USB_STRING_COUNT]; +extern const usb_desc_dev msc_dev_desc; +extern const usb_desc_config_set msc_config_desc; + +extern usb_class_core msc_class; + +#endif /* __USBD_MSC_CORE_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_data.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_data.h new file mode 100644 index 0000000..61500d0 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_data.h @@ -0,0 +1,49 @@ +/*! + \file usbd_msc_data.h + \brief the header file of the usbd_msc_data.c file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_MSC_DATA_H +#define __USBD_MSC_DATA_H + +#include "usbd_conf.h" + +#define MODE_SENSE6_LENGTH 8U +#define MODE_SENSE10_LENGTH 8U +#define INQUIRY_PAGE00_LENGTH 7U +#define FORMAT_CAPACITIES_LENGTH 20U + +extern const uint8_t msc_page00_inquiry_data[]; +extern const uint8_t msc_mode_sense6_data[]; +extern const uint8_t msc_mode_sense10_data[]; + +#endif /* __USBD_MSC_DATA_H_ */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_mem.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_mem.h new file mode 100644 index 0000000..d76fc74 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_mem.h @@ -0,0 +1,59 @@ +/*! + \file usbd_msc_mem.h + \brief header file for storage memory + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_MSC_MEM_H +#define __USBD_MSC_MEM_H + +#include "usbd_conf.h" + +#define USBD_STD_INQUIRY_LENGTH 36U + +typedef struct +{ + int8_t (*mem_init) (uint8_t lun); + int8_t (*mem_ready) (uint8_t lun); + int8_t (*mem_protected) (uint8_t lun); + int8_t (*mem_read) (uint8_t lun, uint8_t *buf, uint32_t block_addr, uint16_t block_len); + int8_t (*mem_write) (uint8_t lun, uint8_t *buf, uint32_t block_addr, uint16_t block_len); + int8_t (*mem_maxlun) (void); + + uint8_t *mem_toc_data; + uint8_t *mem_inquiry_data[MEM_LUN_NUM]; + uint32_t mem_block_size[MEM_LUN_NUM]; + uint32_t mem_block_len[MEM_LUN_NUM]; +}usbd_mem_cb; + +extern usbd_mem_cb *usbd_mem_fops; + +#endif /* __USBD_MSC_MEM_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_scsi.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_scsi.h new file mode 100644 index 0000000..0de5330 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Include/usbd_msc_scsi.h @@ -0,0 +1,53 @@ +/*! + \file usbd_msc_scsi.h + \brief the header file of the usbd_msc_scsi.c file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_MSC_SCSI_H +#define __USBD_MSC_SCSI_H + +#include "usbd_msc_data.h" +#include "usbd_msc_bbb.h" +#include "msc_scsi.h" + +#define SENSE_LIST_DEEPTH 4U + +extern msc_scsi_sense scsi_sense[SENSE_LIST_DEEPTH]; + +extern uint8_t scsi_sense_head; +extern uint8_t scsi_sense_tail; + +int8_t scsi_process_cmd (usb_core_driver *pudev, uint8_t lun, uint8_t *cmd); + +void scsi_sense_code (uint8_t lun, uint8_t skey, uint8_t asc); + +#endif /* __USBD_MSC_SCSI_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/app.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/app.c new file mode 100644 index 0000000..4635f5d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/app.c @@ -0,0 +1,73 @@ +/*! + \file main.c + \brief USB main routine for MSC device(Udisk) + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "usbd_msc_core.h" +#include +#include +#include + + +usb_core_driver USB_OTG_dev = { + .dev = { + .desc = { + .dev_desc = (uint8_t *)&msc_dev_desc, + .config_desc = (uint8_t *)&msc_config_desc, + .strings = usbd_msc_strings + } + } +}; + +/** + * @brief Main routine will construct a USB mass storage device + * @param None + * @retval None + */ +int main(void) +{ + eclic_global_interrupt_enable(); + + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL2_PRIO2); + + usb_rcu_config(); + + usb_timer_init(); + + usb_intr_config(); + + usbd_init(&USB_OTG_dev, USB_CORE_ENUM_FS, &msc_class); + + while (1) { + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/flash_msd.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/flash_msd.c new file mode 100644 index 0000000..9e79ff9 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/flash_msd.c @@ -0,0 +1,112 @@ +/*! + \file flash_msd.c + \brief flash access functions + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_conf.h" +#include "flash_msd.h" + +/* pages 0 and 1 base and end addresses */ +#define NAND_FLASH_BASE_ADDRESS 0x8010000 +#define PAGE_SIZE 0x400 + +/*! + \brief initialize the nand flash + \param[in] none + \param[out] none + \retval status +*/ +uint32_t flash_init () +{ + fmc_unlock(); + + return 0; +} + +/*! + \brief read data from multiple blocks of nand flash + \param[in] pBuf: pointer to user buffer + \param[in] read_addr: address to be read + \param[in] block_size: size of block + \param[in] block_num: number of block + \param[out] none + \retval status +*/ +uint32_t flash_multi_blocks_read (uint8_t *pBuf, uint32_t read_addr, uint16_t block_size, uint32_t block_num) +{ + uint32_t i; + uint8_t *pSource = (uint8_t *)(read_addr + NAND_FLASH_BASE_ADDRESS); + + /* Data transfer */ + while (block_num--) { + for (i = 0; i < block_size; i++) { + *pBuf++ = *pSource++; + } + } + + return 0; +} + +/*! + \brief write data to multiple blocks of flash + \param[in] pBuf: pointer to user buffer + \param[in] write_addr: address to be write + \param[in] block_size: block size + \param[in] block_num: number of block + \param[out] none + \retval status +*/ +uint32_t flash_multi_blocks_write (uint8_t *pBuf, + uint32_t write_addr, + uint16_t block_size, + uint32_t block_num) +{ + uint32_t i, page; + uint32_t start_page = (write_addr / PAGE_SIZE) * PAGE_SIZE + NAND_FLASH_BASE_ADDRESS; + uint32_t *ptrs = (uint32_t *)pBuf; + uint16_t word_count = block_size / 4; + + page = block_num; + + for(; page > 0; page--){ + fmc_page_erase(start_page); + + i = 0; + + do{ + fmc_word_program(start_page, *ptrs++); + start_page += 4; + }while(++i < word_count); + } + + return 0; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/gd32vf103_hw.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/gd32vf103_hw.c new file mode 100644 index 0000000..b2931b1 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/gd32vf103_hw.c @@ -0,0 +1,204 @@ +/*! + \file gd32vf103_hw.c + \brief USB hardware configuration for GD32VF103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include +#include +#include + +#define TIM_MSEC_DELAY 0x01 +#define TIM_USEC_DELAY 0x02 + +__IO uint32_t delay_time = 0; +__IO uint32_t timer_prescaler; +__IO uint32_t usbfs_prescaler = 0; + +static void hw_time_set (uint8_t unit); +static void hw_delay (uint32_t ntime, uint8_t unit); + +/*! + \brief configure USB clock + \param[in] none + \param[out] none + \retval none +*/ +void usb_rcu_config(void) +{ + uint32_t system_clock = rcu_clock_freq_get(CK_SYS); + + if (system_clock == 48000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1; + timer_prescaler = 3; + } else if (system_clock == 72000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1_5; + timer_prescaler = 5; + } else if (system_clock == 96000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV2; + timer_prescaler = 7; + } else { + /* reserved */ + } + + rcu_usb_clock_config(usbfs_prescaler); + rcu_periph_clock_enable(RCU_USBFS); +} + +/*! + \brief configure USB interrupt + \param[in] none + \param[out] none + \retval none +*/ +void usb_intr_config(void) +{ + eclic_irq_enable((uint8_t)USBFS_IRQn, 1, 0); + + /* enable the power module clock */ + rcu_periph_clock_enable(RCU_PMU); + + /* USB wakeup EXTI line configuration */ + exti_interrupt_flag_clear(EXTI_18); + exti_init(EXTI_18, EXTI_INTERRUPT, EXTI_TRIG_RISING); + exti_interrupt_enable(EXTI_18); + + eclic_irq_enable((uint8_t)USBFS_WKUP_IRQn, 3, 0); +} + +/*! + \brief initializes delay unit using Timer2 + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_init (void) +{ + rcu_periph_clock_enable(RCU_TIMER2); + + eclic_irq_enable(TIMER2_IRQn, 2, 0); +} + +/*! + \brief delay in micro seconds + \param[in] usec: value of delay required in micro seconds + \param[out] none + \retval none +*/ +void usb_udelay (const uint32_t usec) +{ + hw_delay(usec, TIM_USEC_DELAY); +} + +/*! + \brief delay in milli seconds + \param[in] msec: value of delay required in milli seconds + \param[out] none + \retval none +*/ +void usb_mdelay (const uint32_t msec) +{ + hw_delay(msec, TIM_MSEC_DELAY); +} + +/*! + \brief time base IRQ + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_irq (void) +{ + if (RESET != timer_flag_get(TIMER2, TIMER_FLAG_UP)){ + timer_flag_clear(TIMER2, TIMER_FLAG_UP); + + if (delay_time > 0x00U){ + delay_time--; + } else { + timer_disable(TIMER2); + } + } +} + +/*! + \brief delay routine based on TIM0 + \param[in] nTime: delay Time + \param[in] unit: delay Time unit = mili sec / micro sec + \param[out] none + \retval none +*/ +static void hw_delay(uint32_t ntime, uint8_t unit) +{ + delay_time = ntime; + + hw_time_set(unit); + + while (0U != delay_time) { + } + + timer_disable(TIMER2); +} + +/*! + \brief configures TIM0 for delay routine based on TIM0 + \param[in] unit: msec /usec + \param[out] none + \retval none +*/ +static void hw_time_set(uint8_t unit) +{ + timer_parameter_struct timer_initpara; + + rcu_periph_clock_enable(RCU_TIMER2); + timer_deinit(TIMER2); + + if(TIM_USEC_DELAY == unit) { + timer_initpara.period = 11; + } else if(TIM_MSEC_DELAY == unit) { + timer_initpara.period = 11999; + } + + timer_initpara.prescaler = timer_prescaler; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TIMER2, &timer_initpara); + + timer_update_event_enable(TIMER2); + timer_interrupt_enable(TIMER2,TIMER_INT_UP); + timer_flag_clear(TIMER2, TIMER_FLAG_UP); + timer_update_source_config(TIMER2, TIMER_UPDATE_SRC_GLOBAL); + + /* TIMER2 counter enable */ + timer_enable(TIMER2); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/gd32vf103_it.c new file mode 100644 index 0000000..8cae80e --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/gd32vf103_it.c @@ -0,0 +1,96 @@ +/*! + \file gd32vf103_it.c + \brief main interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usbd_int.h" +#include "drv_usb_hw.h" +#include "gd32vf103_it.h" + +extern usb_core_driver USB_OTG_dev; +extern uint32_t usbfs_prescaler; + +extern void usb_timer_irq(void); + +/*! + \brief this function handles USBD interrupt + \param[in] none + \param[out] none + \retval none +*/ +void USBFS_IRQHandler (void) +{ + usbd_isr (&USB_OTG_dev); +} + +/*! + \brief this function handles EXTI0_IRQ Handler + \param[in] none + \param[out] none + \retval none +*/ +void EXTI0_IRQHandler(void) +{ + +} + +/*! + \brief this function handles USBD wakeup interrupt request. + \param[in] none + \param[out] none + \retval none +*/ +void USBFS_WKUP_IRQHandler(void) +{ + if (USB_OTG_dev.bp.low_power) { + SystemInit(); + + rcu_usb_clock_config(usbfs_prescaler); + + rcu_periph_clock_enable(RCU_USBFS); + + usb_clock_active(&USB_OTG_dev); + } + + exti_interrupt_flag_clear(EXTI_18); +} + +/*! + \brief this function handles Timer0 updata interrupt request. + \param[in] none + \param[out] none + \retval none +*/ +void TIMER2_IRQHandler(void) +{ + usb_timer_irq(); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/system_gd32vf103.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/system_gd32vf103.c new file mode 100644 index 0000000..05e5205 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/system_gd32vf103.c @@ -0,0 +1,998 @@ +/*! + \file system_gd32vf103.h + \brief RISC-V Device Peripheral Access Layer Source File for + GD32VF103 Device Series + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32vf103.h" + +/* system frequency define */ +#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ + +/* select a system clock by uncommenting the following line */ +/* use IRC8M */ +//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000) + +/********************************************************************/ +//#define __SYSTEM_CLOCK_HXTAL (HXTAL_VALUE) +//#define __SYSTEM_CLOCK_24M_PLL_HXTAL (uint32_t)(24000000) +/********************************************************************/ + +//#define __SYSTEM_CLOCK_36M_PLL_HXTAL (uint32_t)(36000000) +//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_56M_PLL_HXTAL (uint32_t)(56000000) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000) +//#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) + +#define SEL_IRC8M 0x00U +#define SEL_HXTAL 0x01U +#define SEL_PLL 0x02U + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_48M_PLL_IRC8M +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M; +static void system_clock_48m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M; +static void system_clock_72m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M; +static void system_clock_108m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; +static void system_clock_hxtal(void); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_24M_PLL_HXTAL; +static void system_clock_24m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_36M_PLL_HXTAL; +static void system_clock_36m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL; +static void system_clock_48m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_56M_PLL_HXTAL; +static void system_clock_56m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; +static void system_clock_72m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL; +static void system_clock_96m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; +static void system_clock_108m_hxtal(void); +#else +uint32_t SystemCoreClock = IRC8M_VALUE; +#endif /* __SYSTEM_CLOCK_48M_PLL_IRC8M */ + +/* configure the system clock */ +static void system_clock_config(void); + +/*! + \brief configure the system clock + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_config(void) +{ +#ifdef __SYSTEM_CLOCK_HXTAL + system_clock_hxtal(); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) + system_clock_24m_hxtal(); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) + system_clock_36m_hxtal(); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) + system_clock_48m_hxtal(); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) + system_clock_56m_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) + system_clock_72m_hxtal(); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) + system_clock_96m_hxtal(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) + system_clock_108m_hxtal(); + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) + system_clock_48m_irc8m(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) + system_clock_72m_irc8m(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) + system_clock_108m_irc8m(); +#endif /* __SYSTEM_CLOCK_HXTAL */ +} + +/*! + \brief setup the microcontroller system, initialize the system + \param[in] none + \param[out] none + \retval none +*/ +void SystemInit(void) +{ + /* reset the RCC clock configuration to the default reset state */ + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL); + + /* reset HXTALEN, CKMEN, PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); + + /* Reset HXTALBPS bit */ + RCU_CTL &= ~(RCU_CTL_HXTALBPS); + + /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */ + + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | + RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4); + RCU_CFG1 = 0x00000000U; + + /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + /* disable all interrupts */ + RCU_INT = 0x00FF0000U; + + /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ + system_clock_config(); +} + +/*! + \brief update the SystemCoreClock with current core clock retrieved from cpu registers + \param[in] none + \param[out] none + \retval none +*/ +void SystemCoreClockUpdate(void) +{ + uint32_t scss; + uint32_t pllsel, predv0sel, pllmf, ck_src; + uint32_t predv0, predv1, pll1mf; + + scss = GET_BITS(RCU_CFG0, 2, 3); + + switch (scss) + { + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + SystemCoreClock = IRC8M_VALUE; + break; + + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + SystemCoreClock = HXTAL_VALUE; + break; + + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + + + if(RCU_PLLSRC_IRC8M_DIV2 == pllsel){ + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE / 2U; + }else{ + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + + predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); + + /* source clock use PLL1 */ + if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ + predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; + pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; + if(17U == pll1mf){ + pll1mf = 20U; + } + ck_src = (ck_src / predv1) * pll1mf; + } + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; + ck_src /= predv0; + } + + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + + if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ + pllmf |= 0x10U; + } + + if(pllmf >= 15U){ + pllmf += 1U; + }else{ + pllmf += 2U; + } + + SystemCoreClock = ck_src * pllmf; + + if(15U == pllmf){ + /* PLL source clock multiply by 6.5 */ + SystemCoreClock = ck_src * 6U + ck_src / 2U; + } + + break; + + /* IRC8M is selected as CK_SYS */ + default: + SystemCoreClock = IRC8M_VALUE; + break; + } +} + +#ifdef __SYSTEM_CLOCK_HXTAL +/*! + \brief configure the system clock to HXTAL + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + + /* wait until HXTAL is selected as system clock */ + while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +/*! + \brief configure the system clock to 24M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_24m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 6 = 24 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +/*! + \brief configure the system clock to 36M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_36m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 9 = 36 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +/*! + \brief configure the system clock to 48M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12); + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +/*! + \brief configure the system clock to 56M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_56m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 14 = 56 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL14); + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +/*! + \brief configure the system clock to 72M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18); + + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +/*! + \brief configure the system clock to 96M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_96m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + if(HXTAL_VALUE==25000000){ + + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +/*! + \brief configure the system clock to 108M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ + +static void system_clock_108m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PREDV1_DIV5 | RCU_PLL1_MUL8 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL2EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){ + } + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 | RCU_PREDV1_DIV2 | RCU_PLL1_MUL20 | RCU_PLL2_MUL20); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } + + /* enable PLL2 */ + RCU_CTL |= RCU_CTL_PLL2EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){ + } + + } + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) +/*! + \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL12; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +/*! + \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL18; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +/*! + \brief configure the system clock to 108M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL27; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#endif diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_msc_bbb.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_msc_bbb.c new file mode 100644 index 0000000..37bf786 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_msc_bbb.c @@ -0,0 +1,275 @@ +/*! + \file usbd_msc_bbb.c + \brief USB BBB(Bulk/Bulk/Bulk) protocol core functions + \note BBB means Bulk-only transport protocol for USB MSC + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_msc_bbb.h" +#include "usbd_msc_mem.h" +#include "usbd_msc_scsi.h" +#include "usbd_transc.h" +#include "usbd_enum.h" + +uint8_t msc_bbb_state; +uint8_t msc_bbb_status; + +uint16_t msc_bbb_datalen; + +uint8_t msc_bbb_data[MSC_MEDIA_PACKET_SIZE]; + +msc_bbb_cbw bbb_cbw; +msc_bbb_csw bbb_csw; + +static void msc_bbb_cbw_decode (usb_core_driver *pudev); +static void msc_bbb_data_send (usb_core_driver *pudev, uint8_t *pbuf, uint16_t Len); +static void msc_bbb_abort (usb_core_driver *pudev); + +/*! + \brief initialize the bbb process + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval none +*/ +void msc_bbb_init (usb_core_driver *pudev) +{ + uint8_t lun_num; + + msc_bbb_state = BBB_IDLE; + msc_bbb_status = BBB_STATUS_NORMAL; + + /* init the storage logic unit */ + for(lun_num = 0U; lun_num < MEM_LUN_NUM; lun_num++) { + usbd_mem_fops->mem_init(lun_num); + } + + /* flush the Rx FIFO */ + usbd_fifo_flush (pudev, MSC_OUT_EP); + + /* flush the Tx FIFO */ + usbd_fifo_flush (pudev, MSC_IN_EP); + + /* prepare endpoint to receive the first BBB CBW */ + usbd_ep_recev (pudev, MSC_OUT_EP, (uint8_t *)&bbb_cbw, BBB_CBW_LENGTH); +} + +/*! + \brief reset the BBB machine + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval none +*/ +void msc_bbb_reset (usb_core_driver *pudev) +{ + msc_bbb_state = BBB_IDLE; + msc_bbb_status = BBB_STATUS_RECOVERY; + + /* prapare endpoint to receive the first BBB command */ + usbd_ep_recev (pudev, MSC_OUT_EP, (uint8_t *)&bbb_cbw, BBB_CBW_LENGTH); +} + +/*! + \brief de-initialize the BBB machine + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval none +*/ +void msc_bbb_deinit (usb_core_driver *pudev) +{ + msc_bbb_state = BBB_IDLE; +} + +/*! + \brief handle BBB data IN stage + \param[in] pudev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval none +*/ +void msc_bbb_data_in (usb_core_driver *pudev, uint8_t ep_num) +{ + usbd_fifo_flush (pudev, MSC_IN_EP); + + switch (msc_bbb_state) { + case BBB_DATA_IN: + if (scsi_process_cmd (pudev, bbb_cbw.bCBWLUN, &bbb_cbw.CBWCB[0]) < 0) { + msc_bbb_csw_send (pudev, CSW_CMD_FAILED); + } + break; + + case BBB_SEND_DATA: + case BBB_LAST_DATA_IN: + msc_bbb_csw_send (pudev, CSW_CMD_PASSED); + break; + + default: + break; + } +} + +/*! + \brief handle BBB data OUT stage + \param[in] pudev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval none +*/ +void msc_bbb_data_out (usb_core_driver *pudev, uint8_t ep_num) +{ + switch (msc_bbb_state) { + case BBB_IDLE: + msc_bbb_cbw_decode (pudev); + break; + + case BBB_DATA_OUT: + if (scsi_process_cmd (pudev, bbb_cbw.bCBWLUN, &bbb_cbw.CBWCB[0]) < 0) { + msc_bbb_csw_send (pudev, CSW_CMD_FAILED); + } + break; + + default: + break; + } +} + +/*! + \brief decode the CBW command and set the BBB state machine accordingtly + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +static void msc_bbb_cbw_decode (usb_core_driver *pudev) +{ + bbb_csw.dCSWTag = bbb_cbw.dCBWTag; + bbb_csw.dCSWDataResidue = bbb_cbw.dCBWDataTransferLength; + + if ((BBB_CBW_LENGTH != usbd_rxcount_get (pudev, MSC_OUT_EP)) || + (BBB_CBW_SIGNATURE != bbb_cbw.dCBWSignature)|| + (bbb_cbw.bCBWLUN > 1U) || + (bbb_cbw.bCBWCBLength < 1U) || + (bbb_cbw.bCBWCBLength > 16U)) { + /* illegal command handler */ + scsi_sense_code (bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); + + msc_bbb_status = BBB_STATUS_ERROR; + + msc_bbb_abort (pudev); + } else { + if (scsi_process_cmd (pudev, bbb_cbw.bCBWLUN, &bbb_cbw.CBWCB[0]) < 0) { + msc_bbb_abort (pudev); + } else if ((BBB_DATA_IN != msc_bbb_state) && + (BBB_DATA_OUT != msc_bbb_state) && + (BBB_LAST_DATA_IN != msc_bbb_state)) { /* burst xfer handled internally */ + if (msc_bbb_datalen > 0U) { + msc_bbb_data_send (pudev, msc_bbb_data, msc_bbb_datalen); + } else if (0U == msc_bbb_datalen) { + msc_bbb_csw_send (pudev, CSW_CMD_PASSED); + } + } + } +} + +/*! + \brief send the requested data + \param[in] udev: pointer to USB device instance + \param[in] buf: pointer to data buffer + \param[in] len: data length + \param[out] none + \retval none +*/ +static void msc_bbb_data_send (usb_core_driver *pudev, uint8_t *buf, uint16_t len) +{ + len = USB_MIN (bbb_cbw.dCBWDataTransferLength, len); + + bbb_csw.dCSWDataResidue -= len; + bbb_csw.bCSWStatus = CSW_CMD_PASSED; + msc_bbb_state = BBB_SEND_DATA; + + usbd_ep_send (pudev, MSC_IN_EP, buf, len); +} + +/*! + \brief send the CSW(command status wrapper) + \param[in] udev: pointer to USB device instance + \param[in] csw_status: CSW status + \param[out] none + \retval none +*/ +void msc_bbb_csw_send (usb_core_driver *pudev, uint8_t csw_status) +{ + bbb_csw.dCSWSignature = BBB_CSW_SIGNATURE; + bbb_csw.bCSWStatus = csw_status; + msc_bbb_state = BBB_IDLE; + + usbd_ep_send (pudev, MSC_IN_EP, (uint8_t *)&bbb_csw, BBB_CSW_LENGTH); + + /* prapare endpoint to receive next command */ + usbd_ep_recev (pudev, MSC_OUT_EP, (uint8_t *)&bbb_cbw, BBB_CBW_LENGTH); +} + +/*! + \brief abort the current transfer + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval none +*/ +static void msc_bbb_abort (usb_core_driver *pudev) +{ + if ((bbb_cbw.bmCBWFlags == 0) && + (bbb_cbw.dCBWDataTransferLength != 0) && + (msc_bbb_status == BBB_STATUS_NORMAL)) { + usbd_ep_stall(pudev, MSC_OUT_EP); + } + + usbd_ep_stall(pudev, MSC_IN_EP); + + if (msc_bbb_status == BBB_STATUS_ERROR) { + usbd_ep_recev (pudev, MSC_OUT_EP, (uint8_t *)&bbb_cbw, BBB_CBW_LENGTH); + } +} + +/*! + \brief complete the clear feature request + \param[in] pudev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval none +*/ +void msc_bbb_clrfeature (usb_core_driver *pudev, uint8_t ep_num) +{ + if (msc_bbb_status == BBB_STATUS_ERROR)/* bad CBW signature */ { + usbd_ep_stall(pudev, MSC_IN_EP); + + msc_bbb_status = BBB_STATUS_NORMAL; + } else if(((ep_num & 0x80) == 0x80) && (msc_bbb_status != BBB_STATUS_RECOVERY)) { + msc_bbb_csw_send (pudev, CSW_CMD_FAILED); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_msc_core.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_msc_core.c new file mode 100644 index 0000000..1b9df70 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_msc_core.c @@ -0,0 +1,277 @@ +/*! + \file usbd_msc_core.c + \brief USB MSC device class core functions + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_msc_mem.h" +#include "usbd_msc_core.h" +#include "usbd_msc_bbb.h" +#include "usbd_enum.h" + +#define USBD_VID 0x28E9U +#define USBD_PID 0x028FU + +static uint8_t msc_core_init (usb_dev *pudev, uint8_t config_index); +static uint8_t msc_core_deinit (usb_dev *pudev, uint8_t config_index); +static uint8_t msc_core_req (usb_dev *pudev, usb_req *req); +static uint8_t msc_core_in (usb_dev *pudev, uint8_t ep_num); +static uint8_t msc_core_out (usb_dev *pudev, uint8_t ep_num); + +usb_class_core msc_class = +{ + .init = msc_core_init, + .deinit = msc_core_deinit, + + .req_proc = msc_core_req, + + .data_in = msc_core_in, + .data_out = msc_core_out +}; + +/* note: it should use the C99 standard when compiling the below codes */ +/* USB standard device descriptor */ +const usb_desc_dev msc_dev_desc = +{ + .header = { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, + .bcdUSB = 0x0200U, + .bDeviceClass = 0x00U, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM +}; + +/* USB device configuration descriptor */ +const usb_desc_config_set msc_config_desc = +{ + .config = + { + .header = { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = USB_MSC_CONFIG_DESC_SIZE, + .bNumInterfaces = 0x01U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0xC0U, + .bMaxPower = 0x32U + }, + + .msc_itf = + { + .header = { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x02U, + .bInterfaceClass = USB_CLASS_MSC, + .bInterfaceSubClass = USB_MSC_SUBCLASS_SCSI, + .bInterfaceProtocol = USB_MSC_PROTOCOL_BBB, + .iInterface = 0x00U + }, + + .msc_epin = + { + .header = { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = MSC_IN_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = MSC_EPIN_SIZE, + .bInterval = 0x00U + }, + + .msc_epout = + { + .header = { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = MSC_OUT_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = MSC_EPOUT_SIZE, + .bInterval = 0x00U + } +}; + +/* USB language ID descriptor */ +const usb_desc_LANGID usbd_language_id_desc = +{ + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + .wLANGID = ENG_LANGID +}; + +/* usb string descriptor */ +void *const usbd_msc_strings[] = +{ + [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, + [STR_IDX_MFC] = USBD_STRING_DESC("GigaDevice"), + [STR_IDX_PRODUCT] = USBD_STRING_DESC("GD32 USB MSC in FS Mode"), + [STR_IDX_SERIAL] = USBD_STRING_DESC("GD32VF103-V1.0.0-ka4db5ec") +}; + +static uint8_t usbd_msc_maxlun = 0; + +/*! + \brief initialize the MSC device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t msc_core_init (usb_dev *pudev, uint8_t config_index) +{ + /* configure MSC Tx endpoint */ + usbd_ep_setup (pudev, &(msc_config_desc.msc_epin)); + + /* configure MSC Rx endpoint */ + usbd_ep_setup (pudev, &(msc_config_desc.msc_epout)); + + /* init the BBB layer */ + msc_bbb_init(pudev); + + return USBD_OK; +} + +/*! + \brief de-initialize the MSC device + \param[in] pudev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t msc_core_deinit (usb_dev *pudev, uint8_t config_index) +{ + /* clear MSC endpoints */ + usbd_ep_clear (pudev, MSC_IN_EP); + usbd_ep_clear (pudev, MSC_OUT_EP); + + /* un-init the BBB layer */ + msc_bbb_deinit(pudev); + + return USBD_OK; +} + +/*! + \brief handle the MSC class-specific and standard requests + \param[in] pudev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t msc_core_req (usb_dev *pudev, usb_req *req) +{ + usb_transc *transc = &pudev->dev.transc_in[0]; + + switch (req->bRequest) { + case BBB_GET_MAX_LUN : + if((0U == req->wValue) && + (1U == req->wLength) && + (0x80U == (req->bmRequestType & 0x80U))) { + usbd_msc_maxlun = usbd_mem_fops->mem_maxlun(); + + transc->xfer_buf = &usbd_msc_maxlun; + transc->remain_len = 1; + } else { + return USBD_FAIL; + } + break; + + case BBB_RESET : + if((0U == req->wValue) && + (0U == req->wLength) && + (0x80U != (req->bmRequestType & 0x80U))) { + msc_bbb_reset(pudev); + } else { + return USBD_FAIL; + } + break; + + case USB_CLEAR_FEATURE: + msc_bbb_clrfeature (pudev, (uint8_t)req->wIndex); + break; + + default: + return USBD_FAIL; + } + + return USBD_OK; +} + +/*! + \brief handle data in stage + \param[in] pudev: pointer to USB device instance + \param[in] ep_num: the endpoint number + \param[out] none + \retval none +*/ +static uint8_t msc_core_in (usb_dev *pudev, uint8_t ep_num) +{ + if ((MSC_IN_EP & 0x7FU) == ep_num) { + msc_bbb_data_in(pudev, ep_num); + } + + return USBD_OK; +} + +/*! + \brief handle data out stage + \param[in] pudev: pointer to USB device instance + \param[in] ep_num: the endpoint number + \param[out] none + \retval none +*/ +static uint8_t msc_core_out (usb_dev *pudev, uint8_t ep_num) +{ + if (MSC_OUT_EP == ep_num) { + msc_bbb_data_out (pudev, ep_num); + } + + return USBD_OK; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_msc_data.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_msc_data.c new file mode 100644 index 0000000..f90fcba --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_msc_data.c @@ -0,0 +1,73 @@ +/*! + \file usbd_msc_data.c + \brief USB MSC vital inquiry pages and sense data + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_msc_data.h" + +/* USB mass storage page 0 inquiry data */ +const uint8_t msc_page00_inquiry_data[] = +{ + 0x00, + 0x00, + 0x00, + (INQUIRY_PAGE00_LENGTH - 4), + 0x00, + 0x80, + 0x83 +}; + +/* USB mass storage sense 6 data */ +const uint8_t msc_mode_sense6_data[] = +{ + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 +}; + +/* USB mass storage sense 10 data */ +const uint8_t msc_mode_sense10_data[] = +{ + 0x00, + 0x06, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 +}; diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_msc_scsi.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_msc_scsi.c new file mode 100644 index 0000000..2d45c70 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_msc_scsi.c @@ -0,0 +1,650 @@ +/*! + \file usbd_msc_scsi.c + \brief USB SCSI layer functions + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_msc_bbb.h" +#include "usbd_msc_scsi.h" +#include "usbd_msc_mem.h" +#include "usbd_msc_data.h" +#include "usbd_enum.h" + +msc_scsi_sense scsi_sense[SENSE_LIST_DEEPTH]; + +uint8_t scsi_sense_head; +uint8_t scsi_sense_tail; + +uint32_t scsi_blk_size[MEM_LUN_NUM]; +uint32_t scsi_blk_nbr[MEM_LUN_NUM]; + +uint32_t scsi_blk_addr; +uint32_t scsi_blk_len; + +usb_core_driver *cdev; + +static int8_t scsi_test_unit_ready (uint8_t lun, uint8_t *params); +static int8_t scsi_inquiry (uint8_t lun, uint8_t *params); +static int8_t scsi_read_format_capacity (uint8_t lun, uint8_t *params); +static int8_t scsi_read_capacity10 (uint8_t lun, uint8_t *params); +static int8_t scsi_request_sense (uint8_t lun, uint8_t *params); +static int8_t scsi_start_stop_unit (uint8_t lun, uint8_t *params); +static int8_t scsi_allow_medium_removal (uint8_t lun, uint8_t *params); +static int8_t scsi_mode_sense6 (uint8_t lun, uint8_t *params); +static int8_t scsi_toc_cmd_read (uint8_t lun, uint8_t *params); +static int8_t scsi_mode_sense10 (uint8_t lun, uint8_t *params); +static int8_t scsi_write10 (uint8_t lun, uint8_t *params); +static int8_t scsi_read10 (uint8_t lun, uint8_t *params); +static int8_t scsi_verify10 (uint8_t lun, uint8_t *params); +static int8_t scsi_check_address_range (uint8_t lun, uint32_t blk_offset, uint16_t blk_nbr); +static int8_t scsi_process_read (uint8_t lun); +static int8_t scsi_process_write (uint8_t lun); +static int8_t scsi_format_cmd (uint8_t lun); + +/*! + \brief process SCSI commands + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval none +*/ +int8_t scsi_process_cmd(usb_core_driver *pudev, uint8_t lun, uint8_t *params) +{ + cdev = pudev; + + switch (params[0]) { + case SCSI_TEST_UNIT_READY: + return scsi_test_unit_ready (lun, params); + + case SCSI_REQUEST_SENSE: + return scsi_request_sense (lun, params); + + case SCSI_INQUIRY: + return scsi_inquiry (lun, params); + + case SCSI_START_STOP_UNIT: + return scsi_start_stop_unit (lun, params); + + case SCSI_ALLOW_MEDIUM_REMOVAL: + return scsi_allow_medium_removal (lun, params); + + case SCSI_MODE_SENSE6: + return scsi_mode_sense6 (lun, params); + + case SCSI_MODE_SENSE10: + return scsi_mode_sense10 (lun, params); + + case SCSI_READ_FORMAT_CAPACITIES: + return scsi_read_format_capacity (lun, params); + + case SCSI_READ_CAPACITY10: + return scsi_read_capacity10 (lun, params); + + case SCSI_READ10: + return scsi_read10 (lun, params); + + case SCSI_WRITE10: + return scsi_write10 (lun, params); + + case SCSI_VERIFY10: + return scsi_verify10 (lun, params); + + case SCSI_FORMAT_UNIT: + return scsi_format_cmd (lun); + + case SCSI_READ_TOC_DATA: + return scsi_toc_cmd_read (lun, params); + + default: + scsi_sense_code (lun, ILLEGAL_REQUEST, INVALID_CDB); + return -1; + } +} + +/*! + \brief process SCSI Test Unit Ready command + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval none +*/ +static int8_t scsi_test_unit_ready (uint8_t lun, uint8_t *params) +{ + /* case 9 : Hi > D0 */ + if (0U != bbb_cbw.dCBWDataTransferLength) { + scsi_sense_code (bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); + + return -1; + } + + if (0U != usbd_mem_fops->mem_ready(lun)) { + scsi_sense_code(lun, NOT_READY, MEDIUM_NOT_PRESENT); + + return -1; + } + + msc_bbb_datalen = 0; + + return 0; +} + +/*! + \brief process Inquiry command + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval none +*/ +static int8_t scsi_inquiry (uint8_t lun, uint8_t *params) +{ + uint8_t *page = NULL; + + uint16_t len = 0U; + + if (params[1] & 0x01U) { + /* Evpd is set */ + page = (uint8_t *)msc_page00_inquiry_data; + + len = INQUIRY_PAGE00_LENGTH; + } else { + page = (uint8_t *)usbd_mem_fops->mem_inquiry_data[lun]; + + len = page[4] + 5; + + if (params[4] <= len) { + len = params[4]; + } + } + + msc_bbb_datalen = len; + + while (len) { + len--; + msc_bbb_data[len] = page[len]; + } + + return 0; +} + +/*! + \brief process Read Capacity 10 command + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval none +*/ +static int8_t scsi_read_capacity10 (uint8_t lun, uint8_t *params) +{ + uint32_t blk_num = usbd_mem_fops->mem_block_len[lun] - 1; + + scsi_blk_nbr[lun] = usbd_mem_fops->mem_block_len[lun]; + scsi_blk_size[lun] = usbd_mem_fops->mem_block_size[lun]; + + msc_bbb_data[0] = (uint8_t)(blk_num >> 24); + msc_bbb_data[1] = (uint8_t)(blk_num >> 16); + msc_bbb_data[2] = (uint8_t)(blk_num >> 8); + msc_bbb_data[3] = (uint8_t)(blk_num); + + msc_bbb_data[4] = (uint8_t)(scsi_blk_size[lun] >> 24); + msc_bbb_data[5] = (uint8_t)(scsi_blk_size[lun] >> 16); + msc_bbb_data[6] = (uint8_t)(scsi_blk_size[lun] >> 8); + msc_bbb_data[7] = (uint8_t)(scsi_blk_size[lun]); + + msc_bbb_datalen = 8; + + return 0; +} + +/*! + \brief process Read Format Capacity command + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval none +*/ +static int8_t scsi_read_format_capacity (uint8_t lun, uint8_t *params) +{ + uint32_t blk_size = usbd_mem_fops->mem_block_size[lun]; + uint32_t blk_num = usbd_mem_fops->mem_block_len[lun]; + + uint16_t i = 0U; + + for (i = 0U; i < 12U; i++) { + msc_bbb_data[i] = 0; + } + + uint32_t blk_nbr = blk_num - 1; + + msc_bbb_data[3] = 0x08U; + msc_bbb_data[4] = (uint8_t)(blk_nbr >> 24); + msc_bbb_data[5] = (uint8_t)(blk_nbr >> 16); + msc_bbb_data[6] = (uint8_t)(blk_nbr >> 8); + msc_bbb_data[7] = (uint8_t)(blk_nbr); + + msc_bbb_data[8] = 0x02U; + msc_bbb_data[9] = (uint8_t)(blk_size >> 16); + msc_bbb_data[10] = (uint8_t)(blk_size >> 8); + msc_bbb_data[11] = (uint8_t)(blk_size); + + msc_bbb_datalen = 12U; + + return 0; +} + +/*! + \brief process Mode Sense6 command + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval none +*/ +static int8_t scsi_mode_sense6 (uint8_t lun, uint8_t *params) +{ + uint16_t len = 8U; + + msc_bbb_datalen = len; + + while (len) { + len--; + msc_bbb_data[len] = msc_mode_sense6_data[len]; + } + + return 0; +} + +/*! + \brief process Mode Sense10 command + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval none +*/ +static int8_t scsi_mode_sense10 (uint8_t lun, uint8_t *params) +{ + uint16_t len = 8; + + msc_bbb_datalen = len; + + while (len) { + len--; + msc_bbb_data[len] = msc_mode_sense10_data[len]; + } + + return 0; +} + +/*! + \brief process Request Sense command + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval none +*/ +static int8_t scsi_request_sense (uint8_t lun, uint8_t *params) +{ + uint8_t i = 0U; + + for (i = 0U; i < REQUEST_SENSE_DATA_LEN; i++) { + msc_bbb_data[i] = 0U; + } + + msc_bbb_data[0] = 0x70U; + msc_bbb_data[7] = REQUEST_SENSE_DATA_LEN - 6U; + + if ((scsi_sense_head != scsi_sense_tail)) { + msc_bbb_data[2] = scsi_sense[scsi_sense_head].SenseKey; + msc_bbb_data[12] = scsi_sense[scsi_sense_head].ASCQ; + msc_bbb_data[13] = scsi_sense[scsi_sense_head].ASC; + scsi_sense_head++; + + if (scsi_sense_head == SENSE_LIST_DEEPTH) { + scsi_sense_head = 0U; + } + } + + msc_bbb_datalen = USB_MIN(REQUEST_SENSE_DATA_LEN, params[4]); + + return 0; +} + +/*! + \brief load the last error code in the error list + \param[in] lun: logical unit number + \param[in] skey: sense key + \param[in] asc: additional aense key + \param[out] none + \retval none +*/ +void scsi_sense_code (uint8_t lun, uint8_t skey, uint8_t asc) +{ + scsi_sense[scsi_sense_tail].SenseKey = skey; + scsi_sense[scsi_sense_tail].ASC = asc << 8; + scsi_sense_tail++; + + if (SENSE_LIST_DEEPTH == scsi_sense_tail) { + scsi_sense_tail = 0; + } +} + +/*! + \brief process Start Stop Unit command + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval none +*/ +static int8_t scsi_start_stop_unit (uint8_t lun, uint8_t *params) +{ + msc_bbb_datalen = 0; + + return 0; +} + +/*! + \brief process Allow Medium Removal command + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval none +*/ +static int8_t scsi_allow_medium_removal (uint8_t lun, uint8_t *params) +{ + msc_bbb_datalen = 0; + + return 0; +} + +/*! + \brief process Read10 command + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval none +*/ +static int8_t scsi_read10 (uint8_t lun, uint8_t *params) +{ + if (msc_bbb_state == BBB_IDLE) { + /* direction is from device to host */ + if (0x80U != (bbb_cbw.bmCBWFlags & 0x80U)) { + scsi_sense_code (bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); + + return -1; + } + + if (0U != usbd_mem_fops->mem_ready(lun)) { + scsi_sense_code (lun, NOT_READY, MEDIUM_NOT_PRESENT); + + return -1; + } + + scsi_blk_addr = (params[2] << 24) | (params[3] << 16) | \ + (params[4] << 8) | params[5]; + + scsi_blk_len = (params[7] << 8) | params[8]; + + if (scsi_check_address_range (lun, scsi_blk_addr, scsi_blk_len) < 0) { + return -1; /* error */ + } + + msc_bbb_state = BBB_DATA_IN; + + scsi_blk_addr *= scsi_blk_size[lun]; + scsi_blk_len *= scsi_blk_size[lun]; + + /* cases 4,5 : Hi <> Dn */ + if (bbb_cbw.dCBWDataTransferLength != scsi_blk_len) { + scsi_sense_code (bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); + + return -1; + } + } + + msc_bbb_datalen = MSC_MEDIA_PACKET_SIZE; + + return scsi_process_read (lun); +} + +/*! + \brief process Write10 command + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval none +*/ +static int8_t scsi_write10 (uint8_t lun, uint8_t *params) +{ + if (BBB_IDLE == msc_bbb_state) { + /* case 8 : Hi <> Do */ + if (0x80U == (bbb_cbw.bmCBWFlags & 0x80U)) { + scsi_sense_code (bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); + + return -1; + } + + /* check whether media is ready */ + if (0U != usbd_mem_fops->mem_ready(lun)) { + scsi_sense_code (lun, NOT_READY, MEDIUM_NOT_PRESENT); + + return -1; + } + + /* check if media is write-protected */ + if (0U != usbd_mem_fops->mem_protected(lun)) { + scsi_sense_code (lun, NOT_READY, WRITE_PROTECTED); + + return -1; + } + + scsi_blk_addr = (params[2] << 24) | (params[3] << 16) | \ + (params[4] << 8) | params[5]; + + scsi_blk_len = (params[7] << 8) | params[8]; + + /* check if LBA address is in the right range */ + if (scsi_check_address_range (lun, scsi_blk_addr, scsi_blk_len) < 0) { + return -1; /* error */ + } + + scsi_blk_addr *= scsi_blk_size[lun]; + scsi_blk_len *= scsi_blk_size[lun]; + + /* cases 3,11,13 : Hn,Ho <> D0 */ + if (bbb_cbw.dCBWDataTransferLength != scsi_blk_len) { + scsi_sense_code (bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); + + return -1; + } + + /* prepare endpoint to receive first data packet */ + msc_bbb_state = BBB_DATA_OUT; + + usbd_ep_recev (cdev, + MSC_OUT_EP, + msc_bbb_data, + USB_MIN (scsi_blk_len, MSC_MEDIA_PACKET_SIZE)); + } else { /* write process ongoing */ + return scsi_process_write (lun); + } + + return 0; +} + +/*! + \brief process Verify10 command + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval none +*/ +static int8_t scsi_verify10 (uint8_t lun, uint8_t *params) +{ + if (0x02U == (params[1] & 0x02U)) { + scsi_sense_code (lun, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND); + + return -1; /* error, verify mode not supported*/ + } + + if (scsi_check_address_range (lun, scsi_blk_addr, scsi_blk_len) < 0) { + return -1; /* error */ + } + + msc_bbb_datalen = 0U; + + return 0; +} + +/*! + \brief check address range + \param[in] lun: logical unit number + \param[in] blk_offset: block offset + \param[in] blk_nbr: number of block to be processed + \param[out] none + \retval none +*/ +static int8_t scsi_check_address_range (uint8_t lun, uint32_t blk_offset, uint16_t blk_nbr) +{ + if ((blk_offset + blk_nbr) > scsi_blk_nbr[lun]) { + scsi_sense_code (lun, ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE); + + return -1; + } + + return 0; +} + +/*! + \brief handle read process + \param[in] lun: logical unit number + \param[out] none + \retval none +*/ +static int8_t scsi_process_read (uint8_t lun) +{ + uint32_t len = USB_MIN(scsi_blk_len, MSC_MEDIA_PACKET_SIZE); + + if (usbd_mem_fops->mem_read(lun, + msc_bbb_data, + scsi_blk_addr, + len / scsi_blk_size[lun]) < 0) { + scsi_sense_code(lun, HARDWARE_ERROR, UNRECOVERED_READ_ERROR); + + return -1; + } + + usbd_ep_send (cdev, MSC_IN_EP, msc_bbb_data, len); + + scsi_blk_addr += len; + scsi_blk_len -= len; + + /* case 6 : Hi = Di */ + bbb_csw.dCSWDataResidue -= len; + + if (0U == scsi_blk_len) { + msc_bbb_state = BBB_LAST_DATA_IN; + } + + return 0; +} + +/*! + \brief handle write process + \param[in] lun: logical unit number + \param[out] none + \retval status +*/ +static int8_t scsi_process_write (uint8_t lun) +{ + uint32_t len = USB_MIN(scsi_blk_len, MSC_MEDIA_PACKET_SIZE); + + if (usbd_mem_fops->mem_write (lun, + msc_bbb_data, + scsi_blk_addr, + len / scsi_blk_size[lun]) < 0) { + scsi_sense_code(lun, HARDWARE_ERROR, WRITE_FAULT); + + return -1; + } + + scsi_blk_addr += len; + scsi_blk_len -= len; + + /* case 12 : Ho = Do */ + bbb_csw.dCSWDataResidue -= len; + + if (0U == scsi_blk_len) { + msc_bbb_csw_send (cdev, CSW_CMD_PASSED); + } else { + /* prapare endpoint to receive next packet */ + usbd_ep_recev (cdev, + MSC_OUT_EP, + msc_bbb_data, + USB_MIN (scsi_blk_len, MSC_MEDIA_PACKET_SIZE)); + } + + return 0; +} + +/*! + \brief process Format Unit command + \param[in] lun: logical unit number + \param[out] none + \retval status +*/ +static int8_t scsi_format_cmd (uint8_t lun) +{ + return 0; +} + +/*! + \brief process Read_Toc command + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval none +*/ +static int8_t scsi_toc_cmd_read (uint8_t lun, uint8_t *params) +{ + uint8_t* pPage; + uint16_t len; + + pPage = (uint8_t *)&usbd_mem_fops->mem_toc_data[lun * READ_TOC_CMD_LEN]; + len = pPage[1] + 2; + + msc_bbb_datalen = len; + + while (len) { + len--; + msc_bbb_data[len] = pPage[len]; + } + + return 0; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_storage_msd.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_storage_msd.c new file mode 100644 index 0000000..cfca536 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/Source/usbd_storage_msd.c @@ -0,0 +1,224 @@ +/*! + \file usbd_storage_msd.c + \brief disk operations functions + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usb_conf.h" +//#include "sram_msd.h" +#include "flash_msd.h" +#include "usbd_msc_mem.h" + +/* USB Mass storage Standard Inquiry Data */ + +const int8_t STORAGE_InquiryData[] = +{ +#ifdef SRAM_STORAGE + /* LUN 0 */ + 0x00, + 0x80, + 0x00, + 0x01, + (USBD_STD_INQUIRY_LENGTH - 5), + 0x00, + 0x00, + 0x00, + 'G', 'D', '3', '2', ' ', ' ', ' ', ' ', /* Manufacturer : 8 bytes */ + 'I', 'n', 't', 'e', 'r', 'n', 'a', 'l', /* Product : 16 Bytes */ + ' ', 's', 'r', 'a', 'm', ' ', ' ', ' ', + '1', '.', '0' ,'0', /* Version : 4 Bytes */ +#else + /* LUN 0 */ + 0x00, + 0x80, + 0x00, + 0x01, + (USBD_STD_INQUIRY_LENGTH - 5), + 0x00, + 0x00, + 0x00, + 'G', 'D', '3', '2', ' ', ' ', ' ', ' ', /* Manufacturer : 8 bytes */ + 'I', 'n', 't', 'e', 'r', 'n', 'a', 'l', /* Product : 16 Bytes */ + ' ', 'f', 'l', 'a', 's', 'h', ' ', ' ', + '1', '.', '0' ,'0', /* Version : 4 Bytes */ +#endif +}; + +static int8_t STORAGE_Init (uint8_t Lun); +static int8_t STORAGE_IsReady (uint8_t Lun); +static int8_t STORAGE_IsWriteProtected (uint8_t Lun); +static int8_t STORAGE_GetMaxLun (void); + +static int8_t STORAGE_Read (uint8_t Lun, + uint8_t *buf, + uint32_t BlkAddr, + uint16_t BlkLen); + +static int8_t STORAGE_Write (uint8_t Lun, + uint8_t *buf, + uint32_t BlkAddr, + uint16_t BlkLen); + + +usbd_mem_cb USBD_Internal_Storage_fops = +{ + .mem_init = STORAGE_Init, + .mem_ready = STORAGE_IsReady, + .mem_protected = STORAGE_IsWriteProtected, + .mem_read = STORAGE_Read, + .mem_write = STORAGE_Write, + .mem_maxlun = STORAGE_GetMaxLun, + + .mem_inquiry_data = {(uint8_t *)STORAGE_InquiryData}, + +#ifdef SRAM_STORAGE + .mem_block_size = {ISRAM_BLOCK_SIZE}, + .mem_block_len = {ISRAM_BLOCK_NUM} +#else + .mem_block_size = {ISFLASH_BLOCK_SIZE}, + .mem_block_len = {ISFLASH_BLOCK_NUM} +#endif /* SRAM_STORAGE */ +}; + +usbd_mem_cb *usbd_mem_fops = &USBD_Internal_Storage_fops; + + +/** + * @brief Initialize the storage medium + * @param Lun: logical unit number + * @retval Status + */ +static int8_t STORAGE_Init (uint8_t Lun) +{ +#ifdef SRAM_STORAGE + +#else + flash_init (); +#endif + return 0; +} + +/** + * @brief Check whether the medium is ready + * @param Lun: Logical unit number + * @retval Status + */ +static int8_t STORAGE_IsReady (uint8_t Lun) +{ + return 0; +} + +/** + * @brief Check whether the medium is write-protected + * @param Lun: logical unit number + * @retval Status + */ +static int8_t STORAGE_IsWriteProtected (uint8_t Lun) +{ + return 0; +} + +/** + * @brief Read data from the medium + * @param Lun: logical unit number + * @param buf: pointer to the buffer to save data + * @param BlkAddr: address of 1st block to be read + * @param BlkLen: number of blocks to be read + * @retval Status + */ +static int8_t STORAGE_Read (uint8_t Lun, + uint8_t *buf, + uint32_t BlkAddr, + uint16_t BlkLen) +{ +#ifdef SRAM_STORAGE + if(SRAM_ReadMultiBlocks(buf, + BlkAddr, + ISRAM_BLOCK_SIZE, + BlkLen) != 0) + { + return 5; + } +#else + if(flash_multi_blocks_read (buf, + BlkAddr, + ISFLASH_BLOCK_SIZE, + BlkLen) != 0) + { + return 5; + } +#endif + return 0; +} + +/** + * @brief Write data to the medium + * @param Lun: logical unit number + * @param buf: pointer to the buffer to write + * @param BlkAddr: address of blocks to be written + * @param BlkLen: number of blocks to be read + * @retval Status + */ +static int8_t STORAGE_Write (uint8_t Lun, + uint8_t *buf, + uint32_t BlkAddr, + uint16_t BlkLen) +{ +#ifdef SRAM_STORAGE + if(SRAM_WriteMultiBlocks(buf, + BlkAddr, + ISRAM_BLOCK_SIZE, + BlkLen) != 0) + { + return 5; + } +#else + if(flash_multi_blocks_write (buf, + BlkAddr, + ISFLASH_BLOCK_SIZE, + BlkLen) != 0) + { + return 5; + } + +#endif + return (0); +} + +/** + * @brief Get number of supported logical unit + * @param None + * @retval Number of logical unit + */ +static int8_t STORAGE_GetMaxLun (void) +{ + return (MEM_LUN_NUM - 1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/readme.txt new file mode 100644 index 0000000..a15c91a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Device/MSC_Internal_flash/readme.txt @@ -0,0 +1,62 @@ +/*! + \file readme.txt + \brief description of the USB MSC device(Udisk) demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board,it provides a description of +how to use the USB device application based on the Mass Storage Class (MSC). + + The GD32 MCU is enumerated as a MSC device using the native PC Host MSC driver +to which the GD32VF103V-EVAL-V1.0 board is connected. + + It illustrates an implementation of the MSC class which uses the bulk transfer +while the internal sram is used as storage media. + + This example supports the BOT (bulk only transfer) protocol and all needed SCSI +(small computer system interface) commands, and is compatible with Windows platform. + + After running the example, the user just has to plug the USB cable into a PC host +and the device is automatically detected. One new removable drives appear in the +system window and write/read/format operations can be performed as with any other +removable drive. + + To select the appropriate USB Core to work with, user must add the following macro +defines within the compiler preprocessor (already done in the preconfigured projects +provided with this application): + - "USE_USB_FS" when using USB Full Speed (FS) Core + + In order to make the program work, you must do the following : + - Open your preferred toolchain + + - Rebuild all files and load your image into target memory + + - Run the application diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Eclipse/usbh_hid/.cproject b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Eclipse/usbh_hid/.cproject new file mode 100644 index 0000000..f03b2a3 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Eclipse/usbh_hid/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Eclipse/usbh_hid/.project b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Eclipse/usbh_hid/.project new file mode 100644 index 0000000..040e5aa --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Eclipse/usbh_hid/.project @@ -0,0 +1,678 @@ + + + usbh_hid + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Examples + 2 + virtual:/virtual + + + Firmware + 2 + virtual:/virtual + + + Utilities + 2 + virtual:/virtual + + + Examples/USBFS + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral + 2 + virtual:/virtual + + + Firmware/GD32VF103_usbfs_driver + 2 + virtual:/virtual + + + Firmware/RSICV + 2 + virtual:/virtual + + + Utilities/gd32vf103v_eval.c + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_eval.c + + + Utilities/gd32vf103v_eval.h + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_eval.h + + + Utilities/gd32vf103v_lcd_eval.c + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_lcd_eval.c + + + Utilities/gd32vf103v_lcd_eval.h + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_lcd_eval.h + + + Examples/USBFS/USB_Host + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Include + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Source + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/gd32vf103.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/gd32vf103.h + + + Firmware/GD32VF103_standard_peripheral/system_gd32vf103.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/system_gd32vf103.h + + + Firmware/GD32VF103_usbfs_driver/Include + 2 + virtual:/virtual + + + Firmware/GD32VF103_usbfs_driver/Source + 2 + virtual:/virtual + + + Firmware/RSICV/drivers + 2 + virtual:/virtual + + + Firmware/RSICV/env_Eclipse + 2 + virtual:/virtual + + + Firmware/RSICV/stubs + 2 + virtual:/virtual + + + Examples/USBFS/USB_Host/HID_Host + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h + 1 + 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PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c + 1 + 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PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_core.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_core.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_host.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_host.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_hw.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_hw.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_regs.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_regs.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usbh_int.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usbh_int.h + + + Firmware/GD32VF103_usbfs_driver/Include/usb_ch9_std.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usb_ch9_std.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbh_core.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbh_core.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbh_enum.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbh_enum.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbh_pipe.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbh_pipe.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbh_transc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbh_transc.h + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usb_core.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_core.c + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usb_host.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_host.c + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usbh_int.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usbh_int.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbh_core.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbh_core.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbh_enum.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbh_enum.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbh_pipe.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbh_pipe.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbh_transc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbh_transc.c + + + Firmware/RSICV/drivers/n200_eclic.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_eclic.h + + + Firmware/RSICV/drivers/n200_func.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_func.c + + + Firmware/RSICV/drivers/n200_func.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_func.h + + + Firmware/RSICV/drivers/n200_timer.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_timer.h + + + Firmware/RSICV/drivers/riscv_bits.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_bits.h + + + Firmware/RSICV/drivers/riscv_const.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_const.h + + + Firmware/RSICV/drivers/riscv_encoding.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_encoding.h + + + Firmware/RSICV/env_Eclipse/GD32VF103x4.lds + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/GD32VF103x4.lds + + + Firmware/RSICV/env_Eclipse/GD32VF103x6.lds + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/GD32VF103x6.lds + + + Firmware/RSICV/env_Eclipse/GD32VF103x8.lds + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/GD32VF103x8.lds + + + Firmware/RSICV/env_Eclipse/GD32VF103xB.lds + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/GD32VF103xB.lds + + + Firmware/RSICV/env_Eclipse/entry.S + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/entry.S + + + Firmware/RSICV/env_Eclipse/handlers.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/handlers.c + + + Firmware/RSICV/env_Eclipse/init.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/init.c + + + Firmware/RSICV/env_Eclipse/start.S + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/start.S + + + Firmware/RSICV/env_Eclipse/your_printf.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/your_printf.c + + + Firmware/RSICV/stubs/_exit.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/_exit.c + + + Firmware/RSICV/stubs/close.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/close.c + + + Firmware/RSICV/stubs/fstat.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/fstat.c + + + Firmware/RSICV/stubs/isatty.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/isatty.c + + + Firmware/RSICV/stubs/lseek.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/lseek.c + + + Firmware/RSICV/stubs/read.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/read.c + + + Firmware/RSICV/stubs/sbrk.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/sbrk.c + + + Firmware/RSICV/stubs/stub.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/stub.h + + + Firmware/RSICV/stubs/write.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/write.c + + + Firmware/RSICV/stubs/write_hex.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/write_hex.c + + + Examples/USBFS/USB_Host/HID_Host/Include + 2 + virtual:/virtual + + + Examples/USBFS/USB_Host/HID_Host/Source + 2 + virtual:/virtual + + + Examples/USBFS/USB_Host/HID_Host/Include/gd32vf103_it.h + 1 + PARENT-2-PROJECT_LOC/Include/gd32vf103_it.h + + + Examples/USBFS/USB_Host/HID_Host/Include/gd32vf103_libopt.h + 1 + PARENT-2-PROJECT_LOC/Include/gd32vf103_libopt.h + + + Examples/USBFS/USB_Host/HID_Host/Include/lcd_font.h + 1 + PARENT-2-PROJECT_LOC/Include/lcd_font.h + + + Examples/USBFS/USB_Host/HID_Host/Include/lcd_log.h + 1 + PARENT-2-PROJECT_LOC/Include/lcd_log.h + + + Examples/USBFS/USB_Host/HID_Host/Include/usb_conf.h + 1 + PARENT-2-PROJECT_LOC/Include/usb_conf.h + + + Examples/USBFS/USB_Host/HID_Host/Include/usb_hid.h + 1 + PARENT-2-PROJECT_LOC/Include/usb_hid.h + + + Examples/USBFS/USB_Host/HID_Host/Include/usbh_conf.h + 1 + PARENT-2-PROJECT_LOC/Include/usbh_conf.h + + + Examples/USBFS/USB_Host/HID_Host/Include/usbh_hid_core.h + 1 + PARENT-2-PROJECT_LOC/Include/usbh_hid_core.h + + + Examples/USBFS/USB_Host/HID_Host/Include/usbh_hid_keybd.h + 1 + PARENT-2-PROJECT_LOC/Include/usbh_hid_keybd.h + + + Examples/USBFS/USB_Host/HID_Host/Include/usbh_hid_mouse.h + 1 + PARENT-2-PROJECT_LOC/Include/usbh_hid_mouse.h + + + Examples/USBFS/USB_Host/HID_Host/Include/usbh_usr.h + 1 + PARENT-2-PROJECT_LOC/Include/usbh_usr.h + + + Examples/USBFS/USB_Host/HID_Host/Source/app.c + 1 + PARENT-2-PROJECT_LOC/Source/app.c + + + Examples/USBFS/USB_Host/HID_Host/Source/gd32vf103_it.c + 1 + PARENT-2-PROJECT_LOC/Source/gd32vf103_it.c + + + Examples/USBFS/USB_Host/HID_Host/Source/gd32vf103_usb_hw.c + 1 + PARENT-2-PROJECT_LOC/Source/gd32vf103_usb_hw.c + + + Examples/USBFS/USB_Host/HID_Host/Source/lcd_font.c + 1 + PARENT-2-PROJECT_LOC/Source/lcd_font.c + + + Examples/USBFS/USB_Host/HID_Host/Source/lcd_log.c + 1 + PARENT-2-PROJECT_LOC/Source/lcd_log.c + + + Examples/USBFS/USB_Host/HID_Host/Source/system_gd32vf103.c + 1 + PARENT-2-PROJECT_LOC/Source/system_gd32vf103.c + + + Examples/USBFS/USB_Host/HID_Host/Source/usbh_hid_core.c + 1 + PARENT-2-PROJECT_LOC/Source/usbh_hid_core.c + + + Examples/USBFS/USB_Host/HID_Host/Source/usbh_hid_keybd.c + 1 + PARENT-2-PROJECT_LOC/Source/usbh_hid_keybd.c + + + Examples/USBFS/USB_Host/HID_Host/Source/usbh_hid_mouse.c + 1 + PARENT-2-PROJECT_LOC/Source/usbh_hid_mouse.c + + + Examples/USBFS/USB_Host/HID_Host/Source/usbh_usr.c + 1 + PARENT-2-PROJECT_LOC/Source/usbh_usr.c + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Eclipse/usbh_hid/.settings/language.settings.xml b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Eclipse/usbh_hid/.settings/language.settings.xml new file mode 100644 index 0000000..c6c3708 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Eclipse/usbh_hid/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/gd32vf103_it.h new file mode 100644 index 0000000..91215b6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/gd32vf103_it.h @@ -0,0 +1,46 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ +/* this function handles USB wakeup interrupt handler */ +void USBFS_WKUP_IRQHandler(void); +/* this function handles USBFS IRQ Handler */ +void USBFS_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/lcd_font.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/lcd_font.h new file mode 100644 index 0000000..f70a41c --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/lcd_font.h @@ -0,0 +1,44 @@ +/*! + \file lcd_font.h + \brief the header file of LCD font + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef LCD_FONT_H +#define LCD_FONT_H + +#include + +extern unsigned char const ascii_8x16[1536]; + +extern const uint16_t ASCII_Table_16x24[]; + +#endif /* LCD_FONT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/lcd_log.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/lcd_log.h new file mode 100644 index 0000000..4f1fa8f --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/lcd_log.h @@ -0,0 +1,52 @@ +/*! + \file lcd_log.h + \brief the header file of LCD log + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "stdint.h" +#include "lcd_font.h" + +/* initialize the LCD log module */ +void lcd_log_init (void); +/* de-initialize the LCD log module */ +void lcd_log_deinit (void); +/* display the application header (title) on the LCD screen */ +void lcd_log_header_set (uint8_t *p_title, uint16_t start_x); +/* display the application footer (status) on the LCD screen */ +void lcd_log_footer_set (uint8_t *p_status, uint16_t start_x); +/* redirect the printf to the lcd */ +void lcd_log_print (uint8_t *p_str, uint16_t offset, uint16_t char_color); +/* clear the text zone */ +void lcd_log_text_zone_clear (uint16_t start_x, + uint16_t start_y, + uint16_t width, + uint16_t height); diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usb_conf.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usb_conf.h new file mode 100644 index 0000000..04d2c46 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usb_conf.h @@ -0,0 +1,93 @@ +/*! + \file usb_conf.h + \brief general low level driver configuration + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_CONF_H +#define __USB_CONF_H + + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" +#include "gd32vf103v_lcd_eval.h" + +#include + +#ifdef USE_USB_FS + #define USB_FS_CORE +#endif + +#ifdef USB_FS_CORE + #define USB_RX_FIFO_FS_SIZE 128 + #define USB_HTX_NPFIFO_FS_SIZE 96 + #define USB_HTX_PFIFO_FS_SIZE 96 +#endif + +#define USB_SOF_OUTPUT 0 +#define USB_LOW_POWER 0 + +#define USE_HOST_MODE +//#define USE_DEVICE_MODE +//#define USE_OTG_MODE + +#ifndef USB_FS_CORE + #ifndef USB_HS_CORE + #error "USB_HS_CORE or USB_FS_CORE should be defined" + #endif +#endif + +#ifndef USE_DEVICE_MODE + #ifndef USE_HOST_MODE + #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" + #endif +#endif + +#ifndef USE_USB_HS + #ifndef USE_USB_FS + #error "USE_USB_HS or USE_USB_FS should be defined" + #endif +#endif + +/****************** C Compilers dependant keywords ****************************/ +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined (__GNUC__) /* GNU Compiler */ + #define __ALIGN_END __attribute__ ((aligned(4))) + #define __ALIGN_BEGIN + #endif /* __GNUC__ */ +#else + #define __ALIGN_BEGIN + #define __ALIGN_END +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + +#endif /* __USB_CONF_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usb_hid.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usb_hid.h new file mode 100644 index 0000000..c105cf5 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usb_hid.h @@ -0,0 +1,83 @@ +/*! + \file usb_hid.h + \brief definitions for the USB HID class + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_HID_H +#define __USB_HID_H + +#include "usb_ch9_std.h" + +#define USB_HID_CLASS 0x03U + +#define USB_DESCTYPE_HID 0x21U +#define USB_DESCTYPE_REPORT 0x22U + +/* HID subclass code */ +#define USB_HID_SUBCLASS_BOOT_ITF 0x01U + +/* HID protocol codes */ +#define USB_HID_PROTOCOL_KEYBOARD 0x01U +#define USB_HID_PROTOCOL_MOUSE 0x02U + +#define GET_REPORT 0x01U +#define GET_IDLE 0x02U +#define GET_PROTOCOL 0x03U +#define SET_REPORT 0x09U +#define SET_IDLE 0x0AU +#define SET_PROTOCOL 0x0BU + +#pragma pack(1) + +typedef struct +{ + usb_desc_header header; /*!< regular descriptor header containing the descriptor's type and length */ + + uint16_t bcdHID; /*!< BCD encoded version that the HID descriptor and device complies to */ + uint8_t bCountryCode; /*!< country code of the localized device, or zero if universal */ + uint8_t bNumDescriptors; /*!< total number of HID report descriptors for the interface */ + uint8_t bDescriptorType; /*!< type of HID report */ + uint16_t wDescriptorLength; /*!< length of the associated HID report descriptor, in bytes */ +} usb_desc_hid; + +#pragma pack() + +typedef struct +{ + usb_desc_config config; + usb_desc_itf hid_itf; + usb_desc_hid hid_vendor; + usb_desc_ep hid_epin; + usb_desc_ep hid_epout; +}usb_hid_desc_config_set; + +#endif /* __USB_HID_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usbh_conf.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usbh_conf.h new file mode 100644 index 0000000..ae12fd4 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usbh_conf.h @@ -0,0 +1,42 @@ +/*! + \file usbh_conf.h + \brief general low level driver configuration + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_CONF_H +#define __USBH_CONF_H + +#define USBH_MAX_EP_NUM 2 +#define USBH_MAX_INTERFACES_NUM 2 +#define USBH_MSC_MPS_SIZE 0x200 + +#endif /* __USBH_CONF_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usbh_hid_core.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usbh_hid_core.h new file mode 100644 index 0000000..ed0854b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usbh_hid_core.h @@ -0,0 +1,126 @@ +/*! + \file usbh_hid_core.h + \brief header file for usbh_hid_core.c + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_HID_CORE_H +#define __USBH_HID_CORE_H + +#include "usb_hid.h" +#include "usbh_enum.h" +#include "usbh_transc.h" + +#define HID_MIN_POLL 10U + +#define USB_HID_DESC_SIZE 9U + +/* States for HID State Machine */ +typedef enum { + HID_IDLE = 0U, + HID_SEND_DATA, + HID_BUSY, + HID_GET_DATA, + HID_SYNC, + HID_POLL, + HID_ERROR, +}hid_state; + +typedef enum { + HID_REQ_IDLE = 0U, + HID_REQ_GET_REPORT_DESC, + HID_REQ_GET_HID_DESC, + HID_REQ_SET_IDLE, + HID_REQ_SET_PROTOCOL, + HID_REQ_SET_REPORT, +}hid_ctlstate; + +typedef struct +{ + void (*Init) (void); + void (*Decode) (uint8_t *data); +}hid_proc; + +typedef struct +{ + uint8_t ReportID; + uint8_t ReportType; + uint16_t UsagePage; + uint32_t Usage[2]; + uint32_t NbrUsage; + uint32_t UsageMin; + uint32_t UsageMax; + int32_t LogMin; + int32_t LogMax; + int32_t PhyMin; + int32_t PhyMax; + int32_t UnitExp; + uint32_t Unit; + uint32_t ReportSize; + uint32_t ReportCnt; + uint32_t Flag; + uint32_t PhyUsage; + uint32_t AppUsage; + uint32_t LogUsage; +}usb_desc_report; + +/* structure for HID process */ +typedef struct +{ + uint8_t buf[64]; + + uint8_t pipe_in; + uint8_t pipe_out; + + uint8_t ep_addr; + uint8_t ep_out; + uint8_t ep_in; + + uint16_t len; + uint16_t poll; + + __IO uint16_t timer; + + hid_state state; + hid_ctlstate ctlstate; + hid_proc *proc; +}hid_machine_struct; + +extern usbh_class_cb usbh_hid_cb; + +usbh_status usbh_set_report (usb_core_driver *pudev, + usbh_host *phost, + uint8_t report_type, + uint8_t report_id, + uint8_t report_len, + uint8_t *report_buff); + +#endif /* __USBH_HID_CORE_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usbh_hid_keybd.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usbh_hid_keybd.h new file mode 100644 index 0000000..4fb808c --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usbh_hid_keybd.h @@ -0,0 +1,63 @@ +/*! + \file usbh_hid_keybd.h + \brief this file contains all the prototypes for the usbh_hid_keybd.c + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBH_HID_KEYBD_H +#define USBH_HID_KEYBD_H + +#include "usb_conf.h" +#include "usbh_hid_core.h" + +//#define AZERTY_KEYBOARD +#define QWERTY_KEYBOARD + +#define KBD_LEFT_CTRL 0x01U +#define KBD_LEFT_SHIFT 0x02U +#define KBD_LEFT_ALT 0x04U +#define KBD_LEFT_GUI 0x08U +#define KBD_RIGHT_CTRL 0x10U +#define KBD_RIGHT_SHIFT 0x20U +#define KBD_RIGHT_ALT 0x40U +#define KBD_RIGHT_GUI 0x80U + +#define KBR_MAX_NBR_PRESSED 6U + +extern hid_proc HID_KEYBRD_cb; + +/* function declarations */ +/* init keyboard window */ +void usr_keybrd_init (void); +/* process keyboard data */ +void usr_keybrd_process_data (uint8_t pbuf); + +#endif /* USBH_HID_KEYBD_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usbh_hid_mouse.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usbh_hid_mouse.h new file mode 100644 index 0000000..f41ce83 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usbh_hid_mouse.h @@ -0,0 +1,79 @@ +/*! + \file usbh_hid_mouse.h + \brief this file contains all the prototypes for the usbh_hid_mouse.c + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBH_HID_MOUSE_H +#define USBH_HID_MOUSE_H + +#include "usbh_hid_core.h" + +/* Left Button: Report data: 0x00*/ +#define HID_MOUSE_LEFTBUTTON 0x00 + +/* Right Button: Report data: 0x01*/ +#define HID_MOUSE_RIGHTBUTTON 0x01 + +/* Middle Button: Report data: 0x02*/ +#define HID_MOUSE_MIDDLEBUTTON 0x02 + +#define MOUSE_WINDOW_X 190 +#define MOUSE_WINDOW_Y 40 +#define MOUSE_WINDOW_X_MAX 181 +#define MOUSE_WINDOW_Y_MIN 101 +#define MOUSE_WINDOW_HEIGHT 110 +#define MOUSE_WINDOW_WIDTH 240 + +typedef struct +{ + uint8_t x; + uint8_t y; + uint8_t z; /* not supported */ + uint8_t button; +}hid_mouse_data_struct; + +extern hid_proc hid_mouse_cb; +extern hid_mouse_data_struct hid_mouse_data; + +/* function declarations */ +/* init mouse window */ +void usr_mouse_init (void); +/* process mouse data */ +void usr_mouse_process_data (hid_mouse_data_struct *data); + +void hid_mouse_update_position (int8_t X, int8_t Y); + +void hid_mouse_button_released (uint8_t ButtonIdx); + +void hid_mouse_button_pressed (uint8_t ButtonIdx); + +#endif /* USBH_HID_MOUSE_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usbh_usr.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usbh_usr.h new file mode 100644 index 0000000..8f11561 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Include/usbh_usr.h @@ -0,0 +1,83 @@ +/*! + \file usbh_usr.h + \brief user application layer header file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBH_USR_H +#define USBH_USR_H + +#include "usbh_core.h" +#include "usbh_hid_core.h" +#include "usb_conf.h" +#include + +extern usbh_user_cb user_callback_funs; + +/* function declarations */ +/* user operation for host-mode initialization */ +void usbh_user_init (void); +/* de-int user state and associated variables */ +void usbh_user_deinit (void); +/* user operation for device attached */ +void usbh_user_device_connected (void); +/* user operation for reset USB Device */ +void usbh_user_device_reset (void); +/* user operation for device disconnect event */ +void usbh_user_device_disconnected (void); +/* user operation for device overcurrent detection event */ +void usbh_user_over_current_detected (void); +/* user operation for detectting device speed */ +void usbh_user_device_speed_detected (uint32_t DeviceSpeed); +/* user operation when device descriptor is available */ +void usbh_user_device_descavailable (void *dev_desc); +/* USB device is successfully assigned the address */ +void usbh_user_device_address_assigned (void); +/* user operation when configuration descriptor is available */ +void usbh_user_configuration_descavailable (usb_desc_config *cfgDesc, + usb_desc_itf *itfDesc, + usb_desc_ep *epDesc); +/* user operation when manufacturer string exists */ +void usbh_user_manufacturer_string (void *mfc_string); +/* user operation when product string exists */ +void usbh_user_product_string (void *prod_string); +/* user operatin when serialNum string exists */ +void usbh_user_serialnum_string (void *serialnum_string); +/* user response request is displayed to ask for application jump to class */ +void usbh_user_enumeration_finish (void); +/* user action for application state entry */ +usbh_user_status usbh_user_userinput (void); +/* user operation when device is not supported */ +void usbh_user_device_not_supported (void); +/* user operation when unrecoveredError happens */ +void usbh_user_unrecovered_error (void); + +#endif /* USBH_USR_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/app.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/app.c new file mode 100644 index 0000000..2b52137 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/app.c @@ -0,0 +1,79 @@ +/*! + \file main.c + \brief this file realizes the HID host + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "drv_usb_core.h" +#include "usbh_usr.h" +#include "usbh_hid_core.h" +#include "gd32vf103v_eval.h" +#include +#include +#include + + +usb_core_driver usb_hid_core; + +usbh_host usb_host = { + .class_cb = &usbh_hid_cb, + .usr_cb = &user_callback_funs +}; + +/** + * @brief Main routine for HID mouse / keyboard class application + * @param None + * @retval None + */ +int main(void) +{ + eclic_global_interrupt_enable(); + + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL2_PRIO2); + + usb_rcu_config(); + + usb_timer_init(); + + /* configure GPIO pin used for switching VBUS power and charge pump I/O */ + usb_vbus_config(); + + usbh_init (&usb_hid_core, USB_CORE_ENUM_FS, &usb_host); + + /* enable interrupts */ + usb_intr_config(); + + while (1) { + /* Host state handler */ + usbh_core_task (&usb_hid_core, &usb_host); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/gd32vf103_it.c new file mode 100644 index 0000000..1de19df --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/gd32vf103_it.c @@ -0,0 +1,63 @@ +/*! + \file gd32vf103_it.c + \brief main interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usbh_int.h" +#include "drv_usb_hw.h" +#include "gd32vf103_it.h" + +extern usb_core_driver usb_hid_core; + +extern void usb_timer_irq (void); + +/*! + \brief this function handles USBD interrupt + \param[in] none + \param[out] none + \retval none +*/ +void USBFS_IRQHandler (void) +{ + usbh_isr (&usb_hid_core); +} + +/*! + \brief this function handles timer2 updata interrupt request. + \param[in] none + \param[out] none + \retval none +*/ +void TIMER2_IRQHandler(void) +{ + usb_timer_irq(); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/gd32vf103_usb_hw.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/gd32vf103_usb_hw.c new file mode 100644 index 0000000..7e5c736 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/gd32vf103_usb_hw.c @@ -0,0 +1,259 @@ +/*! + \file gd32vf103_usb_hw.c + \brief this file implements the board support package for the USB host library + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include +#include +#include + + +#define TIM_MSEC_DELAY 0x01 +#define TIM_USEC_DELAY 0x02 + +#define HOST_POWERSW_PORT_RCC RCU_GPIOD +#define HOST_POWERSW_PORT GPIOD +#define HOST_POWERSW_VBUS GPIO_PIN_13 + +__IO uint32_t delay_time = 0; +__IO uint32_t usbfs_prescaler = 0; +__IO uint32_t timer_prescaler = 5; + +static void hwp_time_set (uint8_t unit); +static void hwp_delay (uint32_t ntime, uint8_t unit); + +/*! + \brief configure USB clock + \param[in] none + \param[out] none + \retval none +*/ +void usb_rcu_config (void) +{ + uint32_t system_clock = rcu_clock_freq_get(CK_SYS); + + if (system_clock == 48000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1; + timer_prescaler = 3; + } else if (system_clock == 72000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1_5; + timer_prescaler = 5; + } else if (system_clock == 96000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV2; + timer_prescaler = 7; + } else { + /* reserved */ + } + + rcu_usb_clock_config(usbfs_prescaler); + rcu_periph_clock_enable(RCU_USBFS); +} + +/*! + \brief configure USB global interrupt + \param[in] none + \param[out] none + \retval none +*/ +void usb_intr_config (void) +{ + eclic_irq_enable((uint8_t)USBFS_IRQn, 1, 0); + +#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT + + /* enable the power module clock */ + rcu_periph_clock_enable(RCU_PMU); + + /* USB wakeup EXTI line configuration */ + exti_interrupt_flag_clear(EXTI_18); + exti_init(EXTI_18, EXTI_INTERRUPT, EXTI_TRIG_RISING); + exti_interrupt_enable(EXTI_18); + + eclic_irq_enable((uint8_t)USBFS_WKUP_IRQn, 3U, 0U); + +#endif /* USBHS_LOW_PWR_MGMT_SUPPORT */ +} + +/*! + \brief drives the VBUS signal through gpio + \param[in] state: VBUS states + \param[out] none + \retval none +*/ +void usb_vbus_drive (uint8_t state) +{ + if (0 == state) + { + /* DISABLE is needed on output of the Power Switch */ + gpio_bit_reset(HOST_POWERSW_PORT, HOST_POWERSW_VBUS); + } + else + { + /*ENABLE the Power Switch by driving the Enable LOW */ + gpio_bit_set(HOST_POWERSW_PORT, HOST_POWERSW_VBUS); + } +} + +/*! + \brief configures the GPIO for the VBUS + \param[in] none + \param[out] none + \retval none +*/ +void usb_vbus_config (void) +{ + rcu_periph_clock_enable(HOST_POWERSW_PORT_RCC); + + gpio_init(HOST_POWERSW_PORT, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, HOST_POWERSW_VBUS); + + /* by default, disable is needed on output of the power switch */ + gpio_bit_set(HOST_POWERSW_PORT, HOST_POWERSW_VBUS); + + /* Delay is need for stabilising the Vbus Low in Reset Condition, + * when Vbus=1 and Reset-button is pressed by user + */ + //usb_mdelay (1); + usb_mdelay (2); +} + +/*! + \brief initializes delay unit using Timer2 + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_init (void) +{ + rcu_periph_clock_enable(RCU_TIMER2); + + eclic_irq_enable(TIMER2_IRQn, 2, 0); +} + +/*! + \brief delay in micro seconds + \param[in] usec: value of delay required in micro seconds + \param[out] none + \retval none +*/ +void usb_udelay (const uint32_t usec) +{ + hwp_delay(usec, TIM_USEC_DELAY); +} + +/*! + \brief delay in milli seconds + \param[in] msec: value of delay required in milli seconds + \param[out] none + \retval none +*/ +void usb_mdelay (const uint32_t msec) +{ + hwp_delay(msec, TIM_MSEC_DELAY); +} + +/*! + \brief timer base IRQ + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_irq (void) +{ + if (timer_interrupt_flag_get(TIMER2, TIMER_INT_UP) != RESET){ + timer_interrupt_flag_clear(TIMER2, TIMER_INT_UP); + + if (delay_time > 0x00U){ + delay_time--; + } else { + timer_disable(TIMER2); + } + } +} + +/*! + \brief delay routine based on TIM2 + \param[in] ntime: delay Time + \param[in] unit: delay Time unit = mili sec / micro sec + \param[out] none + \retval none +*/ +static void hwp_delay(uint32_t ntime, uint8_t unit) +{ + delay_time = ntime; + hwp_time_set(unit); + + while(delay_time != 0); + + timer_disable(TIMER2); +} + +/*! + \brief configures TIM2 for delay routine based on TIM2 + \param[in] unit: msec /usec + \param[out] none + \retval none +*/ +static void hwp_time_set(uint8_t unit) +{ + timer_parameter_struct timer_basestructure; + + timer_disable(TIMER2); + timer_interrupt_disable(TIMER2, TIMER_INT_UP); + + if (unit == TIM_USEC_DELAY) { + timer_basestructure.period = 11; + } else if(unit == TIM_MSEC_DELAY) { + timer_basestructure.period = 11999; + } else { + /* no operation */ + } + + timer_basestructure.prescaler = timer_prescaler; + timer_basestructure.alignedmode = TIMER_COUNTER_EDGE; + timer_basestructure.counterdirection = TIMER_COUNTER_UP; + timer_basestructure.clockdivision = TIMER_CKDIV_DIV1; + timer_basestructure.repetitioncounter = 0; + + timer_init(TIMER2, &timer_basestructure); + + timer_interrupt_flag_clear(TIMER2, TIMER_INT_UP); + + timer_auto_reload_shadow_enable(TIMER2); + + /* timer2 interrupt enable */ + timer_interrupt_enable(TIMER2, TIMER_INT_UP); + + /* timer2 enable counter */ + timer_enable(TIMER2); +} + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/lcd_font.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/lcd_font.c new file mode 100644 index 0000000..b53596c --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/lcd_font.c @@ -0,0 +1,711 @@ +/*! + \file lcd_font.c + \brief text fonts driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "lcd_font.h" + +unsigned char const ascii_8x16[1536] = { +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x18,0x3C,0x3C,0x3C,0x18,0x18,0x18,0x00,0x18,0x18,0x00,0x00,0x00,0x00, +0x00,0x66,0x66,0x66,0x24,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x6C,0x6C,0xFE,0x6C,0x6C,0x6C,0xFE,0x6C,0x6C,0x00,0x00,0x00,0x00, +0x18,0x18,0x7C,0xC6,0xC2,0xC0,0x7C,0x06,0x86,0xC6,0x7C,0x18,0x18,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0xC2,0xC6,0x0C,0x18,0x30,0x60,0xC6,0x86,0x00,0x00,0x00,0x00, +0x00,0x00,0x38,0x6C,0x6C,0x38,0x76,0xDC,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00, +0x00,0x30,0x30,0x30,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x0C,0x18,0x30,0x30,0x30,0x30,0x30,0x30,0x18,0x0C,0x00,0x00,0x00,0x00, +0x00,0x00,0x30,0x18,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x18,0x30,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x66,0x3C,0xFF,0x3C,0x66,0x00,0x00,0x00,0x00,0x00,0x00, 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+0x00,0x00,0x00,0x00,0x10,0x38,0x6C,0xC6,0xC6,0xC6,0xFE,0x00,0x00,0x00,0x00,0x00 +}; + + + +/* ASCII Table: each character is 16 column (16dots large) and 24 raw (24 dots high) */ +const uint16_t ASCII_Table_16x24[] = +{ +/** + * @brief Space ' ' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '!' + */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '"' + */ + 0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '#' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60, + 0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318, + 0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000, +/** + * @brief '$' + */ + 0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C, + 0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C, + 0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000, +/** + * @brief '%' + */ + 0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611, + 0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460, + 0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000, +/** + * @brief '&' + */ + 0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0, + 0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06, + 0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ''' + */ + 0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '(' + */ + 0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060, + 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, + 0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000, +/** + * @brief ')' + */ + 0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300, + 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, + 0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000, +/** + * @brief '*' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '+' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ',' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, +/** + * @brief '-' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '.' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '/' + */ + 0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300, + 0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0, + 0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '0' + */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C, + 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '1' + */ + 0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '2' + */ + 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800, + 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, + 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '3' + */ + 0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600, + 0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18, + 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '4' + */ + 0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60, + 0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00, + 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '5' + */ + 0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC, + 0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18, + 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '6' + */ + 0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC, + 0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '7' + */ + 0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380, + 0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030, + 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '8' + */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638, + 0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38, + 0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '9' + */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C, + 0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C, + 0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ':' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ';' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000, +/** + * @brief '<' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0, + 0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '=' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '>' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0, + 0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '?' + */ + 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00, + 0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '@' + */ + 0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411, + 0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004, + 0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'A' + */ + 0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60, + 0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C, + 0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'B' + */ + 0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C, + 0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C, + 0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'C' + */ + 0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006, + 0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C, + 0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'D' + */ + 0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006, + 0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06, + 0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'E' + */ + 0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'F' + */ + 0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'G' + */ + 0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003, + 0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C, + 0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'H' + */ + 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'I' + */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'J' + */ + 0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, + 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738, + 0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'K' + */ + 0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6, + 0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806, + 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'L' + */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'M' + */ + 0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836, + 0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6, + 0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'N' + */ + 0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC, + 0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C, + 0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'O' + */ + 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003, + 0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C, + 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'P' + */ + 0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'Q' + */ + 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003, + 0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C, + 0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'R' + */ + 0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806, + 0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006, + 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'S' + */ + 0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C, + 0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C, + 0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'T' + */ + 0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'U' + */ + 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818, + 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'V' + */ + 0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C, + 0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360, + 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'W' + */ + 0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366, + 0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C, + 0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'X' + */ + 0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0, + 0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C, + 0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'Y' + */ + 0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660, + 0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'Z' + */ + 0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600, + 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006, + 0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '[' + */ + 0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, + 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, + 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000, +/** + * @brief '\' + */ + 0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0, + 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300, + 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ']' + */ + 0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, + 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, + 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000, +/** + * @brief '^' + */ + 0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630, + 0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '_' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ''' + */ + 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'a' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8, + 0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C, + 0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'b' + */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8, + 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38, + 0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'c' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0, + 0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30, + 0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'd' + */ + 0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0, + 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30, + 0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'e' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0, + 0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30, + 0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'f' + */ + 0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'g' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8, + 0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18, + 0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000, +/** + * @brief 'h' + */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8, + 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, + 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'i' + */ + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'j' + */ + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000, +/** + * @brief 'k' + */ + 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C, + 0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C, + 0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'l' + */ + 0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'm' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF, + 0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, + 0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'n' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8, + 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, + 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'o' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0, + 0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30, + 0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'p' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8, + 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38, + 0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000, +/** + * @brief 'q' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0, + 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30, + 0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000, +/** + * @brief 'r' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0, + 0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, + 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 's' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0, + 0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 't' + */ + 0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'u' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818, + 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38, + 0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'v' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18, + 0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360, + 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'w' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1, + 0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C, + 0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'x' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38, + 0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30, + 0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'y' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830, + 0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380, + 0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000, +/** + * @brief 'z' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC, + 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, + 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '{' + */ + 0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000, +/** + * @brief '|' + */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, +/** + * @brief '}' + */ + 0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000, +/** + * @brief '~' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +}; diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/lcd_log.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/lcd_log.c new file mode 100644 index 0000000..9a344a0 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/lcd_log.c @@ -0,0 +1,168 @@ +/*! + \file lcd_log.c + \brief LCD log driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "lcd_log.h" +#include "string.h" + +#include "gd32vf103v_lcd_eval.h" + +uint16_t LINE; + +char_format_struct charform = { + .font = CHAR_FONT_8_16, + .direction = CHAR_DIRECTION_HORIZONTAL, + .char_color = LCD_COLOR_RED, + .bk_color = LCD_COLOR_BLACK +}; + +/*! + \brief initialize the LCD log module + \param[in] none + \param[out] none + \retval none +*/ +void lcd_log_init (void) +{ + lcd_clear(LCD_COLOR_BLACK); +} + +/*! + \brief de-initialize the LCD log module + \param[in] none + \param[out] none + \retval none +*/ +void lcd_log_deinit (void) +{ +} + +/*! + \brief display the application header (title) on the LCD screen + \param[in] p_title: pointer to the string to be displayed + \param[in] start_x: the start x position + \param[out] none + \retval none +*/ +void lcd_log_header_set (uint8_t *p_title, uint16_t start_x) +{ + uint16_t i = 0; + uint16_t str_len = strlen((const char *)p_title); + + lcd_rectangle_fill(210, 0, 240, 320, LCD_COLOR_BLUE); + + charform.bk_color = LCD_COLOR_BLUE; + + for (i = 0; i < str_len; i++) { + lcd_char_display (230, (start_x + 8 * i), p_title[i], charform); + } + +} + +/*! + \brief display the application footer (status) on the LCD screen + \param[in] p_status: pointer to the string to be displayed + \param[in] start_x: the start x position + \param[out] none + \retval none +*/ +void lcd_log_footer_set (uint8_t *p_status, uint16_t start_x) +{ + uint16_t i = 0; + uint16_t str_len = strlen((const char *)p_status); + + lcd_rectangle_fill(0, 0, 30, 320, LCD_COLOR_BLUE); + + + charform.bk_color = LCD_COLOR_BLUE; + + for (i = 0; i < str_len; i++) { + lcd_char_display (20, (start_x + 8 * i), p_status[i], charform); + } + +} + +/*! + \brief clear the text zone + \param[in] start_x: the start x position + \param[in] start_y: the start y position + \param[in] width: the width to clear text zone + \param[in] height: the heitht to clear text zone + \param[out] none + \retval none +*/ +void lcd_log_text_zone_clear(uint16_t start_x, + uint16_t start_y, + uint16_t width, + uint16_t height) +{ + lcd_rectangle_fill(start_x, start_y, width, height, LCD_COLOR_BLACK); +} + +/*! + \brief redirect the printf to the lcd + \param[in] p_str: pointer to string to be displayed + \param[in] offset: the offset to set + \param[in] char_color: the clar color to set + \param[out] none + \retval none +*/ +void lcd_log_print (uint8_t *p_str, uint16_t offset, uint16_t char_color) +{ + uint16_t i; + +#if defined(USE_HOST_MODE) && defined(USE_DEVICE_MODE) + if(LINE <= 60) + { + LINE = 190; + + lcd_rectangle_fill(60, 0, 210, 320, BLACK); + } +#else + if(LINE <= 30) + { + LINE = 190; + + lcd_rectangle_fill(30, 0, 210, 320, LCD_COLOR_BLACK); + } +#endif + + charform.bk_color = LCD_COLOR_BLACK; + charform.char_color = char_color; + + for (i = 0; i < offset; i++) { + lcd_char_display(LINE, (10 + 8 * i), *p_str++, charform); + } + + LINE -= 20; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/system_gd32vf103.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/system_gd32vf103.c new file mode 100644 index 0000000..05e5205 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/system_gd32vf103.c @@ -0,0 +1,998 @@ +/*! + \file system_gd32vf103.h + \brief RISC-V Device Peripheral Access Layer Source File for + GD32VF103 Device Series + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32vf103.h" + +/* system frequency define */ +#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ + +/* select a system clock by uncommenting the following line */ +/* use IRC8M */ +//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000) + +/********************************************************************/ +//#define __SYSTEM_CLOCK_HXTAL (HXTAL_VALUE) +//#define __SYSTEM_CLOCK_24M_PLL_HXTAL (uint32_t)(24000000) +/********************************************************************/ + +//#define __SYSTEM_CLOCK_36M_PLL_HXTAL (uint32_t)(36000000) +//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_56M_PLL_HXTAL (uint32_t)(56000000) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000) +//#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) + +#define SEL_IRC8M 0x00U +#define SEL_HXTAL 0x01U +#define SEL_PLL 0x02U + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_48M_PLL_IRC8M +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M; +static void system_clock_48m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M; +static void system_clock_72m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M; +static void system_clock_108m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; +static void system_clock_hxtal(void); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_24M_PLL_HXTAL; +static void system_clock_24m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_36M_PLL_HXTAL; +static void system_clock_36m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL; +static void system_clock_48m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_56M_PLL_HXTAL; +static void system_clock_56m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; +static void system_clock_72m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL; +static void system_clock_96m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; +static void system_clock_108m_hxtal(void); +#else +uint32_t SystemCoreClock = IRC8M_VALUE; +#endif /* __SYSTEM_CLOCK_48M_PLL_IRC8M */ + +/* configure the system clock */ +static void system_clock_config(void); + +/*! + \brief configure the system clock + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_config(void) +{ +#ifdef __SYSTEM_CLOCK_HXTAL + system_clock_hxtal(); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) + system_clock_24m_hxtal(); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) + system_clock_36m_hxtal(); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) + system_clock_48m_hxtal(); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) + system_clock_56m_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) + system_clock_72m_hxtal(); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) + system_clock_96m_hxtal(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) + system_clock_108m_hxtal(); + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) + system_clock_48m_irc8m(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) + system_clock_72m_irc8m(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) + system_clock_108m_irc8m(); +#endif /* __SYSTEM_CLOCK_HXTAL */ +} + +/*! + \brief setup the microcontroller system, initialize the system + \param[in] none + \param[out] none + \retval none +*/ +void SystemInit(void) +{ + /* reset the RCC clock configuration to the default reset state */ + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL); + + /* reset HXTALEN, CKMEN, PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); + + /* Reset HXTALBPS bit */ + RCU_CTL &= ~(RCU_CTL_HXTALBPS); + + /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */ + + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | + RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4); + RCU_CFG1 = 0x00000000U; + + /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + /* disable all interrupts */ + RCU_INT = 0x00FF0000U; + + /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ + system_clock_config(); +} + +/*! + \brief update the SystemCoreClock with current core clock retrieved from cpu registers + \param[in] none + \param[out] none + \retval none +*/ +void SystemCoreClockUpdate(void) +{ + uint32_t scss; + uint32_t pllsel, predv0sel, pllmf, ck_src; + uint32_t predv0, predv1, pll1mf; + + scss = GET_BITS(RCU_CFG0, 2, 3); + + switch (scss) + { + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + SystemCoreClock = IRC8M_VALUE; + break; + + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + SystemCoreClock = HXTAL_VALUE; + break; + + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + + + if(RCU_PLLSRC_IRC8M_DIV2 == pllsel){ + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE / 2U; + }else{ + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + + predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); + + /* source clock use PLL1 */ + if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ + predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; + pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; + if(17U == pll1mf){ + pll1mf = 20U; + } + ck_src = (ck_src / predv1) * pll1mf; + } + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; + ck_src /= predv0; + } + + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + + if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ + pllmf |= 0x10U; + } + + if(pllmf >= 15U){ + pllmf += 1U; + }else{ + pllmf += 2U; + } + + SystemCoreClock = ck_src * pllmf; + + if(15U == pllmf){ + /* PLL source clock multiply by 6.5 */ + SystemCoreClock = ck_src * 6U + ck_src / 2U; + } + + break; + + /* IRC8M is selected as CK_SYS */ + default: + SystemCoreClock = IRC8M_VALUE; + break; + } +} + +#ifdef __SYSTEM_CLOCK_HXTAL +/*! + \brief configure the system clock to HXTAL + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + + /* wait until HXTAL is selected as system clock */ + while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +/*! + \brief configure the system clock to 24M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_24m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 6 = 24 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +/*! + \brief configure the system clock to 36M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_36m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 9 = 36 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +/*! + \brief configure the system clock to 48M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12); + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +/*! + \brief configure the system clock to 56M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_56m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 14 = 56 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL14); + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +/*! + \brief configure the system clock to 72M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18); + + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +/*! + \brief configure the system clock to 96M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_96m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + if(HXTAL_VALUE==25000000){ + + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +/*! + \brief configure the system clock to 108M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ + +static void system_clock_108m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PREDV1_DIV5 | RCU_PLL1_MUL8 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL2EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){ + } + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 | RCU_PREDV1_DIV2 | RCU_PLL1_MUL20 | RCU_PLL2_MUL20); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } + + /* enable PLL2 */ + RCU_CTL |= RCU_CTL_PLL2EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){ + } + + } + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) +/*! + \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL12; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +/*! + \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL18; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +/*! + \brief configure the system clock to 108M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL27; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#endif diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/usbh_hid_core.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/usbh_hid_core.c new file mode 100644 index 0000000..c8a2489 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/usbh_hid_core.c @@ -0,0 +1,492 @@ +/*! + \file usbh_hid_core.c + \brief this file implements the functions for the HID core state process + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_pipe.h" +#include "drv_usb_hw.h" +#include "usbh_hid_core.h" +#include "usbh_hid_mouse.h" +#include "usbh_hid_keybd.h" +#include + +hid_machine_struct hid_machine; + +usb_desc_hid hid_desc; +usb_desc_report hid_report; + +__IO uint8_t start_toggle = 0; + +static void usbh_hiddesc_parse (usb_desc_hid *hid_desc, uint8_t *buf); + +static void usbh_hid_itf_deinit (usb_core_driver *pudev, void *phost); + +static usbh_status usbh_hid_itf_init (usb_core_driver *pudev, void *phost); + +static usbh_status usbh_hid_handle (usb_core_driver *pudev, void *phost); + +static usbh_status usbh_hid_class_req (usb_core_driver *pudev, void *phost); + +static usbh_status usbh_hid_reportdesc_get (usb_core_driver *pudev, + usbh_host *phost, + uint16_t Len); + +static usbh_status usbh_hid_desc_get (usb_core_driver *pudev, usbh_host *phost, uint16_t Len); + +static usbh_status usbh_set_idle (usb_core_driver *pudev, + usbh_host *phost, + uint8_t Duration, + uint8_t ReportId); + +static usbh_status usbh_set_protocol (usb_core_driver *pudev, + usbh_host *phost, + uint8_t Protocol); + +usbh_class_cb usbh_hid_cb = +{ + usbh_hid_itf_init, + usbh_hid_itf_deinit, + usbh_hid_class_req, + usbh_hid_handle +}; + +/*! + \brief initialize the hid class + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_hid_itf_init (usb_core_driver *pudev, void *phost) +{ + uint8_t num = 0; + uint8_t ep_num = 0; + + usbh_host *pphost = phost; + + usbh_status status = USBH_BUSY; + + usb_desc_itf *itf_desc = &pphost->dev_prop.itf_desc[0]; + + hid_machine.state = HID_ERROR; + + if (itf_desc->bInterfaceSubClass == USB_HID_SUBCLASS_BOOT_ITF) { + /* decode bootclass protocl: mouse or keyboard */ + if (itf_desc->bInterfaceProtocol == USB_HID_PROTOCOL_KEYBOARD) { + hid_machine.proc = &HID_KEYBRD_cb; + } else if (itf_desc->bInterfaceProtocol == USB_HID_PROTOCOL_MOUSE) { + hid_machine.proc = &hid_mouse_cb; + } else { + return status; + } + + hid_machine.state = HID_IDLE; + hid_machine.ctlstate = HID_REQ_IDLE; + + hid_machine.poll = pphost->dev_prop.ep_desc[0][0].bInterval; + + if (hid_machine.poll < HID_MIN_POLL) { + hid_machine.poll = HID_MIN_POLL; + } + + /* check fo available number of endpoints */ + /* find the number of endpoints in the interface descriptor */ + /* choose the lower number in order not to overrun the buffer allocated */ + ep_num = USB_MIN(itf_desc->bNumEndpoints, USBH_MAX_EP_NUM); + + /* decode endpoint IN and OUT address from interface descriptor */ + for (num = 0; num < ep_num; num++) { + usb_desc_ep *ep_desc = &pphost->dev_prop.ep_desc[0][num]; + + uint8_t ep_addr = ep_desc->bEndpointAddress; + + hid_machine.len = ep_desc->wMaxPacketSize; + + if (ep_addr & 0x80) { + hid_machine.ep_in = ep_addr; + hid_machine.pipe_in = usbh_pipe_allocate (pudev, ep_addr); + + /* open channel for IN endpoint */ + usbh_pipe_create (pudev, + &pphost->dev_prop, + hid_machine.pipe_in, + USB_EPTYPE_INTR, + hid_machine.len); + } else { + hid_machine.ep_out = ep_addr; + hid_machine.pipe_out = usbh_pipe_allocate (pudev, ep_addr); + + /* open channel for OUT endpoint */ + usbh_pipe_create (pudev, + &pphost->dev_prop, + hid_machine.pipe_out, + USB_EPTYPE_INTR, + hid_machine.len); + } + } + + start_toggle = 0; + status = USBH_OK; + } else { + pphost->usr_cb->dev_not_supported(); + } + + return status; +} + +/*! + \brief de-initialize the host pipes used for the HID class + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +void usbh_hid_itf_deinit (usb_core_driver *pudev, void *phost) +{ + if (0x00U != hid_machine.pipe_in) { + usb_pipe_halt (pudev, hid_machine.pipe_in); + + usbh_pipe_free (pudev, hid_machine.pipe_in); + + hid_machine.pipe_in = 0; /* reset the pipe as free */ + } + + if (0x00U != hid_machine.pipe_out) { + usb_pipe_halt (pudev, hid_machine.pipe_out); + + usbh_pipe_free (pudev, hid_machine.pipe_out); + + hid_machine.pipe_out = 0; /* reset the channel as free */ + } + + start_toggle = 0; +} + +/*! + \brief handle HID class requests for HID class + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_hid_class_req (usb_core_driver *pudev, void *phost) +{ + usbh_host *pphost = phost; + + usbh_status status = USBH_BUSY; + usbh_status class_req_status = USBH_BUSY; + + /* handle HID control state machine */ + switch (hid_machine.ctlstate) { + case HID_REQ_IDLE: + case HID_REQ_GET_HID_DESC: + /* get HID descriptor */ + if (usbh_hid_desc_get (pudev, pphost, USB_HID_DESC_SIZE) == USBH_OK) { + usbh_hiddesc_parse(&hid_desc, pudev->host.rx_buf); + + hid_machine.ctlstate = HID_REQ_GET_REPORT_DESC; + } + break; + + case HID_REQ_GET_REPORT_DESC: + /* get report descriptor */ + if (usbh_hid_reportdesc_get(pudev, pphost, hid_desc.wDescriptorLength) == USBH_OK) { + hid_machine.ctlstate = HID_REQ_SET_IDLE; + } + break; + + case HID_REQ_SET_IDLE: + class_req_status = usbh_set_idle (pudev, pphost, 0, 0); + + /* set idle */ + if (class_req_status == USBH_OK) { + hid_machine.ctlstate = HID_REQ_SET_PROTOCOL; + } else if(class_req_status == USBH_NOT_SUPPORTED) { + hid_machine.ctlstate = HID_REQ_SET_PROTOCOL; + } + break; + + case HID_REQ_SET_PROTOCOL: + /* set protocol */ + if (usbh_set_protocol (pudev, pphost, 0) == USBH_OK) { + hid_machine.ctlstate = HID_REQ_IDLE; + + /* all requests performed */ + status = USBH_OK; + } + break; + + default: + break; + } + + return status; +} + +/*! + \brief manage state machine for HID data transfers + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_hid_handle (usb_core_driver *pudev, void *phost) +{ + usbh_host *pphost = phost; + usbh_status status = USBH_OK; + + static uint32_t frame_count; + + switch (hid_machine.state) { + case HID_IDLE: + hid_machine.proc->Init(); + hid_machine.state = HID_SYNC; + break; + + case HID_SYNC: + /* sync with start of even frame */ + if (usb_frame_even(pudev) == TRUE) { + hid_machine.state = HID_GET_DATA; + } + break; + + case HID_GET_DATA: + + usbh_data_recev (pudev, hid_machine.buf, hid_machine.pipe_in, hid_machine.len); + + start_toggle = 1; + hid_machine.state = HID_POLL; + hid_machine.timer = usb_curframe_get (pudev); + break; + + case HID_POLL: + frame_count = usb_curframe_get (pudev); + + if ((frame_count > hid_machine.timer) && ((frame_count - hid_machine.timer) >= hid_machine.poll)) { + hid_machine.state = HID_GET_DATA; + } else if ((frame_count < hid_machine.timer) && ((frame_count + 0x3FFFU - hid_machine.timer) >= hid_machine.poll)) { + hid_machine.state = HID_GET_DATA; + } else if (usbh_urbstate_get (pudev, hid_machine.pipe_in) == URB_DONE) { + if (start_toggle == 1) { /* handle data once */ + start_toggle = 0; + hid_machine.proc->Decode(hid_machine.buf); + } + } else if (usbh_urbstate_get (pudev, hid_machine.pipe_in) == URB_STALL) { /* IN endpoint stalled */ + /* issue clear feature on interrupt in endpoint */ + if ((usbh_clrfeature (pudev, pphost, hid_machine.ep_addr, hid_machine.pipe_in)) == USBH_OK) { + /* change state to issue next in token */ + hid_machine.state = HID_GET_DATA; + } + } + break; + + default: + break; + } + + return status; +} + +/*! + \brief send get report descriptor command to the device + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[in] len: HID report descriptor length + \param[out] none + \retval operation status +*/ +static usbh_status usbh_hid_reportdesc_get (usb_core_driver *pudev, usbh_host *puhost, uint16_t len) +{ + usbh_status status = USBH_BUSY; + + if (puhost->control.ctl_state == CTL_IDLE) { + puhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_RECPTYPE_ITF | USB_REQTYPE_STRD, + .bRequest = USB_GET_DESCRIPTOR, + .wValue = USBH_DESC(USB_DESCTYPE_REPORT), + .wIndex = 0, + .wLength = len + }; + + usbh_ctlstate_config (puhost, pudev->host.rx_buf, len); + } + + status = usbh_ctl_handler (pudev, puhost); + + return status; +} + +/*! + \brief send get HID descriptor command to the device + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[in] len: HID descriptor length + \param[out] none + \retval operation status +*/ +static usbh_status usbh_hid_desc_get (usb_core_driver *pudev, usbh_host *puhost, uint16_t len) +{ + usbh_status status = USBH_BUSY; + + if (puhost->control.ctl_state == CTL_IDLE) { + puhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_RECPTYPE_ITF | USB_REQTYPE_STRD, + .bRequest = USB_GET_DESCRIPTOR, + .wValue = USBH_DESC(USB_DESCTYPE_HID), + .wIndex = 0, + .wLength = len + }; + + usbh_ctlstate_config (puhost, pudev->host.rx_buf, len); + } + + status = usbh_ctl_handler (pudev, puhost); + + return status; +} + +/*! + \brief set idle state + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[in] duration: duration for HID set idle request + \param[in] report_ID: targetted report ID for HID set idle request + \param[out] none + \retval operation status +*/ +static usbh_status usbh_set_idle (usb_core_driver *pudev, + usbh_host *puhost, + uint8_t duration, + uint8_t report_ID) +{ + usbh_status status = USBH_BUSY; + + if (puhost->control.ctl_state == CTL_IDLE) { + puhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_CLASS, + .bRequest = SET_IDLE, + .wValue = (duration << 8) | report_ID, + .wIndex = 0, + .wLength = 0 + }; + + usbh_ctlstate_config (puhost, NULL, 0); + } + + status = usbh_ctl_handler (pudev, puhost); + + return status; +} + +/*! + \brief set report + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[in] report_type: duration for HID set idle request + \param[in] report_ID: targetted report ID for HID set idle request + \param[in] report_len: length of data report to be send + \param[in] report_buf: report buffer + \param[out] none + \retval operation status +*/ +usbh_status usbh_set_report (usb_core_driver *pudev, + usbh_host *puhost, + uint8_t report_type, + uint8_t report_ID, + uint8_t report_len, + uint8_t *report_buf) +{ + usbh_status status = USBH_BUSY; + + if (puhost->control.ctl_state == CTL_IDLE) { + puhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_CLASS, + .bRequest = SET_REPORT, + .wValue = (report_type << 8) | report_ID, + .wIndex = 0, + .wLength = report_len + }; + + usbh_ctlstate_config (puhost, report_buf, report_len); + } + + status = usbh_ctl_handler (pudev, puhost); + + return status; +} + +/*! + \brief set protocol state + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[in] protocol: boot/report protocol + \param[out] none + \retval operation status +*/ +static usbh_status usbh_set_protocol (usb_core_driver *pudev, usbh_host *puhost, uint8_t protocol) +{ + usbh_status status = USBH_BUSY; + + if (puhost->control.ctl_state == CTL_IDLE) { + puhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_CLASS, + .bRequest = SET_PROTOCOL, + .wValue = !protocol, + .wIndex = 0, + .wLength = 0 + }; + + usbh_ctlstate_config (puhost, NULL, 0); + } + + status = usbh_ctl_handler (pudev, puhost); + + return status; +} + +/*! + \brief parse the HID descriptor + \param[in] hid_desc: pointer to HID descriptor + \param[in] buf: pointer to buffer where the source descriptor is available + \param[out] none + \retval operation status +*/ +static void usbh_hiddesc_parse (usb_desc_hid *hid_desc, uint8_t *buf) +{ + hid_desc->header.bLength = *(uint8_t *)(buf + 0); + hid_desc->header.bDescriptorType = *(uint8_t *)(buf + 1); + hid_desc->bcdHID = BYTE_SWAP(buf + 2); + hid_desc->bCountryCode = *(uint8_t *)(buf + 4); + hid_desc->bNumDescriptors = *(uint8_t *)(buf + 5); + hid_desc->bDescriptorType = *(uint8_t *)(buf + 6); + hid_desc->wDescriptorLength = BYTE_SWAP(buf + 7); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/usbh_hid_keybd.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/usbh_hid_keybd.c new file mode 100644 index 0000000..db5a3f9 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/usbh_hid_keybd.c @@ -0,0 +1,250 @@ +/*! + \file usbh_hid_keybd.c + \brief this file is the application layer for usb host hid keyboard handling + qwerty and azerty keyboard are supported as per the selection in + usbh_hid_keybd.h + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_hid_keybd.h" +#include + +static void keybrd_init (void); +static void keybrd_decode (uint8_t *pbuf); + +hid_proc HID_KEYBRD_cb= +{ + keybrd_init, + keybrd_decode +}; + +/* LOCAL CONSTANTS */ +static const uint8_t HID_KEYBRD_Codes[] = +{ + 0, 0, 0, 0, 31, 50, 48, 33, + 19, 34, 35, 36, 24, 37, 38, 39, /* 0x00 - 0x0F */ + 52, 51, 25, 26, 17, 20, 32, 21, + 23, 49, 18, 47, 22, 46, 2, 3, /* 0x10 - 0x1F */ + 4, 5, 6, 7, 8, 9, 10, 11, + 43, 110, 15, 16, 61, 12, 13, 27, /* 0x20 - 0x2F */ + 28, 29, 42, 40, 41, 1, 53, 54, + 55, 30, 112, 113, 114, 115, 116, 117, /* 0x30 - 0x3F */ + 118, 119, 120, 121, 122, 123, 124, 125, + 126, 75, 80, 85, 76, 81, 86, 89, /* 0x40 - 0x4F */ + 79, 84, 83, 90, 95, 100, 105, 106, + 108, 93, 98, 103, 92, 97, 102, 91, /* 0x50 - 0x5F */ + 96, 101, 99, 104, 45, 129, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x60 - 0x6F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x70 - 0x7F */ + 0, 0, 0, 0, 0, 107, 0, 56, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x80 - 0x8F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x90 - 0x9F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xA0 - 0xAF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xB0 - 0xBF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xC0 - 0xCF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xD0 - 0xDF */ + 58, 44, 60, 127, 64, 57, 62, 128 /* 0xE0 - 0xE7 */ +}; + +#ifdef QWERTY_KEYBOARD +static const int8_t HID_KEYBRD_Key[] = +{ + '\0', '`', '1', '2', '3', '4', '5', '6', + '7', '8', '9', '0', '-', '=', '\0', '\r', + '\t', 'q', 'w', 'e', 'r', 't', 'y', 'u', + 'i', 'o', 'p', '[', ']', '\\', + '\0', 'a', 's', 'd', 'f', 'g', 'h', 'j', + 'k', 'l', ';', '\'', '\0', '\n', + '\0', '\0', 'z', 'x', 'c', 'v', 'b', 'n', + 'm', ',', '.', '/', '\0', '\0', + '\0', '\0', '\0', ' ', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '7', '4', '1', + '\0', '/', '8', '5', '2', + '0', '*', '9', '6', '3', + '.', '-', '+', '\0', '\n', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0' +}; + +static const int8_t HID_KEYBRD_ShiftKey[] = { + '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', + '_', '+', '\0', '\0', '\0', 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', + 'I', 'O', 'P', '{', '}', '|', '\0', 'A', 'S', 'D', 'F', 'G', + 'H', 'J', 'K', 'L', ':', '"', '\0', '\n', '\0', '\0', 'Z', 'X', + 'C', 'V', 'B', 'N', 'M', '<', '>', '?', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; + +#else + +static const int8_t HID_KEYBRD_Key[] = { + '\0', '`', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', + '-', '=', '\0', '\r', '\t', 'a', 'z', 'e', 'r', 't', 'y', 'u', + 'i', 'o', 'p', '[', ']', '\\', '\0', 'q', 's', 'd', 'f', 'g', + 'h', 'j', 'k', 'l', 'm', '\0', '\0', '\n', '\0', '\0', 'w', 'x', + 'c', 'v', 'b', 'n', ',', ';', ':', '!', '\0', '\0', '\0', '\0', + '\0', ' ', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '7', '4', '1', '\0', '/', + '8', '5', '2', '0', '*', '9', '6', '3', '.', '-', '+', '\0', + '\n', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; + +static const int8_t HID_KEYBRD_ShiftKey[] = { + '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', + '+', '\0', '\0', '\0', 'A', 'Z', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', + 'P', '{', '}', '*', '\0', 'Q', 'S', 'D', 'F', 'G', 'H', 'J', 'K', + 'L', 'M', '%', '\0', '\n', '\0', '\0', 'W', 'X', 'C', 'V', 'B', 'N', + '?', '.', '/', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; +#endif + +/*! + \brief initialize the keyboard function. + \param[in] none + \param[out] none + \retval none +*/ +static void keybrd_init (void) +{ + /* call user init*/ + usr_keybrd_init(); +} + +/*! + \brief decode the pressed keys. + \param[in] pbuf: pointer to the HID IN report data buffer + \param[out] none + \retval none +*/ +static void keybrd_decode(uint8_t *pbuf) +{ + static uint8_t shift; + static uint8_t keys[KBR_MAX_NBR_PRESSED]; + static uint8_t keys_new[KBR_MAX_NBR_PRESSED]; + static uint8_t keys_last[KBR_MAX_NBR_PRESSED]; + static uint8_t key_newest; + static uint8_t nbr_keys; + static uint8_t nbr_keys_new; + static uint8_t nbr_keys_last; + uint8_t ix; + uint8_t jx; + uint8_t error; + uint8_t output; + + nbr_keys = 0U; + nbr_keys_new = 0U; + nbr_keys_last = 0U; + key_newest = 0x00U; + + /* check if shift key is pressed */ + if ((KBD_LEFT_SHIFT == pbuf[0]) || (KBD_RIGHT_SHIFT == pbuf[0])) { + shift = TRUE; + } else { + shift = FALSE; + } + + error = FALSE; + + /* check for the value of pressed key */ + for (ix = 2U; ix < 2U + KBR_MAX_NBR_PRESSED; ix++) { + if ((0x01U == pbuf[ix]) || (0x02U == pbuf[ix]) || (0x03U == pbuf[ix])) { + error = TRUE; + } + } + + if (TRUE == error) { + return; + } + + nbr_keys = 0U; + nbr_keys_new = 0U; + + for (ix = 2U; ix < 2U + KBR_MAX_NBR_PRESSED; ix++) { + if (0U != pbuf[ix]) { + keys[nbr_keys] = pbuf[ix]; + nbr_keys++; + + for (jx = 0U; jx < nbr_keys_last; jx++) { + if (pbuf[ix] == keys_last[jx]) { + break; + } + } + + if (jx == nbr_keys_last) { + keys_new[nbr_keys_new] = pbuf[ix]; + nbr_keys_new++; + } + } + } + + if (1U == nbr_keys_new) { + key_newest = keys_new[0]; + + if (TRUE == shift) { + output = (uint8_t)HID_KEYBRD_ShiftKey[HID_KEYBRD_Codes[key_newest]]; + } else { + output = (uint8_t)HID_KEYBRD_Key[HID_KEYBRD_Codes[key_newest]]; + } + + /* call user process handle */ + usr_keybrd_process_data(output); + } else { + key_newest = 0x00U; + } + + nbr_keys_last = nbr_keys; + + for (ix = 0U; ix < KBR_MAX_NBR_PRESSED; ix++) { + keys_last[ix] = keys[ix]; + } +} + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/usbh_hid_mouse.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/usbh_hid_mouse.c new file mode 100644 index 0000000..c567d16 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/usbh_hid_mouse.c @@ -0,0 +1,181 @@ +/*! + \file usbh_hid_mouse.c + \brief this file is the application layer for usb host hid mouse handling + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_hid_mouse.h" + +int16_t x_loc = 0, y_loc = 0; +int16_t prev_x = 0, prev_y = 0; + +static void mouse_init (void); +static void mouse_decode (uint8_t *data); + +extern char_format_struct charform; + +hid_mouse_data_struct hid_mouse_data; + +hid_proc hid_mouse_cb = +{ + mouse_init, + mouse_decode, +}; + +/*! + \brief init mouse state. + \param[in] none + \param[out] none + \retval none +*/ +static void mouse_init (void) +{ + /* call user init */ + usr_mouse_init(); +} + +/*! + \brief decode mouse data + \param[in] data: pointer to mouse hid data buffer + \param[out] none + \retval none +*/ +static void mouse_decode(uint8_t *data) +{ + hid_mouse_data.button = data[0]; + + hid_mouse_data.x = data[1]; + hid_mouse_data.y = data[2]; + + usr_mouse_process_data(&hid_mouse_data); +} + +/*! + \brief the function is to handle mouse button press + \param[in] button_idx : mouse button pressed + \param[out] none + \retval none +*/ +void hid_mouse_button_pressed(uint8_t button_idx) +{ + /* change the color of button pressed to indicate button press*/ + switch (button_idx) { + /* left button pressed */ + case HID_MOUSE_LEFTBUTTON: + lcd_rectangle_fill(40, 40, 70, 110, LCD_COLOR_MAGENTA); + break; + + /* right button pressed */ + case HID_MOUSE_RIGHTBUTTON: + lcd_rectangle_fill(40, 210, 70, 280, LCD_COLOR_MAGENTA); + break; + + /* middle button pressed */ + case HID_MOUSE_MIDDLEBUTTON: + lcd_rectangle_fill(40, 130, 70, 190, LCD_COLOR_MAGENTA); + break; + + default: + break; + } +} + +/*! + \brief the function is to handle mouse button release + \param[in] button_idx : mouse button released + \param[out] none + \retval none +*/ +void hid_mouse_button_released(uint8_t button_idx) +{ + /* change the color of button released to default button color*/ + switch (button_idx) { + /* left button released */ + case HID_MOUSE_LEFTBUTTON: + lcd_rectangle_fill(40, 40, 70, 110, LCD_COLOR_WHITE); + break; + + /* right button released */ + case HID_MOUSE_RIGHTBUTTON: + lcd_rectangle_fill(40, 210, 70, 280, LCD_COLOR_WHITE); + break; + + /* middle button released */ + case HID_MOUSE_MIDDLEBUTTON: + lcd_rectangle_fill(40, 130, 70, 190, LCD_COLOR_WHITE); + break; + + default: + break; + } +} + +/*! + \brief the function is to handle mouse scroll to upadte the mouse position on display window + \param[in] x: USB HID mouse X co-ordinate + \param[in] y: USB HID mouse Y co-ordinate + \param[out] none + \retval none +*/ +void hid_mouse_update_position (int8_t x, int8_t y) +{ + if ((x != 0) || (y != 0)) { + x_loc += x / 2; + y_loc += y / 2; + + if(y_loc > MOUSE_WINDOW_HEIGHT - 16) { + y_loc = MOUSE_WINDOW_HEIGHT - 16; + } + + if(x_loc > MOUSE_WINDOW_WIDTH - 8) { + x_loc = MOUSE_WINDOW_WIDTH - 8; + } + + if(y_loc < 2) { + y_loc = 2; + } + + if(x_loc < 2) { + x_loc = 2; + } + + lcd_rectangle_fill(81, 41, 190, 280, LCD_COLOR_BLACK); + + charform.char_color = LCD_COLOR_GREEN; + + lcd_char_display (MOUSE_WINDOW_X - y_loc, + MOUSE_WINDOW_Y + x_loc, + 'x', charform); + + prev_x = x_loc; + prev_y = x_loc; + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/usbh_usr.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/usbh_usr.c new file mode 100644 index 0000000..3bda9f2 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/Source/usbh_usr.c @@ -0,0 +1,527 @@ +/*! + \file usbh_usr.c + \brief the user callback function definitions + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "usbh_usr.h" +#include "usbh_hid_mouse.h" +#include "usbh_hid_keybd.h" +#include "lcd_log.h" +#include +#include "gd32vf103v_lcd_eval.h" + +#define SMALL_FONT_COLUMN_WIDTH 8 +#define SMALL_FONT_LINE_WIDTH 16 + +#define KYBRD_FIRST_COLUMN (uint16_t)0 +#define KYBRD_LAST_COLUMN (uint16_t)320 +#define KYBRD_FIRST_LINE (uint16_t)144 +#define KYBRD_LAST_LINE (uint16_t)40 + +uint16_t keybrd_char_xpos = 0; +uint16_t keybrd_char_ypos = 0; +uint8_t need_clear = 0; +uint8_t user_input_flag = 0; +uint8_t button_pressed_flag = 0; + +extern int16_t x_loc, y_loc; +extern __IO int16_t prev_x, prev_y; +extern uint16_t LINE; + +extern char_format_struct charform; + +/* points to the DEVICE_PROP structure of current device */ +usbh_user_cb user_callback_funs = +{ + usbh_user_init, + usbh_user_deinit, + usbh_user_device_connected, + usbh_user_device_reset, + usbh_user_device_disconnected, + usbh_user_over_current_detected, + usbh_user_device_speed_detected, + usbh_user_device_descavailable, + usbh_user_device_address_assigned, + usbh_user_configuration_descavailable, + usbh_user_manufacturer_string, + usbh_user_product_string, + usbh_user_serialnum_string, + usbh_user_enumeration_finish, + usbh_user_userinput, + NULL, + usbh_user_device_not_supported, + usbh_user_unrecovered_error +}; + +/* printf messages */ +const uint8_t MSG_HOST_INIT[] = "> Host Library Initialized."; +const uint8_t MSG_DEV_ATTACHED[] = "> Device Attached."; +const uint8_t MSG_DEV_DISCONNECTED[] = "> Device Disconnected."; +const uint8_t MSG_DEV_ENUMERATED[] = "> Enumeration completed."; +const uint8_t MSG_DEV_HIGHSPEED[] = "> High speed device detected."; +const uint8_t MSG_DEV_FULLSPEED[] = "> Full speed device detected."; +const uint8_t MSG_DEV_LOWSPEED[] = "> Low speed device detected."; +const uint8_t MSG_DEV_ERROR[] = "> Device fault."; + +const uint8_t MSG_MSC_CLASS[] = "> Mass storage device connected."; +const uint8_t MSG_HID_CLASS[] = "> HID device connected."; + +const uint8_t USB_HID_MouseStatus[] = "> HID Demo Device : Mouse."; +const uint8_t USB_HID_KeybrdStatus[] = "> HID Demo Device : Keyboard."; +const uint8_t MSG_UNREC_ERROR[] = "> UNRECOVERED ERROR STATE."; + +const uint8_t MSG_HOST_HEADER[] = "USBFS HID Host"; +const uint8_t MSG_HOST_FOOTER[] = "USB Host Library v2.0.0"; + +const uint8_t MSG_LIB_START[] = "##### USB Host library started #####"; +const uint8_t MSG_DEV_NOSUP[] = "> Device not supported."; +const uint8_t MSG_OVERCURRENT[] = "> Overcurrent detected."; +const uint8_t MSG_USE_KYBD[] = "> Use Keyboard to tape characters: "; +const uint8_t MSG_RESET_DEV[] = "> Reset the USB device."; + +const uint8_t MSG_WAIT_INPUT[] = "> Wait for user input!"; +const uint8_t MSG_USER_INPUT[] = "> User has input!"; + +/*! + \brief user operation for host-mode initialization + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_init(void) +{ + static uint8_t startup = 0; + + if (0U == startup) { + startup = 1U; + + /* configure the User key */ + gd_eval_key_init(KEY_CET, KEY_MODE_GPIO); + + exmc_lcd_init(); + + usb_mdelay(50); + + lcd_init(); + + lcd_log_init(); + + lcd_log_header_set((uint8_t *)MSG_HOST_HEADER, 80); + + lcd_log_print((uint8_t *)MSG_LIB_START, sizeof(MSG_LIB_START) - 1, LCD_COLOR_WHITE); + + charform.char_color = LCD_COLOR_RED; + + lcd_log_footer_set((uint8_t *)MSG_HOST_FOOTER, 60); + } +} + +/*! + \brief user operation for device attached + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_device_connected(void) +{ + if (need_clear != 0) { + lcd_log_text_zone_clear(30, 0, 210, 320); + + need_clear = 0; + } + + lcd_log_print((uint8_t *)MSG_DEV_ATTACHED, sizeof(MSG_DEV_ATTACHED) - 1, LCD_COLOR_WHITE); +} + +/*! + \brief user operation when unrecoveredError happens + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_unrecovered_error (void) +{ + lcd_log_print((uint8_t *)MSG_UNREC_ERROR, sizeof(MSG_UNREC_ERROR) - 1, LCD_COLOR_WHITE); +} + +/*! + \brief user operation for device disconnect event + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_device_disconnected (void) +{ + LINE = 30; + + lcd_log_text_zone_clear(30, 0, 210, 320); + + lcd_log_print((uint8_t *)MSG_DEV_DISCONNECTED, sizeof(MSG_DEV_DISCONNECTED) - 1, LCD_COLOR_WHITE); + + need_clear = 1; +} + +/*! + \brief user operation for reset USB device + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_device_reset(void) +{ + lcd_log_print((uint8_t *)MSG_RESET_DEV, sizeof(MSG_RESET_DEV) - 1, LCD_COLOR_WHITE); +} + +/*! + \brief user operation for detectting device speed + \param[in] device_speed: the device speed + \param[out] none + \retval none +*/ +void usbh_user_device_speed_detected(uint32_t device_speed) +{ + if (PORT_SPEED_HIGH == device_speed) { + lcd_log_print((uint8_t *)MSG_DEV_HIGHSPEED, sizeof(MSG_DEV_HIGHSPEED) - 1, LCD_COLOR_WHITE); + } else if (PORT_SPEED_FULL == device_speed) { + lcd_log_print((uint8_t *)MSG_DEV_FULLSPEED, sizeof(MSG_DEV_FULLSPEED) - 1, LCD_COLOR_WHITE); + } else if (PORT_SPEED_LOW == device_speed) { + lcd_log_print((uint8_t *)MSG_DEV_LOWSPEED, sizeof(MSG_DEV_LOWSPEED) - 1, LCD_COLOR_WHITE); + } else { + lcd_log_print((uint8_t *)MSG_DEV_ERROR, sizeof(MSG_DEV_ERROR) - 1, LCD_COLOR_WHITE); + } +} + +/*! + \brief user operation when device descriptor is available + \param[in] device_desc: the device descripter + \param[out] none + \retval none +*/ +void usbh_user_device_descavailable(void *device_desc) +{ + uint8_t TempStr[64], str_len = 0; + usb_desc_dev *pDevStr = device_desc; + + sprintf((char *)TempStr, "VID: %04Xh", (uint32_t)pDevStr->idVendor); + str_len = strlen((const char *)TempStr); + lcd_log_print((uint8_t *)TempStr, str_len, LCD_COLOR_WHITE); + + sprintf((char *)TempStr, "PID: %04Xh" , (uint32_t)pDevStr->idProduct); + str_len = strlen((const char *)TempStr); + lcd_log_print((uint8_t *)TempStr, str_len, LCD_COLOR_WHITE); +} + +/*! + \brief USB device is successfully assigned the address + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_device_address_assigned(void) +{ + +} + +/*! + \brief user operation when configuration descriptor is available + \param[in] cfg_desc: pointer to configuration descriptor + \param[in] itf_desc: pointer to interface descriptor + \param[in] ep_desc: pointer to endpoint descriptor + \param[out] none + \retval none +*/ +void usbh_user_configuration_descavailable(usb_desc_config *cfg_desc, + usb_desc_itf *itf_desc, + usb_desc_ep *ep_desc) +{ + usb_desc_itf *id = itf_desc; + + if (0x08U == (*id).bInterfaceClass) { + lcd_log_print((uint8_t *)MSG_MSC_CLASS, sizeof(MSG_MSC_CLASS) - 1, LCD_COLOR_WHITE); + } else if (0x03U == (*id).bInterfaceClass) { + lcd_log_print((uint8_t *)MSG_HID_CLASS, sizeof(MSG_HID_CLASS) - 1, LCD_COLOR_WHITE); + } +} + +/*! + \brief user operation when manufacturer string exists + \param[in] manufacturer_string: manufacturer string of usb device + \param[out] none + \retval none +*/ +void usbh_user_manufacturer_string(void *manufacturer_string) +{ + uint8_t TempStr[64], str_len = 0; + + sprintf((char *)TempStr, "Manufacturer: %s", (char *)manufacturer_string); + str_len = strlen((const char *)TempStr); + lcd_log_print((uint8_t *)TempStr, str_len, LCD_COLOR_WHITE); +} + +/*! + \brief user operation when product string exists + \param[in] product_string: product string of usb device + \param[out] none + \retval none +*/ +void usbh_user_product_string(void *product_string) +{ + uint8_t TempStr[64], str_len = 0; + + sprintf((char *)TempStr, "Product: %s", (char *)product_string); + str_len = strlen((const char *)TempStr); + lcd_log_print((uint8_t *)TempStr, str_len, LCD_COLOR_WHITE); +} + +/*! + \brief user operatin when serialNum string exists + \param[in] serial_num_string: serialNum string of usb device + \param[out] none + \retval none +*/ +void usbh_user_serialnum_string(void *serial_num_string) +{ + uint8_t TempStr[64], str_len = 0; + + sprintf((char *)TempStr, "Serial Number: %s", (char *)serial_num_string); + str_len = strlen((const char *)TempStr); + lcd_log_print((uint8_t *)TempStr, str_len, LCD_COLOR_WHITE); +} + +/*! + \brief user response request is displayed to ask for application jump to class + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_enumeration_finish(void) +{ + /* enumeration complete */ + uint8_t Str1[] = "To start the HID class operations: "; + uint8_t Str2[] = "Press CET Key... "; + + lcd_log_print((uint8_t *)MSG_DEV_ENUMERATED, sizeof(MSG_DEV_ENUMERATED) - 1, LCD_COLOR_WHITE); + lcd_log_print((uint8_t *)Str1, sizeof(Str1) - 1, LCD_COLOR_GREEN); + lcd_log_print((uint8_t *)Str2, sizeof(Str2) - 1, LCD_COLOR_GREEN); +} + +/*! + \brief user operation when device is not supported + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_device_not_supported(void) +{ + lcd_log_print((uint8_t *)MSG_DEV_NOSUP, sizeof(MSG_DEV_NOSUP) - 1, LCD_COLOR_WHITE); +} + +/*! + \brief user action for application state entry + \param[in] none + \param[out] none + \retval none +*/ +usbh_user_status usbh_user_userinput(void) +{ + usbh_user_status usbh_usr_status = USBH_USER_NO_RESP; + + /*key B3 is in polling mode to detect user action */ + if (SET != gd_eval_key_state_get(KEY_CET)) { + usbh_usr_status = USBH_USER_RESP_OK; + } + + return usbh_usr_status; +} + +/*! + \brief user operation for device overcurrent detection event + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_over_current_detected (void) +{ + lcd_log_print((uint8_t *)MSG_OVERCURRENT, sizeof(MSG_OVERCURRENT) - 1, LCD_COLOR_WHITE); +} + +/*! + \brief init mouse window + \param[in] none + \param[out] none + \retval none +*/ +void usr_mouse_init (void) +{ + lcd_log_print((uint8_t *)USB_HID_MouseStatus, sizeof(USB_HID_MouseStatus) - 1, LCD_COLOR_WHITE); + + lcd_rectangle_fill(30, 0, 210, 320, LCD_COLOR_BLACK); + + lcd_rectangle_draw(80, 40, 190, 280, LCD_COLOR_YELLOW); + + lcd_rectangle_fill(40, 40, 70, 110, LCD_COLOR_WHITE); + lcd_rectangle_fill(40, 130, 70, 190, LCD_COLOR_WHITE); + lcd_rectangle_fill(40, 210, 70, 280, LCD_COLOR_WHITE); + + hid_mouse_button_released(0); + hid_mouse_button_released(1); + hid_mouse_button_released(2); + + charform.char_color = LCD_COLOR_GREEN; + charform.bk_color = LCD_COLOR_BLACK; + + lcd_char_display (184, 44, 'x', charform); + + x_loc = 0; + y_loc = 0; + prev_x = 0; + prev_y = 0; +} + +/*! + \brief process mouse data + \param[in] data: mouse data to be displayed + \param[out] none + \retval none +*/ +void usr_mouse_process_data(hid_mouse_data_struct *data) +{ + uint8_t idx = 1; + static uint8_t b_state[3] = {0}; + + if ((data->x != 0) && (data->y != 0)) { + hid_mouse_update_position(data->x, data->y); + } + + for (idx = 0; idx < 3; idx ++) { + if (data->button & 1 << idx) { + if (b_state[idx] == 0) { + hid_mouse_button_pressed(idx); + b_state[idx] = 1; + } + } else { + if (b_state[idx] == 1) { + hid_mouse_button_released(idx); + b_state[idx] = 0; + } + } + } +} + +/*! + \brief init keyboard window + \param[in] none + \param[out] none + \retval none +*/ +void usr_keybrd_init (void) +{ + LINE = 190; + + lcd_rectangle_fill(30, 0, 210, 320, LCD_COLOR_BLACK); + + lcd_log_print((uint8_t *)USB_HID_KeybrdStatus, sizeof(USB_HID_KeybrdStatus) - 1, LCD_COLOR_WHITE); + + lcd_log_print((uint8_t *)MSG_USE_KYBD, sizeof(MSG_USE_KYBD) - 1, LCD_COLOR_WHITE); + + lcd_hline_draw(150, 0, 320, LCD_COLOR_GREEN, 2); + + keybrd_char_xpos = KYBRD_FIRST_LINE; + keybrd_char_ypos = KYBRD_FIRST_COLUMN; + + lcd_hline_draw(30, 0, 320, LCD_COLOR_GREEN, 2); +} + +/*! + \brief process keyboard data + \param[in] data: keyboard data to be displayed + \param[out] none + \retval none +*/ +void usr_keybrd_process_data (uint8_t data) +{ + if (data == '\n') { + keybrd_char_ypos = KYBRD_FIRST_COLUMN; + + /* increment char x position */ + keybrd_char_xpos -= SMALL_FONT_LINE_WIDTH; + } else if (data == '\r') { + /* manage deletion of charactter and upadte cursor location */ + if (keybrd_char_ypos == KYBRD_FIRST_COLUMN) { + /* first character of first line to be deleted */ + if (keybrd_char_xpos == KYBRD_FIRST_LINE) { + keybrd_char_ypos = KYBRD_FIRST_COLUMN; + } else { + keybrd_char_xpos -= SMALL_FONT_LINE_WIDTH; + keybrd_char_ypos =(KYBRD_LAST_COLUMN + SMALL_FONT_COLUMN_WIDTH); + } + } else { + keybrd_char_ypos += SMALL_FONT_COLUMN_WIDTH; + } + + charform.char_color = LCD_COLOR_BLACK; + + lcd_char_display(keybrd_char_xpos, keybrd_char_ypos, ' ', charform); + } else { + charform.char_color = LCD_COLOR_WHITE; + lcd_char_display(keybrd_char_xpos, keybrd_char_ypos, data, charform); + + /* update the cursor position on lcd */ + /* check if the y position has reached the last column*/ + if(keybrd_char_ypos == KYBRD_LAST_COLUMN) { + keybrd_char_ypos = KYBRD_FIRST_COLUMN; + + /* increment char X position */ + keybrd_char_xpos -= SMALL_FONT_LINE_WIDTH; + } else { + /* increment char Y position */ + keybrd_char_ypos += SMALL_FONT_COLUMN_WIDTH; + } + } + + if (keybrd_char_xpos <= KYBRD_LAST_LINE) { + lcd_rectangle_fill(32, 0, 144, 320, LCD_COLOR_BLACK); + + keybrd_char_xpos = KYBRD_FIRST_LINE; + } +} + +/*! + \brief deinit user state and associated variables + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_deinit(void) +{ +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/readme.txt new file mode 100644 index 0000000..7d288cc --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/HID_Host/readme.txt @@ -0,0 +1,53 @@ +/*! + \file readme.txt + \brief description of the usb host mode to control hid device + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, and it provides a description of +how to use the USBFS host peripheral on the GD32VF103V devices. + + When an USB Device is attached to the Host port, the device is enumerated and checked +whether it can support HID device, if the attached device is HID one, when the user +press the CET key, the mouse or the keyboard application is launched. + + If a mouse has been attached, moving the mouse will print the position of the mouse and +the state of botton through the serial port. + + If a keyboard has been attached, pressing the keyboard will print the state of the button +through the serial port. + +Note: In the USB Host HID class, two layouts are defined in the usbh_hid_keybd.h file + and could be used (Azerty and Querty) + //#define QWERTY_KEYBOARD + #define AZERTY_KEYBOARD + The User can eventually add his own layout by editing the HID_KEYBRD_Key array + in the usbh_hid_keybd.c file. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Eclipse/usbh_msc/.cproject b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Eclipse/usbh_msc/.cproject new file mode 100644 index 0000000..682c61d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Eclipse/usbh_msc/.cproject @@ -0,0 +1,209 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Eclipse/usbh_msc/.project b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Eclipse/usbh_msc/.project new file mode 100644 index 0000000..0610e29 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Eclipse/usbh_msc/.project @@ -0,0 +1,728 @@ + + + usbh_msc + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Examples + 2 + virtual:/virtual + + + Firmware + 2 + virtual:/virtual + + + Utilities + 2 + virtual:/virtual + + + Examples/USBFS + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral + 2 + virtual:/virtual + + + Firmware/GD32VF103_usbfs_driver + 2 + virtual:/virtual + + + Firmware/RSICV + 2 + virtual:/virtual + + + Utilities/gd32vf103v_eval.c + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_eval.c + + + Utilities/gd32vf103v_eval.h + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_eval.h + + + Utilities/gd32vf103v_lcd_eval.c + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_lcd_eval.c + + + Utilities/gd32vf103v_lcd_eval.h + 1 + PARENT-6-PROJECT_LOC/Utilities/gd32vf103v_lcd_eval.h + + + Examples/USBFS/USB_Host + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Include + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Source + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/gd32vf103.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/gd32vf103.h + + + Firmware/GD32VF103_standard_peripheral/system_gd32vf103.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/system_gd32vf103.h + + + Firmware/GD32VF103_usbfs_driver/Include + 2 + virtual:/virtual + + + Firmware/GD32VF103_usbfs_driver/Source + 2 + virtual:/virtual + + + Firmware/RSICV/drivers + 2 + virtual:/virtual + + + Firmware/RSICV/env_Eclipse + 2 + virtual:/virtual + + + Firmware/RSICV/stubs + 2 + virtual:/virtual + + + Examples/USBFS/USB_Host/MSC_Host + 2 + virtual:/virtual + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h + + + Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c + + + Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_core.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_core.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_host.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_host.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_hw.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_hw.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usb_regs.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_regs.h + + + Firmware/GD32VF103_usbfs_driver/Include/drv_usbh_int.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/drv_usbh_int.h + + + Firmware/GD32VF103_usbfs_driver/Include/usb_ch9_std.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usb_ch9_std.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbh_core.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbh_core.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbh_enum.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbh_enum.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbh_pipe.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbh_pipe.h + + + Firmware/GD32VF103_usbfs_driver/Include/usbh_transc.h + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Include/usbh_transc.h + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usb_core.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_core.c + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usb_host.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_host.c + + + Firmware/GD32VF103_usbfs_driver/Source/drv_usbh_int.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/drv_usbh_int.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbh_core.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbh_core.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbh_enum.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbh_enum.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbh_pipe.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbh_pipe.c + + + Firmware/GD32VF103_usbfs_driver/Source/usbh_transc.c + 1 + PARENT-6-PROJECT_LOC/Firmware/GD32VF103_usbfs_driver/Source/usbh_transc.c + + + Firmware/RSICV/drivers/n200_eclic.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_eclic.h + + + Firmware/RSICV/drivers/n200_func.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_func.c + + + Firmware/RSICV/drivers/n200_func.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_func.h + + + Firmware/RSICV/drivers/n200_timer.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/n200_timer.h + + + Firmware/RSICV/drivers/riscv_bits.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_bits.h + + + Firmware/RSICV/drivers/riscv_const.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_const.h + + + Firmware/RSICV/drivers/riscv_encoding.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/drivers/riscv_encoding.h + + + Firmware/RSICV/env_Eclipse/GD32VF103x4.lds + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/GD32VF103x4.lds + + + Firmware/RSICV/env_Eclipse/GD32VF103x6.lds + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/GD32VF103x6.lds + + + Firmware/RSICV/env_Eclipse/GD32VF103x8.lds + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/GD32VF103x8.lds + + + Firmware/RSICV/env_Eclipse/GD32VF103xB.lds + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/GD32VF103xB.lds + + + Firmware/RSICV/env_Eclipse/entry.S + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/entry.S + + + Firmware/RSICV/env_Eclipse/handlers.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/handlers.c + + + Firmware/RSICV/env_Eclipse/init.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/init.c + + + Firmware/RSICV/env_Eclipse/start.S + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/start.S + + + Firmware/RSICV/env_Eclipse/your_printf.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/env_Eclipse/your_printf.c + + + Firmware/RSICV/stubs/_exit.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/_exit.c + + + Firmware/RSICV/stubs/close.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/close.c + + + Firmware/RSICV/stubs/fstat.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/fstat.c + + + Firmware/RSICV/stubs/isatty.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/isatty.c + + + Firmware/RSICV/stubs/lseek.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/lseek.c + + + Firmware/RSICV/stubs/read.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/read.c + + + Firmware/RSICV/stubs/sbrk.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/sbrk.c + + + Firmware/RSICV/stubs/stub.h + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/stub.h + + + Firmware/RSICV/stubs/write.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/write.c + + + Firmware/RSICV/stubs/write_hex.c + 1 + PARENT-6-PROJECT_LOC/Firmware/RISCV/stubs/write_hex.c + + + Examples/USBFS/USB_Host/MSC_Host/Include + 2 + virtual:/virtual + + + Examples/USBFS/USB_Host/MSC_Host/Source + 2 + virtual:/virtual + + + Examples/USBFS/USB_Host/MSC_Host/Include/diskio.h + 1 + PARENT-2-PROJECT_LOC/Include/diskio.h + + + Examples/USBFS/USB_Host/MSC_Host/Include/fattime.h + 1 + PARENT-2-PROJECT_LOC/Include/fattime.h + + + Examples/USBFS/USB_Host/MSC_Host/Include/ff.h + 1 + PARENT-2-PROJECT_LOC/Include/ff.h + + + Examples/USBFS/USB_Host/MSC_Host/Include/ffconf.h + 1 + PARENT-2-PROJECT_LOC/Include/ffconf.h + + + Examples/USBFS/USB_Host/MSC_Host/Include/gd32vf103_it.h + 1 + PARENT-2-PROJECT_LOC/Include/gd32vf103_it.h + + + Examples/USBFS/USB_Host/MSC_Host/Include/gd32vf103_libopt.h + 1 + PARENT-2-PROJECT_LOC/Include/gd32vf103_libopt.h + + + Examples/USBFS/USB_Host/MSC_Host/Include/integer.h + 1 + PARENT-2-PROJECT_LOC/Include/integer.h + + + Examples/USBFS/USB_Host/MSC_Host/Include/lcd_font.h + 1 + PARENT-2-PROJECT_LOC/Include/lcd_font.h + + + Examples/USBFS/USB_Host/MSC_Host/Include/lcd_log.h + 1 + PARENT-2-PROJECT_LOC/Include/lcd_log.h + + + Examples/USBFS/USB_Host/MSC_Host/Include/msc_bbb.h + 1 + PARENT-2-PROJECT_LOC/Include/msc_bbb.h + + + Examples/USBFS/USB_Host/MSC_Host/Include/msc_scsi.h + 1 + PARENT-2-PROJECT_LOC/Include/msc_scsi.h + + + Examples/USBFS/USB_Host/MSC_Host/Include/usb_conf.h + 1 + PARENT-2-PROJECT_LOC/Include/usb_conf.h + + + Examples/USBFS/USB_Host/MSC_Host/Include/usb_msc.h + 1 + PARENT-2-PROJECT_LOC/Include/usb_msc.h + + + Examples/USBFS/USB_Host/MSC_Host/Include/usbh_conf.h + 1 + PARENT-2-PROJECT_LOC/Include/usbh_conf.h + + + Examples/USBFS/USB_Host/MSC_Host/Include/usbh_msc_bbb.h + 1 + PARENT-2-PROJECT_LOC/Include/usbh_msc_bbb.h + + + Examples/USBFS/USB_Host/MSC_Host/Include/usbh_msc_core.h + 1 + PARENT-2-PROJECT_LOC/Include/usbh_msc_core.h + + + Examples/USBFS/USB_Host/MSC_Host/Include/usbh_msc_scsi.h + 1 + PARENT-2-PROJECT_LOC/Include/usbh_msc_scsi.h + + + Examples/USBFS/USB_Host/MSC_Host/Include/usbh_usr.h + 1 + PARENT-2-PROJECT_LOC/Include/usbh_usr.h + + + Examples/USBFS/USB_Host/MSC_Host/Source/app.c + 1 + PARENT-2-PROJECT_LOC/Source/app.c + + + Examples/USBFS/USB_Host/MSC_Host/Source/fattime.c + 1 + PARENT-2-PROJECT_LOC/Source/fattime.c + + + Examples/USBFS/USB_Host/MSC_Host/Source/ff.c + 1 + PARENT-2-PROJECT_LOC/Source/ff.c + + + Examples/USBFS/USB_Host/MSC_Host/Source/gd32vf103_it.c + 1 + PARENT-2-PROJECT_LOC/Source/gd32vf103_it.c + + + Examples/USBFS/USB_Host/MSC_Host/Source/gd32vf103_usb_hw.c + 1 + PARENT-2-PROJECT_LOC/Source/gd32vf103_usb_hw.c + + + Examples/USBFS/USB_Host/MSC_Host/Source/lcd_font.c + 1 + PARENT-2-PROJECT_LOC/Source/lcd_font.c + + + Examples/USBFS/USB_Host/MSC_Host/Source/lcd_log.c + 1 + PARENT-2-PROJECT_LOC/Source/lcd_log.c + + + Examples/USBFS/USB_Host/MSC_Host/Source/system_gd32vf103.c + 1 + PARENT-2-PROJECT_LOC/Source/system_gd32vf103.c + + + Examples/USBFS/USB_Host/MSC_Host/Source/usbh_msc_bbb.c + 1 + PARENT-2-PROJECT_LOC/Source/usbh_msc_bbb.c + + + Examples/USBFS/USB_Host/MSC_Host/Source/usbh_msc_core.c + 1 + PARENT-2-PROJECT_LOC/Source/usbh_msc_core.c + + + Examples/USBFS/USB_Host/MSC_Host/Source/usbh_msc_fatfs.c + 1 + PARENT-2-PROJECT_LOC/Source/usbh_msc_fatfs.c + + + Examples/USBFS/USB_Host/MSC_Host/Source/usbh_msc_scsi.c + 1 + PARENT-2-PROJECT_LOC/Source/usbh_msc_scsi.c + + + Examples/USBFS/USB_Host/MSC_Host/Source/usbh_usr.c + 1 + PARENT-2-PROJECT_LOC/Source/usbh_usr.c + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Eclipse/usbh_msc/.settings/language.settings.xml b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Eclipse/usbh_msc/.settings/language.settings.xml new file mode 100644 index 0000000..d5f8aa4 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Eclipse/usbh_msc/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/diskio.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/diskio.h new file mode 100644 index 0000000..26fe9cd --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/diskio.h @@ -0,0 +1,68 @@ +/*----------------------------------------------------------------------- +/ Low level disk interface modlue include file R0.07 (C)ChaN, 2009 +/-----------------------------------------------------------------------*/ + +#ifndef _DISKIO + +#define _READONLY 0 /* 1: Read-only mode */ +#define _USE_IOCTL 1 + +#include "integer.h" + +/* Status of Disk Functions */ +typedef BYTE DSTATUS; + +/* Results of Disk Functions */ +typedef enum { + RES_OK = 0, /* 0: Successful */ + RES_ERROR, /* 1: R/W Error */ + RES_WRPRT, /* 2: Write Protected */ + RES_NOTRDY, /* 3: Not Ready */ + RES_PARERR /* 4: Invalid Parameter */ +} DRESULT; + + +/*---------------------------------------*/ +/* Prototypes for disk control functions */ + +bool assign_drives (int argc, char *argv[]); +DSTATUS disk_initialize (BYTE); +DSTATUS disk_status (BYTE); +DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE); +#if _READONLY == 0 +DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE); +#endif +DRESULT disk_ioctl (BYTE, BYTE, void*); + + + +/* Disk Status Bits (DSTATUS) */ + +#define STA_NOINIT 0x01 /* Drive not initialized */ +#define STA_NODISK 0x02 /* No medium in the drive */ +#define STA_PROTECT 0x04 /* Write protected */ + + +/* Command code for disk_ioctrl() */ + +/* Generic command */ +#define CTRL_SYNC 0 /* Mandatory for write functions */ +#define GET_SECTOR_COUNT 1 /* Mandatory for only f_mkfs() */ +#define GET_SECTOR_SIZE 2 +#define GET_BLOCK_SIZE 3 /* Mandatory for only f_mkfs() */ +#define CTRL_POWER 4 +#define CTRL_LOCK 5 +#define CTRL_EJECT 6 +/* MMC/SDC command */ +#define MMC_GET_TYPE 10 +#define MMC_GET_CSD 11 +#define MMC_GET_CID 12 +#define MMC_GET_OCR 13 +#define MMC_GET_SDSTAT 14 +/* ATA/CF command */ +#define ATA_GET_REV 20 +#define ATA_GET_MODEL 21 +#define ATA_GET_SN 22 + +#define _DISKIO +#endif diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/fattime.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/fattime.h new file mode 100644 index 0000000..94b7068 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/fattime.h @@ -0,0 +1,7 @@ +#ifndef FATTIME_H_ + +#include "integer.h" + +DWORD get_fattime (void); + +#endif diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/ff.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/ff.h new file mode 100644 index 0000000..91c4b6b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/ff.h @@ -0,0 +1,596 @@ +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module include file R0.07e (C)ChaN, 2009 +/----------------------------------------------------------------------------/ +/ FatFs module is a generic FAT file system module for small embedded systems. +/ This is a free software that opened for education, research and commercial +/ developments under license policy of following terms. +/ +/ Copyright (C) 2009, ChaN, all right reserved. +/ +/ * The FatFs module is a free software and there is NO WARRANTY. +/ * No restriction on use. You can use, modify and redistribute it for +/ personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. +/ * Redistributions of source code must retain the above copyright notice. +/----------------------------------------------------------------------------*/ + +#ifndef _FATFS +#define _FATFS 0x007E + +#include "integer.h" /* Basic integer types */ +#include "ffconf.h" /* FatFs configuration options */ + +#if _FATFS != _FFCONFIG +#error Wrong configuration file (ffconf.h). +#endif + + +/* DBCS code ranges and SBCS extend char conversion table */ + +#if _CODE_PAGE == 932 /* Japanese Shift-JIS */ +#define _DF1S 0x81 /* DBC 1st byte range 1 start */ +#define _DF1E 0x9F /* DBC 1st byte range 1 end */ +#define _DF2S 0xE0 /* DBC 1st byte range 2 start */ +#define _DF2E 0xFC /* DBC 1st byte range 2 end */ +#define _DS1S 0x40 /* DBC 2nd byte range 1 start */ +#define _DS1E 0x7E /* DBC 2nd byte range 1 end */ +#define _DS2S 0x80 /* DBC 2nd byte range 2 start */ +#define _DS2E 0xFC /* DBC 2nd byte range 2 end */ + +#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x40 +#define _DS1E 0x7E +#define _DS2S 0x80 +#define _DS2E 0xFE + +#elif _CODE_PAGE == 949 /* Korean */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x41 +#define _DS1E 0x5A +#define _DS2S 0x61 +#define _DS2E 0x7A +#define _DS3S 0x81 +#define _DS3E 0xFE + +#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x40 +#define _DS1E 0x7E +#define _DS2S 0xA1 +#define _DS2E 0xFE + +#elif _CODE_PAGE == 437 /* U.S. (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 720 /* Arabic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 737 /* Greek (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ + 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 775 /* Baltic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 850 /* Multilingual Latin 1 (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 852 /* Latin 2 (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} + +#elif _CODE_PAGE == 855 /* Cyrillic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ + 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ + 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 857 /* Turkish (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 858 /* Multilingual Latin 1 + Euro (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 862 /* Hebrew (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 866 /* Russian (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 874 /* Thai (OEM, Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} + +#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ + 0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF} + +#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} + +#elif _CODE_PAGE == 1253 /* Greek (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \ + 0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF} + +#elif _CODE_PAGE == 1254 /* Turkish (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} + +#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1256 /* Arabic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1257 /* Baltic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} + +#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F} + +#elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */ +#define _DF1S 0 + +#else +#error Unknown code page + +#endif + + + +/* Character code support macros */ + +#define IsUpper(c) (((c)>='A')&&((c)<='Z')) +#define IsLower(c) (((c)>='a')&&((c)<='z')) + +#if _DF1S /* DBCS configuration */ + +#ifdef _DF2S /* Two 1st byte areas */ +#define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E)) +#else /* One 1st byte area */ +#define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) +#endif + +#ifdef _DS3S /* Three 2nd byte areas */ +#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E)) +#else /* Two 2nd byte areas */ +#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E)) +#endif + +#else /* SBCS configuration */ + +#define IsDBCS1(c) 0 +#define IsDBCS2(c) 0 + +#endif /* _DF1S */ + + + +/* Definitions corresponds to multi partition */ + +#if _MULTI_PARTITION /* Multiple partition configuration */ + +typedef struct _PARTITION { + BYTE pd; /* Physical drive# */ + BYTE pt; /* Partition # (0-3) */ +} PARTITION; + +extern +const PARTITION Drives[]; /* Logical drive# to physical location conversion table */ +#define LD2PD(drv) (Drives[drv].pd) /* Get physical drive# */ +#define LD2PT(drv) (Drives[drv].pt) /* Get partition# */ + +#else /* Single partition configuration */ + +#define LD2PD(drv) (drv) /* Physical drive# is equal to the logical drive# */ +#define LD2PT(drv) 0 /* Always mounts the 1st partition */ + +#endif + + + +/* Definitions corresponds to multiple sector size */ + +#if _MAX_SS == 512 /* Single sector size */ +#define SS(fs) 512U + +#elif _MAX_SS == 1024 || _MAX_SS == 2048 || _MAX_SS == 4096 /* Multiple sector size */ +#define SS(fs) ((fs)->s_size) + +#else +#error Sector size must be 512, 1024, 2048 or 4096. + +#endif + + + +/* Type of file name on FatFs API */ + +#if _LFN_UNICODE && _USE_LFN +typedef WCHAR XCHAR; /* Unicode */ +#else +typedef char XCHAR; /* SBCS, DBCS */ +#endif + + + +/* File system object structure */ + +typedef struct _FATFS_ { + BYTE fs_type; /* FAT sub type */ + BYTE drive; /* Physical drive number */ + BYTE csize; /* Number of sectors per cluster */ + BYTE n_fats; /* Number of FAT copies */ + BYTE wflag; /* win[] dirty flag (1:must be written back) */ + BYTE fsi_flag; /* fsinfo dirty flag (1:must be written back) */ + WORD id; /* File system mount ID */ + WORD n_rootdir; /* Number of root directory entries (0 on FAT32) */ +#if _FS_REENTRANT + _SYNC_t sobj; /* Identifier of sync object */ +#endif +#if _MAX_SS != 512 + WORD s_size; /* Sector size */ +#endif +#if !_FS_READONLY + DWORD last_clust; /* Last allocated cluster */ + DWORD free_clust; /* Number of free clusters */ + DWORD fsi_sector; /* fsinfo sector */ +#endif +#if _FS_RPATH + DWORD cdir; /* Current directory (0:root)*/ +#endif + DWORD sects_fat; /* Sectors per fat */ + DWORD max_clust; /* Maximum cluster# + 1. Number of clusters is max_clust - 2 */ + DWORD fatbase; /* FAT start sector */ + DWORD dirbase; /* Root directory start sector (Cluster# on FAT32) */ + DWORD database; /* Data start sector */ + DWORD winsect; /* Current sector appearing in the win[] */ + BYTE win[_MAX_SS];/* Disk access window for Directory/FAT */ +} FATFS; + + + +/* Directory object structure */ + +typedef struct _DIR_ { + FATFS* fs; /* Pointer to the owner file system object */ + WORD id; /* Owner file system mount ID */ + WORD index; /* Current read/write index number */ + DWORD sclust; /* Table start cluster (0:Static table) */ + DWORD clust; /* Current cluster */ + DWORD sect; /* Current sector */ + BYTE* dir; /* Pointer to the current SFN entry in the win[] */ + BYTE* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */ +#if _USE_LFN + WCHAR* lfn; /* Pointer to the LFN working buffer */ + WORD lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */ +#endif +} DIR; + + + +/* File object structure */ + +typedef struct _FIL_ { + FATFS* fs; /* Pointer to the owner file system object */ + WORD id; /* Owner file system mount ID */ + BYTE flag; /* File status flags */ + BYTE csect; /* Sector address in the cluster */ + DWORD fptr; /* File R/W pointer */ + DWORD fsize; /* File size */ + DWORD org_clust; /* File start cluster */ + DWORD curr_clust; /* Current cluster */ + DWORD dsect; /* Current data sector */ +#if !_FS_READONLY + DWORD dir_sect; /* Sector containing the directory entry */ + BYTE* dir_ptr; /* Pointer to the directory entry in the window */ +#endif +#if !_FS_TINY + BYTE buf[_MAX_SS];/* File R/W buffer */ +#endif +} FIL; + + + +/* File status structure */ + +typedef struct _FILINFO_ { + DWORD fsize; /* File size */ + WORD fdate; /* Last modified date */ + WORD ftime; /* Last modified time */ + BYTE fattrib; /* Attribute */ + char fname[13]; /* Short file name (8.3 format) */ +#if _USE_LFN + XCHAR* lfname; /* Pointer to the LFN buffer */ + int lfsize; /* Size of LFN buffer [chrs] */ +#endif +} FILINFO; + + + +/* File function return code (FRESULT) */ + +typedef enum { + FR_OK = 0, /* 0 */ + FR_DISK_ERR, /* 1 */ + FR_INT_ERR, /* 2 */ + FR_NOT_READY, /* 3 */ + FR_NO_FILE, /* 4 */ + FR_NO_PATH, /* 5 */ + FR_INVALID_NAME, /* 6 */ + FR_DENIED, /* 7 */ + FR_EXIST, /* 8 */ + FR_INVALID_OBJECT, /* 9 */ + FR_WRITE_PROTECTED, /* 10 */ + FR_INVALID_DRIVE, /* 11 */ + FR_NOT_ENABLED, /* 12 */ + FR_NO_FILESYSTEM, /* 13 */ + FR_MKFS_ABORTED, /* 14 */ + FR_TIMEOUT /* 15 */ +} FRESULT; + + + +/*--------------------------------------------------------------*/ +/* FatFs module application interface */ + +FRESULT f_mount (BYTE, FATFS*); /* Mount/Unmount a logical drive */ +FRESULT f_open (FIL*, const XCHAR*, BYTE); /* Open or create a file */ +FRESULT f_read (FIL*, void*, UINT, UINT*); /* Read data from a file */ +FRESULT f_write (FIL*, const void*, UINT, UINT*); /* Write data to a file */ +FRESULT f_lseek (FIL*, DWORD); /* Move file pointer of a file object */ +FRESULT f_close (FIL*); /* Close an open file object */ +FRESULT f_opendir (DIR*, const XCHAR*); /* Open an existing directory */ +FRESULT f_readdir (DIR*, FILINFO*); /* Read a directory item */ +FRESULT f_stat (const XCHAR*, FILINFO*); /* Get file status */ +FRESULT f_getfree (const XCHAR*, DWORD*, FATFS**); /* Get number of free clusters on the drive */ +FRESULT f_truncate (FIL*); /* Truncate file */ +FRESULT f_sync (FIL*); /* Flush cached data of a writing file */ +FRESULT f_unlink (const XCHAR*); /* Delete an existing file or directory */ +FRESULT f_mkdir (const XCHAR*); /* Create a new directory */ +FRESULT f_chmod (const XCHAR*, BYTE, BYTE); /* Change attribute of the file/dir */ +FRESULT f_utime (const XCHAR*, const FILINFO*); /* Change time-stamp of the file/dir */ +FRESULT f_rename (const XCHAR*, const XCHAR*); /* Rename/Move a file or directory */ +FRESULT f_forward (FIL*, UINT(*)(const BYTE*,UINT), UINT, UINT*); /* Forward data to the stream */ +FRESULT f_mkfs (BYTE, BYTE, WORD); /* Create a file system on the drive */ +FRESULT f_chdir (const XCHAR*); /* Change current directory */ +FRESULT f_chdrive (BYTE); /* Change current drive */ + +#if _USE_STRFUNC +int f_putc (int, FIL*); /* Put a character to the file */ +int f_puts (const char*, FIL*); /* Put a string to the file */ +int f_printf (FIL*, const char*, ...); /* Put a formatted string to the file */ +char* f_gets (char*, int, FIL*); /* Get a string from the file */ +#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0) +#define f_error(fp) (((fp)->flag & FA__ERROR) ? 1 : 0) +#ifndef EOF +#define EOF -1 +#endif +#endif + + + +/*--------------------------------------------------------------*/ +/* User defined functions */ + +/* Real time clock */ +#if !_FS_READONLY +DWORD get_fattime (void); /* 31-25: Year(0-127 org.1980), 24-21: Month(1-12), 20-16: Day(1-31) */ + /* 15-11: Hour(0-23), 10-5: Minute(0-59), 4-0: Second(0-29 *2) */ +#endif + +/* Unicode - OEM code conversion */ +#if _USE_LFN +WCHAR ff_convert (WCHAR, UINT); +WCHAR ff_wtoupper (WCHAR); +#endif + +/* Sync functions */ +#if _FS_REENTRANT +BOOL ff_cre_syncobj(BYTE, _SYNC_t*); +BOOL ff_del_syncobj(_SYNC_t); +BOOL ff_req_grant(_SYNC_t); +void ff_rel_grant(_SYNC_t); +#endif + + + +/*--------------------------------------------------------------*/ +/* Flags and offset address */ + + +/* File access control and file status flags (FIL.flag) */ + +#define FA_READ 0x01 +#define FA_OPEN_EXISTING 0x00 +#if _FS_READONLY == 0 +#define FA_WRITE 0x02 +#define FA_CREATE_NEW 0x04 +#define FA_CREATE_ALWAYS 0x08 +#define FA_OPEN_ALWAYS 0x10 +#define FA__WRITTEN 0x20 +#define FA__DIRTY 0x40 +#endif +#define FA__ERROR 0x80 + + +/* FAT sub type (FATFS.fs_type) */ + +#define FS_FAT12 1 +#define FS_FAT16 2 +#define FS_FAT32 3 + + +/* File attribute bits for directory entry */ + +#define AM_RDO 0x01 /* Read only */ +#define AM_HID 0x02 /* Hidden */ +#define AM_SYS 0x04 /* System */ +#define AM_VOL 0x08 /* Volume label */ +#define AM_LFN 0x0F /* LFN entry */ +#define AM_DIR 0x10 /* Directory */ +#define AM_ARC 0x20 /* Archive */ +#define AM_MASK 0x3F /* Mask of defined bits */ + + +/* FatFs refers the members in the FAT structures with byte offset instead +/ of structure member because there are incompatibility of the packing option +/ between various compilers. */ + +#define BS_jmpBoot 0 +#define BS_OEMName 3 +#define BPB_BytsPerSec 11 +#define BPB_SecPerClus 13 +#define BPB_RsvdSecCnt 14 +#define BPB_NumFATs 16 +#define BPB_RootEntCnt 17 +#define BPB_TotSec16 19 +#define BPB_Media 21 +#define BPB_FATSz16 22 +#define BPB_SecPerTrk 24 +#define BPB_NumHeads 26 +#define BPB_HiddSec 28 +#define BPB_TotSec32 32 +#define BS_55AA 510 + +#define BS_DrvNum 36 +#define BS_BootSig 38 +#define BS_VolID 39 +#define BS_VolLab 43 +#define BS_FilSysType 54 + +#define BPB_FATSz32 36 +#define BPB_ExtFlags 40 +#define BPB_FSVer 42 +#define BPB_RootClus 44 +#define BPB_FSInfo 48 +#define BPB_BkBootSec 50 +#define BS_DrvNum32 64 +#define BS_BootSig32 66 +#define BS_VolID32 67 +#define BS_VolLab32 71 +#define BS_FilSysType32 82 + +#define FSI_LeadSig 0 +#define FSI_StrucSig 484 +#define FSI_Free_Count 488 +#define FSI_Nxt_Free 492 + +#define MBR_Table 446 + +#define DIR_Name 0 +#define DIR_Attr 11 +#define DIR_NTres 12 +#define DIR_CrtTime 14 +#define DIR_CrtDate 16 +#define DIR_FstClusHI 20 +#define DIR_WrtTime 22 +#define DIR_WrtDate 24 +#define DIR_FstClusLO 26 +#define DIR_FileSize 28 +#define LDIR_Ord 0 +#define LDIR_Attr 11 +#define LDIR_Type 12 +#define LDIR_Chksum 13 +#define LDIR_FstClusLO 26 + + + +/*--------------------------------*/ +/* Multi-byte word access macros */ + +#if _WORD_ACCESS == 1 /* Enable word access to the FAT structure */ +#define LD_WORD(ptr) (WORD)(*(WORD*)(BYTE*)(ptr)) +#define LD_DWORD(ptr) (DWORD)(*(DWORD*)(BYTE*)(ptr)) +#define ST_WORD(ptr,val) *(WORD*)(BYTE*)(ptr)=(WORD)(val) +#define ST_DWORD(ptr,val) *(DWORD*)(BYTE*)(ptr)=(DWORD)(val) +#else /* Use byte-by-byte access to the FAT structure */ +#define LD_WORD(ptr) (WORD)(((WORD)*(BYTE*)((ptr)+1)<<8)|(WORD)*(BYTE*)(ptr)) +#define LD_DWORD(ptr) (DWORD)(((DWORD)*(BYTE*)((ptr)+3)<<24)|((DWORD)*(BYTE*)((ptr)+2)<<16)|((WORD)*(BYTE*)((ptr)+1)<<8)|*(BYTE*)(ptr)) +#define ST_WORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *(BYTE*)((ptr)+1)=(BYTE)((WORD)(val)>>8) +#define ST_DWORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *(BYTE*)((ptr)+1)=(BYTE)((WORD)(val)>>8); *(BYTE*)((ptr)+2)=(BYTE)((DWORD)(val)>>16); *(BYTE*)((ptr)+3)=(BYTE)((DWORD)(val)>>24) +#endif + + +#endif /* _FATFS */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/ffconf.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/ffconf.h new file mode 100644 index 0000000..8154888 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/ffconf.h @@ -0,0 +1,166 @@ +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file R0.07e (C)ChaN, 2009 +/----------------------------------------------------------------------------/ +/ +/ CAUTION! Do not forget to make clean the project after any changes to +/ the configuration options. +/ +/----------------------------------------------------------------------------*/ +#ifndef _FFCONFIG +#define _FFCONFIG 0x007E + + +/*---------------------------------------------------------------------------/ +/ Function and Buffer Configurations +/----------------------------------------------------------------------------*/ + +#define _FS_TINY 0 /* 0 or 1 */ +/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system +/ object instead of the sector buffer in the individual file object for file +/ data transfer. This reduces memory consumption 512 bytes each file object. */ + + +#define _FS_READONLY 0 /* 0 or 1 */ +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, +/ f_truncate and useless f_getfree. */ + + +#define _FS_MINIMIZE 0 /* 0, 1, 2 or 3 */ +/* The _FS_MINIMIZE option defines minimization level to remove some functions. +/ +/ 0: Full function. +/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename +/ are removed. +/ 2: f_opendir and f_readdir are removed in addition to level 1. +/ 3: f_lseek is removed in addition to level 2. */ + + +#define _USE_STRFUNC 2 /* 0, 1 or 2 */ +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + + +#define _USE_MKFS 1 /* 0 or 1 */ +/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ + + +#define _USE_FORWARD 0 /* 0 or 1 */ +/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ + + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/----------------------------------------------------------------------------*/ + +#define _CODE_PAGE 1252 +/* The _CODE_PAGE specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) +/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) +/ 949 - Korean (DBCS, OEM, Windows) +/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) +/ 1250 - Central Europe (Windows) +/ 1251 - Cyrillic (Windows) +/ 1252 - Latin 1 (Windows) +/ 1253 - Greek (Windows) +/ 1254 - Turkish (Windows) +/ 1255 - Hebrew (Windows) +/ 1256 - Arabic (Windows) +/ 1257 - Baltic (Windows) +/ 1258 - Vietnam (OEM, Windows) +/ 437 - U.S. (OEM) +/ 720 - Arabic (OEM) +/ 737 - Greek (OEM) +/ 775 - Baltic (OEM) +/ 850 - Multilingual Latin 1 (OEM) +/ 858 - Multilingual Latin 1 + Euro (OEM) +/ 852 - Latin 2 (OEM) +/ 855 - Cyrillic (OEM) +/ 866 - Russian (OEM) +/ 857 - Turkish (OEM) +/ 862 - Hebrew (OEM) +/ 874 - Thai (OEM, Windows) +/ 1 - ASCII only (Valid for non LFN cfg.) +*/ + + +#define _USE_LFN 0 /* 0, 1 or 2 */ +#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ +/* The _USE_LFN option switches the LFN support. +/ +/ 0: Disable LFN. _MAX_LFN and _LFN_UNICODE have no effect. +/ 1: Enable LFN with static working buffer on the bss. NOT REENTRANT. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ +/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. When enable LFN, +/ two Unicode handling functions ff_convert() and ff_wtoupper() must be added +/ to the project. */ + + +#define _LFN_UNICODE 0 /* 0 or 1 */ +/* To switch the character code set on FatFs API to Unicode, +/ enable LFN feature and set _LFN_UNICODE to 1. +*/ + + +#define _FS_RPATH 0 /* 0 or 1 */ +/* When _FS_RPATH is set to 1, relative path feature is enabled and f_chdir, +/ f_chdrive function are available. +/ Note that output of the f_readdir function is affected by this option. */ + + + +/*---------------------------------------------------------------------------/ +/ Physical Drive Configurations +/----------------------------------------------------------------------------*/ + +#define _DRIVES 2 +/* Number of volumes (logical drives) to be used. */ + + +#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ +/* Maximum sector size to be handled. +/ Always set 512 for memory card and hard disk but a larger value may be +/ required for floppy disk (512/1024) and optical disk (512/2048). +/ When _MAX_SS is larger than 512, GET_SECTOR_SIZE command must be implemented +/ to the disk_ioctl function. */ + + +#define _MULTI_PARTITION 0 /* 0 or 1 */ +/* When _MULTI_PARTITION is set to 0, each volume is bound to the same physical +/ drive number and can mount only first primary partition. When it is set to 1, +/ each volume is tied to the partitions listed in Drives[]. */ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/----------------------------------------------------------------------------*/ + +#define _WORD_ACCESS 0 /* 0 or 1 */ +/* The _WORD_ACCESS option defines which access method is used to the word +/ data on the FAT volume. +/ +/ 0: Byte-by-byte access. Always compatible with all platforms. +/ 1: Word access. Do not choose this unless following condition is met. +/ +/ When the byte order on the memory is big-endian or address miss-aligned +/ word access results incorrect behavior, the _WORD_ACCESS must be set to 0. +/ If it is not the case, the value can also be set to 1 to improve the +/ performance and code size. */ + + +#define _FS_REENTRANT 0 /* 0 or 1 */ +#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ +#define _SYNC_t HANDLE /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ +/* The _FS_REENTRANT option switches the reentrancy of the FatFs module. +/ +/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect. +/ 1: Enable reentrancy. Also user provided synchronization handlers, +/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj +/ function must be added to the project. */ + + +#endif /* _FFCONFIG */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/gd32vf103_it.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/gd32vf103_it.h new file mode 100644 index 0000000..91215b6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/gd32vf103_it.h @@ -0,0 +1,46 @@ +/*! + \file gd32vf103_it.h + \brief the header file of the ISR + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_IT_H +#define GD32VF103_IT_H + +#include "gd32vf103.h" + +/* function declarations */ +/* this function handles USB wakeup interrupt handler */ +void USBFS_WKUP_IRQHandler(void); +/* this function handles USBFS IRQ Handler */ +void USBFS_IRQHandler(void); + +#endif /* GD32VF103_IT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/integer.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/integer.h new file mode 100644 index 0000000..2741b70 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/integer.h @@ -0,0 +1,46 @@ +/*-------------------------------------------*/ +/* Integer type definitions for FatFs module */ +/*-------------------------------------------*/ + +#ifndef _INTEGER + +#if 0 +#include +#else + +#include "usb_conf.h" + +/* These types must be 16-bit, 32-bit or larger integer */ +typedef int INT; +typedef unsigned int UINT; + +/* These types must be 8-bit integer */ +typedef signed char CHAR; +typedef unsigned char UCHAR; +typedef unsigned char BYTE; + +/* These types must be 16-bit integer */ +typedef short SHORT; +typedef unsigned short USHORT; +typedef unsigned short WORD; +typedef unsigned short WCHAR; + +/* These types must be 32-bit integer */ +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long DWORD; + +/* Boolean type */ +// typedef enum { FALSE = 0, TRUE } BOOL; +#include +//typedef bool BOOL; +#ifndef FALSE +#define FALSE false +#define TRUE true +#endif + + +#endif + +#define _INTEGER +#endif diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/lcd_font.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/lcd_font.h new file mode 100644 index 0000000..00a44f2 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/lcd_font.h @@ -0,0 +1,45 @@ +/*! + \file lcd_font.h + \brief the header file of LCD font + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef LCD_FONT_H +#define LCD_FONT_H + +#include + +extern unsigned char const ascii_8x16[1536]; + +extern const uint16_t ASCII_Table_16x24[]; + +#endif /* LCD_FONT_H */ + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/lcd_log.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/lcd_log.h new file mode 100644 index 0000000..4f1fa8f --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/lcd_log.h @@ -0,0 +1,52 @@ +/*! + \file lcd_log.h + \brief the header file of LCD log + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "stdint.h" +#include "lcd_font.h" + +/* initialize the LCD log module */ +void lcd_log_init (void); +/* de-initialize the LCD log module */ +void lcd_log_deinit (void); +/* display the application header (title) on the LCD screen */ +void lcd_log_header_set (uint8_t *p_title, uint16_t start_x); +/* display the application footer (status) on the LCD screen */ +void lcd_log_footer_set (uint8_t *p_status, uint16_t start_x); +/* redirect the printf to the lcd */ +void lcd_log_print (uint8_t *p_str, uint16_t offset, uint16_t char_color); +/* clear the text zone */ +void lcd_log_text_zone_clear (uint16_t start_x, + uint16_t start_y, + uint16_t width, + uint16_t height); diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/msc_bbb.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/msc_bbb.h new file mode 100644 index 0000000..0e2e171 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/msc_bbb.h @@ -0,0 +1,69 @@ +/*! + \file msc_bbb.h + \brief definitions for the USB MSC BBB(bulk/bulk/bulk) protocol + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __MSC_BBB_H +#define __MSC_BBB_H + +#include "usb_ch9_std.h" + +#define BBB_CBW_SIGNATURE 0x43425355U +#define BBB_CSW_SIGNATURE 0x53425355U +#define BBB_CBW_LENGTH 31U +#define BBB_CSW_LENGTH 13U + +typedef struct { + uint32_t dCBWSignature; + uint32_t dCBWTag; + uint32_t dCBWDataTransferLength; + uint8_t bmCBWFlags; + uint8_t bCBWLUN; + uint8_t bCBWCBLength; + uint8_t CBWCB[16]; +}msc_bbb_cbw; + +typedef struct { + uint32_t dCSWSignature; + uint32_t dCSWTag; + uint32_t dCSWDataResidue; + uint8_t bCSWStatus; +}msc_bbb_csw; + +/* CSW command status */ +enum msc_csw_status { + CSW_CMD_PASSED = 0, + CSW_CMD_FAILED, + CSW_PHASE_ERROR +}; + +#endif /* __MSC_BBB_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/msc_scsi.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/msc_scsi.h new file mode 100644 index 0000000..359aea6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/msc_scsi.h @@ -0,0 +1,117 @@ +/*! + \file msc_scsi.h + \brief definitions for the USB MSC SCSI commands + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __MSC_SCSI_H +#define __MSC_SCSI_H + +#include "usb_ch9_std.h" + +/* SCSI commands */ +#define SCSI_FORMAT_UNIT 0x04U +#define SCSI_INQUIRY 0x12U +#define SCSI_MODE_SELECT6 0x15U +#define SCSI_MODE_SELECT10 0x55U +#define SCSI_MODE_SENSE6 0x1AU +#define SCSI_READ_TOC_DATA 0x43U +#define SCSI_MODE_SENSE10 0x5AU +#define SCSI_ALLOW_MEDIUM_REMOVAL 0x1EU +#define SCSI_READ6 0x08U +#define SCSI_READ10 0x28U +#define SCSI_READ12 0xA8U +#define SCSI_READ16 0x88U + +#define SCSI_READ_CAPACITY10 0x25U +#define SCSI_READ_CAPACITY16 0x9EU + +#define SCSI_REQUEST_SENSE 0x03U +#define SCSI_START_STOP_UNIT 0x1BU +#define SCSI_TEST_UNIT_READY 0x00U +#define SCSI_WRITE6 0x0AU +#define SCSI_WRITE10 0x2AU +#define SCSI_WRITE12 0xAAU +#define SCSI_WRITE16 0x8AU + +#define SCSI_VERIFY10 0x2FU +#define SCSI_VERIFY12 0xAFU +#define SCSI_VERIFY16 0x8FU + +#define SCSI_SEND_DIAGNOSTIC 0x1DU +#define SCSI_READ_FORMAT_CAPACITIES 0x23U + +#define INVALID_CDB 0x20U +#define INVALID_FIELED_IN_COMMAND 0x24U +#define PARAMETER_LIST_LENGTH_ERROR 0x1AU +#define INVALID_FIELD_IN_PARAMETER_LIST 0x26U +#define ADDRESS_OUT_OF_RANGE 0x21U +#define MEDIUM_NOT_PRESENT 0x3AU +#define MEDIUM_HAVE_CHANGED 0x28U +#define WRITE_PROTECTED 0x27U +#define UNRECOVERED_READ_ERROR 0x11U +#define WRITE_FAULT 0x03U + +#define READ_FORMAT_CAPACITY_DATA_LEN 0x0CU +#define READ_CAPACITY10_DATA_LEN 0x08U +#define MODE_SENSE10_DATA_LEN 0x08U +#define MODE_SENSE6_DATA_LEN 0x04U +#define READ_TOC_CMD_LEN 0x14U +#define REQUEST_SENSE_DATA_LEN 0x12U +#define STANDARD_INQUIRY_DATA_LEN 0x24U +#define BLKVFY 0x04U + +enum sense_state { + NO_SENSE = 0U, + RECOVERED_ERROR, + NOT_READY, + MEDIUM_ERROR, + HARDWARE_ERROR, + ILLEGAL_REQUEST, + UNIT_ATTENTION, + DATA_PROTECT, + BLANK_CHECK, + VENDOR_SPECIFIC, + COPY_ABORTED, + ABORTED_COMMAND, + RESERVED, + VOLUME_OVERFLOW, + MISCOMPARE +}; + +typedef struct { + uint8_t SenseKey; + uint32_t Information; + uint8_t ASC; + uint8_t ASCQ; +} msc_scsi_sense; + +#endif /* __MSC_SCSI_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usb_conf.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usb_conf.h new file mode 100644 index 0000000..3107009 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usb_conf.h @@ -0,0 +1,92 @@ +/*! + \file usb_conf.h + \brief general low level driver configuration + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_CONF_H +#define __USB_CONF_H + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" +#include "gd32vf103V_lcd_eval.h" + +#include + +#ifdef USE_USB_FS + #define USB_FS_CORE +#endif + +#ifdef USB_FS_CORE + #define USB_RX_FIFO_FS_SIZE 128 + #define USB_HTX_NPFIFO_FS_SIZE 96 + #define USB_HTX_PFIFO_FS_SIZE 96 +#endif + +#define USB_SOF_OUTPUT 0 +#define USB_LOW_POWER 0 + +#define USE_HOST_MODE +//#define USE_DEVICE_MODE +//#define USE_OTG_MODE + +#ifndef USB_FS_CORE + #ifndef USB_HS_CORE + #error "USB_HS_CORE or USB_FS_CORE should be defined" + #endif +#endif + +#ifndef USE_DEVICE_MODE + #ifndef USE_HOST_MODE + #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" + #endif +#endif + +#ifndef USE_USB_HS + #ifndef USE_USB_FS + #error "USE_USB_HS or USE_USB_FS should be defined" + #endif +#endif + +/****************** C Compilers dependant keywords ****************************/ +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + #if defined (__GNUC__) /* GNU Compiler */ + #define __ALIGN_END __attribute__ ((aligned(4))) + #define __ALIGN_BEGIN + #endif /* __GNUC__ */ +#else + #define __ALIGN_BEGIN + #define __ALIGN_END +#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ + +#endif /* __USB_CONF_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usb_msc.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usb_msc.h new file mode 100644 index 0000000..485e747 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usb_msc.h @@ -0,0 +1,66 @@ +/*! + \file usb_msc.h + \brief definitions for the USB MSC class + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_MSC_H +#define __USB_MSC_H + +#include "usb_ch9_std.h" + +/* mass storage device class code */ +#define USB_CLASS_MSC 0x08U + +/* mass storage subclass code */ +#define USB_MSC_SUBCLASS_RBC 0x01U +#define USB_MSC_SUBCLASS_ATAPI 0x02U +#define USB_MSC_SUBCLASS_UFI 0x04U +#define USB_MSC_SUBCLASS_SCSI 0x06U +#define USB_MSC_SUBCLASS_LOCKABLE 0x07U +#define USB_MSC_SUBCLASS_IEEE1667 0x08U + +/* mass storage interface class control protocol codes */ +#define USB_MSC_PROTOCOL_CBI 0x00U +#define USB_MSC_PROTOCOL_CBI_ALT 0x01U +#define USB_MSC_PROTOCOL_BBB 0x50U + +/* mass storage request codes */ +#define USB_MSC_REQ_CODES_ADSC 0x00U +#define USB_MSC_REQ_CODES_GET 0xFCU +#define USB_MSC_REQ_CODES_PUT 0xFDU +#define USB_MSC_REQ_CODES_GML 0xFEU +#define USB_MSC_REQ_CODES_BOMSR 0xFFU + +#define BBB_GET_MAX_LUN 0xFEU +#define BBB_RESET 0xFFU + +#endif /* __USB_MSC_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usbh_conf.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usbh_conf.h new file mode 100644 index 0000000..ae12fd4 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usbh_conf.h @@ -0,0 +1,42 @@ +/*! + \file usbh_conf.h + \brief general low level driver configuration + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_CONF_H +#define __USBH_CONF_H + +#define USBH_MAX_EP_NUM 2 +#define USBH_MAX_INTERFACES_NUM 2 +#define USBH_MSC_MPS_SIZE 0x200 + +#endif /* __USBH_CONF_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usbh_msc_bbb.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usbh_msc_bbb.h new file mode 100644 index 0000000..42d71ab --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usbh_msc_bbb.h @@ -0,0 +1,127 @@ +/*! + \file usbh_msc_bbb.h + \brief header file for usbh_msc_bbb.c + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_MSC_BBB_H +#define __USBH_MSC_BBB_H + +#include "usbh_enum.h" +#include "msc_bbb.h" + +typedef union { + msc_bbb_cbw field; + + uint8_t CBWArray[31]; +}usbh_cbw_pkt; + +typedef union { + msc_bbb_csw field; + + uint8_t CSWArray[13]; +}usbh_csw_pkt; + +enum usbh_msc_state { + USBH_MSC_BOT_INIT_STATE = 0, + USBH_MSC_BOT_RESET, + USBH_MSC_GET_MAX_LUN, + USBH_MSC_TEST_UNIT_READY, + USBH_MSC_READ_CAPACITY10, + USBH_MSC_MODE_SENSE6, + USBH_MSC_REQUEST_SENSE, + USBH_MSC_BOT_USB_TRANSFERS, + USBH_MSC_DEFAULT_APPLI_STATE, + USBH_MSC_CTRL_ERROR_STATE, + USBH_MSC_UNRECOVERED_STATE +}; + +enum msc_bot_state { + USBH_MSC_SEND_CBW = 1U, + USBH_MSC_SENT_CBW, + USBH_MSC_BOT_DATAIN_STATE, + USBH_MSC_BOT_DATAOUT_STATE, + USBH_MSC_RECEIVE_CSW_STATE, + USBH_MSC_DECODE_CSW, + USBH_MSC_BOT_ERROR_IN, + USBH_MSC_BOT_ERROR_OUT +}; + +typedef struct { + uint8_t msc_state; + uint8_t msc_state_bkp; + uint8_t msc_state_current; + uint8_t cmd_state_machine; + uint8_t bot_state; + uint8_t bot_state_bkp; + + uint8_t *xfer_buf; + uint16_t data_len; + + uint8_t bot_xfer_status; +} usbh_botxfer; + + +#define USBH_MSC_BOT_CBW_TAG 0x20304050 + +#define USBH_MSC_CSW_MAX_LENGTH 63 + +#define USBH_MSC_SEND_CSW_DISABLE 0 +#define USBH_MSC_SEND_CSW_ENABLE 1 + +#define USBH_MSC_DIR_IN 0 +#define USBH_MSC_DIR_OUT 1 +#define USBH_MSC_BOTH_DIR 2 + +#define USBH_MSC_PAGE_LENGTH 512 + +#define CBW_CB_LENGTH 16 +#define CBW_LENGTH 10 +#define CBW_LENGTH_TEST_UNIT_READY 6 + +#define MAX_BULK_STALL_COUNT_LIMIT 0x04 /* If STALL is seen on Bulk + Endpoint continously, this means + that device and Host has phase error + Hence a Reset is needed */ + +extern usbh_botxfer msc_botxfer_param; +extern usbh_cbw_pkt msc_cbw_data; +extern usbh_csw_pkt msc_csw_data; + +void usbh_msc_init (usb_core_driver *pudev); + +void usbh_msc_botxfer (usb_core_driver *pudev, usbh_host *puhost); + +uint8_t usbh_msc_csw_decode (usb_core_driver *pudev, usbh_host *puhost); + +usbh_status usbh_msc_bot_abort (usb_core_driver *pudev, usbh_host *puhost, uint8_t direction); + +#endif /* __USBH_MSC_BOT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usbh_msc_core.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usbh_msc_core.h new file mode 100644 index 0000000..a14f67b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usbh_msc_core.h @@ -0,0 +1,58 @@ +/*! + \file usbh_msc_core.h + \brief header file for the usbh_msc_core.c + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_MSC_CORE_H +#define __USBH_MSC_CORE_H + +#include "usb_msc.h" +#include "usbh_msc_scsi.h" +#include "usbh_msc_bbb.h" + +/* structure for msc process */ +typedef struct { + uint8_t hc_num_in; + uint8_t hc_num_out; + uint8_t msc_bulk_epin; + uint8_t msc_bulk_epout; + uint16_t msc_bulk_epinsize; + uint16_t msc_bulk_epoutsize; + uint8_t buf[USBH_MSC_MPS_SIZE]; + uint8_t max_lun; +} usbh_msc_machine; + +extern usbh_class_cb usbh_msc_cb; +extern usbh_msc_machine msc_machine; +extern uint8_t msc_error_count; + +#endif /* __USBH_MSC_CORE_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usbh_msc_scsi.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usbh_msc_scsi.h new file mode 100644 index 0000000..1b5d651 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usbh_msc_scsi.h @@ -0,0 +1,91 @@ +/*! + \file usbh_msc_scsi.h + \brief header file for usbh_msc_scsi.c + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_MSC_SCSI_H +#define __USBH_MSC_SCSI_H + +#include "msc_scsi.h" +#include "usbh_enum.h" + +typedef enum +{ + USBH_MSC_OK = 0U, + USBH_MSC_FAIL = 1U, + USBH_MSC_PHASE_ERROR = 2U, + USBH_MSC_BUSY = 3U +}usbh_msc_status; + +enum cmd_states { + CMD_UNINITIALIZED_STATE = 0, + CMD_SEND_STATE, + CMD_WAIT_STATUS +}; + +typedef struct +{ + uint32_t msc_capacity; + uint32_t msc_sense_key; + uint16_t msc_page_len; + uint8_t msc_write_protect; +}usbh_msc_parameter; + +#define DESC_REQUEST_SENSE 0x00U +#define ALLOCATION_LENGTH_REQUEST_SENSE 63U +#define XFER_LEN_MODE_SENSE6 63U + +#define MASK_MODE_SENSE_WRITE_PROTECT 0x80U +#define MODE_SENSE_PAGE_CONTROL_FIELD 0x00U +#define MODE_SENSE_PAGE_CODE 0x3FU +#define DISK_WRITE_PROTECTED 0x01U + +extern usbh_msc_parameter usbh_msc_param; + +uint8_t usbh_msc_test_unitready (usb_core_driver *pudev); +uint8_t usbh_msc_read_capacity10 (usb_core_driver *pudev); +uint8_t usbh_msc_mode_sense6 (usb_core_driver *pudev); +uint8_t usbh_msc_request_sense (usb_core_driver *pudev); + +uint8_t usbh_msc_write10 (usb_core_driver *pudev, + uint8_t *data_buf, + uint32_t addr, + uint32_t byte_num); + +uint8_t usbh_msc_read10 (usb_core_driver *pudev, + uint8_t *data_buf, + uint32_t addr, + uint32_t byte_num); + +void usbh_msc_state_machine (usb_core_driver *pudev); + +#endif /* __USBH_MSC_SCSI_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usbh_usr.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usbh_usr.h new file mode 100644 index 0000000..96988fd --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Include/usbh_usr.h @@ -0,0 +1,94 @@ +/*! + \file usbh_usr.h + \brief user application layer header file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef USBH_USR_H +#define USBH_USR_H + +#include "ff.h" +#include "usbh_core.h" +#include "usb_conf.h" +#include "usbh_msc_core.h" +#include + +extern usbh_user_cb user_callback_funs; + +/* state machine for the usbh_usr_application_state */ +#define USBH_USR_FS_INIT 0 +#define USBH_USR_FS_READLIST 1 +#define USBH_USR_FS_WRITEFILE 2 +#define USBH_USR_FS_DEMOEND 3 + +extern uint8_t usbh_usr_application_state; + +/* function declarations */ +/* user operation for host-mode initialization */ +void usbh_user_init (void); +/* de-int user state and associated variables */ +void usbh_user_deinit (void); +/* user operation for device attached */ +void usbh_user_device_connected (void); +/* user operation for reset USB Device */ +void usbh_user_device_reset (void); +/* user operation for device disconnect event */ +void usbh_user_device_disconnected (void); +/* user operation for device overcurrent detection event */ +void usbh_user_over_current_detected (void); +/* user operation for detectting device speed */ +void usbh_user_device_speed_detected (uint32_t device_speed); +/* user operation when device descriptor is available */ +void usbh_user_device_desc_available (void *dev_desc); +/* USB device is successfully assigned the address */ +void usbh_user_device_address_assigned (void); +/* user operation when configuration descriptor is available */ +void usbh_user_configuration_descavailable (usb_desc_config *cfg_desc, + usb_desc_itf *itf_desc, + usb_desc_ep *ep_desc); +/* user operation when manufacturer string exists */ +void usbh_user_manufacturer_string (void *mfc_string); +/* user operation when product string exists */ +void usbh_user_product_string (void *prod_string); +/* user operatin when serialNum string exists */ +void usbh_user_serialnum_string (void *serialnum_string); +/* user response request is displayed to ask for application jump to class */ +void usbh_user_enumeration_finish (void); +/* user action for application state entry */ +usbh_user_status usbh_user_userinput (void); +/* user operation when device is not supported */ +void usbh_user_device_not_supported (void); +/* user operation when unrecoveredError happens */ +void usbh_user_unrecovered_error (void); +/* demo application for mass storage */ +int usbh_usr_msc_application (void); + +#endif /* USBH_USR_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/app.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/app.c new file mode 100644 index 0000000..6521e26 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/app.c @@ -0,0 +1,78 @@ +/*! + \file main.c + \brief this file realizes the MSC host + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "drv_usb_core.h" +#include "usbh_usr.h" +#include "usbh_msc_core.h" +#include "gd32vf103v_eval.h" +#include +#include +#include + +usb_core_driver usbh_msc_core; + +usbh_host usb_host = { + .class_cb = &usbh_msc_cb, + .usr_cb = &user_callback_funs +}; + +/** + * @brief Main routine for HID mouse / keyboard class application + * @param None + * @retval None + */ +int main(void) +{ + eclic_global_interrupt_enable(); + + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL2_PRIO2); + + usb_rcu_config(); + + usb_timer_init(); + + /* configure GPIO pin used for switching VBUS power and charge pump I/O */ + usb_vbus_config(); + + usbh_init (&usbh_msc_core, USB_CORE_ENUM_FS, &usb_host); + + /* enable interrupts */ + usb_intr_config(); + + while (1) { + /* Host state handler */ + usbh_core_task (&usbh_msc_core, &usb_host); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/fattime.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/fattime.c new file mode 100644 index 0000000..d9f2ebc --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/fattime.c @@ -0,0 +1,11 @@ + + +#include "integer.h" +#include "fattime.h" + + +DWORD get_fattime (void) +{ + return 0; +} + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/ff.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/ff.c new file mode 100644 index 0000000..de3bae1 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/ff.c @@ -0,0 +1,3152 @@ +/*----------------------------------------------------------------------------/ +/ FatFs - FAT file system module R0.07e (C)ChaN, 2009 +/-----------------------------------------------------------------------------/ +/ FatFs module is a generic FAT file system module for small embedded systems. +/ This is a free software that opened for education, research and commercial +/ developments under license policy of following terms. +/ +/ Copyright (C) 2009, ChaN, all right reserved. +/ +/ * The FatFs module is a free software and there is NO WARRANTY. +/ * No restriction on use. You can use, modify and redistribute it for +/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY. +/ * Redistributions of source code must retain the above copyright notice. +/ +/-----------------------------------------------------------------------------/ +/ Feb 26,'06 R0.00 Prototype. +/ +/ Apr 29,'06 R0.01 First stable version. +/ +/ Jun 01,'06 R0.02 Added FAT12 support. +/ Removed unbuffered mode. +/ Fixed a problem on small (<32M) partition. +/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM). +/ +/ Sep 22,'06 R0.03 Added f_rename(). +/ Changed option _FS_MINIMUM to _FS_MINIMIZE. +/ Dec 11,'06 R0.03a Improved cluster scan algorithm to write files fast. +/ Fixed f_mkdir() creates incorrect directory on FAT32. +/ +/ Feb 04,'07 R0.04 Supported multiple drive system. +/ Changed some interfaces for multiple drive system. +/ Changed f_mountdrv() to f_mount(). +/ Added f_mkfs(). +/ Apr 01,'07 R0.04a Supported multiple partitions on a physical drive. +/ Added a capability of extending file size to f_lseek(). +/ Added minimization level 3. +/ Fixed an endian sensitive code in f_mkfs(). +/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG. +/ Added FSInfo support. +/ Fixed DBCS name can result FR_INVALID_NAME. +/ Fixed short seek (<= csize) collapses the file object. +/ +/ Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs(). +/ Fixed f_mkfs() on FAT32 creates incorrect FSInfo. +/ Fixed f_mkdir() on FAT32 creates incorrect directory. +/ Feb 03,'08 R0.05a Added f_truncate() and f_utime(). +/ Fixed off by one error at FAT sub-type determination. +/ Fixed btr in f_read() can be mistruncated. +/ Fixed cached sector is not flushed when create and close +/ without write. +/ +/ Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets(). +/ Improved performance of f_lseek() on moving to the same +/ or following cluster. +/ +/ Apr 01,'09 R0.07 Merged Tiny-FatFs as a buffer configuration option. +/ Added long file name support. +/ Added multiple code page support. +/ Added re-entrancy for multitask operation. +/ Added auto cluster size selection to f_mkfs(). +/ Added rewind option to f_readdir(). +/ Changed result code of critical errors. +/ Renamed string functions to avoid name collision. +/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg. +/ Added multiple sector size support. +/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error. +/ Fixed wrong cache control in f_lseek(). +/ Added relative path feature. +/ Added f_chdir() and f_chdrive(). +/ Added proper case conversion to extended char. +/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h. +/ Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH. +/ Fixed name matching error on the 13 char boundary. +/ Added a configuration option, _LFN_UNICODE. +/ Changed f_readdir() to return the SFN with always upper +/ case on non-LFN cfg. +/---------------------------------------------------------------------------*/ + +#include "ff.h" /* FatFs configurations and declarations */ +#include "diskio.h" /* Declarations of low level disk I/O functions */ + + +/*-------------------------------------------------------------------------- + + Module Private Definitions + +---------------------------------------------------------------------------*/ + +#if _FATFS != 0x007E +#error Wrong include file (ff.h). +#endif + +#if _FS_REENTRANT +#if _USE_LFN == 1 +#error Static LFN work area must not be used in re-entrant configuration. +#endif +#define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; } +#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; } + +#else +#define ENTER_FF(fs) +#define LEAVE_FF(fs, res) return res + +#endif + +#define ABORT(fs, res) { fp->flag |= FA__ERROR; LEAVE_FF(fs, res); } + +#ifndef NULL +#define NULL 0 +#endif + +/* Name status flags */ +#define NS 11 /* Offset of name status byte */ +#define NS_LOSS 0x01 /* Out of 8.3 format */ +#define NS_LFN 0x02 /* Force to create LFN entry */ +#define NS_LAST 0x04 /* Last segment */ +#define NS_BODY 0x08 /* Lower case flag (body) */ +#define NS_EXT 0x10 /* Lower case flag (ext) */ +#define NS_DOT 0x20 /* Dot entry */ + + + + +/*-------------------------------------------------------------------------- + + Private Work Area + +---------------------------------------------------------------------------*/ + +#if _DRIVES < 1 || _DRIVES > 9 +#error Number of drives must be 1-9. +#endif +static +FATFS *FatFs[_DRIVES]; /* Pointer to the file system objects (logical drives) */ + +static +WORD Fsid; /* File system mount ID */ + +#if _FS_RPATH +static +BYTE Drive; /* Current drive */ +#endif + + +#if _USE_LFN == 1 /* LFN with static LFN working buffer */ +static +WCHAR LfnBuf[_MAX_LFN + 1]; +#define NAMEBUF(sp,lp) BYTE sp[12]; WCHAR *lp = LfnBuf +#define INITBUF(dj,sp,lp) dj.fn = sp; dj.lfn = lp + +#elif _USE_LFN > 1 /* LFN with dynamic LFN working buffer */ +#define NAMEBUF(sp,lp) BYTE sp[12]; WCHAR lbuf[_MAX_LFN + 1], *lp = lbuf +#define INITBUF(dj,sp,lp) dj.fn = sp; dj.lfn = lp + +#else /* No LFN */ +#define NAMEBUF(sp,lp) BYTE sp[12] +#define INITBUF(dj,sp,lp) dj.fn = sp + +#endif + + + + +/*-------------------------------------------------------------------------- + + Module Private Functions + +---------------------------------------------------------------------------*/ + + +/*-----------------------------------------------------------------------*/ +/* String functions */ +/*-----------------------------------------------------------------------*/ + +/* Copy memory to memory */ +static +void mem_cpy (void* dst, const void* src, int cnt) { + char *d = (char*)dst; + const char *s = (const char *)src; + while (cnt--) *d++ = *s++; +} + +/* Fill memory */ +static +void mem_set (void* dst, int val, int cnt) { + char *d = (char*)dst; + while (cnt--) *d++ = (char)val; +} + +/* Compare memory to memory */ +static +int mem_cmp (const void* dst, const void* src, int cnt) { + const char *d = (const char *)dst, *s = (const char *)src; + int r = 0; + while (cnt-- && (r = *d++ - *s++) == 0) ; + return r; +} + +/* Check if chr is contained in the string */ +static +int chk_chr (const char* str, int chr) { + while (*str && *str != chr) str++; + return *str; +} + + + +/*-----------------------------------------------------------------------*/ +/* Request/Release grant to access the volume */ +/*-----------------------------------------------------------------------*/ +#if _FS_REENTRANT + +static +BOOL lock_fs ( + FATFS *fs /* File system object */ +) +{ + return ff_req_grant(fs->sobj); +} + + +static +void unlock_fs ( + FATFS *fs, /* File system object */ + FRESULT res /* Result code to be returned */ +) +{ + if (res != FR_NOT_ENABLED && + res != FR_INVALID_DRIVE && + res != FR_INVALID_OBJECT && + res != FR_TIMEOUT) { + ff_rel_grant(fs->sobj); + } +} +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Change window offset */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT move_window ( + FATFS *fs, /* File system object */ + DWORD sector /* Sector number to make appearance in the fs->win[] */ +) /* Move to zero only writes back dirty window */ +{ + DWORD wsect; + + + wsect = fs->winsect; + if (wsect != sector) { /* Changed current window */ +#if !_FS_READONLY + if (fs->wflag) { /* Write back dirty window if needed */ + if (disk_write(fs->drive, fs->win, wsect, 1) != RES_OK) + return FR_DISK_ERR; + fs->wflag = 0; + if (wsect < (fs->fatbase + fs->sects_fat)) { /* In FAT area */ + BYTE nf; + for (nf = fs->n_fats; nf > 1; nf--) { /* Reflect the change to all FAT copies */ + wsect += fs->sects_fat; + disk_write(fs->drive, fs->win, wsect, 1); + } + } + } +#endif + if (sector) { + if (disk_read(fs->drive, fs->win, sector, 1) != RES_OK) + return FR_DISK_ERR; + fs->winsect = sector; + } + } + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Clean-up cached data */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT sync ( /* FR_OK: successful, FR_DISK_ERR: failed */ + FATFS *fs /* File system object */ +) +{ + FRESULT res; + + + res = move_window(fs, 0); + if (res == FR_OK) { + /* Update FSInfo sector if needed */ + if (fs->fs_type == FS_FAT32 && fs->fsi_flag) { + fs->winsect = 0; + mem_set(fs->win, 0, 512); + ST_WORD(fs->win+BS_55AA, 0xAA55); + ST_DWORD(fs->win+FSI_LeadSig, 0x41615252); + ST_DWORD(fs->win+FSI_StrucSig, 0x61417272); + ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust); + ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust); + disk_write(fs->drive, fs->win, fs->fsi_sector, 1); + fs->fsi_flag = 0; + } + /* Make sure that no pending write process in the physical drive */ + if (disk_ioctl(fs->drive, CTRL_SYNC, (void*)NULL) != RES_OK) + res = FR_DISK_ERR; + } + + return res; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* FAT access - Read value of a FAT entry */ +/*-----------------------------------------------------------------------*/ + + +DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, Else:Cluster status */ + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to get the link information */ +) +{ + UINT wc, bc; + DWORD fsect; + + + if (clst < 2 || clst >= fs->max_clust) /* Range check */ + return 1; + + fsect = fs->fatbase; + switch (fs->fs_type) { + case FS_FAT12 : + bc = clst; bc += bc / 2; + if (move_window(fs, fsect + (bc / SS(fs)))) break; + wc = fs->win[bc & (SS(fs) - 1)]; bc++; + if (move_window(fs, fsect + (bc / SS(fs)))) break; + wc |= (WORD)fs->win[bc & (SS(fs) - 1)] << 8; + return (clst & 1) ? (wc >> 4) : (wc & 0xFFF); + + case FS_FAT16 : + if (move_window(fs, fsect + (clst / (SS(fs) / 2)))) break; + return LD_WORD(&fs->win[((WORD)clst * 2) & (SS(fs) - 1)]); + + case FS_FAT32 : + if (move_window(fs, fsect + (clst / (SS(fs) / 4)))) break; + return LD_DWORD(&fs->win[((WORD)clst * 4) & (SS(fs) - 1)]) & 0x0FFFFFFF; + } + + return 0xFFFFFFFF; /* An error occurred at the disk I/O layer */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT access - Change value of a FAT entry */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY + +FRESULT put_fat ( + FATFS *fs, /* File system object */ + DWORD clst, /* Cluster# to be changed in range of 2 to fs->max_clust - 1 */ + DWORD val /* New value to mark the cluster */ +) +{ + UINT bc; + BYTE *p; + DWORD fsect; + FRESULT res; + + + if (clst < 2 || clst >= fs->max_clust) { /* Range check */ + res = FR_INT_ERR; + + } else { + fsect = fs->fatbase; + switch (fs->fs_type) { + case FS_FAT12 : + bc = clst; bc += bc / 2; + res = move_window(fs, fsect + (bc / SS(fs))); + if (res != FR_OK) break; + p = &fs->win[bc & (SS(fs) - 1)]; + *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; + bc++; + fs->wflag = 1; + res = move_window(fs, fsect + (bc / SS(fs))); + if (res != FR_OK) break; + p = &fs->win[bc & (SS(fs) - 1)]; + *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); + break; + + case FS_FAT16 : + res = move_window(fs, fsect + (clst / (SS(fs) / 2))); + if (res != FR_OK) break; + ST_WORD(&fs->win[((WORD)clst * 2) & (SS(fs) - 1)], (WORD)val); + break; + + case FS_FAT32 : + res = move_window(fs, fsect + (clst / (SS(fs) / 4))); + if (res != FR_OK) break; + ST_DWORD(&fs->win[((WORD)clst * 4) & (SS(fs) - 1)], val); + break; + + default : + res = FR_INT_ERR; + } + fs->wflag = 1; + } + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Remove a cluster chain */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT remove_chain ( + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to remove a chain from */ +) +{ + FRESULT res; + DWORD nxt; + + + if (clst < 2 || clst >= fs->max_clust) { /* Check the range of cluster# */ + res = FR_INT_ERR; + + } else { + res = FR_OK; + while (clst < fs->max_clust) { /* Not a last link? */ + nxt = get_fat(fs, clst); /* Get cluster status */ + if (nxt == 0) break; /* Empty cluster? */ + if (nxt == 1) { res = FR_INT_ERR; break; } /* Internal error? */ + if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } /* Disk error? */ + res = put_fat(fs, clst, 0); /* Mark the cluster "empty" */ + if (res != FR_OK) break; + if (fs->free_clust != 0xFFFFFFFF) { /* Update FSInfo */ + fs->free_clust++; + fs->fsi_flag = 1; + } + clst = nxt; /* Next cluster */ + } + } + + return res; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Stretch or Create a cluster chain */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */ + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to stretch. 0 means create a new chain. */ +) +{ + DWORD cs, ncl, scl, mcl; + + + mcl = fs->max_clust; + if (clst == 0) { /* Create new chain */ + scl = fs->last_clust; /* Get suggested start point */ + if (scl == 0 || scl >= mcl) scl = 1; + } + else { /* Stretch existing chain */ + cs = get_fat(fs, clst); /* Check the cluster status */ + if (cs < 2) return 1; /* It is an invalid cluster */ + if (cs < mcl) return cs; /* It is already followed by next cluster */ + scl = clst; + } + + ncl = scl; /* Start cluster */ + for (;;) { + ncl++; /* Next cluster */ + if (ncl >= mcl) { /* Wrap around */ + ncl = 2; + if (ncl > scl) return 0; /* No free cluster */ + } + cs = get_fat(fs, ncl); /* Get the cluster status */ + if (cs == 0) break; /* Found a free cluster */ + if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */ + return cs; + if (ncl == scl) return 0; /* No free cluster */ + } + + if (put_fat(fs, ncl, 0x0FFFFFFF)) /* Mark the new cluster "in use" */ + return 0xFFFFFFFF; + if (clst != 0) { /* Link it to the previous one if needed */ + if (put_fat(fs, clst, ncl)) + return 0xFFFFFFFF; + } + + fs->last_clust = ncl; /* Update FSINFO */ + if (fs->free_clust != 0xFFFFFFFF) { + fs->free_clust--; + fs->fsi_flag = 1; + } + + return ncl; /* Return new cluster number */ +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Get sector# from cluster# */ +/*-----------------------------------------------------------------------*/ + + +DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */ + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to be converted */ +) +{ + clst -= 2; + if (clst >= (fs->max_clust - 2)) return 0; /* Invalid cluster# */ + return clst * fs->csize + fs->database; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Seek directory index */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_seek ( + DIR *dj, /* Pointer to directory object */ + WORD idx /* Directory index number */ +) +{ + DWORD clst; + WORD ic; + + + dj->index = idx; + clst = dj->sclust; + if (clst == 1 || clst >= dj->fs->max_clust) /* Check start cluster range */ + return FR_INT_ERR; + if (!clst && dj->fs->fs_type == FS_FAT32) /* Replace cluster# 0 with root cluster# if in FAT32 */ + clst = dj->fs->dirbase; + + if (clst == 0) { /* Static table */ + dj->clust = clst; + if (idx >= dj->fs->n_rootdir) /* Index is out of range */ + return FR_INT_ERR; + dj->sect = dj->fs->dirbase + idx / (SS(dj->fs) / 32); /* Sector# */ + } + else { /* Dynamic table */ + ic = SS(dj->fs) / 32 * dj->fs->csize; /* Entries per cluster */ + while (idx >= ic) { /* Follow cluster chain */ + clst = get_fat(dj->fs, clst); /* Get next cluster */ + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + if (clst < 2 || clst >= dj->fs->max_clust) /* Reached to end of table or int error */ + return FR_INT_ERR; + idx -= ic; + } + dj->clust = clst; + dj->sect = clust2sect(dj->fs, clst) + idx / (SS(dj->fs) / 32); /* Sector# */ + } + + dj->dir = dj->fs->win + (idx % (SS(dj->fs) / 32)) * 32; /* Ptr to the entry in the sector */ + + return FR_OK; /* Seek succeeded */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Move directory index next */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_next ( /* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:EOT and could not streach */ + DIR *dj, /* Pointer to directory object */ + bool streach /* FALSE: Do not stretch table, TRUE: Stretch table if needed */ +) +{ + DWORD clst; + WORD i; + + + i = dj->index + 1; + if (!i || !dj->sect) /* Report EOT when index has reached 65535 */ + return FR_NO_FILE; + + if (!(i % (SS(dj->fs) / 32))) { /* Sector changed? */ + dj->sect++; /* Next sector */ + + if (dj->clust == 0) { /* Static table */ + if (i >= dj->fs->n_rootdir) /* Report EOT when end of table */ + return FR_NO_FILE; + } + else { /* Dynamic table */ + if (((i / (SS(dj->fs) / 32)) & (dj->fs->csize - 1)) == 0) { /* Cluster changed? */ + clst = get_fat(dj->fs, dj->clust); /* Get next cluster */ + if (clst <= 1) return FR_INT_ERR; + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; + if (clst >= dj->fs->max_clust) { /* When it reached end of dynamic table */ +#if !_FS_READONLY + BYTE c; + if (!streach) return FR_NO_FILE; /* When do not stretch, report EOT */ + clst = create_chain(dj->fs, dj->clust); /* Stretch cluster chain */ + if (clst == 0) return FR_DENIED; /* No free cluster */ + if (clst == 1) return FR_INT_ERR; + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; + /* Clean-up streached table */ + if (move_window(dj->fs, 0)) return FR_DISK_ERR; /* Flush active window */ + mem_set(dj->fs->win, 0, SS(dj->fs)); /* Clear window buffer */ + dj->fs->winsect = clust2sect(dj->fs, clst); /* Cluster start sector */ + for (c = 0; c < dj->fs->csize; c++) { /* Fill the new cluster with 0 */ + dj->fs->wflag = 1; + if (move_window(dj->fs, 0)) return FR_DISK_ERR; + dj->fs->winsect++; + } + dj->fs->winsect -= c; /* Rewind window address */ +#else + return FR_NO_FILE; /* Report EOT */ +#endif + } + dj->clust = clst; /* Initialize data for new cluster */ + dj->sect = clust2sect(dj->fs, clst); + } + } + } + + dj->index = i; + dj->dir = dj->fs->win + (i % (SS(dj->fs) / 32)) * 32; + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +static +const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN chars in the directory entry */ + + +static +BOOL cmp_lfn ( /* TRUE:Matched, FALSE:Not matched */ + WCHAR *lfnbuf, /* Pointer to the LFN to be compared */ + BYTE *dir /* Pointer to the directory entry containing a part of LFN */ +) +{ + int i, s; + WCHAR wc, uc; + + + i = ((dir[LDIR_Ord] & 0xBF) - 1) * 13; /* Get offset in the LFN buffer */ + s = 0; wc = 1; + do { + uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ + if (wc) { /* Last char has not been processed */ + wc = ff_wtoupper(uc); /* Convert it to upper case */ + if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++])) /* Compare it */ + return FALSE; /* Not matched */ + } else { + if (uc != 0xFFFF) return FALSE; /* Check filler */ + } + } while (++s < 13); /* Repeat until all chars in the entry are checked */ + + if ((dir[LDIR_Ord] & 0x40) && wc && lfnbuf[i]) /* Last segment matched but different length */ + return FALSE; + + return TRUE; /* The part of LFN matched */ +} + + + +static +BOOL pick_lfn ( /* TRUE:Succeeded, FALSE:Buffer overflow */ + WCHAR *lfnbuf, /* Pointer to the Unicode-LFN buffer */ + BYTE *dir /* Pointer to the directory entry */ +) +{ + int i, s; + WCHAR wc, uc; + + + i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ + + s = 0; wc = 1; + do { + uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ + if (wc) { /* Last char has not been processed */ + if (i >= _MAX_LFN) return FALSE; /* Buffer overflow? */ + lfnbuf[i++] = wc = uc; /* Store it */ + } else { + if (uc != 0xFFFF) return FALSE; /* Check filler */ + } + } while (++s < 13); /* Read all character in the entry */ + + if (dir[LDIR_Ord] & 0x40) { /* Put terminator if it is the last LFN part */ + if (i >= _MAX_LFN) return FALSE; /* Buffer overflow? */ + lfnbuf[i] = 0; + } + + return TRUE; +} + + +#if !_FS_READONLY +static +void fit_lfn ( + const WCHAR *lfnbuf, /* Pointer to the LFN buffer */ + BYTE *dir, /* Pointer to the directory entry */ + BYTE ord, /* LFN order (1-20) */ + BYTE sum /* SFN sum */ +) +{ + int i, s; + WCHAR wc; + + + dir[LDIR_Chksum] = sum; /* Set check sum */ + dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ + dir[LDIR_Type] = 0; + ST_WORD(dir+LDIR_FstClusLO, 0); + + i = (ord - 1) * 13; /* Get offset in the LFN buffer */ + s = wc = 0; + do { + if (wc != 0xFFFF) wc = lfnbuf[i++]; /* Get an effective char */ + ST_WORD(dir+LfnOfs[s], wc); /* Put it */ + if (!wc) wc = 0xFFFF; /* Padding chars following last char */ + } while (++s < 13); + if (wc == 0xFFFF || !lfnbuf[i]) ord |= 0x40; /* Bottom LFN part is the start of LFN sequence */ + dir[LDIR_Ord] = ord; /* Set the LFN order */ +} + +#endif +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Create numbered name */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +void gen_numname ( + BYTE *dst, /* Pointer to generated SFN */ + const BYTE *src, /* Pointer to source SFN to be modified */ + const WCHAR *lfn, /* Pointer to LFN */ + WORD num /* Sequence number */ +) +{ + char ns[8]; + int i, j; + + + mem_cpy(dst, src, 11); + + if (num > 5) { /* On many collisions, generate a hash number instead of sequential number */ + do num = (num >> 1) + (num << 15) + (WORD)*lfn++; while (*lfn); + } + + /* itoa */ + i = 7; + do { + ns[i--] = (num % 10) + '0'; + num /= 10; + } while (num); + ns[i] = '~'; + + /* Append the number */ + for (j = 0; j < i && dst[j] != ' '; j++) { + if (IsDBCS1(dst[j])) { + if (j == i - 1) break; + j++; + } + } + do { + dst[j++] = (i < 8) ? ns[i++] : ' '; + } while (j < 8); +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Calculate sum of an SFN */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +static +BYTE sum_sfn ( + const BYTE *dir /* Ptr to directory entry */ +) +{ + BYTE sum = 0; + int n = 11; + + do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n); + return sum; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Find an object in the directory */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_find ( + DIR *dj /* Pointer to the directory object linked to the file name */ +) +{ + FRESULT res; + BYTE c, *dir; +#if _USE_LFN + BYTE a, ord, sum; +#endif + + res = dir_seek(dj, 0); /* Rewind directory object */ + if (res != FR_OK) return res; + +#if _USE_LFN + ord = sum = 0xFF; +#endif + do { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + dir = dj->dir; /* Ptr to the directory entry of current index */ + c = dir[DIR_Name]; + if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ +#if _USE_LFN /* LFN configuration */ + a = dir[DIR_Attr] & AM_MASK; + if (c == 0xE5 || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ + ord = 0xFF; + } else { + if (a == AM_LFN) { /* An LFN entry is found */ + if (dj->lfn) { + if (c & 0x40) { /* Is it start of LFN sequence? */ + sum = dir[LDIR_Chksum]; + c &= 0xBF; ord = c; /* LFN start order */ + dj->lfn_idx = dj->index; + } + /* Check validity of the LFN entry and compare it with given name */ + ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF; + } + } else { /* An SFN entry is found */ + if (!ord && sum == sum_sfn(dir)) break; /* LFN matched? */ + ord = 0xFF; dj->lfn_idx = 0xFFFF; /* Reset LFN sequence */ + if (!(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11)) break; /* SFN matched? */ + } + } +#else /* Non LFN configuration */ + if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */ + break; +#endif + res = dir_next(dj, FALSE); /* Next entry */ + } while (res == FR_OK); + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read an object from the directory */ +/*-----------------------------------------------------------------------*/ +#if _FS_MINIMIZE <= 1 +static +FRESULT dir_read ( + DIR *dj /* Pointer to the directory object that pointing the entry to be read */ +) +{ + FRESULT res; + BYTE c, *dir; +#if _USE_LFN + BYTE a, ord = 0xFF, sum = 0xFF; +#endif + + res = FR_NO_FILE; + while (dj->sect) { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + dir = dj->dir; /* Ptr to the directory entry of current index */ + c = dir[DIR_Name]; + if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ +#if _USE_LFN /* LFN configuration */ + a = dir[DIR_Attr] & AM_MASK; + if (c == 0xE5 || (!_FS_RPATH && c == '.') || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ + ord = 0xFF; + } else { + if (a == AM_LFN) { /* An LFN entry is found */ + if (c & 0x40) { /* Is it start of LFN sequence? */ + sum = dir[LDIR_Chksum]; + c &= 0xBF; ord = c; + dj->lfn_idx = dj->index; + } + /* Check LFN validity and capture it */ + ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF; + } else { /* An SFN entry is found */ + if (ord || sum != sum_sfn(dir)) /* Is there a valid LFN? */ + dj->lfn_idx = 0xFFFF; /* It has no LFN. */ + break; + } + } +#else /* Non LFN configuration */ + if (c != 0xE5 && (_FS_RPATH || c != '.') && !(dir[DIR_Attr] & AM_VOL)) /* Is it a valid entry? */ + break; +#endif + res = dir_next(dj, FALSE); /* Next entry */ + if (res != FR_OK) break; + } + + if (res != FR_OK) dj->sect = 0; + + return res; +} +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Register an object to the directory */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */ + DIR *dj /* Target directory with object name to be created */ +) +{ + FRESULT res; + BYTE c, *dir; +#if _USE_LFN /* LFN configuration */ + WORD n, ne, is; + BYTE sn[12], *fn, sum; + WCHAR *lfn; + + + fn = dj->fn; lfn = dj->lfn; + mem_cpy(sn, fn, 12); + + if (_FS_RPATH && (sn[NS] & NS_DOT)) return FR_INVALID_NAME; /* Cannot create dot entry */ + + if (sn[NS] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */ + fn[NS] = 0; dj->lfn = NULL; /* Find only SFN */ + for (n = 1; n < 100; n++) { + gen_numname(fn, sn, lfn, n); /* Generate a numbered name */ + res = dir_find(dj); /* Check if the name collides with existing SFN */ + if (res != FR_OK) break; + } + if (n == 100) return FR_DENIED; /* Abort if too many collisions */ + if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ + fn[NS] = sn[NS]; dj->lfn = lfn; + } + + if (sn[NS] & NS_LFN) { /* When LFN is to be created, reserve reserve an SFN + LFN entries. */ + for (ne = 0; lfn[ne]; ne++) ; + ne = (ne + 25) / 13; + } else { /* Otherwise reserve only an SFN entry. */ + ne = 1; + } + + /* Reserve contiguous entries */ + res = dir_seek(dj, 0); + if (res != FR_OK) return res; + n = is = 0; + do { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + c = *dj->dir; /* Check the entry status */ + if (c == 0xE5 || c == 0) { /* Is it a blank entry? */ + if (n == 0) is = dj->index; /* First index of the contiguous entry */ + if (++n == ne) break; /* A contiguous entry that required count is found */ + } else { + n = 0; /* Not a blank entry. Restart to search */ + } + res = dir_next(dj, TRUE); /* Next entry with table stretch */ + } while (res == FR_OK); + + if (res == FR_OK && ne > 1) { /* Initialize LFN entry if needed */ + res = dir_seek(dj, is); + if (res == FR_OK) { + sum = sum_sfn(dj->fn); /* Sum of the SFN tied to the LFN */ + ne--; + do { /* Store LFN entries in bottom first */ + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + fit_lfn(dj->lfn, dj->dir, (BYTE)ne, sum); + dj->fs->wflag = 1; + res = dir_next(dj, FALSE); /* Next entry */ + } while (res == FR_OK && --ne); + } + } + +#else /* Non LFN configuration */ + res = dir_seek(dj, 0); + if (res == FR_OK) { + do { /* Find a blank entry for the SFN */ + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + c = *dj->dir; + if (c == 0xE5 || c == 0) break; /* Is it a blank entry? */ + res = dir_next(dj, TRUE); /* Next entry with table streach */ + } while (res == FR_OK); + } +#endif + + if (res == FR_OK) { /* Initialize the SFN entry */ + res = move_window(dj->fs, dj->sect); + if (res == FR_OK) { + dir = dj->dir; + mem_set(dir, 0, 32); /* Clean the entry */ + mem_cpy(dir, dj->fn, 11); /* Put SFN */ + dir[DIR_NTres] = *(dj->fn+NS) & (NS_BODY | NS_EXT); /* Put NT flag */ + dj->fs->wflag = 1; + } + } + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Remove an object from the directory */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY && !_FS_MINIMIZE +static +FRESULT dir_remove ( /* FR_OK: Successful, FR_DISK_ERR: A disk error */ + DIR *dj /* Directory object pointing the entry to be removed */ +) +{ + FRESULT res; +#if _USE_LFN /* LFN configuration */ + WORD i; + + i = dj->index; /* SFN index */ + res = dir_seek(dj, (WORD)((dj->lfn_idx == 0xFFFF) ? i : dj->lfn_idx)); /* Goto the SFN or top of the LFN entries */ + if (res == FR_OK) { + do { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + *dj->dir = 0xE5; /* Mark the entry "deleted" */ + dj->fs->wflag = 1; + if (dj->index >= i) break; /* When reached SFN, all entries of the object has been deleted. */ + res = dir_next(dj, FALSE); /* Next entry */ + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR; + } + +#else /* Non LFN configuration */ + res = dir_seek(dj, dj->index); + if (res == FR_OK) { + res = move_window(dj->fs, dj->sect); + if (res == FR_OK) { + *dj->dir = 0xE5; /* Mark the entry "deleted" */ + dj->fs->wflag = 1; + } + } +#endif + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Pick a segment and create the object name in directory form */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT create_name ( + DIR *dj, /* Pointer to the directory object */ + const XCHAR **path /* Pointer to pointer to the segment in the path string */ +) +{ +#ifdef _EXCVT + static const BYTE cvt[] = _EXCVT; +#endif + +#if _USE_LFN /* LFN configuration */ + BYTE b, cf; + WCHAR w, *lfn; + int i, ni, si, di; + const XCHAR *p; + + /* Create LFN in Unicode */ + si = di = 0; + p = *path; + lfn = dj->lfn; + for (;;) { + w = p[si++]; /* Get a character */ + if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */ + if (di >= _MAX_LFN) /* Reject too long name */ + return FR_INVALID_NAME; +#if !_LFN_UNICODE + w &= 0xFF; + if (IsDBCS1(w)) { /* If it is a DBC 1st byte */ + b = p[si++]; /* Get 2nd byte */ + if (!IsDBCS2(b)) /* Reject invalid code for DBC */ + return FR_INVALID_NAME; + //w = (w << 8) + b; + else w = (w << 8) + b; + } + w = ff_convert(w, 1); /* Convert OEM to Unicode */ + if (!w) return FR_INVALID_NAME; /* Reject invalid code */ +#endif + if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal chars for LFN */ + return FR_INVALID_NAME; + lfn[di++] = w; /* Store the Unicode char */ + } + *path = &p[si]; /* Return pointer to the next segment */ + cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ +#if _FS_RPATH + if ((di == 1 && lfn[di - 1] == '.') || /* Is this a dot entry? */ + (di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) { + lfn[di] = 0; + for (i = 0; i < 11; i++) + dj->fn[i] = (i < di) ? '.' : ' '; + dj->fn[i] = cf | NS_DOT; /* This is a dot entry */ + return FR_OK; + } +#endif + while (di) { /* Strip trailing spaces and dots */ + w = lfn[di - 1]; + if (w != ' ' && w != '.') break; + di--; + } + if (!di) return FR_INVALID_NAME; /* Reject null string */ + + lfn[di] = 0; /* LFN is created */ + + /* Create SFN in directory form */ + mem_set(dj->fn, ' ', 11); + for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */ + if (si) cf |= NS_LOSS | NS_LFN; + while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */ + + b = i = 0; ni = 8; + for (;;) { + w = lfn[si++]; /* Get an LFN char */ + if (!w) break; /* Break on end of the LFN */ + if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */ + cf |= NS_LOSS | NS_LFN; continue; + } + + if (i >= ni || si == di) { /* Extension or end of SFN */ + if (ni == 11) { /* Long extension */ + cf |= NS_LOSS | NS_LFN; break; + } + if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */ + if (si > di) break; /* No extension */ + si = di; i = 8; ni = 11; /* Enter extension section */ + b <<= 2; continue; + } + + if (w >= 0x80) { /* Non ASCII char */ +#ifdef _EXCVT + w = ff_convert(w, 0); /* Unicode -> OEM code */ + if (w) w = cvt[w - 0x80]; /* Convert extended char to upper (SBCS) */ +#else + w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */ +#endif + cf |= NS_LFN; /* Force create LFN entry */ + } + + if (_DF1S && w >= 0x100) { /* Double byte char */ + if (i >= ni - 1) { + cf |= NS_LOSS | NS_LFN; i = ni; continue; + } + dj->fn[i++] = (BYTE)(w >> 8); + } else { /* Single byte char */ + if (!w || chk_chr("+,;[=]", w)) { /* Replace illegal chars for SFN */ + w = '_'; cf |= NS_LOSS | NS_LFN; /* Lossy conversion */ + } else { + if (IsUpper(w)) { /* ASCII large capital */ + b |= 2; + } else { + if (IsLower(w)) { /* ASCII small capital */ + b |= 1; w -= 0x20; + } + } + } + } + dj->fn[i++] = (BYTE)w; + } + + if (dj->fn[0] == 0xE5) dj->fn[0] = 0x05; /* If the first char collides with deleted mark, replace it with 0x05 */ + + if (ni == 8) b <<= 2; + if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) /* Create LFN entry when there are composite capitals */ + cf |= NS_LFN; + if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended char, NT flags are created */ + if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */ + if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */ + } + + dj->fn[NS] = cf; /* SFN is created */ + return FR_OK; + + +#else /* Non-LFN configuration */ + BYTE b, c, d, *sfn; + int ni, si, i; + const char *p; + + /* Create file name in directory form */ + sfn = dj->fn; + mem_set(sfn, ' ', 11); + si = i = b = 0; ni = 8; + p = *path; +#if _FS_RPATH + if (p[si] == '.') { /* Is this a dot entry? */ + for (;;) { + c = p[si++]; + if (c != '.' || si >= 3) break; + sfn[i++] = c; + } + if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME; + *path = &p[si]; /* Return pointer to the next segment */ + sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */ + return FR_OK; + } +#endif + for (;;) { + c = p[si++]; + if (c <= ' ' || c == '/' || c == '\\') break; /* Break on end of segment */ + if (c == '.' || i >= ni) { + if (ni != 8 || c != '.') return FR_INVALID_NAME; + i = 8; ni = 11; + b <<= 2; continue; + } + if (c >= 0x80) { /* Extended char */ +#ifdef _EXCVT + c = cvt[c - 0x80]; /* Convert extend char (SBCS) */ +#else + b |= 3; /* Eliminate NT flag if ext char is exist */ +#if !_DF1S /* ASCII only cfg */ + return FR_INVALID_NAME; +#endif +#endif + } + if (IsDBCS1(c)) { /* DBC 1st byte? */ + d = p[si++]; /* Get 2nd byte */ + if (!IsDBCS2(d) || i >= ni - 1) /* Reject invalid DBC */ + return FR_INVALID_NAME; + sfn[i++] = c; + sfn[i++] = d; + } else { /* Single byte code */ + if (chk_chr(" \"*+,[=]|\x7F", c)) /* Reject illegal chrs for SFN */ + return FR_INVALID_NAME; + if (IsUpper(c)) { /* ASCII large capital? */ + b |= 2; + } else { + if (IsLower(c)) { /* ASCII small capital? */ + b |= 1; c -= 0x20; + } + } + sfn[i++] = c; + } + } + *path = &p[si]; /* Return pointer to the next segment */ + c = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ + + if (!i) return FR_INVALID_NAME; /* Reject null string */ + if (sfn[0] == 0xE5) sfn[0] = 0x05; /* When first char collides with 0xE5, replace it with 0x05 */ + + if (ni == 8) b <<= 2; + if ((b & 0x03) == 0x01) c |= NS_EXT; /* NT flag (Extension has only small capital) */ + if ((b & 0x0C) == 0x04) c |= NS_BODY; /* NT flag (Filename has only small capital) */ + + sfn[NS] = c; /* Store NT flag, File name is created */ + + return FR_OK; +#endif +} + + + + +/*-----------------------------------------------------------------------*/ +/* Get file information from directory entry */ +/*-----------------------------------------------------------------------*/ +#if _FS_MINIMIZE <= 1 +static +void get_fileinfo ( /* No return code */ + DIR *dj, /* Pointer to the directory object */ + FILINFO *fno /* Pointer to the file information to be filled */ +) +{ + int i; + BYTE c, nt, *dir; + char *p; + + + p = fno->fname; + if (dj->sect) { + dir = dj->dir; + nt = dir[DIR_NTres]; /* NT flag */ + for (i = 0; i < 8; i++) { /* Copy name body */ + c = dir[i]; + if (c == ' ') break; + if (c == 0x05) c = 0xE5; + if (_USE_LFN && (nt & NS_BODY) && IsUpper(c)) c += 0x20; + *p++ = c; + } + if (dir[8] != ' ') { /* Copy name extension */ + *p++ = '.'; + for (i = 8; i < 11; i++) { + c = dir[i]; + if (c == ' ') break; + if (_USE_LFN && (nt & NS_EXT) && IsUpper(c)) c += 0x20; + *p++ = c; + } + } + fno->fattrib = dir[DIR_Attr]; /* Attribute */ + fno->fsize = LD_DWORD(dir+DIR_FileSize); /* Size */ + fno->fdate = LD_WORD(dir+DIR_WrtDate); /* Date */ + fno->ftime = LD_WORD(dir+DIR_WrtTime); /* Time */ + } + *p = 0; + +#if _USE_LFN + if (fno->lfname) { + XCHAR *tp = fno->lfname; + WCHAR w, *lfn; + + i = 0; + if (dj->sect && dj->lfn_idx != 0xFFFF) {/* Get LFN if available */ + lfn = dj->lfn; + while ((w = *lfn++) != 0) { /* Get an LFN char */ +#if !_LFN_UNICODE + w = ff_convert(w, 0); /* Unicode -> OEM conversion */ + if (!w) { i = 0; break; } /* Could not convert, no LFN */ + if (_DF1S && w >= 0x100) /* Put 1st byte if it is a DBC */ + tp[i++] = (XCHAR)(w >> 8); +#endif + if (i >= fno->lfsize - 1) { i = 0; break; } /* Buffer overrun, no LFN */ + tp[i++] = (XCHAR)w; + } + } + tp[i] = 0; /* Terminator */ + } +#endif +} +#endif /* _FS_MINIMIZE <= 1 */ + + + + +/*-----------------------------------------------------------------------*/ +/* Follow a file path */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ + DIR *dj, /* Directory object to return last directory and found object */ + const XCHAR *path /* Full-path string to find a file or directory */ +) +{ + FRESULT res; + BYTE *dir, last; + + while (!_USE_LFN && *path == ' ') path++; /* Skip leading spaces */ +#if _FS_RPATH + if (*path == '/' || *path == '\\') { /* There is a heading separator */ + path++; dj->sclust = 0; /* Strip it and start from the root dir */ + } else { /* No heading separator */ + dj->sclust = dj->fs->cdir; /* Start from the current dir */ + } +#else + if (*path == '/' || *path == '\\') /* Strip heading separator if exist */ + path++; + dj->sclust = 0; /* Start from the root dir */ +#endif + + if ((UINT)*path < ' ') { /* Null path means the start directory itself */ + res = dir_seek(dj, 0); + dj->dir = NULL; + + } else { /* Follow path */ + for (;;) { + res = create_name(dj, &path); /* Get a segment */ + if (res != FR_OK) break; + res = dir_find(dj); /* Find it */ + last = *(dj->fn+NS) & NS_LAST; + if (res != FR_OK) { /* Could not find the object */ + if (res == FR_NO_FILE && !last) + res = FR_NO_PATH; + break; + } + if (last) break; /* Last segment match. Function completed. */ + dir = dj->dir; /* There is next segment. Follow the sub directory */ + if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */ + res = FR_NO_PATH; break; + } + dj->sclust = ((DWORD)LD_WORD(dir+DIR_FstClusHI) << 16) | LD_WORD(dir+DIR_FstClusLO); + } + } + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Load boot record and check if it is an FAT boot record */ +/*-----------------------------------------------------------------------*/ + +static +BYTE check_fs ( /* 0:The FAT boot record, 1:Valid boot record but not an FAT, 2:Not a boot record, 3:Error */ + FATFS *fs, /* File system object */ + DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */ +) +{ + if (disk_read(fs->drive, fs->win, sect, 1) != RES_OK) /* Load boot record */ + return 3; + if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) /* Check record signature (always placed at offset 510 even if the sector size is >512) */ + return 2; + + if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */ + return 0; + if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146) + return 0; + + return 1; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Make sure that the file system is valid */ +/*-----------------------------------------------------------------------*/ + + +FRESULT chk_mounted ( /* FR_OK(0): successful, !=0: any error occurred */ + const XCHAR **path, /* Pointer to pointer to the path name (drive number) */ + FATFS **rfs, /* Pointer to pointer to the found file system object */ + BYTE chk_wp /* !=0: Check media write protection for write access */ +) +{ + BYTE fmt, *tbl; + UINT vol; + DSTATUS stat; + DWORD bsect, fsize, tsect, mclst; + const XCHAR *p = *path; + FATFS *fs; + + /* Get logical drive number from the path name */ + vol = p[0] - '0'; /* Is there a drive number? */ + if (vol <= 9 && p[1] == ':') { /* Found a drive number, get and strip it */ + p += 2; *path = p; /* Return pointer to the path name */ + } else { /* No drive number is given */ +#if _FS_RPATH + vol = Drive; /* Use current drive */ +#else + vol = 0; /* Use drive 0 */ +#endif + } + + /* Check if the logical drive is valid or not */ + if (vol >= _DRIVES) /* Is the drive number valid? */ + return FR_INVALID_DRIVE; + *rfs = fs = FatFs[vol]; /* Return pointer to the corresponding file system object */ + if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */ + + ENTER_FF(fs); /* Lock file system */ + + if (fs->fs_type) { /* If the logical drive has been mounted */ + stat = disk_status(fs->drive); + if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized (has not been changed), */ +#if !_FS_READONLY + if (chk_wp && (stat & STA_PROTECT)) /* Check write protection if needed */ + return FR_WRITE_PROTECTED; +#endif + return FR_OK; /* The file system object is valid */ + } + } + + /* The logical drive must be mounted. Following code attempts to mount the volume */ + + fs->fs_type = 0; /* Clear the file system object */ + fs->drive = (BYTE)LD2PD(vol); /* Bind the logical drive and a physical drive */ + stat = disk_initialize(fs->drive); /* Initialize low level disk I/O layer */ + if (stat & STA_NOINIT) /* Check if the drive is ready */ + return FR_NOT_READY; +#if _MAX_SS != 512 /* Get disk sector size if needed */ + if (disk_ioctl(fs->drive, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > _MAX_SS) + return FR_NO_FILESYSTEM; +#endif +#if !_FS_READONLY + if (chk_wp && (stat & STA_PROTECT)) /* Check disk write protection if needed */ + return FR_WRITE_PROTECTED; +#endif + /* Search FAT partition on the drive */ + fmt = check_fs(fs, bsect = 0); /* Check sector 0 as an SFD format */ + if (fmt == 1) { /* Not an FAT boot record, it may be partitioned */ + /* Check a partition listed in top of the partition table */ + tbl = &fs->win[MBR_Table + LD2PT(vol) * 16]; /* Partition table */ + if (tbl[4]) { /* Is the partition existing? */ + bsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */ + fmt = check_fs(fs, bsect); /* Check the partition */ + } + } + if (fmt == 3) return FR_DISK_ERR; + if (fmt || LD_WORD(fs->win+BPB_BytsPerSec) != SS(fs)) /* No valid FAT partition is found */ + return FR_NO_FILESYSTEM; + + /* Initialize the file system object */ + fsize = LD_WORD(fs->win+BPB_FATSz16); /* Number of sectors per FAT */ + if (!fsize) fsize = LD_DWORD(fs->win+BPB_FATSz32); + fs->sects_fat = fsize; + fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FAT copies */ + fsize *= fs->n_fats; /* (Number of sectors in FAT area) */ + fs->fatbase = bsect + LD_WORD(fs->win+BPB_RsvdSecCnt); /* FAT start sector (lba) */ + fs->csize = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */ + fs->n_rootdir = LD_WORD(fs->win+BPB_RootEntCnt); /* Number of root directory entries */ + tsect = LD_WORD(fs->win+BPB_TotSec16); /* Number of sectors on the volume */ + if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32); + fs->max_clust = mclst = (tsect /* Last cluster# + 1 (Number of clusters + 2) */ + - LD_WORD(fs->win+BPB_RsvdSecCnt) - fsize - fs->n_rootdir / (SS(fs)/32) + ) / fs->csize + 2; + + fmt = FS_FAT12; /* Determine the FAT sub type */ + if (mclst >= 0xFF7) fmt = FS_FAT16; /* Number of clusters >= 0xFF5 */ + if (mclst >= 0xFFF7) fmt = FS_FAT32; /* Number of clusters >= 0xFFF5 */ + + if (fmt == FS_FAT32) + fs->dirbase = LD_DWORD(fs->win+BPB_RootClus); /* Root directory start cluster */ + else + fs->dirbase = fs->fatbase + fsize; /* Root directory start sector (lba) */ + fs->database = fs->fatbase + fsize + fs->n_rootdir / (SS(fs)/32); /* Data start sector (lba) */ + +#if !_FS_READONLY + /* Initialize allocation information */ + fs->free_clust = 0xFFFFFFFF; + fs->wflag = 0; + /* Get fsinfo if needed */ + if (fmt == FS_FAT32) { + fs->fsi_flag = 0; + fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo); + if (disk_read(fs->drive, fs->win, fs->fsi_sector, 1) == RES_OK && + LD_WORD(fs->win+BS_55AA) == 0xAA55 && + LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 && + LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) { + fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free); + fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count); + } + } +#endif + fs->fs_type = fmt; /* FAT sub-type */ + fs->winsect = 0; /* Invalidate sector cache */ +#if _FS_RPATH + fs->cdir = 0; /* Current directory (root dir) */ +#endif + fs->id = ++Fsid; /* File system mount ID */ + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Check if the file/dir object is valid or not */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT validate ( /* FR_OK(0): The object is valid, !=0: Invalid */ + FATFS *fs, /* Pointer to the file system object */ + WORD id /* Member id of the target object to be checked */ +) +{ + if (!fs || !fs->fs_type || fs->id != id) + return FR_INVALID_OBJECT; + + ENTER_FF(fs); /* Lock file system */ + + if (disk_status(fs->drive) & STA_NOINIT) + return FR_NOT_READY; + + return FR_OK; +} + + + + +/*-------------------------------------------------------------------------- + + Public Functions + +--------------------------------------------------------------------------*/ + + + +/*-----------------------------------------------------------------------*/ +/* Mount/Unmount a Logical Drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mount ( + BYTE vol, /* Logical drive number to be mounted/unmounted */ + FATFS *fs /* Pointer to new file system object (NULL for unmount)*/ +) +{ + FATFS *rfs; + + + if (vol >= _DRIVES) /* Check if the drive number is valid */ + return FR_INVALID_DRIVE; + rfs = FatFs[vol]; /* Get current fs object */ + + if (rfs) { +#if _FS_REENTRANT /* Discard sync object of the current volume */ + if (!ff_del_syncobj(rfs->sobj)) return FR_INT_ERR; +#endif + rfs->fs_type = 0; /* Clear old fs object */ + } + + if (fs) { + fs->fs_type = 0; /* Clear new fs object */ +#if _FS_REENTRANT /* Create sync object for the new volume */ + if (!ff_cre_syncobj(vol, &fs->sobj)) return FR_INT_ERR; +#endif + } + FatFs[vol] = fs; /* Register new fs object */ + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Open or Create a File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_open ( + FIL *fp, /* Pointer to the blank file object */ + const XCHAR *path, /* Pointer to the file name */ + BYTE mode /* Access mode and file open mode flags */ +) +{ + FRESULT res; + DIR dj; + NAMEBUF(sfn, lfn); + BYTE *dir; + + + fp->fs = NULL; /* Clear file object */ +#if !_FS_READONLY + mode &= (FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW); + res = chk_mounted(&path, &dj.fs, (BYTE)(mode & (FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW))); +#else + mode &= FA_READ; + res = chk_mounted(&path, &dj.fs, 0); +#endif + if (res != FR_OK) LEAVE_FF(dj.fs, res); + INITBUF(dj, sfn, lfn); + res = follow_path(&dj, path); /* Follow the file path */ + +#if !_FS_READONLY + /* Create or Open a file */ + if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) { + DWORD ps, cl; + + if (res != FR_OK) { /* No file, create new */ + if (res == FR_NO_FILE) /* There is no file to open, create a new entry */ + res = dir_register(&dj); + if (res != FR_OK) LEAVE_FF(dj.fs, res); + mode |= FA_CREATE_ALWAYS; + dir = dj.dir; /* Created entry (SFN entry) */ + } + else { /* Any object is already existing */ + if (mode & FA_CREATE_NEW) /* Cannot create new */ + LEAVE_FF(dj.fs, FR_EXIST); + dir = dj.dir; + if (!dir || (dir[DIR_Attr] & (AM_RDO | AM_DIR))) /* Cannot overwrite it (R/O or DIR) */ + LEAVE_FF(dj.fs, FR_DENIED); + if (mode & FA_CREATE_ALWAYS) { /* Resize it to zero on over write mode */ + cl = ((DWORD)LD_WORD(dir+DIR_FstClusHI) << 16) | LD_WORD(dir+DIR_FstClusLO); /* Get start cluster */ + ST_WORD(dir+DIR_FstClusHI, 0); /* cluster = 0 */ + ST_WORD(dir+DIR_FstClusLO, 0); + ST_DWORD(dir+DIR_FileSize, 0); /* size = 0 */ + dj.fs->wflag = 1; + ps = dj.fs->winsect; /* Remove the cluster chain */ + if (cl) { + res = remove_chain(dj.fs, cl); + if (res) LEAVE_FF(dj.fs, res); + dj.fs->last_clust = cl - 1; /* Reuse the cluster hole */ + } + res = move_window(dj.fs, ps); + if (res != FR_OK) LEAVE_FF(dj.fs, res); + } + } + if (mode & FA_CREATE_ALWAYS) { + dir[DIR_Attr] = 0; /* Reset attribute */ + ps = get_fattime(); + ST_DWORD(dir+DIR_CrtTime, ps); /* Created time */ + dj.fs->wflag = 1; + mode |= FA__WRITTEN; /* Set file changed flag */ + } + } + /* Open an existing file */ + else { +#endif /* !_FS_READONLY */ + if (res != FR_OK) LEAVE_FF(dj.fs, res); /* Follow failed */ + dir = dj.dir; + if (!dir || (dir[DIR_Attr] & AM_DIR)) /* It is a directory */ + LEAVE_FF(dj.fs, FR_NO_FILE); +#if !_FS_READONLY + if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */ + LEAVE_FF(dj.fs, FR_DENIED); + } + fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */ + fp->dir_ptr = dj.dir; +#endif + fp->flag = mode; /* File access mode */ + fp->org_clust = /* File start cluster */ + ((DWORD)LD_WORD(dir+DIR_FstClusHI) << 16) | LD_WORD(dir+DIR_FstClusLO); + fp->fsize = LD_DWORD(dir+DIR_FileSize); /* File size */ + fp->fptr = 0; fp->csect = 255; /* File pointer */ + fp->dsect = 0; + fp->fs = dj.fs; fp->id = dj.fs->id; /* Owner file system object of the file */ + + LEAVE_FF(dj.fs, FR_OK); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_read ( + FIL *fp, /* Pointer to the file object */ + void *buff, /* Pointer to data buffer */ + UINT btr, /* Number of bytes to read */ + UINT *br /* Pointer to number of bytes read */ +) +{ + FRESULT res; + DWORD clst, sect, remain; + UINT rcnt, cc; + BYTE *rbuff = buff; + + + *br = 0; /* Initialize bytes read */ + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check abort flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + if (!(fp->flag & FA_READ)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + remain = fp->fsize - fp->fptr; + if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + + for ( ; btr; /* Repeat until all data transferred */ + rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + if (fp->csect >= fp->fs->csize) { /* On the cluster boundary? */ + clst = (fp->fptr == 0) ? /* On the top of the file? */ + fp->org_clust : get_fat(fp->fs, fp->curr_clust); + if (clst <= 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->curr_clust = clst; /* Update current cluster */ + fp->csect = 0; /* Reset sector offset in the cluster */ + } + sect = clust2sect(fp->fs, fp->curr_clust); /* Get current sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += fp->csect; + cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Read maximum contiguous sectors directly */ + if (fp->csect + cc > fp->fs->csize) /* Clip at cluster boundary */ + cc = fp->fs->csize - fp->csect; + if (disk_read(fp->fs->drive, rbuff, sect, (BYTE)cc) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); +#if !_FS_READONLY && _FS_MINIMIZE <= 2 +#if _FS_TINY + if (fp->fs->wflag && fp->fs->winsect - sect < cc) /* Replace one of the read sectors with cached data if it contains a dirty sector */ + mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs)); +#else + if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc) /* Replace one of the read sectors with cached data if it contains a dirty sector */ + mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs)); +#endif +#endif + fp->csect += (BYTE)cc; /* Next sector address in the cluster */ + rcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ + continue; + } +#if !_FS_TINY +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Write sector I/O buffer if needed */ + if (disk_write(fp->fs->drive, fp->buf, fp->dsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + if (fp->dsect != sect) { /* Fill sector buffer with file data */ + if (disk_read(fp->fs->drive, fp->buf, sect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + } +#endif + fp->dsect = sect; + fp->csect++; /* Next sector address in the cluster */ + } + rcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs)); /* Get partial sector data from sector buffer */ + if (rcnt > btr) rcnt = btr; +#if _FS_TINY + if (move_window(fp->fs, fp->dsect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ +#else + mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ +#endif + } + + LEAVE_FF(fp->fs, FR_OK); +} + + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Write File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_write ( + FIL *fp, /* Pointer to the file object */ + const void *buff, /* Pointer to the data to be written */ + UINT btw, /* Number of bytes to write */ + UINT *bw /* Pointer to number of bytes written */ +) +{ + FRESULT res; + DWORD clst, sect; + UINT wcnt, cc; + const BYTE *wbuff = buff; + + + *bw = 0; /* Initialize bytes written */ + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check abort flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + if (!(fp->flag & FA_WRITE)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + if (fp->fsize + btw < fp->fsize) btw = 0; /* File size cannot reach 4GB */ + + for ( ; btw; /* Repeat until all data transferred */ + wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + if (fp->csect >= fp->fs->csize) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clst = fp->org_clust; /* Follow from the origin */ + if (clst == 0) /* When there is no cluster chain, */ + fp->org_clust = clst = create_chain(fp->fs, 0); /* Create a new cluster chain */ + } else { /* Middle or end of the file */ + clst = create_chain(fp->fs, fp->curr_clust); /* Follow or stretch cluster chain */ + } + if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ + if (clst == 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->curr_clust = clst; /* Update current cluster */ + fp->csect = 0; /* Reset sector address in the cluster */ + } +#if _FS_TINY + if (fp->fs->winsect == fp->dsect && move_window(fp->fs, 0)) /* Write back data buffer prior to following direct transfer */ + ABORT(fp->fs, FR_DISK_ERR); +#else + if (fp->flag & FA__DIRTY) { /* Write back data buffer prior to following direct transfer */ + if (disk_write(fp->fs->drive, fp->buf, fp->dsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + sect = clust2sect(fp->fs, fp->curr_clust); /* Get current sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += fp->csect; + cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Write maximum contiguous sectors directly */ + if (fp->csect + cc > fp->fs->csize) /* Clip at cluster boundary */ + cc = fp->fs->csize - fp->csect; + if (disk_write(fp->fs->drive, wbuff, sect, (BYTE)cc) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); +#if _FS_TINY + if (fp->fs->winsect - sect < cc) { /* Refill sector cache if it gets dirty by the direct write */ + mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs)); + fp->fs->wflag = 0; + } +#else + if (fp->dsect - sect < cc) { /* Refill sector cache if it gets dirty by the direct write */ + mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs)); + fp->flag &= ~FA__DIRTY; + } +#endif + fp->csect += (BYTE)cc; /* Next sector address in the cluster */ + wcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ + continue; + } +#if _FS_TINY + if (fp->fptr >= fp->fsize) { /* Avoid silly buffer filling at growing edge */ + if (move_window(fp->fs, 0)) ABORT(fp->fs, FR_DISK_ERR); + fp->fs->winsect = sect; + } +#else + if (fp->dsect != sect) { /* Fill sector buffer with file data */ + if (fp->fptr < fp->fsize && + disk_read(fp->fs->drive, fp->buf, sect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + } +#endif + fp->dsect = sect; + fp->csect++; /* Next sector address in the cluster */ + } + wcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs)); /* Put partial sector into file I/O buffer */ + if (wcnt > btw) wcnt = btw; +#if _FS_TINY + if (move_window(fp->fs, fp->dsect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ + fp->fs->wflag = 1; +#else + mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ + fp->flag |= FA__DIRTY; +#endif + } + + if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */ + fp->flag |= FA__WRITTEN; /* Set file changed flag */ + + LEAVE_FF(fp->fs, FR_OK); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Synchronize the File Object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_sync ( + FIL *fp /* Pointer to the file object */ +) +{ + FRESULT res; + DWORD tim; + BYTE *dir; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res == FR_OK) { + if (fp->flag & FA__WRITTEN) { /* Has the file been written? */ +#if !_FS_TINY /* Write-back dirty buffer */ + if (fp->flag & FA__DIRTY) { + if (disk_write(fp->fs->drive, fp->buf, fp->dsect, 1) != RES_OK) + LEAVE_FF(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + /* Update the directory entry */ + res = move_window(fp->fs, fp->dir_sect); + if (res == FR_OK) { + dir = fp->dir_ptr; + dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ + ST_DWORD(dir+DIR_FileSize, fp->fsize); /* Update file size */ + ST_WORD(dir+DIR_FstClusLO, fp->org_clust); /* Update start cluster */ + ST_WORD(dir+DIR_FstClusHI, fp->org_clust >> 16); + tim = get_fattime(); /* Updated time */ + ST_DWORD(dir+DIR_WrtTime, tim); + fp->flag &= ~FA__WRITTEN; + fp->fs->wflag = 1; + res = sync(fp->fs); + } + } + } + + LEAVE_FF(fp->fs, res); +} + +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Close File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_close ( + FIL *fp /* Pointer to the file object to be closed */ +) +{ + FRESULT res; + + +#if _FS_READONLY + res = validate(fp->fs, fp->id); + if (res == FR_OK) fp->fs = NULL; + LEAVE_FF(fp->fs, res); +#else + res = f_sync(fp); + if (res == FR_OK) fp->fs = NULL; + return res; +#endif +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Current Drive/Directory */ +/*-----------------------------------------------------------------------*/ + +#if _FS_RPATH + +FRESULT f_chdrive ( + BYTE drv /* Drive number */ +) +{ + if (drv >= _DRIVES) return FR_INVALID_DRIVE; + + Drive = drv; + + return FR_OK; +} + + + + +FRESULT f_chdir ( + const XCHAR *path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR dj; + NAMEBUF(sfn, lfn); + BYTE *dir; + + + res = chk_mounted(&path, &dj.fs, 0); + if (res == FR_OK) { + INITBUF(dj, sfn, lfn); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) { /* Follow completed */ + dir = dj.dir; /* Pointer to the entry */ + if (!dir) { + dj.fs->cdir = 0; /* No entry (root dir) */ + } else { + if (dir[DIR_Attr] & AM_DIR) /* Reached to the dir */ + dj.fs->cdir = ((DWORD)LD_WORD(dir+DIR_FstClusHI) << 16) | LD_WORD(dir+DIR_FstClusLO); + else + res = FR_NO_PATH; /* Could not reach the dir (it is a file) */ + } + } + if (res == FR_NO_FILE) res = FR_NO_PATH; + } + + LEAVE_FF(dj.fs, res); +} + +#endif + + + +#if _FS_MINIMIZE <= 2 +/*-----------------------------------------------------------------------*/ +/* Seek File R/W Pointer */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_lseek ( + FIL *fp, /* Pointer to the file object */ + DWORD ofs /* File pointer from top of file */ +) +{ + FRESULT res; + DWORD clst, bcs, nsect, ifptr; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check abort flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + if (ofs > fp->fsize /* In read-only mode, clip offset with the file size */ +#if !_FS_READONLY + && !(fp->flag & FA_WRITE) +#endif + ) ofs = fp->fsize; + + ifptr = fp->fptr; + fp->fptr = nsect = 0; fp->csect = 255; + if (ofs > 0) { + bcs = (DWORD)fp->fs->csize * SS(fp->fs); /* Cluster size (byte) */ + if (ifptr > 0 && + (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ + fp->fptr = (ifptr - 1) & ~(bcs - 1); /* start from the current cluster */ + ofs -= fp->fptr; + clst = fp->curr_clust; + } else { /* When seek to back cluster, */ + clst = fp->org_clust; /* start from the first cluster */ +#if !_FS_READONLY + if (clst == 0) { /* If no cluster chain, create a new chain */ + clst = create_chain(fp->fs, 0); + if (clst == 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->org_clust = clst; + } +#endif + fp->curr_clust = clst; + } + if (clst != 0) { + while (ofs > bcs) { /* Cluster following loop */ +#if !_FS_READONLY + if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ + clst = create_chain(fp->fs, clst); /* Force stretch if in write mode */ + if (clst == 0) { /* When disk gets full, clip file size */ + ofs = bcs; break; + } + } else +#endif + clst = get_fat(fp->fs, clst); /* Follow cluster chain if not in write mode */ + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + if (clst <= 1 || clst >= fp->fs->max_clust) ABORT(fp->fs, FR_INT_ERR); + fp->curr_clust = clst; + fp->fptr += bcs; + ofs -= bcs; + } + fp->fptr += ofs; + fp->csect = (BYTE)(ofs / SS(fp->fs)); /* Sector offset in the cluster */ + if (ofs % SS(fp->fs)) { + nsect = clust2sect(fp->fs, clst); /* Current sector */ + if (!nsect) ABORT(fp->fs, FR_INT_ERR); + nsect += fp->csect; + fp->csect++; + } + } + } + if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) { +#if !_FS_TINY +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Write-back dirty buffer if needed */ + if (disk_write(fp->fs->drive, fp->buf, fp->dsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + if (disk_read(fp->fs->drive, fp->buf, nsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); +#endif + fp->dsect = nsect; + } +#if !_FS_READONLY + if (fp->fptr > fp->fsize) { /* Set changed flag if the file size is extended */ + fp->fsize = fp->fptr; + fp->flag |= FA__WRITTEN; + } +#endif + + LEAVE_FF(fp->fs, res); +} + + + + +#if _FS_MINIMIZE <= 1 +/*-----------------------------------------------------------------------*/ +/* Create a Directroy Object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_opendir ( + DIR *dj, /* Pointer to directory object to create */ + const XCHAR *path /* Pointer to the directory path */ +) +{ + FRESULT res; + NAMEBUF(sfn, lfn); + BYTE *dir; + + res = chk_mounted(&path, &dj->fs, 0); + if (res == FR_OK) { + INITBUF((*dj), sfn, lfn); + res = follow_path(dj, path); /* Follow the path to the directory */ + if (res == FR_OK) { /* Follow completed */ + dir = dj->dir; + if (dir) { /* It is not the root dir */ + if (dir[DIR_Attr] & AM_DIR) { /* The object is a directory */ + dj->sclust = ((DWORD)LD_WORD(dir+DIR_FstClusHI) << 16) | LD_WORD(dir+DIR_FstClusLO); + } else { /* The object is not a directory */ + res = FR_NO_PATH; + } + } + if (res == FR_OK) { + dj->id = dj->fs->id; + res = dir_seek(dj, 0); /* Rewind dir */ + } + } + if (res == FR_NO_FILE) res = FR_NO_PATH; + } + + LEAVE_FF(dj->fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read Directory Entry in Sequense */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_readdir ( + DIR *dj, /* Pointer to the open directory object */ + FILINFO *fno /* Pointer to file information to return */ +) +{ + FRESULT res; + NAMEBUF(sfn, lfn); + + + res = validate(dj->fs, dj->id); /* Check validity of the object */ + if (res == FR_OK) { + INITBUF((*dj), sfn, lfn); + if (!fno) { + res = dir_seek(dj, 0); + } else { + res = dir_read(dj); + if (res == FR_NO_FILE) { + dj->sect = 0; + res = FR_OK; + } + if (res == FR_OK) { /* A valid entry is found */ + get_fileinfo(dj, fno); /* Get the object information */ + res = dir_next(dj, FALSE); /* Increment index for next */ + if (res == FR_NO_FILE) { + dj->sect = 0; + res = FR_OK; + } + } + } + } + + LEAVE_FF(dj->fs, res); +} + + + +#if _FS_MINIMIZE == 0 +/*-----------------------------------------------------------------------*/ +/* Get File Status */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_stat ( + const XCHAR *path, /* Pointer to the file path */ + FILINFO *fno /* Pointer to file information to return */ +) +{ + FRESULT res; + DIR dj; + NAMEBUF(sfn, lfn); + + + res = chk_mounted(&path, &dj.fs, 0); + if (res == FR_OK) { + INITBUF(dj, sfn, lfn); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) { /* Follow completed */ + if (dj.dir) /* Found an object */ + get_fileinfo(&dj, fno); + else /* It is root dir */ + res = FR_INVALID_NAME; + } + } + + LEAVE_FF(dj.fs, res); +} + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Get Number of Free Clusters */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_getfree ( + const XCHAR *path, /* Pointer to the logical drive number (root dir) */ + DWORD *nclst, /* Pointer to the variable to return number of free clusters */ + FATFS **fatfs /* Pointer to pointer to corresponding file system object to return */ +) +{ + FRESULT res; + DWORD n, clst, sect, stat; + UINT i; + BYTE fat, *p; + + + /* Get drive number */ + res = chk_mounted(&path, fatfs, 0); + if (res != FR_OK) LEAVE_FF(*fatfs, res); + + /* If number of free cluster is valid, return it without cluster scan. */ + if ((*fatfs)->free_clust <= (*fatfs)->max_clust - 2) { + *nclst = (*fatfs)->free_clust; + LEAVE_FF(*fatfs, FR_OK); + } + + /* Get number of free clusters */ + fat = (*fatfs)->fs_type; + n = 0; + if (fat == FS_FAT12) { + clst = 2; + do { + stat = get_fat(*fatfs, clst); + if (stat == 0xFFFFFFFF) LEAVE_FF(*fatfs, FR_DISK_ERR); + if (stat == 1) LEAVE_FF(*fatfs, FR_INT_ERR); + if (stat == 0) n++; + } while (++clst < (*fatfs)->max_clust); + } else { + clst = (*fatfs)->max_clust; + sect = (*fatfs)->fatbase; + i = 0; p = 0; + do { + if (!i) { + res = move_window(*fatfs, sect++); + if (res != FR_OK) + LEAVE_FF(*fatfs, res); + p = (*fatfs)->win; + i = SS(*fatfs); + } + if (fat == FS_FAT16) { + if (LD_WORD(p) == 0) n++; + p += 2; i -= 2; + } else { + if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++; + p += 4; i -= 4; + } + } while (--clst); + } + (*fatfs)->free_clust = n; + if (fat == FS_FAT32) (*fatfs)->fsi_flag = 1; + *nclst = n; + + LEAVE_FF(*fatfs, FR_OK); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Truncate File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_truncate ( + FIL *fp /* Pointer to the file object */ +) +{ + FRESULT res; + DWORD ncl; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check abort flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + if (!(fp->flag & FA_WRITE)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + + if (fp->fsize > fp->fptr) { + fp->fsize = fp->fptr; /* Set file size to current R/W point */ + fp->flag |= FA__WRITTEN; + if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ + res = remove_chain(fp->fs, fp->org_clust); + fp->org_clust = 0; + } else { /* When truncate a part of the file, remove remaining clusters */ + ncl = get_fat(fp->fs, fp->curr_clust); + res = FR_OK; + if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (ncl == 1) res = FR_INT_ERR; + if (res == FR_OK && ncl < fp->fs->max_clust) { + res = put_fat(fp->fs, fp->curr_clust, 0x0FFFFFFF); + if (res == FR_OK) res = remove_chain(fp->fs, ncl); + } + } + } + if (res != FR_OK) fp->flag |= FA__ERROR; + + LEAVE_FF(fp->fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Delete a File or Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_unlink ( + const XCHAR *path /* Pointer to the file or directory path */ +) +{ + FRESULT res; + DIR dj, sdj; + NAMEBUF(sfn, lfn); + BYTE *dir; + DWORD dclst; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res != FR_OK) LEAVE_FF(dj.fs, res); + + INITBUF(dj, sfn, lfn); + res = follow_path(&dj, path); /* Follow the file path */ + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res != FR_OK) LEAVE_FF(dj.fs, res); /* Follow failed */ + + dir = dj.dir; + if (!dir) /* Is it the root directory? */ + LEAVE_FF(dj.fs, FR_INVALID_NAME); + if (dir[DIR_Attr] & AM_RDO) /* Is it a R/O object? */ + LEAVE_FF(dj.fs, FR_DENIED); + dclst = ((DWORD)LD_WORD(dir+DIR_FstClusHI) << 16) | LD_WORD(dir+DIR_FstClusLO); + + if (dir[DIR_Attr] & AM_DIR) { /* It is a sub-directory */ + if (dclst < 2) LEAVE_FF(dj.fs, FR_INT_ERR); + mem_cpy(&sdj, &dj, sizeof(DIR)); /* Check if the sub-dir is empty or not */ + sdj.sclust = dclst; + res = dir_seek(&sdj, 2); + if (res != FR_OK) LEAVE_FF(dj.fs, res); + res = dir_read(&sdj); + if (res == FR_OK) res = FR_DENIED; /* Not empty sub-dir */ + if (res != FR_NO_FILE) LEAVE_FF(dj.fs, res); + } + + res = dir_remove(&dj); /* Remove directory entry */ + if (res == FR_OK) { + if (dclst) + res = remove_chain(dj.fs, dclst); /* Remove the cluster chain */ + if (res == FR_OK) res = sync(dj.fs); + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Create a Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mkdir ( + const XCHAR *path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR dj; + NAMEBUF(sfn, lfn); + BYTE *dir, n; + DWORD dsect, dclst, pclst, tim; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res != FR_OK) LEAVE_FF(dj.fs, res); + + INITBUF(dj, sfn, lfn); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) res = FR_EXIST; /* Any file or directory is already existing */ + if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res != FR_NO_FILE) /* Any error occurred */ + LEAVE_FF(dj.fs, res); + + dclst = create_chain(dj.fs, 0); /* Allocate a new cluster for new directory table */ + res = FR_OK; + if (dclst == 0) res = FR_DENIED; + if (dclst == 1) res = FR_INT_ERR; + if (dclst == 0xFFFFFFFF) res = FR_DISK_ERR; + if (res == FR_OK) + res = move_window(dj.fs, 0); + if (res != FR_OK) LEAVE_FF(dj.fs, res); + dsect = clust2sect(dj.fs, dclst); + + dir = dj.fs->win; /* Initialize the new directory table */ + mem_set(dir, 0, SS(dj.fs)); + mem_set(dir+DIR_Name, ' ', 8+3); /* Create "." entry */ + dir[DIR_Name] = '.'; + dir[DIR_Attr] = AM_DIR; + tim = get_fattime(); + ST_DWORD(dir+DIR_WrtTime, tim); + ST_WORD(dir+DIR_FstClusLO, dclst); + ST_WORD(dir+DIR_FstClusHI, dclst >> 16); + mem_cpy(dir+32, dir, 32); /* Create ".." entry */ + dir[33] = '.'; + pclst = dj.sclust; + if (dj.fs->fs_type == FS_FAT32 && pclst == dj.fs->dirbase) + pclst = 0; + ST_WORD(dir+32+DIR_FstClusLO, pclst); + ST_WORD(dir+32+DIR_FstClusHI, pclst >> 16); + for (n = 0; n < dj.fs->csize; n++) { /* Write dot entries and clear left sectors */ + dj.fs->winsect = dsect++; + dj.fs->wflag = 1; + res = move_window(dj.fs, 0); + if (res) LEAVE_FF(dj.fs, res); + mem_set(dir, 0, SS(dj.fs)); + } + + res = dir_register(&dj); + if (res != FR_OK) { + remove_chain(dj.fs, dclst); + } else { + dir = dj.dir; + dir[DIR_Attr] = AM_DIR; /* Attribute */ + ST_DWORD(dir+DIR_WrtTime, tim); /* Create time */ + ST_WORD(dir+DIR_FstClusLO, dclst); /* Table start cluster */ + ST_WORD(dir+DIR_FstClusHI, dclst >> 16); + dj.fs->wflag = 1; + res = sync(dj.fs); + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change File Attribute */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_chmod ( + const XCHAR *path, /* Pointer to the file path */ + BYTE value, /* Attribute bits */ + BYTE mask /* Attribute mask to change */ +) +{ + FRESULT res; + DIR dj; + NAMEBUF(sfn, lfn); + BYTE *dir; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res == FR_OK) { + INITBUF(dj, sfn, lfn); + res = follow_path(&dj, path); /* Follow the file path */ + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res == FR_OK) { + dir = dj.dir; + if (!dir) { /* Is it a root directory? */ + res = FR_INVALID_NAME; + } else { /* File or sub directory */ + mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ + dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ + dj.fs->wflag = 1; + res = sync(dj.fs); + } + } + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Timestamp */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_utime ( + const XCHAR *path, /* Pointer to the file/directory name */ + const FILINFO *fno /* Pointer to the time-stamp to be set */ +) +{ + FRESULT res; + DIR dj; + NAMEBUF(sfn, lfn); + BYTE *dir; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res == FR_OK) { + INITBUF(dj, sfn, lfn); + res = follow_path(&dj, path); /* Follow the file path */ + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res == FR_OK) { + dir = dj.dir; + if (!dir) { /* Root directory */ + res = FR_INVALID_NAME; + } else { /* File or sub-directory */ + ST_WORD(dir+DIR_WrtTime, fno->ftime); + ST_WORD(dir+DIR_WrtDate, fno->fdate); + dj.fs->wflag = 1; + res = sync(dj.fs); + } + } + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Rename File/Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_rename ( + const XCHAR *path_old, /* Pointer to the old name */ + const XCHAR *path_new /* Pointer to the new name */ +) +{ + FRESULT res; + DIR dj_old, dj_new; + NAMEBUF(sfn, lfn); + BYTE buf[21], *dir; + DWORD dw; + + + INITBUF(dj_old, sfn, lfn); + res = chk_mounted(&path_old, &dj_old.fs, 1); + if (res == FR_OK) { + dj_new.fs = dj_old.fs; + res = follow_path(&dj_old, path_old); /* Check old object */ + if (_FS_RPATH && res == FR_OK && (dj_old.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + } + if (res != FR_OK) LEAVE_FF(dj_old.fs, res); /* The old object is not found */ + + if (!dj_old.dir) LEAVE_FF(dj_old.fs, FR_NO_FILE); /* Is root dir? */ + mem_cpy(buf, dj_old.dir+DIR_Attr, 21); /* Save the object information */ + + mem_cpy(&dj_new, &dj_old, sizeof(DIR)); + res = follow_path(&dj_new, path_new); /* Check new object */ + if (res == FR_OK) res = FR_EXIST; /* The new object name is already existing */ + if (res == FR_NO_FILE) { /* Is it a valid path and no name collision? */ + res = dir_register(&dj_new); /* Register the new object */ + if (res == FR_OK) { + dir = dj_new.dir; /* Copy object information into new entry */ + mem_cpy(dir+13, buf+2, 19); + dir[DIR_Attr] = buf[0] | AM_ARC; + dj_old.fs->wflag = 1; + if (dir[DIR_Attr] & AM_DIR) { /* Update .. entry in the directory if needed */ + dw = clust2sect(dj_new.fs, (DWORD)LD_WORD(dir+DIR_FstClusHI) | LD_WORD(dir+DIR_FstClusLO)); + if (!dw) { + res = FR_INT_ERR; + } else { + res = move_window(dj_new.fs, dw); + dir = dj_new.fs->win+32; + if (res == FR_OK && dir[1] == '.') { + dw = (dj_new.fs->fs_type == FS_FAT32 && dj_new.sclust == dj_new.fs->dirbase) ? 0 : dj_new.sclust; + ST_WORD(dir+DIR_FstClusLO, dw); + ST_WORD(dir+DIR_FstClusHI, dw >> 16); + dj_new.fs->wflag = 1; + } + } + } + if (res == FR_OK) { + res = dir_remove(&dj_old); /* Remove old entry */ + if (res == FR_OK) + res = sync(dj_old.fs); + } + } + } + + LEAVE_FF(dj_old.fs, res); +} + +#endif /* !_FS_READONLY */ +#endif /* _FS_MINIMIZE == 0 */ +#endif /* _FS_MINIMIZE <= 1 */ +#endif /* _FS_MINIMIZE <= 2 */ + + + +/*-----------------------------------------------------------------------*/ +/* Forward data to the stream directly (Available on only _FS_TINY cfg) */ +/*-----------------------------------------------------------------------*/ +#if _USE_FORWARD && _FS_TINY + +FRESULT f_forward ( + FIL *fp, /* Pointer to the file object */ + UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ + UINT btr, /* Number of bytes to forward */ + UINT *bf /* Pointer to number of bytes forwarded */ +) +{ + FRESULT res; + DWORD remain, clst, sect; + UINT rcnt; + + + *bf = 0; + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check error flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + if (!(fp->flag & FA_READ)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + + remain = fp->fsize - fp->fptr; + if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + + for ( ; btr && (*func)(NULL, 0); /* Repeat until all data transferred or stream becomes busy */ + fp->fptr += rcnt, *bf += rcnt, btr -= rcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + if (fp->csect >= fp->fs->csize) { /* On the cluster boundary? */ + clst = (fp->fptr == 0) ? /* On the top of the file? */ + fp->org_clust : get_fat(fp->fs, fp->curr_clust); + if (clst <= 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->curr_clust = clst; /* Update current cluster */ + fp->csect = 0; /* Reset sector address in the cluster */ + } + fp->csect++; /* Next sector address in the cluster */ + } + sect = clust2sect(fp->fs, fp->curr_clust); /* Get current data sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += fp->csect - 1; + if (move_window(fp->fs, sect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + fp->dsect = sect; + rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs)); /* Forward data from sector window */ + if (rcnt > btr) rcnt = btr; + rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt); + if (!rcnt) ABORT(fp->fs, FR_INT_ERR); + } + + LEAVE_FF(fp->fs, FR_OK); +} +#endif /* _USE_FORWARD */ + + + +#if _USE_MKFS && !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Create File System on the Drive */ +/*-----------------------------------------------------------------------*/ +#define N_ROOTDIR 512 /* Multiple of 32 and <= 2048 */ +#define N_FATS 1 /* 1 or 2 */ +#define MAX_SECTOR 131072000UL /* Maximum partition size */ +#define MIN_SECTOR 2000UL /* Minimum partition size */ + + +FRESULT f_mkfs ( + BYTE drv, /* Logical drive number */ + BYTE partition, /* Partitioning rule 0:FDISK, 1:SFD */ + WORD allocsize /* Allocation unit size [bytes] */ +) +{ + static const DWORD sstbl[] = { 2048000, 1024000, 512000, 256000, 128000, 64000, 32000, 16000, 8000, 4000, 0 }; + static const WORD cstbl[] = { 32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512 }; + BYTE fmt, m, *tbl; + DWORD b_part, b_fat, b_dir, b_data; /* Area offset (LBA) */ + DWORD n_part, n_rsv, n_fat, n_dir; /* Area size */ + DWORD n_clst, d, n; + WORD as; + FATFS *fs; + DSTATUS stat; + + + /* Check validity of the parameters */ + if (drv >= _DRIVES) return FR_INVALID_DRIVE; + if (partition >= 2) return FR_MKFS_ABORTED; + + /* Check mounted drive and clear work area */ + fs = FatFs[drv]; + if (!fs) return FR_NOT_ENABLED; + fs->fs_type = 0; + drv = LD2PD(drv); + + /* Get disk statics */ + stat = disk_initialize(drv); + if (stat & STA_NOINIT) return FR_NOT_READY; + if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; +#if _MAX_SS != 512 /* Get disk sector size */ + if (disk_ioctl(drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK + || SS(fs) > _MAX_SS) + return FR_MKFS_ABORTED; +#endif + if (disk_ioctl(drv, GET_SECTOR_COUNT, &n_part) != RES_OK || n_part < MIN_SECTOR) + return FR_MKFS_ABORTED; + if (n_part > MAX_SECTOR) n_part = MAX_SECTOR; + b_part = (!partition) ? 63 : 0; /* Boot sector */ + n_part -= b_part; + for (d = 512; d <= 32768U && d != allocsize; d <<= 1) ; /* Check validity of the allocation unit size */ + if (d != allocsize) allocsize = 0; + if (!allocsize) { /* Auto selection of cluster size */ + d = n_part; + for (as = SS(fs); as > 512U; as >>= 1) d >>= 1; + for (n = 0; d < sstbl[n]; n++) ; + allocsize = cstbl[n]; + } + if (allocsize < SS(fs)) allocsize = SS(fs); + + allocsize /= SS(fs); /* Number of sectors per cluster */ + + /* Pre-compute number of clusters and FAT type */ + n_clst = n_part / allocsize; + fmt = FS_FAT12; + if (n_clst >= 0xFF5) fmt = FS_FAT16; + if (n_clst >= 0xFFF5) fmt = FS_FAT32; + + /* Determine offset and size of FAT structure */ + switch (fmt) { + case FS_FAT12: + n_fat = ((n_clst * 3 + 1) / 2 + 3 + SS(fs) - 1) / SS(fs); + n_rsv = 1 + partition; + n_dir = N_ROOTDIR * 32 / SS(fs); + break; + case FS_FAT16: + n_fat = ((n_clst * 2) + 4 + SS(fs) - 1) / SS(fs); + n_rsv = 1 + partition; + n_dir = N_ROOTDIR * 32 / SS(fs); + break; + default: + n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs); + n_rsv = 33 - partition; + n_dir = 0; + } + b_fat = b_part + n_rsv; /* FATs start sector */ + b_dir = b_fat + n_fat * N_FATS; /* Directory start sector */ + b_data = b_dir + n_dir; /* Data start sector */ + + /* Align data start sector to erase block boundary (for flash memory media) */ + if (disk_ioctl(drv, GET_BLOCK_SIZE, &n) != RES_OK) return FR_MKFS_ABORTED; + n = (b_data + n - 1) & ~(n - 1); + n_fat += (n - b_data) / N_FATS; + /* b_dir and b_data are no longer used below */ + + /* Determine number of cluster and final check of validity of the FAT type */ + n_clst = (n_part - n_rsv - n_fat * N_FATS - n_dir) / allocsize; + if ( (fmt == FS_FAT16 && n_clst < 0xFF5) + || (fmt == FS_FAT32 && n_clst < 0xFFF5)) + return FR_MKFS_ABORTED; + + /* Create partition table if needed */ + if (!partition) { + DWORD n_disk = b_part + n_part; + + mem_set(fs->win, 0, SS(fs)); + tbl = fs->win+MBR_Table; + ST_DWORD(tbl, 0x00010180); /* Partition start in CHS */ + if (n_disk < 63UL * 255 * 1024) { /* Partition end in CHS */ + n_disk = n_disk / 63 / 255; + tbl[7] = (BYTE)n_disk; + tbl[6] = (BYTE)((n_disk >> 2) | 63); + } else { + ST_WORD(&tbl[6], 0xFFFF); + } + tbl[5] = 254; + if (fmt != FS_FAT32) /* System ID */ + tbl[4] = (n_part < 0x10000) ? 0x04 : 0x06; + else + tbl[4] = 0x0c; + ST_DWORD(tbl+8, 63); /* Partition start in LBA */ + ST_DWORD(tbl+12, n_part); /* Partition size in LBA */ + ST_WORD(tbl+64, 0xAA55); /* Signature */ + if (disk_write(drv, fs->win, 0, 1) != RES_OK) + return FR_DISK_ERR; + partition = 0xF8; + } else { + partition = 0xF0; + } + + /* Create boot record */ + tbl = fs->win; /* Clear buffer */ + mem_set(tbl, 0, SS(fs)); + ST_DWORD(tbl+BS_jmpBoot, 0x90FEEB); /* Boot code (jmp $, nop) */ + ST_WORD(tbl+BPB_BytsPerSec, SS(fs)); /* Sector size */ + tbl[BPB_SecPerClus] = (BYTE)allocsize; /* Sectors per cluster */ + ST_WORD(tbl+BPB_RsvdSecCnt, n_rsv); /* Reserved sectors */ + tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */ + ST_WORD(tbl+BPB_RootEntCnt, SS(fs) / 32 * n_dir); /* Number of rootdir entries */ + if (n_part < 0x10000) { /* Number of total sectors */ + ST_WORD(tbl+BPB_TotSec16, n_part); + } else { + ST_DWORD(tbl+BPB_TotSec32, n_part); + } + tbl[BPB_Media] = partition; /* Media descriptor */ + ST_WORD(tbl+BPB_SecPerTrk, 63); /* Number of sectors per track */ + ST_WORD(tbl+BPB_NumHeads, 255); /* Number of heads */ + ST_DWORD(tbl+BPB_HiddSec, b_part); /* Hidden sectors */ + n = get_fattime(); /* Use current time as a VSN */ + if (fmt != FS_FAT32) { + ST_DWORD(tbl+BS_VolID, n); /* Volume serial number */ + ST_WORD(tbl+BPB_FATSz16, n_fat); /* Number of sectors per FAT */ + tbl[BS_DrvNum] = 0x80; /* Drive number */ + tbl[BS_BootSig] = 0x29; /* Extended boot signature */ + mem_cpy(tbl+BS_VolLab, "NO NAME FAT ", 19); /* Volume label, FAT signature */ + } else { + ST_DWORD(tbl+BS_VolID32, n); /* Volume serial number */ + ST_DWORD(tbl+BPB_FATSz32, n_fat); /* Number of sectors per FAT */ + ST_DWORD(tbl+BPB_RootClus, 2); /* Root directory cluster (2) */ + ST_WORD(tbl+BPB_FSInfo, 1); /* FSInfo record offset (bs+1) */ + ST_WORD(tbl+BPB_BkBootSec, 6); /* Backup boot record offset (bs+6) */ + tbl[BS_DrvNum32] = 0x80; /* Drive number */ + tbl[BS_BootSig32] = 0x29; /* Extended boot signature */ + mem_cpy(tbl+BS_VolLab32, "NO NAME FAT32 ", 19); /* Volume label, FAT signature */ + } + ST_WORD(tbl+BS_55AA, 0xAA55); /* Signature */ + if (SS(fs) > 512U) { + ST_WORD(tbl+SS(fs)-2, 0xAA55); + } + if (disk_write(drv, tbl, b_part+0, 1) != RES_OK) + return FR_DISK_ERR; + if (fmt == FS_FAT32) + disk_write(drv, tbl, b_part+6, 1); + + /* Initialize FAT area */ + for (m = 0; m < N_FATS; m++) { + mem_set(tbl, 0, SS(fs)); /* 1st sector of the FAT */ + if (fmt != FS_FAT32) { + n = (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00; + n |= partition; + ST_DWORD(tbl, n); /* Reserve cluster #0-1 (FAT12/16) */ + } else { + ST_DWORD(tbl+0, 0xFFFFFFF8); /* Reserve cluster #0-1 (FAT32) */ + ST_DWORD(tbl+4, 0xFFFFFFFF); + ST_DWORD(tbl+8, 0x0FFFFFFF); /* Reserve cluster #2 for root dir */ + } + if (disk_write(drv, tbl, b_fat++, 1) != RES_OK) + return FR_DISK_ERR; + mem_set(tbl, 0, SS(fs)); /* Following FAT entries are filled by zero */ + for (n = 1; n < n_fat; n++) { + if (disk_write(drv, tbl, b_fat++, 1) != RES_OK) + return FR_DISK_ERR; + } + } + + /* Initialize Root directory */ + m = (BYTE)((fmt == FS_FAT32) ? allocsize : n_dir); + do { + if (disk_write(drv, tbl, b_fat++, 1) != RES_OK) + return FR_DISK_ERR; + } while (--m); + + /* Create FSInfo record if needed */ + if (fmt == FS_FAT32) { + ST_WORD(tbl+BS_55AA, 0xAA55); + ST_DWORD(tbl+FSI_LeadSig, 0x41615252); + ST_DWORD(tbl+FSI_StrucSig, 0x61417272); + ST_DWORD(tbl+FSI_Free_Count, n_clst - 1); + ST_DWORD(tbl+FSI_Nxt_Free, 0xFFFFFFFF); + disk_write(drv, tbl, b_part+1, 1); + disk_write(drv, tbl, b_part+7, 1); + } + + return (disk_ioctl(drv, CTRL_SYNC, (void*)NULL) == RES_OK) ? FR_OK : FR_DISK_ERR; +} + +#endif /* _USE_MKFS && !_FS_READONLY */ + + + + +#if _USE_STRFUNC +/*-----------------------------------------------------------------------*/ +/* Get a string from the file */ +/*-----------------------------------------------------------------------*/ +char* f_gets ( + char* buff, /* Pointer to the string buffer to read */ + int len, /* Size of string buffer */ + FIL* fil /* Pointer to the file object */ +) +{ + int i = 0; + char *p = buff; + UINT rc; + + + while (i < len - 1) { /* Read bytes until buffer gets filled */ + f_read(fil, p, 1, &rc); + if (rc != 1) break; /* Break when no data to read */ +#if _USE_STRFUNC >= 2 + if (*p == '\r') continue; /* Strip '\r' */ +#endif + i++; + if (*p++ == '\n') break; /* Break when reached end of line */ + } + *p = 0; + return i ? buff : NULL; /* When no data read (eof or error), return with error. */ +} + + + +#if !_FS_READONLY +#include +/*-----------------------------------------------------------------------*/ +/* Put a character to the file */ +/*-----------------------------------------------------------------------*/ +int f_putc ( + int chr, /* A character to be output */ + FIL* fil /* Pointer to the file object */ +) +{ + UINT bw; + char c; + + +#if _USE_STRFUNC >= 2 + if (chr == '\n') f_putc ('\r', fil); /* LF -> CRLF conversion */ +#endif + if (!fil) { /* Special value may be used to switch the destination to any other device */ + /* put_console(chr); */ + return chr; + } + c = (char)chr; + f_write(fil, &c, 1, &bw); /* Write a byte to the file */ + return bw ? chr : EOF; /* Return the result */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a string to the file */ +/*-----------------------------------------------------------------------*/ +int f_puts ( + const char* str, /* Pointer to the string to be output */ + FIL* fil /* Pointer to the file object */ +) +{ + int n; + + + for (n = 0; *str; str++, n++) { + if (f_putc(*str, fil) == EOF) return EOF; + } + return n; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a formatted string to the file */ +/*-----------------------------------------------------------------------*/ +int f_printf ( + FIL* fil, /* Pointer to the file object */ + const char* str, /* Pointer to the format string */ + ... /* Optional arguments... */ +) +{ + va_list arp; + UCHAR c, f, r; + ULONG val; + char s[16]; + int i, w, res, cc; + + + va_start(arp, str); + + for (cc = res = 0; cc != EOF; res += cc) { + c = *str++; + if (c == 0) break; /* End of string */ + if (c != '%') { /* Non escape character */ + cc = f_putc(c, fil); + if (cc != EOF) cc = 1; + continue; + } + w = f = 0; + c = *str++; + if (c == '0') { /* Flag: '0' padding */ + f = 1; c = *str++; + } + while (c >= '0' && c <= '9') { /* Precision */ + w = w * 10 + (c - '0'); + c = *str++; + } + if (c == 'l') { /* Prefix: Size is long int */ + f |= 2; c = *str++; + } + if (c == 's') { /* Type is string */ + cc = f_puts(va_arg(arp, char*), fil); + continue; + } + if (c == 'c') { /* Type is character */ + cc = f_putc(va_arg(arp, int), fil); + if (cc != EOF) cc = 1; + continue; + } + r = 0; + if (c == 'd') r = 10; /* Type is signed decimal */ + if (c == 'u') r = 10; /* Type is unsigned decimal */ + if (c == 'X') r = 16; /* Type is unsigned hexdecimal */ + if (r == 0) break; /* Unknown type */ + if (f & 2) { /* Get the value */ + val = (ULONG)va_arg(arp, long); + } else { + val = (c == 'd') ? (ULONG)(long)va_arg(arp, int) : (ULONG)va_arg(arp, unsigned int); + } + /* Put numeral string */ + if (c == 'd') { + if (val & 0x80000000) { + val = 0 - val; + f |= 4; + } + } + i = sizeof(s) - 1; s[i] = 0; + do { + c = (UCHAR)(val % r + '0'); + if (c > '9') c += 7; + s[--i] = c; + val /= r; + } while (i && val); + if (i && (f & 4)) s[--i] = '-'; + w = sizeof(s) - 1 - w; + while (i && i > w) s[--i] = (f & 1) ? '0' : ' '; + cc = f_puts(&s[i], fil); + } + + va_end(arp); + return (cc == EOF) ? cc : res; +} + +#endif /* !_FS_READONLY */ +#endif /* _USE_STRFUNC */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/gd32vf103_it.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/gd32vf103_it.c new file mode 100644 index 0000000..87cf4a1 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/gd32vf103_it.c @@ -0,0 +1,63 @@ +/*! + \file gd32vf103_it.c + \brief main interrupt service routines + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usbh_int.h" +#include "drv_usb_hw.h" +#include "gd32vf103_it.h" + +extern usb_core_driver usbh_msc_core; + +extern void usb_timer_irq (void); + +/*! + \brief this function handles USBD interrupt + \param[in] none + \param[out] none + \retval none +*/ +void USBFS_IRQHandler (void) +{ + usbh_isr (&usbh_msc_core); +} + +/*! + \brief this function handles timer2 updata interrupt request. + \param[in] none + \param[out] none + \retval none +*/ +void TIMER2_IRQHandler(void) +{ + usb_timer_irq(); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/gd32vf103_usb_hw.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/gd32vf103_usb_hw.c new file mode 100644 index 0000000..4447273 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/gd32vf103_usb_hw.c @@ -0,0 +1,256 @@ +/*! + \file gd32vf103_usb_hw.c + \brief this file implements the board support package for the USB host library + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include +#include +#include + +#define TIM_MSEC_DELAY 0x01 +#define TIM_USEC_DELAY 0x02 + +#define HOST_POWERSW_PORT_RCC RCU_GPIOD +#define HOST_POWERSW_PORT GPIOD +#define HOST_POWERSW_VBUS GPIO_PIN_13 + +__IO uint32_t delay_time = 0; +__IO uint32_t usbfs_prescaler = 0; +__IO uint32_t timer_prescaler = 5; + +static void hwp_time_set (uint8_t unit); +static void hwp_delay (uint32_t ntime, uint8_t unit); + +/*! + \brief configure USB clock + \param[in] none + \param[out] none + \retval none +*/ +void usb_rcu_config (void) +{ + uint32_t system_clock = rcu_clock_freq_get(CK_SYS); + + if (system_clock == 48000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1; + timer_prescaler = 3; + } else if (system_clock == 72000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1_5; + timer_prescaler = 5; + } else if (system_clock == 96000000) { + usbfs_prescaler = RCU_CKUSB_CKPLL_DIV2; + timer_prescaler = 7; + } else { + /* reserved */ + } + + rcu_usb_clock_config(usbfs_prescaler); + rcu_periph_clock_enable(RCU_USBFS); +} + +/*! + \brief configure USB global interrupt + \param[in] none + \param[out] none + \retval none +*/ +void usb_intr_config (void) +{ + eclic_irq_enable((uint8_t)USBFS_IRQn, 1, 0); + +#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT + + /* enable the power module clock */ + rcu_periph_clock_enable(RCU_PMU); + + /* USB wakeup EXTI line configuration */ + exti_interrupt_flag_clear(EXTI_18); + exti_init(EXTI_18, EXTI_INTERRUPT, EXTI_TRIG_RISING); + exti_interrupt_enable(EXTI_18); + + eclic_irq_enable((uint8_t)USBFS_WKUP_IRQn, 3U, 0U); + +#endif /* USBHS_LOW_PWR_MGMT_SUPPORT */ +} + +/*! + \brief drives the VBUS signal through gpio + \param[in] state: VBUS states + \param[out] none + \retval none +*/ +void usb_vbus_drive (uint8_t state) +{ + if (0 == state) + { + /* DISABLE is needed on output of the Power Switch */ + gpio_bit_reset(HOST_POWERSW_PORT, HOST_POWERSW_VBUS); + } + else + { + /*ENABLE the Power Switch by driving the Enable LOW */ + gpio_bit_set(HOST_POWERSW_PORT, HOST_POWERSW_VBUS); + } +} + +/*! + \brief configures the GPIO for the VBUS + \param[in] none + \param[out] none + \retval none +*/ +void usb_vbus_config (void) +{ + rcu_periph_clock_enable(HOST_POWERSW_PORT_RCC); + + gpio_init(HOST_POWERSW_PORT, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, HOST_POWERSW_VBUS); + + /* by default, disable is needed on output of the power switch */ + gpio_bit_set(HOST_POWERSW_PORT, HOST_POWERSW_VBUS); + + /* Delay is need for stabilising the Vbus Low in Reset Condition, + * when Vbus=1 and Reset-button is pressed by user + */ + usb_mdelay (2); +} + +/*! + \brief initializes delay unit using Timer2 + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_init (void) +{ + rcu_periph_clock_enable(RCU_TIMER2); + + eclic_irq_enable(TIMER2_IRQn, 2, 0); +} + +/*! + \brief delay in micro seconds + \param[in] usec: value of delay required in micro seconds + \param[out] none + \retval none +*/ +void usb_udelay (const uint32_t usec) +{ + hwp_delay(usec, TIM_USEC_DELAY); +} + +/*! + \brief delay in milli seconds + \param[in] msec: value of delay required in milli seconds + \param[out] none + \retval none +*/ +void usb_mdelay (const uint32_t msec) +{ + hwp_delay(msec, TIM_MSEC_DELAY); +} + +/*! + \brief timer base IRQ + \param[in] none + \param[out] none + \retval none +*/ +void usb_timer_irq (void) +{ + if (timer_interrupt_flag_get(TIMER2, TIMER_INT_UP) != RESET){ + timer_interrupt_flag_clear(TIMER2, TIMER_INT_UP); + + if (delay_time > 0x00U){ + delay_time--; + } else { + timer_disable(TIMER2); + } + } +} + +/*! + \brief delay routine based on TIM2 + \param[in] ntime: delay Time + \param[in] unit: delay Time unit = mili sec / micro sec + \param[out] none + \retval none +*/ +static void hwp_delay(uint32_t ntime, uint8_t unit) +{ + delay_time = ntime; + hwp_time_set(unit); + + while(delay_time != 0); + + timer_disable(TIMER2); +} + +/*! + \brief configures TIM2 for delay routine based on TIM2 + \param[in] unit: msec /usec + \param[out] none + \retval none +*/ +static void hwp_time_set(uint8_t unit) +{ + timer_parameter_struct timer_basestructure; + + timer_disable(TIMER2); + timer_interrupt_disable(TIMER2, TIMER_INT_UP); + + if (unit == TIM_USEC_DELAY) { + timer_basestructure.period = 11; + } else if(unit == TIM_MSEC_DELAY) { + timer_basestructure.period = 11999; + } else { + /* no operation */ + } + + timer_basestructure.prescaler = timer_prescaler; + timer_basestructure.alignedmode = TIMER_COUNTER_EDGE; + timer_basestructure.counterdirection = TIMER_COUNTER_UP; + timer_basestructure.clockdivision = TIMER_CKDIV_DIV1; + timer_basestructure.repetitioncounter = 0; + + timer_init(TIMER2, &timer_basestructure); + + timer_interrupt_flag_clear(TIMER2, TIMER_INT_UP); + + timer_auto_reload_shadow_enable(TIMER2); + + /* timer2 interrupt enable */ + timer_interrupt_enable(TIMER2, TIMER_INT_UP); + + /* timer2 enable counter */ + timer_enable(TIMER2); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/lcd_font.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/lcd_font.c new file mode 100644 index 0000000..4e872c3 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/lcd_font.c @@ -0,0 +1,709 @@ +/*! + \file lcd_font.c + \brief text fonts driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "lcd_font.h" + +unsigned char const ascii_8x16[1536] = { +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x18,0x3C,0x3C,0x3C,0x18,0x18,0x18,0x00,0x18,0x18,0x00,0x00,0x00,0x00, +0x00,0x66,0x66,0x66,0x24,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x6C,0x6C,0xFE,0x6C,0x6C,0x6C,0xFE,0x6C,0x6C,0x00,0x00,0x00,0x00, +0x18,0x18,0x7C,0xC6,0xC2,0xC0,0x7C,0x06,0x86,0xC6,0x7C,0x18,0x18,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0xC2,0xC6,0x0C,0x18,0x30,0x60,0xC6,0x86,0x00,0x00,0x00,0x00, +0x00,0x00,0x38,0x6C,0x6C,0x38,0x76,0xDC,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00, +0x00,0x30,0x30,0x30,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x0C,0x18,0x30,0x30,0x30,0x30,0x30,0x30,0x18,0x0C,0x00,0x00,0x00,0x00, +0x00,0x00,0x30,0x18,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x18,0x30,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x66,0x3C,0xFF,0x3C,0x66,0x00,0x00,0x00,0x00,0x00,0x00, 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+0x00,0x00,0x00,0x00,0x10,0x38,0x6C,0xC6,0xC6,0xC6,0xFE,0x00,0x00,0x00,0x00,0x00 +}; + +/* ASCII Table: each character is 16 column (16dots large) and 24 raw (24 dots high) */ +const uint16_t ASCII_Table_16x24[] = +{ +/** + * @brief Space ' ' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '!' + */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '"' + */ + 0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '#' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60, + 0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318, + 0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000, +/** + * @brief '$' + */ + 0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C, + 0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C, + 0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000, +/** + * @brief '%' + */ + 0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611, + 0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460, + 0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000, +/** + * @brief '&' + */ + 0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0, + 0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06, + 0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ''' + */ + 0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '(' + */ + 0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060, + 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, + 0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000, +/** + * @brief ')' + */ + 0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300, + 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, + 0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000, +/** + * @brief '*' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '+' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ',' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, +/** + * @brief '-' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '.' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '/' + */ + 0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300, + 0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0, + 0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '0' + */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C, + 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '1' + */ + 0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '2' + */ + 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800, + 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, + 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '3' + */ + 0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600, + 0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18, + 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '4' + */ + 0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60, + 0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00, + 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '5' + */ + 0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC, + 0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18, + 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '6' + */ + 0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC, + 0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '7' + */ + 0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380, + 0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030, + 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '8' + */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638, + 0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38, + 0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '9' + */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C, + 0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C, + 0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ':' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ';' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000, +/** + * @brief '<' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0, + 0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '=' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '>' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0, + 0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '?' + */ + 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00, + 0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '@' + */ + 0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411, + 0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004, + 0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'A' + */ + 0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60, + 0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C, + 0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'B' + */ + 0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C, + 0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C, + 0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'C' + */ + 0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006, + 0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C, + 0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'D' + */ + 0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006, + 0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06, + 0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'E' + */ + 0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'F' + */ + 0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'G' + */ + 0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003, + 0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C, + 0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'H' + */ + 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'I' + */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'J' + */ + 0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, + 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738, + 0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'K' + */ + 0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6, + 0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806, + 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'L' + */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'M' + */ + 0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836, + 0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6, + 0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'N' + */ + 0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC, + 0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C, + 0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'O' + */ + 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003, + 0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C, + 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'P' + */ + 0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'Q' + */ + 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003, + 0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C, + 0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'R' + */ + 0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806, + 0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006, + 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'S' + */ + 0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C, + 0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C, + 0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'T' + */ + 0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'U' + */ + 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818, + 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'V' + */ + 0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C, + 0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360, + 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'W' + */ + 0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366, + 0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C, + 0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'X' + */ + 0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0, + 0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C, + 0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'Y' + */ + 0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660, + 0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'Z' + */ + 0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600, + 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006, + 0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '[' + */ + 0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, + 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, + 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000, +/** + * @brief '\' + */ + 0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0, + 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300, + 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ']' + */ + 0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, + 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, + 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000, +/** + * @brief '^' + */ + 0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630, + 0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '_' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ''' + */ + 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'a' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8, + 0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C, + 0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'b' + */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8, + 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38, + 0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'c' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0, + 0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30, + 0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'd' + */ + 0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0, + 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30, + 0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'e' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0, + 0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30, + 0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'f' + */ + 0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'g' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8, + 0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18, + 0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000, +/** + * @brief 'h' + */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8, + 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, + 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'i' + */ + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'j' + */ + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000, +/** + * @brief 'k' + */ + 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C, + 0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C, + 0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'l' + */ + 0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'm' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF, + 0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, + 0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'n' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8, + 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, + 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'o' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0, + 0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30, + 0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'p' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8, + 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38, + 0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000, +/** + * @brief 'q' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0, + 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30, + 0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000, +/** + * @brief 'r' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0, + 0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, + 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 's' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0, + 0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 't' + */ + 0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'u' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818, + 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38, + 0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'v' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18, + 0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360, + 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'w' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1, + 0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C, + 0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'x' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38, + 0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30, + 0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'y' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830, + 0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380, + 0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000, +/** + * @brief 'z' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC, + 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, + 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '{' + */ + 0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000, +/** + * @brief '|' + */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, +/** + * @brief '}' + */ + 0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000, +/** + * @brief '~' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +}; diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/lcd_log.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/lcd_log.c new file mode 100644 index 0000000..8dd216a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/lcd_log.c @@ -0,0 +1,168 @@ +/*! + \file lcd_log.c + \brief LCD log driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "lcd_log.h" +#include "string.h" + +#include "gd32vf103v_lcd_eval.h" + +uint16_t LINE; + +char_format_struct charform = { + .font = CHAR_FONT_8_16, + .direction = CHAR_DIRECTION_HORIZONTAL, + .char_color = LCD_COLOR_RED, + .bk_color = LCD_COLOR_BLACK +}; + +/*! + \brief initialize the LCD log module + \param[in] none + \param[out] none + \retval none +*/ +void lcd_log_init (void) +{ + lcd_clear(LCD_COLOR_BLACK); +} + +/*! + \brief de-initialize the LCD log module + \param[in] none + \param[out] none + \retval none +*/ +void lcd_log_deinit (void) +{ +} + +/*! + \brief display the application header (title) on the LCD screen + \param[in] p_title: pointer to the string to be displayed + \param[in] start_x: the start x position + \param[out] none + \retval none +*/ +void lcd_log_header_set (uint8_t *p_title, uint16_t start_x) +{ + uint16_t i = 0; + uint16_t str_len = strlen((const char *)p_title); + + lcd_rectangle_fill(210, 0, 240, 320, LCD_COLOR_BLUE); + + charform.bk_color = LCD_COLOR_BLUE; + + for (i = 0; i < str_len; i++) { + lcd_char_display (230, (start_x + 8 * i), p_title[i], charform); + } + +} + +/*! + \brief display the application footer (status) on the LCD screen + \param[in] p_status: pointer to the string to be displayed + \param[in] start_x: the start x position + \param[out] none + \retval none +*/ +void lcd_log_footer_set (uint8_t *p_status, uint16_t start_x) +{ + uint16_t i = 0; + uint16_t str_len = strlen((const char *)p_status); + + lcd_rectangle_fill(0, 0, 30, 320, LCD_COLOR_BLUE); + + + charform.bk_color = LCD_COLOR_BLUE; + + for (i = 0; i < str_len; i++) { + lcd_char_display (20, (start_x + 8 * i), p_status[i], charform); + } + +} + +/*! + \brief clear the text zone + \param[in] start_x: the start x position + \param[in] start_y: the start y position + \param[in] width: the width to clear text zone + \param[in] height: the heitht to clear text zone + \param[out] none + \retval none +*/ +void lcd_log_text_zone_clear(uint16_t start_x, + uint16_t start_y, + uint16_t width, + uint16_t height) +{ + lcd_rectangle_fill(start_x, start_y, width, height, LCD_COLOR_BLACK); +} + +/*! + \brief redirect the printf to the lcd + \param[in] p_str: pointer to string to be displayed + \param[in] offset: the offset to set + \param[in] char_color: the clar color to set + \param[out] none + \retval none +*/ +void lcd_log_print (uint8_t *p_str, uint16_t offset, uint16_t char_color) +{ + uint16_t i; + +#if defined(USE_HOST_MODE) && defined(USE_DEVICE_MODE) + if(LINE <= 60) + { + LINE = 190; + + lcd_rectangle_fill(60, 0, 210, 320, LCD_COLOR_BLACK); + } +#else + if(LINE <= 30) + { + LINE = 190; + + lcd_rectangle_fill(30, 0, 210, 320, LCD_COLOR_BLACK); + } +#endif + + charform.bk_color = LCD_COLOR_BLACK; + charform.char_color = char_color; + + for (i = 0; i < offset; i++) { + lcd_char_display(LINE, (10 + 8 * i), *p_str++, charform); + } + + LINE -= 20; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/system_gd32vf103.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/system_gd32vf103.c new file mode 100644 index 0000000..05e5205 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/system_gd32vf103.c @@ -0,0 +1,998 @@ +/*! + \file system_gd32vf103.h + \brief RISC-V Device Peripheral Access Layer Source File for + GD32VF103 Device Series + +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32vf103.h" + +/* system frequency define */ +#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ + +/* select a system clock by uncommenting the following line */ +/* use IRC8M */ +//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000) + +/********************************************************************/ +//#define __SYSTEM_CLOCK_HXTAL (HXTAL_VALUE) +//#define __SYSTEM_CLOCK_24M_PLL_HXTAL (uint32_t)(24000000) +/********************************************************************/ + +//#define __SYSTEM_CLOCK_36M_PLL_HXTAL (uint32_t)(36000000) +//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_56M_PLL_HXTAL (uint32_t)(56000000) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000) +//#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) + +#define SEL_IRC8M 0x00U +#define SEL_HXTAL 0x01U +#define SEL_PLL 0x02U + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_48M_PLL_IRC8M +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M; +static void system_clock_48m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M; +static void system_clock_72m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M; +static void system_clock_108m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; +static void system_clock_hxtal(void); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_24M_PLL_HXTAL; +static void system_clock_24m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_36M_PLL_HXTAL; +static void system_clock_36m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL; +static void system_clock_48m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_56M_PLL_HXTAL; +static void system_clock_56m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; +static void system_clock_72m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL; +static void system_clock_96m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; +static void system_clock_108m_hxtal(void); +#else +uint32_t SystemCoreClock = IRC8M_VALUE; +#endif /* __SYSTEM_CLOCK_48M_PLL_IRC8M */ + +/* configure the system clock */ +static void system_clock_config(void); + +/*! + \brief configure the system clock + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_config(void) +{ +#ifdef __SYSTEM_CLOCK_HXTAL + system_clock_hxtal(); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) + system_clock_24m_hxtal(); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) + system_clock_36m_hxtal(); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) + system_clock_48m_hxtal(); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) + system_clock_56m_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) + system_clock_72m_hxtal(); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) + system_clock_96m_hxtal(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) + system_clock_108m_hxtal(); + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) + system_clock_48m_irc8m(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) + system_clock_72m_irc8m(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) + system_clock_108m_irc8m(); +#endif /* __SYSTEM_CLOCK_HXTAL */ +} + +/*! + \brief setup the microcontroller system, initialize the system + \param[in] none + \param[out] none + \retval none +*/ +void SystemInit(void) +{ + /* reset the RCC clock configuration to the default reset state */ + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL); + + /* reset HXTALEN, CKMEN, PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); + + /* Reset HXTALBPS bit */ + RCU_CTL &= ~(RCU_CTL_HXTALBPS); + + /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */ + + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | + RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4); + RCU_CFG1 = 0x00000000U; + + /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + /* disable all interrupts */ + RCU_INT = 0x00FF0000U; + + /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ + system_clock_config(); +} + +/*! + \brief update the SystemCoreClock with current core clock retrieved from cpu registers + \param[in] none + \param[out] none + \retval none +*/ +void SystemCoreClockUpdate(void) +{ + uint32_t scss; + uint32_t pllsel, predv0sel, pllmf, ck_src; + uint32_t predv0, predv1, pll1mf; + + scss = GET_BITS(RCU_CFG0, 2, 3); + + switch (scss) + { + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + SystemCoreClock = IRC8M_VALUE; + break; + + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + SystemCoreClock = HXTAL_VALUE; + break; + + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + + + if(RCU_PLLSRC_IRC8M_DIV2 == pllsel){ + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE / 2U; + }else{ + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + + predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); + + /* source clock use PLL1 */ + if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ + predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; + pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; + if(17U == pll1mf){ + pll1mf = 20U; + } + ck_src = (ck_src / predv1) * pll1mf; + } + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; + ck_src /= predv0; + } + + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + + if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ + pllmf |= 0x10U; + } + + if(pllmf >= 15U){ + pllmf += 1U; + }else{ + pllmf += 2U; + } + + SystemCoreClock = ck_src * pllmf; + + if(15U == pllmf){ + /* PLL source clock multiply by 6.5 */ + SystemCoreClock = ck_src * 6U + ck_src / 2U; + } + + break; + + /* IRC8M is selected as CK_SYS */ + default: + SystemCoreClock = IRC8M_VALUE; + break; + } +} + +#ifdef __SYSTEM_CLOCK_HXTAL +/*! + \brief configure the system clock to HXTAL + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + + /* wait until HXTAL is selected as system clock */ + while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +/*! + \brief configure the system clock to 24M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_24m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 6 = 24 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +/*! + \brief configure the system clock to 36M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_36m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 9 = 36 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +/*! + \brief configure the system clock to 48M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12); + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +/*! + \brief configure the system clock to 56M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_56m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 14 = 56 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL14); + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +/*! + \brief configure the system clock to 72M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18); + + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +/*! + \brief configure the system clock to 96M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_96m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + if(HXTAL_VALUE==25000000){ + + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +/*! + \brief configure the system clock to 108M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ + +static void system_clock_108m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PREDV1_DIV5 | RCU_PLL1_MUL8 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL2EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){ + } + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 | RCU_PREDV1_DIV2 | RCU_PLL1_MUL20 | RCU_PLL2_MUL20); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } + + /* enable PLL2 */ + RCU_CTL |= RCU_CTL_PLL2EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){ + } + + } + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) +/*! + \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL12; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +/*! + \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL18; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +/*! + \brief configure the system clock to 108M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL27; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#endif diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/usbh_msc_bbb.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/usbh_msc_bbb.c new file mode 100644 index 0000000..eadf765 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/usbh_msc_bbb.c @@ -0,0 +1,454 @@ +/*! + \file usbh_msc_bbb.c + \brief USB MSC BBB protocol related functions + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_transc.h" +#include "drv_usbh_int.h" +#include "usbh_msc_core.h" +#include "usbh_msc_scsi.h" +#include "usbh_msc_bbb.h" + +usbh_cbw_pkt msc_cbw_data; +usbh_csw_pkt msc_csw_data; + +static uint32_t bot_stall_error_count; /* keeps count of stall error cases */ +usbh_botxfer msc_botxfer_param; + +/*! + \brief initialize the mass storage parameters + \param[in] pudev: pointer to usb core instance + \param[out] none + \retval none +*/ +void usbh_msc_init (usb_core_driver *pudev) +{ + if (pudev->host.connect_status) { + msc_cbw_data.field.dCBWSignature = BBB_CBW_SIGNATURE; + msc_cbw_data.field.dCBWTag = USBH_MSC_BOT_CBW_TAG; + msc_cbw_data.field.bCBWLUN = 0; /* only one lun is supported */ + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + } + + bot_stall_error_count = 0; + + msc_error_count = 0; +} + +/*! + \brief manage the different states of BOT transfer and updates the status to upper layer + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval none +*/ +void usbh_msc_botxfer (usb_core_driver *pudev, usbh_host *puhost) +{ + uint8_t xfer_dir, index; + static uint32_t remain_len; + static uint8_t *data_pointer, *data_pointer_prev; + static uint8_t error_dir; + + usbh_status status; + + usb_urb_state URB_Status = URB_IDLE; + + if (pudev->host.connect_status) { + switch (msc_botxfer_param.bot_state) { + case USBH_MSC_SEND_CBW: + /* send CBW */ + usbh_data_send (pudev, + &msc_cbw_data.CBWArray[0], + msc_machine.hc_num_out, + BBB_CBW_LENGTH); + + msc_botxfer_param.bot_state_bkp = USBH_MSC_SEND_CBW; + msc_botxfer_param.bot_state = USBH_MSC_SENT_CBW; + break; + + case USBH_MSC_SENT_CBW: + URB_Status = usbh_urbstate_get(pudev, msc_machine.hc_num_out); + + if (URB_Status == URB_DONE) { + bot_stall_error_count = 0; + msc_botxfer_param.bot_state_bkp = USBH_MSC_SENT_CBW; + + /* if the CBW packet is sent successful, then change the state */ + xfer_dir = (msc_cbw_data.field.bmCBWFlags & USB_TRX_MASK); + + if (msc_cbw_data.field.dCBWDataTransferLength != 0) { + remain_len = msc_cbw_data.field.dCBWDataTransferLength; + data_pointer = msc_botxfer_param.xfer_buf; + data_pointer_prev = data_pointer; + + /* if there is data transfer stage */ + if (xfer_dir == USB_TRX_IN) { + /* data direction is IN */ + msc_botxfer_param.bot_state = USBH_MSC_BOT_DATAIN_STATE; + } else { + /* data direction is OUT */ + msc_botxfer_param.bot_state = USBH_MSC_BOT_DATAOUT_STATE; + } + } else { + /* If there is NO Data Transfer Stage */ + msc_botxfer_param.bot_state = USBH_MSC_RECEIVE_CSW_STATE; + } + } else if (URB_Status == URB_NOTREADY) { + msc_botxfer_param.bot_state = msc_botxfer_param.bot_state_bkp; + } else if (URB_Status == URB_STALL) { + error_dir = USBH_MSC_DIR_OUT; + msc_botxfer_param.bot_state = USBH_MSC_BOT_ERROR_OUT; + } + break; + + case USBH_MSC_BOT_DATAIN_STATE: + URB_Status = usbh_urbstate_get(pudev, msc_machine.hc_num_in); + + /* BOT DATA IN stage */ + if ((URB_Status == URB_DONE) || + (msc_botxfer_param.bot_state_bkp != USBH_MSC_BOT_DATAIN_STATE)) { + bot_stall_error_count = 0; + msc_botxfer_param.bot_state_bkp = USBH_MSC_BOT_DATAIN_STATE; + + if (remain_len > msc_machine.msc_bulk_epinsize) { + usbh_data_recev (pudev, + data_pointer, + msc_machine.hc_num_in, + msc_machine.msc_bulk_epinsize); + + remain_len -= msc_machine.msc_bulk_epinsize; + data_pointer = data_pointer + msc_machine.msc_bulk_epinsize; + } else if (remain_len == 0) { + /* if value was 0, and successful transfer, then change the state */ + msc_botxfer_param.bot_state = USBH_MSC_RECEIVE_CSW_STATE; + } else { + usbh_data_recev (pudev, + data_pointer, + msc_machine.hc_num_in, + remain_len); + + remain_len = 0; /* reset this value and keep in same state */ + } + } else if(URB_Status == URB_STALL) { + /* this is data stage stall condition */ + + error_dir = USBH_MSC_DIR_IN; + msc_botxfer_param.bot_state = USBH_MSC_BOT_ERROR_IN; + + /* Refer to USB Mass-Storage Class : BOT (www.usb.org) + 6.7.2 Host expects to receive data from the device + 3. On a STALL condition receiving data, then: + The host shall accept the data received. + The host shall clear the Bulk-In pipe. + 4. The host shall attempt to receive a CSW. + + msc_botxfer_param.bot_state_bkp is used to switch to the Original + state after the ClearFeature Command is issued. + */ + msc_botxfer_param.bot_state_bkp = USBH_MSC_RECEIVE_CSW_STATE; + } + break; + + case USBH_MSC_BOT_DATAOUT_STATE: + /* BOT DATA OUT stage */ + URB_Status = usbh_urbstate_get(pudev, msc_machine.hc_num_out); + if (URB_Status == URB_DONE) { + bot_stall_error_count = 0; + msc_botxfer_param.bot_state_bkp = USBH_MSC_BOT_DATAOUT_STATE; + + if (remain_len > msc_machine.msc_bulk_epoutsize) { + usbh_data_send (pudev, + data_pointer, + msc_machine.hc_num_out, + msc_machine.msc_bulk_epoutsize); + + data_pointer_prev = data_pointer; + data_pointer = data_pointer + msc_machine.msc_bulk_epoutsize; + + remain_len = remain_len - msc_machine.msc_bulk_epoutsize; + } else if (remain_len == 0) { + /* if value was 0, and successful transfer, then change the state */ + msc_botxfer_param.bot_state = USBH_MSC_RECEIVE_CSW_STATE; + } else { + usbh_data_send (pudev, + data_pointer, + msc_machine.hc_num_out, + remain_len); + + remain_len = 0; /* reset this value and keep in same state */ + } + } else if (URB_Status == URB_NOTREADY) { + if (data_pointer != data_pointer_prev) { + usbh_data_send (pudev, + (data_pointer - msc_machine.msc_bulk_epoutsize), + msc_machine.hc_num_out, + msc_machine.msc_bulk_epoutsize); + } else { + usbh_data_send (pudev, + data_pointer, + msc_machine.hc_num_out, + msc_machine.msc_bulk_epoutsize); + } + } else if (URB_Status == URB_STALL) { + error_dir = USBH_MSC_DIR_OUT; + msc_botxfer_param.bot_state = USBH_MSC_BOT_ERROR_OUT; + + /* Refer to USB Mass-Storage Class : BOT (www.usb.org) + 6.7.3 Ho - Host expects to send data to the device + 3. On a STALL condition sending data, then: + " The host shall clear the Bulk-Out pipe. + 4. The host shall attempt to receive a CSW. + + The Above statement will do the clear the Bulk-Out pipe. + The Below statement will help in Getting the CSW. + + msc_botxfer_param.bot_state_bkp is used to switch to the Original + state after the ClearFeature Command is issued. + */ + + msc_botxfer_param.bot_state_bkp = USBH_MSC_RECEIVE_CSW_STATE; + } + break; + + case USBH_MSC_RECEIVE_CSW_STATE: + /* BOT CSW stage */ + /* NOTE: We cannot reset the BOTStallErrorCount here as it may come from the clearFeature from previous command */ + msc_botxfer_param.bot_state_bkp = USBH_MSC_RECEIVE_CSW_STATE; + msc_botxfer_param.xfer_buf = msc_csw_data.CSWArray; + msc_botxfer_param.data_len = USBH_MSC_CSW_MAX_LENGTH; + + for (index = BBB_CSW_LENGTH; index != 0; index--) { + msc_csw_data.CSWArray[index] = 0; + } + + msc_csw_data.CSWArray[0] = 0; + + usbh_data_recev (pudev, + msc_botxfer_param.xfer_buf, + msc_machine.hc_num_in, + USBH_MSC_CSW_MAX_LENGTH); + + msc_botxfer_param.bot_state = USBH_MSC_DECODE_CSW; + break; + + case USBH_MSC_DECODE_CSW: + URB_Status = usbh_urbstate_get(pudev, msc_machine.hc_num_in); + + /* decode CSW */ + if (URB_Status == URB_DONE) { + bot_stall_error_count = 0; + msc_botxfer_param.bot_state_bkp = USBH_MSC_RECEIVE_CSW_STATE; + msc_botxfer_param.msc_state = msc_botxfer_param.msc_state_current ; + msc_botxfer_param.bot_xfer_status = usbh_msc_csw_decode (pudev , puhost); + } else if (URB_Status == URB_STALL) { + error_dir = USBH_MSC_DIR_IN; + msc_botxfer_param.bot_state = USBH_MSC_BOT_ERROR_IN; + } + break; + + case USBH_MSC_BOT_ERROR_IN: + status = usbh_msc_bot_abort(pudev, puhost, USBH_MSC_DIR_IN); + + if (status == USBH_OK) { + /* check if the error was due in both the directions */ + if (error_dir == USBH_MSC_BOTH_DIR) { + /* if both directions are needed, switch to OUT direction */ + msc_botxfer_param.bot_state = USBH_MSC_BOT_ERROR_OUT; + } else { + /* switch back to the original state, in many cases this will be USBH_MSC_RECEIVE_CSW_STATE state */ + msc_botxfer_param.bot_state = msc_botxfer_param.bot_state_bkp; + } + } else if (status == USBH_UNRECOVERED_ERROR) { + /* this means that there is a stall error limit, do reset recovery */ + msc_botxfer_param.bot_xfer_status = USBH_MSC_PHASE_ERROR; + } + break; + + case USBH_MSC_BOT_ERROR_OUT: + status = usbh_msc_bot_abort (pudev, puhost, USBH_MSC_DIR_OUT); + + if (status == USBH_OK) { + /* switch back to the original state */ + msc_botxfer_param.bot_state = msc_botxfer_param.bot_state_bkp; + } else if (status == USBH_UNRECOVERED_ERROR) { + /* this means that there is a stall error limit, do reset recovery */ + msc_botxfer_param.bot_xfer_status = USBH_MSC_PHASE_ERROR; + } + break; + + default: + break; + } + } +} + +/*! + \brief manages the different error handling for stall + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[in] direction: data IN or OUT + \param[out] none + \retval none +*/ +usbh_status usbh_msc_bot_abort (usb_core_driver *pudev, usbh_host *puhost, uint8_t direction) +{ + usbh_status status = USBH_BUSY; + + switch (direction) { + case USBH_MSC_DIR_IN : + /* send clrfeture command on bulk IN endpoint */ + status = usbh_clrfeature(pudev, + puhost, + msc_machine.msc_bulk_epin, + msc_machine.hc_num_in); + break; + + case USBH_MSC_DIR_OUT : + /*send clrfeature command on bulk OUT endpoint */ + status = usbh_clrfeature(pudev, + puhost, + msc_machine.msc_bulk_epout, + msc_machine.hc_num_out); + break; + + default: + break; + } + + bot_stall_error_count++; /* check continous number of times, stall has occured */ + + if (bot_stall_error_count > MAX_BULK_STALL_COUNT_LIMIT) { + status = USBH_UNRECOVERED_ERROR; + } + + return status; +} + +/*! + \brief decode the CSW received by the device and updates the same to upper layer + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval on success USBH_MSC_OK, on failure USBH_MSC_FAIL + \notes + Refer to USB Mass-Storage Class: BOT (www.usb.org) + 6.3.1 Valid CSW Conditions : + The host shall consider the CSW valid when: + 1. dCSWSignature is equal to 53425355h + 2. the CSW is 13 (Dh) bytes in length, + 3. dCSWTag matches the dCBWTag from the corresponding CBW. +*/ +uint8_t usbh_msc_csw_decode (usb_core_driver *pudev, usbh_host *puhost) +{ + uint8_t status; + uint32_t data_xfercount = 0; + + status = USBH_MSC_FAIL; + + if (pudev->host.connect_status) { + /* checking if the transfer length is diffrent than 13 */ + data_xfercount = usbh_xfercount_get (pudev, msc_machine.hc_num_in); + + if (data_xfercount != BBB_CSW_LENGTH) { + /* (4) Hi > Dn (Host expects to receive data from the device, + Device intends to transfer no data) + (5) Hi > Di (Host expects to receive data from the device, + Device intends to send data to the host) + (9) Ho > Dn (Host expects to send data to the device, + Device intends to transfer no data) + (11) Ho > Do (Host expects to send data to the device, + Device intends to receive data from the host) + */ + + status = USBH_MSC_PHASE_ERROR; + } else { + /* CSW length is correct */ + + /* check validity of the CSW Signature and CSWStatus */ + if (msc_csw_data.field.dCSWSignature == BBB_CSW_SIGNATURE) { + /* check condition 1. dCSWSignature is equal to 53425355h */ + if (msc_csw_data.field.dCSWTag == msc_cbw_data.field.dCBWTag) { + /* check condition 3. dCSWTag matches the dCBWTag from the corresponding CBW */ + if (msc_csw_data.field.bCSWStatus == USBH_MSC_OK) { + /* refer to USB Mass-Storage Class : BOT (www.usb.org) + Hn Host expects no data transfers + Hi Host expects to receive data from the device + Ho Host expects to send data to the device + + Dn Device intends to transfer no data + Di Device intends to send data to the host + Do Device intends to receive data from the host + + Section 6.7 + (1) Hn = Dn (Host expects no data transfers, + Device intends to transfer no data) + (6) Hi = Di (Host expects to receive data from the device, + Device intends to send data to the host) + (12) Ho = Do (Host expects to send data to the device, + Device intends to receive data from the host) + */ + + status = USBH_MSC_OK; + } else if (msc_csw_data.field.bCSWStatus == USBH_MSC_FAIL) { + status = USBH_MSC_FAIL; + } else if(msc_csw_data.field.bCSWStatus == USBH_MSC_PHASE_ERROR) { + /* refer to USB Mass-Storage Class : BOT (www.usb.org) + Section 6.7 + (2) Hn < Di ( Host expects no data transfers, + Device intends to send data to the host) + (3) Hn < Do ( Host expects no data transfers, + Device intends to receive data from the host) + (7) Hi < Di ( Host expects to receive data from the device, + Device intends to send data to the host) + (8) Hi <> Do ( Host expects to receive data from the device, + Device intends to receive data from the host) + (10) Ho <> Di (Host expects to send data to the device, + Di Device intends to send data to the host) + (13) Ho < Do (Host expects to send data to the device, + Device intends to receive data from the host) + */ + + status = USBH_MSC_PHASE_ERROR; + } + } /* CSW tag matching is checked */ + } /* CSW signature correct checking */else { + /* If the CSW signature is not valid, we sall return the phase error to + upper layers for reset recovery */ + status = USBH_MSC_PHASE_ERROR; + } + } /* CSW length check */ + } + + msc_botxfer_param.bot_xfer_status = status; + + return status; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/usbh_msc_core.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/usbh_msc_core.c new file mode 100644 index 0000000..3f6b0c7 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/usbh_msc_core.c @@ -0,0 +1,367 @@ +/*! + \file usbh_msc_core.c + \brief USB MSC(mass storage device) class driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_pipe.h" +#include "usbh_transc.h" +#include "usbh_msc_core.h" +#include "usbh_msc_scsi.h" +#include "usbh_msc_bbb.h" + +#define USBH_MSC_ERROR_RETRY_LIMIT 10 + +uint8_t msc_error_count = 0; + +usbh_msc_machine msc_machine; + +static void usbh_msc_itf_deinit (usb_core_driver *pudev, void *puhost); +static usbh_status usbh_msc_itf_init (usb_core_driver *pudev, void *puhost); +static usbh_status usbh_msc_handle (usb_core_driver *pudev, void *puhost); +static usbh_status usbh_msc_req (usb_core_driver *pudev, void *puhost); +static usbh_status usbh_msc_maxlun_get (usb_core_driver *pudev, usbh_host *puhost); + +usbh_class_cb usbh_msc_cb = +{ + usbh_msc_itf_init, + usbh_msc_itf_deinit, + usbh_msc_req, + usbh_msc_handle, +}; + +void usbh_msc_error_handle (uint8_t status); + +/*! + \brief interface initialization for MSC class + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_msc_itf_init (usb_core_driver *pudev, void *puhost) +{ + usbh_host *pphost = puhost; + + usb_desc_itf *itf_desc = &pphost->dev_prop.itf_desc[0]; + + if ((itf_desc->bInterfaceClass == MSC_CLASS) && + (itf_desc->bInterfaceProtocol == MSC_PROTOCOL)) { + + usb_desc_ep *ep_desc = &pphost->dev_prop.ep_desc[0][0]; + + if (ep_desc->bEndpointAddress & 0x80) { + msc_machine.msc_bulk_epin = ep_desc->bEndpointAddress; + msc_machine.msc_bulk_epinsize = ep_desc->wMaxPacketSize; + } else { + msc_machine.msc_bulk_epout = ep_desc->bEndpointAddress; + msc_machine.msc_bulk_epoutsize = ep_desc->wMaxPacketSize; + } + + ep_desc = &pphost->dev_prop.ep_desc[0][1]; + + if (ep_desc->bEndpointAddress & 0x80) { + msc_machine.msc_bulk_epin = ep_desc->bEndpointAddress; + msc_machine.msc_bulk_epinsize = ep_desc->wMaxPacketSize; + } else { + msc_machine.msc_bulk_epout = ep_desc->bEndpointAddress; + msc_machine.msc_bulk_epoutsize = ep_desc->wMaxPacketSize; + } + + msc_machine.hc_num_out = usbh_pipe_allocate(pudev, msc_machine.msc_bulk_epout); + + msc_machine.hc_num_in = usbh_pipe_allocate(pudev, msc_machine.msc_bulk_epin); + + + /* open the new channels */ + usbh_pipe_create (pudev, + &pphost->dev_prop, + msc_machine.hc_num_out, + USB_EPTYPE_BULK, + msc_machine.msc_bulk_epoutsize); + + usbh_pipe_create (pudev, + &pphost->dev_prop, + msc_machine.hc_num_in, + USB_EPTYPE_BULK, + msc_machine.msc_bulk_epinsize); + + } else { + pphost->usr_cb->dev_not_supported(); + } + + return USBH_OK; +} + +/*! + \brief de-initialize interface by freeing host channels allocated to interface + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +void usbh_msc_itf_deinit (usb_core_driver *pudev, void *puhost) +{ + if (msc_machine.hc_num_out) { + usb_pipe_halt (pudev, msc_machine.hc_num_out); + usbh_pipe_free (pudev, msc_machine.hc_num_out); + + msc_machine.hc_num_out = 0; + } + + if (msc_machine.hc_num_in) { + usb_pipe_halt (pudev, msc_machine.hc_num_in); + usbh_pipe_free (pudev, msc_machine.hc_num_in); + + msc_machine.hc_num_in = 0; + } +} + +/*! + \brief initialize the MSC state machine + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_msc_req (usb_core_driver *pudev, void *puhost) +{ + usbh_status status = USBH_OK; + msc_botxfer_param.msc_state = USBH_MSC_BOT_INIT_STATE; + + return status; +} + +/*! + \brief MSC state machine handler + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_msc_handle (usb_core_driver *pudev, void *puhost) +{ + usbh_host *pphost = puhost; + usbh_status status = USBH_BUSY; + uint8_t msc_status = USBH_MSC_BUSY; + uint8_t app_status = 0; + + static uint8_t max_lun_exceed = FALSE; + + if (pudev->host.connect_status) { + switch (msc_botxfer_param.msc_state) { + case USBH_MSC_BOT_INIT_STATE: + usbh_msc_init(pudev); + msc_botxfer_param.msc_state = USBH_MSC_BOT_RESET; + break; + + case USBH_MSC_BOT_RESET: + status = USBH_OK; + + msc_botxfer_param.msc_state = USBH_MSC_GET_MAX_LUN; + break; + + case USBH_MSC_GET_MAX_LUN: + /* issue Get_MaxLun request */ + status = usbh_msc_maxlun_get (pudev, puhost); + + if (status == USBH_OK) { + msc_machine.max_lun = *(msc_machine.buf); + + /* if device has more that one logical unit then it is not supported */ + if ((msc_machine.max_lun > 0) && (max_lun_exceed == FALSE)) { + max_lun_exceed = TRUE; + //pphost->usr_cb->dev_not_supported(); + + break; + } + + msc_botxfer_param.msc_state = USBH_MSC_TEST_UNIT_READY; + } + + if (status == USBH_NOT_SUPPORTED) { + /* if the command has failed, then we need to move to next state, after + STALL condition is cleared by Control-Transfer */ + msc_botxfer_param.msc_state_bkp = USBH_MSC_TEST_UNIT_READY; + + /* a clear feature should be issued here */ + msc_botxfer_param.msc_state = USBH_MSC_CTRL_ERROR_STATE; + } + break; + + case USBH_MSC_CTRL_ERROR_STATE: + /* issue clearfeature request */ + status = usbh_clrfeature(pudev, + puhost, + 0x00, + pphost->control.pipe_out_num); + + if (status == USBH_OK) { + /* if GetMaxLun request not support, assume single LUN configuration */ + msc_machine.max_lun = 0; + + msc_botxfer_param.msc_state = msc_botxfer_param.msc_state_bkp; + } + break; + + case USBH_MSC_TEST_UNIT_READY: + /* issue SCSI command TestUnitReady */ + msc_status = usbh_msc_test_unitready(pudev); + + if (msc_status == USBH_MSC_OK) { + msc_botxfer_param.msc_state = USBH_MSC_READ_CAPACITY10; + msc_error_count = 0; + status = USBH_OK; + } else { + usbh_msc_error_handle (msc_status); + } + break; + + case USBH_MSC_READ_CAPACITY10: + /* issue READ_CAPACITY10 SCSI command */ + msc_status = usbh_msc_read_capacity10(pudev); + + if (msc_status == USBH_MSC_OK) { + msc_botxfer_param.msc_state = USBH_MSC_MODE_SENSE6; + msc_error_count = 0; + status = USBH_OK; + } else { + usbh_msc_error_handle (msc_status); + } + break; + + case USBH_MSC_MODE_SENSE6: + /* issue ModeSense6 SCSI command for detecting if device is write-protected */ + msc_status = usbh_msc_mode_sense6 (pudev); + + if (msc_status == USBH_MSC_OK) { + msc_botxfer_param.msc_state = USBH_MSC_DEFAULT_APPLI_STATE; + msc_error_count = 0; + status = USBH_OK; + } else { + usbh_msc_error_handle (msc_status); + } + break; + + case USBH_MSC_REQUEST_SENSE: + /* issue RequestSense SCSI command for retreiving error code */ + msc_status = usbh_msc_request_sense (pudev); + if (msc_status == USBH_MSC_OK) { + msc_botxfer_param.msc_state = msc_botxfer_param.msc_state_bkp; + status = USBH_OK; + } else { + usbh_msc_error_handle (msc_status); + } + break; + + case USBH_MSC_BOT_USB_TRANSFERS: + /* process the BOT state machine */ + usbh_msc_botxfer(pudev , puhost); + break; + + case USBH_MSC_DEFAULT_APPLI_STATE: + /* process application callback for MSC */ + app_status = pphost->usr_cb->dev_user_app(); + + if (app_status == 0) { + msc_botxfer_param.msc_state = USBH_MSC_DEFAULT_APPLI_STATE; + } else if (app_status == 1) { + /* de-init requested from application layer */ + status = USBH_APPLY_DEINIT; + } + break; + + case USBH_MSC_UNRECOVERED_STATE: + status = USBH_UNRECOVERED_ERROR; + break; + + default: + break; + } + } + + return status; +} + +/*! + \brief get max lun of the mass storage device + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_msc_maxlun_get (usb_core_driver *pudev, usbh_host *puhost) +{ + usbh_status status = USBH_BUSY; + + if (puhost->control.ctl_state == CTL_IDLE) { + puhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_REQTYPE_CLASS | USB_RECPTYPE_ITF, + .bRequest = BBB_GET_MAX_LUN, + .wValue = 0, + .wIndex = 0, + .wLength = 1 + }; + + usbh_ctlstate_config (puhost, msc_machine.buf, 1); + } + + status = usbh_ctl_handler (pudev, puhost); + + return status; +} + +/*! + \brief handling errors occuring during the MSC state machine + \param[in] status: error status + \param[out] none + \retval operation status +*/ +void usbh_msc_error_handle (uint8_t status) +{ + if (status == USBH_MSC_FAIL) { + msc_error_count++; + + if (msc_error_count < USBH_MSC_ERROR_RETRY_LIMIT) { + /* try msc level error recovery, issue the request sense to get drive error reason */ + msc_botxfer_param.msc_state = USBH_MSC_REQUEST_SENSE; + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + } else { + /* error trials exceeded the limit, go to unrecovered state */ + msc_botxfer_param.msc_state = USBH_MSC_UNRECOVERED_STATE; + } + } else if (status == USBH_MSC_PHASE_ERROR) { + /* phase error, go to unrecoovered state */ + msc_botxfer_param.msc_state = USBH_MSC_UNRECOVERED_STATE; + } else if (status == USBH_MSC_BUSY) { + /* no change in state */ + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/usbh_msc_fatfs.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/usbh_msc_fatfs.c new file mode 100644 index 0000000..c6f7ee0 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/usbh_msc_fatfs.c @@ -0,0 +1,222 @@ +/*! + \file usbh_msc_fatfs.c + \brief USB MSC host FATFS related functions + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usb_conf.h" +#include "diskio.h" +#include "usbh_msc_core.h" + +static volatile DSTATUS state = STA_NOINIT; /* disk status */ + +extern usb_core_driver usbh_msc_core; +extern usbh_host usb_host; + +/*! + \brief initialize the disk drive + \param[in] drv: physical drive number (0) + \param[out] none + \retval operation status +*/ +DSTATUS disk_initialize (BYTE drv) +{ + if (usbh_msc_core.host.connect_status) { + state &= ~STA_NOINIT; + } + + return state; +} + +/*! + \brief get disk status + \param[in] drv: physical drive number (0) + \param[out] none + \retval operation status +*/ +DSTATUS disk_status (BYTE drv) +{ + if (drv) { + return STA_NOINIT; /* supports only single drive */ + } + + return state; +} + +/*! + \brief read sectors + \param[in] drv: physical drive number (0) + \param[in] buff: pointer to the data buffer to store read data + \param[in] sector: start sector number (LBA) + \param[in] count: sector count (1..255) + \param[out] none + \retval operation status +*/ +DRESULT disk_read (BYTE drv, + BYTE *buff, + DWORD sector, + BYTE count) +{ + BYTE status = USBH_MSC_OK; + + if (drv || !count) { + return RES_PARERR; + } + + if (state & STA_NOINIT) { + return RES_NOTRDY; + } + + if (usbh_msc_core.host.connect_status) { + do { + status = usbh_msc_read10 (&usbh_msc_core, buff,sector, 512 * count); + usbh_msc_botxfer(&usbh_msc_core, &usb_host); + + if (!usbh_msc_core.host.connect_status) { + return RES_ERROR; + } + } while(status == USBH_MSC_BUSY); + } + + if (status == USBH_MSC_OK) { + return RES_OK; + } + + return RES_ERROR; +} + +#if _READONLY == 0 + +/*! + \brief write sectors + \param[in] drv: physical drive number (0) + \param[in] buff: pointer to the data buffer to store read data + \param[in] sector: start sector number (LBA) + \param[in] count: sector count (1..255) + \param[out] none + \retval operation status +*/ +DRESULT disk_write (BYTE drv, + const BYTE *buff, + DWORD sector, + BYTE count) +{ + BYTE status = USBH_MSC_OK; + + if (drv || !count) { + return RES_PARERR; + } + + if (state & STA_NOINIT) { + return RES_NOTRDY; + } + + if (state & STA_PROTECT) { + return RES_WRPRT; + } + + if (usbh_msc_core.host.connect_status) { + do { + status = usbh_msc_write10 (&usbh_msc_core, (BYTE*)buff,sector, 512 * count); + usbh_msc_botxfer(&usbh_msc_core, &usb_host); + + if (!usbh_msc_core.host.connect_status) { + return RES_ERROR; + } + } while(status == USBH_MSC_BUSY); + } + + if (status == USBH_MSC_OK) { + return RES_OK; + } + + return RES_ERROR; +} + +#endif /* _READONLY == 0 */ + +/*-----------------------------------------------------------------------*/ +/* Miscellaneous Functions */ +/*-----------------------------------------------------------------------*/ + +#if _USE_IOCTL != 0 + +/*! + \brief I/O control function + \param[in] drv: physical drive number (0) + \param[in] ctrl: control code + \param[in] buff: pointer to the data buffer to store read data + \param[out] none + \retval operation status +*/ +DRESULT disk_ioctl (BYTE drv, + BYTE ctrl, + void *buff) +{ + DRESULT res = RES_OK; + + if (drv) { + return RES_PARERR; + } + + res = RES_ERROR; + + if (state & STA_NOINIT) { + return RES_NOTRDY; + } + + switch (ctrl) { + case CTRL_SYNC: /* make sure that no pending write process */ + res = RES_OK; + break; + + case GET_SECTOR_COUNT: /* get number of sectors on the disk (dword) */ + *(DWORD*)buff = (DWORD) usbh_msc_param.msc_capacity; + res = RES_OK; + break; + + case GET_SECTOR_SIZE: /* get r/w sector size (word) */ + *(WORD*)buff = 512; + res = RES_OK; + break; + + case GET_BLOCK_SIZE: /* get erase block size in unit of sector (dword) */ + *(DWORD*)buff = 512; + break; + + default: + res = RES_PARERR; + break; + } + + return res; +} +#endif /* _USE_IOCTL != 0 */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/usbh_msc_scsi.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/usbh_msc_scsi.c new file mode 100644 index 0000000..1bd9b48 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/usbh_msc_scsi.c @@ -0,0 +1,488 @@ +/*! + \file usbh_msc_scsi.c + \brief USB MSC SCSI commands implemention + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_msc_core.h" +#include "usbh_msc_scsi.h" +#include "usbh_msc_bbb.h" + +usbh_msc_parameter usbh_msc_param; + +uint8_t usbh_databuf_in[512]; +uint8_t usbh_databuf_out[512]; + +/*! + \brief send 'Test unit ready' command to the device + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +uint8_t usbh_msc_test_unitready (usb_core_driver *pudev) +{ + uint8_t index; + usbh_msc_status status = USBH_MSC_BUSY; + + if (pudev->host.connect_status) { + switch (msc_botxfer_param.cmd_state_machine) { + case CMD_SEND_STATE: + /* prepare the CBW and relevent field */ + msc_cbw_data.field.dCBWDataTransferLength = 0; /* no data transfer */ + msc_cbw_data.field.bmCBWFlags = USB_TRX_OUT; + msc_cbw_data.field.bCBWCBLength = CBW_LENGTH_TEST_UNIT_READY; + + msc_botxfer_param.xfer_buf = msc_csw_data.CSWArray; + msc_botxfer_param.data_len = USBH_MSC_CSW_MAX_LENGTH; + msc_botxfer_param.msc_state_current = USBH_MSC_TEST_UNIT_READY; + + for (index = CBW_CB_LENGTH; index != 0; index--) { + msc_cbw_data.field.CBWCB[index] = 0x00; + } + + msc_cbw_data.field.CBWCB[0] = SCSI_TEST_UNIT_READY; + msc_botxfer_param.bot_state = USBH_MSC_SEND_CBW; + + /* start the transfer, then let the state machine magage the other transactions */ + msc_botxfer_param.msc_state = USBH_MSC_BOT_USB_TRANSFERS; + msc_botxfer_param.bot_xfer_status = USBH_MSC_BUSY; + msc_botxfer_param.cmd_state_machine = CMD_WAIT_STATUS; + + status = USBH_MSC_BUSY; + break; + + case CMD_WAIT_STATUS: + if (msc_botxfer_param.bot_xfer_status == USBH_MSC_OK) { + /* commands successfully sent and response received */ + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + status = USBH_MSC_OK; + } else if ( msc_botxfer_param.bot_xfer_status == USBH_MSC_FAIL) { + /* failure mode */ + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + status = USBH_MSC_FAIL; + } else if (msc_botxfer_param.bot_xfer_status == USBH_MSC_PHASE_ERROR) { + /* failure mode */ + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + status = USBH_MSC_PHASE_ERROR; + } + break; + + default: + break; + } + } + + return status; +} + +/*! + \brief send the read capacity command to the device + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +uint8_t usbh_msc_read_capacity10 (usb_core_driver *pudev) +{ + uint8_t index; + usbh_msc_status status = USBH_MSC_BUSY; + + if (pudev->host.connect_status) { + switch (msc_botxfer_param.cmd_state_machine) { + case CMD_SEND_STATE: + /* prepare the CBW and relevent field */ + msc_cbw_data.field.dCBWDataTransferLength = READ_CAPACITY10_DATA_LEN; + msc_cbw_data.field.bmCBWFlags = USB_TRX_IN; + msc_cbw_data.field.bCBWCBLength = CBW_LENGTH; + + msc_botxfer_param.xfer_buf = usbh_databuf_in; + msc_botxfer_param.msc_state_current = USBH_MSC_READ_CAPACITY10; + + for (index = CBW_CB_LENGTH; index != 0; index--) { + msc_cbw_data.field.CBWCB[index] = 0x00; + } + + msc_cbw_data.field.CBWCB[0] = SCSI_READ_CAPACITY10; + msc_botxfer_param.bot_state = USBH_MSC_SEND_CBW; + + /* start the transfer, then let the state machine manage the other transactions */ + msc_botxfer_param.msc_state = USBH_MSC_BOT_USB_TRANSFERS; + msc_botxfer_param.bot_xfer_status = USBH_MSC_BUSY; + msc_botxfer_param.cmd_state_machine = CMD_WAIT_STATUS; + + status = USBH_MSC_BUSY; + break; + + case CMD_WAIT_STATUS: + if (msc_botxfer_param.bot_xfer_status == USBH_MSC_OK) { + /* assign the capacity */ + (((uint8_t*)&usbh_msc_param.msc_capacity )[3]) = usbh_databuf_in[0]; + (((uint8_t*)&usbh_msc_param.msc_capacity )[2]) = usbh_databuf_in[1]; + (((uint8_t*)&usbh_msc_param.msc_capacity )[1]) = usbh_databuf_in[2]; + (((uint8_t*)&usbh_msc_param.msc_capacity )[0]) = usbh_databuf_in[3]; + + /* assign the page length */ + (((uint8_t*)&usbh_msc_param.msc_page_len )[1]) = usbh_databuf_in[6]; + (((uint8_t*)&usbh_msc_param.msc_page_len )[0]) = usbh_databuf_in[7]; + + /* commands successfully sent and response received */ + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + status = USBH_MSC_OK; + } else if (msc_botxfer_param.bot_xfer_status == USBH_MSC_FAIL) { + /* failure mode */ + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + status = USBH_MSC_FAIL; + } else if (msc_botxfer_param.bot_xfer_status == USBH_MSC_PHASE_ERROR) { + /* Failure Mode */ + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + status = USBH_MSC_PHASE_ERROR; + } else { + /* wait for the commands to get completed */ + /* no change in state machine */ + } + break; + + default: + break; + } + } + + return status; +} + +/*! + \brief send the mode sense6 command to the device + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +uint8_t usbh_msc_mode_sense6 (usb_core_driver *pudev) +{ + uint8_t index; + usbh_msc_status status = USBH_MSC_BUSY; + + if (pudev->host.connect_status) { + switch (msc_botxfer_param.cmd_state_machine) { + case CMD_SEND_STATE: + /* prepare the CBW and relevent field */ + msc_cbw_data.field.dCBWDataTransferLength = XFER_LEN_MODE_SENSE6; + msc_cbw_data.field.bmCBWFlags = USB_TRX_IN; + msc_cbw_data.field.bCBWCBLength = CBW_LENGTH; + + msc_botxfer_param.xfer_buf = usbh_databuf_in; + msc_botxfer_param.msc_state_current = USBH_MSC_MODE_SENSE6; + + for (index = CBW_CB_LENGTH; index != 0; index--) { + msc_cbw_data.field.CBWCB[index] = 0x00; + } + + msc_cbw_data.field.CBWCB[0] = SCSI_MODE_SENSE6; + msc_cbw_data.field.CBWCB[2] = MODE_SENSE_PAGE_CONTROL_FIELD | MODE_SENSE_PAGE_CODE; + msc_cbw_data.field.CBWCB[4] = XFER_LEN_MODE_SENSE6; + msc_botxfer_param.bot_state = USBH_MSC_SEND_CBW; + + /* start the transfer, then let the state machine manage the other transactions */ + msc_botxfer_param.msc_state = USBH_MSC_BOT_USB_TRANSFERS; + msc_botxfer_param.bot_xfer_status = USBH_MSC_BUSY; + msc_botxfer_param.cmd_state_machine = CMD_WAIT_STATUS; + + status = USBH_MSC_BUSY; + break; + + case CMD_WAIT_STATUS: + if (msc_botxfer_param.bot_xfer_status == USBH_MSC_OK) { + /* assign the write protect status */ + /* if writeprotect = 0, writing is allowed + if writeprotect != 0, disk is write protected */ + if (usbh_databuf_in[2] & MASK_MODE_SENSE_WRITE_PROTECT) { + usbh_msc_param.msc_write_protect = DISK_WRITE_PROTECTED; + } else { + usbh_msc_param.msc_write_protect = 0; + } + + /* commands successfully sent and response received */ + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + status = USBH_MSC_OK; + } else if (msc_botxfer_param.bot_xfer_status == USBH_MSC_FAIL) { + /* failure mode */ + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + status = USBH_MSC_FAIL; + } else if (msc_botxfer_param.bot_xfer_status == USBH_MSC_PHASE_ERROR) { + /* failure mode */ + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + status = USBH_MSC_PHASE_ERROR; + } else { + /* wait for the commands to get completed */ + /* no change in state machine */ + } + break; + + default: + break; + } + } + + return status; +} + +/*! + \brief send the Request Sense command to the device + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +uint8_t usbh_msc_request_sense (usb_core_driver *pudev) +{ + usbh_msc_status status = USBH_MSC_BUSY; + uint8_t index; + + if (pudev->host.connect_status) { + switch (msc_botxfer_param.cmd_state_machine) { + case CMD_SEND_STATE: + /* prepare the cbw and relevent field */ + msc_cbw_data.field.dCBWDataTransferLength = ALLOCATION_LENGTH_REQUEST_SENSE; + msc_cbw_data.field.bmCBWFlags = USB_TRX_IN; + msc_cbw_data.field.bCBWCBLength = CBW_LENGTH; + + msc_botxfer_param.xfer_buf = usbh_databuf_in; + msc_botxfer_param.msc_state_bkp = msc_botxfer_param.msc_state_current; + msc_botxfer_param.msc_state_current = USBH_MSC_REQUEST_SENSE; + + for (index = CBW_CB_LENGTH; index != 0; index--) { + msc_cbw_data.field.CBWCB[index] = 0x00; + } + + msc_cbw_data.field.CBWCB[0] = SCSI_REQUEST_SENSE; + msc_cbw_data.field.CBWCB[1] = DESC_REQUEST_SENSE; + msc_cbw_data.field.CBWCB[4] = ALLOCATION_LENGTH_REQUEST_SENSE; + + msc_botxfer_param.bot_state = USBH_MSC_SEND_CBW; + + /* start the transfer, then let the state machine magage the other transactions */ + msc_botxfer_param.msc_state = USBH_MSC_BOT_USB_TRANSFERS; + msc_botxfer_param.bot_xfer_status = USBH_MSC_BUSY; + msc_botxfer_param.cmd_state_machine = CMD_WAIT_STATUS; + + status = USBH_MSC_BUSY; + break; + + case CMD_WAIT_STATUS: + if (msc_botxfer_param.bot_xfer_status == USBH_MSC_OK) { + /* get sense data */ + (((uint8_t*)&usbh_msc_param.msc_sense_key )[3]) = usbh_databuf_in[0]; + (((uint8_t*)&usbh_msc_param.msc_sense_key )[2]) = usbh_databuf_in[1]; + (((uint8_t*)&usbh_msc_param.msc_sense_key )[1]) = usbh_databuf_in[2]; + (((uint8_t*)&usbh_msc_param.msc_sense_key )[0]) = usbh_databuf_in[3]; + + /* commands successfully sent and response received */ + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + status = USBH_MSC_OK; + } else if (msc_botxfer_param.bot_xfer_status == USBH_MSC_FAIL) { + /* failure mode */ + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + status = USBH_MSC_FAIL; + } else if ( msc_botxfer_param.bot_xfer_status == USBH_MSC_PHASE_ERROR ) { + /* failure mode */ + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + status = USBH_MSC_PHASE_ERROR; + } else { + /* wait for the commands to get completed */ + /* no change in state machine */ + } + break; + + default: + break; + } + } + + return status; +} + +/*! + \brief send the write10 command to the device + \param[in] pudev: pointer to usb device + \param[in] data_buf: data buffer contains the data to write + \param[in] addr: address to which the data will be written + \param[in] byte_num: number of bytes to be written + \param[out] none + \retval operation status +*/ +uint8_t usbh_msc_write10 (usb_core_driver *pudev, uint8_t *data_buf, uint32_t addr, uint32_t byte_num) +{ + uint8_t index; + uint16_t nbOfPages; + usbh_msc_status status = USBH_MSC_BUSY; + + if (pudev->host.connect_status) { + switch (msc_botxfer_param.cmd_state_machine) { + case CMD_SEND_STATE: + msc_cbw_data.field.dCBWDataTransferLength = byte_num; + msc_cbw_data.field.bmCBWFlags = USB_TRX_OUT; + msc_cbw_data.field.bCBWCBLength = CBW_LENGTH; + msc_botxfer_param.xfer_buf = data_buf; + + for (index = CBW_CB_LENGTH; index != 0; index--) { + msc_cbw_data.field.CBWCB[index] = 0x00; + } + + msc_cbw_data.field.CBWCB[0] = SCSI_WRITE10; + + /* logical block address */ + msc_cbw_data.field.CBWCB[2] = (((uint8_t*)&addr)[3]); + msc_cbw_data.field.CBWCB[3] = (((uint8_t*)&addr)[2]); + msc_cbw_data.field.CBWCB[4] = (((uint8_t*)&addr)[1]); + msc_cbw_data.field.CBWCB[5] = (((uint8_t*)&addr)[0]); + + /* USBH_MSC_PAGE_LENGTH = 512*/ + nbOfPages = byte_num / USBH_MSC_PAGE_LENGTH; + + /* tranfer length */ + msc_cbw_data.field.CBWCB[7] = (((uint8_t *)&nbOfPages)[1]); + msc_cbw_data.field.CBWCB[8] = (((uint8_t *)&nbOfPages)[0]); + + msc_botxfer_param.bot_state = USBH_MSC_SEND_CBW; + + /* start the transfer, then let the state machine magage the other transactions */ + msc_botxfer_param.msc_state = USBH_MSC_BOT_USB_TRANSFERS; + msc_botxfer_param.bot_xfer_status = USBH_MSC_BUSY; + msc_botxfer_param.cmd_state_machine = CMD_WAIT_STATUS; + + status = USBH_MSC_BUSY; + break; + + case CMD_WAIT_STATUS: + if (msc_botxfer_param.bot_xfer_status == USBH_MSC_OK) { + /* commands successfully sent and response received */ + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + status = USBH_MSC_OK; + } else if (msc_botxfer_param.bot_xfer_status == USBH_MSC_FAIL) { + /* failure mode */ + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + } else if (msc_botxfer_param.bot_xfer_status == USBH_MSC_PHASE_ERROR) { + /* failure mode */ + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + status = USBH_MSC_PHASE_ERROR; + } + break; + + default: + break; + } + } + + return status; +} + +/*! + \brief send the read10 command to the device + \param[in] pudev: pointer to usb device + \param[in] data_buf: data buffer contains the data to write + \param[in] addr: address to which the data will be written + \param[in] byte_num: number of bytes to be written + \param[out] none + \retval operation status +*/ +uint8_t usbh_msc_read10 (usb_core_driver *pudev, uint8_t *data_buf, uint32_t addr, uint32_t byte_num) +{ + uint8_t index; + uint16_t nbOfPages; + + static usbh_msc_status status = USBH_MSC_BUSY; + + status = USBH_MSC_BUSY; + + if (pudev->host.connect_status) { + switch (msc_botxfer_param.cmd_state_machine) { + case CMD_SEND_STATE: + /* prepare the CBW and relevent field */ + msc_cbw_data.field.dCBWDataTransferLength = byte_num; + msc_cbw_data.field.bmCBWFlags = USB_TRX_IN; + msc_cbw_data.field.bCBWCBLength = CBW_LENGTH; + + msc_botxfer_param.xfer_buf = data_buf; + + for(index = CBW_CB_LENGTH; index != 0; index--) + { + msc_cbw_data.field.CBWCB[index] = 0x00; + } + + msc_cbw_data.field.CBWCB[0] = SCSI_READ10; + + /* logical block address */ + msc_cbw_data.field.CBWCB[2] = (((uint8_t*)&addr)[3]); + msc_cbw_data.field.CBWCB[3] = (((uint8_t*)&addr)[2]); + msc_cbw_data.field.CBWCB[4] = (((uint8_t*)&addr)[1]); + msc_cbw_data.field.CBWCB[5] = (((uint8_t*)&addr)[0]); + + /* USBH_MSC_PAGE_LENGTH = 512 */ + nbOfPages = byte_num / USBH_MSC_PAGE_LENGTH; + + /* tranfer length */ + msc_cbw_data.field.CBWCB[7] = (((uint8_t *)&nbOfPages)[1]); + msc_cbw_data.field.CBWCB[8] = (((uint8_t *)&nbOfPages)[0]); + + msc_botxfer_param.bot_state = USBH_MSC_SEND_CBW; + + /* start the transfer, then let the state machine magage the other transactions */ + msc_botxfer_param.msc_state = USBH_MSC_BOT_USB_TRANSFERS; + msc_botxfer_param.bot_xfer_status = USBH_MSC_BUSY; + msc_botxfer_param.cmd_state_machine = CMD_WAIT_STATUS; + + status = USBH_MSC_BUSY; + break; + + case CMD_WAIT_STATUS: + if ((msc_botxfer_param.bot_xfer_status == USBH_MSC_OK) && \ + (pudev->host.connect_status)) { + /* commands successfully sent and response received */ + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + status = USBH_MSC_OK; + } else if ((msc_botxfer_param.bot_xfer_status == USBH_MSC_FAIL) && \ + (pudev->host.connect_status)) { + /* failure mode */ + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + } else if (msc_botxfer_param.bot_xfer_status == USBH_MSC_PHASE_ERROR) { + /* failure mode */ + msc_botxfer_param.cmd_state_machine = CMD_SEND_STATE; + status = USBH_MSC_PHASE_ERROR; + } else { + /* wait for the commands to get completed */ + /* no change in state machine */ + } + break; + + default: + break; + } + } + + return status; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/usbh_usr.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/usbh_usr.c new file mode 100644 index 0000000..ebd5979 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/Source/usbh_usr.c @@ -0,0 +1,595 @@ +/*! + \file usbh_usr.c + \brief user application layer for USBFS host-mode MSC class operation + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include +#include "usbh_usr.h" +#include "drv_usb_hw.h" +#include "ff.h" +#include "usbh_msc_core.h" +#include "usbh_msc_scsi.h" +#include "usbh_msc_bbb.h" +#include "lcd_log.h" + +extern uint16_t LINE; +extern usb_core_driver usbh_msc_core; +extern char_format_struct charform; + +FATFS fatfs; +FIL file; + +uint8_t line_idx = 0; +uint8_t need_clear = 0; +uint8_t usbh_usr_application_state = USBH_USR_FS_INIT; +uint8_t WriteTextBuff[] = "GD32 Connectivity line Host Demo application using FAT_FS "; + +/* points to the DEVICE_PROP structure of current device */ +usbh_user_cb user_callback_funs = +{ + usbh_user_init, + usbh_user_deinit, + usbh_user_device_connected, + usbh_user_device_reset, + usbh_user_device_disconnected, + usbh_user_over_current_detected, + usbh_user_device_speed_detected, + usbh_user_device_desc_available, + usbh_user_device_address_assigned, + usbh_user_configuration_descavailable, + usbh_user_manufacturer_string, + usbh_user_product_string, + usbh_user_serialnum_string, + usbh_user_enumeration_finish, + usbh_user_userinput, + usbh_usr_msc_application, + usbh_user_device_not_supported, + usbh_user_unrecovered_error +}; + +const uint8_t MSG_HOST_INIT[] = "> Host Library Initialized."; +const uint8_t MSG_DEV_ATTACHED[] = "> Device Attached."; +const uint8_t MSG_DEV_DISCONNECTED[] = "> Device Disconnected."; +const uint8_t MSG_DEV_ENUMERATED[] = "> Enumeration completed."; +const uint8_t MSG_DEV_HIGHSPEED[] = "> High speed device detected."; +const uint8_t MSG_DEV_FULLSPEED[] = "> Full speed device detected."; +const uint8_t MSG_DEV_LOWSPEED[] = "> Low speed device detected."; +const uint8_t MSG_DEV_ERROR[] = "> Device fault."; + +const uint8_t MSG_HOST_HEADER[] = "> USBFS MSC Host"; +const uint8_t MSG_HOST_FOOTER[] = "> USB Host Library v2.0.0"; + +const uint8_t MSG_LIB_START[] = "##### USB Host library started #####"; +const uint8_t MSG_DEV_NOSUP[] = "> Device not supported."; +const uint8_t MSG_OVERCURRENT[] = "> Overcurrent detected."; +const uint8_t MSG_RESET_DEV[] = "> Reset the USB device."; + +const uint8_t MSG_MSC_CLASS[] = "> Mass storage device connected."; +const uint8_t MSG_HID_CLASS[] = "> HID device connected."; +const uint8_t MSG_DISK_SIZE[] = "> Size of the disk in MBytes: "; +const uint8_t MSG_LUN[] = "> LUN Available in the device:"; +const uint8_t MSG_ROOT_CONT[] = "> Exploring disk flash ..."; +const uint8_t MSG_WR_PROTECT[] = "> The disk is write protected."; +const uint8_t MSG_UNREC_ERROR[] = "> UNRECOVERED ERROR STATE."; +const uint8_t MSG_FILE_NOTINIT[] = "> Cannot initialize File System."; +const uint8_t MSG_FILE_INIT[] = "> File System initialized."; +const uint8_t MSG_Write_File[] = "> Writing File to disk flash ..."; +const uint8_t MSG_Write_Protect[] = "> Disk flash is write protected "; +const uint8_t MSG_NOT_WRITE[] = "> GD32.TXT CANNOT be writen."; +const uint8_t MSG_CREATE_FILE[] = "> GD32.TXT created in the disk."; + +static uint8_t explore_disk (char* path, uint8_t recu_level); +static void toggle_leds (void); + +/*! + \brief user operation for host-mode initialization + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_init(void) +{ + static uint8_t startup = 0U; + + if (0U == startup) { + startup = 1U; + + /* configure the LEDs and KEYs*/ + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + gd_eval_key_init(KEY_CET, KEY_MODE_GPIO); + gd_eval_key_init(KEY_B, KEY_MODE_GPIO); + gd_eval_key_init(KEY_C, KEY_MODE_GPIO); + + exmc_lcd_init(); + + usb_mdelay(50); + + lcd_init(); + + lcd_log_init(); + + lcd_log_header_set((uint8_t *)MSG_HOST_HEADER, 80); + + lcd_log_print((uint8_t *)MSG_LIB_START, sizeof(MSG_LIB_START) - 1, LCD_COLOR_WHITE); + + charform.char_color = LCD_COLOR_RED; + + lcd_log_footer_set((uint8_t *)MSG_HOST_FOOTER, 70); + } +} + +/*! + \brief user operation for device attached + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_device_connected(void) +{ + if (need_clear != 0) { + lcd_log_text_zone_clear(30, 0, 210, 320); + need_clear = 0; + } + + lcd_log_print((uint8_t *)MSG_DEV_ATTACHED, sizeof(MSG_DEV_ATTACHED) - 1, LCD_COLOR_WHITE); +} + +/*! + \brief user operation when unrecoveredError happens + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_unrecovered_error (void) +{ + lcd_log_print((uint8_t *)MSG_UNREC_ERROR, sizeof(MSG_UNREC_ERROR) - 1, LCD_COLOR_WHITE); +} + +/*! + \brief user operation for device disconnect event + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_device_disconnected (void) +{ + LINE = 190; + + lcd_log_text_zone_clear(30, 0, 210, 320); + + lcd_log_print((uint8_t *)MSG_DEV_DISCONNECTED, sizeof(MSG_DEV_DISCONNECTED) - 1, LCD_COLOR_WHITE); + + need_clear = 1; +} + +/*! + \brief user operation for reset USB Device + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_device_reset(void) +{ + lcd_log_print((uint8_t *)MSG_RESET_DEV, sizeof(MSG_RESET_DEV) - 1, LCD_COLOR_WHITE); +} + +/*! + \brief user operation for detectting device speed + \param[in] device_speed: device speed + \param[out] none + \retval none +*/ +void usbh_user_device_speed_detected(uint32_t device_speed) +{ + if (PORT_SPEED_HIGH == device_speed) { + lcd_log_print((uint8_t *)MSG_DEV_HIGHSPEED, sizeof(MSG_DEV_HIGHSPEED) - 1, LCD_COLOR_WHITE); + } else if(PORT_SPEED_FULL == device_speed) { + lcd_log_print((uint8_t *)MSG_DEV_FULLSPEED, sizeof(MSG_DEV_FULLSPEED) - 1, LCD_COLOR_WHITE); + } else if(PORT_SPEED_LOW == device_speed) { + lcd_log_print((uint8_t *)MSG_DEV_LOWSPEED, sizeof(MSG_DEV_LOWSPEED) - 1, LCD_COLOR_WHITE); + } else { + lcd_log_print((uint8_t *)MSG_DEV_ERROR, sizeof(MSG_DEV_ERROR) - 1, LCD_COLOR_WHITE); + } +} + +/*! + \brief user operation when device descriptor is available + \param[in] device_desc: device descriptor + \param[out] none + \retval none +*/ +void usbh_user_device_desc_available(void *device_desc) +{ + uint8_t TempStr[64], str_len = 0; + usb_desc_dev *pDevStr = device_desc; + + sprintf((char *)TempStr, "VID: %04Xh", (uint32_t)pDevStr->idVendor); + str_len = strlen((const char *)TempStr); + lcd_log_print((uint8_t *)TempStr, str_len, LCD_COLOR_WHITE); + + sprintf((char *)TempStr, "PID: %04Xh", (uint32_t)pDevStr->idProduct); + str_len = strlen((const char *)TempStr); + lcd_log_print((uint8_t *)TempStr, str_len, LCD_COLOR_WHITE); +} + +/*! + \brief usb device is successfully assigned the Address + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_device_address_assigned(void) +{ +} + +/*! + \brief user operation when configuration descriptor is available + \param[in] cfg_desc: pointer to configuration descriptor + \param[in] itf_desc: pointer to interface descriptor + \param[in] ep_desc: pointer to endpoint descriptor + \param[out] none + \retval none +*/ +void usbh_user_configuration_descavailable(usb_desc_config *cfg_desc, + usb_desc_itf *itf_desc, + usb_desc_ep *ep_desc) +{ + usb_desc_itf *id = itf_desc; + + if (0x08U == (*id).bInterfaceClass) { + lcd_log_print((uint8_t *)MSG_MSC_CLASS, sizeof(MSG_MSC_CLASS) - 1, LCD_COLOR_WHITE); + } else if (0x03U == (*id).bInterfaceClass) { + lcd_log_print((uint8_t *)MSG_HID_CLASS, sizeof(MSG_HID_CLASS) - 1, LCD_COLOR_WHITE); + } +} + +/*! + \brief user operation when manufacturer string exists + \param[in] manufacturer_string: manufacturer string of usb device + \param[out] none + \retval none +*/ +void usbh_user_manufacturer_string(void *manufacturer_string) +{ + uint8_t TempStr[64], str_len = 0; + + sprintf((char *)TempStr, "Manufacturer: %s", (char *)manufacturer_string); + str_len = strlen((const char *)TempStr); + lcd_log_print((uint8_t *)TempStr, str_len, LCD_COLOR_WHITE); +} + +/*! + \brief user operation when product string exists + \param[in] product_string: product string of usb device + \param[out] none + \retval none +*/ +void usbh_user_product_string(void *product_string) +{ + uint8_t TempStr[64], str_len = 0; + + sprintf((char *)TempStr, "Product: %s", (char *)product_string); + str_len = strlen((const char *)TempStr); + lcd_log_print((uint8_t *)TempStr, str_len, LCD_COLOR_WHITE); +} + +/*! + \brief user operatin when serialNum string exists + \param[in] serial_num_string: serialNum string of usb device + \param[out] none + \retval none +*/ +void usbh_user_serialnum_string(void *serial_num_string) +{ + uint8_t TempStr[64], str_len = 0; + + sprintf((char *)TempStr, "Serial Number: %s", (char *)serial_num_string); + str_len = strlen((const char *)TempStr); + lcd_log_print((uint8_t *)TempStr, str_len, LCD_COLOR_WHITE); +} + +/*! + \brief user response request is displayed to ask for application jump to class + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_enumeration_finish(void) +{ + uint8_t Str1[] = "To see the disk information: "; + uint8_t Str2[] = "Press CET Key..."; + + lcd_log_print((uint8_t *)MSG_DEV_ENUMERATED, sizeof(MSG_DEV_ENUMERATED) - 1, LCD_COLOR_WHITE); + lcd_log_print((uint8_t *)Str1, sizeof(Str1) - 1, LCD_COLOR_GREEN); + lcd_log_print((uint8_t *)Str2, sizeof(Str2) - 1, LCD_COLOR_GREEN); +} + +/*! + \brief user operation when device is not supported + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_device_not_supported(void) +{ + lcd_log_print((uint8_t *)MSG_DEV_NOSUP, sizeof(MSG_DEV_NOSUP) - 1, LCD_COLOR_WHITE); +} + +/*! + \brief user action for application state entry + \param[in] none + \param[out] none + \retval user response for user key +*/ +usbh_user_status usbh_user_userinput(void) +{ + usbh_user_status usbh_usr_status = USBH_USER_NO_RESP; + + /*key B3 is in polling mode to detect user action */ + if (RESET == gd_eval_key_state_get(KEY_CET)) { + LINE = 190; + + lcd_log_text_zone_clear(30, 0, 210, 320); + + usbh_usr_status = USBH_USER_RESP_OK; + } + + return usbh_usr_status; +} + +/*! + \brief user operation for device overcurrent detection event + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_over_current_detected (void) +{ + lcd_log_print((uint8_t *)MSG_OVERCURRENT, sizeof(MSG_OVERCURRENT) - 1, LCD_COLOR_WHITE); +} + +/*! + \brief demo application for mass storage + \param[in] pudev: pointer to device + \param[in] id: no use here + \param[out] none + \retval status +*/ +int usbh_usr_msc_application(void) +{ + FRESULT res; + uint16_t bytesWritten, bytesToWrite; + + uint8_t Str1[] = "> To see the root content of the disk "; + uint8_t Str2[] = "> Press C Key to write file"; + uint8_t Str3[] = "> The MSC host demo is end."; + uint8_t Str4[] = "> Press CET key..."; + uint8_t TempStr[64], str_len = 0; + + switch(usbh_usr_application_state) + { + case USBH_USR_FS_INIT: + /* initialises the file system*/ + if (FR_OK != f_mount(0, &fatfs)) { + lcd_log_print((uint8_t *)MSG_FILE_NOTINIT, sizeof(MSG_FILE_NOTINIT) - 1, LCD_COLOR_WHITE); + + return(-1); + } + + lcd_log_print((uint8_t *)MSG_FILE_INIT, sizeof(MSG_FILE_INIT) - 1, LCD_COLOR_WHITE); + + sprintf((char *)TempStr, "> Disk capacity: %ud Bytes.", \ + usbh_msc_param.msc_capacity * usbh_msc_param.msc_page_len); + + str_len = strlen((const char *)TempStr); + + lcd_log_print((uint8_t *)TempStr, str_len, LCD_COLOR_WHITE); + + if (DISK_WRITE_PROTECTED == usbh_msc_param.msc_write_protect) { + lcd_log_print((uint8_t *)MSG_WR_PROTECT, sizeof(MSG_WR_PROTECT) - 1, LCD_COLOR_WHITE); + } + + usbh_usr_application_state = USBH_USR_FS_READLIST; + break; + + case USBH_USR_FS_READLIST: + lcd_log_print((uint8_t *)MSG_ROOT_CONT, sizeof(MSG_ROOT_CONT) - 1, LCD_COLOR_WHITE); + lcd_log_print((uint8_t *)Str1, sizeof(Str1) - 1, LCD_COLOR_GREEN); + lcd_log_print((uint8_t *)Str4, sizeof(Str4) - 1, LCD_COLOR_GREEN); + + /*Key B3 in polling*/ + while ((usbh_msc_core.host.connect_status) && \ + (SET == gd_eval_key_state_get (KEY_CET))) { + toggle_leds(); + } + + LINE = 190; + + lcd_log_text_zone_clear(30, 0, 210, 320); + + explore_disk("0:/", 1); + line_idx = 0; + usbh_usr_application_state = USBH_USR_FS_WRITEFILE; + break; + + case USBH_USR_FS_WRITEFILE: + usb_mdelay(100U); + + lcd_log_print((uint8_t *)Str2, sizeof(Str2) - 1, LCD_COLOR_GREEN); + + /*key b3 in polling*/ + while ((usbh_msc_core.host.connect_status) && \ + (SET == gd_eval_key_state_get (KEY_C))) { + toggle_leds(); + } + + lcd_log_print((uint8_t *)MSG_Write_File, sizeof(MSG_Write_File) - 1, LCD_COLOR_WHITE); + + if (DISK_WRITE_PROTECTED == usbh_msc_param.msc_write_protect) { + lcd_log_print((uint8_t *)MSG_Write_Protect, sizeof(MSG_Write_Protect) - 1, LCD_COLOR_WHITE); + + usbh_usr_application_state = USBH_USR_FS_DEMOEND; + break; + } + + /* register work area for logical drives */ + f_mount(0, &fatfs); + + if (FR_OK == f_open(&file, "0:GD32.TXT", FA_CREATE_ALWAYS | FA_WRITE)) { + /* write buffer to file */ + bytesToWrite = sizeof(WriteTextBuff); + res = f_write (&file, WriteTextBuff, bytesToWrite, (void *)&bytesWritten); + /* EOF or error */ + if ((0U == bytesWritten) || (FR_OK != res)) { + lcd_log_print((uint8_t *)MSG_NOT_WRITE, sizeof(MSG_NOT_WRITE) - 1, LCD_COLOR_WHITE); + } else { + lcd_log_print((uint8_t *)MSG_CREATE_FILE, sizeof(MSG_CREATE_FILE) - 1, LCD_COLOR_WHITE); + } + + /* close file and filesystem */ + f_close(&file); + f_mount(0, NULL); + } else { + lcd_log_print((uint8_t *)MSG_CREATE_FILE, sizeof(MSG_CREATE_FILE) - 1, LCD_COLOR_WHITE); + } + + usbh_usr_application_state = USBH_USR_FS_DEMOEND; + lcd_log_print((uint8_t *)Str3, sizeof(Str3) - 1, LCD_COLOR_GREEN); + break; + + case USBH_USR_FS_DEMOEND: + break; + + default: + break; + } + + return(0); +} + +/*! + \brief displays disk content + \param[in] path: pointer to root path + \param[in] recu_level: recursive level + \param[out] none + \retval status +*/ +static uint8_t explore_disk (char* path, uint8_t recu_level) +{ + FRESULT res; + FILINFO fno; + DIR dir; + char *fn; + + uint8_t Str2[] = "Press B Key to continue"; + + res = f_opendir(&dir, path); + + if (res == FR_OK) { + while (usbh_msc_core.host.connect_status) { + res = f_readdir(&dir, &fno); + if (FR_OK != res || 0U == fno.fname[0]) { + break; + } + + if ('.' == fno.fname[0]) { + continue; + } + + fn = fno.fname; + + line_idx++; + + if (line_idx > 4) { + line_idx = 0; + + lcd_log_print((uint8_t *)Str2, sizeof(Str2) - 1, LCD_COLOR_GREEN); + + /*key B3 in polling*/ + while ((usbh_msc_core.host.connect_status) && \ + (SET == gd_eval_key_state_get (KEY_B))) { + toggle_leds(); + } + } + + if (1U == recu_level) { + uint8_t temp[] = " |__"; + lcd_log_print((uint8_t *)temp, strlen((const char *)temp), LCD_COLOR_WHITE); + } else if(2U == recu_level) { + uint8_t temp[] = " | |__"; + lcd_log_print((uint8_t *)temp, strlen((const char *)temp), LCD_COLOR_WHITE); + } + + if (AM_DIR == (fno.fattrib & AM_MASK)) { + lcd_log_print((uint8_t *)fno.fname, strlen(fno.fname), LCD_COLOR_RED); + } else { + lcd_log_print((uint8_t *)fno.fname, strlen(fno.fname), LCD_COLOR_WHITE); + } + + if ((AM_DIR == (fno.fattrib & AM_MASK)) && (1U == recu_level)) { + explore_disk(fn, 2); + } + } + } + + return res; +} + +/*! + \brief toggle leds to shows user input state + \param[in] none + \param[out] none + \retval none +*/ +static void toggle_leds(void) +{ + static uint32_t i; + + if (0x10000U == i++) { + gd_eval_led_toggle(LED2); + gd_eval_led_toggle(LED3); + gd_eval_led_toggle(LED4); + i = 0; + } +} + +/*! + \brief deinit user state and associated variables + \param[in] none + \param[out] none + \retval none +*/ +void usbh_user_deinit(void) +{ + usbh_usr_application_state = USBH_USR_FS_INIT; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/readme.txt new file mode 100644 index 0000000..7f37292 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/USBFS/USB_Host/MSC_Host/readme.txt @@ -0,0 +1,43 @@ +/*! + \file readme.txt + \brief Description of the USB host mode to control MSC device + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, and it provides a description of how +to use the USBFS host peripheral on the GD32VF103V devices. + + Insert the OTG cable to the USB_FS port. Then download it to the EVAL board and run. + + If an Udisk has been attached, the user will see the information of Udisk enumeration. +First pressing the CET key will see the Udisk information, next pressing the CET key +will see the root content of the Udisk, then press the C key will write file to the +Udisk, finally the user will see information that the msc host demo is end. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/WWDGT/WWDGT_delay_feed/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/WWDGT/WWDGT_delay_feed/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/WWDGT/WWDGT_delay_feed/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/WWDGT/WWDGT_delay_feed/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/WWDGT/WWDGT_delay_feed/main.c new file mode 100644 index 0000000..9f3306e --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/WWDGT/WWDGT_delay_feed/main.c @@ -0,0 +1,90 @@ +/*! + \file main.c + \brief WWDGT delay feed demo + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" +#include "gd32vf103v_eval.h" + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + /* configure systick */ + //systick_config(); + + /* configure LED2 and LED3 */ + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + + /* turn off LED2 and LED3 */ + gd_eval_led_off(LED2); + gd_eval_led_off(LED3); + + /* delay */ + delay_1ms(150); + + /* check if the system has resumed from WWDGT reset */ + if(RESET != rcu_flag_get(RCU_FLAG_WWDGTRST)){ + /* WWDGTRST flag set */ + gd_eval_led_on(LED2); + /* clear the WWDGTRST flag */ + rcu_all_reset_flag_clear(); + while(1){ + } + } + /* enable WWDGT clock */ + rcu_periph_clock_enable(RCU_WWDGT); + + /* + * set WWDGT clock = (PCLK1 (54MHz)/4096)/8 = 1648Hz (~606.8 us) + * set counter value to 127 + * set window value to 80 + * refresh window is: ~606.8 * (127-80)= 28.5ms < refresh window < ~606.8 * (127-63) =38.8ms. + */ + wwdgt_config(127, 80, WWDGT_CFG_PSC_DIV8); + wwdgt_enable(); + + while(1){ + /* toggle LED3 */ + gd_eval_led_toggle(LED3); + /* insert 30 ms delay */ + delay_1ms(30); + /* update WWDGT counter */ + wwdgt_counter_update(127); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/WWDGT/WWDGT_delay_feed/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/WWDGT/WWDGT_delay_feed/readme.txt new file mode 100644 index 0000000..d21c287 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/WWDGT/WWDGT_delay_feed/readme.txt @@ -0,0 +1,47 @@ +/*! + \file readme.txt + \brief description of the WWDGT_delay_feed example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This demo is based on the GD32VF103V-EVAL-V1.0 board, it shows the WWDGT with different +counter value and window value make the different WWDGT timeout. As a result, LED1 +and LED2 display a different phenomenon. + + In this demo, the WWDGT counter value is set to 127, the refresh window is set to +80. In this case the WWDGT timeout is set to 38.8ms(the timeout may varies due to +APB1 frequency dispersion), the value in the delay function is set to 30ms, the WWDGT +counter can reloaded normally, the LED2 is turn off, LED3 is blinking fast. + + If the value in the delay function is not set properly, the WWDGT counter is not +reloaded. As a result, the system reset and only the LED2 is remain illuminated. + + In this example the system clock is set to 108 MHz , and the APB1 is set to 54MHz. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/WWDGT/WWDGT_delay_feed/systick.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/WWDGT/WWDGT_delay_feed/systick.c new file mode 100644 index 0000000..4296e59 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/WWDGT/WWDGT_delay_feed/systick.c @@ -0,0 +1,57 @@ +/*! + \file systick.c + \brief the systick configuration file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" + +/*! + \brief delay a time in milliseconds + \param[in] count: count in milliseconds + \param[out] none + \retval none +*/ +void delay_1ms(uint32_t count) +{ + uint64_t start_mtime, delta_mtime; + + // Don't start measuruing until we see an mtime tick + uint64_t tmp = get_timer_value(); + do { + start_mtime = get_timer_value(); + } while (start_mtime == tmp); + + do { + delta_mtime = get_timer_value() - start_mtime; + }while(delta_mtime <(SystemCoreClock/4000.0 *count )); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/WWDGT/WWDGT_delay_feed/systick.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/WWDGT/WWDGT_delay_feed/systick.h new file mode 100644 index 0000000..9a74c22 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Examples/WWDGT/WWDGT_delay_feed/systick.h @@ -0,0 +1,42 @@ +/*! + \file systick.h + \brief the header file of systick + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef SYS_TICK_H +#define SYS_TICK_H + +#include + +void delay_1ms(uint32_t count); + +#endif /* SYS_TICK_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h new file mode 100644 index 0000000..f06da0a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h @@ -0,0 +1,396 @@ +/*! + \file gd32vf103_adc.h + \brief definitions for the ADC + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_ADC_H +#define GD32VF103_ADC_H + +#include "gd32vf103.h" + +/* ADC definitions */ +#define ADC0 ADC_BASE +#define ADC1 (ADC_BASE + 0x400U) + +/* registers definitions */ +#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ +#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ +#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ +#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ +#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ +#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ +#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ +#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ +#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ +#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ +#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ +#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */ +#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */ +#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */ +#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ +#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ +#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ +#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ +#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ +#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */ +#define ADC_OVSCR(adcx) REG32((adcx) + 0x80U) /*!< ADC oversample control register */ + +/* bits definitions */ +/* ADC_STAT */ +#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ +#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ +#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ +#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ +#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ + +/* ADC_CTL0 */ +#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ +#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ +#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ +#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ +#define ADC_CTL0_SM BIT(8) /*!< scan mode */ +#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ +#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ +#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ +#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ +#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ +#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ +#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ +#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ + +/* ADC_CTL1 */ +#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ +#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ +#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ +#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ +#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ +#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ +#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ +#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ +#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ +#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ +#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ +#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ +#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ + +/* ADC_SAMPTx x=0..1 */ +#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n sample time selection */ + +/* ADC_IOFFx x=0..3 */ +#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ + +/* ADC_WDHT */ +#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ + +/* ADC_WDLT */ +#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ + +/* ADC_RSQx x=0..2 */ +#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion in regular sequence */ +#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ + +/* ADC_ISQ */ +#define ADC_ISQ_ISQN BITS(0,4) /*!< nth conversion in inserted sequence */ +#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ + +/* ADC_IDATAx x=0..3*/ +#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data n */ + +/* ADC_RDATA */ +#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ +#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ + +/* ADC_OVSCR */ +#define ADC_OVSCR_OVSEN BIT(0) /*!< oversampling enable */ +#define ADC_OVSCR_OVSR BITS(2,4) /*!< oversampling ratio */ +#define ADC_OVSCR_OVSS BITS(5,8) /*!< oversampling shift */ +#define ADC_OVSCR_TOVS BIT(9) /*!< triggered oversampling */ +#define ADC_OVSCR_DRES BITS(12,13) /*!< ADC data resolution */ + +/* constants definitions */ +/* adc_stat register value */ +#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ +#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ +#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ +#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ +#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ + +/* adc_ctl0 register value */ +#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ + +/* scan mode */ +#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ + +/* inserted channel group convert automatically */ +#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ + +/* ADC sync mode */ +#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ +#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ +#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ +#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ +#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */ +#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */ +#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */ +#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */ +#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */ +#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */ +#define ADC_DAUL_INSERTED_TRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */ + +/* adc_ctl1 register value */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ +#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ + +/* continuous mode */ +#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ + +/* external trigger select for regular channel */ +#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ +/* for ADC0 and ADC1 regular channel */ +#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */ +#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< TIMER3 CH3 event select */ +#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ +#define ADC0_1_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ + +/* external trigger mode for inserted channel */ +#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ +/* for ADC0 and ADC1 inserted channel */ +#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ +#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ +#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */ +#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */ +#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */ +#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< TIMER3 TRGO event select */ +#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ +#define ADC0_1_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ + +/* adc_samptx register value */ +#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ +#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ +#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ +#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ +#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ +#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ +#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ +#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ +#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ + +/* adc_ioffx register value */ +#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ + +/* adc_wdht register value */ +#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ + +/* adc_wdlt register value */ +#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ + +/* adc_rsqx register value */ +#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ + +/* adc_isq register value */ +#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ + +/* ADC channel group definitions */ +#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ +#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ +#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ + +#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ + +/* ADC inserted channel definitions */ +#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ +#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ +#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ +#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ + +/* ADC channel definitions */ +#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ +#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ +#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ +#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ +#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ +#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ +#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ +#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ +#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ +#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ +#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ +#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ +#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ +#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ +#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ +#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ +#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ +#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ + +/* ADC interrupt */ +#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ +#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ +#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ + +/* ADC interrupt flag */ +#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ +#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ +#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ + +/* ADC resolution definitions */ +#define OVSCR_DRES(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) +#define ADC_RESOLUTION_12B OVSCR_DRES(0) /*!< 12-bit ADC resolution */ +#define ADC_RESOLUTION_10B OVSCR_DRES(1) /*!< 10-bit ADC resolution */ +#define ADC_RESOLUTION_8B OVSCR_DRES(2) /*!< 8-bit ADC resolution */ +#define ADC_RESOLUTION_6B OVSCR_DRES(3) /*!< 6-bit ADC resolution */ + +/* ADC oversampling mode */ +#define ADC_OVERSAMPLING_ALL_CONVERT 0 /*!< all oversampled conversions for a channel are done consecutively after a trigger */ +#define ADC_OVERSAMPLING_ONE_CONVERT 1 /*!< each oversampled conversion for a channel needs a trigger */ + +/* ADC oversampling shift */ +#define OVSCR_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) +#define ADC_OVERSAMPLING_SHIFT_NONE OVSCR_OVSS(0) /*!< no oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_1B OVSCR_OVSS(1) /*!< 1-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_2B OVSCR_OVSS(2) /*!< 2-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_3B OVSCR_OVSS(3) /*!< 3-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_4B OVSCR_OVSS(4) /*!< 4-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_5B OVSCR_OVSS(5) /*!< 5-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_6B OVSCR_OVSS(6) /*!< 6-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_7B OVSCR_OVSS(7) /*!< 7-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_8B OVSCR_OVSS(8) /*!< 8-bit oversampling shift */ + +/* ADC oversampling ratio */ +#define OVSCR_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) +#define ADC_OVERSAMPLING_RATIO_MUL2 OVSCR_OVSR(0) /*!< oversampling ratio X2 */ +#define ADC_OVERSAMPLING_RATIO_MUL4 OVSCR_OVSR(1) /*!< oversampling ratio X4 */ +#define ADC_OVERSAMPLING_RATIO_MUL8 OVSCR_OVSR(2) /*!< oversampling ratio X8 */ +#define ADC_OVERSAMPLING_RATIO_MUL16 OVSCR_OVSR(3) /*!< oversampling ratio X16 */ +#define ADC_OVERSAMPLING_RATIO_MUL32 OVSCR_OVSR(4) /*!< oversampling ratio X32 */ +#define ADC_OVERSAMPLING_RATIO_MUL64 OVSCR_OVSR(5) /*!< oversampling ratio X64 */ +#define ADC_OVERSAMPLING_RATIO_MUL128 OVSCR_OVSR(6) /*!< oversampling ratio X128 */ +#define ADC_OVERSAMPLING_RATIO_MUL256 OVSCR_OVSR(7) /*!< oversampling ratio X256 */ + +/* function declarations */ +/* initialization config */ +/* reset ADC */ +void adc_deinit(uint32_t adc_periph); +/* configure the ADC sync mode */ +void adc_mode_config(uint32_t mode); +/* enable or disable ADC special function */ +void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue); +/* configure ADC data alignment */ +void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment); +/* enable ADC interface */ +void adc_enable(uint32_t adc_periph); +/* disable ADC interface */ +void adc_disable(uint32_t adc_periph); +/* ADC calibration and reset calibration */ +void adc_calibration_enable(uint32_t adc_periph); +/* enable the temperature sensor and Vrefint channel */ +void adc_tempsensor_vrefint_enable(void); +/* disable the temperature sensor and Vrefint channel */ +void adc_tempsensor_vrefint_disable(void); + +/* DMA config */ +/* enable DMA request */ +void adc_dma_mode_enable(uint32_t adc_periph); +/* disable DMA request */ +void adc_dma_mode_disable(uint32_t adc_periph); + +/* regular group and inserted group config */ +/* configure ADC discontinuous mode */ +void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length); + +/* configure the length of regular channel group or inserted channel group */ +void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length); +/* configure ADC regular channel */ +void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); +/* configure ADC inserted channel */ +void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); +/* configure ADC inserted channel offset */ +void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset); + +/* configure ADC external trigger source */ +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source); +/* configure ADC external trigger */ +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue); +/* enable ADC software trigger */ +void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group); + +/* get channel data */ +/* read ADC regular group data register */ +uint16_t adc_regular_data_read(uint32_t adc_periph); +/* read ADC inserted group data register */ +uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel); +/* read the last ADC0 and ADC1 conversion result data in sync mode */ +uint32_t adc_sync_mode_convert_value_read(void); + +/* watchdog config */ +/* configure ADC analog watchdog single channel */ +void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel); +/* configure ADC analog watchdog group channel */ +void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group); +/* disable ADC analog watchdog */ +void adc_watchdog_disable(uint32_t adc_periph); +/* configure ADC analog watchdog threshold */ +void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold); + +/* interrupt & flag functions */ +/* get the ADC flag bits */ +FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag); +/* clear the ADC flag bits */ +void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag); +/* get the bit state of ADCx software start conversion */ +FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph); +/* get the bit state of ADCx software inserted channel start conversion */ +FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph); +/* get the ADC interrupt bits */ +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt); +/* clear the ADC flag */ +void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt); +/* enable ADC interrupt */ +void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt); +/* disable ADC interrupt */ +void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt); + +/* ADC resolution & oversample */ +/* ADC resolution config */ +void adc_resolution_config(uint32_t adc_periph, uint32_t resolution); +/* ADC oversample mode config */ +void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio); +/* enable ADC oversample mode */ +void adc_oversample_mode_enable(uint32_t adc_periph); +/* disable ADC oversample mode */ +void adc_oversample_mode_disable(uint32_t adc_periph); + +#endif /* GD32VF103_ADC_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h new file mode 100644 index 0000000..733d701 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h @@ -0,0 +1,227 @@ +/*! + \file gd32vf103_bkp.h + \brief definitions for the BKP + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_BKP_H +#define GD32VF103_BKP_H + +#include "gd32vf103.h" + +/* BKP definitions */ +#define BKP BKP_BASE /*!< BKP base address */ + +/* registers definitions */ +#define BKP_DATA0 REG16((BKP) + 0x04U) /*!< BKP data register 0 */ +#define BKP_DATA1 REG16((BKP) + 0x08U) /*!< BKP data register 1 */ +#define BKP_DATA2 REG16((BKP) + 0x0CU) /*!< BKP data register 2 */ +#define BKP_DATA3 REG16((BKP) + 0x10U) /*!< BKP data register 3 */ +#define BKP_DATA4 REG16((BKP) + 0x14U) /*!< BKP data register 4 */ +#define BKP_DATA5 REG16((BKP) + 0x18U) /*!< BKP data register 5 */ +#define BKP_DATA6 REG16((BKP) + 0x1CU) /*!< BKP data register 6 */ +#define BKP_DATA7 REG16((BKP) + 0x20U) /*!< BKP data register 7 */ +#define BKP_DATA8 REG16((BKP) + 0x24U) /*!< BKP data register 8 */ +#define BKP_DATA9 REG16((BKP) + 0x28U) /*!< BKP data register 9 */ +#define BKP_DATA10 REG16((BKP) + 0x40U) /*!< BKP data register 10 */ +#define BKP_DATA11 REG16((BKP) + 0x44U) /*!< BKP data register 11 */ +#define BKP_DATA12 REG16((BKP) + 0x48U) /*!< BKP data register 12 */ +#define BKP_DATA13 REG16((BKP) + 0x4CU) /*!< BKP data register 13 */ +#define BKP_DATA14 REG16((BKP) + 0x50U) /*!< BKP data register 14 */ +#define BKP_DATA15 REG16((BKP) + 0x54U) /*!< BKP data register 15 */ +#define BKP_DATA16 REG16((BKP) + 0x58U) /*!< BKP data register 16 */ +#define BKP_DATA17 REG16((BKP) + 0x5CU) /*!< BKP data register 17 */ +#define BKP_DATA18 REG16((BKP) + 0x60U) /*!< BKP data register 18 */ +#define BKP_DATA19 REG16((BKP) + 0x64U) /*!< BKP data register 19 */ +#define BKP_DATA20 REG16((BKP) + 0x68U) /*!< BKP data register 20 */ +#define BKP_DATA21 REG16((BKP) + 0x6CU) /*!< BKP data register 21 */ +#define BKP_DATA22 REG16((BKP) + 0x70U) /*!< BKP data register 22 */ +#define BKP_DATA23 REG16((BKP) + 0x74U) /*!< BKP data register 23 */ +#define BKP_DATA24 REG16((BKP) + 0x78U) /*!< BKP data register 24 */ +#define BKP_DATA25 REG16((BKP) + 0x7CU) /*!< BKP data register 25 */ +#define BKP_DATA26 REG16((BKP) + 0x80U) /*!< BKP data register 26 */ +#define BKP_DATA27 REG16((BKP) + 0x84U) /*!< BKP data register 27 */ +#define BKP_DATA28 REG16((BKP) + 0x88U) /*!< BKP data register 28 */ +#define BKP_DATA29 REG16((BKP) + 0x8CU) /*!< BKP data register 29 */ +#define BKP_DATA30 REG16((BKP) + 0x90U) /*!< BKP data register 30 */ +#define BKP_DATA31 REG16((BKP) + 0x94U) /*!< BKP data register 31 */ +#define BKP_DATA32 REG16((BKP) + 0x98U) /*!< BKP data register 32 */ +#define BKP_DATA33 REG16((BKP) + 0x9CU) /*!< BKP data register 33 */ +#define BKP_DATA34 REG16((BKP) + 0xA0U) /*!< BKP data register 34 */ +#define BKP_DATA35 REG16((BKP) + 0xA4U) /*!< BKP data register 35 */ +#define BKP_DATA36 REG16((BKP) + 0xA8U) /*!< BKP data register 36 */ +#define BKP_DATA37 REG16((BKP) + 0xACU) /*!< BKP data register 37 */ +#define BKP_DATA38 REG16((BKP) + 0xB0U) /*!< BKP data register 38 */ +#define BKP_DATA39 REG16((BKP) + 0xB4U) /*!< BKP data register 39 */ +#define BKP_DATA40 REG16((BKP) + 0xB8U) /*!< BKP data register 40 */ +#define BKP_DATA41 REG16((BKP) + 0xBCU) /*!< BKP data register 41 */ +#define BKP_OCTL REG16((BKP) + 0x2CU) /*!< RTC signal output control register */ +#define BKP_TPCTL REG16((BKP) + 0x30U) /*!< tamper pin control register */ +#define BKP_TPCS REG16((BKP) + 0x34U) /*!< tamper control and status register */ + +/* bits definitions */ +/* BKP_DATA */ +#define BKP_DATA BITS(0,15) /*!< backup data */ + +/* BKP_OCTL */ +#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ +#define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ +#define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ +#define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ + +/* BKP_TPCTL */ +#define BKP_TPCTL_TPEN BIT(0) /*!< tamper detection enable */ +#define BKP_TPCTL_TPAL BIT(1) /*!< tamper pin active level */ + +/* BKP_TPCS */ +#define BKP_TPCS_TER BIT(0) /*!< tamper event reset */ +#define BKP_TPCS_TIR BIT(1) /*!< tamper interrupt reset */ +#define BKP_TPCS_TPIE BIT(2) /*!< tamper interrupt enable */ +#define BKP_TPCS_TEF BIT(8) /*!< tamper event flag */ +#define BKP_TPCS_TIF BIT(9) /*!< tamper interrupt flag */ + +/* constants definitions */ +/* BKP data register number */ +typedef enum +{ + BKP_DATA_0 = 1, /*!< BKP data register 0 */ + BKP_DATA_1, /*!< BKP data register 1 */ + BKP_DATA_2, /*!< BKP data register 2 */ + BKP_DATA_3, /*!< BKP data register 3 */ + BKP_DATA_4, /*!< BKP data register 4 */ + BKP_DATA_5, /*!< BKP data register 5 */ + BKP_DATA_6, /*!< BKP data register 6 */ + BKP_DATA_7, /*!< BKP data register 7 */ + BKP_DATA_8, /*!< BKP data register 8 */ + BKP_DATA_9, /*!< BKP data register 9 */ + BKP_DATA_10, /*!< BKP data register 10 */ + BKP_DATA_11, /*!< BKP data register 11 */ + BKP_DATA_12, /*!< BKP data register 12 */ + BKP_DATA_13, /*!< BKP data register 13 */ + BKP_DATA_14, /*!< BKP data register 14 */ + BKP_DATA_15, /*!< BKP data register 15 */ + BKP_DATA_16, /*!< BKP data register 16 */ + BKP_DATA_17, /*!< BKP data register 17 */ + BKP_DATA_18, /*!< BKP data register 18 */ + BKP_DATA_19, /*!< BKP data register 19 */ + BKP_DATA_20, /*!< BKP data register 20 */ + BKP_DATA_21, /*!< BKP data register 21 */ + BKP_DATA_22, /*!< BKP data register 22 */ + BKP_DATA_23, /*!< BKP data register 23 */ + BKP_DATA_24, /*!< BKP data register 24 */ + BKP_DATA_25, /*!< BKP data register 25 */ + BKP_DATA_26, /*!< BKP data register 26 */ + BKP_DATA_27, /*!< BKP data register 27 */ + BKP_DATA_28, /*!< BKP data register 28 */ + BKP_DATA_29, /*!< BKP data register 29 */ + BKP_DATA_30, /*!< BKP data register 30 */ + BKP_DATA_31, /*!< BKP data register 31 */ + BKP_DATA_32, /*!< BKP data register 32 */ + BKP_DATA_33, /*!< BKP data register 33 */ + BKP_DATA_34, /*!< BKP data register 34 */ + BKP_DATA_35, /*!< BKP data register 35 */ + BKP_DATA_36, /*!< BKP data register 36 */ + BKP_DATA_37, /*!< BKP data register 37 */ + BKP_DATA_38, /*!< BKP data register 38 */ + BKP_DATA_39, /*!< BKP data register 39 */ + BKP_DATA_40, /*!< BKP data register 40 */ + BKP_DATA_41, /*!< BKP data register 41 */ +}bkp_data_register_enum; + +/* BKP register */ +#define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U) +#define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U) + +/* get data of BKP data register */ +#define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) + +/* RTC clock calibration value */ +#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) + +/* RTC output selection */ +#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ +#define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U) /*!< RTC second pulse is selected as the RTC output */ + +/* tamper pin active level */ +#define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U) /*!< the tamper pin is active high */ +#define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U) /*!< the tamper pin is active low */ + +/* tamper flag */ +#define BKP_FLAG_TAMPER BKP_TPCS_TEF /*!< tamper event flag */ + +/* tamper interrupt flag */ +#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */ + +/* function declarations */ +/* reset BKP registers */ +void bkp_deinit(void); +/* write BKP data register */ +void bkp_data_write(bkp_data_register_enum register_number, uint16_t data); +/* read BKP data register */ +uint16_t bkp_data_read(bkp_data_register_enum register_number); + +/* RTC related functions */ +/* enable RTC clock calibration output */ +void bkp_rtc_calibration_output_enable(void); +/* disable RTC clock calibration output */ +void bkp_rtc_calibration_output_disable(void); +/* enable RTC alarm or second signal output */ +void bkp_rtc_signal_output_enable(void); +/* disable RTC alarm or second signal output */ +void bkp_rtc_signal_output_disable(void); +/* select RTC output */ +void bkp_rtc_output_select(uint16_t outputsel); +/* set RTC clock calibration value */ +void bkp_rtc_calibration_value_set(uint8_t value); + +/* tamper pin related functions */ +/* enable tamper pin detection */ +void bkp_tamper_detection_enable(void); +/* disable tamper pin detection */ +void bkp_tamper_detection_disable(void); +/* set tamper pin active level */ +void bkp_tamper_active_level_set(uint16_t level); + +/* interrupt & flag functions */ +/* enable tamper interrupt */ +void bkp_interrupt_enable(void); +/* disable tamper interrupt */ +void bkp_interrupt_disable(void); +/* get tamper flag state */ +FlagStatus bkp_flag_get(void); +/* clear tamper flag state */ +void bkp_flag_clear(void); +/* get tamper interrupt flag state */ +FlagStatus bkp_interrupt_flag_get(void); +/* clear tamper interrupt flag state */ +void bkp_interrupt_flag_clear(void); + +#endif /* GD32VF103_BKP_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h new file mode 100644 index 0000000..c23674d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h @@ -0,0 +1,717 @@ +/*! + \file gd32vf103_can.h + \brief definitions for the CAN + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_CAN_H +#define GD32VF103_CAN_H + +#include "gd32vf103.h" + +/* CAN definitions */ +#define CAN0 CAN_BASE /*!< CAN0 base address */ +#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ + +/* registers definitions */ +#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ +#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ +#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/ +#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */ +#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */ +#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */ +#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */ +#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */ +#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */ +#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */ +#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */ +#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */ +#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */ +#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */ +#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */ +#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */ +#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */ +#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */ +#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */ +#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */ +#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ +#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ +#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ +#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */ +#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ +#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ +#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ +#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */ +#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */ +#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */ +#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */ +#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */ +#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */ +#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */ +#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */ +#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */ +#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */ +#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */ +#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */ +#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */ +#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */ +#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */ +#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */ +#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */ +#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */ +#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */ +#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */ +#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */ +#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */ +#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */ +#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */ +#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */ +#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */ +#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */ +#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */ +#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */ +#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */ +#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */ +#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */ +#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */ +#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */ +#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */ +#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */ +#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */ +#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */ +#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */ +#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */ +#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */ +#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */ +#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */ +#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */ +#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */ +#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */ +#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */ +#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */ +#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */ +#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */ +#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */ +#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */ +#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */ +#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */ +#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */ +#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */ +#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */ +#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */ +#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */ +#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */ +#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */ +#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ + +/* CAN transmit mailbox bank */ +#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ +#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ +#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ +#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ + +/* CAN filter bank */ +#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ +#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ + +/* CAN receive fifo mailbox bank */ +#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ +#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ +#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ +#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ + +/* bits definitions */ +/* CAN_CTL */ +#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */ +#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */ +#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */ +#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */ +#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */ +#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */ +#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */ +#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */ +#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */ +#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */ + +/* CAN_STAT */ +#define CAN_STAT_IWS BIT(0) /*!< initial working state */ +#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */ +#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/ +#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */ +#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */ +#define CAN_STAT_TS BIT(8) /*!< transmitting state */ +#define CAN_STAT_RS BIT(9) /*!< receiving state */ +#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */ +#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */ + +/* CAN_TSTAT */ +#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */ +#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */ +#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */ +#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */ +#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */ +#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */ +#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */ +#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */ +#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */ +#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */ +#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */ +#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */ +#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ +#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ +#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ +#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ +#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ +#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ +#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ +#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */ +#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */ +#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ + +/* CAN_RFIFO0 */ +#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ +#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ +#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ +#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ + +/* CAN_RFIFO1 */ +#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ +#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ +#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ +#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ + +/* CAN_INTEN */ +#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */ +#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */ +#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */ +#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */ +#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */ +#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */ +#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */ +#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */ +#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */ +#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ +#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ +#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ +#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ +#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ + +/* CAN_ERR */ +#define CAN_ERR_WERR BIT(0) /*!< warning error */ +#define CAN_ERR_PERR BIT(1) /*!< passive error */ +#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ +#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ +#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ +#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ + +/* CAN_BT */ +#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ +#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ +#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ +#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ +#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ +#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ + +/* CAN_TMIx */ +#define CAN_TMI_TEN BIT(0) /*!< transmit enable */ +#define CAN_TMI_FT BIT(1) /*!< frame type */ +#define CAN_TMI_FF BIT(2) /*!< frame format */ +#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ +#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ + +/* CAN_TMPx */ +#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ +#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ +#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ + +/* CAN_TMDATA0x */ +#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ +#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ +#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ +#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ + +/* CAN_TMDATA1x */ +#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ +#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ +#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ +#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ + +/* CAN_RFIFOMIx */ +#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ +#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ +#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ +#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ + +/* CAN_RFIFOMPx */ +#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ +#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ +#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ + +/* CAN_RFIFOMDATA0x */ +#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ +#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ +#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ +#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ + +/* CAN_RFIFOMDATA1x */ +#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ +#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ +#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ +#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ + +/* CAN_FCTL */ +#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ +#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ + +/* CAN_FMCFG */ +#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ + +/* CAN_FSCFG */ +#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/ + +/* CAN_FAFIFO */ +#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ + +/* CAN_FW */ +#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ + +/* CAN_FxDATAy */ +#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */ + +/* consts definitions */ +/* define the CAN bit position and its register index offset */ +#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) +#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) +#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) +#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) +#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) + +/* register offset */ +#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ +#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */ +#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */ +#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */ +#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ + +/* CAN flags */ +typedef enum { + /* flags in TSTAT register */ + CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ + CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ + CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ + CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ + CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ + CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ + /* flags in RFIFO0 register */ + CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ + CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ + /* flags in RFIFO1 register */ + CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ + CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ + /* flags in ERR register */ + CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ + CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ + CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ +} can_flag_enum; + +/* CAN interrupt flags */ +typedef enum { + /* interrupt flags in STAT register */ + CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ + CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ + CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ + /* interrupt flags in TSTAT register */ + CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ + CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ + CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ +} can_interrupt_flag_enum; + +/* CAN initiliaze parameters struct */ +typedef struct { + uint8_t working_mode; /*!< CAN working mode */ + uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ + uint8_t time_segment_1; /*!< time segment 1 */ + uint8_t time_segment_2; /*!< time segment 2 */ + ControlStatus time_triggered; /*!< time triggered communication mode */ + ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ + ControlStatus auto_wake_up; /*!< automatic wake-up mode */ + ControlStatus no_auto_retrans; /*!< automatic retransmission mode disable */ + ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ + ControlStatus trans_fifo_order; /*!< transmit FIFO order */ + uint16_t prescaler; /*!< baudrate prescaler */ +} can_parameter_struct; + +/* CAN transmit message struct */ +typedef struct { + uint32_t tx_sfid; /*!< standard format frame identifier */ + uint32_t tx_efid; /*!< extended format frame identifier */ + uint8_t tx_ff; /*!< format of frame, standard or extended format */ + uint8_t tx_ft; /*!< type of frame, data or remote */ + uint8_t tx_dlen; /*!< data length */ + uint8_t tx_data[8]; /*!< transmit data */ +} can_trasnmit_message_struct; + +/* CAN receive message struct */ +typedef struct { + uint32_t rx_sfid; /*!< standard format frame identifier */ + uint32_t rx_efid; /*!< extended format frame identifier */ + uint8_t rx_ff; /*!< format of frame, standard or extended format */ + uint8_t rx_ft; /*!< type of frame, data or remote */ + uint8_t rx_dlen; /*!< data length */ + uint8_t rx_data[8]; /*!< receive data */ + uint8_t rx_fi; /*!< filtering index */ +} can_receive_message_struct; + +/* CAN filter parameters struct */ +typedef struct { + uint16_t filter_list_high; /*!< filter list number high bits*/ + uint16_t filter_list_low; /*!< filter list number low bits */ + uint16_t filter_mask_high; /*!< filter mask number high bits */ + uint16_t filter_mask_low; /*!< filter mask number low bits */ + uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */ + uint16_t filter_number; /*!< filter number */ + uint16_t filter_mode; /*!< filter mode, list or mask */ + uint16_t filter_bits; /*!< filter scale */ + ControlStatus filter_enable; /*!< filter work or not */ +} can_filter_parameter_struct; + +/* CAN errors */ +typedef enum { + CAN_ERROR_NONE = 0, /*!< no error */ + CAN_ERROR_FILL, /*!< fill error */ + CAN_ERROR_FORMATE, /*!< format error */ + CAN_ERROR_ACK, /*!< ACK error */ + CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ + CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ + CAN_ERROR_CRC, /*!< CRC error */ + CAN_ERROR_SOFTWARECFG, /*!< software configure */ +} can_error_enum; + +/* transmit states */ +typedef enum { + CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */ + CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */ + CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */ + CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */ +} can_transmit_state_enum; + +typedef enum { + CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ + CAN_FILTER_STRUCT, /* CAN filter parameters struct */ + CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ + CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ +} can_struct_type_enum; + +/* CAN baudrate prescaler*/ +#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) + +/* CAN bit segment 1*/ +#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) + +/* CAN bit segment 2*/ +#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) + +/* CAN resynchronization jump width*/ +#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) + +/* CAN communication mode*/ +#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) + +/* CAN FDATA high 16 bits */ +#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) + +/* CAN FDATA low 16 bits */ +#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) + +/* CAN1 filter start bank_number*/ +#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) + +/* CAN transmit mailbox extended identifier*/ +#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) + +/* CAN transmit mailbox standard identifier*/ +#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) + +/* transmit data byte 0 */ +#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* transmit data byte 1 */ +#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) + +/* transmit data byte 2 */ +#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) + +/* transmit data byte 3 */ +#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) + +/* transmit data byte 4 */ +#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* transmit data byte 5 */ +#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) + +/* transmit data byte 6 */ +#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) + +/* transmit data byte 7 */ +#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) + +/* receive mailbox extended identifier*/ +#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31) + +/* receive mailbox standrad identifier*/ +#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31) + +/* receive data length */ +#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3) + +/* the index of the filter by which the frame is passed */ +#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15) + +/* receive data byte 0 */ +#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* receive data byte 1 */ +#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15) + +/* receive data byte 2 */ +#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23) + +/* receive data byte 3 */ +#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31) + +/* receive data byte 4 */ +#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* receive data byte 5 */ +#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15) + +/* receive data byte 6 */ +#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23) + +/* receive data byte 7 */ +#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31) + +/* error number */ +#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4, 6) + +/* transmit error count */ +#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16, 23) + +/* receive error count */ +#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24, 31) + +/* CAN errors */ +#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) +#define CAN_ERRN_0 ERR_ERRN(0) /* no error */ +#define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */ +#define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */ +#define CAN_ERRN_3 ERR_ERRN(3) /*!< ACK error */ +#define CAN_ERRN_4 ERR_ERRN(4) /*!< bit recessive error */ +#define CAN_ERRN_5 ERR_ERRN(5) /*!< bit dominant error */ +#define CAN_ERRN_6 ERR_ERRN(6) /*!< CRC error */ +#define CAN_ERRN_7 ERR_ERRN(7) /*!< software error */ + +#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ + +/* CAN communication mode */ +#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */ +#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */ +#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ +#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ + +/* CAN resynchronisation jump width */ +#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ + +/* CAN time segment 1 */ +#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ +#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ +#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ +#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ +#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ +#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */ +#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */ +#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */ +#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */ +#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */ +#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */ +#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */ +#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */ + +/* CAN time segment 2 */ +#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ +#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ +#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ +#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ +#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ + +/* CAN mailbox number */ +#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */ +#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */ +#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */ +#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */ + +/* CAN frame format */ +#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ +#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ + +/* CAN receive fifo */ +#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ +#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ + +/* frame number of receive fifo */ +#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ + +#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ +#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ + +/* CAN working mode */ +#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */ +#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */ +#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */ + +/* filter bits */ +#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */ +#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */ + +/* filter mode */ +#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */ +#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ + +/* filter 16 bits mask */ +#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */ + +/* frame type */ +#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ +#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */ + +/* CAN timeout */ +#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ + +/* interrupt enable bits */ +#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ +#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ +#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ +#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ +#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ +#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ +#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ +#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ +#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ +#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ +#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ +#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ +#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ +#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ + +/* function declarations */ +/* deinitialize CAN */ +void can_deinit(uint32_t can_periph); +/* initialize CAN struct */ +void can_struct_para_init(can_struct_type_enum type, void* p_struct); +/* initialize CAN */ +ErrStatus can_init(uint32_t can_periph, + can_parameter_struct* can_parameter_init); +/* CAN filter init */ +void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init); +/* set can1 fliter start bank number */ +void can1_filter_start_bank(uint8_t start_bank); +/* enable functions */ +/* CAN debug freeze enable */ +void can_debug_freeze_enable(uint32_t can_periph); +/* CAN debug freeze disable */ +void can_debug_freeze_disable(uint32_t can_periph); +/* CAN time trigger mode enable */ +void can_time_trigger_mode_enable(uint32_t can_periph); +/* CAN time trigger mode disable */ +void can_time_trigger_mode_disable(uint32_t can_periph); + +/* transmit functions */ +/* transmit CAN message */ +uint8_t can_message_transmit(uint32_t can_periph, + can_trasnmit_message_struct* transmit_message); +/* get CAN transmit state */ +can_transmit_state_enum can_transmit_states(uint32_t can_periph, + uint8_t mailbox_number); +/* stop CAN transmission */ +void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); +/* CAN receive message */ +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, + can_receive_message_struct* receive_message); +/* CAN release fifo */ +void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); +/* CAN receive message length */ +uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); +/* CAN working mode */ +ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); +/* CAN wakeup from sleep mode */ +ErrStatus can_wakeup(uint32_t can_periph); + +/* CAN get error */ +can_error_enum can_error_get(uint32_t can_periph); +/* get CAN receive error number */ +uint8_t can_receive_error_number_get(uint32_t can_periph); +/* get CAN transmit error number */ +uint8_t can_transmit_error_number_get(uint32_t can_periph); + +/* CAN interrupt enable */ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); +/* CAN interrupt disable */ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); +/* CAN get flag state */ +FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); +/* CAN clear flag state */ +void can_flag_clear(uint32_t can_periph, can_flag_enum flag); +/* CAN get interrupt flag state */ +FlagStatus can_interrupt_flag_get(uint32_t can_periph, + can_interrupt_flag_enum flag); +/* CAN clear interrupt flag state */ +void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); + +#endif /* GD32VF103_CAN_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h new file mode 100644 index 0000000..78b94e7 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h @@ -0,0 +1,78 @@ +/*! + \file gd32vf103_crc.h + \brief definitions for the CRC + + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_CRC_H +#define GD32VF103_CRC_H + +#include "gd32vf103.h" + +/* CRC definitions */ +#define CRC CRC_BASE + +/* registers definitions */ +#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */ +#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */ +#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */ + +/* bits definitions */ +/* CRC_DATA */ +#define CRC_DATA_DATA BITS(0, 31) /*!< CRC calculation result bits */ + +/* CRC_FDATA */ +#define CRC_FDATA_FDATA BITS(0, 7) /*!< CRC free data bits */ + +/* CRC_CTL */ +#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ + +/* function declarations */ +/* deinit CRC calculation unit */ +void crc_deinit(void); + +/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */ +void crc_data_register_reset(void); +/* read the value of the data register */ +uint32_t crc_data_register_read(void); + +/* read the value of the free data register */ +uint8_t crc_free_data_register_read(void); +/* write data to the free data register */ +void crc_free_data_register_write(uint8_t free_data); + +/* calculate the CRC value of a 32-bit data */ +uint32_t crc_single_data_calculate(uint32_t sdata); +/* calculate the CRC value of an array of 32-bit values */ +uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); + +#endif /* GD32VF103_CRC_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h new file mode 100644 index 0000000..3ebc930 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h @@ -0,0 +1,242 @@ +/*! + \file gd32vf103_dac.h + \brief definitions for the DAC + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_DAC_H +#define GD32VF103_DAC_H + +#include "gd32vf103.h" + +/* DACx(x=0,1) definitions */ +#define DAC DAC_BASE +#define DAC0 (0U) +#define DAC1 (1U) + +/* registers definitions */ +#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ +#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ +#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ +#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ +#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ +#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ +#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ +#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ +#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ +#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ +#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ +#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ +#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ + +/* bits definitions */ +/* DAC_CTL */ +#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ +#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ +#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ +#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ +#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ +#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ +#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ +#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ +#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ +#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ + +/* DAC_SWT */ +#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ +#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ + +/* DAC0_R12DH */ +#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ + +/* DAC0_L12DH */ +#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ + +/* DAC0_R8DH */ +#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ + +/* DAC1_R12DH */ +#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ + +/* DAC1_L12DH */ +#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ + +/* DAC1_R8DH */ +#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ + +/* DACC_R12DH */ +#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ +#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ + +/* DACC_L12DH */ +#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ +#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ + +/* DACC_R8DH */ +#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ +#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ + +/* DAC0_DO */ +#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ + +/* DAC1_DO */ +#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ + +/* constants definitions */ +/* DAC trigger source */ +#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ +#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ +#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ +#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ +#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ +#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ +#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ +#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ + +/* DAC noise wave mode */ +#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ +#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ +#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ + +/* DAC noise wave bit width */ +#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) +#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ +#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ +#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ +#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ +#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ +#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ +#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ +#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ +#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ +#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ +#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ +#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ + +/* unmask LFSR bits in DAC LFSR noise mode */ +#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ +#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ +#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ +#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ +#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ +#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ +#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ +#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ +#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ +#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ +#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ +#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ + +/* DAC data alignment */ +#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */ +#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */ +#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */ +/* triangle amplitude in DAC triangle noise mode */ +#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ +#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ +#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ +#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ +#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ +#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ +#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ +#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ +#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ +#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ +#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ +#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ + +/* function declarations */ +/* initialization functions */ +/* deinitialize DAC */ +void dac_deinit(void); +/* enable DAC */ +void dac_enable(uint32_t dac_periph); +/* disable DAC */ +void dac_disable(uint32_t dac_periph); +/* enable DAC DMA */ +void dac_dma_enable(uint32_t dac_periph); +/* disable DAC DMA */ +void dac_dma_disable(uint32_t dac_periph); +/* enable DAC output buffer */ +void dac_output_buffer_enable(uint32_t dac_periph); +/* disable DAC output buffer */ +void dac_output_buffer_disable(uint32_t dac_periph); +/* get the last data output value */ +uint16_t dac_output_value_get(uint32_t dac_periph); +/* set DAC data holding register value */ +void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); + +/* DAC trigger configuration */ +/* enable DAC trigger */ +void dac_trigger_enable(uint32_t dac_periph); +/* disable DAC trigger */ +void dac_trigger_disable(uint32_t dac_periph); +/* configure DAC trigger source */ +void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); +/* enable DAC software trigger */ +void dac_software_trigger_enable(uint32_t dac_periph); +/* disable DAC software trigger */ +void dac_software_trigger_disable(uint32_t dac_periph); + +/* DAC wave mode configuration */ +/* configure DAC wave mode */ +void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode); +/* configure DAC wave bit width */ +void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width); +/* configure DAC LFSR noise mode */ +void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits); +/* configure DAC triangle noise mode */ +void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude); + +/* DAC concurrent mode configuration */ +/* enable DAC concurrent mode */ +void dac_concurrent_enable(void); +/* disable DAC concurrent mode */ +void dac_concurrent_disable(void); +/* enable DAC concurrent software trigger */ +void dac_concurrent_software_trigger_enable(void); +/* disable DAC concurrent software trigger */ +void dac_concurrent_software_trigger_disable(void); +/* enable DAC concurrent buffer function */ +void dac_concurrent_output_buffer_enable(void); +/* disable DAC concurrent buffer function */ +void dac_concurrent_output_buffer_disable(void); +/* set DAC concurrent mode data holding register value */ +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); + +#endif /* GD32VF103_DAC_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h new file mode 100644 index 0000000..262abc7 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h @@ -0,0 +1,109 @@ +/*! + \file gd32vf103_dbg.h + \brief definitions for the DBG + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_DBG_H +#define GD32VF103_DBG_H + +#include "gd32vf103.h" + +/* DBG definitions */ +#define DBG DBG_BASE + +/* registers definitions */ +#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ +#define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */ + +/* bits definitions */ +/* DBG_ID */ +#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ + +/* DBG_CTL */ +#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ +#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ +#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ +#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ +#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ +#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ +#define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */ +#define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */ +#define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */ +#define DBG_CTL_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */ +#define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ +#define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ +#define DBG_CTL_TIMER4_HOLD BIT(18) /*!< hold TIMER4 counter when core is halted */ +#define DBG_CTL_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */ +#define DBG_CTL_TIMER6_HOLD BIT(20) /*!< hold TIMER6 counter when core is halted */ +#define DBG_CTL_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */ + +/* constants definitions */ +/* debug hold when core is halted */ +typedef enum +{ + DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */ + DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */ + DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */ + DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */ + DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */ + DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */ + DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */ + DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */ + DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */ + DBG_TIMER4_HOLD = BIT(17), /*!< hold TIMER4 counter when core is halted */ + DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */ + DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */ + DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */ +}dbg_periph_enum; + +/* DBG low power mode configurations */ +#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */ +#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ +#define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */ + +/* function declarations */ +/* read DBG_ID code register */ +uint32_t dbg_id_get(void); + +/* low power behavior configuration */ +/* enable low power behavior when the MCU is in debug mode */ +void dbg_low_power_enable(uint32_t dbg_low_power); +/* disable low power behavior when the MCU is in debug mode */ +void dbg_low_power_disable(uint32_t dbg_low_power); + +/* peripheral behavior configuration */ +/* enable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_enable(dbg_periph_enum dbg_periph); +/* disable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_disable(dbg_periph_enum dbg_periph); + +#endif /* GD32VF103_DBG_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h new file mode 100644 index 0000000..9b027d4 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h @@ -0,0 +1,282 @@ +/*! + \file gd32vf103_dma.h + \brief definitions for the DMA + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_DMA_H +#define GD32VF103_DMA_H + +#include "gd32vf103.h" + +/* DMA definitions */ +#define DMA0 (DMA_BASE) /*!< DMA0 base address */ +#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */ + +/* registers definitions */ +#define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */ +#define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */ + +#define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */ +#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */ +#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */ +#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */ + +#define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */ +#define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */ +#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */ +#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */ + +#define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */ +#define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */ +#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */ +#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */ + +#define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */ +#define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */ +#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */ +#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */ + +#define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */ +#define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */ +#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */ +#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */ + +#define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */ +#define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */ +#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */ +#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */ + +#define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */ +#define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */ +#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */ +#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */ + +/* bits definitions */ +/* DMA_INTF */ +#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ +#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ +#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ +#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ + +/* DMA_INTC */ +#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ +#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ +#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ +#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ + +/* DMA_CHxCTL, x=0..6 */ +#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */ +#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */ +#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */ +#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */ +#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */ +#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ +#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ +#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ +#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ +#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ +#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ +#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ + +/* DMA_CHxCNT, x=0..6 */ +#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ + +/* DMA_CHxPADDR, x=0..6 */ +#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ + +/* DMA_CHxMADDR, x=0..6 */ +#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ + +/* constants definitions */ +/* DMA channel select */ +typedef enum +{ + DMA_CH0 = 0, /*!< DMA Channel0 */ + DMA_CH1, /*!< DMA Channel1 */ + DMA_CH2, /*!< DMA Channel2 */ + DMA_CH3, /*!< DMA Channel3 */ + DMA_CH4, /*!< DMA Channel4 */ + DMA_CH5, /*!< DMA Channel5 */ + DMA_CH6 /*!< DMA Channel6 */ +} dma_channel_enum; + +/* DMA initialize struct */ +typedef struct +{ + uint32_t periph_addr; /*!< peripheral base address */ + uint32_t periph_width; /*!< transfer data size of peripheral */ + uint32_t memory_addr; /*!< memory base address */ + uint32_t memory_width; /*!< transfer data size of memory */ + uint32_t number; /*!< channel transfer number */ + uint32_t priority; /*!< channel priority level */ + uint8_t periph_inc; /*!< peripheral increasing mode */ + uint8_t memory_inc; /*!< memory increasing mode */ + uint8_t direction; /*!< channel data transfer direction */ + +} dma_parameter_struct; + +#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */ + +/* DMA_register address */ +#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ +#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ +#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ +#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ + +/* DMA reset value */ +#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ +#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ +#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ +#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ +#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ + DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */ + +/* DMA_INTF register */ +/* interrupt flag bits */ +#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ + +/* flag bits */ +#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ +#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ +#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ + +/* DMA_CHxCTL register */ +/* interrupt enable bits */ +#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ +#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ +#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ + +/* transfer direction */ +#define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x0000U) /*!< read from peripheral and write to memory */ +#define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x0001U) /*!< read from memory and write to peripheral */ + +/* peripheral increasing mode */ +#define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x0000U) /*!< next address of peripheral is fixed address mode */ +#define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of peripheral is increasing address mode */ + +/* memory increasing mode */ +#define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x0000U) /*!< next address of memory is fixed address mode */ +#define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of memory is increasing address mode */ + +/* transfer data size of peripheral */ +#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */ +#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */ +#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */ +#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */ + +/* transfer data size of memory */ +#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */ +#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */ +#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */ +#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */ + +/* channel priority level */ +#define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ +#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */ +#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */ +#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */ +#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */ + +/* memory to memory mode */ +#define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U) /*!< disable memory to memory mode */ +#define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U) /*!< enable memory to memory mode */ + +/* DMA_CHxCNT register */ +/* transfer counter */ +#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */ + +/* function declarations */ +/* DMA deinitialization and initialization functions */ +/* deinitialize DMA a channel registers */ +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); +/* initialize the parameters of DMA struct with the default values */ +void dma_struct_para_init(dma_parameter_struct* init_struct); +/* initialize DMA channel */ +void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct); +/* enable DMA circulation mode */ +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable DMA circulation mode */ +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable memory to memory mode */ +void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable memory to memory mode */ +void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable DMA channel */ +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable DMA channel */ +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); + +/* DMA configuration functions */ +/* set DMA peripheral base address */ +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); +/* set DMA memory base address */ +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); +/* set the number of remaining data to be transferred by the DMA */ +void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number); +/* get the number of remaining data to be transferred by the DMA */ +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); +/* configure priority level of DMA channel */ +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); +/* configure transfer data size of memory */ +void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth); +/* configure transfer data size of peripheral */ +void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth); +/* enable next address increasement algorithm of memory */ +void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable next address increasement algorithm of memory */ +void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable next address increasement algorithm of peripheral */ +void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable next address increasement algorithm of peripheral */ +void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* configure the direction of data transfer on the channel */ +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction); + +/* flag and interrupt functions */ +/* check DMA flag is set or not */ +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* clear the flag of a DMA channel */ +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* check DMA flag and interrupt enable bit is set or not */ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* clear the interrupt flag of a DMA channel */ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* enable DMA interrupt */ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); +/* disable DMA interrupt */ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); + +#endif /* GD32VF103_DMA_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h new file mode 100644 index 0000000..b36f9a6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h @@ -0,0 +1,66 @@ +/*! + \file gd32vf103_eclic.h + \brief definitions for the ECLIC(Enhancement Core-Local Interrupt Controller) + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_ECLIC_H +#define GD32VF103_ECLIC_H + +#include "gd32vf103.h" + +/* constants definitions */ +#define ECLIC_PRIGROUP_LEVEL0_PRIO4 0 /*!< 0 bits for level 4 bits for priority */ +#define ECLIC_PRIGROUP_LEVEL1_PRIO3 1 /*!< 1 bits for level 3 bits for priority */ +#define ECLIC_PRIGROUP_LEVEL2_PRIO2 2 /*!< 2 bits for level 2 bits for priority */ +#define ECLIC_PRIGROUP_LEVEL3_PRIO1 3 /*!< 3 bits for level 1 bits for priority */ +#define ECLIC_PRIGROUP_LEVEL4_PRIO0 4 /*!< 4 bits for level 0 bits for priority */ + +#define __SEV eclic_send_event + +/* function declarations */ +/* enable the global interrupt */ +void eclic_global_interrupt_enable(void); +/* disable the global interrupt */ +void eclic_global_interrupt_disable(void); +/* set the priority group */ +void eclic_priority_group_set(uint32_t prigroup); +/* enable the interrupt request */ +void eclic_irq_enable(uint32_t source, uint8_t level, uint8_t priority); +/* disable the interrupt request */ +void eclic_irq_disable(uint32_t source); + +/* reset system */ +void eclic_system_reset(void); +/* send event(SEV) */ +void eclic_send_event(void); + +#endif /* GD32VF103_ECLIC_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h new file mode 100644 index 0000000..8022104 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h @@ -0,0 +1,126 @@ +/*! + \file gd32vf103_exmc.h + \brief definitions for the EXMC + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_EXMC_H +#define GD32VF103_EXMC_H + +#include "gd32vf103.h" + +/* EXMC definitions */ +#define EXMC (EXMC_BASE) /*!< EXMC register base address */ + +/* registers definitions */ +/* NOR/PSRAM */ +#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */ +#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */ +#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */ + +/* bits definitions */ +/* NOR/PSRAM */ +/* EXMC_SNCTLx, x=0 */ +#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ +#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */ +#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ +#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ +#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ +#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ +#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ +#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ +#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ + +/* EXMC_SNTCFGx, x=0 */ +#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ +#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ +#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ +#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ + +/* constants definitions */ +/* EXMC NOR/SRAM timing initialize struct */ +typedef struct +{ + uint32_t bus_latency; /*!< configure the bus latency */ + uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ + uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */ + uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ +}exmc_norsram_timing_parameter_struct; + +/* EXMC NOR/SRAM initialize struct */ +typedef struct +{ + uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ + uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ + uint32_t nwait_signal; /*!< enable or disable the NWAIT signal */ + uint32_t memory_write; /*!< enable or disable the write operation */ + uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ + uint32_t databus_width; /*!< specifies the databus width of external memory */ + uint32_t memory_type; /*!< specifies the type of external memory */ + uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ + exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write */ +}exmc_norsram_parameter_struct; + +/* EXMC register address */ +#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */ +#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */ + +/* NOR bank memory data bus width */ +#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ +#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ + +/* NOR bank memory type */ +#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ +#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ +#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ + +/* EXMC NOR/SRAM bank region definition */ +#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ + +/* EXMC NWAIT signal polarity configuration */ +#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ +#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */ + +/* function declarations */ +/* deinitialize EXMC NOR/SRAM region */ +void exmc_norsram_deinit(uint32_t norsram_region); +/* exmc_norsram_parameter_struct parameter initialize */ +void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); +/* initialize EXMC NOR/SRAM region */ +void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); +/* EXMC NOR/SRAM bank enable */ +void exmc_norsram_enable(uint32_t norsram_region); +/* EXMC NOR/SRAM bank disable */ +void exmc_norsram_disable(uint32_t norsram_region); + +#endif /* GD32VF103_EXMC_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h new file mode 100644 index 0000000..8e8ca85 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h @@ -0,0 +1,245 @@ +/*! + \file gd32vf103_exti.h + \brief definitions for the EXTI + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_EXTI_H +#define GD32VF103_EXTI_H + +#include "gd32vf103.h" + +/* EXTI definitions */ +#define EXTI EXTI_BASE + +/* registers definitions */ +#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */ +#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */ +#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */ +#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */ +#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */ +#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */ + +/* bits definitions */ +/* EXTI_INTEN */ +#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ +#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ +#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ +#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ +#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ +#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ +#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ +#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ +#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ +#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ +#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ +#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ +#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ +#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ +#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ +#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ +#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ +#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ +#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ + +/* EXTI_EVEN */ +#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ +#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ +#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ +#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ +#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ +#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ +#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ +#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ +#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ +#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ +#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ +#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ +#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ +#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ +#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ +#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ +#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ +#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ +#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ + +/* EXTI_RTEN */ +#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ +#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ +#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ +#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ +#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ +#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ +#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ +#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ +#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ +#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ +#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ +#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ +#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ +#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ +#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ +#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ +#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ +#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ +#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ + +/* EXTI_FTEN */ +#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ +#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ +#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ +#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ +#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ +#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ +#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ +#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ +#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ +#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ +#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ +#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ +#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ +#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ +#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ +#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ +#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ +#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ +#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ + +/* EXTI_SWIEV */ +#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ +#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ +#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ +#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ +#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ +#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ +#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ +#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ +#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ +#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ +#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ +#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ +#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ +#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ +#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ +#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ +#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ +#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ +#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ + +/* EXTI_PD */ +#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ +#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ +#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ +#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ +#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ +#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ +#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ +#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ +#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ +#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ +#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ +#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ +#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ +#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ +#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ +#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ +#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ +#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ +#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ + +/* constants definitions */ +/* EXTI line number */ +typedef enum { + EXTI_0 = BIT(0), /*!< EXTI line 0 */ + EXTI_1 = BIT(1), /*!< EXTI line 1 */ + EXTI_2 = BIT(2), /*!< EXTI line 2 */ + EXTI_3 = BIT(3), /*!< EXTI line 3 */ + EXTI_4 = BIT(4), /*!< EXTI line 4 */ + EXTI_5 = BIT(5), /*!< EXTI line 5 */ + EXTI_6 = BIT(6), /*!< EXTI line 6 */ + EXTI_7 = BIT(7), /*!< EXTI line 7 */ + EXTI_8 = BIT(8), /*!< EXTI line 8 */ + EXTI_9 = BIT(9), /*!< EXTI line 9 */ + EXTI_10 = BIT(10), /*!< EXTI line 10 */ + EXTI_11 = BIT(11), /*!< EXTI line 11 */ + EXTI_12 = BIT(12), /*!< EXTI line 12 */ + EXTI_13 = BIT(13), /*!< EXTI line 13 */ + EXTI_14 = BIT(14), /*!< EXTI line 14 */ + EXTI_15 = BIT(15), /*!< EXTI line 15 */ + EXTI_16 = BIT(16), /*!< EXTI line 16 */ + EXTI_17 = BIT(17), /*!< EXTI line 17 */ + EXTI_18 = BIT(18), /*!< EXTI line 18 */ +} exti_line_enum; + +/* external interrupt and event */ +typedef enum { + EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ + EXTI_EVENT /*!< EXTI event mode */ +} exti_mode_enum; + +/* interrupt trigger mode */ +typedef enum { + EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ + EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ + EXTI_TRIG_BOTH, /*!< EXTI rising edge and falling edge trigger */ + EXTI_TRIG_NONE /*!< without rising edge or falling edge trigger */ +} exti_trig_type_enum; + +/* function declarations */ +/* initialization, EXTI lines configuration functions */ +/* deinitialize the EXTI */ +void exti_deinit(void); +/* enable the configuration of EXTI initialize */ +void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); +/* enable the interrupts from EXTI line x */ +void exti_interrupt_enable(exti_line_enum linex); +/* enable the events from EXTI line x */ +void exti_event_enable(exti_line_enum linex); +/* disable the interrupts from EXTI line x */ +void exti_interrupt_disable(exti_line_enum linex); +/* disable the events from EXTI line x */ +void exti_event_disable(exti_line_enum linex); + +/* interrupt & flag functions */ +/* get EXTI lines pending flag */ +FlagStatus exti_flag_get(exti_line_enum linex); +/* clear EXTI lines pending flag */ +void exti_flag_clear(exti_line_enum linex); +/* get EXTI lines flag when the interrupt flag is set */ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex); +/* clear EXTI lines pending flag */ +void exti_interrupt_flag_clear(exti_line_enum linex); +/* enable the EXTI software interrupt event */ +void exti_software_interrupt_enable(exti_line_enum linex); +/* disable the EXTI software interrupt event */ +void exti_software_interrupt_disable(exti_line_enum linex); + +#endif /* GD32VF103_EXTI_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h new file mode 100644 index 0000000..05ecbd6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h @@ -0,0 +1,312 @@ +/*! + \file gd32vf103_fmc.h + \brief definitions for the FMC + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + \version 2019-09-18, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_FMC_H +#define GD32VF103_FMC_H + +#include "gd32vf103.h" + +/* FMC and option byte definition */ +#define FMC FMC_BASE /*!< FMC register base address */ +#define OB OB_BASE /*!< option bytes base address */ + +/* registers definitions */ +#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ +#define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */ +#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */ +#define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */ +#define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */ +#define FMC_ADDR REG32((FMC) + 0x14U) /*!< FMC address register */ +#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */ +#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */ +#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ + +#define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */ +#define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/ +#define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */ +#define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */ +#define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */ +#define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */ + +/* bits definitions */ +/* FMC_WS */ +#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ + +/* FMC_KEY */ +#define FMC_KEY_KEY BITS(0,31) /*!< FMC_CTL unlock key bits */ + +/* FMC_OBKEY */ +#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ + +/* FMC_STAT */ +#define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */ +#define FMC_STAT_PGERR BIT(2) /*!< flash program error flag bit */ +#define FMC_STAT_WPERR BIT(4) /*!< erase/program protection error flag bit */ +#define FMC_STAT_ENDF BIT(5) /*!< end of operation flag bit */ + +/* FMC_CTL */ +#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */ +#define FMC_CTL_PER BIT(1) /*!< main flash page erase command bit */ +#define FMC_CTL_MER BIT(2) /*!< main flash mass erase command bit */ +#define FMC_CTL_OBPG BIT(4) /*!< option bytes program command bit */ +#define FMC_CTL_OBER BIT(5) /*!< option bytes erase command bit */ +#define FMC_CTL_START BIT(6) /*!< send erase command to FMC bit */ +#define FMC_CTL_LK BIT(7) /*!< FMC_CTL lock bit */ +#define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ +#define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable bit */ +#define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ + +/* FMC_ADDR */ +#define FMC_ADDR0_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ + +/* FMC_OBSTAT */ +#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ +#define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ +#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ +#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ + +/* FMC_WP */ +#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ + +/* FMC_WSEN */ +#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ + +/* FMC_PID */ +#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ + +/* constants definitions */ +/* define the FMC bit position and its register index offset */ +#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6))) +#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) +#define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12))) +#define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) +#define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) +#define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12) + +/* configuration register */ +#define FMC_STAT_REG_OFFSET 0x0CU /*!< status register offset */ +#define FMC_CTL_REG_OFFSET 0x10U /*!< control register offset */ +#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */ + +/* fmc state */ +typedef enum +{ + FMC_READY, /*!< the operation has been completed */ + FMC_BUSY, /*!< the operation is in progress */ + FMC_PGERR, /*!< program error */ + FMC_WPERR, /*!< erase/program protection error */ + FMC_TOERR, /*!< timeout error */ +}fmc_state_enum; + +/* FMC interrupt enable */ +typedef enum +{ + FMC_INT_END = FMC_REGIDX_BIT(FMC_CTL_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */ + FMC_INT_ERR = FMC_REGIDX_BIT(FMC_CTL_REG_OFFSET, 10U), /*!< enable FMC error interrupt */ +}fmc_int_enum; + +/* FMC flags */ +typedef enum +{ + FMC_FLAG_BUSY = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 0U), /*!< FMC busy flag */ + FMC_FLAG_PGERR = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 2U), /*!< FMC operation error flag bit */ + FMC_FLAG_WPERR = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 4U), /*!< FMC erase/program protection error flag bit */ + FMC_FLAG_END = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 5U), /*!< FMC end of operation flag bit */ + FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */ +}fmc_flag_enum; + +/* FMC interrupt flags */ +typedef enum +{ + FMC_INT_FLAG_PGERR = FMC_REGIDX_BITS(FMC_STAT_REG_OFFSET, 2U, 10U), /*!< FMC operation error interrupt flag bit */ + FMC_INT_FLAG_WPERR = FMC_REGIDX_BITS(FMC_STAT_REG_OFFSET, 4U, 10U), /*!< FMC erase/program protection error interrupt flag bit */ + FMC_INT_FLAG_END = FMC_REGIDX_BITS(FMC_STAT_REG_OFFSET, 5U, 12U), /*!< FMC end of operation interrupt flag bit */ +}fmc_interrupt_flag_enum; + +/* unlock key */ +#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ +#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ + +/* FMC wait state counter */ +#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) +#define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ +#define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ +#define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ + +/* option bytes software/hardware free watch dog timer */ +#define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */ +#define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */ + +/* option bytes reset or not entering deep sleep mode */ +#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */ +#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */ + +/* option bytes reset or not entering standby mode */ +#define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */ +#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */ + +/* option bytes boot bank value */ +#define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */ + +#define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */ + +/* read protect configure */ +#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ +#define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */ + +/* OB_SPC */ +#define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */ +#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */ + +/* OB_USER */ +#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */ +#define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */ + +/* OB_WP0 */ +#define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */ + +/* OB_WP1 */ +#define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */ + +/* OB_WP2 */ +#define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */ + +/* OB_WP3 */ +#define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */ + +/* option bytes write protection */ +#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ +#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ +#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ +#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ +#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ +#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ +#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ +#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ +#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ +#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ +#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ +#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ +#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */ +#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */ +#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */ +#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */ +#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */ +#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */ +#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */ +#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */ +#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */ +#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */ +#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */ +#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */ +#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */ +#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */ +#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */ +#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */ +#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */ +#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */ +#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */ +#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */ +#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */ + +/* FMC timeout */ +#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */ + +/* FMC BANK address */ +#define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */ +#define SRAM_SIZE (*(uint16_t *)0x1FFFF7E2U) /*!< SRAM size*/ + +/* function declarations */ +/* FMC main memory programming functions */ +/* set the FMC wait state counter */ +void fmc_wscnt_set(uint32_t wscnt); +/* unlock the main FMC operation */ +void fmc_unlock(void); +/* lock the main FMC operation */ +void fmc_lock(void); +/* FMC erase page */ +fmc_state_enum fmc_page_erase(uint32_t page_address); +/* FMC erase whole chip */ +fmc_state_enum fmc_mass_erase(void); +/* FMC program a word at the corresponding address */ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); +/* FMC program a half word at the corresponding address */ +fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); + +/* FMC option bytes programming functions */ +/* unlock the option byte operation */ +void ob_unlock(void); +/* lock the option byte operation */ +void ob_lock(void); +/* erase the FMC option byte */ +fmc_state_enum ob_erase(void); +/* enable write protection */ +fmc_state_enum ob_write_protection_enable(uint32_t ob_wp); +/* configure security protection */ +fmc_state_enum ob_security_protection_config(uint8_t ob_spc); +/* program the FMC user option byte */ +fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot); +/* program the FMC data option byte */ +fmc_state_enum ob_data_program(uint32_t address, uint8_t data); +/* get OB_USER in register FMC_OBSTAT */ +uint8_t ob_user_get(void); +/* get OB_DATA in register FMC_OBSTAT */ +uint16_t ob_data_get(void); +/* get the FMC option byte write protection */ +uint32_t ob_write_protection_get(void); +/* get FMC option byte security protection state */ +FlagStatus ob_spc_get(void); + +/* FMC interrupts and flags management functions */ +/* enable FMC interrupt */ +void fmc_interrupt_enable(uint32_t interrupt); +/* disable FMC interrupt */ +void fmc_interrupt_disable(uint32_t interrupt); +/* check flag is set or not */ +FlagStatus fmc_flag_get(uint32_t flag); +/* clear the FMC flag */ +void fmc_flag_clear(uint32_t flag); +/* get FMC interrupt flag state */ +FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag); +/* clear FMC interrupt flag state */ +void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag); +/* return the FMC state */ +fmc_state_enum fmc_state_get(void); +/* check FMC ready or not */ +fmc_state_enum fmc_ready_wait(uint32_t timeout); + +#endif /* GD32VF103_FMC_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h new file mode 100644 index 0000000..941cdc1 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h @@ -0,0 +1,104 @@ +/*! + \file gd32vf103_fwdgt.h + \brief definitions for the FWDGT + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_FWDGT_H +#define GD32VF103_FWDGT_H + +#include "gd32vf103.h" + +/* FWDGT definitions */ +#define FWDGT FWDGT_BASE /*!< FWDGT base address */ + +/* registers definitions */ +#define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */ +#define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */ +#define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */ +#define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */ + +/* bits definitions */ +/* FWDGT_CTL */ +#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ + +/* FWDGT_PSC */ +#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ + +/* FWDGT_RLD */ +#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ + +/* FWDGT_STAT */ +#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ +#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ + +/* constants definitions */ +/* psc register value */ +#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ +#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ +#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ +#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ +#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ +#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ +#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ + +/* control value */ +#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ +#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ +#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ +#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ + +/* FWDGT timeout value */ +#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ +#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ + +/* FWDGT flag definitions */ +#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ +#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ + +/* function declarations */ +/* enable write access to FWDGT_PSC and FWDGT_RLD */ +void fwdgt_write_enable(void); +/* disable write access to FWDGT_PSC and FWDGT_RLD */ +void fwdgt_write_disable(void); +/* start the free watchdog timer counter */ +void fwdgt_enable(void); + +/* reload the counter of FWDGT */ +void fwdgt_counter_reload(void); +/* configure counter reload value, and prescaler divider value */ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); + +/* get flag state of FWDGT */ +FlagStatus fwdgt_flag_get(uint16_t flag); + +#endif /* GD32VF103_FWDGT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h new file mode 100644 index 0000000..d547299 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h @@ -0,0 +1,421 @@ +/*! + \file gd32vf103_gpio.h + \brief definitions for the GPIO + + \version 2019-06-5, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_GPIO_H +#define GD32VF103_GPIO_H + +#include "gd32vf103.h" + +/* GPIOx(x=A,B,C,D,E) definitions */ +#define GPIOA (GPIO_BASE + 0x00000000U) +#define GPIOB (GPIO_BASE + 0x00000400U) +#define GPIOC (GPIO_BASE + 0x00000800U) +#define GPIOD (GPIO_BASE + 0x00000C00U) +#define GPIOE (GPIO_BASE + 0x00001000U) + +/* AFIO definitions */ +#define AFIO AFIO_BASE + +/* registers definitions */ + +/* GPIO registers definitions */ +#define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register 0 */ +#define GPIO_CTL1(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port control register 1 */ +#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port input status register */ +#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port output control register */ +#define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port bit operation register */ +#define GPIO_BC(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO bit clear register */ +#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port configuration lock register */ + +/* AFIO registers definitions */ +#define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */ +#define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register 0 */ +#define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection register 0 */ +#define AFIO_EXTISS1 REG32(AFIO + 0x0CU) /*!< AFIO port EXTI sources selection register 1 */ +#define AFIO_EXTISS2 REG32(AFIO + 0x10U) /*!< AFIO port EXTI sources selection register 2 */ +#define AFIO_EXTISS3 REG32(AFIO + 0x14U) /*!< AFIO port EXTI sources selection register 3 */ +#define AFIO_PCF1 REG32(AFIO + 0x1CU) /*!< AFIO port configuration register 1 */ + +/* bits definitions */ +/* GPIO_CTL0 */ +#define GPIO_CTL0_MD0 BITS(0, 1) /*!< port 0 mode bits */ +#define GPIO_CTL0_CTL0 BITS(2, 3) /*!< pin 0 configuration bits */ +#define GPIO_CTL0_MD1 BITS(4, 5) /*!< port 1 mode bits */ +#define GPIO_CTL0_CTL1 BITS(6, 7) /*!< pin 1 configuration bits */ +#define GPIO_CTL0_MD2 BITS(8, 9) /*!< port 2 mode bits */ +#define GPIO_CTL0_CTL2 BITS(10, 11) /*!< pin 2 configuration bits */ +#define GPIO_CTL0_MD3 BITS(12, 13) /*!< port 3 mode bits */ +#define GPIO_CTL0_CTL3 BITS(14, 15) /*!< pin 3 configuration bits */ +#define GPIO_CTL0_MD4 BITS(16, 17) /*!< port 4 mode bits */ +#define GPIO_CTL0_CTL4 BITS(18, 19) /*!< pin 4 configuration bits */ +#define GPIO_CTL0_MD5 BITS(20, 21) /*!< port 5 mode bits */ +#define GPIO_CTL0_CTL5 BITS(22, 23) /*!< pin 5 configuration bits */ +#define GPIO_CTL0_MD6 BITS(24, 25) /*!< port 6 mode bits */ +#define GPIO_CTL0_CTL6 BITS(26, 27) /*!< pin 6 configuration bits */ +#define GPIO_CTL0_MD7 BITS(28, 29) /*!< port 7 mode bits */ +#define GPIO_CTL0_CTL7 BITS(30, 31) /*!< pin 7 configuration bits */ + +/* GPIO_CTL1 */ +#define GPIO_CTL1_MD8 BITS(0, 1) /*!< port 8 mode bits */ +#define GPIO_CTL1_CTL8 BITS(2, 3) /*!< pin 8 configuration bits */ +#define GPIO_CTL1_MD9 BITS(4, 5) /*!< port 9 mode bits */ +#define GPIO_CTL1_CTL9 BITS(6, 7) /*!< pin 9 configuration bits */ +#define GPIO_CTL1_MD10 BITS(8, 9) /*!< port 10 mode bits */ +#define GPIO_CTL1_CTL10 BITS(10, 11) /*!< pin 10 configuration bits */ +#define GPIO_CTL1_MD11 BITS(12, 13) /*!< port 11 mode bits */ +#define GPIO_CTL1_CTL11 BITS(14, 15) /*!< pin 11 configuration bits */ +#define GPIO_CTL1_MD12 BITS(16, 17) /*!< port 12 mode bits */ +#define GPIO_CTL1_CTL12 BITS(18, 19) /*!< pin 12 configuration bits */ +#define GPIO_CTL1_MD13 BITS(20, 21) /*!< port 13 mode bits */ +#define GPIO_CTL1_CTL13 BITS(22, 23) /*!< pin 13 configuration bits */ +#define GPIO_CTL1_MD14 BITS(24, 25) /*!< port 14 mode bits */ +#define GPIO_CTL1_CTL14 BITS(26, 27) /*!< pin 14 configuration bits */ +#define GPIO_CTL1_MD15 BITS(28, 29) /*!< port 15 mode bits */ +#define GPIO_CTL1_CTL15 BITS(30, 31) /*!< pin 15 configuration bits */ + +/* GPIO_ISTAT */ +#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ +#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ +#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ +#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ +#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ +#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ +#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ +#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ +#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ +#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ +#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ +#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ +#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ +#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ +#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ +#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ + +/* GPIO_OCTL */ +#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ +#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ +#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ +#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ +#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ +#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ +#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ +#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ +#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ +#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ +#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ +#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ +#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ +#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ +#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ +#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ + +/* GPIO_BOP */ +#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ +#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ +#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ +#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ +#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ +#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ +#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ +#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ +#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ +#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ +#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ +#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ +#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ +#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ +#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ +#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ +#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ +#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ +#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ +#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ +#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ +#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ +#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ +#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ +#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ +#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ +#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ +#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ +#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ +#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ +#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ +#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ + +/* GPIO_BC */ +#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ +#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ +#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ +#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ +#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ +#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ +#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ +#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ +#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ +#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ +#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ +#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ +#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ +#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ +#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ +#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ + +/* GPIO_LOCK */ +#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ +#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ +#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ +#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ +#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ +#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ +#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ +#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ +#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ +#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ +#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ +#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ +#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ +#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ +#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ +#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ +#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ + +/* AFIO_EC */ +#define AFIO_EC_PIN BITS(0, 3) /*!< event output pin selection */ +#define AFIO_EC_PORT BITS(4, 6) /*!< event output port selection */ +#define AFIO_EC_EOE BIT(7) /*!< event output enable */ + +/* AFIO_PCF0 */ +#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ +#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ +#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ +#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ +#define AFIO_PCF0_USART2_REMAP BITS(4, 5) /*!< USART2 remapping */ +#define AFIO_PCF0_TIMER0_REMAP BITS(6, 7) /*!< TIMER0 remapping */ +#define AFIO_PCF0_TIMER1_REMAP BITS(8, 9) /*!< TIMER1 remapping */ +#define AFIO_PCF0_TIMER2_REMAP BITS(10, 11) /*!< TIMER2 remapping */ +#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ +#define AFIO_PCF0_CAN_REMAP BITS(13, 14) /*!< CAN remapping */ +#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER3 channel3 internal remapping */ +#define AFIO_PCF0_SWJ_CFG BITS(24, 26) /*!< serial wire JTAG configuration */ +#define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ +#define AFIO_PCF0_TIMER1_ITI1_REMAP BIT(29) /*!< TIMER1 internal trigger 1 remapping */ + +/* AFIO_EXTISS0 */ +#define AFIO_EXTI0_SS BITS(0, 3) /*!< EXTI 0 sources selection */ +#define AFIO_EXTI1_SS BITS(4, 7) /*!< EXTI 1 sources selection */ +#define AFIO_EXTI2_SS BITS(8, 11) /*!< EXTI 2 sources selection */ +#define AFIO_EXTI3_SS BITS(12, 15) /*!< EXTI 3 sources selection */ + +/* AFIO_EXTISS1 */ +#define AFIO_EXTI4_SS BITS(0, 3) /*!< EXTI 4 sources selection */ +#define AFIO_EXTI5_SS BITS(4, 7) /*!< EXTI 5 sources selection */ +#define AFIO_EXTI6_SS BITS(8, 11) /*!< EXTI 6 sources selection */ +#define AFIO_EXTI7_SS BITS(12, 15) /*!< EXTI 7 sources selection */ + +/* AFIO_EXTISS2 */ +#define AFIO_EXTI8_SS BITS(0, 3) /*!< EXTI 8 sources selection */ +#define AFIO_EXTI9_SS BITS(4, 7) /*!< EXTI 9 sources selection */ +#define AFIO_EXTI10_SS BITS(8, 11) /*!< EXTI 10 sources selection */ +#define AFIO_EXTI11_SS BITS(12, 15) /*!< EXTI 11 sources selection */ + +/* AFIO_EXTISS3 */ +#define AFIO_EXTI12_SS BITS(0, 3) /*!< EXTI 12 sources selection */ +#define AFIO_EXTI13_SS BITS(4, 7) /*!< EXTI 13 sources selection */ +#define AFIO_EXTI14_SS BITS(8, 11) /*!< EXTI 14 sources selection */ +#define AFIO_EXTI15_SS BITS(12, 15) /*!< EXTI 15 sources selection */ + +/* AFIO_PCF1 */ +#define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ + +/* constants definitions */ +typedef FlagStatus bit_status; + +/* GPIO mode values set */ +#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (4U * (n)))) +#define GPIO_MODE_MASK(n) (0xFU << (4U * (n))) + +/* GPIO mode definitions */ +#define GPIO_MODE_AIN ((uint8_t)0x00U) /*!< analog input mode */ +#define GPIO_MODE_IN_FLOATING ((uint8_t)0x04U) /*!< floating input mode */ +#define GPIO_MODE_IPD ((uint8_t)0x28U) /*!< pull-down input mode */ +#define GPIO_MODE_IPU ((uint8_t)0x48U) /*!< pull-up input mode */ +#define GPIO_MODE_OUT_OD ((uint8_t)0x14U) /*!< GPIO output with open-drain */ +#define GPIO_MODE_OUT_PP ((uint8_t)0x10U) /*!< GPIO output with push-pull */ +#define GPIO_MODE_AF_OD ((uint8_t)0x1CU) /*!< AFIO output with open-drain */ +#define GPIO_MODE_AF_PP ((uint8_t)0x18U) /*!< AFIO output with push-pull */ + +/* GPIO output max speed value */ +#define GPIO_OSPEED_10MHZ ((uint8_t)0x01U) /*!< output max speed 10MHz */ +#define GPIO_OSPEED_2MHZ ((uint8_t)0x02U) /*!< output max speed 2MHz */ +#define GPIO_OSPEED_50MHZ ((uint8_t)0x03U) /*!< output max speed 50MHz */ + +/* GPIO event output port definitions */ +#define GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U) /*!< event output port A */ +#define GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U) /*!< event output port B */ +#define GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U) /*!< event output port C */ +#define GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U) /*!< event output port D */ +#define GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U) /*!< event output port E */ + +/* GPIO output port source definitions */ +#define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U) /*!< output port source A */ +#define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U) /*!< output port source B */ +#define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U) /*!< output port source C */ +#define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U) /*!< output port source D */ +#define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U) /*!< output port source E */ + +/* GPIO event output pin definitions */ +#define GPIO_EVENT_PIN_0 ((uint8_t)0x00U) /*!< GPIO event pin 0 */ +#define GPIO_EVENT_PIN_1 ((uint8_t)0x01U) /*!< GPIO event pin 1 */ +#define GPIO_EVENT_PIN_2 ((uint8_t)0x02U) /*!< GPIO event pin 2 */ +#define GPIO_EVENT_PIN_3 ((uint8_t)0x03U) /*!< GPIO event pin 3 */ +#define GPIO_EVENT_PIN_4 ((uint8_t)0x04U) /*!< GPIO event pin 4 */ +#define GPIO_EVENT_PIN_5 ((uint8_t)0x05U) /*!< GPIO event pin 5 */ +#define GPIO_EVENT_PIN_6 ((uint8_t)0x06U) /*!< GPIO event pin 6 */ +#define GPIO_EVENT_PIN_7 ((uint8_t)0x07U) /*!< GPIO event pin 7 */ +#define GPIO_EVENT_PIN_8 ((uint8_t)0x08U) /*!< GPIO event pin 8 */ +#define GPIO_EVENT_PIN_9 ((uint8_t)0x09U) /*!< GPIO event pin 9 */ +#define GPIO_EVENT_PIN_10 ((uint8_t)0x0AU) /*!< GPIO event pin 10 */ +#define GPIO_EVENT_PIN_11 ((uint8_t)0x0BU) /*!< GPIO event pin 11 */ +#define GPIO_EVENT_PIN_12 ((uint8_t)0x0CU) /*!< GPIO event pin 12 */ +#define GPIO_EVENT_PIN_13 ((uint8_t)0x0DU) /*!< GPIO event pin 13 */ +#define GPIO_EVENT_PIN_14 ((uint8_t)0x0EU) /*!< GPIO event pin 14 */ +#define GPIO_EVENT_PIN_15 ((uint8_t)0x0FU) /*!< GPIO event pin 15 */ + +/* GPIO output pin source definitions */ +#define GPIO_PIN_SOURCE_0 ((uint8_t)0x00U) /*!< GPIO pin source 0 */ +#define GPIO_PIN_SOURCE_1 ((uint8_t)0x01U) /*!< GPIO pin source 1 */ +#define GPIO_PIN_SOURCE_2 ((uint8_t)0x02U) /*!< GPIO pin source 2 */ +#define GPIO_PIN_SOURCE_3 ((uint8_t)0x03U) /*!< GPIO pin source 3 */ +#define GPIO_PIN_SOURCE_4 ((uint8_t)0x04U) /*!< GPIO pin source 4 */ +#define GPIO_PIN_SOURCE_5 ((uint8_t)0x05U) /*!< GPIO pin source 5 */ +#define GPIO_PIN_SOURCE_6 ((uint8_t)0x06U) /*!< GPIO pin source 6 */ +#define GPIO_PIN_SOURCE_7 ((uint8_t)0x07U) /*!< GPIO pin source 7 */ +#define GPIO_PIN_SOURCE_8 ((uint8_t)0x08U) /*!< GPIO pin source 8 */ +#define GPIO_PIN_SOURCE_9 ((uint8_t)0x09U) /*!< GPIO pin source 9 */ +#define GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU) /*!< GPIO pin source 10 */ +#define GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU) /*!< GPIO pin source 11 */ +#define GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU) /*!< GPIO pin source 12 */ +#define GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU) /*!< GPIO pin source 13 */ +#define GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU) /*!< GPIO pin source 14 */ +#define GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU) /*!< GPIO pin source 15 */ + +/* GPIO pin definitions */ +#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ +#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ +#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ +#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ +#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ +#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ +#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ +#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ +#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ +#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ +#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ +#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ +#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ +#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ +#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ +#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ +#define GPIO_PIN_ALL BITS(0, 15) /*!< GPIO pin all */ + +/* GPIO remap definitions */ +#define GPIO_SPI0_REMAP ((uint32_t)0x00000001U) /*!< SPI0 remapping */ +#define GPIO_I2C0_REMAP ((uint32_t)0x00000002U) /*!< I2C0 remapping */ +#define GPIO_USART0_REMAP ((uint32_t)0x00000004U) /*!< USART0 remapping */ +#define GPIO_USART1_REMAP ((uint32_t)0x00000008U) /*!< USART1 remapping */ +#define GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140010U) /*!< USART2 partial remapping */ +#define GPIO_USART2_FULL_REMAP ((uint32_t)0x00140030U) /*!< USART2 full remapping */ +#define GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160040U) /*!< TIMER0 partial remapping */ +#define GPIO_TIMER0_FULL_REMAP ((uint32_t)0x001600C0U) /*!< TIMER0 full remapping */ +#define GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180100U) /*!< TIMER1 partial remapping */ +#define GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180200U) /*!< TIMER1 partial remapping */ +#define GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180300U) /*!< TIMER1 full remapping */ +#define GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0800U) /*!< TIMER2 partial remapping */ +#define GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0C00U) /*!< TIMER2 full remapping */ +#define GPIO_TIMER3_REMAP ((uint32_t)0x00001000U) /*!< TIMER3 remapping */ +#define GPIO_CAN0_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN0 partial remapping */ +#define GPIO_CAN0_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN0 full remapping */ +#define GPIO_PD01_REMAP ((uint32_t)0x00008000U) /*!< PD01 remapping */ +#define GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200001U) /*!< TIMER4 channel3 internal remapping */ +#define GPIO_CAN1_REMAP ((uint32_t)0x00200040U) /*!< CAN1 remapping */ +#define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300100U) /*!< JTAG-DP,but without NJTRST */ +#define GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300200U) /*!< JTAG-DP disabled */ +#define GPIO_SPI2_REMAP ((uint32_t)0x00201100U) /*!< SPI2 remapping */ +#define GPIO_TIMER1ITI1_REMAP ((uint32_t)0x00202000U) /*!< TIMER1 internal trigger 1 remapping */ +#define GPIO_EXMC_NADV_REMAP ((uint32_t)0x80000400U) /*!< EXMC_NADV connect/disconnect */ + +/* function declarations */ +/* reset GPIO port */ +void gpio_deinit(uint32_t gpio_periph); +/* reset alternate function I/O(AFIO) */ +void gpio_afio_deinit(void); +/* GPIO parameter initialization */ +void gpio_init(uint32_t gpio_periph,uint32_t mode,uint32_t speed,uint32_t pin); + +/* set GPIO pin bit */ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); +/* reset GPIO pin bit */ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); +/* write data to the specified GPIO pin */ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); +/* write data to the specified GPIO port */ +void gpio_port_write(uint32_t gpio_periph, uint16_t data); + +/* get GPIO pin input status */ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port input status */ +uint16_t gpio_input_port_get(uint32_t gpio_periph); +/* get GPIO pin output status */ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port output status */ +uint16_t gpio_output_port_get(uint32_t gpio_periph); + +/* configure GPIO pin remap */ +void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue); + +/* select GPIO pin exti sources */ +void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin); +/* configure GPIO pin event output */ +void gpio_event_output_config(uint8_t output_port, uint8_t output_pin); +/* enable GPIO pin event output */ +void gpio_event_output_enable(void); +/* disable GPIO pin event output */ +void gpio_event_output_disable(void); + +/* lock GPIO pin bit */ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); + +#endif /* GD32VF103_GPIO_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h new file mode 100644 index 0000000..c06a3e5 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h @@ -0,0 +1,343 @@ +/*! + \file gd32vf103_i2c.h + \brief definitions for the I2C + + \version 2019-06-05, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_I2C_H +#define GD32VF103_I2C_H + +#include "gd32vf103.h" + +/* I2Cx(x=0,1) definitions */ +#define I2C0 I2C_BASE /*!< I2C0 base address */ +#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ + +/* registers definitions */ +#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ +#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ +#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ +#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ +#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ +#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ +#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ +#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */ +#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ +#define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x90U) /*!< I2C fast-mode-plus configure register */ +/* bits definitions */ +/* I2Cx_CTL0 */ +#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ +#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ +#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ +#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ +#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ +#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ +#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ +#define I2C_CTL0_START BIT(8) /*!< start generation */ +#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ +#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ +#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ +#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ +#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ +#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ + +/* I2Cx_CTL1 */ +#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ +#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ +#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ +#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ +#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ +#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ + +/* I2Cx_SADDR0 */ +#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ +#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ + +/* I2Cx_SADDR1 */ +#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ +#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ + +/* I2Cx_DATA */ +#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ + +/* I2Cx_STAT0 */ +#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ +#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ +#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ +#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ +#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ +#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ +#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ +#define I2C_STAT0_BERR BIT(8) /*!< bus error */ +#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ +#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ +#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ +#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ +#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ +#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ + +/* I2Cx_STAT1 */ +#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ +#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ +#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ +#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ +#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ +#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ +#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ +#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ + +/* I2Cx_CKCFG */ +#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ +#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ +#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ + +/* I2Cx_RT */ +#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ + +/* I2Cx_FMPCFG */ +#define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */ + +/* constants definitions */ +/* define the I2C bit position and its register index offset */ +#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) +#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) +#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) + +/* register offset */ +#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */ +#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */ +#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */ + +/* I2C flags */ +typedef enum { + /* flags in STAT0 register */ + I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ + I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ + I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ + I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ + I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */ + I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ + I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ + I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ + I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ + I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ + I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ + I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ + I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ + /* flags in STAT1 register */ + I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ + I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ + I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ + I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ + I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ + I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ + I2C_FLAG_DUMODF = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ +} i2c_flag_enum; + +/* I2C interrupt flags */ +typedef enum { + /* interrupt flags in CTL1 register */ + I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ + I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ + I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ + I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ + I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ + I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ + I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ + I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ + I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ + I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ + I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ + I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ + I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ +} i2c_interrupt_flag_enum; + +/* I2C interrupt enable or disable */ +typedef enum { + /* interrupt in CTL1 register */ + I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ + I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ + I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ +} i2c_interrupt_enum; + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ +#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ +#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ + +/* I2C transfer direction */ +#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ +#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ + +/* whether or not to send an ACK */ +#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ +#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ + +/* I2C POAP position*/ +#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ +#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ + +/* I2C dual-address mode switch */ +#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */ +#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */ + +/* whether or not to stretch SCL low */ +#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */ +#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is disabled */ + +/* whether or not to response to a general call */ +#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ +#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ + +/* software reset I2C */ +#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ +#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ + +/* I2C DMA mode configure */ +/* DMA mode switch */ +#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ +#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ + +/* flag indicating DMA last transfer */ +#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ +#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ + +/* I2C PEC configure */ +/* PEC enable */ +#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ +#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ + +/* PEC transfer */ +#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ +#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ + +/* I2C SMBus configure */ +/* issue or not alert through SMBA pin */ +#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ +#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ + +/* ARP protocol in SMBus switch */ +#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */ +#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ + +/* transmit I2C data */ +#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* receive I2C data */ +#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* I2C duty cycle in fast mode */ +#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */ + +/* address mode for the I2C slave */ +#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ +#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ + +/* function declarations */ +/* reset I2C */ +void i2c_deinit(uint32_t i2c_periph); +/* configure I2C clock */ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); +/* configure I2C address */ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode,uint32_t addformat, uint32_t addr); +/* SMBus type selection */ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); +/* whether or not to send an ACK */ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); +/* configure I2C POAP position */ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); +/* master sends slave address */ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr,uint32_t trandirection); +/* enable dual-address mode */ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr); +/* disable dual-address mode */ +void i2c_dualaddr_disable(uint32_t i2c_periph); +/* enable I2C */ +void i2c_enable(uint32_t i2c_periph); +/* disable I2C */ +void i2c_disable(uint32_t i2c_periph); + +/* generate a START condition on I2C bus */ +void i2c_start_on_bus(uint32_t i2c_periph); +/* generate a STOP condition on I2C bus */ +void i2c_stop_on_bus(uint32_t i2c_periph); +/* I2C transmit data function */ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); +/* I2C receive data function */ +uint8_t i2c_data_receive(uint32_t i2c_periph); +/* enable I2C DMA mode */ +void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); +/* configure whether next DMA EOT is DMA last transfer or not */ +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); +/* whether to stretch SCL low when data is not ready in slave mode */ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); +/* whether or not to response to a general call */ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); +/* software reset I2C */ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); + +/* I2C PEC calculation on or off */ +void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); +/* I2C whether to transfer PEC value */ +void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); +/* packet error checking value */ +uint8_t i2c_pec_value_get(uint32_t i2c_periph); +/* I2C issue alert through SMBA pin */ +void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); +/* I2C ARP protocol in SMBus switch */ +void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); + +/* check I2C flag is set or not */ +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); +/* clear I2C flag */ +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); +/* enable I2C interrupt */ +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* disable I2C interrupt */ +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* check I2C interrupt flag */ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag); +/* clear I2C interrupt flag */ +void i2c_interrupt_flag_clear(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag); + +#endif /* GD32VF103_I2C_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h new file mode 100644 index 0000000..bb36512 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h @@ -0,0 +1,125 @@ +/*! + \file gd32vf103_pmu.h + \brief definitions for the PMU + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_PMU_H +#define GD32VF103_PMU_H + +#include "gd32vf103.h" + +/* PMU definitions */ +#define PMU PMU_BASE /*!< PMU base address */ + +/* registers definitions */ +#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ +#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ + +/* bits definitions */ +/* PMU_CTL */ +#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ +#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ +#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ +#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ +#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ +#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ +#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ + +/* PMU_CS */ +#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ +#define PMU_CS_STBF BIT(1) /*!< standby flag */ +#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ +#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ + +/* constants definitions */ +/* PMU low voltage detector threshold definitions */ +#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5)) +#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */ +#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ +#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ +#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.5V */ +#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.6V */ +#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.7V */ +#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 2.8V */ +#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 2.9V */ + +/* PMU flag definitions */ +#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ +#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ +#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ + +/* PMU ldo definitions */ +#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ +#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ + +/* PMU flag reset definitions */ +#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ +#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ + +/* PMU command constants definitions */ +#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ +#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ + +/* function declarations */ +/* reset PMU registers */ +void pmu_deinit(void); + +/* select low voltage detector threshold */ +void pmu_lvd_select(uint32_t lvdt_n); +/* disable PMU lvd */ +void pmu_lvd_disable(void); + +/* set PMU mode */ +/* PMU work at sleep mode */ +void pmu_to_sleepmode(uint8_t sleepmodecmd); +/* PMU work at deepsleep mode */ +void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); +/* PMU work at standby mode */ +void pmu_to_standbymode(uint8_t standbymodecmd); +/* enable PMU wakeup pin */ +void pmu_wakeup_pin_enable(void); +/* disable PMU wakeup pin */ +void pmu_wakeup_pin_disable(void); + +/* backup related functions */ +/* enable write access to the registers in backup domain */ +void pmu_backup_write_enable(void); +/* disable write access to the registers in backup domain */ +void pmu_backup_write_disable(void); + +/* flag functions */ +/* get flag state */ +FlagStatus pmu_flag_get(uint32_t flag); +/* clear flag bit */ +void pmu_flag_clear(uint32_t flag_reset); + +#endif /* GD32VF103_PMU_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h new file mode 100644 index 0000000..c20e1a0 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h @@ -0,0 +1,720 @@ +/*! + \file gd32vf103_rcu.h + \brief definitions for the RCU + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_RCU_H +#define GD32VF103_RCU_H + +#include "gd32vf103.h" + +/* RCU definitions */ +#define RCU RCU_BASE + +/* registers definitions */ + +#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ +#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ +#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ +#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ +#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ +#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */ +#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ +#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ +#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ +#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ +#define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */ +#define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ +#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ + + +/* bits definitions */ +/* RCU_CTL */ +#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ +#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ +#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ +#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ +#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ +#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ +#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ +#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ +#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ +#define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */ +#define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization flag */ +#define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */ +#define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ + + +#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ +#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ +#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ +#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ +#define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ +#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ +#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ +#define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ +#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ +#define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ + +/* RCU_INT */ +#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ +#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ +#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ +#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ +#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ +#define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt flag */ +#define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt flag */ +#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ +#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ +#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ +#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ +#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ +#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ +#define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt enable */ +#define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt enable */ +#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ +#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ +#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ +#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ +#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ +#define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt clear */ +#define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt clear */ +#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ + +/* RCU_APB2RST */ +#define RCU_APB2RST_AFRST BIT(0) /*!< alternate function I/O reset */ +#define RCU_APB2RST_PARST BIT(2) /*!< GPIO port A reset */ +#define RCU_APB2RST_PBRST BIT(3) /*!< GPIO port B reset */ +#define RCU_APB2RST_PCRST BIT(4) /*!< GPIO port C reset */ +#define RCU_APB2RST_PDRST BIT(5) /*!< GPIO port D reset */ +#define RCU_APB2RST_PERST BIT(6) /*!< GPIO port E reset */ +#define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */ +#define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */ +#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ +#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ +#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ + +/* RCU_APB1RST */ +#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ +#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ +#define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ +#define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */ +#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ +#define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ + +#define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ +#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ +#define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ +#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ +#define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ +#define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ +#define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ +#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ +#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ +#define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ +#define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ +#define RCU_APB1RST_BKPIRST BIT(27) /*!< backup interface reset */ +#define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ +#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ + +/* RCU_AHBEN */ +#define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */ +#define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */ +#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */ +#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */ +#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ +#define RCU_AHBEN_EXMCEN BIT(8) /*!< EXMC clock enable */ +#define RCU_AHBEN_USBFSEN BIT(12) /*!< USBFS clock enable */ + +/* RCU_APB2EN */ +#define RCU_APB2EN_AFEN BIT(0) /*!< alternate function IO clock enable */ +#define RCU_APB2EN_PAEN BIT(2) /*!< GPIO port A clock enable */ +#define RCU_APB2EN_PBEN BIT(3) /*!< GPIO port B clock enable */ +#define RCU_APB2EN_PCEN BIT(4) /*!< GPIO port C clock enable */ +#define RCU_APB2EN_PDEN BIT(5) /*!< GPIO port D clock enable */ +#define RCU_APB2EN_PEEN BIT(6) /*!< GPIO port E clock enable */ +#define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */ +#define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */ +#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */ +#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ +#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ + +/* RCU_APB1EN */ +#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ +#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ +#define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ +#define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */ +#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ +#define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ +#define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ +#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ +#define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ +#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ +#define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ +#define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ +#define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ +#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ +#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ +#define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ +#define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ +#define RCU_APB1EN_BKPIEN BIT(27) /*!< backup interface clock enable */ +#define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ +#define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ + +/* RCU_BDCTL */ +#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ +#define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ +#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ +#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ +#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ +#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ + +/* RCU_RSTSCK */ +#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ +#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */ +#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ +#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ +#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ +#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ +#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ +#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ +#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ + +/* RCU_AHBRST */ +#define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ + +/* RCU_CFG1 */ +#define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ +#define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ +#define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ +#define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ +#define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ +#define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ +#define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ + +/* RCU_DSV */ +#define RCU_DSV_DSLPVS BITS(0,1) /*!< deep-sleep mode voltage select */ + +/* constants definitions */ +/* define the peripheral clock enable bit position and its register index offset */ +#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) +#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +/* register offset */ +/* peripherals enable */ +#define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */ +#define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */ +#define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */ + +/* peripherals reset */ +#define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ +#define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */ +#define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */ +#define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */ + +/* clock control */ +#define CTL_REG_OFFSET 0x00U /*!< control register offset */ +#define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */ + +/* clock stabilization and stuck interrupt */ +#define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */ + +/* configuration register */ +#define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */ +#define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */ + +/* peripheral clock enable */ +typedef enum { + /* AHB peripherals */ + RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */ + RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */ + RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */ + RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */ + RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */ + /* APB1 peripherals */ + RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ + RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ + RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ + RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */ + RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ + RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ + RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ + RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ + RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ + RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ + RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ + RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ + RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ + RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ + RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ + RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ + RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ + RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */ + RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ + RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ + RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ + /* APB2 peripherals */ + RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */ + RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */ + RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */ + RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */ + RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */ + RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */ + RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */ + RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */ + RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */ + RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ + RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */ +} rcu_periph_enum; + +/* peripheral clock enable when sleep mode*/ +typedef enum { +/* AHB peripherals */ + RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */ + RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */ +} rcu_periph_sleep_enum; + +/* peripherals reset */ +typedef enum { + /* AHB peripherals */ + RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */ + /* APB1 peripherals */ + RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ + RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ + RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ + RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */ + RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ + RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ + RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ + RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ + RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ + RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ + RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ + RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ + RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ + RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ + RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ + RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ + RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ + RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */ + RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ + RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ + /* APB2 peripherals */ + RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */ + RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */ + RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */ + RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ + RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */ + RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */ + RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */ + RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ + RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */ + RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ + RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */ +} rcu_periph_reset_enum; + +/* clock stabilization and peripheral reset flags */ +typedef enum { + /* clock stabilization flags */ + RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */ + RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ + RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ + RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */ + RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */ + RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ + RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */ + /* reset source flags */ + RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */ + RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ + RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */ + RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ + RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ + RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */ +} rcu_flag_enum; + +/* clock stabilization and ckm interrupt flags */ +typedef enum { + RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ + RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ + RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ + RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ + RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ + RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */ + RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */ + RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ +} rcu_int_flag_enum; + +/* clock stabilization and stuck interrupt flags clear */ +typedef enum { + RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */ + RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */ + RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ + RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */ + RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */ + RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ +} rcu_int_flag_clear_enum; + +/* clock stabilization interrupt enable or disable */ +typedef enum { + RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */ + RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ + RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ + RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ + RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ + RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */ + RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */ +} rcu_int_enum; + +/* oscillator types */ +typedef enum { + RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ + RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ + RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ + RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */ + RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ + RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */ + RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */ +} rcu_osci_type_enum; + +/* rcu clock frequency */ +typedef enum { + CK_SYS = 0, /*!< system clock */ + CK_AHB, /*!< AHB clock */ + CK_APB1, /*!< APB1 clock */ + CK_APB2, /*!< APB2 clock */ +} rcu_clock_freq_enum; + +/* RCU_CFG0 register bit define */ +/* system clock source select */ +#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ +#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ +#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ + +/* system clock source select status */ +#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ +#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ +#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ + +/* AHB prescaler selection */ +#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ +#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ +#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ +#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ +#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ +#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ +#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ +#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ +#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ + +/* APB1 prescaler selection */ +#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) +#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ +#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ +#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ +#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ +#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ + +/* APB2 prescaler selection */ +#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) +#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ +#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ +#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ +#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ +#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ + +/* ADC prescaler select */ +#define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U) /*!< ADC prescaler select CK_APB2/2 */ +#define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U) /*!< ADC prescaler select CK_APB2/4 */ +#define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U) /*!< ADC prescaler select CK_APB2/6 */ +#define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U) /*!< ADC prescaler select CK_APB2/8 */ +#define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U) /*!< ADC prescaler select CK_APB2/12 */ +#define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U) /*!< ADC prescaler select CK_APB2/16 */ + +/* PLL clock source selection */ +#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock selected as source clock of PLL */ +#define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL /*!< HXTAL clock selected as source clock of PLL */ + +/* PLL clock multiplication factor */ +#define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */ + +#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) +#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ +#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ +#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ +#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ +#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ +#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ +#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ +#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ +#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ +#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ +#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ +#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ +#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ +#define RCU_PLL_MUL6_5 CFG0_PLLMF(13) /*!< PLL source clock multiply by 6.5 */ +#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ +#define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ +#define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ +#define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ +#define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ +#define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ +#define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ +#define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ +#define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ +#define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ +#define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ +#define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ +#define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ +#define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ +#define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ +#define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ +#define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ + +/* USBFS prescaler select */ +#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) +#define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBFS prescaler select CK_PLL/1.5 */ +#define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBFS prescaler select CK_PLL/1 */ +#define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBFS prescaler select CK_PLL/2.5 */ +#define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBFS prescaler select CK_PLL/2 */ + +/* CKOUT0 clock source selection */ +#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) +#define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ +#define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ +#define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ +#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< high speed crystal oscillator clock (HXTAL) selected */ +#define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_PLL/2 clock selected */ +#define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8) /*!< CK_PLL1 clock selected */ +#define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9) /*!< CK_PLL2/2 clock selected */ +#define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10) /*!< EXT1 selected */ +#define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */ + +/* RTC clock entry selection */ +#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ +#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ +#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ +#define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ + +/* PREDV0 division factor */ +#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) +#define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ +#define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ +#define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ +#define RCU_PREDV0_DIV4 CFG1_PREDV0(3) /*!< PREDV0 input source clock divided by 4 */ +#define RCU_PREDV0_DIV5 CFG1_PREDV0(4) /*!< PREDV0 input source clock divided by 5 */ +#define RCU_PREDV0_DIV6 CFG1_PREDV0(5) /*!< PREDV0 input source clock divided by 6 */ +#define RCU_PREDV0_DIV7 CFG1_PREDV0(6) /*!< PREDV0 input source clock divided by 7 */ +#define RCU_PREDV0_DIV8 CFG1_PREDV0(7) /*!< PREDV0 input source clock divided by 8 */ +#define RCU_PREDV0_DIV9 CFG1_PREDV0(8) /*!< PREDV0 input source clock divided by 9 */ +#define RCU_PREDV0_DIV10 CFG1_PREDV0(9) /*!< PREDV0 input source clock divided by 10 */ +#define RCU_PREDV0_DIV11 CFG1_PREDV0(10) /*!< PREDV0 input source clock divided by 11 */ +#define RCU_PREDV0_DIV12 CFG1_PREDV0(11) /*!< PREDV0 input source clock divided by 12 */ +#define RCU_PREDV0_DIV13 CFG1_PREDV0(12) /*!< PREDV0 input source clock divided by 13 */ +#define RCU_PREDV0_DIV14 CFG1_PREDV0(13) /*!< PREDV0 input source clock divided by 14 */ +#define RCU_PREDV0_DIV15 CFG1_PREDV0(14) /*!< PREDV0 input source clock divided by 15 */ +#define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ + +/* PREDV1 division factor */ +#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ +#define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ +#define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ +#define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input source clock divided by 4 */ +#define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input source clock divided by 5 */ +#define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input source clock divided by 6 */ +#define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input source clock divided by 7 */ +#define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input source clock divided by 8 */ +#define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input source clock divided by 9 */ +#define RCU_PREDV1_DIV10 CFG1_PREDV1(9) /*!< PREDV1 input source clock divided by 10 */ +#define RCU_PREDV1_DIV11 CFG1_PREDV1(10) /*!< PREDV1 input source clock divided by 11 */ +#define RCU_PREDV1_DIV12 CFG1_PREDV1(11) /*!< PREDV1 input source clock divided by 12 */ +#define RCU_PREDV1_DIV13 CFG1_PREDV1(12) /*!< PREDV1 input source clock divided by 13 */ +#define RCU_PREDV1_DIV14 CFG1_PREDV1(13) /*!< PREDV1 input source clock divided by 14 */ +#define RCU_PREDV1_DIV15 CFG1_PREDV1(14) /*!< PREDV1 input source clock divided by 15 */ +#define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ + +/* PLL1 clock multiplication factor */ +#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) +#define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ +#define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ +#define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ +#define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock multiply by 11 */ +#define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock multiply by 12 */ +#define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock multiply by 13 */ +#define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock multiply by 14 */ +#define RCU_PLL1_MUL15 CFG1_PLL1MF(13) /*!< PLL1 source clock multiply by 15 */ +#define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock multiply by 16 */ +#define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ + +/* PLL2 clock multiplication factor */ +#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) +#define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ +#define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ +#define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ +#define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock multiply by 11 */ +#define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock multiply by 12 */ +#define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock multiply by 13 */ +#define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock multiply by 14 */ +#define RCU_PLL2_MUL15 CFG1_PLL2MF(13) /*!< PLL2 source clock multiply by 15 */ +#define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */ +#define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */ + + +/* PREDV0 input clock source selection */ +#define RCU_PREDV0SRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PREDV0 input source clock */ +#define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */ + +/* I2S1 clock source selection */ +#define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S1 source clock */ +#define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL /*!< (CK_PLL2 x 2) selected as I2S1 source clock */ + +/* I2S2 clock source selection */ +#define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */ +#define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */ + + +/* deep-sleep mode voltage */ +#define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1) /*!< core voltage is 1.1V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3) /*!< core voltage is 0.9V in deep-sleep mode */ + +/* function declarations */ +/* initialization, peripheral clock enable/disable functions */ +/* deinitialize the RCU */ +void rcu_deinit(void); +/* enable the peripherals clock */ +void rcu_periph_clock_enable(rcu_periph_enum periph); +/* disable the peripherals clock */ +void rcu_periph_clock_disable(rcu_periph_enum periph); +/* enable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); +/* disable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); +/* reset the peripherals */ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); +/* disable reset the peripheral */ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); +/* reset the BKP domain */ +void rcu_bkp_reset_enable(void); +/* disable the BKP domain reset */ +void rcu_bkp_reset_disable(void); + +/* clock configuration functions */ +/* configure the system clock source */ +void rcu_system_clock_source_config(uint32_t ck_sys); +/* get the system clock source */ +uint32_t rcu_system_clock_source_get(void); +/* configure the AHB prescaler selection */ +void rcu_ahb_clock_config(uint32_t ck_ahb); +/* configure the APB1 prescaler selection */ +void rcu_apb1_clock_config(uint32_t ck_apb1); +/* configure the APB2 prescaler selection */ +void rcu_apb2_clock_config(uint32_t ck_apb2); +/* configure the CK_OUT0 clock source and divider */ +void rcu_ckout0_config(uint32_t ckout0_src); +/* configure the PLL clock source selection and PLL multiply factor */ +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); + +/* configure the PREDV0 division factor and clock source */ +void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div); +/* configure the PREDV1 division factor */ +void rcu_predv1_config(uint32_t predv1_div); +/* configure the PLL1 clock */ +void rcu_pll1_config(uint32_t pll_mul); +/* configure the PLL2 clock */ +void rcu_pll2_config(uint32_t pll_mul); + +/* peripheral clock configuration functions */ +/* configure the ADC division factor */ +void rcu_adc_clock_config(uint32_t adc_psc); +/* configure the USBD/USBFS prescaler factor */ +void rcu_usb_clock_config(uint32_t usb_psc); +/* configure the RTC clock source selection */ +void rcu_rtc_clock_config(uint32_t rtc_clock_source); + +/* configure the I2S1 clock source selection */ +void rcu_i2s1_clock_config(uint32_t i2s_clock_source); +/* configure the I2S2 clock source selection */ +void rcu_i2s2_clock_config(uint32_t i2s_clock_source); + +/* interrupt & flag functions */ +/* get the clock stabilization and periphral reset flags */ +FlagStatus rcu_flag_get(rcu_flag_enum flag); +/* clear the reset flag */ +void rcu_all_reset_flag_clear(void); +/* get the clock stabilization interrupt and ckm flags */ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); +/* clear the interrupt flags */ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); +/* enable the stabilization interrupt */ +void rcu_interrupt_enable(rcu_int_enum stab_int); +/* disable the stabilization interrupt */ +void rcu_interrupt_disable(rcu_int_enum stab_int); + +/* oscillator configuration functions */ +/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); +/* turn on the oscillator */ +void rcu_osci_on(rcu_osci_type_enum osci); +/* turn off the oscillator */ +void rcu_osci_off(rcu_osci_type_enum osci); +/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); +/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); +/* enable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_enable(void); +/* disable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_disable(void); + +/* set the IRC8M adjust value */ +void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval); +/* set the deep sleep mode voltage */ +void rcu_deepsleep_voltage_set(uint32_t dsvol); + +/* get the system clock, bus and peripheral clock frequency */ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); + +#endif /* GD32VF103_RCU_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h new file mode 100644 index 0000000..874c6bb --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h @@ -0,0 +1,148 @@ +/*! + \file gd32vf103_rtc.h + \brief definitions for the RTC + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_RTC_H +#define GD32VF103_RTC_H + +#include "gd32vf103.h" + +/* RTC definitions */ +#define RTC RTC_BASE + +/* registers definitions */ +#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */ +#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */ +#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */ +#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */ +#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */ +#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */ +#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */ +#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */ +#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */ +#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */ + +/* bits definitions */ +/* RTC_INTEN */ +#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */ +#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */ +#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */ + +/* RTC_CTL */ +#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */ +#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */ +#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */ +#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */ +#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */ +#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ + +/* RTC_PSCH */ +#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */ + +/* RTC_PSCL */ +#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */ + +/* RTC_DIVH */ +#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */ + +/* RTC_DIVL */ +#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */ + +/* RTC_CNTH */ +#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */ + +/* RTC_CNTL */ +#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */ + +/* RTC_ALRMH */ +#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */ + +/* RTC_ALRML */ +#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */ + +/* constants definitions */ +/* RTC interrupt enable or disable definitions */ +#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */ +#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */ +#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */ + +/* RTC interrupt flag definitions */ +#define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ +#define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ +#define RTC_INT_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ + +/* RTC flag definitions */ +#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ +#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ +#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ +#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */ +#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */ + +/* function declarations */ +/* initialization functions */ +/* enter RTC configuration mode */ +void rtc_configuration_mode_enter(void); +/* exit RTC configuration mode */ +void rtc_configuration_mode_exit(void); +/* set RTC counter value */ +void rtc_counter_set(uint32_t cnt); +/* set RTC prescaler value */ +void rtc_prescaler_set(uint32_t psc); + +/* operation functions */ +/* wait RTC last write operation finished flag set */ +void rtc_lwoff_wait(void); +/* wait RTC registers synchronized flag set */ +void rtc_register_sync_wait(void); +/* set RTC alarm value */ +void rtc_alarm_config(uint32_t alarm); +/* get RTC counter value */ +uint32_t rtc_counter_get(void); +/* get RTC divider value */ +uint32_t rtc_divider_get(void); + +/* flag & interrupt functions */ +/* get RTC flag status */ +FlagStatus rtc_flag_get(uint32_t flag); +/* clear RTC flag status */ +void rtc_flag_clear(uint32_t flag); +/* get RTC interrupt flag status */ +FlagStatus rtc_interrupt_flag_get(uint32_t flag); +/* clear RTC interrupt flag status */ +void rtc_interrupt_flag_clear(uint32_t flag); +/* enable RTC interrupt */ +void rtc_interrupt_enable(uint32_t interrupt); +/* disable RTC interrupt */ +void rtc_interrupt_disable(uint32_t interrupt); + +#endif /* GD32VF103_RTC_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h new file mode 100644 index 0000000..3ca09e2 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h @@ -0,0 +1,341 @@ +/*! + \file gd32vf103_spi.h + \brief definitions for the SPI + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_SPI_H +#define GD32VF103_SPI_H + +#include "gd32vf103.h" + +/* SPIx(x=0,1,2) definitions */ +#define SPI0 (SPI_BASE + 0x0000F800U) +#define SPI1 SPI_BASE +#define SPI2 (SPI_BASE + 0x00000400U) + +/* SPI registers definitions */ +#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ +#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ +#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ +#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ +#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ +#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ +#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ +#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ +#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ + +/* bits definitions */ +/* SPI_CTL0 */ +#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ +#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ +#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ +#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ +#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ +#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ +#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ +#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ +#define SPI_CTL0_RO BIT(10) /*!< receive only */ +#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ +#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ +#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ +#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ +#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ + +/* SPI_CTL1 */ +#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ +#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ +#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ +#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */ +#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */ +#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ +#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ +#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ + +/* SPI_STAT */ +#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ +#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ +#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ +#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ +#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ +#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ +#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ +#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ +#define SPI_STAT_FERR BIT(8) /*!< format error bit */ + +/* SPI_DATA */ +#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ + +/* SPI_CRCPOLY */ +#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */ + +/* SPI_RCRC */ +#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */ + +/* SPI_TCRC */ +#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */ + +/* SPI_I2SCTL */ +#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ +#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ +#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ +#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ +#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ +#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ +#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ +#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ + +/* SPI_I2SPSC */ +#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ +#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ +#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ + +/* constants definitions */ +/* SPI and I2S parameter struct definitions */ +typedef struct +{ + uint32_t device_mode; /*!< SPI master or slave */ + uint32_t trans_mode; /*!< SPI transtype */ + uint32_t frame_size; /*!< SPI frame size */ + uint32_t nss; /*!< SPI NSS control by handware or software */ + uint32_t endian; /*!< SPI big endian or little endian */ + uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ + uint32_t prescale; /*!< SPI prescale factor */ +}spi_parameter_struct; + +/* SPI mode definitions */ +#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ +#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ + +/* SPI bidirectional transfer direction */ +#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ +#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ + +/* SPI transmit type */ +#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ +#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ +#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ +#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ + +/* SPI frame size */ +#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ +#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ + +/* SPI NSS control mode */ +#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by software */ +#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ + +/* SPI transmit way */ +#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ +#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ + +/* SPI clock phase and polarity */ +#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ +#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ +#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ +#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ + +/* SPI clock prescale factor */ +#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ +#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ +#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ +#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ +#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ +#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ +#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ +#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ + +/* I2S audio sample rate */ +#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ +#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ +#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ +#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ +#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ +#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ +#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ +#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ +#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ + +/* I2S frame format */ +#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) +#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ +#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ + +/* I2S master clock output */ +#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ +#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ + +/* I2S operation mode */ +#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ +#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ +#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ +#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ + +/* I2S standard */ +#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ +#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ +#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ +#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ +#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ + +/* I2S clock polarity */ +#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ +#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ + +/* SPI DMA constants definitions */ +#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ +#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ + +/* SPI CRC constants definitions */ +#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ +#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ + +/* SPI/I2S interrupt enable/disable constants definitions */ +#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ +#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ +#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ + +/* SPI/I2S interrupt flag constants definitions */ +#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ +#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ +#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ +#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ +#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ + +/* SPI/I2S flag definitions */ +#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ +#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ +#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ +#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ +#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ +#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ +#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ +#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ + +/* function declarations */ +/* SPI/I2S deinitialization and initialization functions */ +/* reset SPI and I2S */ +void spi_i2s_deinit(uint32_t spi_periph); +/* initialize the parameters of SPI struct with the default values */ +void spi_struct_para_init(spi_parameter_struct* spi_struct); +/* initialize SPI parameter */ +void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct); +/* enable SPI */ +void spi_enable(uint32_t spi_periph); +/* disable SPI */ +void spi_disable(uint32_t spi_periph); + +/* initialize I2S parameter */ +void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl); +/* configure I2S prescaler */ +void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); +/* enable I2S */ +void i2s_enable(uint32_t spi_periph); +/* disable I2S */ +void i2s_disable(uint32_t spi_periph); + +/* NSS functions */ +/* enable SPI NSS output */ +void spi_nss_output_enable(uint32_t spi_periph); +/* disable SPI NSS output */ +void spi_nss_output_disable(uint32_t spi_periph); +/* SPI NSS pin high level in software mode */ +void spi_nss_internal_high(uint32_t spi_periph); +/* SPI NSS pin low level in software mode */ +void spi_nss_internal_low(uint32_t spi_periph); + +/* DMA communication */ +/* enable SPI DMA */ +void spi_dma_enable(uint32_t spi_periph, uint8_t dma); +/* disable SPI DMA */ +void spi_dma_disable(uint32_t spi_periph, uint8_t dma); + +/* normal mode communication */ +/* configure SPI/I2S data frame format */ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); +/* SPI transmit data */ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); +/* SPI receive data */ +uint16_t spi_i2s_data_receive(uint32_t spi_periph); +/* configure SPI bidirectional transfer direction */ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); + +/* SPI CRC functions */ +/* set SPI CRC polynomial */ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); +/* get SPI CRC polynomial */ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph); +/* turn on SPI CRC function */ +void spi_crc_on(uint32_t spi_periph); +/* turn off SPI CRC function */ +void spi_crc_off(uint32_t spi_periph); +/* SPI next data is CRC value */ +void spi_crc_next(uint32_t spi_periph); +/* get SPI CRC send value or receive value */ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); + +/* SPI TI mode functions */ +/* enable SPI TI mode */ +void spi_ti_mode_enable(uint32_t spi_periph); +/* disable SPI TI mode */ +void spi_ti_mode_disable(uint32_t spi_periph); + +/* SPI NSS pulse mode functions */ +/* enable SPI NSS pulse mode */ +void spi_nssp_mode_enable(uint32_t spi_periph); +/* disable SPI NSS pulse mode */ +void spi_nssp_mode_disable(uint32_t spi_periph); +/* flag and interrupt functions */ +/* enable SPI and I2S interrupt */ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); +/* disable SPI and I2S interrupt */ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); +/* get SPI and I2S interrupt status */ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); +/* get SPI and I2S flag status */ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); +/* clear SPI CRC error flag status */ +void spi_crc_error_clear(uint32_t spi_periph); + +#endif /* GD32VF103_SPI_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h new file mode 100644 index 0000000..ea2026e --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h @@ -0,0 +1,722 @@ +/*! + \file gd32vf103_timer.h + \brief definitions for the TIMER + + \version 2019-06-05, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_TIMER_H +#define GD32VF103_TIMER_H + +#include "gd32vf103.h" + +/* TIMERx(x=0..13) definitions */ +#define TIMER0 (TIMER_BASE + 0x00012C00U) +#define TIMER1 (TIMER_BASE + 0x00000000U) +#define TIMER2 (TIMER_BASE + 0x00000400U) +#define TIMER3 (TIMER_BASE + 0x00000800U) +#define TIMER4 (TIMER_BASE + 0x00000C00U) +#define TIMER5 (TIMER_BASE + 0x00001000U) +#define TIMER6 (TIMER_BASE + 0x00001400U) + +/* registers definitions */ +#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ +#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ +#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ +#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ +#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ +#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ +#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ +#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ +#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ +#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ +#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ +#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ +#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */ +#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ +#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ +#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ +#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ +#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER channel complementary protection register */ +#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ +#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ + +/* bits definitions */ +/* TIMER_CTL0 */ +#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ +#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ +#define TIMER_CTL0_UPS BIT(2) /*!< update source */ +#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ +#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ +#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ +#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ +#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ + +/* TIMER_CTL1 */ +#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ +#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ +#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ +#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ +#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ +#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ +#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ +#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ +#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ +#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ +#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ +#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ + +/* TIMER_SMCFG */ +#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ +#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ +#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ +#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ +#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ +#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ +#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ + +/* TIMER_DMAINTEN */ +#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ +#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ +#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ +#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ +#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ +#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 capture/compare DMA request enable */ +#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 capture/compare DMA request enable */ +#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 capture/compare DMA request enable */ +#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 capture/compare DMA request enable */ +#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ +#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ + +/* TIMER_INTF */ +#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ +#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ +#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ +#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ +#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ +#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ +#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ +#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ +#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 over capture flag */ +#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 over capture flag */ +#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 over capture flag */ +#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 over capture flag */ + +/* TIMER_SWEVG */ +#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ +#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ +#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ +#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ +#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ +#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ +#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ +#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ + +/* TIMER_CHCTL0 */ +/* output compare mode */ +#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ +#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ +#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ +#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare control */ +#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ +#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ +#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ +#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ +#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare control */ +#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ +#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ +#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ +#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ + +/* TIMER_CHCTL1 */ +/* output compare mode */ +#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ +#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ +#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ +#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare control */ +#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ +#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ +#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ +#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ +#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control */ +#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ +#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ +#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ +#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ + +/* TIMER_CHCTL2 */ +#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ +#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ +#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ +#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ +#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ +#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ +#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ +#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ +#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ +#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ +#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ +#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ +#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ +#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ + +/* TIMER_CNT */ +#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ + +/* TIMER_PSC */ +#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ + +/* TIMER_CAR */ +#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ + +/* TIMER_CREP */ +#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ + +/* TIMER_CH0CV */ +#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ + +/* TIMER_CH1CV */ +#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ + +/* TIMER_CH2CV */ +#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ + +/* TIMER_CH3CV */ +#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ + +/* TIMER_CCHP */ +#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ +#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ +#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ +#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ +#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ +#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ +#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ +#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ + +/* TIMER_DMACFG */ +#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ +#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ + +/* TIMER_DMATB */ +#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ + +/* constants definitions */ +/* TIMER init parameter struct definitions */ +typedef struct +{ + uint16_t prescaler; /*!< prescaler value */ + uint16_t alignedmode; /*!< aligned mode */ + uint16_t counterdirection; /*!< counter direction */ + uint32_t period; /*!< period value */ + uint16_t clockdivision; /*!< clock division value */ + uint8_t repetitioncounter; /*!< the counter repetition value */ +}timer_parameter_struct; + +/* break parameter struct definitions */ +typedef struct +{ + uint16_t runoffstate; /*!< run mode off-state */ + uint16_t ideloffstate; /*!< idle mode off-state */ + uint16_t deadtime; /*!< dead time */ + uint16_t breakpolarity; /*!< break polarity */ + uint16_t outputautostate; /*!< output automatic enable */ + uint16_t protectmode; /*!< complementary register protect control */ + uint16_t breakstate; /*!< break enable */ +}timer_break_parameter_struct; + +/* channel output parameter struct definitions */ +typedef struct +{ + uint16_t outputstate; /*!< channel output state */ + uint16_t outputnstate; /*!< channel complementary output state */ + uint16_t ocpolarity; /*!< channel output polarity */ + uint16_t ocnpolarity; /*!< channel complementary output polarity */ + uint16_t ocidlestate; /*!< idle state of channel output */ + uint16_t ocnidlestate; /*!< idle state of channel complementary output */ +}timer_oc_parameter_struct; + +/* channel input parameter struct definitions */ +typedef struct +{ + uint16_t icpolarity; /*!< channel input polarity */ + uint16_t icselection; /*!< channel input mode selection */ + uint16_t icprescaler; /*!< channel input capture prescaler */ + uint16_t icfilter; /*!< channel input capture filter control */ +}timer_ic_parameter_struct; + +/* TIMER interrupt enable or disable */ +#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ +#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ +#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ +#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ +#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ +#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ +#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ +#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ + +/* TIMER interrupt flag */ +#define TIMER_INT_FLAG_UP TIMER_INT_UP /*!< update interrupt */ +#define TIMER_INT_FLAG_CH0 TIMER_INT_CH0 /*!< channel 0 interrupt */ +#define TIMER_INT_FLAG_CH1 TIMER_INT_CH1 /*!< channel 1 interrupt */ +#define TIMER_INT_FLAG_CH2 TIMER_INT_CH2 /*!< channel 2 interrupt */ +#define TIMER_INT_FLAG_CH3 TIMER_INT_CH3 /*!< channel 3 interrupt */ +#define TIMER_INT_FLAG_CMT TIMER_INT_CMT /*!< channel commutation interrupt flag */ +#define TIMER_INT_FLAG_TRG TIMER_INT_TRG /*!< trigger interrupt */ +#define TIMER_INT_FLAG_BRK TIMER_INT_BRK + +/* TIMER flag */ +#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ +#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ +#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ +#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ +#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ +#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel control update flag */ +#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ +#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ +#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ +#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ +#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ +#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ + +/* TIMER DMA source enable */ +#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ +#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ +#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ +#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ +#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ +#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ +#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ + +/* channel DMA request source selection */ +#define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel n is sent when update event occurs */ +#define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */ + +/* DMA access base address */ +#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) +#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ +#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ +#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ +#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ +#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ +#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ +#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ +#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ +#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ +#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ +#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ +#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ +#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ +#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ +#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ +#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ +#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ +#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ +#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ + +/* DMA access burst length */ +#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) +#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ +#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ +#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ +#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ +#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ +#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ +#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ +#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ +#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ +#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ +#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ +#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ +#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ +#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ +#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ +#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ +#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ +#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ + +/* TIMER software event generation source */ +#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ +#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ +#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ +#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ +#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ + +/* center-aligned mode selection */ +#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) +#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ +#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ +#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ +#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ + +/* TIMER prescaler reload mode */ +#define TIMER_PSC_RELOAD_NOW TIMER_SWEVG_UPG /*!< the prescaler is loaded right now */ +#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000000U) /*!< the prescaler is loaded at the next update event */ + +/* count direction */ +#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ +#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ + +/* specify division ratio between TIMER clock and dead-time and sampling clock */ +#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ +#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ +#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ + +/* single pulse mode */ +#define TIMER_SP_MODE_SINGLE TIMER_CTL0_SPM /*!< single pulse mode */ +#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000000U) /*!< repetitive pulse mode */ + +/* update source */ +#define TIMER_UPDATE_SRC_REGULAR TIMER_CTL0_UPS /*!< update generate only by counter overflow/underflow */ +#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000000U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ + +/* run mode off-state configure */ +#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are disabled */ + + +/* idle mode off-state configure */ +#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals(CHx_O/CHx_ON) are disabled */ + +/* break input polarity */ +#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ +#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ + +/* output automatic enable */ +#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ +#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ + +/* complementary register protect control */ +#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ +#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ +#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ +#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ + +/* break input enable */ +#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ +#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ + +/* TIMER channel n(n=0,1,2,3) */ +#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4)) */ +#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4)) */ +#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4)) */ +#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4)) */ + +/* channel enable state */ +#define TIMER_CCX_ENABLE ((uint16_t)0x0001U) /*!< channel enable */ +#define TIMER_CCX_DISABLE ((uint16_t)0x0000U) /*!< channel disable */ + +/* channel complementary output enable state */ +#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ +#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ + +/* channel output polarity */ +#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ +#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ + +/* channel complementary output polarity */ +#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ +#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ + +/* idle state of channel output */ +#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ +#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ + +/* idle state of channel complementary output */ +#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ +#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ + +/* channel output compare mode */ +#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ +#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ +#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ +#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ +#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ +#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ +#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ +#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode */ + +/* channel output compare shadow enable */ +#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ +#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ + +/* channel output compare fast enable */ +#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ +#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ + +/* channel output compare clear enable */ +#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ +#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ + +/* channel control shadow register update control */ +#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers update by when CMTG bit is set */ +#define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ + +/* channel input capture polarity */ +#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ +#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ +#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ + +/* TIMER input capture selection */ +#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel n is configured as input and icy is mapped on CIy */ +#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel n is configured as input and icy is mapped on opposite input */ +#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel n is configured as input and icy is mapped on ITS */ + +/* channel input capture prescaler */ +#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ +#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ +#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4 */ +#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ + +/* trigger selection */ +#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ +#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ +#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ +#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ +#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ +#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ +#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ +#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< filtered external trigger input */ + +/* master mode control */ +#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ +#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ +#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ +#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channel 0 as trigger output TRGO */ +#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ + +/* slave mode control */ +#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) +#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ +#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ +#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ +#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ +#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ +#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ +#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ +#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ + +/* master slave mode selection */ +#define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */ +#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ + +/* external trigger prescaler */ +#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) +#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ +#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ +#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ +#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ + +/* external trigger polarity */ +#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ +#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ + +/* channel 0 trigger input selection */ +#define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */ +#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */ + +/* TIMERx(x=0..4) write CHxVAL register selection */ +#define TIMER_CHVSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< write CHxVAL register selection enable */ +#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ + +/* function declarations */ +/* TIMER timebase */ +/* deinit a timer */ +void timer_deinit(uint32_t timer_periph); +/* initialize TIMER init parameter struct */ +void timer_struct_para_init(timer_parameter_struct* initpara); +/* initialize TIMER counter */ +void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); +/* enable a timer */ +void timer_enable(uint32_t timer_periph); +/* disable a timer */ +void timer_disable(uint32_t timer_periph); +/* enable the auto reload shadow function */ +void timer_auto_reload_shadow_enable(uint32_t timer_periph); +/* disable the auto reload shadow function */ +void timer_auto_reload_shadow_disable(uint32_t timer_periph); +/* enable the update event */ +void timer_update_event_enable(uint32_t timer_periph); +/* disable the update event */ +void timer_update_event_disable(uint32_t timer_periph); +/* set TIMER counter alignment mode */ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); +/* set TIMER counter up direction */ +void timer_counter_up_direction(uint32_t timer_periph); +/* set TIMER counter down direction */ +void timer_counter_down_direction(uint32_t timer_periph); + +/* configure TIMER prescaler */ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload); +/* configure TIMER repetition register value */ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); +/* configure TIMER autoreload register value */ +void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload); +/* configure TIMER counter register value */ +void timer_counter_value_config(uint32_t timer_periph, uint16_t counter); +/* read TIMER counter value */ +uint32_t timer_counter_read(uint32_t timer_periph); +/* read TIMER prescaler value */ +uint16_t timer_prescaler_read(uint32_t timer_periph); +/* configure TIMER single pulse mode */ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); +/* configure TIMER update source */ +void timer_update_source_config(uint32_t timer_periph, uint32_t update); + +/* TIMER DMA and event */ +/* enable the TIMER DMA */ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma); +/* disable the TIMER DMA */ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma); +/* channel DMA request source selection */ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request); +/* configure the TIMER DMA transfer */ +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth); +/* software generate events */ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event); + +/* TIMER channel complementary protection */ +/* initialize TIMER break parameter struct */ +void timer_break_struct_para_init(timer_break_parameter_struct* breakpara); +/* configure TIMER break function */ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); +/* enable TIMER break function */ +void timer_break_enable(uint32_t timer_periph); +/* disable TIMER break function */ +void timer_break_disable(uint32_t timer_periph); +/* enable TIMER output automatic function */ +void timer_automatic_output_enable(uint32_t timer_periph); +/* disable TIMER output automatic function */ +void timer_automatic_output_disable(uint32_t timer_periph); +/* enable or disable TIMER primary output function */ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); +/* enable or disable channel capture/compare control shadow register */ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); +/* configure TIMER channel control shadow register update control */ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl); + +/* TIMER channel output */ +/* initialize TIMER channel output parameter struct */ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara); +/* configure TIMER channel output function */ +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara); +/* configure TIMER channel output compare mode */ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode); +/* configure TIMER channel output pulse value */ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); +/* configure TIMER channel output shadow function */ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); +/* configure TIMER channel output fast function */ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); +/* configure TIMER channel output clear function */ +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear); +/* configure TIMER channel output polarity */ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); +/* configure TIMER channel complementary output polarity */ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); +/* configure TIMER channel enable state */ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); +/* configure TIMER channel complementary output enable state */ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); + +/* TIMER channel input */ +/* initialize TIMER channel input parameter struct */ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara); +/* configure TIMER input capture parameter */ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); +/* configure TIMER channel input capture prescaler value */ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); +/* read TIMER channel capture compare register value */ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); +/* configure TIMER input pwm capture function */ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); +/* configure TIMER hall sensor mode */ +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); + +/* TIMER master and slave mode */ +/* select TIMER input trigger source */ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); +/* select TIMER master mode output trigger source */ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); +/* select TIMER slave mode */ +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode); +/* configure TIMER master slave mode */ +void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); +/* configure TIMER external trigger input */ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER quadrature decoder mode */ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); +/* configure TIMER internal clock mode */ +void timer_internal_clock_config(uint32_t timer_periph); +/* configure TIMER the internal trigger as external clock input */ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); +/* configure TIMER the external trigger as external clock input */ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 0 */ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 1 */ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* disable TIMER the external clock mode 1 */ +void timer_external_clock_mode1_disable(uint32_t timer_periph); + +/* TIMER interrupt and flag */ +/* enable the TIMER interrupt */ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); +/* disable the TIMER interrupt */ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); +/* get TIMER interrupt flag */ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); +/* clear TIMER interrupt flag */ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); +/* get TIMER flag */ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); +/* clear TIMER flag */ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag); + +#endif /* GD32VF103_TIMER_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h new file mode 100644 index 0000000..aadadfa --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h @@ -0,0 +1,375 @@ +/*! + \file gd32vf103_usart.h + \brief definitions for the USART + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + \version 2019-09-18, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_USART_H +#define GD32VF103_USART_H + +#include "gd32vf103.h" + +/* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */ +#define USART1 USART_BASE /*!< USART1 base address */ +#define USART2 (USART_BASE+(0x00000400U)) /*!< USART2 base address */ +#define UART3 (USART_BASE+(0x00000800U)) /*!< UART3 base address */ +#define UART4 (USART_BASE+(0x00000C00U)) /*!< UART4 base address */ +#define USART0 (USART_BASE+(0x0000F400U)) /*!< USART0 base address */ + +/* registers definitions */ +#define USART_STAT(usartx) REG32((usartx) + (0x00000000U)) /*!< USART status register */ +#define USART_DATA(usartx) REG32((usartx) + (0x00000004U)) /*!< USART data register */ +#define USART_BAUD(usartx) REG32((usartx) + (0x00000008U)) /*!< USART baud rate register */ +#define USART_CTL0(usartx) REG32((usartx) + (0x0000000CU)) /*!< USART control register 0 */ +#define USART_CTL1(usartx) REG32((usartx) + (0x00000010U)) /*!< USART control register 1 */ +#define USART_CTL2(usartx) REG32((usartx) + (0x00000014U)) /*!< USART control register 2 */ +#define USART_GP(usartx) REG32((usartx) + (0x00000018U)) /*!< USART guard time and prescaler register */ + +/* bits definitions */ +/* USARTx_STAT */ +#define USART_STAT_PERR BIT(0) /*!< parity error flag */ +#define USART_STAT_FERR BIT(1) /*!< frame error flag */ +#define USART_STAT_NERR BIT(2) /*!< noise error flag */ +#define USART_STAT_ORERR BIT(3) /*!< overrun error */ +#define USART_STAT_IDLEF BIT(4) /*!< IDLE frame detected flag */ +#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */ +#define USART_STAT_TC BIT(6) /*!< transmission complete */ +#define USART_STAT_TBE BIT(7) /*!< transmit data buffer empty */ +#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */ +#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */ + +/* USARTx_DATA */ +#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ + +/* USARTx_BAUD */ +#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ +#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ + +/* USARTx_CTL0 */ +#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ +#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ +#define USART_CTL0_REN BIT(2) /*!< receiver enable */ +#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ +#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ +#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ +#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ +#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ +#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ +#define USART_CTL0_PM BIT(9) /*!< parity mode */ +#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ +#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ +#define USART_CTL0_WL BIT(12) /*!< word length */ +#define USART_CTL0_UEN BIT(13) /*!< USART enable */ + +/* USARTx_CTL1 */ +#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ +#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ +#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ +#define USART_CTL1_CLEN BIT(8) /*!< CK length */ +#define USART_CTL1_CPH BIT(9) /*!< CK phase */ +#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ +#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ +#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ +#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ + +/* USARTx_CTL2 */ +#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ +#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ +#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ +#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ +#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ +#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ +#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ +#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ +#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ +#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ +#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ + +/* USARTx_GP */ +#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ +#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ + +/* constants definitions */ +/* define the USART bit position and its register index offset */ +#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & (0x0000FFFFU)) >> 6))) +#define USART_BIT_POS(val) ((uint32_t)(val) & (0x0000001FU)) +#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) +#define USART_BIT_POS2(val) (((uint32_t)(val) & (0x001F0000U)) >> 16) + +/* register offset */ +#define USART_STAT_REG_OFFSET (0x00000000U) /*!< STAT register offset */ +#define USART_CTL0_REG_OFFSET (0x0000000CU) /*!< CTL0 register offset */ +#define USART_CTL1_REG_OFFSET (0x00000010U) /*!< CTL1 register offset */ +#define USART_CTL2_REG_OFFSET (0x00000014U) /*!< CTL2 register offset */ + +/* USART flags */ +typedef enum +{ + /* flags in STAT register */ + USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */ + USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */ + USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */ + USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */ + USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */ + USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ + USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */ + USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */ + USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */ + USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */ +}usart_flag_enum; + +/* USART interrupt flags */ +typedef enum +{ + /* interrupt flags in CTL0 register */ + USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ + USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ + USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ + USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ + USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ + USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ + /* interrupt flags in CTL1 register */ + USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ + /* interrupt flags in CTL2 register */ + USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ + USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ + USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ + USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ +}usart_interrupt_flag_enum; + +/* USART interrupt enable or disable */ +typedef enum +{ + /* interrupt in CTL0 register */ + USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ + USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ + USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ + USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ + USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ + /* interrupt in CTL1 register */ + USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ + /* interrupt in CTL2 register */ + USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ + USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ +}usart_interrupt_enum; + +/* USART receiver configure */ +#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ +#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ + +/* USART transmitter configure */ +#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) +#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ +#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ + +/* USART parity bits definitions */ +#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) +#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ +#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ +#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ + +/* USART wakeup method in mute mode */ +#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ +#define USART_WM_ADDR CTL0_WM(1) /*!< address match */ + +/* USART word length definitions */ +#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) +#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ +#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ + +/* USART stop bits definitions */ +#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) +#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ +#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ +#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ +#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ + +/* USART LIN break frame length */ +#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) +#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ +#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ + +/* USART CK length */ +#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ +#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ + +/* USART clock phase */ +#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ +#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ + +/* USART clock polarity */ +#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) +#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ +#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ + +/* USART DMA request for receive configure */ +#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) +#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ +#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ + +/* USART DMA request for transmission configure */ +#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) +#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ +#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ + +/* USART RTS configure */ +#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ +#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ + +/* USART CTS configure */ +#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ +#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ + +/* USART IrDA low-power enable */ +#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ +#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ + +/* function declarations */ +/* initialization functions */ +/* reset USART */ +void usart_deinit(uint32_t usart_periph); +/* configure USART baud rate value */ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); +/* configure USART parity function */ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); +/* configure USART word length */ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); +/* configure USART stop bit length */ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); + +/* USART normal mode communication */ +/* enable USART */ +void usart_enable(uint32_t usart_periph); +/* disable USART */ +void usart_disable(uint32_t usart_periph); +/* configure USART transmitter */ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); +/* configure USART receiver */ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); +/* USART transmit data function */ +void usart_data_transmit(uint32_t usart_periph, uint32_t data); +/* USART receive data function */ +uint16_t usart_data_receive(uint32_t usart_periph); + +/* multi-processor communication */ +/* configure address of the USART */ +void usart_address_config(uint32_t usart_periph, uint8_t addr); +/* enable mute mode */ +void usart_mute_mode_enable(uint32_t usart_periph); +/* disable mute mode */ +void usart_mute_mode_disable(uint32_t usart_periph); +/* configure wakeup method in mute mode */ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); + +/* LIN mode communication */ +/* LIN mode enable */ +void usart_lin_mode_enable(uint32_t usart_periph); +/* LIN mode disable */ +void usart_lin_mode_disable(uint32_t usart_periph); +/* LIN break detection length */ +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); +/* send break frame */ +void usart_send_break(uint32_t usart_periph); + +/* half-duplex communication */ +/* half-duplex enable */ +void usart_halfduplex_enable(uint32_t usart_periph); +/* half-duplex disable */ +void usart_halfduplex_disable(uint32_t usart_periph); + +/* synchronous communication */ +/* clock enable */ +void usart_synchronous_clock_enable(uint32_t usart_periph); +/* clock disable */ +void usart_synchronous_clock_disable(uint32_t usart_periph); +/* configure usart synchronous mode parameters */ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); + +/* smartcard communication */ +/* guard time value configure in smartcard mode */ +void usart_guard_time_config(uint32_t usart_periph, uint32_t gaut); +/* smartcard mode enable */ +void usart_smartcard_mode_enable(uint32_t usart_periph); +/* smartcard mode disable */ +void usart_smartcard_mode_disable(uint32_t usart_periph); +/* NACK enable in smartcard mode */ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph); +/* NACK disable in smartcard mode */ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph); + +/* IrDA communication */ +/* enable IrDA mode */ +void usart_irda_mode_enable(uint32_t usart_periph); +/* disable IrDA mode */ +void usart_irda_mode_disable(uint32_t usart_periph); +/* configure the peripheral clock prescaler */ +void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); +/* configure IrDA low-power */ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); + +/* hardware flow communication */ +/* configure hardware flow control RTS */ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); +/* configure hardware flow control CTS */ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); + +/* configure USART DMA for reception */ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); +/* configure USART DMA for transmission */ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); + +/* flag functions */ +/* get flag in STAT register */ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); +/* clear flag in STAT register */ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); + +/* interrupt functions */ +/* enable USART interrupt */ +void usart_interrupt_enable(uint32_t usart_periph, uint32_t interrupt); +/* disable USART interrupt */ +void usart_interrupt_disable(uint32_t usart_periph, uint32_t interrupt); +/* get USART interrupt and flag status */ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag); +/* clear interrupt flag in STAT register */ +void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t int_flag); +#endif /* GD32VF103_USART_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h new file mode 100644 index 0000000..23f5905 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h @@ -0,0 +1,86 @@ +/*! + \file gd32vf103_wwdgt.h + \brief definitions for the WWDGT + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_WWDGT_H +#define GD32VF103_WWDGT_H + +#include "gd32vf103.h" + +/* WWDGT definitions */ +#define WWDGT WWDGT_BASE /*!< WWDGT base address */ + +/* registers definitions */ +#define WWDGT_CTL REG32((WWDGT) + 0x00000000U) /*!< WWDGT control register */ +#define WWDGT_CFG REG32((WWDGT) + 0x00000004U) /*!< WWDGT configuration register */ +#define WWDGT_STAT REG32((WWDGT) + 0x00000008U) /*!< WWDGT status register */ + +/* bits definitions */ +/* WWDGT_CTL */ +#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ +#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ + +/* WWDGT_CFG */ +#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ +#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ +#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ + +/* WWDGT_STAT */ +#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ + +/* constants definitions */ +#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ +#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ +#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ +#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ +#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ + +/* function declarations */ +/* reset the window watchdog timer configuration */ +void wwdgt_deinit(void); +/* start the window watchdog timer counter */ +void wwdgt_enable(void); + +/* configure the window watchdog timer counter value */ +void wwdgt_counter_update(uint16_t counter_value); +/* configure counter value, window value, and prescaler divider value */ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); + +/* enable early wakeup interrupt of WWDGT */ +void wwdgt_interrupt_enable(void); +/* check early wakeup interrupt state of WWDGT */ +FlagStatus wwdgt_flag_get(void); +/* clear early wakeup interrupt state of WWDGT */ +void wwdgt_flag_clear(void); + +#endif /* GD32VF103_WWDGT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c new file mode 100644 index 0000000..362a87a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c @@ -0,0 +1,992 @@ +/*! + \file gd32vf103_adc.c + \brief ADC driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_adc.h" + +/* discontinuous mode macro*/ +#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U) + +/* ADC regular channel macro */ +#define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U) +#define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U) +#define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U) +#define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U) + +/* ADC sampling time macro */ +#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U) +#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U) +#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U) + +/* ADC inserted channel macro */ +#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U) +#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U) + +/* ADC inserted channel offset macro */ +#define ADC_OFFSET_LENGTH ((uint8_t)3U) +#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) + +/*! + \brief reset ADC + \param[in] adc_periph: ADCx, x=0,1 + \param[out] none + \retval none +*/ +void adc_deinit(uint32_t adc_periph) +{ + switch(adc_periph){ + case ADC0: + /* reset ADC0 */ + rcu_periph_reset_enable(RCU_ADC0RST); + rcu_periph_reset_disable(RCU_ADC0RST); + break; + case ADC1: + /* reset ADC1 */ + rcu_periph_reset_enable(RCU_ADC1RST); + rcu_periph_reset_disable(RCU_ADC1RST); + break; + default: + break; + } +} + +/*! + \brief configure the ADC sync mode + \param[in] mode: ADC mode + only one parameter can be selected which is shown as below: + \arg ADC_MODE_FREE: all the ADCs work independently + \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode + \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode + \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode + \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode + \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only + \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only + \arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only + \arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only + \arg ADC_DAUL_INSERTED_TRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only + \param[out] none + \retval none +*/ +void adc_mode_config(uint32_t mode) +{ + ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM); + ADC_CTL0(ADC0) |= mode; +} + +/*! + \brief enable or disable ADC special function + \param[in] adc_periph: ADCx, x=0,1 + \param[in] function: the function to config + only one parameter can be selected which is shown as below: + \arg ADC_SCAN_MODE: scan mode select + \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically + \arg ADC_CONTINUOUS_MODE: continuous mode select + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue) +{ + if(newvalue){ + if(0U != (function & ADC_SCAN_MODE)){ + /* enable scan mode */ + ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; + } + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ + /* enable inserted channel group convert automatically */ + ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; + } + if(0U != (function & ADC_CONTINUOUS_MODE)){ + /* enable continuous mode */ + ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; + } + }else{ + if(0U != (function & ADC_SCAN_MODE)){ + /* disable scan mode */ + ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; + } + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ + /* disable inserted channel group convert automatically */ + ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; + } + if(0U != (function & ADC_CONTINUOUS_MODE)){ + /* disable continuous mode */ + ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; + } + } +} + +/*! + \brief configure ADC data alignment + \param[in] adc_periph: ADCx, x=0,1 + \param[in] data_alignment: data alignment select + only one parameter can be selected which is shown as below: + \arg ADC_DATAALIGN_RIGHT: LSB alignment + \arg ADC_DATAALIGN_LEFT: MSB alignment + \param[out] none + \retval none +*/ +void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment) +{ + if(ADC_DATAALIGN_RIGHT != data_alignment){ + /* MSB alignment */ + ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; + }else{ + /* LSB alignment */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); + } +} + +/*! + \brief enable ADC interface + \param[in] adc_periph: ADCx, x=0,1 + \param[out] none + \retval none +*/ +void adc_enable(uint32_t adc_periph) +{ + if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){ + /* enable ADC */ + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; + } +} + +/*! + \brief disable ADC interface + \param[in] adc_periph: ADCx, x=0,1 + \param[out] none + \retval none +*/ +void adc_disable(uint32_t adc_periph) +{ + /* disable ADC */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON); +} + +/*! + \brief ADC calibration and reset calibration + \param[in] adc_periph: ADCx, x=0,1 + \param[out] none + \retval none +*/ +void adc_calibration_enable(uint32_t adc_periph) +{ + /* reset the selected ADC1 calibration registers */ + ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; + /* check the RSTCLB bit state */ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ + } + /* enable ADC calibration process */ + ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; + /* check the CLB bit state */ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){ + } +} + +/*! + \brief enable the temperature sensor and Vrefint channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_tempsensor_vrefint_enable(void) +{ + /* enable the temperature sensor and Vrefint channel */ + ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN; +} + +/*! + \brief disable the temperature sensor and Vrefint channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_tempsensor_vrefint_disable(void) +{ + /* disable the temperature sensor and Vrefint channel */ + ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN; +} + +/*! + \brief enable DMA request + \param[in] adc_periph: ADCx, x=0,1 + \param[out] none + \retval none +*/ +void adc_dma_mode_enable(uint32_t adc_periph) +{ + /* enable DMA request */ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA); +} + +/*! + \brief disable DMA request + \param[in] adc_periph: ADCx, x=0,1 + \param[out] none + \retval none +*/ +void adc_dma_mode_disable(uint32_t adc_periph) +{ + /* disable DMA request */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA); +} + +/*! + \brief configure ADC discontinuous mode + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel + \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 + for regular channel, the number has no effect for inserted channel + \param[out] none + \retval none +*/ +void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length) +{ + /* disable discontinuous mode of regular & inserted channel */ + ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* config the number of conversions in discontinuous mode */ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); + ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + /* enable regular channel group discontinuous mode */ + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; + break; + case ADC_INSERTED_CHANNEL: + /* enable inserted channel group discontinuous mode */ + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; + break; + case ADC_CHANNEL_DISCON_DISABLE: + /* disable discontinuous mode of regular & inserted channel */ + default: + break; + } +} + +/*! + \brief configure the length of regular channel group or inserted channel group + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] length: the length of the channel + regular channel 1-16 + inserted channel 1-4 + \param[out] none + \retval none +*/ +void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length) +{ + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* configure the length of regular channel group */ + ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); + ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + break; + case ADC_INSERTED_CHANNEL: + /* configure the length of inserted channel group */ + ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); + ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + break; + default: + break; + } +} + +/*! + \brief configure ADC regular channel + \param[in] adc_periph: ADCx, x=0,1 + \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx + \param[in] sample_time: the sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles + \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles + \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles + \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles + \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles + \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles + \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles + \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles + \param[out] none + \retval none +*/ +void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) +{ + uint32_t rsq,sampt; + + /* ADC regular sequence config */ + if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){ + /* the regular group sequence rank is smaller than six */ + rsq = ADC_RSQ2(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank))); + /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ + rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank)); + ADC_RSQ2(adc_periph) = rsq; + }else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){ + /* the regular group sequence rank is smaller than twelve */ + rsq = ADC_RSQ1(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ + rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX))); + ADC_RSQ1(adc_periph) = rsq; + }else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){ + /* the regular group sequence rank is smaller than sixteen */ + rsq = ADC_RSQ0(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ + rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE))); + ADC_RSQ0(adc_periph) = rsq; + }else{ + } + + /* ADC sampling time config */ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ + /* the regular group sequence rank is smaller than ten */ + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); + /* channel sample time set*/ + sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)); + ADC_SAMPT1(adc_periph) = sampt; + }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){ + /* the regular group sequence rank is smaller than eighteen */ + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)))); + /* channel sample time set*/ + sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))); + ADC_SAMPT0(adc_periph) = sampt; + }else{ + } +} + +/*! + \brief configure ADC inserted channel + \param[in] adc_periph: ADCx, x=0,1 + \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx + \param[in] sample_time: The sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles + \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles + \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles + \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles + \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles + \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles + \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles + \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles + \param[out] none + \retval none +*/ +void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) +{ + uint8_t inserted_length; + uint32_t isq,sampt; + /* get inserted channel group length */ + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); + /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */ + isq = ADC_ISQ(adc_periph); + isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH))); + isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH)); + ADC_ISQ(adc_periph) = isq; + + /* ADC sampling time config */ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ + /* the inserted group sequence rank is smaller than ten */ + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); + /* channel sample time set*/ + sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel); + ADC_SAMPT1(adc_periph) = sampt; + }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){ + /* the inserted group sequence rank is smaller than eighteen */ + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)))); + /* channel sample time set*/ + sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))); + ADC_SAMPT0(adc_periph) = sampt; + }else{ + } +} + +/*! + \brief configure ADC inserted channel offset + \param[in] adc_periph: ADCx, x=0,1 + \param[in] inserted_channel: insert channel select + only one parameter can be selected + \arg ADC_INSERTED_CHANNEL_0: inserted channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted channel3 + \param[in] offset: the offset data + \param[out] none + \retval none +*/ +void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset) +{ + uint8_t inserted_length; + uint32_t num = 0U; + + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); + num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel)); + + if(num <= ADC_OFFSET_LENGTH){ + /* calculate the offset of the register */ + num = num * ADC_OFFSET_SHIFT_LENGTH; + /* config the offset of the selected channels */ + REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); + } +} + +/*! + \brief configure ADC external trigger source + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] external_trigger_source: regular or inserted group trigger source + only one parameter can be selected + for regular channel: + \arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select + \arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select + \arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select + \arg ADC0_1_EXTTRIG_REGULAR_T1_CH1: TIMER1 CH1 event select + \arg ADC0_1_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select + \arg ADC0_1_EXTTRIG_REGULAR_T3_CH3: TIMER3 CH3 event select + \arg ADC0_1_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11 + \arg ADC0_1_EXTTRIG_REGULAR_NONE: software trigger + for inserted channel: + \arg ADC0_1_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select + \arg ADC0_1_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select + \arg ADC0_1_EXTTRIG_INSERTED_T1_TRGO: TIMER1 TRGO event select + \arg ADC0_1_EXTTRIG_INSERTED_T1_CH0: TIMER1 CH0 event select + \arg ADC0_1_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select + \arg ADC0_1_EXTTRIG_INSERTED_T3_TRGO: TIMER3 TRGO event select + \arg ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 + \arg ADC0_1_EXTTRIG_INSERTED_NONE: software trigger + \param[out] none + \retval none +*/ +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source) +{ + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* configure ADC regular group external trigger source */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; + break; + case ADC_INSERTED_CHANNEL: + /* configure ADC inserted group external trigger source */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; + break; + default: + break; + } +} + +/*! + \brief configure ADC external trigger + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_channel_group: select the channel group + one or more parameters can be selected which are shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue) +{ + if(newvalue){ + if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + /* enable ADC regular channel group external trigger */ + ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC; + } + if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + /* enable ADC inserted channel group external trigger */ + ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC; + } + }else{ + if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + /* disable ADC regular channel group external trigger */ + ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC; + } + if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + /* disable ADC regular channel group external trigger */ + ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC; + } + } +} + +/*! + \brief enable ADC software trigger + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_channel_group: select the channel group + one or more parameters can be selected which are shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[out] none + \retval none +*/ +void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group) +{ + if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + /* enable ADC regular channel group software trigger */ + ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST; + } + if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + /* enable ADC inserted channel group software trigger */ + ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST; + } +} + +/*! + \brief read ADC regular group data register + \param[in] adc_periph: ADCx, x=0,1 + \param[in] none + \param[out] none + \retval the conversion value +*/ +uint16_t adc_regular_data_read(uint32_t adc_periph) +{ + return (uint16_t)(ADC_RDATA(adc_periph)); +} + +/*! + \brief read ADC inserted group data register + \param[in] adc_periph: ADCx, x=0,1 + \param[in] inserted_channel: insert channel select + only one parameter can be selected + \arg ADC_INSERTED_CHANNEL_0: inserted Channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted Channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted Channel3 + \param[out] none + \retval the conversion value +*/ +uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel) +{ + uint32_t idata; + /* read the data of the selected channel */ + switch(inserted_channel){ + case ADC_INSERTED_CHANNEL_0: + /* read the data of channel 0 */ + idata = ADC_IDATA0(adc_periph); + break; + case ADC_INSERTED_CHANNEL_1: + /* read the data of channel 1 */ + idata = ADC_IDATA1(adc_periph); + break; + case ADC_INSERTED_CHANNEL_2: + /* read the data of channel 2 */ + idata = ADC_IDATA2(adc_periph); + break; + case ADC_INSERTED_CHANNEL_3: + /* read the data of channel 3 */ + idata = ADC_IDATA3(adc_periph); + break; + default: + idata = 0U; + break; + } + return (uint16_t)idata; +} + +/*! + \brief read the last ADC0 and ADC1 conversion result data in sync mode + \param[in] none + \param[out] none + \retval the conversion value +*/ +uint32_t adc_sync_mode_convert_value_read(void) +{ + /* return conversion value */ + return ADC_RDATA(ADC0); +} + + +/*! + \brief configure ADC analog watchdog single channel + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0) + \param[out] none + \retval none +*/ +void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel) +{ + ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); + /* analog watchdog channel select */ + ADC_CTL0(adc_periph) |= (uint32_t)adc_channel; + ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); +} + +/*! + \brief configure ADC analog watchdog group channel + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_channel_group: the channel group use analog watchdog + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group + \param[out] none + \retval none +*/ +void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group) +{ + ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); + /* select the group */ + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* regular channel analog watchdog enable */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; + break; + case ADC_INSERTED_CHANNEL: + /* inserted channel analog watchdog enable */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; + break; + case ADC_REGULAR_INSERTED_CHANNEL: + /* regular and inserted channel analog watchdog enable */ + ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); + break; + default: + break; + } +} + +/*! + \brief disable ADC analog watchdog + \param[in] adc_periph: ADCx, x=0,1 + \param[out] none + \retval none +*/ +void adc_watchdog_disable(uint32_t adc_periph) +{ + ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); +} + +/*! + \brief configure ADC analog watchdog threshold + \param[in] adc_periph: ADCx, x=0,1 + \param[in] low_threshold: analog watchdog low threshold, 0..4095 + \param[in] high_threshold: analog watchdog high threshold, 0..4095 + \param[out] none + \retval none +*/ +void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold) +{ + ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold); + ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold); +} + +/*! + \brief get the ADC flag bits + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_flag: the adc flag bits + only one parameter can be selected which is shown as below: + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag) +{ + FlagStatus reval = RESET; + if(ADC_STAT(adc_periph) & adc_flag){ + reval = SET; + } + return reval; +} + +/*! + \brief clear the ADC flag bits + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_flag: the adc flag bits + one or more parameters can be selected which are shown as below: + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \param[out] none + \retval none +*/ +void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag) +{ + ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); +} + +/*! + \brief get the bit state of ADCx software start conversion + \param[in] adc_periph: ADCx, x=0,1 + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph) +{ + FlagStatus reval = RESET; + if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWRCST)){ + reval = SET; + } + return reval; +} + +/*! + \brief get the bit state of ADCx software inserted channel start conversion + \param[in] adc_periph: ADCx, x=0,1 + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph) +{ + FlagStatus reval = RESET; + if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWICST)){ + reval = SET; + } + return reval; +} + +/*! + \brief get the ADC interrupt bits + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_interrupt: the adc interrupt bits + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt) +{ + FlagStatus interrupt_flag = RESET; + uint32_t state; + /* check the interrupt bits */ + switch(adc_interrupt){ + case ADC_INT_FLAG_WDE: + /* get the ADC analog watchdog interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_WDE; + if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){ + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOC: + /* get the ADC end of group conversion interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_EOC; + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){ + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOIC: + /* get the ADC end of inserted group conversion interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){ + interrupt_flag = SET; + } + break; + default: + break; + } + return interrupt_flag; +} + +/*! + \brief clear the ADC flag + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_interrupt: the adc status flag + one or more parameters can be selected which are shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt + \param[out] none + \retval none +*/ +void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt) +{ + ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); +} + +/*! + \brief enable ADC interrupt + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_interrupt: the adc interrupt + one or more parameters can be selected which are shown as below: + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of group conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) +{ + /* enable ADC analog watchdog interrupt */ + if(0U != (adc_interrupt & ADC_INT_WDE)){ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; + } + /* enable ADC end of group conversion interrupt */ + if(0U != (adc_interrupt & ADC_INT_EOC)){ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; + } + /* enable ADC end of inserted group conversion interrupt */ + if(0U != (adc_interrupt & ADC_INT_EOIC)){ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; + } +} + +/*! + \brief disable ADC interrupt + \param[in] adc_periph: ADCx, x=0,1 + \param[in] adc_interrupt: the adc interrupt flag + one or more parameters can be selected which are shown as below: + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of group conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) +{ + /* disable ADC analog watchdog interrupt */ + if(0U != (adc_interrupt & ADC_INT_WDE)){ + ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE; + } + /* disable ADC end of group conversion interrupt */ + if(0U != (adc_interrupt & ADC_INT_EOC)){ + ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE; + } + /* disable ADC end of inserted group conversion interrupt */ + if(0U != (adc_interrupt & ADC_INT_EOIC)){ + ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE; + } +} + +/*! + \brief adc resolution config + \param[in] adc_periph: ADCx, x=0,1 + \param[in] resolution: ADC resolution + only one parameter can be selected which is shown as below: + \arg ADC_RESOLUTION_12B: 12-bit ADC resolution + \arg ADC_RESOLUTION_10B: 10-bit ADC resolution + \arg ADC_RESOLUTION_8B: 8-bit ADC resolution + \arg ADC_RESOLUTION_6B: 6-bit ADC resolution + \param[out] none + \retval none +*/ +void adc_resolution_config(uint32_t adc_periph, uint32_t resolution) +{ + ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_DRES); + ADC_OVSCR(adc_periph) |= (uint32_t)resolution; +} + +/*! + \brief adc oversample mode config + \param[in] adc_periph: ADCx, x=0,1 + \param[in] mode: ADC oversampling mode + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel + are done consecutively after a trigger + \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel + needs a trigger + \param[in] shift: ADC oversampling shift + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift + \param[in] ratio: ADC oversampling ratio + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio X2 + \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio X4 + \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio X8 + \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio X16 + \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio X32 + \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio X64 + \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio X128 + \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio X256 + \param[out] none + \retval none +*/ +void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift,uint8_t ratio) +{ + if(mode){ + ADC_OVSCR(adc_periph) |= (uint32_t)ADC_OVSCR_TOVS; + }else{ + ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_TOVS); + } + /* config the shift and ratio */ + ADC_OVSCR(adc_periph) &= ~((uint32_t)(ADC_OVSCR_OVSR | ADC_OVSCR_OVSS)); + ADC_OVSCR(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio); +} + +/*! + \brief enable ADC oversample mode + \param[in] adc_periph: ADCx, x=0,1 + \param[out] none + \retval none +*/ +void adc_oversample_mode_enable(uint32_t adc_periph) +{ + ADC_OVSCR(adc_periph) |= ADC_OVSCR_OVSEN; +} + +/*! + \brief disable ADC oversample mode + \param[in] adc_periph: ADCx, x=0,1 + \param[out] none + \retval none +*/ +void adc_oversample_mode_disable(uint32_t adc_periph) +{ + ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_OVSEN); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c new file mode 100644 index 0000000..3be5bdc --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c @@ -0,0 +1,292 @@ +/*! + \file gd32vf103_bkp.c + \brief BKP driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_bkp.h" + +/* BKP register bits offset */ +#define BKP_TAMPER_BITS_OFFSET ((uint32_t)8U) + +/*! + \brief reset BKP registers + \param[in] none + \param[out] none + \retval none +*/ +void bkp_deinit(void) +{ + /* reset BKP domain register*/ + rcu_bkp_reset_enable(); + rcu_bkp_reset_disable(); +} + +/*! + \brief write BKP data register + \param[in] register_number: refer to bkp_data_register_enum + only one parameter can be selected which is shown as below: + \arg BKP_DATA_x(x = 0..41): bkp data register number x + \param[in] data: the data to be write in BKP data register + \param[out] none + \retval none +*/ +void bkp_data_write(bkp_data_register_enum register_number, uint16_t data) +{ + if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ + BKP_DATA10_41(register_number - 1U) = data; + }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ + BKP_DATA0_9(register_number - 1U) = data; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief read BKP data register + \param[in] register_number: refer to bkp_data_register_enum + only one parameter can be selected which is shown as below: + \arg BKP_DATA_x(x = 0..41): bkp data register number x + \param[out] none + \retval data of BKP data register +*/ +uint16_t bkp_data_read(bkp_data_register_enum register_number) +{ + uint16_t data = 0U; + + /* get the data from the BKP data register */ + if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ + data = BKP_DATA10_41(register_number - 1U); + }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ + data = BKP_DATA0_9(register_number - 1U); + }else{ + /* illegal parameters */ + } + return data; +} + +/*! + \brief enable RTC clock calibration output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_calibration_output_enable(void) +{ + BKP_OCTL |= (uint16_t)BKP_OCTL_COEN; +} + +/*! + \brief disable RTC clock calibration output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_calibration_output_disable(void) +{ + BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN; +} + +/*! + \brief enable RTC alarm or second signal output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_signal_output_enable(void) +{ + BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN; +} + +/*! + \brief disable RTC alarm or second signal output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_signal_output_disable(void) +{ + BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN; +} + +/*! + \brief select RTC output + \param[in] outputsel: RTC output selection + only one parameter can be selected which is shown as below: + \arg RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output + \arg RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output + \param[out] none + \retval none +*/ +void bkp_rtc_output_select(uint16_t outputsel) +{ + uint16_t ctl = 0U; + + /* configure BKP_OCTL_ROSEL with outputsel */ + ctl = BKP_OCTL; + ctl &= (uint16_t)~BKP_OCTL_ROSEL; + ctl |= outputsel; + BKP_OCTL = ctl; +} + +/*! + \brief set RTC clock calibration value + \param[in] value: RTC clock calibration value + \arg 0x00 - 0x7F + \param[out] none + \retval none +*/ +void bkp_rtc_calibration_value_set(uint8_t value) +{ + uint16_t ctl; + + /* configure BKP_OCTL_RCCV with value */ + ctl = BKP_OCTL; + ctl &= (uint16_t)~BKP_OCTL_RCCV; + ctl |= (uint16_t)OCTL_RCCV(value); + BKP_OCTL = ctl; +} + +/*! + \brief enable tamper detection + \param[in] none + \param[out] none + \retval none +*/ +void bkp_tamper_detection_enable(void) +{ + BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN; +} + +/*! + \brief disable tamper detection + \param[in] none + \param[out] none + \retval none +*/ +void bkp_tamper_detection_disable(void) +{ + BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN; +} + +/*! + \brief set tamper pin active level + \param[in] level: tamper active level + only one parameter can be selected which is shown as below: + \arg TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high + \arg TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low + \param[out] none + \retval none +*/ +void bkp_tamper_active_level_set(uint16_t level) +{ + uint16_t ctl = 0U; + + /* configure BKP_TPCTL_TPAL with level */ + ctl = BKP_TPCTL; + ctl &= (uint16_t)~BKP_TPCTL_TPAL; + ctl |= level; + BKP_TPCTL = ctl; +} + +/*! + \brief enable tamper interrupt + \param[in] none + \param[out] none + \retval none +*/ +void bkp_interrupt_enable(void) +{ + BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE; +} + +/*! + \brief disable tamper interrupt + \param[in] none + \param[out] none + \retval none +*/ +void bkp_interrupt_disable(void) +{ + BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE; +} + +/*! + \brief get tamper flag state + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus bkp_flag_get(void) +{ + if(RESET != (BKP_TPCS & BKP_FLAG_TAMPER)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear tamper flag state + \param[in] none + \param[out] none + \retval none +*/ +void bkp_flag_clear(void) +{ + BKP_TPCS |= (uint16_t)(BKP_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET); +} + +/*! + \brief get tamper interrupt flag state + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus bkp_interrupt_flag_get(void) +{ + if(RESET != (BKP_TPCS & BKP_INT_FLAG_TAMPER)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear tamper interrupt flag state + \param[in] none + \param[out] none + \retval none +*/ +void bkp_interrupt_flag_clear(void) +{ + BKP_TPCS |= (uint16_t)(BKP_INT_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c new file mode 100644 index 0000000..9cb6a58 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c @@ -0,0 +1,989 @@ +/*! + \file gd32vf103_can.c + \brief CAN driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_can.h" + +#define CAN_ERROR_HANDLE(s) do{}while(1) + +/*! + \brief deinitialize CAN + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_deinit(uint32_t can_periph) +{ + if(CAN0 == can_periph){ + rcu_periph_reset_enable(RCU_CAN0RST); + rcu_periph_reset_disable(RCU_CAN0RST); + }else{ + rcu_periph_reset_enable(RCU_CAN1RST); + rcu_periph_reset_disable(RCU_CAN1RST); + } +} + +/*! + \brief initialize CAN parameter struct with a default value + \param[in] type: the type of CAN parameter struct + only one parameter can be selected which is shown as below: + \arg CAN_INIT_STRUCT: the CAN initial struct + \arg CAN_FILTER_STRUCT: the CAN filter struct + \arg CAN_TX_MESSAGE_STRUCT: the CAN TX message struct + \arg CAN_RX_MESSAGE_STRUCT: the CAN RX message struct + \param[in] p_struct: the pointer of the specific struct + \param[out] none + \retval none +*/ +void can_struct_para_init(can_struct_type_enum type, void* p_struct) +{ + uint8_t i; + + /* get type of the struct */ + switch(type){ + /* used for can_init() */ + case CAN_INIT_STRUCT: + ((can_parameter_struct*)p_struct)->auto_bus_off_recovery = DISABLE; + ((can_parameter_struct*)p_struct)->no_auto_retrans = DISABLE; + ((can_parameter_struct*)p_struct)->auto_wake_up = DISABLE; + ((can_parameter_struct*)p_struct)->prescaler = 0x03FFU; + ((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE; + ((can_parameter_struct*)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; + ((can_parameter_struct*)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; + ((can_parameter_struct*)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; + ((can_parameter_struct*)p_struct)->time_triggered = DISABLE; + ((can_parameter_struct*)p_struct)->trans_fifo_order = DISABLE; + ((can_parameter_struct*)p_struct)->working_mode = CAN_NORMAL_MODE; + + break; + /* used for can_filter_init() */ + case CAN_FILTER_STRUCT: + ((can_filter_parameter_struct*)p_struct)->filter_bits = CAN_FILTERBITS_32BIT; + ((can_filter_parameter_struct*)p_struct)->filter_enable = DISABLE; + ((can_filter_parameter_struct*)p_struct)->filter_fifo_number = CAN_FIFO0; + ((can_filter_parameter_struct*)p_struct)->filter_list_high = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_list_low = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_mask_high = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_mask_low = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_mode = CAN_FILTERMODE_MASK; + ((can_filter_parameter_struct*)p_struct)->filter_number = 0U; + + break; + /* used for can_message_transmit() */ + case CAN_TX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++){ + ((can_trasnmit_message_struct*)p_struct)->tx_data[i] = 0U; + } + + ((can_trasnmit_message_struct*)p_struct)->tx_dlen = 0u; + ((can_trasnmit_message_struct*)p_struct)->tx_efid = 0U; + ((can_trasnmit_message_struct*)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_trasnmit_message_struct*)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; + ((can_trasnmit_message_struct*)p_struct)->tx_sfid = 0U; + + break; + /* used for can_message_receive() */ + case CAN_RX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++){ + ((can_receive_message_struct*)p_struct)->rx_data[i] = 0U; + } + + ((can_receive_message_struct*)p_struct)->rx_dlen = 0U; + ((can_receive_message_struct*)p_struct)->rx_efid = 0U; + ((can_receive_message_struct*)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_receive_message_struct*)p_struct)->rx_fi = 0U; + ((can_receive_message_struct*)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA; + ((can_receive_message_struct*)p_struct)->rx_sfid = 0U; + + break; + + default: + CAN_ERROR_HANDLE("parameter is invalid \r\n"); + } +} + +/*! + \brief initialize CAN + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] can_parameter_init: parameters for CAN initializtion + \arg working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE + \arg resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4) + \arg time_segment_1: CAN_BT_BS1_xTQ(1..16) + \arg time_segment_2: CAN_BT_BS2_xTQ(1..8) + \arg time_triggered: ENABLE or DISABLE + \arg auto_bus_off_recovery: ENABLE or DISABLE + \arg auto_wake_up: ENABLE or DISABLE + \arg no_auto_retrans: ENABLE or DISABLE + \arg rec_fifo_overwrite: ENABLE or DISABLE + \arg trans_fifo_order: ENABLE or DISABLE + \arg prescaler: 0x0000 - 0x03FF + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init) +{ + uint32_t timeout = CAN_TIMEOUT; + ErrStatus flag = ERROR; + + /* disable sleep mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; + /* enable initialize mode */ + CAN_CTL(can_periph) |= CAN_CTL_IWMOD; + /* wait ACK */ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ + timeout--; + } + /* check initialize working success */ + if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ + flag = ERROR; + }else{ + /* set the bit timing register */ + CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \ + BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \ + BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \ + BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \ + BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U))); + + /* time trigger communication mode */ + if(ENABLE == can_parameter_init->time_triggered){ + CAN_CTL(can_periph) |= CAN_CTL_TTC; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_TTC; + } + /* automatic bus-off managment */ + if(ENABLE == can_parameter_init->auto_bus_off_recovery){ + CAN_CTL(can_periph) |= CAN_CTL_ABOR; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_ABOR; + } + /* automatic wakeup mode */ + if(ENABLE == can_parameter_init->auto_wake_up){ + CAN_CTL(can_periph) |= CAN_CTL_AWU; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_AWU; + } + /* automatic retransmission mode disable*/ + if(ENABLE == can_parameter_init->no_auto_retrans){ + CAN_CTL(can_periph) |= CAN_CTL_ARD; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_ARD; + } + /* receive fifo overwrite mode */ + if(ENABLE == can_parameter_init->rec_fifo_overwrite){ + CAN_CTL(can_periph) |= CAN_CTL_RFOD; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; + } + /* transmit fifo order */ + if(ENABLE == can_parameter_init->trans_fifo_order){ + CAN_CTL(can_periph) |= CAN_CTL_TFO; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_TFO; + } + /* disable initialize mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; + timeout = CAN_TIMEOUT; + /* wait the ACK */ + while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ + timeout--; + } + /* check exit initialize mode */ + if(0U != timeout){ + flag = SUCCESS; + } + } + CAN_TMI0(can_periph) = 0x0; + CAN_TMI1(can_periph) = 0x0; + CAN_TMI2(can_periph) = 0x0; + CAN_TMP0(can_periph) = 0x0; + CAN_TMP1(can_periph) = 0x0; + CAN_TMP2(can_periph) = 0x0; + CAN_TMDATA00(can_periph) = 0x0; + CAN_TMDATA01(can_periph) = 0x0; + CAN_TMDATA02(can_periph) = 0x0; + CAN_TMDATA10(can_periph) = 0x0; + CAN_TMDATA11(can_periph) = 0x0; + CAN_TMDATA12(can_periph) = 0x0; + + return flag; +} + +/*! + \brief initialize CAN filter + \param[in] can_filter_parameter_init: struct for CAN filter initialization + \arg filter_list_high: 0x0000 - 0xFFFF + \arg filter_list_low: 0x0000 - 0xFFFF + \arg filter_mask_high: 0x0000 - 0xFFFF + \arg filter_mask_low: 0x0000 - 0xFFFF + \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 + \arg filter_number: 0 - 27 + \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST + \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT + \arg filter_enable: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) +{ + uint32_t val = 0U; + + val = ((uint32_t)1) << (can_filter_parameter_init->filter_number); + /* filter lock disable */ + CAN_FCTL(CAN0) |= CAN_FCTL_FLD; + /* disable filter */ + CAN_FW(CAN0) &= ~(uint32_t)val; + + /* filter 16 bits */ + if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){ + /* set filter 16 bits */ + CAN_FSCFG(CAN0) &= ~(uint32_t)val; + /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */ + CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */ + CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); + } + /* filter 32 bits */ + if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){ + /* set filter 32 bits */ + CAN_FSCFG(CAN0) |= (uint32_t)val; + /* 32 bits list or first 32 bits list */ + CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + /* 32 bits mask or second 32 bits list */ + CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); + } + + /* filter mode */ + if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){ + /* mask mode */ + CAN_FMCFG(CAN0) &= ~(uint32_t)val; + }else{ + /* list mode */ + CAN_FMCFG(CAN0) |= (uint32_t)val; + } + + /* filter FIFO */ + if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){ + /* FIFO0 */ + CAN_FAFIFO(CAN0) &= ~(uint32_t)val; + }else{ + /* FIFO1 */ + CAN_FAFIFO(CAN0) |= (uint32_t)val; + } + + /* filter working */ + if(ENABLE == can_filter_parameter_init->filter_enable){ + + CAN_FW(CAN0) |= (uint32_t)val; + } + + /* filter lock enable */ + CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; +} + +/*! + \brief set CAN1 fliter start bank number + \param[in] start_bank: CAN1 start bank number + only one parameter can be selected which is shown as below: + \arg (1..27) + \param[out] none + \retval none +*/ +void can1_filter_start_bank(uint8_t start_bank) +{ + /* filter lock disable */ + CAN_FCTL(CAN0) |= CAN_FCTL_FLD; + /* set CAN1 filter start number */ + CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F; + CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank); + /* filter lock enaable */ + CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; +} + +/*! + \brief enable CAN debug freeze + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_debug_freeze_enable(uint32_t can_periph) +{ + /* set DFZ bit */ + CAN_CTL(can_periph) |= CAN_CTL_DFZ; + if(CAN0 == can_periph){ + dbg_periph_enable(DBG_CAN0_HOLD); + }else{ + dbg_periph_enable(DBG_CAN1_HOLD); + } +} + +/*! + \brief disable CAN debug freeze + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_debug_freeze_disable(uint32_t can_periph) +{ + /* set DFZ bit */ + CAN_CTL(can_periph) &= ~CAN_CTL_DFZ; + if(CAN0 == can_periph){ + dbg_periph_disable(DBG_CAN0_HOLD); + }else{ + dbg_periph_disable(DBG_CAN1_HOLD); + } +} + +/*! + \brief enable CAN time trigger mode + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_time_trigger_mode_enable(uint32_t can_periph) +{ + uint8_t mailbox_number; + + /* enable the tcc mode */ + CAN_CTL(can_periph) |= CAN_CTL_TTC; + /* enable time stamp */ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ + CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN; + } +} + +/*! + \brief disable CAN time trigger mode + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval none +*/ +void can_time_trigger_mode_disable(uint32_t can_periph) +{ + uint8_t mailbox_number; + + /* disable the TCC mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_TTC; + /* reset TSEN bits */ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ + CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN; + } +} + +/*! + \brief transmit CAN message + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] transmit_message: struct for CAN transmit message + \arg tx_sfid: 0x00000000 - 0x000007FF + \arg tx_efid: 0x00000000 - 0x1FFFFFFF + \arg tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED + \arg tx_ft: CAN_FT_DATA, CAN_FT_REMOTE + \arg tx_dlenc: 1 - 7 + \arg tx_data[]: 0x00 - 0xFF + \param[out] none + \retval mailbox_number +*/ +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message) +{ + uint8_t mailbox_number = CAN_MAILBOX0; + + /* select one empty mailbox */ + if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){ + mailbox_number = CAN_MAILBOX0; + }else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){ + mailbox_number = CAN_MAILBOX1; + }else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){ + mailbox_number = CAN_MAILBOX2; + }else{ + mailbox_number = CAN_NOMAILBOX; + } + /* return no mailbox empty */ + if(CAN_NOMAILBOX == mailbox_number){ + return CAN_NOMAILBOX; + } + + CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; + if(CAN_FF_STANDARD == transmit_message->tx_ff){ + /* set transmit mailbox standard identifier */ + CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \ + transmit_message->tx_ft); + }else{ + /* set transmit mailbox extended identifier */ + CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \ + transmit_message->tx_ff | \ + transmit_message->tx_ft); + } + /* set the data length */ + CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_DLENC; + CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen; + /* set the data */ + CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \ + TMDATA0_DB2(transmit_message->tx_data[2]) | \ + TMDATA0_DB1(transmit_message->tx_data[1]) | \ + TMDATA0_DB0(transmit_message->tx_data[0]); + CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \ + TMDATA1_DB6(transmit_message->tx_data[6]) | \ + TMDATA1_DB5(transmit_message->tx_data[5]) | \ + TMDATA1_DB4(transmit_message->tx_data[4]); + /* enable transmission */ + CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN; + + return mailbox_number; +} + +/*! + \brief get CAN transmit state + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] mailbox_number + only one parameter can be selected which is shown as below: + \arg CAN_MAILBOX(x=0,1,2) + \param[out] none + \retval can_transmit_state_enum +*/ +can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number) +{ + can_transmit_state_enum state = CAN_TRANSMIT_FAILED; + uint32_t val = 0U; + + /* check selected mailbox state */ + switch(mailbox_number){ + /* mailbox0 */ + case CAN_MAILBOX0: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0); + break; + /* mailbox1 */ + case CAN_MAILBOX1: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1); + break; + /* mailbox2 */ + case CAN_MAILBOX2: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2); + break; + default: + val = CAN_TRANSMIT_FAILED; + break; + } + + switch(val){ + /* transmit pending */ + case (CAN_STATE_PENDING): + state = CAN_TRANSMIT_PENDING; + break; + /* mailbox0 transmit succeeded */ + case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): + state = CAN_TRANSMIT_OK; + break; + /* mailbox1 transmit succeeded */ + case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): + state = CAN_TRANSMIT_OK; + break; + /* mailbox2 transmit succeeded */ + case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): + state = CAN_TRANSMIT_OK; + break; + /* transmit failed */ + default: + state = CAN_TRANSMIT_FAILED; + break; + } + return state; +} + +/*! + \brief stop CAN transmission + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] mailbox_number + only one parameter can be selected which is shown as below: + \arg CAN_MAILBOXx(x=0,1,2) + \param[out] none + \retval none +*/ +void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) +{ + if(CAN_MAILBOX0 == mailbox_number){ + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; + while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)){ + } + }else if(CAN_MAILBOX1 == mailbox_number){ + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; + while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)){ + } + }else if(CAN_MAILBOX2 == mailbox_number){ + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; + while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)){ + } + }else{ + /* illegal parameters */ + } +} + +/*! + \brief CAN receive message + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] fifo_number + \arg CAN_FIFOx(x=0,1) + \param[out] receive_message: struct for CAN receive message + \arg rx_sfid: 0x00000000 - 0x000007FF + \arg rx_efid: 0x00000000 - 0x1FFFFFFF + \arg rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED + \arg rx_ft: CAN_FT_DATA, CAN_FT_REMOTE + \arg rx_dlenc: 1 - 7 + \arg rx_data[]: 0x00 - 0xFF + \arg rx_fi: 0 - 27 + \retval none +*/ +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message) +{ + /* get the frame format */ + receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number)); + if(CAN_FF_STANDARD == receive_message->rx_ff){ + /* get standard identifier */ + receive_message->rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); + }else{ + /* get extended identifier */ + receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); + } + + /* get frame type */ + receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); + /* filtering index */ + receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); + /* get recevie data length */ + receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); + + /* receive data */ + receive_message -> rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[1] = (uint8_t)(GET_RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[2] = (uint8_t)(GET_RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[3] = (uint8_t)(GET_RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[4] = (uint8_t)(GET_RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[5] = (uint8_t)(GET_RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[6] = (uint8_t)(GET_RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); + + /* release FIFO */ + if(CAN_FIFO0 == fifo_number){ + CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; + }else{ + CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; + } +} + +/*! + \brief release FIFO0 + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] fifo_number + only one parameter can be selected which is shown as below: + \arg CAN_FIFOx(x=0,1) + \param[out] none + \retval none +*/ +void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) +{ + if(CAN_FIFO0 == fifo_number){ + CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; + }else if(CAN_FIFO1 == fifo_number){ + CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; + }else{ + /* illegal parameters */ + CAN_ERROR_HANDLE("CAN FIFO NUM is invalid \r\n"); + } +} + +/*! + \brief CAN receive message length + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] fifo_number + only one parameter can be selected which is shown as below: + \arg CAN_FIFOx(x=0,1) + \param[out] none + \retval message length +*/ +uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) +{ + uint8_t val = 0U; + + if(CAN_FIFO0 == fifo_number){ + /* FIFO0 */ + val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); + }else if(CAN_FIFO1 == fifo_number){ + /* FIFO1 */ + val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK); + }else{ + /* illegal parameters */ + } + return val; +} + +/*! + \brief set CAN working mode + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] can_working_mode + only one parameter can be selected which is shown as below: + \arg CAN_MODE_INITIALIZE + \arg CAN_MODE_NORMAL + \arg CAN_MODE_SLEEP + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) +{ + ErrStatus flag = ERROR; + /* timeout for IWS or also for SLPWS bits */ + uint32_t timeout = CAN_TIMEOUT; + + if(CAN_MODE_INITIALIZE == working_mode){ + /* disable sleep mode */ + CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); + /* set initialize mode */ + CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; + /* wait the acknowledge */ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ + timeout--; + } + if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ + flag = ERROR; + }else{ + flag = SUCCESS; + } + }else if(CAN_MODE_NORMAL == working_mode){ + /* enter normal mode */ + CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); + /* wait the acknowledge */ + while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){ + timeout--; + } + if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){ + flag = ERROR; + }else{ + flag = SUCCESS; + } + }else if(CAN_MODE_SLEEP == working_mode){ + /* disable initialize mode */ + CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD); + /* set sleep mode */ + CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; + /* wait the acknowledge */ + while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){ + timeout--; + } + if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ + flag = ERROR; + }else{ + flag = SUCCESS; + } + }else{ + flag = ERROR; + } + return flag; +} + +/*! + \brief wake up CAN + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus can_wakeup(uint32_t can_periph) +{ + ErrStatus flag = ERROR; + uint32_t timeout = CAN_TIMEOUT; + + /* wakeup */ + CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; + + while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){ + timeout--; + } + /* check state */ + if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ + flag = ERROR; + }else{ + flag = SUCCESS; + } + return flag; +} + +/*! + \brief get CAN error type + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval can_error_enum + \arg CAN_ERROR_NONE: no error + \arg CAN_ERROR_FILL: fill error + \arg CAN_ERROR_FORMATE: format error + \arg CAN_ERROR_ACK: ACK error + \arg CAN_ERROR_BITRECESSIVE: bit recessive + \arg CAN_ERROR_BITDOMINANTER: bit dominant error + \arg CAN_ERROR_CRC: CRC error + \arg CAN_ERROR_SOFTWARECFG: software configure +*/ +can_error_enum can_error_get(uint32_t can_periph) +{ + can_error_enum error; + error = CAN_ERROR_NONE; + + /* get error type */ + error = (can_error_enum)(GET_ERR_ERRN(CAN_ERR(can_periph))); + return error; +} + +/*! + \brief get CAN receive error number + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval error number +*/ +uint8_t can_receive_error_number_get(uint32_t can_periph) +{ + uint8_t val; + + /* get error count */ + val = (uint8_t)(GET_ERR_RECNT(CAN_ERR(can_periph))); + return val; +} + +/*! + \brief get CAN transmit error number + \param[in] can_periph + \arg CANx(x=0,1) + \param[out] none + \retval error number +*/ +uint8_t can_transmit_error_number_get(uint32_t can_periph) +{ + uint8_t val; + + val = (uint8_t)(GET_ERR_TECNT(CAN_ERR(can_periph))); + return val; +} + +/*! + \brief enable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] interrupt + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WU: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) |= interrupt; +} + +/*! + \brief disable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] interrupt + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WU: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) &= ~interrupt; +} + +/*! + \brief get CAN flag state + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] flag: CAN flags, refer to can_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_FLAG_MTE2: mailbox 2 transmit error + \arg CAN_FLAG_MTE1: mailbox 1 transmit error + \arg CAN_FLAG_MTE0: mailbox 0 transmit error + \arg CAN_FLAG_MTF2: mailbox 2 transmit finished + \arg CAN_FLAG_MTF1: mailbox 1 transmit finished + \arg CAN_FLAG_MTF0: mailbox 0 transmit finished + \arg CAN_FLAG_RFO0: receive FIFO0 overfull + \arg CAN_FLAG_RFF0: receive FIFO0 full + \arg CAN_FLAG_RFO1: receive FIFO1 overfull + \arg CAN_FLAG_RFF1: receive FIFO1 full + \arg CAN_FLAG_BOERR: bus-off error + \arg CAN_FLAG_PERR: passive error + \arg CAN_FLAG_WERR: warning error + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) +{ + /* get flag and interrupt enable state */ + if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear CAN flag state + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] flag: CAN flags, refer to can_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_FLAG_MTE2: mailbox 2 transmit error + \arg CAN_FLAG_MTE1: mailbox 1 transmit error + \arg CAN_FLAG_MTE0: mailbox 0 transmit error + \arg CAN_FLAG_MTF2: mailbox 2 transmit finished + \arg CAN_FLAG_MTF1: mailbox 1 transmit finished + \arg CAN_FLAG_MTF0: mailbox 0 transmit finished + \arg CAN_FLAG_RFO0: receive FIFO0 overfull + \arg CAN_FLAG_RFF0: receive FIFO0 full + \arg CAN_FLAG_RFO1: receive FIFO1 overfull + \arg CAN_FLAG_RFF1: receive FIFO1 full + \arg CAN_FLAG_BOERR: bus-off error + \arg CAN_FLAG_PERR: passive error + \arg CAN_FLAG_WERR: warning error + \param[out] none + \retval none +*/ +void can_flag_clear(uint32_t can_periph, can_flag_enum flag) +{ + CAN_REG_VAL(can_periph, flag) = BIT(CAN_BIT_POS(flag)); +} + +/*! + \brief get CAN interrupt flag state + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering + \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode + \arg CAN_INT_FLAG_ERRIF: error interrupt flag + \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag + \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag + \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag + \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag + \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag) +{ + uint32_t ret1 = RESET; + uint32_t ret2 = RESET; + + /* get the staus of interrupt flag */ + ret1 = CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag)); + /* get the staus of interrupt enale bit */ + ret2 = CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag)); + if(ret1 && ret2){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear CAN interrupt flag state + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering + \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode + \arg CAN_INT_FLAG_ERRIF: error interrupt flag + \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag + \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag + \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag + \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag + \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag + \arg CAN_FLAG_BOERR: bus-off error + \arg CAN_FLAG_PERR: passive error + \arg CAN_FLAG_WERR: warning error + \param[out] none + \retval none +*/ +void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag) +{ + CAN_REG_VALS(can_periph, flag) = BIT(CAN_BIT_POS0(flag)); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c new file mode 100644 index 0000000..b4fb680 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c @@ -0,0 +1,127 @@ +/*! + \file gd32vf103_crc.c + \brief CRC driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_crc.h" + +#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU) +#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U) + +/*! + \brief deinit CRC calculation unit + \param[in] none + \param[out] none + \retval none +*/ +void crc_deinit(void) +{ + CRC_DATA = CRC_DATA_RESET_VALUE; + CRC_FDATA = CRC_FDATA_RESET_VALUE; + CRC_CTL = (uint32_t)CRC_CTL_RST; +} + +/*! + \brief reset data register(CRC_DATA) to the value of 0xFFFFFFFF + \param[in] none + \param[out] none + \retval none +*/ +void crc_data_register_reset(void) +{ + CRC_CTL |= (uint32_t)CRC_CTL_RST; +} + +/*! + \brief read the value of the data register + \param[in] none + \param[out] none + \retval 32-bit value of the data register +*/ +uint32_t crc_data_register_read(void) +{ + uint32_t data; + data = CRC_DATA; + return (data); +} + +/*! + \brief read the value of the free data register + \param[in] none + \param[out] none + \retval 8-bit value of the free data register +*/ +uint8_t crc_free_data_register_read(void) +{ + uint8_t fdata; + fdata = (uint8_t)CRC_FDATA; + return (fdata); +} + +/*! + \brief write data to the free data register + \param[in] free_data: specified 8-bit data + \param[out] none + \retval none +*/ +void crc_free_data_register_write(uint8_t free_data) +{ + CRC_FDATA = (uint32_t)free_data; +} + +/*! + \brief calculate the CRC value of a 32-bit data + \param[in] sdata: specified 32-bit data + \param[out] none + \retval 32-bit value calculated by CRC +*/ +uint32_t crc_single_data_calculate(uint32_t sdata) +{ + CRC_DATA = sdata; + return (CRC_DATA); +} + +/*! + \brief calculate the CRC value of an array of 32-bit values + \param[in] array: pointer to an array of 32-bit values + \param[in] size: size of the array + \param[out] none + \retval 32-bit value calculated by CRC +*/ +uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) +{ + uint32_t index; + for(index = 0U; index < size; index++){ + CRC_DATA = array[index]; + } + return (CRC_DATA); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c new file mode 100644 index 0000000..c866e07 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c @@ -0,0 +1,537 @@ +/*! + \file gd32vf103_dac.c + \brief DAC driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_dac.h" + +/* DAC register bit offset */ +#define DAC1_REG_OFFSET ((uint32_t)16U) +#define DH_12BIT_OFFSET ((uint32_t)16U) +#define DH_8BIT_OFFSET ((uint32_t)8U) + +/*! + \brief deinitialize DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_deinit(void) +{ + rcu_periph_reset_enable(RCU_DACRST); + rcu_periph_reset_disable(RCU_DACRST); +} + +/*! + \brief enable DAC + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL |= DAC_CTL_DEN0; + }else{ + DAC_CTL |= DAC_CTL_DEN1; + } +} + +/*! + \brief disable DAC + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DEN0; + }else{ + DAC_CTL &= ~DAC_CTL_DEN1; + } +} + +/*! + \brief enable DAC DMA function + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_dma_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL |= DAC_CTL_DDMAEN0; + }else{ + DAC_CTL |= DAC_CTL_DDMAEN1; + } +} + +/*! + \brief disable DAC DMA function + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_dma_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DDMAEN0; + }else{ + DAC_CTL &= ~DAC_CTL_DDMAEN1; + } +} + +/*! + \brief enable DAC output buffer + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_output_buffer_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DBOFF0; + }else{ + DAC_CTL &= ~DAC_CTL_DBOFF1; + } +} + +/*! + \brief disable DAC output buffer + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_output_buffer_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL |= DAC_CTL_DBOFF0; + }else{ + DAC_CTL |= DAC_CTL_DBOFF1; + } +} + +/*! + \brief get DAC output value + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval DAC output data +*/ +uint16_t dac_output_value_get(uint32_t dac_periph) +{ + uint16_t data = 0U; + if(DAC0 == dac_periph){ + /* store the DAC0 output value */ + data = (uint16_t)DAC0_DO; + }else{ + /* store the DAC1 output value */ + data = (uint16_t)DAC1_DO; + } + return data; +} + +/*! + \brief set the DAC specified data holding register value + \param[in] dac_periph: DACx(x = 0,1) + \param[in] dac_align: data alignment + only one parameter can be selected which is shown as below: + \arg DAC_ALIGN_8B_R: data right 8 bit alignment + \arg DAC_ALIGN_12B_R: data right 12 bit alignment + \arg DAC_ALIGN_12B_L: data left 12 bit alignment + \param[in] data: data to be loaded + \param[out] none + \retval none +*/ +void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) +{ + if(DAC0 == dac_periph){ + switch(dac_align){ + /* data right 12 bit alignment */ + case DAC_ALIGN_12B_R: + DAC0_R12DH = data; + break; + /* data left 12 bit alignment */ + case DAC_ALIGN_12B_L: + DAC0_L12DH = data; + break; + /* data right 8 bit alignment */ + case DAC_ALIGN_8B_R: + DAC0_R8DH = data; + break; + default: + break; + } + }else{ + switch(dac_align){ + /* data right 12 bit alignment */ + case DAC_ALIGN_12B_R: + DAC1_R12DH = data; + break; + /* data left 12 bit alignment */ + case DAC_ALIGN_12B_L: + DAC1_L12DH = data; + break; + /* data right 8 bit alignment */ + case DAC_ALIGN_8B_R: + DAC1_R8DH = data; + break; + default: + break; + } + } +} + +/*! + \brief enable DAC trigger + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_trigger_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL |= DAC_CTL_DTEN0; + }else{ + DAC_CTL |= DAC_CTL_DTEN1; + } +} + +/*! + \brief disable DAC trigger + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_trigger_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DTEN0; + }else{ + DAC_CTL &= ~DAC_CTL_DTEN1; + } +} + +/*! + \brief set DAC trigger source + \param[in] dac_periph: DACx(x = 0,1) + \param[in] triggersource: external triggers of DAC + only one parameter can be selected which is shown as below: + \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO + \arg DAC_TRIGGER_T2_TRGO: TIMER2 TRGO + \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO + \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO + \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO + \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO + \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event + \arg DAC_TRIGGER_SOFTWARE: software trigger + \param[out] none + \retval none +*/ +void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) +{ + if(DAC0 == dac_periph){ + /* configure DAC0 trigger source */ + DAC_CTL &= ~DAC_CTL_DTSEL0; + DAC_CTL |= triggersource; + }else{ + /* configure DAC1 trigger source */ + DAC_CTL &= ~DAC_CTL_DTSEL1; + DAC_CTL |= (triggersource << DAC1_REG_OFFSET); + } +} + +/*! + \brief enable DAC software trigger + \param[in] dac_periph: DACx(x = 0,1) + \retval none +*/ +void dac_software_trigger_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_SWT |= DAC_SWT_SWTR0; + }else{ + DAC_SWT |= DAC_SWT_SWTR1; + } +} + +/*! + \brief disable DAC software trigger + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_software_trigger_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_SWT &= ~DAC_SWT_SWTR0; + }else{ + DAC_SWT &= ~DAC_SWT_SWTR1; + } +} + +/*! + \brief configure DAC wave mode + \param[in] dac_periph: DACx(x = 0,1) + \param[in] wave_mode: noise wave mode + only one parameter can be selected which is shown as below: + \arg DAC_WAVE_DISABLE: wave disable + \arg DAC_WAVE_MODE_LFSR: LFSR noise mode + \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode + \param[out] none + \retval none +*/ +void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) +{ + if(DAC0 == dac_periph){ + /* configure DAC0 wave mode */ + DAC_CTL &= ~DAC_CTL_DWM0; + DAC_CTL |= wave_mode; + }else{ + /* configure DAC1 wave mode */ + DAC_CTL &= ~DAC_CTL_DWM1; + DAC_CTL |= (wave_mode << DAC1_REG_OFFSET); + } +} + +/*! + \brief configure DAC wave bit width + \param[in] dac_periph: DACx(x = 0,1) + \param[in] bit_width: noise wave bit width + only one parameter can be selected which is shown as below: + \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 + \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 + \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 + \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4 + \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5 + \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6 + \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7 + \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8 + \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9 + \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10 + \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11 + \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12 + \param[out] none + \retval none +*/ +void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) +{ + if(DAC0 == dac_periph){ + /* configure DAC0 wave bit width */ + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= bit_width; + }else{ + /* configure DAC1 wave bit width */ + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= (bit_width << DAC1_REG_OFFSET); + } +} + +/*! + \brief configure DAC LFSR noise mode + \param[in] dac_periph: DACx(x = 0,1) + \param[in] unmask_bits: unmask LFSR bits in DAC LFSR noise mode + only one parameter can be selected which is shown as below: + \arg DAC_LFSR_BIT0: unmask the LFSR bit0 + \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] + \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] + \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0] + \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0] + \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0] + \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0] + \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0] + \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0] + \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0] + \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0] + \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0] + \param[out] none + \retval none +*/ +void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) +{ + if(DAC0 == dac_periph){ + /* configure DAC0 LFSR noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= unmask_bits; + }else{ + /* configure DAC1 LFSR noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET); + } +} + +/*! + \brief configure DAC triangle noise mode + \param[in] dac_periph: DACx(x = 0,1) + \param[in] amplitude: triangle amplitude in DAC triangle noise mode + only one parameter can be selected which is shown as below: + \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 + \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 + \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 + \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15 + \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31 + \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63 + \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127 + \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255 + \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511 + \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023 + \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047 + \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095 + \param[out] none + \retval none +*/ +void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) +{ + if(DAC0 == dac_periph){ + /* configure DAC0 triangle noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= amplitude; + }else{ + /* configure DAC1 triangle noise mode */ + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= (amplitude << DAC1_REG_OFFSET); + } +} + +/*! + \brief enable DAC concurrent mode + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_enable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; + DAC_CTL |= (ctl); +} + +/*! + \brief disable DAC concurrent mode + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_disable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; + DAC_CTL &= (~ctl); +} + +/*! + \brief enable DAC concurrent software trigger function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_software_trigger_enable(void) +{ + uint32_t swt = 0U; + swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; + DAC_SWT |= (swt); +} + +/*! + \brief disable DAC concurrent software trigger function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_software_trigger_disable(void) +{ + uint32_t swt = 0U; + swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; + DAC_SWT &= (~swt); +} + +/*! + \brief enable DAC concurrent buffer function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_output_buffer_enable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; + DAC_CTL &= (~ctl); +} + +/*! + \brief disable DAC concurrent buffer function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_output_buffer_disable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; + DAC_CTL |= (ctl); +} + +/*! + \brief set DAC concurrent mode data holding register value + \param[in] dac_align: data alignment + only one parameter can be selected which is shown as below: + \arg DAC_ALIGN_8B_R: data right 8b alignment + \arg DAC_ALIGN_12B_R: data right 12b alignment + \arg DAC_ALIGN_12B_L: data left 12b alignment + \param[in] data0: data to be loaded + \param[in] data1: data to be loaded + \param[out] none + \retval none +*/ +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) +{ + uint32_t data = 0U; + switch(dac_align){ + /* data right 12b alignment */ + case DAC_ALIGN_12B_R: + data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; + DACC_R12DH = data; + break; + /* data left 12b alignment */ + case DAC_ALIGN_12B_L: + data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; + DACC_L12DH = data; + break; + /* data right 8b alignment */ + case DAC_ALIGN_8B_R: + data = ((uint32_t)data1 << DH_8BIT_OFFSET) | data0; + DACC_R8DH = data; + break; + default: + break; + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c new file mode 100644 index 0000000..7b10a52 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c @@ -0,0 +1,110 @@ +/*! + \file gd32vf103_dbg.c + \brief DBG driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_dbg.h" + +/*! + \brief read DBG_ID code register + \param[in] none + \param[out] none + \retval DBG_ID code +*/ +uint32_t dbg_id_get(void) +{ + return DBG_ID; +} + +/*! + \brief enable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + one or more parameters can be selected which are shown as below: + \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_enable(uint32_t dbg_low_power) +{ + DBG_CTL |= dbg_low_power; +} + +/*! + \brief disable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + one or more parameters can be selected which are shown as below: + \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_disable(uint32_t dbg_low_power) +{ + DBG_CTL &= ~dbg_low_power; +} + +/*! + \brief enable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: refer to dbg_periph_enum + one or more parameters can be selected which are shown as below: + \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted + \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted + \arg DBG_CANx_HOLD (x=0,1): hold CANx counter when core is halted + \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted + \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6): hold TIMERx counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_enable(dbg_periph_enum dbg_periph) +{ + DBG_CTL |= (uint32_t)dbg_periph; +} + +/*! + \brief disable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: refer to dbg_periph_enum + one or more parameters can be selected which are shown as below: + \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted + \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted + \arg DBG_CANx_HOLD (x=0,1): hold CAN0 counter when core is halted + \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted + \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6): hold TIMERx counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_disable(dbg_periph_enum dbg_periph) +{ + DBG_CTL &= ~(uint32_t)dbg_periph; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c new file mode 100644 index 0000000..9cfa28e --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c @@ -0,0 +1,731 @@ +/*! + \file gd32vf103_dma.c + \brief DMA driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_dma.h" + +#define DMA_WRONG_HANDLE while(1){} + +/* check whether peripheral matches channels or not */ +static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx); + +/*! + \brief deinitialize DMA a channel registers + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel is deinitialized + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* disable DMA a channel */ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; + /* reset DMA channel registers */ + DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; + DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; + DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE; + DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; + DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); +} + +/*! + \brief initialize the parameters of DMA struct with the default values + \param[in] init_struct: the initialization data needed to initialize DMA channel + \param[out] none + \retval none +*/ +void dma_struct_para_init(dma_parameter_struct* init_struct) +{ + /* set the DMA struct with the default values */ + init_struct->periph_addr = 0U; + init_struct->periph_width = 0U; + init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE; + init_struct->memory_addr = 0U; + init_struct->memory_width = 0U; + init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE; + init_struct->number = 0U; + init_struct->direction = DMA_PERIPHERAL_TO_MEMORY; + init_struct->priority = DMA_PRIORITY_LOW; +} + +/*! + \brief initialize DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel is initialized + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] init_struct: the data needed to initialize DMA channel + periph_addr: peripheral base address + periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT + periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE + memory_addr: memory base address + memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT + memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE + direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL + number: the number of remaining data to be transferred by the DMA + priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH + \param[out] none + \retval none +*/ +void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct* init_struct) +{ + uint32_t ctl; + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* configure peripheral base address */ + DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr; + + /* configure memory base address */ + DMA_CHMADDR(dma_periph, channelx) = init_struct->memory_addr; + + /* configure the number of remaining data to be transferred */ + DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); + + /* configure peripheral transfer width,memory transfer width and priority */ + ctl = DMA_CHCTL(dma_periph, channelx); + ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); + ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority); + DMA_CHCTL(dma_periph, channelx) = ctl; + + /* configure peripheral increasing mode */ + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + }else{ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; + } + + /* configure memory increasing mode */ + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; + }else{ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; + } + + /* configure the direction of data transfer */ + if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; + }else{ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; + } +} + +/*! + \brief enable DMA circulation mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; +} + +/*! + \brief disable DMA circulation mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; +} + +/*! + \brief enable memory to memory mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M; +} + +/*! + \brief disable memory to memory mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M; +} + +/*! + \brief enable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN; +} + +/*! + \brief disable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; +} + +/*! + \brief set DMA peripheral base address + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set peripheral base address + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] address: peripheral base address + \param[out] none + \retval none +*/ +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHPADDR(dma_periph, channelx) = address; +} + +/*! + \brief set DMA memory base address + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set memory base address + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] address: memory base address + \param[out] none + \retval none +*/ +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHMADDR(dma_periph, channelx) = address; +} + +/*! + \brief set the number of remaining data to be transferred by the DMA + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set number + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] number: the number of remaining data to be transferred by the DMA + \param[out] none + \retval none +*/ +void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK); +} + +/*! + \brief get the number of remaining data to be transferred by the DMA + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set number + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval uint32_t: the number of remaining data to be transferred by the DMA +*/ +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + return (uint32_t)DMA_CHCNT(dma_periph, channelx); +} + +/*! + \brief configure priority level of DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] priority: priority Level of this channel + only one parameter can be selected which is shown as below: + \arg DMA_PRIORITY_LOW: low priority + \arg DMA_PRIORITY_MEDIUM: medium priority + \arg DMA_PRIORITY_HIGH: high priority + \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority + \param[out] none + \retval none +*/ +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) +{ + uint32_t ctl; + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PRIO; + ctl |= priority; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer data size of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] mwidth: transfer data width of memory + only one parameter can be selected which is shown as below: + \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit + \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit + \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit + \param[out] none + \retval none +*/ +void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth) +{ + uint32_t ctl; + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_MWIDTH; + ctl |= mwidth; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer data size of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] pwidth: transfer data width of peripheral + only one parameter can be selected which is shown as below: + \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit + \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit + \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit + \param[out] none + \retval none +*/ +void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth) +{ + uint32_t ctl; + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PWIDTH; + ctl |= pwidth; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief enable next address increasement algorithm of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; +} + +/*! + \brief disable next address increasement algorithm of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; +} + +/*! + \brief enable next address increasement algorithm of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; +} + +/*! + \brief disable next address increasement algorithm of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; +} + +/*! + \brief configure the direction of data transfer on the channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] direction: specify the direction of data transfer + only one parameter can be selected which is shown as below: + \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory + \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral + \param[out] none + \retval none +*/ +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + if(DMA_PERIPHERAL_TO_MEMORY == direction){ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; + } +} + +/*! + \brief check DMA flag is set or not + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get flag + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_G: global interrupt flag of channel + \arg DMA_FLAG_FTF: full transfer finish flag of channel + \arg DMA_FLAG_HTF: half transfer finish flag of channel + \arg DMA_FLAG_ERR: error flag of channel + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + FlagStatus reval; + + if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){ + reval = SET; + }else{ + reval = RESET; + } + + return reval; +} + +/*! + \brief clear DMA a channel flag + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to clear flag + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_G: global interrupt flag of channel + \arg DMA_FLAG_FTF: full transfer finish flag of channel + \arg DMA_FLAG_HTF: half transfer finish flag of channel + \arg DMA_FLAG_ERR: error flag of channel + \param[out] none + \retval none +*/ +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); +} + +/*! + \brief check DMA flag and interrupt enable bit is set or not + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get flag + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_ERR: error interrupt flag of channel + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + uint32_t interrupt_enable = 0U, interrupt_flag = 0U; + + switch(flag){ + case DMA_INT_FLAG_FTF: + /* check whether the full transfer finish interrupt flag is set and enabled */ + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; + break; + case DMA_INT_FLAG_HTF: + /* check whether the half transfer finish interrupt flag is set and enabled */ + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INT_FLAG_ERR: + /* check whether the error interrupt flag is set and enabled */ + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE; + break; + default: + DMA_WRONG_HANDLE + } + + /* when the interrupt flag is set and enabled, return SET */ + if(interrupt_flag && interrupt_enable){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear DMA a channel flag + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to clear flag + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_G: global interrupt flag of channel + \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_ERR: error interrupt flag of channel + \param[out] none + \retval none +*/ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); +} + +/*! + \brief enable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] source: specify which interrupt to enbale + one or more parameters can be selected which are shown as below + \arg DMA_INT_FTF: channel full transfer finish interrupt + \arg DMA_INT_HTF: channel half transfer finish interrupt + \arg DMA_INT_ERR: channel error interrupt + \param[out] none + \retval none +*/ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= source; +} + +/*! + \brief disable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] source: specify which interrupt to disbale + one or more parameters can be selected which are shown as below + \arg DMA_INT_FTF: channel full transfer finish interrupt + \arg DMA_INT_HTF: channel half transfer finish interrupt + \arg DMA_INT_ERR: channel error interrupt + \param[out] none + \retval none +*/ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~source; +} + +/*! + \brief check whether peripheral and channels match + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx) +{ + ErrStatus val = SUCCESS; + + if(DMA1 == dma_periph){ + /* for DMA1, the channel is from DMA_CH0 to DMA_CH4 */ + if(channelx > DMA_CH4){ + val = ERROR; + } + } + + return val; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c new file mode 100644 index 0000000..ad11724 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c @@ -0,0 +1,128 @@ +/*! + \file gd32vf103_eclic.c + \brief ECLIC(Enhancement Core-Local Interrupt Controller) driver + + \version 2019-06-05, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_eclic.h" +#include "riscv_encoding.h" + +#define REG_DBGMCU2 ((uint32_t)0xE0042008) +#define REG_DBGMCU2EN ((uint32_t)0xE004200C) + +/*! + \brief enable the global interrupt + \param[in] none + \param[out] none + \retval none +*/ +void eclic_global_interrupt_enable(void) +{ + /* set machine interrupt enable bit */ + set_csr(mstatus, MSTATUS_MIE); +} + +/*! + \brief disable the global interrupt + \param[in] none + \param[out] none + \retval none +*/ +void eclic_global_interrupt_disable(void) +{ + /* clear machine interrupt enable bit */ + clear_csr(mstatus, MSTATUS_MIE); +} + +/*! + \brief set the priority group + \param[in] prigroup: specify the priority group + \arg ECLIC_PRIGROUP_LEVEL0_PRIO4 + \arg ECLIC_PRIGROUP_LEVEL1_PRIO3 + \arg ECLIC_PRIGROUP_LEVEL2_PRIO2 + \arg ECLIC_PRIGROUP_LEVEL3_PRIO1 + \arg ECLIC_PRIGROUP_LEVEL4_PRIO0 + \param[out] none + \retval none +*/ +void eclic_priority_group_set(uint32_t prigroup) +{ + eclic_set_nlbits(prigroup); +} + +/*! + \brief enable the interrupt request + \param[in] source: interrupt request, detailed in IRQn_Type + \param[in] level: the level needed to set (maximum is 15, refer to the priority group) + \param[in] priority: the priority needed to set (maximum is 15, refer to the priority group) + \param[out] none + \retval none +*/ +void eclic_irq_enable(uint32_t source, uint8_t level, uint8_t priority) +{ + eclic_enable_interrupt(source); + eclic_set_irq_lvl_abs(source, level); + eclic_set_irq_priority(source, priority); +} + +/*! + \brief disable the interrupt request + \param[in] source: interrupt request, detailed in IRQn_Type + \param[out] none + \retval none +*/ +void eclic_irq_disable(uint32_t source) +{ + eclic_disable_interrupt(source); +} + +/*! + \brief reset system + \param[in] none + \param[out] none + \retval none +*/ +void eclic_system_reset(void) +{ + REG32(REG_DBGMCU2EN) = 0x4b5a6978; + REG32(REG_DBGMCU2) = 0x1; +} + +/*! + \brief send event(SEV) + \param[in] none + \param[out] none + \retval none +*/ +void eclic_send_event(void) +{ + set_csr(0x812, 0x1); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c new file mode 100644 index 0000000..c578087 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c @@ -0,0 +1,164 @@ +/*! + \file gd32vf103_exmc.c + \brief EXMC driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_exmc.h" + +/* EXMC bank0 register reset value */ +#define BANK0_SNCTL0_REGION_RESET ((uint32_t)0x000030DAU) +#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU) + +/* EXMC register bit offset */ +#define SNCTL_NRMUX_OFFSET ((uint32_t)1U) +#define SNCTL_WREN_OFFSET ((uint32_t)12U) +#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U) +#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U) + +#define SNTCFG_AHLD_OFFSET ((uint32_t)4U) +#define SNTCFG_DSET_OFFSET ((uint32_t)8U) +#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U) + +/*! + \brief deinitialize EXMC NOR/SRAM region + \param[in] norsram_region: select the region of bank0 + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0) + \param[out] none + \retval none +*/ +void exmc_norsram_deinit(uint32_t norsram_region) +{ + /* reset the registers */ + if(EXMC_BANK0_NORSRAM_REGION0 == norsram_region){ + EXMC_SNCTL(norsram_region) = BANK0_SNCTL0_REGION_RESET; + } + + EXMC_SNTCFG(norsram_region) = BANK0_SNTCFG_RESET; +} + +/*! + \brief initialize the structure exmc_norsram_parameter_struct + \param[in] none + \param[out] exmc_norsram_init_struct: the initialized structure exmc_norsram_parameter_struct pointer + \retval none +*/ +void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) +{ + /* configure the structure with default value */ + exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; + exmc_norsram_init_struct->address_data_mux = ENABLE; + exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM; + exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_16B; + exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW; + exmc_norsram_init_struct->memory_write = ENABLE; + exmc_norsram_init_struct->nwait_signal = ENABLE; + exmc_norsram_init_struct->asyn_wait = DISABLE; + + /* read/write timing configure */ + exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; + exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; + exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; + exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; +} + +/*! + \brief initialize EXMC NOR/SRAM region + \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter + norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0 + asyn_wait: ENABLE or DISABLE + nwait_signal: ENABLE or DISABLE + memory_write: ENABLE or DISABLE + nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH + databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B + memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR + address_data_mux: ENABLE + read_write_timing: structure exmc_norsram_timing_parameter_struct set the time + \param[out] none + \retval none +*/ +void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) +{ + uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U; + + /* get the register value */ + snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); + + /* clear relative bits */ + snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_NRWTPOL | + EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_NRMUX)); + + snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | + exmc_norsram_init_struct->memory_type | + exmc_norsram_init_struct->databus_width | + exmc_norsram_init_struct->nwait_polarity | + (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | + (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | + (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET); + + sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )| + (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) | + (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) | + (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT ); + + /* nor flash access enable */ + if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){ + snctl |= (uint32_t)EXMC_SNCTL_NREN; + } + + /* configure the registers */ + EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl; + EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg; +} + +/*! + \brief enable EXMC NOR/PSRAM bank region + \param[in] norsram_region: specify the region of NOR/PSRAM bank + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0) + \param[out] none + \retval none +*/ +void exmc_norsram_enable(uint32_t norsram_region) +{ + EXMC_SNCTL(norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN; +} + +/*! + \brief disable EXMC NOR/PSRAM bank region + \param[in] norsram_region: specify the region of NOR/PSRAM bank + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0) + \param[out] none + \retval none +*/ +void exmc_norsram_disable(uint32_t norsram_region) +{ + EXMC_SNCTL(norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c new file mode 100644 index 0000000..7190b23 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c @@ -0,0 +1,254 @@ +/*! + \file gd32vf103_exti.c + \brief EXTI driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_exti.h" + +#define EXTI_REG_RESET_VALUE ((uint32_t)0x00000000U) + +/*! + \brief deinitialize the EXTI + \param[in] none + \param[out] none + \retval none + */ +void exti_deinit(void) +{ + /* reset the value of all the EXTI registers */ + EXTI_INTEN = EXTI_REG_RESET_VALUE; + EXTI_EVEN = EXTI_REG_RESET_VALUE; + EXTI_RTEN = EXTI_REG_RESET_VALUE; + EXTI_FTEN = EXTI_REG_RESET_VALUE; + EXTI_SWIEV = EXTI_REG_RESET_VALUE; +} + +/*! + \brief initialize the EXTI + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..18): EXTI line x + \param[in] mode: interrupt or event mode, refer to exti_mode_enum + only one parameter can be selected which is shown as below: + \arg EXTI_INTERRUPT: interrupt mode + \arg EXTI_EVENT: event mode + \param[in] trig_type: trigger type, refer to exti_trig_type_enum + only one parameter can be selected which is shown as below: + \arg EXTI_TRIG_RISING: rising edge trigger + \arg EXTI_TRIG_FALLING: falling edge trigger + \arg EXTI_TRIG_BOTH: rising edge and falling edge trigger + \arg EXTI_TRIG_NONE: without rising edge or falling edge trigger + \param[out] none + \retval none + */ +void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type) +{ + /* reset the EXTI line x */ + EXTI_INTEN &= ~(uint32_t) linex; + EXTI_EVEN &= ~(uint32_t) linex; + EXTI_RTEN &= ~(uint32_t) linex; + EXTI_FTEN &= ~(uint32_t) linex; + + /* set the EXTI mode and enable the interrupts or events from EXTI line x */ + switch (mode) { + case EXTI_INTERRUPT: + EXTI_INTEN |= (uint32_t) linex; + break; + case EXTI_EVENT: + EXTI_EVEN |= (uint32_t) linex; + break; + default: + break; + } + + /* set the EXTI trigger type */ + switch (trig_type) { + case EXTI_TRIG_RISING: + EXTI_RTEN |= (uint32_t) linex; + EXTI_FTEN &= ~(uint32_t) linex; + break; + case EXTI_TRIG_FALLING: + EXTI_RTEN &= ~(uint32_t) linex; + EXTI_FTEN |= (uint32_t) linex; + break; + case EXTI_TRIG_BOTH: + EXTI_RTEN |= (uint32_t) linex; + EXTI_FTEN |= (uint32_t) linex; + break; + case EXTI_TRIG_NONE: + default: + break; + } +} + +/*! + \brief enable the interrupts from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..18): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_enable(exti_line_enum linex) +{ + EXTI_INTEN |= (uint32_t) linex; +} + +/*! + \brief enable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..18): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_enable(exti_line_enum linex) +{ + EXTI_EVEN |= (uint32_t) linex; +} + +/*! + \brief disable the interrupt from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..18): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_disable(exti_line_enum linex) +{ + EXTI_INTEN &= ~(uint32_t) linex; +} + +/*! + \brief disable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..18): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_disable(exti_line_enum linex) +{ + EXTI_EVEN &= ~(uint32_t) linex; +} + +/*! + \brief get EXTI lines flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..18): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_flag_get(exti_line_enum linex) +{ + if (RESET != (EXTI_PD & (uint32_t) linex)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear EXTI lines pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..18): EXTI line x + \param[out] none + \retval none +*/ +void exti_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t) linex; +} + +/*! + \brief get EXTI lines flag when the interrupt flag is set + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..18): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex) +{ + uint32_t flag_left, flag_right; + + flag_left = EXTI_PD & (uint32_t) linex; + flag_right = EXTI_INTEN & (uint32_t) linex; + + if ((RESET != flag_left) && (RESET != flag_right)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear EXTI lines pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..18): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t) linex; +} + +/*! + \brief enable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..18): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_enable(exti_line_enum linex) +{ + EXTI_SWIEV |= (uint32_t) linex; +} + +/*! + \brief disable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..18): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_disable(exti_line_enum linex) +{ + EXTI_SWIEV &= ~(uint32_t) linex; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c new file mode 100644 index 0000000..7d6a1a6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c @@ -0,0 +1,651 @@ +/*! + \file gd32vf103_fmc.c + \brief FMC driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + \version 2019-09-18, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_fmc.h" + +/*! + \brief set the FMC wait state counter + \param[in] wscnt£ºwait state counter value + \arg WS_WSCNT_0: FMC 0 wait state + \arg WS_WSCNT_1: FMC 1 wait state + \arg WS_WSCNT_2: FMC 2 wait state + \param[out] none + \retval none + */ +void fmc_wscnt_set(uint32_t wscnt) +{ + uint32_t reg; + + reg = FMC_WS; + /* set the wait state counter value */ + reg &= ~FMC_WS_WSCNT; + FMC_WS = (reg | wscnt); +} + +/*! + \brief unlock the main FMC operation + \param[in] none + \param[out] none + \retval none + */ +void fmc_unlock(void) +{ + if((RESET != (FMC_CTL & FMC_CTL_LK))){ + /* write the FMC unlock key */ + FMC_KEY = UNLOCK_KEY0; + FMC_KEY = UNLOCK_KEY1; + } +} + +/*! + \brief lock the main FMC operation + \param[in] none + \param[out] none + \retval none + */ +void fmc_lock(void) +{ + /* set the LK bit */ + FMC_CTL |= FMC_CTL_LK; +} + + +/*! + \brief FMC erase page + \param[in] page_address: the page address to be erased. + \param[out] none + \retval state of FMC, refer to fmc_state_enum + */ +fmc_state_enum fmc_page_erase(uint32_t page_address) +{ + fmc_state_enum fmc_state; + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + /* if the last operation is completed, start page erase */ + if (FMC_READY == fmc_state) { + FMC_CTL |= FMC_CTL_PER; + FMC_ADDR = page_address; + FMC_CTL |= FMC_CTL_START; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PER bit */ + FMC_CTL &= ~FMC_CTL_PER; + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief FMC erase whole chip + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum + */ +fmc_state_enum fmc_mass_erase(void) +{ + fmc_state_enum fmc_state; + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* start whole chip erase */ + FMC_CTL |= FMC_CTL_MER; + FMC_CTL |= FMC_CTL_START; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL &= ~FMC_CTL_MER; + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief FMC program a word at the corresponding address + \param[in] address: address to program + \param[in] data: word to program + \param[out] none + \retval state of FMC, refer to fmc_state_enum + */ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) +{ + fmc_state_enum fmc_state = FMC_READY; + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL |= FMC_CTL_PG; + REG32(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL &= ~FMC_CTL_PG; + } + /* return the FMC state */ + return fmc_state; +} +/* + \brief FMC program a half word at the corresponding address + \param[in] address: address to program + \param[in] data: halfword to program + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) +{ + fmc_state_enum fmc_state = FMC_READY; + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL |= FMC_CTL_PG; + REG16(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL &= ~FMC_CTL_PG; + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief unlock the option byte operation + \param[in] none + \param[out] none + \retval none + */ +void ob_unlock(void) +{ + if(RESET == (FMC_CTL & FMC_CTL_OBWEN)){ + /* write the FMC key */ + FMC_OBKEY = UNLOCK_KEY0; + FMC_OBKEY = UNLOCK_KEY1; + } + + /* wait until OBWEN bit is set by hardware */ + while (RESET == (FMC_CTL & FMC_CTL_OBWEN)){ + } +} + +/*! + \brief lock the option byte operation + \param[in] none + \param[out] none + \retval none + */ +void ob_lock(void) +{ + /* reset the OBWEN bit */ + FMC_CTL &= ~FMC_CTL_OBWEN; +} + +/*! + \brief erase the FMC option byte + unlock the FMC_CTL and option byte before calling this function + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum + */ +fmc_state_enum ob_erase(void) +{ + uint16_t temp_spc = FMC_NSPC; + + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* check the option byte security protection value */ + if(RESET != ob_spc_get()){ + temp_spc = FMC_USPC; + } + + if(FMC_READY == fmc_state){ + + /* start erase the option byte */ + FMC_CTL |= FMC_CTL_OBER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + /* set the OBPG bit */ + FMC_CTL |= FMC_CTL_OBPG; + /* no security protection */ + OB_SPC = (uint16_t) temp_spc; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + if (FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + }else{ + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief enable write protection + \param[in] ob_wp: specify sector to be write protected, set the bit to 1 if + you want to protect the corresponding pages. meanwhile, sector + macro could used to set specific sector write protected. + one or more parameters can be selected which are shown as below: + \arg OB_WP_x(x = 0..31): write protect specify sector + \arg OB_WP_ALL: write protect all sector + \param[out] none + \retval state of FMC, refer to fmc_state_enum + */ +fmc_state_enum ob_write_protection_enable(uint32_t ob_wp) +{ + uint16_t temp_wp0, temp_wp1, temp_wp2, temp_wp3; + + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + ob_wp = (uint32_t) (~ob_wp); + temp_wp0 = (uint16_t) (ob_wp & OB_WP0_WP0); + temp_wp1 = (uint16_t) ((ob_wp & OB_WP1_WP1) >> 8U); + temp_wp2 = (uint16_t) ((ob_wp & OB_WP2_WP2) >> 16U); + temp_wp3 = (uint16_t) ((ob_wp & OB_WP3_WP3) >> 24U); + + if(FMC_READY == fmc_state){ + + /* set the OBPG bit*/ + FMC_CTL |= FMC_CTL_OBPG; + + if(0xFFU != temp_wp0){ + OB_WP0 = temp_wp0; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + } + if((FMC_READY == fmc_state) && (0xFFU != temp_wp1)){ + OB_WP1 = temp_wp1; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + } + if((FMC_READY == fmc_state) && (0xFFU != temp_wp2)){ + OB_WP2 = temp_wp2; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + } + if((FMC_READY == fmc_state) && (0xFFU != temp_wp3)){ + OB_WP3 = temp_wp3; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + } + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief configure security protection + \param[in] ob_spc: specify security protection + only one parameter can be selected which is shown as below: + \arg FMC_NSPC: no security protection + \arg FMC_USPC: under security protection + \param[out] none + \retval state of FMC, refer to fmc_state_enum + */ +fmc_state_enum ob_security_protection_config(uint8_t ob_spc) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + FMC_CTL |= FMC_CTL_OBER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + + /* start the option byte program */ + FMC_CTL |= FMC_CTL_OBPG; + + OB_SPC = (uint16_t) ob_spc; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if (FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + }else{ + if (FMC_TOERR != fmc_state) { + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program the FMC user option byte + \param[in] ob_fwdgt: option byte watchdog value + \arg OB_FWDGT_SW: software free watchdog + \arg OB_FWDGT_HW: hardware free watchdog + \param[in] ob_deepsleep: option byte deepsleep reset value + \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode + \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode + \param[in] ob_stdby:option byte standby reset value + \arg OB_STDBY_NRST: no reset when entering standby mode + \arg OB_STDBY_RST: generate a reset instead of entering standby mode + \param[in] ob_boot: specifies the option byte boot bank value + \arg OB_BOOT_B0: boot from bank0 + \param[out] none + \retval state of FMC, refer to fmc_state_enum + */ +fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot) +{ + fmc_state_enum fmc_state = FMC_READY; + uint8_t temp; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the OBPG bit*/ + FMC_CTL |= FMC_CTL_OBPG; + + temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK); + OB_USER = (uint16_t) temp; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program the FMC data option byte + \param[in] address: the option bytes address to be programmed + \param[in] data: the byte to be programmed + \param[out] none + \retval state of FMC, refer to fmc_state_enum + */ +fmc_state_enum ob_data_program(uint32_t address, uint8_t data) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the OBPG bit */ + FMC_CTL |= FMC_CTL_OBPG; + REG16(address) = data; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief get OB_USER in register FMC_OBSTAT + \param[in] none + \param[out] none + \retval the FMC user option byte values + */ +uint8_t ob_user_get(void) +{ + /* return the FMC user option byte value */ + return (uint8_t) (FMC_OBSTAT >> 2U); +} + +/*! + \brief get OB_DATA in register FMC_OBSTAT + \param[in] none + \param[out] none + \retval ob_data + */ +uint16_t ob_data_get(void) +{ + return (uint16_t) (FMC_OBSTAT >> 10U); +} + +/*! + \brief get the FMC option byte write protection + \param[in] none + \param[out] none + \retval the FMC write protection option byte value + */ +uint32_t ob_write_protection_get(void) +{ + /* return the FMC write protection option byte value */ + return FMC_WP; +} + +/*! + \brief get FMC option byte security protection state + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET + */ +FlagStatus ob_spc_get(void) +{ + FlagStatus spc_state = RESET; + + if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)){ + spc_state = SET; + }else{ + spc_state = RESET; + } + return spc_state; +} + +/*! + \brief enable FMC interrupt + \param[in] interrupt: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_INT_END: enable FMC end of program interrupt + \arg FMC_INT_ERR: enable FMC error interrupt + \param[out] none + \retval none + */ +void fmc_interrupt_enable(uint32_t interrupt) +{ + FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt)); +} + +/*! + \brief disable FMC interrupt + \param[in] interrupt: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_INT_END: enable FMC end of program interrupt + \arg FMC_INT_ERR: enable FMC error interrupt + \param[out] none + \retval none + */ +void fmc_interrupt_disable(uint32_t interrupt) +{ + FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt)); +} + +/*! + \brief check flag is set or not + \param[in] flag: check FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_BUSY: FMC busy flag bit + \arg FMC_FLAG_PGERR: FMC operation error flag bit + \arg FMC_FLAG_WPERR: FMC erase/program protection error flag bit + \arg FMC_FLAG_END: FMC end of operation flag bit + \arg FMC_FLAG_OBERR: FMC option byte read error flag bit + \param[out] none + \retval FlagStatus: SET or RESET + */ +FlagStatus fmc_flag_get(uint32_t flag) +{ + if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))){ + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the FMC flag + \param[in] flag: clear FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_PGERR: FMC operation error flag bit + \arg FMC_FLAG_WPERR: FMC erase/program protection error flag bit + \arg FMC_FLAG_END: FMC end of operation flag bit + \param[out] none + \retval none + */ +void fmc_flag_clear(uint32_t flag) +{ + FMC_REG_VAL(flag) = (!FMC_REG_VAL(flag)) | BIT(FMC_BIT_POS(flag)); +} + +/*! + \brief get FMC interrupt flag state + \param[in] flag: FMC interrupt flags, refer to fmc_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg FMC_INT_FLAG_PGERR: FMC operation error interrupt flag bit + \arg FMC_INT_FLAG_WPERR: FMC erase/program protection error interrupt flag bit + \arg FMC_INT_FLAG_END: FMC end of operation interrupt flag bit + \param[out] none + \retval FlagStatus: SET or RESET + */ +FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag) +{ + FlagStatus ret1 = RESET; + FlagStatus ret2 = RESET; + + if(FMC_STAT_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){ + /* get the staus of interrupt flag */ + ret1 = (FlagStatus) (FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); + /* get the staus of interrupt enale bit */ + ret2 = (FlagStatus) (FMC_CTL & BIT(FMC_BIT_POS1(flag))); + } + + if(ret1 && ret2){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear FMC interrupt flag state + \param[in] flag: FMC interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg FMC_INT_FLAG_PGERR: FMC operation error interrupt flag bit + \arg FMC_INT_FLAG_WPERR: FMC erase/program protection error interrupt flag bit + \arg FMC_INT_FLAG_END: FMC end of operation interrupt flag bit + \param[out] none + \retval none + */ +void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag) +{ + FMC_REG_VALS(flag) |= BIT(FMC_BIT_POS0(flag)); +} + +/*! + \brief get the FMC state + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum + */ +fmc_state_enum fmc_state_get(void) +{ + fmc_state_enum fmc_state = FMC_READY; + + if((uint32_t) 0x00U != (FMC_STAT & FMC_STAT_BUSY)){ + fmc_state = FMC_BUSY; + }else{ + if((uint32_t) 0x00U != (FMC_STAT & FMC_STAT_WPERR)){ + fmc_state = FMC_WPERR; + }else{ + if((uint32_t) 0x00U != (FMC_STAT & (FMC_STAT_PGERR))){ + fmc_state = FMC_PGERR; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief check whether FMC is ready or not + \param[in] timeout: count of loop + \param[out] none + \retval state of FMC, refer to fmc_state_enum + */ +fmc_state_enum fmc_ready_wait(uint32_t timeout) +{ + fmc_state_enum fmc_state = FMC_BUSY; + + /* wait for FMC ready */ + do{ + /* get FMC state */ + fmc_state = fmc_state_get(); + timeout--; + }while((FMC_BUSY == fmc_state) && (0x00U != timeout)); + + if(FMC_BUSY == fmc_state){ + fmc_state = FMC_TOERR; + } + /* return the FMC state */ + return fmc_state; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c new file mode 100644 index 0000000..c49ca54 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c @@ -0,0 +1,151 @@ +/*! + \file gd32vf103_fwdgt.c + \brief FWDGT driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_fwdgt.h" + +/* write value to FWDGT_CTL_CMD bit field */ +#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) +/* write value to FWDGT_RLD_RLD bit field */ +#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) + +/*! + \brief enable write access to FWDGT_PSC and FWDGT_RLD + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_enable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; +} + +/*! + \brief disable write access to FWDGT_PSC and FWDGT_RLD + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_disable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; +} + +/*! + \brief start the free watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_enable(void) +{ + FWDGT_CTL = FWDGT_KEY_ENABLE; +} + +/*! + \brief reload the counter of FWDGT + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_counter_reload(void) +{ + FWDGT_CTL = FWDGT_KEY_RELOAD; +} + +/*! + \brief configure counter reload value, and prescaler divider value + \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) + \param[in] prescaler_div: FWDGT prescaler value + only one parameter can be selected which is shown as below: + \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 + \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 + \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 + \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 + \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 + \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 + \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) +{ + uint32_t timeout = FWDGT_PSC_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_PSC,and FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + /* wait until the PUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if((uint32_t)RESET != flag_status){ + return ERROR; + } + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_div; + + timeout = FWDGT_RLD_TIMEOUT; + /* wait until the RUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if((uint32_t)RESET != flag_status){ + return ERROR; + } + FWDGT_RLD = RLD_RLD(reload_value); + /* reload the counter */ + FWDGT_CTL = FWDGT_KEY_RELOAD; + + return SUCCESS; +} + +/*! + \brief get flag state of FWDGT + \param[in] flag: flag to get + only one parameter can be selected which is shown as below: + \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going + \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fwdgt_flag_get(uint16_t flag) +{ + if(FWDGT_STAT & flag){ + return SET; + } + + return RESET; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c new file mode 100644 index 0000000..9b1f5a6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c @@ -0,0 +1,502 @@ +/*! + \file gd32vf103_gpio.c + \brief GPIO driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_gpio.h" + +#define AFIO_EXTI_SOURCE_MASK ((uint8_t)0x03U) /*!< AFIO exti source selection mask*/ +#define AFIO_EXTI_SOURCE_FIELDS ((uint8_t)0x04U) /*!< select AFIO exti source registers */ +#define LSB_16BIT_MASK ((uint16_t)0xFFFFU) /*!< LSB 16-bit mask */ +#define PCF_POSITION_MASK ((uint32_t)0x000F0000U) /*!< AFIO_PCF register position mask */ +#define PCF_SWJCFG_MASK ((uint32_t)0xF0FFFFFFU) /*!< AFIO_PCF register SWJCFG mask */ +#define PCF_LOCATION1_MASK ((uint32_t)0x00200000U) /*!< AFIO_PCF register location1 mask */ +#define PCF_LOCATION2_MASK ((uint32_t)0x00100000U) /*!< AFIO_PCF register location2 mask */ +#define AFIO_PCF1_FIELDS ((uint32_t)0x80000000U) /*!< select AFIO_PCF1 register */ +#define GPIO_OUTPUT_PORT_OFFSET ((uint32_t)4U) /*!< GPIO event output port offset*/ + +/*! + \brief reset GPIO port + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) + \param[out] none + \retval none +*/ +void gpio_deinit(uint32_t gpio_periph) +{ + switch (gpio_periph) { + case GPIOA: + /* reset GPIOA */ + rcu_periph_reset_enable(RCU_GPIOARST); + rcu_periph_reset_disable(RCU_GPIOARST); + break; + case GPIOB: + /* reset GPIOB */ + rcu_periph_reset_enable(RCU_GPIOBRST); + rcu_periph_reset_disable(RCU_GPIOBRST); + break; + case GPIOC: + /* reset GPIOC */ + rcu_periph_reset_enable(RCU_GPIOCRST); + rcu_periph_reset_disable(RCU_GPIOCRST); + break; + case GPIOD: + /* reset GPIOD */ + rcu_periph_reset_enable(RCU_GPIODRST); + rcu_periph_reset_disable(RCU_GPIODRST); + break; + case GPIOE: + /* reset GPIOE */ + rcu_periph_reset_enable(RCU_GPIOERST); + rcu_periph_reset_disable(RCU_GPIOERST); + break; + default: + break; + } +} + +/*! + \brief reset alternate function I/O(AFIO) + \param[in] none + \param[out] none + \retval none +*/ +void gpio_afio_deinit(void) +{ + rcu_periph_reset_enable(RCU_AFRST); + rcu_periph_reset_disable(RCU_AFRST); +} + +/*! + \brief GPIO parameter initialization + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) + \param[in] mode: gpio pin mode + only one parameter can be selected which is shown as below: + \arg GPIO_MODE_AIN: analog input mode + \arg GPIO_MODE_IN_FLOATING: floating input mode + \arg GPIO_MODE_IPD: pull-down input mode + \arg GPIO_MODE_IPU: pull-up input mode + \arg GPIO_MODE_OUT_OD: GPIO output with open-drain + \arg GPIO_MODE_OUT_PP: GPIO output with push-pull + \arg GPIO_MODE_AF_OD: AFIO output with open-drain + \arg GPIO_MODE_AF_PP: AFIO output with push-pull + \param[in] speed: gpio output max speed value + only one parameter can be selected which is shown as below: + \arg GPIO_OSPEED_10MHZ: output max speed 10MHz + \arg GPIO_OSPEED_2MHZ: output max speed 2MHz + \arg GPIO_OSPEED_50MHZ: output max speed 50MHz + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + + \param[out] none + \retval none +*/ +void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, + uint32_t pin) +{ + uint16_t i; + uint32_t temp_mode = 0U; + uint32_t reg = 0U; + + /* GPIO mode configuration */ + temp_mode = (uint32_t) (mode & ((uint32_t) 0x0FU)); + + /* GPIO speed configuration */ + if (((uint32_t) 0x00U) != ((uint32_t) mode & ((uint32_t) 0x10U))) { + /* output mode max speed:10MHz,2MHz,50MHz */ + temp_mode |= (uint32_t) speed; + } + + /* configure the eight low port pins with GPIO_CTL0 */ + for (i = 0U; i < 8U; i++) { + if ((1U << i) & pin) { + reg = GPIO_CTL0(gpio_periph); + + /* clear the specified pin mode bits */ + reg &= ~GPIO_MODE_MASK(i); + /* set the specified pin mode bits */ + reg |= GPIO_MODE_SET(i, temp_mode); + + /* set IPD or IPU */ + if (GPIO_MODE_IPD == mode) { + /* reset the corresponding OCTL bit */ + GPIO_BC(gpio_periph) = (uint32_t) ((1U << i) & pin); + } else { + /* set the corresponding OCTL bit */ + if (GPIO_MODE_IPU == mode) { + GPIO_BOP(gpio_periph) = (uint32_t) ((1U << i) & pin); + } + } + /* set GPIO_CTL0 register */ + GPIO_CTL0(gpio_periph) = reg; + } + } + /* configure the eight high port pins with GPIO_CTL1 */ + for (i = 8U; i < 16U; i++) { + if ((1U << i) & pin) { + reg = GPIO_CTL1(gpio_periph); + + /* clear the specified pin mode bits */ + reg &= ~GPIO_MODE_MASK(i - 8U); + /* set the specified pin mode bits */ + reg |= GPIO_MODE_SET(i - 8U, temp_mode); + + /* set IPD or IPU */ + if (GPIO_MODE_IPD == mode) { + /* reset the corresponding OCTL bit */ + GPIO_BC(gpio_periph) = (uint32_t) ((1U << i) & pin); + } else { + /* set the corresponding OCTL bit */ + if (GPIO_MODE_IPU == mode) { + GPIO_BOP(gpio_periph) = (uint32_t) ((1U << i) & pin); + } + } + /* set GPIO_CTL1 register */ + GPIO_CTL1(gpio_periph) = reg; + } + } +} + +/*! + \brief set GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BOP(gpio_periph) = (uint32_t) pin; +} + +/*! + \brief reset GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BC(gpio_periph) = (uint32_t) pin; +} + +/*! + \brief write data to the specified GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] bit_value: SET or RESET + only one parameter can be selected which is shown as below: + \arg RESET: clear the port pin + \arg SET: set the port pin + \param[out] none + \retval none +*/ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) +{ + if (RESET != bit_value) { + GPIO_BOP(gpio_periph) = (uint32_t) pin; + } else { + GPIO_BC(gpio_periph) = (uint32_t) pin; + } +} + +/*! + \brief write data to the specified GPIO port + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) + \param[in] data: specify the value to be written to the port output data register + \param[out] none + \retval none +*/ +void gpio_port_write(uint32_t gpio_periph, uint16_t data) +{ + GPIO_OCTL(gpio_periph) = (uint32_t) data; +} + +/*! + \brief get GPIO pin input status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) + \param[in] pin: GPIO pin + only one parameter can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval input status of gpio pin: SET or RESET +*/ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) +{ + if ((uint32_t) RESET != (GPIO_ISTAT(gpio_periph) & (pin))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief get GPIO port input status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) + \param[out] none + \retval input status of gpio all pins +*/ +uint16_t gpio_input_port_get(uint32_t gpio_periph) +{ + return (uint16_t) (GPIO_ISTAT(gpio_periph)); +} + +/*! + \brief get GPIO pin output status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) + \param[in] pin: GPIO pin + only one parameter can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval output status of gpio pin: SET or RESET +*/ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) +{ + if ((uint32_t) RESET != (GPIO_OCTL(gpio_periph) & (pin))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief get GPIO port output status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) + \param[out] none + \retval output status of gpio all pins +*/ +uint16_t gpio_output_port_get(uint32_t gpio_periph) +{ + return ((uint16_t) GPIO_OCTL(gpio_periph)); +} + +/*! + \brief configure GPIO pin remap + \param[in] gpio_remap: select the pin to remap + only one parameter can be selected which are shown as below: + \arg GPIO_SPI0_REMAP: SPI0 remapping + \arg GPIO_I2C0_REMAP: I2C0 remapping + \arg GPIO_USART0_REMAP: USART0 remapping + \arg GPIO_USART1_REMAP: USART1 remapping + \arg GPIO_USART2_PARTIAL_REMAP: USART2 partial remapping + \arg GPIO_USART2_FULL_REMAP: USART2 full remapping + \arg GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping + \arg GPIO_TIMER0_FULL_REMAP: TIMER0 full remapping + \arg GPIO_TIMER1_PARTIAL_REMAP0: TIMER1 partial remapping + \arg GPIO_TIMER1_PARTIAL_REMAP1: TIMER1 partial remapping + \arg GPIO_TIMER1_FULL_REMAP: TIMER1 full remapping + \arg GPIO_TIMER2_PARTIAL_REMAP: TIMER2 partial remapping + \arg GPIO_TIMER2_FULL_REMAP: TIMER2 full remapping + \arg GPIO_TIMER3_REMAP: TIMER3 remapping + \arg GPIO_CAN0_PARTIAL_REMAP: CAN0 partial remapping + \arg GPIO_CAN0_FULL_REMAP: CAN0 full remapping + \arg GPIO_PD01_REMAP: PD01 remapping + \arg GPIO_TIMER4CH3_IREMAP: TIMER4 channel3 internal remapping + \arg GPIO_CAN1_REMAP: CAN1 remapping + \arg GPIO_SWJ_NONJTRST_REMAP: JTAG-DP,but without NJTRST + \arg GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled + \arg GPIO_SPI2_REMAP: SPI2 remapping + \arg GPIO_TIMER1ITI1_REMAP: TIMER1 internal trigger 1 remapping + \arg GPIO_EXMC_NADV_REMAP: EXMC_NADV connect/disconnect + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue) +{ + uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U; + + if (AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)) { + /* get AFIO_PCF1 regiter value */ + temp_reg = AFIO_PCF1; + } else { + /* get AFIO_PCF0 regiter value */ + temp_reg = AFIO_PCF0; + } + + temp_mask = (remap & PCF_POSITION_MASK) >> 0x10U; + remap1 = remap & LSB_16BIT_MASK; + + /* judge pin remap type */ + if ((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) + == (remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))) { + temp_reg &= PCF_SWJCFG_MASK; + AFIO_PCF0 &= PCF_SWJCFG_MASK; + } else if (PCF_LOCATION2_MASK == (remap & PCF_LOCATION2_MASK)) { + remap2 = ((uint32_t) 0x03U) << temp_mask; + temp_reg &= ~remap2; + temp_reg |= ~PCF_SWJCFG_MASK; + } else { + temp_reg &= ~(remap1 << ((remap >> 0x15U) * 0x10U)); + temp_reg |= ~PCF_SWJCFG_MASK; + } + + /* set pin remap value */ + if (DISABLE != newvalue) { + temp_reg |= (remap1 << ((remap >> 0x15U) * 0x10U)); + } + + if (AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)) { + /* set AFIO_PCF1 regiter value */ + AFIO_PCF1 = temp_reg; + } else { + /* set AFIO_PCF0 regiter value */ + AFIO_PCF0 = temp_reg; + } +} + +/*! + \brief select GPIO pin exti sources + \param[in] gpio_outputport: gpio event output port + only one parameter can be selected which are shown as below: + \arg GPIO_PORT_SOURCE_GPIOA: output port source A + \arg GPIO_PORT_SOURCE_GPIOB: output port source B + \arg GPIO_PORT_SOURCE_GPIOC: output port source C + \arg GPIO_PORT_SOURCE_GPIOD: output port source D + \arg GPIO_PORT_SOURCE_GPIOE: output port source E + \param[in] gpio_outputpin: GPIO_PIN_SOURCE_x(x=0..15) + \param[out] none + \retval none +*/ +void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin) +{ + uint32_t source = 0U; + source = ((uint32_t) 0x0FU) + << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)); + + /* select EXTI sources */ + if (GPIO_PIN_SOURCE_4 > output_pin) { + /* select EXTI0/EXTI1/EXTI2/EXTI3 */ + AFIO_EXTISS0 &= ~source; + AFIO_EXTISS0 |= (((uint32_t) output_port) + << (AFIO_EXTI_SOURCE_FIELDS + * (output_pin & AFIO_EXTI_SOURCE_MASK))); + } else if (GPIO_PIN_SOURCE_8 > output_pin) { + /* select EXTI4/EXTI5/EXTI6/EXTI7 */ + AFIO_EXTISS1 &= ~source; + AFIO_EXTISS1 |= (((uint32_t) output_port) + << (AFIO_EXTI_SOURCE_FIELDS + * (output_pin & AFIO_EXTI_SOURCE_MASK))); + } else if (GPIO_PIN_SOURCE_12 > output_pin) { + /* select EXTI8/EXTI9/EXTI10/EXTI11 */ + AFIO_EXTISS2 &= ~source; + AFIO_EXTISS2 |= (((uint32_t) output_port) + << (AFIO_EXTI_SOURCE_FIELDS + * (output_pin & AFIO_EXTI_SOURCE_MASK))); + } else { + /* select EXTI12/EXTI13/EXTI14/EXTI15 */ + AFIO_EXTISS3 &= ~source; + AFIO_EXTISS3 |= (((uint32_t) output_port) + << (AFIO_EXTI_SOURCE_FIELDS + * (output_pin & AFIO_EXTI_SOURCE_MASK))); + } +} + +/*! + \brief configure GPIO pin event output + \param[in] output_port: gpio event output port + only one parameter can be selected which are shown as below: + \arg GPIO_EVENT_PORT_GPIOA: event output port A + \arg GPIO_EVENT_PORT_GPIOB: event output port B + \arg GPIO_EVENT_PORT_GPIOC: event output port C + \arg GPIO_EVENT_PORT_GPIOD: event output port D + \arg GPIO_EVENT_PORT_GPIOE: event output port E + \param[in] output_pin: + only one parameter can be selected which are shown as below: + \arg GPIO_EVENT_PIN_x(x=0..15) + \param[out] none + \retval none +*/ +void gpio_event_output_config(uint8_t output_port, uint8_t output_pin) +{ + uint32_t reg = 0U; + reg = AFIO_EC; + + /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */ + reg &= (uint32_t) (~(AFIO_EC_PORT | AFIO_EC_PIN)); + + reg |= (uint32_t) ((uint32_t) output_port << GPIO_OUTPUT_PORT_OFFSET); + reg |= (uint32_t) output_pin; + + AFIO_EC = reg; +} + +/*! + \brief enable GPIO pin event output + \param[in] none + \param[out] none + \retval none +*/ +void gpio_event_output_enable(void) +{ + AFIO_EC |= AFIO_EC_EOE; +} + +/*! + \brief disable GPIO pin event output + \param[in] none + \param[out] none + \retval none +*/ +void gpio_event_output_disable(void) +{ + AFIO_EC &= (uint32_t) (~AFIO_EC_EOE); +} + +/*! + \brief lock GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) +{ + uint32_t lock = 0x00010000U; + lock |= pin; + + /* lock key writing sequence: write 1 -> write 0 -> write 1 -> read 0 -> read 1 */ + GPIO_LOCK(gpio_periph) = (uint32_t) lock; + GPIO_LOCK(gpio_periph) = (uint32_t) pin; + GPIO_LOCK(gpio_periph) = (uint32_t) lock; + lock = GPIO_LOCK(gpio_periph); + lock = GPIO_LOCK(gpio_periph); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c new file mode 100644 index 0000000..5a4591e --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c @@ -0,0 +1,730 @@ +/*! + \file gd32vf103_i2c.c + \brief I2C driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + \version 2019-09-18, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_i2c.h" + +/* I2C register bit mask */ +#define I2CCLK_MAX ((uint32_t)0x00000036U) /*!< i2cclk maximum value */ +#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ +#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ +#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ +#define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */ + +/* I2C register bit offset */ +#define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */ + +/*! + \brief reset I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none + */ +void i2c_deinit(uint32_t i2c_periph) +{ + switch (i2c_periph) { + case I2C0: + /* reset I2C0 */ + rcu_periph_reset_enable(RCU_I2C0RST); + rcu_periph_reset_disable(RCU_I2C0RST); + break; + case I2C1: + /* reset I2C1 */ + rcu_periph_reset_enable(RCU_I2C1RST); + rcu_periph_reset_disable(RCU_I2C1RST); + break; + default: + break; + } +} + +/*! + \brief configure I2C clock + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) + and fast mode plus (up to 1MHz) + \param[in] dutycyc: duty cycle in fast mode or fast mode plus + only one parameter can be selected which is shown as below: + \arg I2C_DTCY_2: T_low/T_high=2 + \arg I2C_DTCY_16_9: T_low/T_high=16/9 + \param[out] none + \retval none + */ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) +{ + uint32_t pclk1, clkc, freq, risetime; + uint32_t temp; + + pclk1 = rcu_clock_freq_get(CK_APB1); + /* I2C peripheral clock frequency */ + freq = (uint32_t) (pclk1 / 1000000U); + if (freq >= I2CCLK_MAX) { + freq = I2CCLK_MAX; + } + temp = I2C_CTL1(i2c_periph); + temp &= ~I2C_CTL1_I2CCLK; + temp |= freq; + + I2C_CTL1(i2c_periph) = temp; + + if (100000U >= clkspeed) { + /* the maximum SCL rise time is 1000ns in standard mode */ + risetime = (uint32_t) ((pclk1 / 1000000U) + 1U); + if (risetime >= I2CCLK_MAX) { + I2C_RT(i2c_periph) = I2CCLK_MAX; + } else if (risetime <= I2CCLK_MIN) { + I2C_RT(i2c_periph) = I2CCLK_MIN; + } else { + I2C_RT(i2c_periph) = risetime; + } + clkc = (uint32_t) (pclk1 / (clkspeed * 2U)); + if (clkc < 0x04U) { + /* the CLKC in standard mode minmum value is 4 */ + clkc = 0x04U; + } + I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); + + } else if (400000U >= clkspeed) { + /* the maximum SCL rise time is 300ns in fast mode */ + I2C_RT(i2c_periph) = (uint32_t) (((freq * (uint32_t) 300U)/(uint32_t)1000U)+(uint32_t)1U); + if (I2C_DTCY_2 == dutycyc){ + /* I2C duty cycle is 2 */ + clkc = (uint32_t) (pclk1 / (clkspeed * 3U)); + I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; + } else { + /* I2C duty cycle is 16/9 */ + clkc = (uint32_t) (pclk1 / (clkspeed * 25U)); + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; + } + if (0U == (clkc & I2C_CKCFG_CLKC)) { + /* the CLKC in fast mode minmum value is 1 */ + clkc |= 0x0001U; + } + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; + I2C_CKCFG(i2c_periph) |= clkc; + } else { + /* fast mode plus, the maximum SCL rise time is 120ns */ + I2C_RT (i2c_periph) = (uint32_t) (((freq * (uint32_t) 120U) / (uint32_t) 1000U)+(uint32_t) 1U); + if (I2C_DTCY_2 == dutycyc) { + /* I2C duty cycle is 2 */ + clkc = (uint32_t) (pclk1 / (clkspeed * 3U)); + I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; + } else { + /* I2C duty cycle is 16/9 */ + clkc = (uint32_t) (pclk1 / (clkspeed * 25U)); + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; + } + /* enable fast mode */ + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; + I2C_CKCFG(i2c_periph) |= clkc; + /* enable I2C fast mode plus */ + I2C_FMPCFG(i2c_periph) |= I2C_FMPCFG_FMPEN; + } +} + +/*! + \brief configure I2C address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] mode: + only one parameter can be selected which is shown as below: + \arg I2C_I2CMODE_ENABLE: I2C mode + \arg I2C_SMBUSMODE_ENABLE: SMBus mode + \param[in] addformat: 7bits or 10bits + only one parameter can be selected which is shown as below: + \arg I2C_ADDFORMAT_7BITS: 7bits + \arg I2C_ADDFORMAT_10BITS: 10bits + \param[in] addr: I2C address + \param[out] none + \retval none + */ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode,uint32_t addformat, uint32_t addr) +{ + /* SMBus/I2C mode selected */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SMBEN); + ctl |= mode; + I2C_CTL0(i2c_periph) = ctl; + /* configure address */ + addr = addr & I2C_ADDRESS_MASK; + I2C_SADDR0(i2c_periph) = (addformat | addr); +} + +/*! + \brief SMBus type selection + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] type: + only one parameter can be selected which is shown as below: + \arg I2C_SMBUS_DEVICE: device + \arg I2C_SMBUS_HOST: host + \param[out] none + \retval none + */ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) +{ + if (I2C_SMBUS_HOST == type) { + I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; + } else { + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); + } +} + +/*! + \brief whether or not to send an ACK + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] ack: + only one parameter can be selected which is shown as below: + \arg I2C_ACK_ENABLE: ACK will be sent + \arg I2C_ACK_DISABLE: ACK will not be sent + \param[out] none + \retval none + */ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) +{ + if (I2C_ACK_ENABLE == ack) { + I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; + } else { + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); + } +} + +/*! + \brief configure I2C POAP position + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pos: + only one parameter can be selected which is shown as below: + \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current + \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte + \param[out] none + \retval none + */ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) +{ + /* configure I2C POAP position */ + if (I2C_ACKPOS_NEXT == pos) { + I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; + } else { + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); + } +} + +/*! + \brief master sends slave address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] addr: slave address + \param[in] trandirection: transmitter or receiver + only one parameter can be selected which is shown as below: + \arg I2C_TRANSMITTER: transmitter + \arg I2C_RECEIVER: receiver + \param[out] none + \retval none + */ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr,uint32_t trandirection) +{ + /* master is a transmitter or a receiver */ + if (I2C_TRANSMITTER == trandirection) { + addr = addr & I2C_TRANSMITTER; + } else { + addr = addr | I2C_RECEIVER; + } + /* send slave address */ + I2C_DATA(i2c_periph) = addr; +} + +/*! + \brief enable dual-address mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] addr: the second address in dual-address mode + \param[out] none + \retval none +*/ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr) +{ + /* configure address */ + addr = addr & I2C_ADDRESS2_MASK; + I2C_SADDR1(i2c_periph) = (I2C_SADDR1_DUADEN | addr); +} + +/*! + \brief disable dual-address mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_dualaddr_disable(uint32_t i2c_periph) +{ + I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); +} + +/*! + \brief enable I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none + */ +void i2c_enable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; +} + +/*! + \brief disable I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none + */ +void i2c_disable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); +} + +/*! + \brief generate a START condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none + */ +void i2c_start_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_START; +} + +/*! + \brief generate a STOP condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none + */ +void i2c_stop_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; +} + +/*! + \brief I2C transmit data function + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] data: data of transmission + \param[out] none + \retval none + */ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) +{ + I2C_DATA(i2c_periph) = DATA_TRANS(data); +} + +/*! + \brief I2C receive data function + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval data of received + */ +uint8_t i2c_data_receive(uint32_t i2c_periph) +{ + return (uint8_t) DATA_RECV(I2C_DATA(i2c_periph)); +} + +/*! + \brief enable I2C DMA mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dmastate: + only one parameter can be selected which is shown as below: + \arg I2C_DMA_ON: DMA mode enable + \arg I2C_DMA_OFF: DMA mode disable + \param[out] none + \retval none + */ +void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) +{ + /* configure I2C DMA function */ + uint32_t ctl = 0U; + + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMAON); + ctl |= dmastate; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief configure whether next DMA EOT is DMA last transfer or not + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dmalast: + only one parameter can be selected which is shown as below: + \arg I2C_DMALST_ON: next DMA EOT is the last transfer + \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer + \param[out] none + \retval none + */ +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) +{ + /* configure DMA last transfer */ + uint32_t ctl = 0U; + + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMALST); + ctl |= dmalast; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief whether to stretch SCL low when data is not ready in slave mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] stretchpara: + only one parameter can be selected which is shown as below: + \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled + \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled + \param[out] none + \retval none + */ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) +{ + /* configure I2C SCL strerching enable or disable */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SS); + ctl |= stretchpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief whether or not to response to a general call + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] gcallpara: + only one parameter can be selected which is shown as below: + \arg I2C_GCEN_ENABLE: slave will response to a general call + \arg I2C_GCEN_DISABLE: slave will not response to a general call + \param[out] none + \retval none + */ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) +{ + /* configure slave response to a general call enable or disable */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_GCEN); + ctl |= gcallpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief software reset I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] sreset: + only one parameter can be selected which is shown as below: + \arg I2C_SRESET_SET: I2C is under reset + \arg I2C_SRESET_RESET: I2C is not under reset + \param[out] none + \retval none + */ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) +{ + /* modify CTL0 and configure software reset I2C state */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SRESET); + ctl |= sreset; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief I2C PEC calculation on or off + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pecpara: + only one parameter can be selected which is shown as below: + \arg I2C_PEC_ENABLE: PEC calculation on + \arg I2C_PEC_DISABLE: PEC calculation off + \param[out] none + \retval none + */ +void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) +{ + /* on/off PEC calculation */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECEN); + ctl |= pecstate; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief I2C whether to transfer PEC value + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pecpara: + only one parameter can be selected which is shown as below: + \arg I2C_PECTRANS_ENABLE: transfer PEC + \arg I2C_PECTRANS_DISABLE: not transfer PEC + \param[out] none + \retval none + */ +void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) +{ + /* whether to transfer PEC */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECTRANS); + ctl |= pecpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief get packet error checking value + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval PEC value + */ +uint8_t i2c_pec_value_get(uint32_t i2c_periph) +{ + return (uint8_t) ((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV)>> STAT1_PECV_OFFSET); +} + +/*! + \brief I2C issue alert through SMBA pin + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] smbuspara: + only one parameter can be selected which is shown as below: + \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin + \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin + \param[out] none + \retval none + */ +void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) +{ + /* issue alert through SMBA pin configure*/ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SALT); + ctl |= smbuspara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief enable or disable I2C ARP protocol in SMBus switch + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] arpstate: + only one parameter can be selected which is shown as below: + \arg I2C_ARP_ENABLE: enable ARP + \arg I2C_ARP_DISABLE: disable ARP + \param[out] none + \retval none + */ +void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) +{ + /* enable or disable I2C ARP protocol*/ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_ARPEN); + ctl |= arpstate; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief check I2C flag is set or not + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SBSEND: start condition send out + \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode + \arg I2C_FLAG_BTC: byte transmission finishes + \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode + \arg I2C_FLAG_STPDET: stop condition detected in slave mode + \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving + \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting + \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_SMBALT: SMBus alert status + \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode + \arg I2C_FLAG_I2CBSY: busy flag + \arg I2C_FLAG_TR: whether the I2C is a transmitter or a receiver + \arg I2C_FLAG_RXGC: general call address (00h) received + \arg I2C_FLAG_DEFSMB: default address of SMBus device + \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode + \arg I2C_FLAG_DUMODF: dual flag in slave mode indicating which address is matched in dual-address mode + \param[out] none + \retval FlagStatus: SET or RESET + */ +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) +{ + if (RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear I2C flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SMBALT: SMBus Alert status + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_BERR: a bus error + \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 + \param[out] none + \retval none + */ +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) +{ + uint32_t temp; + if (I2C_FLAG_ADDSEND == flag) { + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + temp = I2C_STAT0(i2c_periph); + temp = I2C_STAT1(i2c_periph); + } else { + I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); + } +} + +/*! + \brief enable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt enable + \arg I2C_INT_EV: event interrupt enable + \arg I2C_INT_BUF: buffer interrupt enable + \param[out] none + \retval none + */ +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) +{ + I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); +} + +/*! + \brief disable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] interrupt: I2C interrupts, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt enable + \arg I2C_INT_EV: event interrupt enable + \arg I2C_INT_BUF: buffer interrupt enable + \param[out] none + \retval none + */ +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) +{ + I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); +} + +/*! + \brief check I2C interrupt flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BTC: byte transmission finishes + \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag + \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag + \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag + \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET + */ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U, bufie; + + /* check BUFIE */ + bufie = I2C_CTL1(i2c_periph) & I2C_CTL1_BUFIE; + + /* get the interrupt enable bit status */ + intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag)& BIT(I2C_BIT_POS2(int_flag))); + + if ((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)) { + if (intenable && bufie) { + intenable = 1U; + } else { + intenable = 0U; + } + } + if ((0U != flagstatus) && (0U != intenable)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear I2C interrupt flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \param[out] none + \retval none + */ +void i2c_interrupt_flag_clear(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag) +{ + uint32_t temp; + if (I2C_INT_FLAG_ADDSEND == int_flag) { + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + temp = I2C_STAT0(i2c_periph); + temp = I2C_STAT1(i2c_periph); + } else { + I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c new file mode 100644 index 0000000..ed2bb65 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c @@ -0,0 +1,270 @@ +/*! + \file gd32vf103_pmu.c + \brief PMU driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_pmu.h" +#include "riscv_encoding.h" + +/*! + \brief reset PMU register + \param[in] none + \param[out] none + \retval none +*/ +void pmu_deinit(void) +{ + /* reset PMU */ + rcu_periph_reset_enable(RCU_PMURST); + rcu_periph_reset_disable(RCU_PMURST); +} + +/*! + \brief select low voltage detector threshold + \param[in] lvdt_n: + only one parameter can be selected which is shown as below: + \arg PMU_LVDT_0: voltage threshold is 2.2V + \arg PMU_LVDT_1: voltage threshold is 2.3V + \arg PMU_LVDT_2: voltage threshold is 2.4V + \arg PMU_LVDT_3: voltage threshold is 2.5V + \arg PMU_LVDT_4: voltage threshold is 2.6V + \arg PMU_LVDT_5: voltage threshold is 2.7V + \arg PMU_LVDT_6: voltage threshold is 2.8V + \arg PMU_LVDT_7: voltage threshold is 2.9V + \param[out] none + \retval none +*/ +void pmu_lvd_select(uint32_t lvdt_n) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; + /* clear LVDT bits */ + PMU_CTL &= ~PMU_CTL_LVDT; + /* set LVDT bits according to lvdt_n */ + PMU_CTL |= lvdt_n; + /* enable LVD */ + PMU_CTL |= PMU_CTL_LVDEN; +} + +/*! + \brief disable PMU lvd + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lvd_disable(void) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; +} + +/*! + \brief PMU work at sleep mode + \param[in] sleepmodecmd: + only one parameter can be selected which is shown as below: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_sleepmode(uint8_t sleepmodecmd) +{ + /* clear sleepdeep bit of RISC-V system control register */ + clear_csr(0x811, 0x1); + + /* select WFI or WFE command to enter sleep mode */ + if(WFI_CMD == sleepmodecmd){ + __WFI(); + }else{ + clear_csr(mstatus, MSTATUS_MIE); + set_csr(0x810, 0x1); + __WFI(); + clear_csr(0x810, 0x1); + set_csr(mstatus, MSTATUS_MIE); + } +} + +/*! + \brief PMU work at deepsleep mode + \param[in] ldo: + only one parameter can be selected which is shown as below: + \arg PMU_LDO_NORMAL: LDO work at normal power mode when pmu enter deepsleep mode + \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode + \param[in] deepsleepmodecmd: + only one parameter can be selected which is shown as below: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) +{ + /* clear stbmod and ldolp bits */ + PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); + /* set ldolp bit according to pmu_ldo */ + PMU_CTL |= ldo; + /* set CSR_SLEEPVALUE bit of RISC-V system control register */ + set_csr(0x811, 0x1); + /* select WFI or WFE command to enter deepsleep mode */ + if(WFI_CMD == deepsleepmodecmd){ + __WFI(); + }else{ + clear_csr(mstatus, MSTATUS_MIE); + set_csr(0x810, 0x1); + __WFI(); + clear_csr(0x810, 0x1); + set_csr(mstatus, MSTATUS_MIE); + } + /* reset sleepdeep bit of RISC-V system control register */ + clear_csr(0x811, 0x1); +} + +/*! + \brief pmu work at standby mode + \param[in] standbymodecmd: + only one parameter can be selected which is shown as below: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_standbymode(uint8_t standbymodecmd) +{ + /* set CSR_SLEEPVALUE bit of RISC-V system control register */ + set_csr(0x811, 0x1); + + /* set stbmod bit */ + PMU_CTL |= PMU_CTL_STBMOD; + + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + + /* select WFI or WFE command to enter standby mode */ + if(WFI_CMD == standbymodecmd){ + __WFI(); + }else{ + clear_csr(mstatus, MSTATUS_MIE); + set_csr(0x810, 0x1); + __WFI(); + clear_csr(0x810, 0x1); + set_csr(mstatus, MSTATUS_MIE); + } + clear_csr(0x811, 0x1); +} + +/*! + \brief enable wakeup pin + \param[in] none + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_enable(void) +{ + PMU_CS |= PMU_CS_WUPEN; +} + +/*! + \brief disable wakeup pin + \param[in] none + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_disable(void) +{ + PMU_CS &= ~PMU_CS_WUPEN; +} + +/*! + \brief enable write access to the registers in backup domain + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_enable(void) +{ + PMU_CTL |= PMU_CTL_BKPWEN; +} + +/*! + \brief disable write access to the registers in backup domain + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_disable(void) +{ + PMU_CTL &= ~PMU_CTL_BKPWEN; +} + +/*! + \brief get flag state + \param[in] flag: + only one parameter can be selected which is shown as below: + \arg PMU_FLAG_WAKEUP: wakeup flag + \arg PMU_FLAG_STANDBY: standby flag + \arg PMU_FLAG_LVD: lvd flag + \param[out] none + \retval FlagStatus SET or RESET +*/ +FlagStatus pmu_flag_get(uint32_t flag) +{ + if(PMU_CS & flag){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear flag bit + \param[in] flag_reset: + only one parameter can be selected which is shown as below: + \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag + \arg PMU_FLAG_RESET_STANDBY: reset standby flag + \param[out] none + \retval none +*/ +void pmu_flag_clear(uint32_t flag_reset) +{ + switch(flag_reset){ + case PMU_FLAG_RESET_WAKEUP: + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + break; + case PMU_FLAG_RESET_STANDBY: + /* reset standby flag */ + PMU_CTL |= PMU_CTL_STBRST; + break; + default : + break; + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c new file mode 100644 index 0000000..4cdac29 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c @@ -0,0 +1,1111 @@ +/*! + \file gd32vf103_rcu.c + \brief RCU driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_rcu.h" + +/* define clock source */ +#define SEL_IRC8M ((uint16_t)0U) +#define SEL_HXTAL ((uint16_t)1U) +#define SEL_PLL ((uint16_t)2U) + +/* define startup timeout count */ +#define OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU) +#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU) + +/*! + \brief deinitialize the RCU + \param[in] none + \param[out] none + \retval none +*/ +void rcu_deinit(void) +{ + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + rcu_osci_stab_wait(RCU_IRC8M); + + /* reset CFG0 register */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | + RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4); + /* reset CTL register */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); + RCU_CTL &= ~RCU_CTL_HXTALBPS; + RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN); + /* reset INT and CFG1 register */ + RCU_INT = 0x00ff0000U; + RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF | + RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL); +} + +/*! + \brief enable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x=A,B,C,D,E): GPIO ports clock + \arg RCU_AF : alternate function clock + \arg RCU_CRC: CRC clock + \arg RCU_DMAx (x=0,1): DMA clock + \arg RCU_USBFS: USBFS clock + \arg RCU_EXMC: EXMC clock + \arg RCU_TIMERx (x=0,1,2,3,4,5,6): TIMER clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_SPIx (x=0,1,2): SPI clock + \arg RCU_USARTx (x=0,1,2): USART clock + \arg RCU_UARTx (x=3,4): UART clock + \arg RCU_I2Cx (x=0,1): I2C clock + \arg RCU_CANx (x=0,1): CAN clock + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock + \arg RCU_RTC: RTC clock + \arg RCU_ADCx (x=0,1): ADC clock + \arg RCU_BKPI: BKP interface clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_enable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x=A,B,C,D,E): GPIO ports clock + \arg RCU_AF: alternate function clock + \arg RCU_CRC: CRC clock + \arg RCU_DMAx (x=0,1): DMA clock + \arg RCU_USBFS: USBFS clock + \arg RCU_EXMC: EXMC clock + \arg RCU_TIMERx (x=0,1,2,3,4,5,6): TIMER clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_SPIx (x=0,1,2): SPI clock + \arg RCU_USARTx (x=0,1,2): USART clock + \arg RCU_UARTx (x=3,4): UART clock + \arg RCU_I2Cx (x=0,1): I2C clock + \arg RCU_CANx (x=0,1): CAN clock + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock + \arg RCU_RTC: RTC clock + \arg RCU_ADCx (x=0,1): ADC clock + \arg RCU_BKPI: BKP interface clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_disable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief enable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM_SLP: SRAM clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM_SLP: SRAM clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief reset the peripherals + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x=A,B,C,D,E): reset GPIO ports + \arg RCU_AFRST : reset alternate function clock + \arg RCU_USBFSRST: reset USBFS + \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6): reset TIMER + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_SPIxRST (x=0,1,2): reset SPI + \arg RCU_USARTxRST (x=0,1,2): reset USART + \arg RCU_UARTxRST (x=3,4): reset UART + \arg RCU_I2CxRST (x=0,1): reset I2C + \arg RCU_CANxRST (x=0,1): reset CAN + \arg RCU_PMURST: reset PMU + \arg RCU_DACRST: reset DAC + \arg RCU_ADCxRST (x=0,1): reset ADC + \arg RCU_BKPIRST: reset BKPI + \param[out] none + \retval none +*/ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief disable reset the peripheral + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x=A,B,C,D,E): reset GPIO ports + \arg RCU_AFRST : reset alternate function clock + \arg RCU_USBFSRST: reset USBFS + \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6): reset TIMER + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_SPIxRST (x=0,1,2): reset SPI + \arg RCU_USARTxRST (x=0,1,2): reset USART + \arg RCU_UARTxRST (x=3,4): reset UART + \arg RCU_I2CxRST (x=0,1): reset I2C + \arg RCU_CANxRST (x=0,1): reset CAN + \arg RCU_PMURST: reset PMU + \arg RCU_DACRST: reset DAC + \arg RCU_ADCxRST (x=0,1): reset ADC + \arg RCU_BKPIRST: reset BKPI + \param[out] none + \retval none +*/ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief reset the BKP domain + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_enable(void) +{ + RCU_BDCTL |= RCU_BDCTL_BKPRST; +} + +/*! + \brief disable the BKP domain reset + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_disable(void) +{ + RCU_BDCTL &= ~RCU_BDCTL_BKPRST; +} + +/*! + \brief configure the system clock source + \param[in] ck_sys: system clock source select + only one parameter can be selected which is shown as below: + \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source + \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source + \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source + \param[out] none + \retval none +*/ +void rcu_system_clock_source_config(uint32_t ck_sys) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the SCS bits and set according to ck_sys */ + reg &= ~RCU_CFG0_SCS; + RCU_CFG0 = (reg | ck_sys); +} + +/*! + \brief get the system clock source + \param[in] none + \param[out] none + \retval which clock is selected as CK_SYS source + \arg RCU_SCSS_IRC8M: CK_IRC8M is selected as the CK_SYS source + \arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source + \arg RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source +*/ +uint32_t rcu_system_clock_source_get(void) +{ + return (RCU_CFG0 & RCU_CFG0_SCSS); +} + +/*! + \brief configure the AHB clock prescaler selection + \param[in] ck_ahb: AHB clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 + \param[out] none + \retval none +*/ +void rcu_ahb_clock_config(uint32_t ck_ahb) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the AHBPSC bits and set according to ck_ahb */ + reg &= ~RCU_CFG0_AHBPSC; + RCU_CFG0 = (reg | ck_ahb); +} + +/*! + \brief configure the APB1 clock prescaler selection + \param[in] ck_apb1: APB1 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 + \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 + \param[out] none + \retval none +*/ +void rcu_apb1_clock_config(uint32_t ck_apb1) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the APB1PSC and set according to ck_apb1 */ + reg &= ~RCU_CFG0_APB1PSC; + RCU_CFG0 = (reg | ck_apb1); +} + +/*! + \brief configure the APB2 clock prescaler selection + \param[in] ck_apb2: APB2 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 + \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 + \param[out] none + \retval none +*/ +void rcu_apb2_clock_config(uint32_t ck_apb2) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the APB2PSC and set according to ck_apb2 */ + reg &= ~RCU_CFG0_APB2PSC; + RCU_CFG0 = (reg | ck_apb2); +} + +/*! + \brief configure the CK_OUT0 clock source + \param[in] ckout0_src: CK_OUT0 clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CKOUT0SRC_NONE: no clock selected + \arg RCU_CKOUT0SRC_CKSYS: system clock selected + \arg RCU_CKOUT0SRC_IRC8M: high speed 8M internal oscillator clock selected + \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected + \arg RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected + \arg RCU_CKOUT0SRC_CKPLL1: CK_PLL1 selected + \arg RCU_CKOUT0SRC_CKPLL2_DIV2: CK_PLL2/2 selected + \arg RCU_CKOUT0SRC_EXT1: EXT1 selected + \arg RCU_CKOUT0SRC_CKPLL2: PLL2 selected + \param[out] none + \retval none +*/ +void rcu_ckout0_config(uint32_t ckout0_src) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the CKOUT0SRC, set according to ckout0_src */ + reg &= ~RCU_CFG0_CKOUT0SEL; + RCU_CFG0 = (reg | ckout0_src); +} + +/*! + \brief configure the main PLL clock + \param[in] pll_src: PLL clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_PLLSRC_IRC8M_DIV2: IRC8M/2 clock selected as source clock of PLL + \arg RCU_PLLSRC_HXTAL: HXTAL selected as source clock of PLL + \param[in] pll_mul: PLL clock multiplication factor + only one parameter can be selected which is shown as below: + \arg RCU_PLL_MULx (x = 2..14, 6.5, 16..32) + \param[out] none + \retval none +*/ +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) +{ + uint32_t reg = 0U; + + reg = RCU_CFG0; + + /* PLL clock source and multiplication factor configuration */ + reg &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + reg |= (pll_src | pll_mul); + + RCU_CFG0 = reg; +} + +/*! + \brief configure the PREDV0 division factor and clock source + \param[in] predv0_source: PREDV0 input clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_PREDV0SRC_HXTAL: HXTAL selected as PREDV0 input source clock + \arg RCU_PREDV0SRC_CKPLL1: CK_PLL1 selected as PREDV0 input source clock + \param[in] predv0_div: PREDV0 division factor + only one parameter can be selected which is shown as below: + \arg RCU_PREDV0_DIVx, x = 1..16 + \param[out] none + \retval none +*/ +void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div) +{ + uint32_t reg = 0U; + + reg = RCU_CFG1; + /* reset PREDV0SEL and PREDV0 bits */ + reg &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV0); + /* set the PREDV0SEL and PREDV0 division factor */ + reg |= (predv0_source | predv0_div); + + RCU_CFG1 = reg; +} + +/*! + \brief configure the PREDV1 division factor + \param[in] predv1_div: PREDV1 division factor + only one parameter can be selected which is shown as below: + \arg RCU_PREDV1_DIVx, x = 1..16 + \param[out] none + \retval none +*/ +void rcu_predv1_config(uint32_t predv1_div) +{ + uint32_t reg = 0U; + + reg = RCU_CFG1; + /* reset the PREDV1 bits */ + reg &= ~RCU_CFG1_PREDV1; + /* set the PREDV1 division factor */ + reg |= predv1_div; + + RCU_CFG1 = reg; +} + +/*! + \brief configure the PLL1 clock + \param[in] pll_mul: PLL clock multiplication factor + only one parameter can be selected which is shown as below: + \arg RCU_PLL1_MULx (x = 8..16, 20) + \param[out] none + \retval none +*/ +void rcu_pll1_config(uint32_t pll_mul) +{ + RCU_CFG1 &= ~RCU_CFG1_PLL1MF; + RCU_CFG1 |= pll_mul; +} + +/*! + \brief configure the PLL2 clock + \param[in] pll_mul: PLL clock multiplication factor + only one parameter can be selected which is shown as below: + \arg RCU_PLL2_MULx (x = 8..16, 20) + \param[out] none + \retval none +*/ +void rcu_pll2_config(uint32_t pll_mul) +{ + RCU_CFG1 &= ~RCU_CFG1_PLL2MF; + RCU_CFG1 |= pll_mul; +} + +/*! + \brief configure the ADC prescaler factor + \param[in] adc_psc: ADC prescaler factor + only one parameter can be selected which is shown as below: + \arg RCU_CKADC_CKAPB2_DIV2: ADC prescaler select CK_APB2/2 + \arg RCU_CKADC_CKAPB2_DIV4: ADC prescaler select CK_APB2/4 + \arg RCU_CKADC_CKAPB2_DIV6: ADC prescaler select CK_APB2/6 + \arg RCU_CKADC_CKAPB2_DIV8: ADC prescaler select CK_APB2/8 + \arg RCU_CKADC_CKAPB2_DIV12: ADC prescaler select CK_APB2/12 + \arg RCU_CKADC_CKAPB2_DIV16: ADC prescaler select CK_APB2/16 + \param[out] none + \retval none +*/ +void rcu_adc_clock_config(uint32_t adc_psc) +{ + uint32_t reg0; + + /* reset the ADCPSC bits */ + reg0 = RCU_CFG0; + reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC); + + /* set the ADC prescaler factor */ + switch(adc_psc){ + case RCU_CKADC_CKAPB2_DIV2: + case RCU_CKADC_CKAPB2_DIV4: + case RCU_CKADC_CKAPB2_DIV6: + case RCU_CKADC_CKAPB2_DIV8: + reg0 |= (adc_psc << 14); + break; + + case RCU_CKADC_CKAPB2_DIV12: + case RCU_CKADC_CKAPB2_DIV16: + adc_psc &= ~BIT(2); + reg0 |= (adc_psc << 14 | RCU_CFG0_ADCPSC_2); + break; + + default: + break; + } + + /* set the register */ + RCU_CFG0 = reg0; +} + +/*! + \brief configure the USBFS prescaler factor + \param[in] usb_psc: USB prescaler factor + only one parameter can be selected which is shown as below: + \arg RCU_CKUSB_CKPLL_DIV1_5: USBFS prescaler select CK_PLL/1.5 + \arg RCU_CKUSB_CKPLL_DIV1: USBFS prescaler select CK_PLL/1 + \arg RCU_CKUSB_CKPLL_DIV2_5: USBFS prescaler select CK_PLL/2.5 + \arg RCU_CKUSB_CKPLL_DIV2: USBFS prescaler select CK_PLL/2 + \param[out] none + \retval none +*/ +void rcu_usb_clock_config(uint32_t usb_psc) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* configure the USBFS prescaler factor */ + reg &= ~RCU_CFG0_USBFSPSC; + RCU_CFG0 = (reg | usb_psc); +} + +/*! + \brief configure the RTC clock source selection + \param[in] rtc_clock_source: RTC clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_RTCSRC_NONE: no clock selected + \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock + \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock + \arg RCU_RTCSRC_HXTAL_DIV_128: CK_HXTAL/128 selected as RTC source clock + \param[out] none + \retval none +*/ +void rcu_rtc_clock_config(uint32_t rtc_clock_source) +{ + uint32_t reg; + + reg = RCU_BDCTL; + /* reset the RTCSRC bits and set according to rtc_clock_source */ + reg &= ~RCU_BDCTL_RTCSRC; + RCU_BDCTL = (reg | rtc_clock_source); +} + +/*! + \brief configure the I2S1 clock source selection + \param[in] i2s_clock_source: I2S1 clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_I2S1SRC_CKSYS: System clock selected as I2S1 source clock + \arg RCU_I2S1SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S1 source clock + \param[out] none + \retval none +*/ +void rcu_i2s1_clock_config(uint32_t i2s_clock_source) +{ + uint32_t reg; + + reg = RCU_CFG1; + /* reset the I2S1SEL bit and set according to i2s_clock_source */ + reg &= ~RCU_CFG1_I2S1SEL; + RCU_CFG1 = (reg | i2s_clock_source); +} + +/*! + \brief configure the I2S2 clock source selection + \param[in] i2s_clock_source: I2S2 clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_I2S2SRC_CKSYS: system clock selected as I2S2 source clock + \arg RCU_I2S2SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S2 source clock + \param[out] none + \retval none +*/ +void rcu_i2s2_clock_config(uint32_t i2s_clock_source) +{ + uint32_t reg; + + reg = RCU_CFG1; + /* reset the I2S2SEL bit and set according to i2s_clock_source */ + reg &= ~RCU_CFG1_I2S2SEL; + RCU_CFG1 = (reg | i2s_clock_source); +} + +/*! + \brief get the clock stabilization and periphral reset flags + \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag + \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag + \arg RCU_FLAG_PLLSTB: PLL stabilization flag + \arg RCU_FLAG_PLL1STB: PLL1 stabilization flag + \arg RCU_FLAG_PLL2STB: PLL2 stabilization flag + \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag + \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag + \arg RCU_FLAG_EPRST: external PIN reset flag + \arg RCU_FLAG_PORRST: power reset flag + \arg RCU_FLAG_SWRST: software reset flag + \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag + \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag + \arg RCU_FLAG_LPRST: low-power reset flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_flag_get(rcu_flag_enum flag) +{ + /* get the rcu flag */ + if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear all the reset flag + \param[in] none + \param[out] none + \retval none +*/ +void rcu_all_reset_flag_clear(void) +{ + RCU_RSTSCK |= RCU_RSTSCK_RSTFC; +} + +/*! + \brief get the clock stabilization interrupt and ckm flags + \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag + \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag + \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag + \arg RCU_INT_FLAG_PLL1STB: PLL1 stabilization interrupt flag + \arg RCU_INT_FLAG_PLL2STB: PLL2 stabilization interrupt flag + \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) +{ + /* get the rcu interrupt flag */ + if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear the interrupt flags + \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear + \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear + \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear + \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear + \param[out] none + \retval none +*/ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) +{ + RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); +} + +/*! + \brief enable the stabilization interrupt + \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + Only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable + \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable + \param[out] none + \retval none +*/ +void rcu_interrupt_enable(rcu_int_enum stab_int) +{ + RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); +} + +/*! + \brief disable the stabilization interrupt + \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable + \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable + \param[out] none + \retval none +*/ +void rcu_interrupt_disable(rcu_int_enum stab_int) +{ + RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); +} + +/*! + \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) + \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) + \arg RCU_PLL_CK: phase locked loop(PLL) + \arg RCU_PLL1_CK: phase locked loop 1 + \arg RCU_PLL2_CK: phase locked loop 2 + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) +{ + uint32_t stb_cnt = 0U; + ErrStatus reval = ERROR; + FlagStatus osci_stat = RESET; + + switch(osci){ + /* wait HXTAL stable */ + case RCU_HXTAL: + while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ + reval = SUCCESS; + } + break; + + /* wait LXTAL stable */ + case RCU_LXTAL: + while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ + reval = SUCCESS; + } + break; + + /* wait IRC8M stable */ + case RCU_IRC8M: + while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){ + reval = SUCCESS; + } + break; + + /* wait IRC40K stable */ + case RCU_IRC40K: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){ + reval = SUCCESS; + } + break; + + /* wait PLL stable */ + case RCU_PLL_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){ + reval = SUCCESS; + } + break; + /* wait PLL1 stable */ + case RCU_PLL1_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB)){ + reval = SUCCESS; + } + break; + /* wait PLL2 stable */ + case RCU_PLL2_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB)){ + reval = SUCCESS; + } + break; + + default: + break; + } + + /* return value */ + return reval; +} + +/*! + \brief turn on the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) + \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) + \arg RCU_PLL_CK: phase locked loop(PLL) + \arg RCU_PLL1_CK: phase locked loop 1 + \arg RCU_PLL2_CK: phase locked loop 2 + \param[out] none + \retval none +*/ +void rcu_osci_on(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief turn off the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) + \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) + \arg RCU_PLL_CK: phase locked loop(PLL) + \arg RCU_PLL1_CK: phase locked loop 1 + \arg RCU_PLL2_CK: phase locked loop 2 + \param[out] none + \retval none +*/ +void rcu_osci_off(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) +{ + uint32_t reg; + + switch(osci){ + /* enable HXTAL to bypass mode */ + case RCU_HXTAL: + reg = RCU_CTL; + RCU_CTL &= ~RCU_CTL_HXTALEN; + RCU_CTL = (reg | RCU_CTL_HXTALBPS); + break; + /* enable LXTAL to bypass mode */ + case RCU_LXTAL: + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); + break; + case RCU_IRC8M: + case RCU_IRC40K: + case RCU_PLL_CK: + case RCU_PLL1_CK: + case RCU_PLL2_CK: + break; + default: + break; + } +} + +/*! + \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) +{ + uint32_t reg; + + switch(osci){ + /* disable HXTAL to bypass mode */ + case RCU_HXTAL: + reg = RCU_CTL; + RCU_CTL &= ~RCU_CTL_HXTALEN; + RCU_CTL = (reg & ~RCU_CTL_HXTALBPS); + break; + /* disable LXTAL to bypass mode */ + case RCU_LXTAL: + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS); + break; + case RCU_IRC8M: + case RCU_IRC40K: + case RCU_PLL_CK: + case RCU_PLL1_CK: + case RCU_PLL2_CK: + break; + default: + break; + } +} + +/*! + \brief enable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ + +void rcu_hxtal_clock_monitor_enable(void) +{ + RCU_CTL |= RCU_CTL_CKMEN; +} + +/*! + \brief disable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_hxtal_clock_monitor_disable(void) +{ + RCU_CTL &= ~RCU_CTL_CKMEN; +} + +/*! + \brief set the IRC8M adjust value + \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F + \param[out] none + \retval none +*/ +void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval) +{ + uint32_t reg; + + reg = RCU_CTL; + /* reset the IRC8MADJ bits and set according to irc8m_adjval */ + reg &= ~RCU_CTL_IRC8MADJ; + RCU_CTL = (reg | ((irc8m_adjval & 0x1FU) << 3)); +} + +/*! + \brief deep-sleep mode voltage select + \param[in] dsvol: deep sleep mode voltage + only one parameter can be selected which is shown as below: + \arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V + \arg RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V + \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V + \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V + \param[out] none + \retval none +*/ +void rcu_deepsleep_voltage_set(uint32_t dsvol) +{ + dsvol &= RCU_DSV_DSLPVS; + RCU_DSV = dsvol; +} + +/*! + \brief get the system clock, bus and peripheral clock frequency + \param[in] clock: the clock frequency which to get + only one parameter can be selected which is shown as below: + \arg CK_SYS: system clock frequency + \arg CK_AHB: AHB clock frequency + \arg CK_APB1: APB1 clock frequency + \arg CK_APB2: APB2 clock frequency + \param[out] none + \retval clock frequency of system, AHB, APB1, APB2 +*/ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) +{ + uint32_t sws, ck_freq = 0U; + uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; + uint32_t pllsel, predv0sel, pllmf,ck_src, idx, clk_exp; + uint32_t predv0, predv1, pll1mf; + + /* exponent of AHB, APB1 and APB2 clock divider */ + uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + + sws = GET_BITS(RCU_CFG0, 2, 3); + switch(sws){ + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + cksys_freq = IRC8M_VALUE; + break; + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + cksys_freq = HXTAL_VALUE; + break; + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + + if(RCU_PLLSRC_HXTAL == pllsel) { + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + + predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); + /* source clock use PLL1 */ + if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ + predv1 = (uint32_t)((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; + pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; + if(17U == pll1mf){ + pll1mf = 20U; + } + ck_src = (ck_src / predv1) * pll1mf; + } + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; + ck_src /= predv0; + }else{ + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE/2U; + } + + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ + pllmf |= 0x10U; + } + if(pllmf < 15U){ + pllmf += 2U; + }else{ + pllmf += 1U; + } + + cksys_freq = ck_src * pllmf; + + if(15U == pllmf){ + /* PLL source clock multiply by 6.5 */ + cksys_freq = ck_src * 6U + ck_src / 2U; + } + + break; + /* IRC8M is selected as CK_SYS */ + default: + cksys_freq = IRC8M_VALUE; + break; + } + + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + ahb_freq = cksys_freq >> clk_exp; + + /* calculate APB1 clock frequency */ + idx = GET_BITS(RCU_CFG0, 8, 10); + clk_exp = apb1_exp[idx]; + apb1_freq = ahb_freq >> clk_exp; + + /* calculate APB2 clock frequency */ + idx = GET_BITS(RCU_CFG0, 11, 13); + clk_exp = apb2_exp[idx]; + apb2_freq = ahb_freq >> clk_exp; + + /* return the clocks frequency */ + switch(clock){ + case CK_SYS: + ck_freq = cksys_freq; + break; + case CK_AHB: + ck_freq = ahb_freq; + break; + case CK_APB1: + ck_freq = apb1_freq; + break; + case CK_APB2: + ck_freq = apb2_freq; + break; + default: + break; + } + return ck_freq; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c new file mode 100644 index 0000000..6404809 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c @@ -0,0 +1,273 @@ +/*! + \file gd32vf103_rtc.c + \brief RTC driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_rtc.h" + +/* RTC register high / low bits mask */ +#define RTC_HIGH_BITS_MASK ((uint32_t)0x000F0000U) /* RTC high bits mask */ +#define RTC_LOW_BITS_MASK ((uint32_t)0x0000FFFFU) /* RTC low bits mask */ + +/* RTC register high bits offset */ +#define RTC_HIGH_BITS_OFFSET ((uint32_t)16U) + +/*! + \brief enter RTC configuration mode + \param[in] none + \param[out] none + \retval none +*/ +void rtc_configuration_mode_enter(void) +{ + RTC_CTL |= RTC_CTL_CMF; +} + +/*! + \brief exit RTC configuration mode + \param[in] none + \param[out] none + \retval none +*/ +void rtc_configuration_mode_exit(void) +{ + RTC_CTL &= ~RTC_CTL_CMF; +} + +/*! + \brief set RTC counter value + \param[in] cnt: RTC counter value + \param[out] none + \retval none +*/ +void rtc_counter_set(uint32_t cnt) +{ + rtc_configuration_mode_enter(); + /* set the RTC counter high bits */ + RTC_CNTH = (cnt >> RTC_HIGH_BITS_OFFSET); + /* set the RTC counter low bits */ + RTC_CNTL = (cnt & RTC_LOW_BITS_MASK); + rtc_configuration_mode_exit(); +} + +/*! + \brief set RTC prescaler value + \param[in] psc: RTC prescaler value + \param[out] none + \retval none +*/ +void rtc_prescaler_set(uint32_t psc) +{ + rtc_configuration_mode_enter(); + /* set the RTC prescaler high bits */ + RTC_PSCH = ((psc & RTC_HIGH_BITS_MASK) >> RTC_HIGH_BITS_OFFSET); + /* set the RTC prescaler low bits */ + RTC_PSCL = (psc & RTC_LOW_BITS_MASK); + rtc_configuration_mode_exit(); +} + +/*! + \brief wait RTC last write operation finished flag set + \param[in] none + \param[out] none + \retval none +*/ +void rtc_lwoff_wait(void) +{ + /* loop until LWOFF flag is set */ + while(RESET == (RTC_CTL & RTC_CTL_LWOFF)){ + } +} + +/*! + \brief wait RTC registers synchronized flag set + \param[in] none + \param[out] none + \retval none +*/ +void rtc_register_sync_wait(void) +{ + /* clear RSYNF flag */ + RTC_CTL &= ~RTC_CTL_RSYNF; + /* loop until RSYNF flag is set */ + while(RESET == (RTC_CTL & RTC_CTL_RSYNF)){ + } +} + +/*! + \brief set RTC alarm value + \param[in] alarm: RTC alarm value + \param[out] none + \retval none +*/ +void rtc_alarm_config(uint32_t alarm) +{ + rtc_configuration_mode_enter(); + /* set the alarm high bits */ + RTC_ALRMH = (alarm >> RTC_HIGH_BITS_OFFSET); + /* set the alarm low bits */ + RTC_ALRML = (alarm & RTC_LOW_BITS_MASK); + rtc_configuration_mode_exit(); +} + +/*! + \brief get RTC counter value + \param[in] none + \param[out] none + \retval RTC counter value +*/ +uint32_t rtc_counter_get(void) +{ + uint32_t temp = 0x0U; + + temp = RTC_CNTL; + temp |= (RTC_CNTH << RTC_HIGH_BITS_OFFSET); + return temp; +} + +/*! + \brief get RTC divider value + \param[in] none + \param[out] none + \retval RTC divider value +*/ +uint32_t rtc_divider_get(void) +{ + uint32_t temp = 0x00U; + + temp = ((RTC_DIVH & RTC_DIVH_DIV) << RTC_HIGH_BITS_OFFSET); + temp |= RTC_DIVL; + return temp; +} + +/*! + \brief get RTC flag status + \param[in] flag: specify which flag status to get + only one parameter can be selected which is shown as below: + \arg RTC_FLAG_SECOND: second interrupt flag + \arg RTC_FLAG_ALARM: alarm interrupt flag + \arg RTC_FLAG_OVERFLOW: overflow interrupt flag + \arg RTC_FLAG_RSYN: registers synchronized flag + \arg RTC_FLAG_LWOF: last write operation finished flag + \param[out] none + \retval SET or RESET +*/ +FlagStatus rtc_flag_get(uint32_t flag) +{ + if(RESET != (RTC_CTL & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear RTC flag status + \param[in] flag: specify which flag status to clear + one or more parameters can be selected which are shown as below: + \arg RTC_FLAG_SECOND: second interrupt flag + \arg RTC_FLAG_ALARM: alarm interrupt flag + \arg RTC_FLAG_OVERFLOW: overflow interrupt flag + \arg RTC_FLAG_RSYN: registers synchronized flag + \param[out] none + \retval none +*/ +void rtc_flag_clear(uint32_t flag) +{ + /* clear RTC flag */ + RTC_CTL &= ~flag; +} + +/*! + \brief get RTC interrupt flag status + \param[in] flag: specify which flag status to get + only one parameter can be selected which is shown as below: + \arg RTC_INT_FLAG_SECOND: second interrupt flag + \arg RTC_INT_FLAG_ALARM: alarm interrupt flag + \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag + \param[out] none + \retval SET or RESET +*/ +FlagStatus rtc_interrupt_flag_get(uint32_t flag) +{ + if(RESET != (RTC_CTL & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear RTC interrupt flag status + \param[in] flag: specify which flag status to clear + one or more parameters can be selected which are shown as below: + \arg RTC_INT_FLAG_SECOND: second interrupt flag + \arg RTC_INT_FLAG_ALARM: alarm interrupt flag + \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag + \param[out] none + \retval none +*/ +void rtc_interrupt_flag_clear(uint32_t flag) +{ + /* clear RTC interrupt flag */ + RTC_CTL &= ~flag; +} + +/*! + \brief enable RTC interrupt + \param[in] interrupt: specify which interrupt to enbale + one or more parameters can be selected which are shown as below: + \arg RTC_INT_SECOND: second interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_OVERFLOW: overflow interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_enable(uint32_t interrupt) +{ + RTC_INTEN |= interrupt; +} + +/*! + \brief disable RTC interrupt + \param[in] interrupt: specify which interrupt to disbale + one or more parameters can be selected which are shown as below: + \arg RTC_INT_SECOND: second interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_OVERFLOW: overflow interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_disable(uint32_t interrupt) +{ + RTC_INTEN &= ~interrupt; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c new file mode 100644 index 0000000..1c8b434 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c @@ -0,0 +1,766 @@ +/*! + \file gd32vf103_spi.c + \brief SPI driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_spi.h" + +/* SPI/I2S parameter initialization mask */ +#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */ +#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ + +/* I2S clock source selection, multiplication and division mask */ +#define I2S1_CLOCK_SEL ((uint32_t)0x00020000U) /* I2S1 clock source selection */ +#define I2S2_CLOCK_SEL ((uint32_t)0x00040000U) /* I2S2 clock source selection */ +#define I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U) /* I2S clock multiplication mask */ +#define I2S_CLOCK_DIV_MASK ((uint32_t)0x000000F0U) /* I2S clock division mask */ + +/* default value and offset */ +#define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /* default value of SPI_I2SPSC register */ +#define RCU_CFG1_PREDV1_OFFSET 4U /* PREDV1 offset in RCU_CFG1 */ +#define RCU_CFG1_PLL2MF_OFFSET 12U /* PLL2MF offset in RCU_CFG1 */ + +/*! + \brief reset SPI and I2S + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_i2s_deinit(uint32_t spi_periph) +{ + switch(spi_periph){ + case SPI0: + /* reset SPI0 */ + rcu_periph_reset_enable(RCU_SPI0RST); + rcu_periph_reset_disable(RCU_SPI0RST); + break; + case SPI1: + /* reset SPI1 and I2S1 */ + rcu_periph_reset_enable(RCU_SPI1RST); + rcu_periph_reset_disable(RCU_SPI1RST); + break; + case SPI2: + /* reset SPI2 and I2S2 */ + rcu_periph_reset_enable(RCU_SPI2RST); + rcu_periph_reset_disable(RCU_SPI2RST); + break; + default : + break; + } +} + +/*! + \brief initialize the parameters of SPI struct with the default values + \param[in] spi_struct: SPI parameter stuct + \param[out] none + \retval none +*/ +void spi_struct_para_init(spi_parameter_struct* spi_struct) +{ + /* set the SPI struct with the default values */ + spi_struct->device_mode = SPI_SLAVE; + spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_struct->frame_size = SPI_FRAMESIZE_8BIT; + spi_struct->nss = SPI_NSS_HARD; + spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; + spi_struct->prescale = SPI_PSC_2; +} + +/*! + \brief initialize SPI parameter + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] spi_struct: SPI parameter initialization stuct members of the structure + and the member values are shown as below: + device_mode: SPI_MASTER, SPI_SLAVE + trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, + SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT + frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT + nss: SPI_NSS_SOFT, SPI_NSS_HARD + endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB + clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE + SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE + prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) + \param[out] none + \retval none +*/ +void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) +{ + uint32_t reg = 0U; + reg = SPI_CTL0(spi_periph); + reg &= SPI_INIT_MASK; + + /* select SPI as master or slave */ + reg |= spi_struct->device_mode; + /* select SPI transfer mode */ + reg |= spi_struct->trans_mode; + /* select SPI frame size */ + reg |= spi_struct->frame_size; + /* select SPI NSS use hardware or software */ + reg |= spi_struct->nss; + /* select SPI LSB or MSB */ + reg |= spi_struct->endian; + /* select SPI polarity and phase */ + reg |= spi_struct->clock_polarity_phase; + /* select SPI prescale to adjust transmit speed */ + reg |= spi_struct->prescale; + + /* write to SPI_CTL0 register */ + SPI_CTL0(spi_periph) = (uint32_t)reg; + + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); +} + +/*! + \brief enable SPI + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_enable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; +} + +/*! + \brief disable SPI + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_disable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); +} + +/*! + \brief initialize I2S parameter + \param[in] spi_periph: SPIx(x=1,2) + \param[in] mode: I2S operation mode + only one parameter can be selected which is shown as below: + \arg I2S_MODE_SLAVETX: I2S slave transmit mode + \arg I2S_MODE_SLAVERX: I2S slave receive mode + \arg I2S_MODE_MASTERTX: I2S master transmit mode + \arg I2S_MODE_MASTERRX: I2S master receive mode + \param[in] standard: I2S standard + only one parameter can be selected which is shown as below: + \arg I2S_STD_PHILLIPS: I2S phillips standard + \arg I2S_STD_MSB: I2S MSB standard + \arg I2S_STD_LSB: I2S LSB standard + \arg I2S_STD_PCMSHORT: I2S PCM short standard + \arg I2S_STD_PCMLONG: I2S PCM long standard + \param[in] ckpl: I2S idle state clock polarity + only one parameter can be selected which is shown as below: + \arg I2S_CKPL_LOW: I2S clock polarity low level + \arg I2S_CKPL_HIGH: I2S clock polarity high level + \param[out] none + \retval none +*/ +void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl) +{ + uint32_t reg = 0U; + reg = SPI_I2SCTL(spi_periph); + reg &= I2S_INIT_MASK; + + /* enable I2S mode */ + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + /* select I2S mode */ + reg |= (uint32_t)mode; + /* select I2S standard */ + reg |= (uint32_t)standard; + /* select I2S polarity */ + reg |= (uint32_t)ckpl; + + /* write to SPI_I2SCTL register */ + SPI_I2SCTL(spi_periph) = (uint32_t)reg; +} + +/*! + \brief configure I2S prescaler + \param[in] spi_periph: SPIx(x=1,2) + \param[in] audiosample: I2S audio sample rate + only one parameter can be selected which is shown as below: + \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz + \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz + \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz + \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz + \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz + \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz + \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz + \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz + \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz + \param[in] frameformat: I2S data length and channel length + only one parameter can be selected which is shown as below: + \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit + \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit + \param[in] mckout: I2S master clock output + only one parameter can be selected which is shown as below: + \arg I2S_MCKOUT_ENABLE: I2S master clock output enable + \arg I2S_MCKOUT_DISABLE: I2S master clock output disable + \param[out] none + \retval none +*/ +void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) +{ + uint32_t i2sdiv = 2U, i2sof = 0U; + uint32_t clks = 0U; + uint32_t i2sclock = 0U; + + /* deinit SPI_I2SPSC register */ + SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE; + + /* get the I2S clock source */ + if(SPI1 == ((uint32_t)spi_periph)){ + /* I2S1 clock source selection */ + clks = I2S1_CLOCK_SEL; + }else{ + /* I2S2 clock source selection */ + clks = I2S2_CLOCK_SEL; + } + + if(0U != (RCU_CFG1 & clks)){ + /* get RCU PLL2 clock multiplication factor */ + clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> RCU_CFG1_PLL2MF_OFFSET); + + if((clks > 5U) && (clks < 15U)){ + /* multiplier is between 8 and 16 */ + clks += 2U; + }else{ + if(15U == clks){ + /* multiplier is 20 */ + clks = 20U; + } + } + + /* get the PREDV1 value */ + i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> RCU_CFG1_PREDV1_OFFSET) + 1U); + /* calculate I2S clock based on PLL2 and PREDV1 */ + i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U); + }else{ + /* get system clock */ + i2sclock = rcu_clock_freq_get(CK_SYS); + } + + /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ + if(I2S_MCKOUT_ENABLE == mckout){ + clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample); + }else{ + if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){ + clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample); + }else{ + clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample); + } + } + + /* remove the floating point */ + clks = (clks + 5U) / 10U; + i2sof = (clks & 0x00000001U); + i2sdiv = ((clks - i2sof) / 2U); + i2sof = (i2sof << 8U); + + /* set the default values */ + if((i2sdiv < 2U) || (i2sdiv > 255U)){ + i2sdiv = 2U; + i2sof = 0U; + } + /* configure SPI_I2SPSC */ + SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout); + + /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); + /* configure data frame format */ + SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat; +} + +/*! + \brief enable I2S + \param[in] spi_periph: SPIx(x=1,2) + \param[out] none + \retval none +*/ +void i2s_enable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; +} + +/*! + \brief disable I2S + \param[in] spi_periph: SPIx(x=1,2) + \param[out] none + \retval none +*/ +void i2s_disable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); +} + +/*! + \brief enable SPI NSS output + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_output_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; +} + +/*! + \brief disable SPI NSS output + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_output_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); +} + +/*! + \brief SPI NSS pin high level in software mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_internal_high(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; +} + +/*! + \brief SPI NSS pin low level in software mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_internal_low(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); +} + +/*! + \brief enable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA + \arg SPI_DMA_RECEIVE: SPI receive data using DMA + \param[out] none + \retval none +*/ +void spi_dma_enable(uint32_t spi_periph, uint8_t dma) +{ + if(SPI_DMA_TRANSMIT == dma){ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; + }else{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; + } +} + +/*! + \brief disable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA + \arg SPI_DMA_RECEIVE: SPI receive data using DMA + \param[out] none + \retval none +*/ +void spi_dma_disable(uint32_t spi_periph, uint8_t dma) +{ + if(SPI_DMA_TRANSMIT == dma){ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); + }else{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); + } +} + +/*! + \brief configure SPI/I2S data frame format + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] frame_format: SPI frame size + only one parameter can be selected which is shown as below: + \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits + \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits + \param[out] none + \retval none +*/ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) +{ + /* clear SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); + /* configure SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) |= (uint32_t)frame_format; +} + +/*! + \brief SPI transmit data + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] data: 16-bit data + \param[out] none + \retval none +*/ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) +{ + SPI_DATA(spi_periph) = (uint32_t)data; +} + +/*! + \brief SPI receive data + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval 16-bit data +*/ +uint16_t spi_i2s_data_receive(uint32_t spi_periph) +{ + return ((uint16_t)SPI_DATA(spi_periph)); +} + +/*! + \brief configure SPI bidirectional transfer direction + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] transfer_direction: SPI transfer direction + only one parameter can be selected which is shown as below: + \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode + \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode + \param[out] none + \retval none +*/ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) +{ + if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ + /* set the transmit-only mode */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; + }else{ + /* set the receive-only mode */ + SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; + } +} + +/*! + \brief set SPI CRC polynomial + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] crc_poly: CRC polynomial value + \param[out] none + \retval none +*/ +void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly) +{ + /* enable SPI CRC */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; + + /* set SPI CRC polynomial */ + SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; +} + +/*! + \brief get SPI CRC polynomial + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval 16-bit CRC polynomial +*/ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph) +{ + return ((uint16_t)SPI_CRCPOLY(spi_periph)); +} + +/*! + \brief turn on CRC function + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_on(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; +} + +/*! + \brief turn off CRC function + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_off(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); +} + +/*! + \brief SPI next data is CRC value + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_next(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; +} + +/*! + \brief get SPI CRC send value or receive value + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] crc: SPI crc value + only one parameter can be selected which is shown as below: + \arg SPI_CRC_TX: get transmit crc value + \arg SPI_CRC_RX: get receive crc value + \param[out] none + \retval 16-bit CRC value +*/ +uint16_t spi_crc_get(uint32_t spi_periph,uint8_t crc) +{ + if(SPI_CRC_TX == crc){ + return ((uint16_t)(SPI_TCRC(spi_periph))); + }else{ + return ((uint16_t)(SPI_RCRC(spi_periph))); + } +} + +/*! + \brief enable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_ti_mode_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; +} + +/*! + \brief disable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_ti_mode_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); +} + +/*! + \brief enable SPI NSS pulse mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nssp_mode_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; +} + +/*! + \brief disable SPI NSS pulse mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nssp_mode_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); +} + + +/*! + \brief enable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] interrupt: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) +{ + switch(interrupt){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; + break; + default: + break; + } +} + +/*! + \brief disable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] interrupt: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) +{ + switch(interrupt){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); + break; + default: + break; + } +} + +/*! + \brief get SPI and I2S interrupt flag status + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] interrupt: SPI/I2S interrupt flag status + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag + \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag + \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag + \arg SPI_INT_FLAG_CONFERR: config error interrupt flag + \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag + \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag + \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) +{ + uint32_t reg1 = SPI_STAT(spi_periph); + uint32_t reg2 = SPI_CTL1(spi_periph); + + switch(interrupt){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_FLAG_TBE: + reg1 = reg1 & SPI_STAT_TBE; + reg2 = reg2 & SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_FLAG_RBNE: + reg1 = reg1 & SPI_STAT_RBNE; + reg2 = reg2 & SPI_CTL1_RBNEIE; + break; + /* SPI/I2S overrun interrupt */ + case SPI_I2S_INT_FLAG_RXORERR: + reg1 = reg1 & SPI_STAT_RXORERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI config error interrupt */ + case SPI_INT_FLAG_CONFERR: + reg1 = reg1 & SPI_STAT_CONFERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI CRC error interrupt */ + case SPI_INT_FLAG_CRCERR: + reg1 = reg1 & SPI_STAT_CRCERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* I2S underrun error interrupt */ + case I2S_INT_FLAG_TXURERR: + reg1 = reg1 & SPI_STAT_TXURERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI/I2S format error interrupt */ + case SPI_I2S_INT_FLAG_FERR: + reg1 = reg1 & SPI_STAT_FERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + default: + break; + } + /* get SPI/I2S interrupt flag status */ + if((0U != reg1) && (0U != reg2)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get SPI and I2S flag status + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] flag: SPI/I2S flag status + one or more parameters can be selected which are shown as below: + \arg SPI_FLAG_TBE: transmit buffer empty flag + \arg SPI_FLAG_RBNE: receive buffer not empty flag + \arg SPI_FLAG_TRANS: transmit on-going flag + \arg SPI_FLAG_RXORERR: receive overrun error flag + \arg SPI_FLAG_CONFERR: mode config error flag + \arg SPI_FLAG_CRCERR: CRC error flag + \arg SPI_FLAG_FERR: format error interrupt flag + \arg I2S_FLAG_TBE: transmit buffer empty flag + \arg I2S_FLAG_RBNE: receive buffer not empty flag + \arg I2S_FLAG_TRANS: transmit on-going flag + \arg I2S_FLAG_RXORERR: overrun error flag + \arg I2S_FLAG_TXURERR: underrun error flag + \arg I2S_FLAG_CH: channel side flag + \arg I2S_FLAG_FERR: format error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) +{ + if(RESET != (SPI_STAT(spi_periph) & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear SPI CRC error flag status + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_error_clear(uint32_t spi_periph) +{ + SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c new file mode 100644 index 0000000..fe0d991 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c @@ -0,0 +1,1966 @@ +/*! + \file gd32vf103_timer.c + \brief TIMER driver + + \version 2019-06-05, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ +#include "gd32vf103_timer.h" + +/* TIMER init parameter mask */ +#define ALIGNEDMODE_MASK ((uint32_t)0x00000060U) /*!< TIMER init parameter aligne dmode mask */ +#define COUNTERDIRECTION_MASK ((uint32_t)0x00000010U) /*!< TIMER init parameter counter direction mask */ +#define CLOCKDIVISION_MASK ((uint32_t)0x00000300U) /*!< TIMER init parameter clock division value mask */ + +/*! + \brief deinit a timer + \param[in] timer_periph: TIMERx(x=0..6) + \param[out] none + \retval none +*/ +void timer_deinit(uint32_t timer_periph) +{ + switch(timer_periph){ + case TIMER0: + /* reset TIMER0 */ + rcu_periph_reset_enable(RCU_TIMER0RST); + rcu_periph_reset_disable(RCU_TIMER0RST); + break; + case TIMER1: + /* reset TIMER1 */ + rcu_periph_reset_enable(RCU_TIMER1RST); + rcu_periph_reset_disable(RCU_TIMER1RST); + break; + case TIMER2: + /* reset TIMER2 */ + rcu_periph_reset_enable(RCU_TIMER2RST); + rcu_periph_reset_disable(RCU_TIMER2RST); + break; + case TIMER3: + /* reset TIMER3 */ + rcu_periph_reset_enable(RCU_TIMER3RST); + rcu_periph_reset_disable(RCU_TIMER3RST); + break; + case TIMER4: + /* reset TIMER4 */ + rcu_periph_reset_enable(RCU_TIMER4RST); + rcu_periph_reset_disable(RCU_TIMER4RST); + break; + case TIMER5: + /* reset TIMER5 */ + rcu_periph_reset_enable(RCU_TIMER5RST); + rcu_periph_reset_disable(RCU_TIMER5RST); + break; + case TIMER6: + /* reset TIMER6 */ + rcu_periph_reset_enable(RCU_TIMER6RST); + rcu_periph_reset_disable(RCU_TIMER6RST); + break; + + default: + break; + } +} + +/*! + \brief initialize TIMER init parameter struct with a default value + \param[in] initpara: init parameter struct + \param[out] none + \retval none +*/ +void timer_struct_para_init(timer_parameter_struct* initpara) +{ + /* initialize the init parameter struct member with the default value */ + initpara->prescaler = 0U; + initpara->alignedmode = TIMER_COUNTER_EDGE; + initpara->counterdirection = TIMER_COUNTER_UP; + initpara->period = 65535U; + initpara->clockdivision = TIMER_CKDIV_DIV1; + initpara->repetitioncounter = 0U; +} + +/*! + \brief initialize TIMER counter + \param[in] timer_periph: TIMERx(x=0..6) + \param[in] initpara: init parameter struct + prescaler: prescaler value of the counter clock, 0~65535 + alignedmode: TIMER_COUNTER_EDGE, TIMER_COUNTER_CENTER_DOWN, TIMER_COUNTER_CENTER_UP, + TIMER_COUNTER_CENTER_BOTH + counterdirection: TIMER_COUNTER_UP, TIMER_COUNTER_DOWN + period: counter auto reload value, 0~65535 + clockdivision: TIMER_CKDIV_DIV1, TIMER_CKDIV_DIV2, TIMER_CKDIV_DIV4 + repetitioncounter: counter repetition value, 0~255 + \param[out] none + \retval none +*/ +void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) +{ + /* configure the counter prescaler value */ + TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; + + /* configure the counter direction and aligned mode */ + if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) + || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) ){ + TIMER_CTL0(timer_periph) &= (~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM)); + TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->alignedmode & ALIGNEDMODE_MASK); + TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK); + }else{ + TIMER_CTL0(timer_periph) &= (uint32_t)(~ TIMER_CTL0_DIR); + TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK); + } + + /* configure the autoreload value */ + TIMER_CAR(timer_periph) = (uint32_t)initpara->period; + + if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){ + /* reset the CKDIV bit */ + TIMER_CTL0(timer_periph) &= (~(uint32_t)TIMER_CTL0_CKDIV); + TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->clockdivision & CLOCKDIVISION_MASK); + } + + if (TIMER0 == timer_periph) { + /* configure the repetition counter value */ + TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; + } + + /* generate an update event */ + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; +} + +/*! + \brief enable a timer + \param[in] timer_periph: TIMERx(x=0..6) + \param[out] none + \retval none +*/ +void timer_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief disable a timer + \param[in] timer_periph: TIMERx(x=0..6) + \param[out] none + \retval none +*/ +void timer_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief enable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0..6) + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief disable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0..6) + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief enable the update event + \param[in] timer_periph: TIMERx(x=0..6) + \param[out] none + \retval none +*/ +void timer_update_event_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; +} + +/*! + \brief disable the update event + \param[in] timer_periph: TIMERx(x=0..6) + \param[out] none + \retval none +*/ +void timer_update_event_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; +} + +/*! + \brief set TIMER counter alignment mode + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] aligned: + only one parameter can be selected which is shown as below: + \arg TIMER_COUNTER_EDGE: edge-aligned mode + \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode + \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode + \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode + \param[out] none + \retval none +*/ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) +{ + TIMER_CTL0(timer_periph) &= (uint32_t)(~TIMER_CTL0_CAM); + TIMER_CTL0(timer_periph) |= (uint32_t)aligned; +} + +/*! + \brief set TIMER counter up direction + \param[in] timer_periph: TIMERx(x=0..4) + \param[out] none + \retval none +*/ +void timer_counter_up_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief set TIMER counter down direction + \param[in] timer_periph: TIMERx(x=0..4) + \param[out] none + \retval none +*/ +void timer_counter_down_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief configure TIMER prescaler + \param[in] timer_periph: TIMERx(x=0..6) + \param[in] prescaler: prescaler value + \param[in] pscreload: prescaler reload mode + only one parameter can be selected which is shown as below: + \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now + \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event + \param[out] none + \retval none +*/ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload) +{ + TIMER_PSC(timer_periph) = (uint32_t)prescaler; + + if(TIMER_PSC_RELOAD_NOW == pscreload){ + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; + } +} + +/*! + \brief configure TIMER repetition register value + \param[in] timer_periph: TIMERx(x=0) + \param[in] repetition: the counter repetition value, 0~255 + \param[out] none + \retval none +*/ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) +{ + TIMER_CREP(timer_periph) = (uint32_t)repetition; +} + +/*! + \brief configure TIMER autoreload register value + \param[in] timer_periph: TIMERx(x=0..6) + \param[in] autoreload: the counter auto-reload value + \param[out] none + \retval none +*/ +void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload) +{ + TIMER_CAR(timer_periph) = (uint32_t)autoreload; +} + +/*! + \brief configure TIMER counter register value + \param[in] timer_periph: TIMERx(x=0..6) + \param[in] counter: the counter value + \param[out] none + \retval none +*/ +void timer_counter_value_config(uint32_t timer_periph, uint16_t counter) +{ + TIMER_CNT(timer_periph) = (uint32_t)counter; +} + +/*! + \brief read TIMER counter value + \param[in] timer_periph: TIMERx(x=0..6) + \param[out] none + \retval counter value +*/ +uint32_t timer_counter_read(uint32_t timer_periph) +{ + uint32_t count_value = 0U; + count_value = TIMER_CNT(timer_periph); + return (count_value); +} + +/*! + \brief read TIMER prescaler value + \param[in] timer_periph: TIMERx(x=0..6) + \param[out] none + \retval prescaler register value +*/ +uint16_t timer_prescaler_read(uint32_t timer_periph) +{ + uint16_t prescaler_value = 0U; + prescaler_value = (uint16_t) (TIMER_PSC(timer_periph)); + return (prescaler_value); +} + +/*! + \brief configure TIMER single pulse mode + \param[in] timer_periph: TIMERx(x=0..6) + \param[in] spmode: + only one parameter can be selected which is shown as below: + \arg TIMER_SP_MODE_SINGLE: single pulse mode + \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode + \param[out] none + \retval none +*/ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) +{ + if(TIMER_SP_MODE_SINGLE == spmode){ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; + }else if(TIMER_SP_MODE_REPETITIVE == spmode){ + TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); + }else{ + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER update source + \param[in] timer_periph: TIMERx(x=0..6) + \param[in] update: + only one parameter can be selected which is shown as below: + \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow, + or the slave mode controller trigger + \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow + \param[out] none + \retval none +*/ +void timer_update_source_config(uint32_t timer_periph, uint32_t update) +{ + if(TIMER_UPDATE_SRC_REGULAR == update){ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; + }else if(TIMER_UPDATE_SRC_GLOBAL == update){ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; + }else{ + /* illegal parameters */ + } +} + + +/*! + \brief enable the TIMER DMA + \param[in] timer_periph: TIMERx(x=0..6) + \param[in] dma: specify which DMA to enable + one or more parameters can be selected which are shown as below: + \arg TIMER_DMA_UPD: update DMA enable, TIMERx(x=0..6) + \arg TIMER_DMA_CH0D: channel 0 DMA enable, TIMERx(x=0..4) + \arg TIMER_DMA_CH1D: channel 1 DMA enable, TIMERx(x=0..4) + \arg TIMER_DMA_CH2D: channel 2 DMA enable, TIMERx(x=0..4) + \arg TIMER_DMA_CH3D: channel 3 DMA enable, TIMERx(x=0..4) + \arg TIMER_DMA_CMTD: channel commutation DMA request enable, TIMERx(x=0) + \arg TIMER_DMA_TRGD: trigger DMA enable, TIMERx(x=0..4) + \param[out] none + \retval none +*/ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; +} + +/*! + \brief disable the TIMER DMA + \param[in] timer_periph: TIMERxTIMERx(x=0..6) + \param[in] dma: specify which DMA to disbale + one or more parameters can be selected which are shown as below: + \arg TIMER_DMA_UPD: update DMA enable, TIMERx(x=0..6) + \arg TIMER_DMA_CH0D: channel 0 DMA enable, TIMERx(x=0..4) + \arg TIMER_DMA_CH1D: channel 1 DMA enable, TIMERx(x=0..4) + \arg TIMER_DMA_CH2D: channel 2 DMA enable, TIMERx(x=0..4) + \arg TIMER_DMA_CH3D: channel 3 DMA enable, TIMERx(x=0..4) + \arg TIMER_DMA_CMTD: channel commutation DMA request enable, TIMERx(x=0) + \arg TIMER_DMA_TRGD: trigger DMA enable, TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); +} + +/*! + \brief channel DMA request source selection + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] dma_request: channel DMA request source selection + only one parameter can be selected which is shown as below: + \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel n is sent when channel n event occurs + \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel n is sent when update event occurs + \param[out] none + \retval none +*/ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request) +{ + if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; + }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){ + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief configure the TIMER DMA transfer + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] dma_baseaddr: + only one parameter can be selected which is shown as below: + \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0, TIMERx(x=0..4) + \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1, TIMERx(x=0..4) + \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG, TIMERx(x=0..4) + \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN, TIMERx(x=0..4) + \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF, TIMERx(x=0..4) + \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG, TIMERx(x=0..4) + \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0, TIMERx(x=0..4) + \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1, TIMERx(x=0..4) + \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2, TIMERx(x=0..4) + \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT, TIMERx(x=0..4) + \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC, TIMERx(x=0..4) + \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR, TIMERx(x=0..4) + \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP, TIMERx(x=0) + \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV, TIMERx(x=0..4) + \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV, TIMERx(x=0..4) + \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV, TIMERx(x=0..4) + \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV, TIMERx(x=0..4) + \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP, TIMERx(x=0) + \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG, TIMERx(x=0..4) + \param[in] dma_lenth: + only one parameter can be selected which is shown as below: + \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..6): DMA transfer x time + \param[out] none + \retval none +*/ +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) +{ + TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); + TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); +} + +/*! + \brief software generate events + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] event: the timer software event generation sources + one or more parameters can be selected which are shown as below: + \arg TIMER_EVENT_SRC_UPG: update event generation, TIMERx(x=0..6) + \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..4) + \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..4) + \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..4) + \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..4) + \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0) + \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0..4) + \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0) + \param[out] none + \retval none +*/ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event) +{ + TIMER_SWEVG(timer_periph) |= (uint32_t)event; +} + +/*! + \brief initialize TIMER break parameter struct with a default value + \param[in] breakpara: TIMER break parameter struct + \param[out] none + \retval none +*/ +void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) +{ + /* initialize the break parameter struct member with the default value */ + breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; + breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE; + breakpara->deadtime = 0U; + breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW; + breakpara->outputautostate = TIMER_OUTAUTO_DISABLE; + breakpara->protectmode = TIMER_CCHP_PROT_OFF; + breakpara->breakstate = TIMER_BREAK_DISABLE; +} + +/*! + \brief configure TIMER break function + \param[in] timer_periph: TIMERx(x=0) + \param[in] breakpara: TIMER break parameter struct + runoffstate: TIMER_ROS_STATE_ENABLE, TIMER_ROS_STATE_DISABLE + ideloffstate: TIMER_IOS_STATE_ENABLE, TIMER_IOS_STATE_DISABLE + deadtime: 0~255 + breakpolarity: TIMER_BREAK_POLARITY_LOW, TIMER_BREAK_POLARITY_HIGH + outputautostate: TIMER_OUTAUTO_ENABLE, TIMER_OUTAUTO_DISABLE + protectmode: TIMER_CCHP_PROT_OFF, TIMER_CCHP_PROT_0, TIMER_CCHP_PROT_1, TIMER_CCHP_PROT_2 + breakstate: TIMER_BREAK_ENABLE, TIMER_BREAK_DISABLE + \param[out] none + \retval none +*/ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara) +{ + TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | + ((uint32_t)(breakpara->ideloffstate))| + ((uint32_t)(breakpara->deadtime)) | + ((uint32_t)(breakpara->breakpolarity)) | + ((uint32_t)(breakpara->outputautostate)) | + ((uint32_t)(breakpara->protectmode)) | + ((uint32_t)(breakpara->breakstate))); +} + +/*! + \brief enable TIMER break function + \param[in] timer_periph: TIMERx(x=0) + \param[out] none + \retval none +*/ +void timer_break_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief disable TIMER break function + \param[in] timer_periph: TIMERx(x=0) + \param[out] none + \retval none +*/ +void timer_break_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief enable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0) + \param[out] none + \retval none +*/ +void timer_automatic_output_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief disable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0) + \param[out] none + \retval none +*/ +void timer_automatic_output_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief enable or disable TIMER primary output function + \param[in] timer_periph: TIMERx(x=0) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if(ENABLE == newvalue){ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; + }else{ + TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); + } +} + +/*! + \brief enable or disable channel capture/compare control shadow register + \param[in] timer_periph: TIMERx(x=0) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if(ENABLE == newvalue){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; + }else{ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); + } +} + +/*! + \brief configure TIMER channel control shadow register update control + \param[in] timer_periph: TIMERx(x=0) + \param[in] ccuctl: channel control shadow register update control + only one parameter can be selected which is shown as below: + \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set + \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl) +{ + if(TIMER_UPDATECTL_CCU == ccuctl){ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); + }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief initialize TIMER channel output parameter struct with a default value + \param[in] ocpara: TIMER channel n output parameter struct + \param[out] none + \retval none +*/ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara) +{ + /* initialize the channel output parameter struct member with the default value */ + ocpara->outputstate = TIMER_CCX_DISABLE; + ocpara->outputnstate = TIMER_CCXN_DISABLE; + ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; + ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; + ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; + ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; +} + +/*! + \brief configure TIMER channel output function + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) + \param[in] ocpara: TIMER channeln output parameter struct + outputstate: TIMER_CCX_ENABLE, TIMER_CCX_DISABLE + outputnstate: TIMER_CCXN_ENABLE, TIMER_CCXN_DISABLE + ocpolarity: TIMER_OC_POLARITY_HIGH, TIMER_OC_POLARITY_LOW + ocnpolarity: TIMER_OCN_POLARITY_HIGH, TIMER_OCN_POLARITY_LOW + ocidlestate: TIMER_OC_IDLE_STATE_LOW, TIMER_OC_IDLE_STATE_HIGH + ocnidlestate: TIMER_OCN_IDLE_STATE_LOW, TIMER_OCN_IDLE_STATE_HIGH + \param[out] none + \retval none +*/ +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; + /* reset the CH0P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + /* set the CH0P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; + + if (TIMER0 == timer_periph) { + /* reset the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + /* set the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; + /* reset the CH0NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + /* set the CH0NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; + /* reset the ISO0 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); + /* set the ISO0 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; + /* reset the ISO0N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); + /* set the ISO0N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; + } + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 4U); + /* reset the CH1P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + /* set the CH1P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); + + if (TIMER0 == timer_periph) { + /* reset the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + /* set the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U); + /* reset the ISO1 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); + /* set the ISO1 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); + /* reset the ISO1N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); + /* set the ISO1N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U); + } + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 8U); + /* reset the CH2P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + /* set the CH2P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); + + if (TIMER0 == timer_periph) { + /* reset the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + /* set the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U); + /* reset the CH2NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + /* set the CH2NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U); + /* reset the ISO2 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); + /* set the ISO2 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U); + /* reset the ISO2N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); + /* set the ISO2N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U); + } + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN); + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 12U); + /* reset the CH3P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + /* set the CH3P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); + + if (TIMER0 == timer_periph) { + /* reset the ISO3 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); + /* set the ISO3 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U); + } + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output compare mode + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) + \param[in] ocmode: channel output compare mode + only one parameter can be selected which is shown as below: + \arg TIMER_OC_MODE_TIMING: timing mode + \arg TIMER_OC_MODE_ACTIVE: active mode + \arg TIMER_OC_MODE_INACTIVE: inactive mode + \arg TIMER_OC_MODE_TOGGLE: toggle mode + \arg TIMER_OC_MODE_LOW: force low mode + \arg TIMER_OC_MODE_HIGH: force high mode + \arg TIMER_OC_MODE_PWM0: PWM mode 0 + \arg TIMER_OC_MODE_PWM1: PWM mode 1 + \param[out] none + \retval none +*/ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output pulse value + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) + \param[in] pulse: channel output pulse value + \param[out] none + \retval none +*/ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CH0CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CH1CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CH2CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CH3CV(timer_periph) = (uint32_t)pulse; + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output shadow function + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) + \param[in] ocshadow: channel output shadow state + only one parameter can be selected which is shown as below: + \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable + \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable + \param[out] none + \retval none +*/ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output fast function + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) + \param[in] ocfast: channel output fast function + only one parameter can be selected which is shown as below: + \arg TIMER_OC_FAST_ENABLE: channel output fast function enable + \arg TIMER_OC_FAST_DISABLE: channel output fast function disable + \param[out] none + \retval none +*/ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output clear function + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) + \param[in] occlear: channel output clear function + only one parameter can be selected which is shown as below: + \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable + \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable + \param[out] none + \retval none +*/ +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output polarity + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) + \param[in] ocpolarity: channel output polarity + only one parameter can be selected which is shown as below: + \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high + \arg TIMER_OC_POLARITY_LOW: channel output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output polarity + \param[in] timer_periph: TIMERx(x=0) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0)) + \param[in] ocnpolarity: channel complementary output polarity + only one parameter can be selected which is shown as below: + \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high + \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel enable state + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) + \param[in] state: TIMER channel enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCX_ENABLE: channel enable + \arg TIMER_CCX_DISABLE: channel disable + \param[out] none + \retval none +*/ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)state; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output enable state + \param[in] timer_periph: TIMERx(x=0) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0 + \arg TIMER_CH_1: TIMER channel 1 + \arg TIMER_CH_2: TIMER channel 2 + \param[in] ocnstate: TIMER channel complementary output enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCXN_ENABLE: channel complementary enable + \arg TIMER_CCXN_DISABLE: channel complementary disable + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); + break; + default: + break; + } +} + +/*! + \brief initialize TIMER channel input parameter struct with a default value + \param[in] icpara: TIMER channel intput parameter struct + \param[out] none + \retval none +*/ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) +{ + /* initialize the channel input parameter struct member with the default value */ + icpara->icpolarity = TIMER_IC_POLARITY_RISING; + icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; + icpara->icprescaler = TIMER_IC_PSC_DIV1; + icpara->icfilter = 0U; +} + +/*! + \brief configure TIMER input capture parameter + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) + \param[in] icpara: TIMER channel intput parameter struct + icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING, + TIMER_IC_POLARITY_BOTH_EDGE(only for TIMER1~TIMER8) + icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI, + TIMER_IC_SELECTION_ITS + icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4, + TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + break; + + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + + /* reset the CH2P and CH2NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); + + /* reset the CH2MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); + + /* reset the CH2CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + + /* reset the CH3P bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); + + /* reset the CH3MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + + /* reset the CH3CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; + break; + default: + break; + } + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler)); +} + +/*! + \brief configure TIMER channel input capture prescaler value + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) + \param[in] prescaler: channel input capture prescaler value + only one parameter can be selected which is shown as below: + \arg TIMER_IC_PSC_DIV1: no prescaler + \arg TIMER_IC_PSC_DIV2: divided by 2 + \arg TIMER_IC_PSC_DIV4: divided by 4 + \arg TIMER_IC_PSC_DIV8: divided by 8 + \param[out] none + \retval none +*/ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); + TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); + TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); + TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); + TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + default: + break; + } +} + +/*! + \brief read TIMER channel capture compare register value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) + \param[out] none + \retval channel capture compare register value +*/ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) +{ + uint32_t count_value = 0U; + + switch(channel){ + case TIMER_CH_0: + /* read TIMER channel 0 capture compare register value */ + count_value = TIMER_CH0CV(timer_periph); + break; + case TIMER_CH_1: + /* read TIMER channel 1 capture compare register value */ + count_value = TIMER_CH1CV(timer_periph); + break; + case TIMER_CH_2: + /* read TIMER channel 2 capture compare register value */ + count_value = TIMER_CH2CV(timer_periph); + break; + case TIMER_CH_3: + /* read TIMER channel 3 capture compare register value */ + count_value = TIMER_CH3CV(timer_periph); + break; + default: + break; + } + return (count_value); +} + +/*! + \brief configure TIMER input pwm capture function + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0 + \arg TIMER_CH_1: TIMER channel 1 + \param[in] icpwm: TIMER channel intput pwm parameter struct + icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING + icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI + icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4, + TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm) +{ + uint16_t icpolarity = 0x0U; + uint16_t icselection = 0x0U; + + /* Set channel input polarity */ + if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){ + icpolarity = TIMER_IC_POLARITY_FALLING; + }else{ + icpolarity = TIMER_IC_POLARITY_RISING; + } + /* Set channel input mode selection */ + if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){ + icselection = TIMER_IC_SELECTION_INDIRECTTI; + }else{ + icselection = TIMER_IC_SELECTION_DIRECTTI; + } + + if(TIMER_CH_0 == channel){ + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); + + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); + }else{ + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); + + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); + } +} + +/*! + \brief configure TIMER hall sensor mode + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] hallmode: + only one parameter can be selected which is shown as below: + \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable + \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable + \param[out] none + \retval none +*/ +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) +{ + if(TIMER_HALLINTERFACE_ENABLE == hallmode){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; + }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){ + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief select TIMER input trigger source + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] intrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..4)) + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..4)) + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..4)) + \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3(TIMERx(x=0..4)) + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0..4)) + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0..4)) + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0..4)) + \arg TIMER_SMCFG_TRGSEL_ETIFP: filtered external trigger input(TIMERx(x=0..4)) + \param[out] none + \retval none +*/ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); + TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; +} + +/*! + \brief select TIMER master mode output trigger source + \param[in] timer_periph: TIMERx(x=0..6) + \param[in] outrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..6)) + \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..6)) + \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..6)) + \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channel 0 as trigger output TRGO(TIMERx(x=0..4)) + \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..4)) + \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..4)) + \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..4)) + \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..4)) + \param[out] none + \retval none +*/ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) +{ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); + TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; +} + +/*! + \brief select TIMER slave mode + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] slavemode: + only one parameter can be selected which is shown as below: + \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable + \arg TIMER_ENCODER_MODE0: encoder mode 0 + \arg TIMER_ENCODER_MODE1: encoder mode 1 + \arg TIMER_ENCODER_MODE2: encoder mode 2 + \arg TIMER_SLAVE_MODE_RESTART: restart mode + \arg TIMER_SLAVE_MODE_PAUSE: pause mode + \arg TIMER_SLAVE_MODE_EVENT: event mode + \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0 + \param[out] none + \retval none +*/ + +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; +} + +/*! + \brief configure TIMER master slave mode + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] masterslave: + only one parameter can be selected which is shown as below: + \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable + \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable + \param[out] none + \retval none +*/ +void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) +{ + if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){ + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; + }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER external trigger input + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); +} + +/*! + \brief configure TIMER quadrature decoder mode + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] decomode: + only one parameter can be selected which is shown as below: + \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level + \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level + \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input + \param[in] ic0polarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[in] ic1polarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[out] none + \retval none +*/ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity) +{ + /* configure the quadrature decoder mode */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; + /* configure input capture selection */ + TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS))); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); + /* configure channel input capture polarity */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U)); +} + +/*! + \brief configure TIMER internal clock mode + \param[in] timer_periph: TIMERx(x=0..4) + \param[out] none + \retval none +*/ +void timer_internal_clock_config(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; +} + +/*! + \brief configure TIMER the internal trigger as external clock input + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] intrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 + \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 + \param[out] none + \retval none +*/ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) +{ + timer_input_trigger_source_select(timer_periph, intrigger); + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external trigger as external clock input + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] extrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: active low or falling edge active + \arg TIMER_IC_POLARITY_FALLING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter) +{ + if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){ + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + }else{ + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + } + /* select TIMER input trigger source */ + timer_input_trigger_source_select(timer_periph, extrigger); + /* reset the SMC bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + /* set the SMC bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external clock mode0 + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); + /* reset the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); + /* set the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); +} + +/*! + \brief configure TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0..4) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief disable TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0..4) + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_disable(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief enable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: specify which interrupt to enable + one or more parameters can be selected which are shown as below: + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..6) + \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4) + \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4) + \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4) + \arg TIMER_INT_CH3: channel 3 interrupt enable, TIMERx(x=0..4) + \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0) + \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4) + \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0) + \param[out] none + \retval none +*/ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; +} + +/*! + \brief disable the TIMER interrupt + \param[in] timer_periph: TIMERx(x=0..6) + \param[in] interrupt: specify which interrupt to disbale + one or more parameters can be selected which are shown as below: + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..6) + \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4) + \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4) + \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4) + \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4) + \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0) + \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4) + \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0) + \param[out] none + \retval none +*/ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); +} + +/*! + \brief get timer interrupt flag + \param[in] timer_periph: TIMERx(x=0..6) + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..6) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..4) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..4) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..4) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..4) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0) + \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) +{ + uint32_t val; + val = (TIMER_DMAINTEN(timer_periph) & interrupt); + if((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear TIMER interrupt flag + \param[in] timer_periph: TIMERx(x=0..6) + \param[in] interrupt: the timer interrupt bits + one or more parameters can be selected which are shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..6) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..4) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..4) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..4) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..4) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0..4) + \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0) + \param[out] none + \retval none +*/ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_INTF(timer_periph) = (~(uint32_t)interrupt); +} + +/*! + \brief get TIMER flags + \param[in] timer_periph: TIMERx(x=0..6) + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag, TIMERx(x=0..6) + \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..4) + \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..4) + \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..4) + \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..4) + \arg TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0) + \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0..4) + \arg TIMER_FLAG_BRK: break flag, TIMERx(x=0) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..4) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..4) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..4) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..4) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) +{ + if(RESET != (TIMER_INTF(timer_periph) & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear TIMER flags + \param[in] timer_periph: TIMERx(x=0..6) + \param[in] flag: the timer interrupt flags + one or more parameters can be selected which are shown as below: + \arg TIMER_FLAG_UP: update flag, TIMERx(x=0..6) + \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..4) + \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..4) + \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..4) + \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..4) + \arg TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0) + \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0..4) + \arg TIMER_FLAG_BRK: break flag, TIMERx(x=0) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..4) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..4) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..4) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..4) + \param[out] none + \retval none +*/ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag) +{ + TIMER_INTF(timer_periph) = (~(uint32_t)flag); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c new file mode 100644 index 0000000..feff1ed --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c @@ -0,0 +1,765 @@ +/*! + \file gd32vf103_usart.c + \brief USART driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + \version 2019-09-18, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_usart.h" + +/*! + \brief reset USART/UART + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_deinit(uint32_t usart_periph) +{ + switch(usart_periph){ + case USART0: + /* reset USART0 */ + rcu_periph_reset_enable(RCU_USART0RST); + rcu_periph_reset_disable(RCU_USART0RST); + break; + case USART1: + /* reset USART1 */ + rcu_periph_reset_enable(RCU_USART1RST); + rcu_periph_reset_disable(RCU_USART1RST); + break; + case USART2: + /* reset USART2 */ + rcu_periph_reset_enable(RCU_USART2RST); + rcu_periph_reset_disable(RCU_USART2RST); + break; + case UART3: + /* reset UART3 */ + rcu_periph_reset_enable(RCU_UART3RST); + rcu_periph_reset_disable(RCU_UART3RST); + break; + case UART4: + /* reset UART4 */ + rcu_periph_reset_enable(RCU_UART4RST); + rcu_periph_reset_disable(RCU_UART4RST); + break; + default: + break; + } +} + +/*! + \brief configure USART baud rate value + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] baudval: baud rate value + \param[out] none + \retval none +*/ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) +{ + uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U; + switch(usart_periph){ + /* get clock frequency */ + case USART0: + /* get USART0 clock */ + uclk=rcu_clock_freq_get(CK_APB2); + break; + case USART1: + /* get USART1 clock */ + uclk=rcu_clock_freq_get(CK_APB1); + break; + case USART2: + /* get USART2 clock */ + uclk=rcu_clock_freq_get(CK_APB1); + break; + case UART3: + /* get UART3 clock */ + uclk=rcu_clock_freq_get(CK_APB1); + break; + case UART4: + /* get UART4 clock */ + uclk=rcu_clock_freq_get(CK_APB1); + break; + default: + break; + } + /* oversampling by 16, configure the value of USART_BAUD */ + udiv = (uclk+baudval/2U)/baudval; + intdiv = udiv & (0x0000fff0U); + fradiv = udiv & (0x0000000fU); + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); +} + +/*! + \brief configure USART parity + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] paritycfg: configure USART parity + only one parameter can be selected which is shown as below: + \arg USART_PM_NONE: no parity + \arg USART_PM_ODD: odd parity + \arg USART_PM_EVEN: even parity + \param[out] none + \retval none +*/ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) +{ + /* clear USART_CTL0 PM,PCEN bits */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); + /* configure USART parity mode */ + USART_CTL0(usart_periph) |= paritycfg ; +} + +/*! + \brief configure USART word length + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] wlen: USART word length configure + only one parameter can be selected which is shown as below: + \arg USART_WL_8BIT: 8 bits + \arg USART_WL_9BIT: 9 bits + \param[out] none + \retval none +*/ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) +{ + /* clear USART_CTL0 WL bit */ + USART_CTL0(usart_periph) &= ~USART_CTL0_WL; + /* configure USART word length */ + USART_CTL0(usart_periph) |= wlen; +} + +/*! + \brief configure USART stop bit length + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] stblen: USART stop bit configure + only one parameter can be selected which is shown as below: + \arg USART_STB_1BIT: 1 bit + \arg USART_STB_0_5BIT: 0.5 bit, not available for UARTx(x=3,4) + \arg USART_STB_2BIT: 2 bits + \arg USART_STB_1_5BIT: 1.5 bits, not available for UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) +{ + /* clear USART_CTL1 STB bits */ + USART_CTL1(usart_periph) &= ~USART_CTL1_STB; + /* configure USART stop bits */ + USART_CTL1(usart_periph) |= stblen; +} + +/*! + \brief enable USART + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_UEN; +} + +/*! + \brief disable USART + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); +} + +/*! + \brief configure USART transmitter + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] txconfig: enable or disable USART transmitter + only one parameter can be selected which is shown as below: + \arg USART_TRANSMIT_ENABLE: enable USART transmission + \arg USART_TRANSMIT_DISABLE: disable USART transmission + \param[out] none + \retval none +*/ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL0(usart_periph); + ctl &= ~USART_CTL0_TEN; + ctl |= txconfig; + /* configure transfer mode */ + USART_CTL0(usart_periph) = ctl; +} + +/*! + \brief configure USART receiver + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] rxconfig: enable or disable USART receiver + only one parameter can be selected which is shown as below: + \arg USART_RECEIVE_ENABLE: enable USART reception + \arg USART_RECEIVE_DISABLE: disable USART reception + \param[out] none + \retval none +*/ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL0(usart_periph); + ctl &= ~USART_CTL0_REN; + ctl |= rxconfig; + /* configure receiver mode */ + USART_CTL0(usart_periph) = ctl; +} + +/*! + \brief USART transmit data function + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void usart_data_transmit(uint32_t usart_periph, uint32_t data) +{ + USART_DATA(usart_periph) = USART_DATA_DATA & data; +} + +/*! + \brief USART receive data function + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval data of received +*/ +uint16_t usart_data_receive(uint32_t usart_periph) +{ + return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U)); +} + +/*! + \brief configure the address of the USART in wake up by address match mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] addr: address of USART/UART + \param[out] none + \retval none +*/ +void usart_address_config(uint32_t usart_periph, uint8_t addr) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); + USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); +} + +/*! + \brief receiver in mute mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_mute_mode_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_RWU; +} + +/*! + \brief receiver in active mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_mute_mode_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU); +} + +/*! + \brief configure wakeup method in mute mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] wmethod: two methods be used to enter or exit the mute mode + only one parameter can be selected which is shown as below: + \arg USART_WM_IDLE: idle line + \arg USART_WM_ADDR: address mask + \param[out] none + \retval none +*/ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); + USART_CTL0(usart_periph) |= wmethod; +} + +/*! + \brief enable LIN mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_lin_mode_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_LMEN; +} + +/*! + \brief disable LIN mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_lin_mode_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); +} + +/*! + \brief configure lin break frame length + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] lblen: lin break frame length + only one parameter can be selected which is shown as below: + \arg USART_LBLEN_10B: 10 bits + \arg USART_LBLEN_11B: 11 bits + \param[out] none + \retval none +*/ +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); + USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); +} + +/*! + \brief send break frame + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_send_break(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD; +} + +/*! + \brief enable half duplex mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_halfduplex_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_HDEN; +} + +/*! + \brief disable half duplex mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_halfduplex_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); +} + +/*! + \brief enable CK pin in synchronous mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_synchronous_clock_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_CKEN; +} + +/*! + \brief disable CK pin in synchronous mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_synchronous_clock_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); +} + +/*! + \brief configure USART synchronous mode parameters + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] clen: CK length + only one parameter can be selected which is shown as below: + \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame + \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame + \param[in] cph: clock phase + only one parameter can be selected which is shown as below: + \arg USART_CPH_1CK: first clock transition is the first data capture edge + \arg USART_CPH_2CK: second clock transition is the first data capture edge + \param[in] cpl: clock polarity + only one parameter can be selected which is shown as below: + \arg USART_CPL_LOW: steady low value on CK pin + \arg USART_CPL_HIGH: steady high value on CK pin + \param[out] none + \retval none +*/ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) +{ + uint32_t ctl = 0U; + + /* read USART_CTL1 register */ + ctl = USART_CTL1(usart_periph); + ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); + /* set CK length, CK phase, CK polarity */ + ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); + + USART_CTL1(usart_periph) = ctl; +} + +/*! + \brief configure guard time value in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] gaut: guard time value + \param[out] none + \retval none +*/ +void usart_guard_time_config(uint32_t usart_periph,uint32_t gaut) +{ + USART_GP(usart_periph) &= ~(USART_GP_GUAT); + USART_GP(usart_periph) |= (USART_GP_GUAT & ((gaut)<<8)); +} + +/*! + \brief enable smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_SCEN; +} + +/*! + \brief disable smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); +} + +/*! + \brief enable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_NKEN; +} + +/*! + \brief disable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); +} + +/*! + \brief enable IrDA mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_irda_mode_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_IREN; +} + +/*! + \brief disable IrDA mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_irda_mode_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); +} + +/*! + \brief configure the peripheral clock prescaler in USART IrDA low-power mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] psc: 0x00-0xFF + \param[out] none + \retval none +*/ +void usart_prescaler_config(uint32_t usart_periph, uint8_t psc) +{ + USART_GP(usart_periph) &= ~(USART_GP_PSC); + USART_GP(usart_periph) |= psc; +} + +/*! + \brief configure IrDA low-power + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] irlp: IrDA low-power or normal + only one parameter can be selected which is shown as below: + \arg USART_IRLP_LOW: low-power + \arg USART_IRLP_NORMAL: normal + \param[out] none + \retval none +*/ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); + USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); +} + +/*! + \brief configure hardware flow control RTS + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] rtsconfig: enable or disable RTS + only one parameter can be selected which is shown as below: + \arg USART_RTS_ENABLE: enable RTS + \arg USART_RTS_DISABLE: disable RTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_RTSEN; + ctl |= rtsconfig; + /* configure RTS */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure hardware flow control CTS + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] ctsconfig: enable or disable CTS + only one parameter can be selected which is shown as below: + \arg USART_CTS_ENABLE: enable CTS + \arg USART_CTS_DISABLE: disable CTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_CTSEN; + ctl |= ctsconfig; + /* configure CTS */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure USART DMA reception + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) + \param[in] dmacmd: enable or disable DMA for reception + only one parameter can be selected which is shown as below: + \arg USART_DENR_ENABLE: DMA enable for reception + \arg USART_DENR_DISABLE: DMA disable for reception + \param[out] none + \retval none +*/ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_DENR; + ctl |= dmacmd; + /* configure DMA reception */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure USART DMA transmission + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) + \param[in] dmacmd: enable or disable DMA for transmission + only one parameter can be selected which is shown as below: + \arg USART_DENT_ENABLE: DMA enable for transmission + \arg USART_DENT_DISABLE: DMA disable for transmission + \param[out] none + \retval none +*/ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_DENT; + ctl |= dmacmd; + /* configure DMA transmission */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief get flag in STAT register + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] flag: USART flags, refer to usart_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_FLAG_CTS: CTS change flag + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_TBE: transmit data buffer empty + \arg USART_FLAG_TC: transmission complete + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_IDLE: IDLE frame detected flag + \arg USART_FLAG_ORERR: overrun error + \arg USART_FLAG_NERR: noise error flag + \arg USART_FLAG_FERR: frame error flag + \arg USART_FLAG_PERR: parity error flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) +{ + if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear flag in STAT register + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] flag: USART flags, refer to usart_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_FLAG_CTS: CTS change flag + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_TC: transmission complete + \arg USART_FLAG_RBNE: read data buffer not empty + \param[out] none + \retval none +*/ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) +{ + USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag)); +} + +/*! + \brief enable USART interrupt + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] interrupt + only one parameter can be selected which is shown as below: + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_TBE: transmitter buffer empty interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt + \arg USART_INT_IDLE: IDLE line detected interrupt + \arg USART_INT_LBD: LIN break detected interrupt + \arg USART_INT_ERR: error interrupt + \arg USART_INT_CTS: CTS interrupt + \param[out] none + \retval none +*/ +void usart_interrupt_enable(uint32_t usart_periph, uint32_t interrupt) +{ + USART_REG_VAL(usart_periph, interrupt) |= BIT(USART_BIT_POS(interrupt)); +} + +/*! + \brief disable USART interrupt + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] interrupt + only one parameter can be selected which is shown as below: + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_TBE: transmitter buffer empty interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt + \arg USART_INT_IDLE: IDLE line detected interrupt + \arg USART_INT_LBD: LIN break detected interrupt + \arg USART_INT_ERR: error interrupt + \arg USART_INT_CTS: CTS interrupt + \param[out] none + \retval none +*/ +void usart_interrupt_disable(uint32_t usart_periph, uint32_t interrupt) +{ + USART_REG_VAL(usart_periph, interrupt) &= ~BIT(USART_BIT_POS(interrupt)); +} + +/*! + \brief get USART interrupt and flag status + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] int_flag + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_PERR: parity error interrupt and flag + \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag + \arg USART_INT_FLAG_TC: transmission complete interrupt and flag + \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag + \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag + \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag + \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag + \arg USART_INT_FLAG_CTS: CTS interrupt and flag + \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error + \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag + \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U; + /* get the interrupt enable bit status */ + intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); + + if(flagstatus && intenable){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear USART interrupt flag in STAT register + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] int_flag: USART interrupt flag + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_CTS: CTS change flag + \arg USART_INT_FLAG_LBD: LIN break detected flag + \arg USART_INT_FLAG_TC: transmission complete + \arg USART_INT_FLAG_RBNE: read data buffer not empty + \param[out] none + \retval none +*/ +void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t int_flag) +{ + USART_REG_VAL2(usart_periph, int_flag) &= ~BIT(USART_BIT_POS2(int_flag)); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c new file mode 100644 index 0000000..e023ede --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c @@ -0,0 +1,146 @@ +/*! + \file gd32vf103_wwdgt.c + \brief WWDGT driver + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103_wwdgt.h" + +/* write value to WWDGT_CTL_CNT bit field */ +#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) +/* write value to WWDGT_CFG_WIN bit field */ +#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) + +/*! + \brief reset the window watchdog timer configuration + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_deinit(void) +{ + rcu_periph_reset_enable(RCU_WWDGTRST); + rcu_periph_reset_disable(RCU_WWDGTRST); +} + +/*! + \brief start the window watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_enable(void) +{ + WWDGT_CTL |= WWDGT_CTL_WDGTEN; +} + +/*! + \brief configure the window watchdog timer counter value + \param[in] counter_value: 0x00 - 0x7F + \param[out] none + \retval none +*/ +void wwdgt_counter_update(uint16_t counter_value) +{ + uint32_t reg = 0U; + + reg = (WWDGT_CTL & (~WWDGT_CTL_CNT)); + reg |= CTL_CNT(counter_value); + + WWDGT_CTL = reg; +} + +/*! + \brief configure counter value, window value, and prescaler divider value + \param[in] counter: 0x00 - 0x7F + \param[in] window: 0x00 - 0x7F + \param[in] prescaler: wwdgt prescaler value + only one parameter can be selected which is shown as below: + \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 + \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 + \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 + \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 + \param[out] none + \retval none +*/ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) +{ + uint32_t reg_cfg = 0U, reg_ctl = 0U; + + /* clear WIN and PSC bits, clear CNT bit */ + reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC))); + reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT)); + + /* configure WIN and PSC bits, configure CNT bit */ + reg_cfg |= CFG_WIN(window); + reg_cfg |= prescaler; + reg_ctl |= CTL_CNT(counter); + + WWDGT_CTL = reg_ctl; + WWDGT_CFG = reg_cfg; +} + +/*! + \brief enable early wakeup interrupt of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_interrupt_enable(void) +{ + WWDGT_CFG |= WWDGT_CFG_EWIE; +} + +/*! + \brief check early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus wwdgt_flag_get(void) +{ + if(WWDGT_STAT & WWDGT_STAT_EWIF){ + return SET; + } + + return RESET; +} + +/*! + \brief clear early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_flag_clear(void) +{ + WWDGT_STAT &= (~WWDGT_STAT_EWIF); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/gd32vf103.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/gd32vf103.h new file mode 100644 index 0000000..3aba7a5 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/gd32vf103.h @@ -0,0 +1,241 @@ +/*! + \file gd32vf103.h + \brief general definitions for GD32VF103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_H +#define GD32VF103_H + +#ifdef cplusplus + extern "C" { +#endif + + /* IO definitions (access restrictions to peripheral registers) */ + /** + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. + */ + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + + /* define value of high speed crystal oscillator (HXTAL) in Hz */ + #if !defined HXTAL_VALUE + #ifdef GD32VF103R_START + #define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */ + #define HXTAL_VALUE_8M HXTAL_VALUE +#elif defined(GD32VF103V_EVAL) || defined(GD32VF103C_START) || defined(GD32VF103T_START) + #define HXTAL_VALUE ((uint32_t)8000000) /*!< value of the external oscillator in Hz */ + #define HXTAL_VALUE_25M HXTAL_VALUE + #else + #error "Please select the target board type used in your application (in gd32vf103.h file)" + #endif + #endif /* high speed crystal oscillator value */ + +/* define startup timeout value of high speed crystal oscillator (HXTAL) */ +#if !defined (HXTAL_STARTUP_TIMEOUT) +#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF) +#endif /* high speed crystal oscillator startup timeout */ + +/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ +#if !defined (IRC8M_VALUE) +#define IRC8M_VALUE ((uint32_t)8000000) +#endif /* internal 8MHz RC oscillator value */ + +/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ +#if !defined (IRC8M_STARTUP_TIMEOUT) +#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) +#endif /* internal 8MHz RC oscillator startup timeout */ + +/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ +#if !defined (IRC40K_VALUE) +#define IRC40K_VALUE ((uint32_t)40000) +#endif /* internal 40KHz RC oscillator value */ + +/* define value of low speed crystal oscillator (LXTAL)in Hz */ +#if !defined (LXTAL_VALUE) +#define LXTAL_VALUE ((uint32_t)32768) +#endif /* low speed crystal oscillator value */ + +/* define interrupt number */ +typedef enum IRQn +{ + + CLIC_INT_RESERVED = 0, /*!< RISC-V reserved */ + CLIC_INT_SFT = 3, /*!< Software interrupt */ + CLIC_INT_TMR = 7, /*!< CPU Timer interrupt */ + CLIC_INT_BWEI = 17, /*!< Bus Error interrupt */ + CLIC_INT_PMOVI = 18, /*!< Performance Monitor */ + + /* interruput numbers */ + WWDGT_IRQn = 19, /*!< window watchDog timer interrupt */ + LVD_IRQn = 20, /*!< LVD through EXTI line detect interrupt */ + TAMPER_IRQn = 21, /*!< tamper through EXTI line detect */ + RTC_IRQn = 22, /*!< RTC alarm interrupt */ + FMC_IRQn = 23, /*!< FMC interrupt */ + RCU_CTC_IRQn = 24, /*!< RCU and CTC interrupt */ + EXTI0_IRQn = 25, /*!< EXTI line 0 interrupts */ + EXTI1_IRQn = 26, /*!< EXTI line 1 interrupts */ + EXTI2_IRQn = 27, /*!< EXTI line 2 interrupts */ + EXTI3_IRQn = 28, /*!< EXTI line 3 interrupts */ + EXTI4_IRQn = 29, /*!< EXTI line 4 interrupts */ + DMA0_Channel0_IRQn = 30, /*!< DMA0 channel0 interrupt */ + DMA0_Channel1_IRQn = 31, /*!< DMA0 channel1 interrupt */ + DMA0_Channel2_IRQn = 32, /*!< DMA0 channel2 interrupt */ + DMA0_Channel3_IRQn = 33, /*!< DMA0 channel3 interrupt */ + DMA0_Channel4_IRQn = 34, /*!< DMA0 channel4 interrupt */ + DMA0_Channel5_IRQn = 35, /*!< DMA0 channel5 interrupt */ + DMA0_Channel6_IRQn = 36, /*!< DMA0 channel6 interrupt */ + ADC0_1_IRQn = 37, /*!< ADC0 and ADC1 interrupt */ + CAN0_TX_IRQn = 38, /*!< CAN0 TX interrupts */ + CAN0_RX0_IRQn = 39, /*!< CAN0 RX0 interrupts */ + CAN0_RX1_IRQn = 40, /*!< CAN0 RX1 interrupts */ + CAN0_EWMC_IRQn = 41, /*!< CAN0 EWMC interrupts */ + EXTI5_9_IRQn = 42, /*!< EXTI[9:5] interrupts */ + TIMER0_BRK_IRQn = 43, /*!< TIMER0 break interrupts */ + TIMER0_UP_IRQn = 44, /*!< TIMER0 update interrupts */ + TIMER0_TRG_CMT_IRQn = 45, /*!< TIMER0 trigger and commutation interrupts */ + TIMER0_Channel_IRQn = 46, /*!< TIMER0 channel capture compare interrupts */ + TIMER1_IRQn = 47, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 48, /*!< TIMER2 interrupt */ + TIMER3_IRQn = 49, /*!< TIMER3 interrupts */ + I2C0_EV_IRQn = 50, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 51, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 52, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 53, /*!< I2C1 error interrupt */ + SPI0_IRQn = 54, /*!< SPI0 interrupt */ + SPI1_IRQn = 55, /*!< SPI1 interrupt */ + USART0_IRQn = 56, /*!< USART0 interrupt */ + USART1_IRQn = 57, /*!< USART1 interrupt */ + USART2_IRQn = 58, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 59, /*!< EXTI[15:10] interrupts */ + RTC_ALARM_IRQn = 60, /*!< RTC alarm interrupt EXTI */ + USBFS_WKUP_IRQn = 61, /*!< USBFS wakeup interrupt */ + + EXMC_IRQn = 67, /*!< EXMC global interrupt */ + + TIMER4_IRQn = 69, /*!< TIMER4 global interrupt */ + SPI2_IRQn = 70, /*!< SPI2 global interrupt */ + UART3_IRQn = 71, /*!< UART3 global interrupt */ + UART4_IRQn = 72, /*!< UART4 global interrupt */ + TIMER5_IRQn = 73, /*!< TIMER5 global interrupt */ + TIMER6_IRQn = 74, /*!< TIMER6 global interrupt */ + DMA1_Channel0_IRQn = 75, /*!< DMA1 channel0 global interrupt */ + DMA1_Channel1_IRQn = 76, /*!< DMA1 channel1 global interrupt */ + DMA1_Channel2_IRQn = 77, /*!< DMA1 channel2 global interrupt */ + DMA1_Channel3_IRQn = 78, /*!< DMA1 channel3 global interrupt */ + DMA1_Channel4_IRQn = 79, /*!< DMA1 channel3 global interrupt */ + + CAN1_TX_IRQn = 82, /*!< CAN1 TX interrupt */ + CAN1_RX0_IRQn = 83, /*!< CAN1 RX0 interrupt */ + CAN1_RX1_IRQn = 84, /*!< CAN1 RX1 interrupt */ + CAN1_EWMC_IRQn = 85, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 86, /*!< USBFS global interrupt */ + + ECLIC_NUM_INTERRUPTS +} IRQn_Type; + +/* includes */ +#include "system_gd32vf103.h" +#include + +/* enum definitions */ +typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; +typedef enum {FALSE = 0, TRUE = !FALSE} bool; +typedef enum {RESET = 0, SET = 1,MAX = 0X7FFFFFFF} FlagStatus; +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; + +/* bit operations */ +#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) +#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) +#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) +#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) + +/* main flash and SRAM memory map */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ +#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */ +#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ +#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ +#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */ + +/* peripheral memory map */ +#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ +#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ +#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */ +#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */ + +/* advanced peripheral bus 1 memory map */ +#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ +#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ +#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ +#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ +#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ +#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ +#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ +#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ +#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */ +#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ +#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ + +/* advanced peripheral bus 2 memory map */ +#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */ +#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ +#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */ +#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ + +/* advanced high performance bus 1 memory map */ +#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */ +#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */ +#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */ +#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ +#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ + +/* define marco USE_STDPERIPH_DRIVER */ +#if !defined USE_STDPERIPH_DRIVER +#define USE_STDPERIPH_DRIVER +#endif +#ifdef USE_STDPERIPH_DRIVER +#include "gd32vf103_libopt.h" +#endif /* USE_STDPERIPH_DRIVER */ + +#ifdef cplusplus +} +#endif +#endif diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/system_gd32vf103.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/system_gd32vf103.c new file mode 100644 index 0000000..f787347 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/system_gd32vf103.c @@ -0,0 +1,999 @@ +/*! + \file system_gd32vf103.c + \brief RISC-V Device Peripheral Access Layer Source File for + GD32VF103 Device Series + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32vf103.h" + +/* system frequency define */ +#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ + +/* select a system clock by uncommenting the following line */ +/* use IRC8M */ +//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000) + +/********************************************************************/ +//#define __SYSTEM_CLOCK_HXTAL (HXTAL_VALUE) +//#define __SYSTEM_CLOCK_24M_PLL_HXTAL (uint32_t)(24000000) +/********************************************************************/ + +//#define __SYSTEM_CLOCK_36M_PLL_HXTAL (uint32_t)(36000000) +//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_56M_PLL_HXTAL (uint32_t)(56000000) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000) +#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) + +#define SEL_IRC8M 0x00U +#define SEL_HXTAL 0x01U +#define SEL_PLL 0x02U + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_48M_PLL_IRC8M +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M; +static void system_clock_48m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M; +static void system_clock_72m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M; +static void system_clock_108m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; +static void system_clock_hxtal(void); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_24M_PLL_HXTAL; +static void system_clock_24m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_36M_PLL_HXTAL; +static void system_clock_36m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL; +static void system_clock_48m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_56M_PLL_HXTAL; +static void system_clock_56m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; +static void system_clock_72m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL; +static void system_clock_96m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; +static void system_clock_108m_hxtal(void); +#else +uint32_t SystemCoreClock = IRC8M_VALUE; +#endif /* __SYSTEM_CLOCK_48M_PLL_IRC8M */ + +/* configure the system clock */ +static void system_clock_config(void); + +/*! + \brief configure the system clock + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_config(void) +{ +#ifdef __SYSTEM_CLOCK_HXTAL + system_clock_hxtal(); +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) + system_clock_24m_hxtal(); +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) + system_clock_36m_hxtal(); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) + system_clock_48m_hxtal(); +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) + system_clock_56m_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) + system_clock_72m_hxtal(); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) + system_clock_96m_hxtal(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) + system_clock_108m_hxtal(); + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) + system_clock_48m_irc8m(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) + system_clock_72m_irc8m(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) + system_clock_108m_irc8m(); +#endif /* __SYSTEM_CLOCK_HXTAL */ +} + +/*! + \brief setup the microcontroller system, initialize the system + \param[in] none + \param[out] none + \retval none +*/ +void SystemInit(void) +{ + /* reset the RCC clock configuration to the default reset state */ + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL); + + /* reset HXTALEN, CKMEN, PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); + + /* Reset HXTALBPS bit */ + RCU_CTL &= ~(RCU_CTL_HXTALBPS); + + /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */ + + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | + RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4); + RCU_CFG1 = 0x00000000U; + + /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + /* disable all interrupts */ + RCU_INT = 0x00FF0000U; + + /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ + system_clock_config(); +} + +/*! + \brief update the SystemCoreClock with current core clock retrieved from cpu registers + \param[in] none + \param[out] none + \retval none +*/ +void SystemCoreClockUpdate(void) +{ + uint32_t scss; + uint32_t pllsel, predv0sel, pllmf, ck_src; + uint32_t predv0, predv1, pll1mf; + + scss = GET_BITS(RCU_CFG0, 2, 3); + + switch (scss) + { + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + SystemCoreClock = IRC8M_VALUE; + break; + + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + SystemCoreClock = HXTAL_VALUE; + break; + + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + + + if(RCU_PLLSRC_IRC8M_DIV2 == pllsel){ + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE / 2U; + }else{ + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + + predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); + + /* source clock use PLL1 */ + if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ + predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; + pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; + if(17U == pll1mf){ + pll1mf = 20U; + } + ck_src = (ck_src / predv1) * pll1mf; + } + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; + ck_src /= predv0; + } + + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + + if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ + pllmf |= 0x10U; + } + + if(pllmf >= 15U){ + pllmf += 1U; + }else{ + pllmf += 2U; + } + + SystemCoreClock = ck_src * pllmf; + + if(15U == pllmf){ + /* PLL source clock multiply by 6.5 */ + SystemCoreClock = ck_src * 6U + ck_src / 2U; + } + + break; + + /* IRC8M is selected as CK_SYS */ + default: + SystemCoreClock = IRC8M_VALUE; + break; + } +} + +#ifdef __SYSTEM_CLOCK_HXTAL +/*! + \brief configure the system clock to HXTAL + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + + /* wait until HXTAL is selected as system clock */ + while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) +/*! + \brief configure the system clock to 24M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_24m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 6 = 24 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) +/*! + \brief configure the system clock to 36M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_36m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 9 = 36 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +/*! + \brief configure the system clock to 48M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12); + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) +/*! + \brief configure the system clock to 56M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_56m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 14 = 56 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL14); + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +/*! + \brief configure the system clock to 72M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18); + + + if(HXTAL_VALUE==25000000){ + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +/*! + \brief configure the system clock to 96M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_96m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + if(HXTAL_VALUE==25000000){ + + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } + + }else if(HXTAL_VALUE==8000000){ + /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); + + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); + } + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +/*! + \brief configure the system clock to 108M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ + +static void system_clock_108m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27); + + if(HXTAL_VALUE==25000000){ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PREDV1_DIV5 | RCU_PLL1_MUL8 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL2EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){ + } + }else if(HXTAL_VALUE==8000000){ + RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 | RCU_PREDV1_DIV2 | RCU_PLL1_MUL20 | RCU_PLL2_MUL20); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ + } + + /* enable PLL2 */ + RCU_CTL |= RCU_CTL_PLL2EN; + /* wait till PLL1 is ready */ + while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){ + } + + } + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) +/*! + \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL12; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +/*! + \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL18; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +/*! + \brief configure the system clock to 108M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); + RCU_CFG0 |= RCU_PLL_MUL27; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#endif diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/system_gd32vf103.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/system_gd32vf103.h new file mode 100644 index 0000000..9626310 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_standard_peripheral/system_gd32vf103.h @@ -0,0 +1,60 @@ +/*! + \file system_gd32vf103.h + \brief RISC-V Device Peripheral Access Layer Header File for + GD32VF103 Device Series + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */ + +#ifndef SYSTEM_GD32VF103_H +#define SYSTEM_GD32VF103_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* system clock frequency (core clock) */ +extern uint32_t SystemCoreClock; + +/* function declarations */ +/* initialize the system and update the SystemCoreClock variable */ +extern void SystemInit(void); +/* update the SystemCoreClock with current core clock retrieved from cpu registers */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_GD32VF103_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_core.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_core.h new file mode 100644 index 0000000..70563ec --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_core.h @@ -0,0 +1,117 @@ +/*! + \file drv_usb_core.h + \brief USB core low level driver header file + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_CORE_H +#define __DRV_USB_CORE_H + +#include "drv_usb_regs.h" +#include "usb_ch9_std.h" + +#define USB_FS_EP0_MAX_LEN 64U /* maximum packet size of EndPoint0 */ + +#define HC_MAX_PACKET_COUNT 140U /* maximum packet count */ + +#define EP_ID(x) ((uint8_t)((x) & 0x7FU)) /* endpoint number */ +#define EP_DIR(x) ((uint8_t)((x) >> 7)) /* endpoint direction */ + +enum _usb_eptype { + USB_EPTYPE_CTRL = 0U, /*!< control endpoint type */ + USB_EPTYPE_ISOC = 1U, /*!< isochronous endpoint type */ + USB_EPTYPE_BULK = 2U, /*!< bulk endpoint type */ + USB_EPTYPE_INTR = 3U, /*!< interrupt endpoint type */ + USB_EPTYPE_MASK = 3U, /*!< endpoint type mask */ +}; + +typedef enum +{ + USB_OTG_OK = 0, /*!< USB OTG status OK*/ + USB_OTG_FAIL /*!< USB OTG status fail*/ +} usb_otg_status; + +typedef enum +{ + USB_OK = 0, /*!< USB status OK*/ + USB_FAIL /*!< USB status fail*/ +} usb_status; + +typedef enum +{ + USB_USE_FIFO, /*!< USB use FIFO transfer mode */ + USB_USE_DMA /*!< USB use DMA transfer mode */ +} usb_transfer_mode; + +typedef struct +{ + uint8_t core_enum; /*!< USB core type */ + uint8_t core_speed; /*!< USB core speed */ + uint8_t num_pipe; /*!< USB host channel numbers */ + uint8_t num_ep; /*!< USB device endpoint numbers */ + uint8_t transfer_mode; /*!< USB transfer mode */ + uint8_t phy_itf; /*!< USB core PHY interface */ + uint8_t sof_enable; /*!< USB SOF output */ + uint8_t low_power; /*!< USB low power */ +} usb_core_basic; + +/* function declarations */ + +/* config core capabilities */ +usb_status usb_basic_init (usb_core_basic *usb_basic, + usb_core_regs *usb_regs, + usb_core_enum usb_core); + +/*initializes the USB controller registers and prepares the core device mode or host mode operation*/ +usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs); + +/* read a packet from the Rx FIFO associated with the endpoint */ +void *usb_rxfifo_read (usb_core_regs *core_regs, uint8_t *dest_buf, uint16_t byte_count); + +/* write a packet into the Tx FIFO associated with the endpoint */ +usb_status usb_txfifo_write (usb_core_regs *usb_regs, + uint8_t *src_buf, + uint8_t fifo_num, + uint16_t byte_count); + +/* flush a Tx FIFO or all Tx FIFOs */ +usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num); + +/* flush the entire Rx FIFO */ +usb_status usb_rxfifo_flush (usb_core_regs *usb_regs); + +/* get the global interrupts */ +static inline uint32_t usb_coreintr_get(usb_core_regs *usb_regs) +{ + return usb_regs->gr->GINTEN & usb_regs->gr->GINTF; +} + +#endif /* __DRV_USB_CORE_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_dev.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_dev.h new file mode 100644 index 0000000..6b85712 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_dev.h @@ -0,0 +1,217 @@ +/*! + \file drv_usb_dev.h + \brief USB device low level driver header file + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_DEV_H +#define __DRV_USB_DEV_H + +#include "drv_usb_core.h" + +enum usb_ctl_status { + USB_CTL_IDLE = 0U, /*!< USB control transfer idle state */ + USB_CTL_DATA_IN, /*!< USB control transfer data in state */ + USB_CTL_LAST_DATA_IN, /*!< USB control transfer last data in state */ + USB_CTL_DATA_OUT, /*!< USB control transfer data out state */ + USB_CTL_LAST_DATA_OUT, /*!< USB control transfer last data out state */ + USB_CTL_STATUS_IN, /*!< USB control transfer status in state*/ + USB_CTL_STATUS_OUT /*!< USB control transfer status out state */ +}; + +#define EP_IN(x) ((uint8_t)(0x80U | (x))) /*!< device IN endpoint */ +#define EP_OUT(x) ((uint8_t)(x)) /*!< device OUT endpoint */ + +/* USB descriptor */ +typedef struct _usb_desc { + uint8_t *dev_desc; /*!< device descriptor */ + uint8_t *config_desc; /*!< config descriptor */ + uint8_t *bos_desc; /*!< BOS descriptor */ + + void* const *strings; /*!< string descriptor */ +} usb_desc; + +/* USB power management */ +typedef struct _usb_pm { + uint8_t power_mode; /*!< power mode */ + uint8_t power_low; /*!< power low */ + uint8_t dev_remote_wakeup; /*!< remote wakeup */ + uint8_t remote_wakeup_on; /*!< remote wakeup on */ +} usb_pm; + +/* USB control information */ +typedef struct _usb_control { + usb_req req; /*!< USB standard device request */ + + uint8_t ctl_state; /*!< USB control transfer state */ + uint8_t ctl_zlp; /*!< zero lenth package */ +} usb_control; + +typedef struct +{ + struct { + uint8_t num: 4; /*!< the endpoint number.it can be from 0 to 6 */ + uint8_t pad: 3; /*!< padding between number and direction */ + uint8_t dir: 1; /*!< the endpoint direction */ + } ep_addr; + + uint8_t ep_type; /*!< USB endpoint type */ + uint8_t ep_stall; /*!< USB endpoint stall status */ + + uint8_t frame_num; /*!< number of frame */ + uint16_t max_len; /*!< Maximum packet lenth */ + + /* transaction level variables */ + uint8_t *xfer_buf; /*!< transmit buffer */ + uint32_t xfer_len; /*!< transmit buffer length */ + uint32_t xfer_count; /*!< transmit buffer count */ + + uint32_t remain_len; /*!< remain packet lenth */ + + uint32_t dma_addr; /*!< DMA address */ +} usb_transc; + +typedef struct _usb_core_driver usb_dev; + +typedef struct _usb_class_core +{ + uint8_t command; /*!< device class request command */ + uint8_t alter_set; /*!< alternative set */ + + uint8_t (*init) (usb_dev *udev, uint8_t config_index); /*!< initialize handler */ + uint8_t (*deinit) (usb_dev *udev, uint8_t config_index); /*!< de-initialize handler */ + + uint8_t (*req_proc) (usb_dev *udev, usb_req *req); /*!< device request handler */ + + uint8_t (*data_in) (usb_dev *udev, uint8_t ep_num); /*!< device data in handler */ + uint8_t (*data_out) (usb_dev *udev, uint8_t ep_num); /*!< device data out handler */ + + uint8_t (*SOF) (usb_dev *udev); /*!< Start of frame handler */ + + uint8_t (*incomplete_isoc_in) (usb_dev *udev); /*!< Incomplete synchronization IN transfer handler */ + uint8_t (*incomplete_isoc_out) (usb_dev *udev); /*!< Incomplete synchronization OUT transfer handler */ +} usb_class_core; + +typedef struct _usb_perp_dev +{ + uint8_t config; /*!< configuration */ + uint8_t dev_addr; /*!< device address */ + + __IO uint8_t cur_status; /*!< current status */ + __IO uint8_t backup_status; /*!< backup status */ + + usb_transc transc_in[USBFS_MAX_TX_FIFOS]; /*!< endpoint IN transaction */ + usb_transc transc_out[USBFS_MAX_TX_FIFOS]; /*!< endpoint OUT transaction */ + + usb_pm pm; /*!< power management */ + usb_desc desc; /*!< USB descriptors */ + usb_control control; /*!< USB control information */ + + usb_class_core *class_core; /*!< class driver */ +} usb_perp_dev; + +typedef struct _usb_core_driver +{ + usb_core_basic bp; /*!< USB basic parameters */ + usb_core_regs regs; /*!< USB registers */ + usb_perp_dev dev; /*!< USB peripheral device */ +} usb_core_driver; + +/* function declarations */ + +/* initialize USB core registers for device mode */ +usb_status usb_devcore_init (usb_core_driver *udev); + +/* enable the USB device mode interrupts */ +usb_status usb_devint_enable (usb_core_driver *udev); + +/* active the usb transaction */ +usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc); + +/* deactive the usb transaction */ +usb_status usb_transc_deactivate (usb_core_driver *udev, usb_transc *transc); + +/* configure usb transaction to start IN transfer */ +usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc); + +/* configure usb transaction to start OUT transfer */ +usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc); + +/* set the usb transaction STALL status */ +usb_status usb_transc_stall (usb_core_driver *udev, usb_transc *transc); + +/* clear the usb transaction STALL status */ +usb_status usb_transc_clrstall (usb_core_driver *udev, usb_transc *transc); + +/* read device all OUT endpoint interrupt register */ +uint32_t usb_oepintnum_read (usb_core_driver *udev); + +/* read device OUT endpoint interrupt flag register */ +uint32_t usb_oepintr_read (usb_core_driver *udev, uint8_t ep_num); + +/* read device all IN endpoint interrupt register */ +uint32_t usb_iepintnum_read (usb_core_driver *udev); + +/* read device IN endpoint interrupt flag register */ +uint32_t usb_iepintr_read (usb_core_driver *udev, uint8_t ep_num); + +/* config the USB device to be disconnected */ +void usb_dev_disconnect (usb_core_driver *udev); + +/* config the USB device to be connected */ +void usb_dev_connect (usb_core_driver *udev); + +/* set the USB device address */ +void usb_devaddr_set (usb_core_driver *pudev, uint8_t dev_addr); + +/* configures OUT endpoint 0 to receive SETUP packets */ +void usb_ctlep_startout (usb_core_driver *udev); + +/* active remote wakeup signalling */ +void usb_rwkup_active (usb_core_driver *udev); + +/* reset remote wakeup signalling */ +void usb_rwkup_reset (usb_core_driver *udev); + +/* set remote wakeup signalling */ +void usb_rwkup_set (usb_core_driver *udev); + +/* active USB core clock */ +void usb_clock_active (usb_core_driver *udev); + +/* usb device suspend */ +void usb_dev_suspend (usb_core_driver *udev); + +/* stop the device and clean up fifos */ +void usb_dev_stop (usb_core_driver *udev); + +#endif /* __DRV_USB_DEV_H */ + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_host.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_host.h new file mode 100644 index 0000000..e31f3e5 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_host.h @@ -0,0 +1,175 @@ +/*! + \file drv_usb_host.h + \brief USB host mode low level driver header file + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_HOST_H +#define __DRV_USB_HOST_H + +#include "drv_usb_regs.h" +#include "usb_ch9_std.h" +#include "drv_usb_core.h" + +typedef enum _usb_pipe_status +{ + PIPE_IDLE = 0U, + PIPE_XF, + PIPE_HALTED, + PIPE_NAK, + PIPE_NYET, + PIPE_STALL, + PIPE_TRACERR, + PIPE_BBERR, + PIPE_REQOVR, + PIPE_DTGERR, +} usb_pipe_staus; + +typedef enum _usb_pipe_mode +{ + PIPE_PERIOD = 0U, + PIPE_NON_PERIOD = 1U +} usb_pipe_mode; + +typedef enum _usb_urb_state +{ + URB_IDLE = 0U, + URB_DONE, + URB_NOTREADY, + URB_ERROR, + URB_STALL +} usb_urb_state; + +typedef struct _usb_pipe +{ + uint8_t in_used; + uint8_t dev_addr; + uint32_t dev_speed; + + struct { + uint8_t num; + uint8_t dir; + uint8_t type; + uint16_t mps; + } ep; + + uint8_t ping; + uint32_t DPID; + + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t xfer_count; + + uint8_t data_toggle_in; + uint8_t data_toggle_out; + + __IO uint32_t err_count; + __IO usb_pipe_staus pp_status; + __IO usb_urb_state urb_state; +} usb_pipe; + + +typedef struct _usb_host_drv +{ + uint8_t rx_buf[512U]; + __IO uint32_t connect_status; + __IO uint32_t port_enabled; + __IO uint32_t backup_xfercount[USBFS_MAX_TX_FIFOS]; + + usb_pipe pipe[USBFS_MAX_TX_FIFOS]; +} usb_host_drv; + +typedef struct _usb_core_driver +{ + usb_core_basic bp; + + usb_core_regs regs; + + usb_host_drv host; +} usb_core_driver; + +/* initializes USB core for host mode */ +usb_status usb_host_init (usb_core_driver *pudev); + +/* initialize host pipe */ +usb_status usb_pipe_init (usb_core_driver *pudev, uint8_t pipe_num); + +/* prepare host pipe for transferring packets */ +usb_status usb_pipe_xfer (usb_core_driver *pudev, uint8_t pipe_num); + +/* halt host pipe */ +usb_status usb_pipe_halt (usb_core_driver *pudev, uint8_t pipe_num); + +/* configure host pipe to do ping operation */ +usb_status usb_pipe_ping (usb_core_driver *pudev, uint8_t pipe_num); + +/* reset host port */ +uint32_t usb_port_reset (usb_core_driver *pudev); + +/* control the VBUS to power */ +void usb_portvbus_switch (usb_core_driver *pudev, uint8_t state); + +/* stop the USB host and clean up FIFO */ +void usb_host_stop (usb_core_driver *pudev); + +//__STATIC_INLINE uint8_t usb_frame_even (usb_core_driver *pudev) +uint32_t usb_frame_even (usb_core_driver *pudev); +//{ + // return !(pudev->regs.hr->HFINFR & 0x01U); +//} + +//__STATIC_INLINE void usb_phyclock_config (usb_core_driver *pudev, uint8_t clock) +void usb_phyclock_config (usb_core_driver *pudev, uint8_t clock) ; +//{ + //pudev->regs.hr->HCTL &= ~HCTL_CLKSEL; + // pudev->regs.hr->HCTL |= clock; +//} + +uint32_t usb_port_read (usb_core_driver *pudev); +//inline uint32_t usb_port_read (usb_core_driver *pudev) +//{ + // return *pudev->regs.HPCS & ~(HPCS_PE | HPCS_PCD | HPCS_PEDC); +//} + +uint32_t usb_curspeed_get (usb_core_driver *pudev); + +//inline uint32_t usb_curspeed_get (usb_core_driver *pudev) +//{ + // return *pudev->regs.HPCS & HPCS_PS; +//} + +//__STATIC_INLINE uint32_t usb_curframe_get (usb_core_driver *pudev) +uint32_t usb_curframe_get (usb_core_driver *pudev); +//{ + // return (pudev->regs.hr->HFINFR & 0xFFFFU); +//} + +#endif /* __DRV_USB_HOST_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_hw.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_hw.h new file mode 100644 index 0000000..058efa8 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_hw.h @@ -0,0 +1,62 @@ +/*! + \file drv_usb_hw.h + \brief usb hardware configuration header file + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_HW_H +#define __DRV_USB_HW_H + +#include "usb_conf.h" + +/* configure USB clock */ +void usb_rcu_config (void); + +/* configure USB interrupt */ +void usb_intr_config (void); + +/* initializes delay unit using Timer2 */ +void usb_timer_init (void); + +/* delay in micro seconds */ +void usb_udelay (const uint32_t usec); + +/* delay in milli seconds */ +void usb_mdelay (const uint32_t msec); + +#ifdef USE_HOST_MODE +/* configure USB VBus */ + void usb_vbus_config (void); +/* drive usb VBus */ + void usb_vbus_drive (uint8_t State); +#endif /* USE_HOST_MODE */ + +#endif /* __DRV_USB_HW_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_regs.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_regs.h new file mode 100644 index 0000000..451fd6f --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usb_regs.h @@ -0,0 +1,666 @@ +/*! + \file drv_usb_regs.h + \brief USB cell registers definition and handle macros + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_REGS_H +#define __DRV_USB_REGS_H + +#include "usb_conf.h" + +#define USBHS_REG_BASE 0x40040000L /*!< base address of USBHS registers */ +#define USBFS_REG_BASE 0x50000000L /*!< base address of USBFS registers */ + +#define USBFS_MAX_TX_FIFOS 15 /*!< FIFO number */ + +#define USBFS_MAX_PACKET_SIZE 64U /*!< USBFS max packet size */ +#define USBFS_MAX_CHANNEL_COUNT 8U /*!< USBFS host channel count */ +#define USBFS_MAX_EP_COUNT 4U /*!< USBFS device endpoint count */ +#define USBFS_MAX_FIFO_WORDLEN 320U /*!< USBFS max fifo size in words */ + +#define USBHS_MAX_PACKET_SIZE 512U /*!< USBHS max packet size */ +#define USBHS_MAX_CHANNEL_COUNT 12U /*!< USBHS host channel count */ +#define USBHS_MAX_EP_COUNT 6U /*!< USBHS device endpoint count */ +#define USBHS_MAX_FIFO_WORDLEN 1280U /*!< USBHS max fifo size in words */ + +#define USB_DATA_FIFO_OFFSET 0x1000U /*!< USB data fifo offset */ +#define USB_DATA_FIFO_SIZE 0x1000U /*!< USB data fifo size */ + +typedef enum +{ + USB_CORE_ENUM_HS = 0, /*!< USB core type is HS */ + USB_CORE_ENUM_FS = 1 /*!< USB core type is FS */ +} usb_core_enum; + +enum usb_reg_offset { + USB_REG_OFFSET_CORE = 0x0000U, /*!< global OTG control and status register */ + USB_REG_OFFSET_DEV = 0x0800U, /*!< device mode control and status registers */ + USB_REG_OFFSET_EP = 0x0020U, + USB_REG_OFFSET_EP_IN = 0x0900U, /*!< device IN endpoint 0 control register */ + USB_REG_OFFSET_EP_OUT = 0x0B00U, /*!< device OUT endpoint 0 control register */ + USB_REG_OFFSET_HOST = 0x0400U, /*!< host control register */ + USB_REG_OFFSET_CH = 0x0020U, + USB_REG_OFFSET_PORT = 0x0440U, /*!< host port control and status register */ + USB_REG_OFFSET_CH_INOUT = 0x0500U, /*!< Host channel-x control registers */ + USB_REG_OFFSET_PWRCLKCTL = 0x0E00U, /*!< power and clock register */ +}; + +typedef struct +{ + __IO uint32_t GOTGCS; /*!< USB global OTG control and status register 000h */ + __IO uint32_t GOTGINTF; /*!< USB global OTG interrupt flag register 004h */ + __IO uint32_t GAHBCS; /*!< USB global AHB control and status register 008h */ + __IO uint32_t GUSBCS; /*!< USB global USB control and status register 00Ch */ + __IO uint32_t GRSTCTL; /*!< USB global reset control register 010h */ + __IO uint32_t GINTF; /*!< USB global interrupt flag register 014h */ + __IO uint32_t GINTEN; /*!< USB global interrupt enable register 018h */ + __IO uint32_t GRSTATR; /*!< USB receive status debug read register 01Ch */ + __IO uint32_t GRSTATP; /*!< USB receive status and pop register 020h */ + __IO uint32_t GRFLEN; /*!< USB global receive FIFO length register 024h */ + __IO uint32_t DIEP0TFLEN_HNPTFLEN; /*!< USB device IN endpoint 0/host non-periodic transmit FIFO length register 028h */ + __IO uint32_t HNPTFQSTAT; /*!< USB host non-periodic FIFO/queue status register 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< USB global core configuration register 038h */ + __IO uint32_t CID; /*!< USB core ID register 03Ch */ + uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */ + __IO uint32_t HPTFLEN; /*!< USB host periodic transmit FIFO length register 100h */ + __IO uint32_t DIEPTFLEN[15]; /*!< USB device IN endpoint transmit FIFO length register 104h */ +} usb_gr; + + +typedef struct +{ + __IO uint32_t HCTL; /*!< USB host control register 400h */ + __IO uint32_t HFT; /*!< USB host frame interval register 404h */ + __IO uint32_t HFINFR; /*!< USB host frame information remaining register 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTFQSTAT; /*!< USB host periodic transmit FIFO/queue status register 410h */ + __IO uint32_t HACHINT; /*!< USB host all channels interrupt register 414h */ + __IO uint32_t HACHINTEN; /*!< USB host all channels interrupt enable register 418h */ +} usb_hr; + +typedef struct +{ + __IO uint32_t HCHCTL; /*!< USB host channel control register 500h */ + __IO uint32_t HCHSTCTL; /*!< Reserved 504h */ + __IO uint32_t HCHINTF; /*!< USB host channel interrupt flag register 508h */ + __IO uint32_t HCHINTEN; /*!< USB host channel interrupt enable register 50Ch */ + __IO uint32_t HCHLEN; /*!< USB host channel transfer length register 510h */ + __IO uint32_t HCHDMAADDR; /*!< USB host channel-x DMA address register 514h*/ + uint32_t Reserved[2]; +} usb_pr; + +typedef struct +{ + __IO uint32_t DCFG; /*!< USB device configuration register 800h */ + __IO uint32_t DCTL; /*!< USB device control register 804h */ + __IO uint32_t DSTAT; /*!< USB device status register 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPINTEN; /*!< USB device IN endpoint common interrupt enable register 810h */ + __IO uint32_t DOEPINTEN; /*!< USB device OUT endpoint common interrupt enable register 814h */ + __IO uint32_t DAEPINT; /*!< USB device all endpoints interrupt register 818h */ + __IO uint32_t DAEPINTEN; /*!< USB device all endpoints interrupt enable register 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved24; /*!< Reserved 824h */ + __IO uint32_t DVBUSDT; /*!< USB device VBUS discharge time register 828h */ + __IO uint32_t DVBUSPT; /*!< USB device VBUS pulsing time register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev thr 830h */ + __IO uint32_t DIEPFEINTEN; /*!< USB Device IN endpoint FIFO empty interrupt enable register 834h */ + __IO uint32_t DEP1INT; /*!< USB device endpoint 1 interrupt register 838h */ + __IO uint32_t DEP1INTEN; /*!< USB device endpoint 1 interrupt enable register 83Ch */ + uint32_t Reserved40; /*!< Reserved 840h */ + __IO uint32_t DIEP1INTEN; /*!< USB device IN endpoint-1 interrupt enable register 844h */ + uint32_t Reserved48[15]; /*!< Reserved 848-880h */ + __IO uint32_t DOEP1INTEN; /*!< USB device OUT endpoint-1 interrupt enable register 884h */ +} usb_dr; + +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< USB device IN endpoint control register 900h + (EpNum * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (EpNum * 20h) + 04h */ + __IO uint32_t DIEPINTF; /*!< USB device IN endpoint interrupt flag register 900h + (EpNum * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (EpNum * 20h) + 0Ch */ + __IO uint32_t DIEPLEN; /*!< USB device IN endpoint transfer length register 900h + (EpNum * 20h) + 10h */ + __IO uint32_t DIEPDMAADDR; /*!< Device IN endpoint-x DMA address register 900h + (EpNum * 20h) + 14h */ + __IO uint32_t DIEPTFSTAT; /*!< USB device IN endpoint transmit FIFO status register 900h + (EpNum * 20h) + 18h */ +} usb_erin; + +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< USB device IN endpoint control register B00h + (EpNum * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (EpNum * 20h) + 04h */ + __IO uint32_t DOEPINTF; /*!< USB device IN endpoint interrupt flag register B00h + (EpNum * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (EpNum * 20h) + 0Ch */ + __IO uint32_t DOEPLEN; /*!< USB device IN endpoint transfer length register B00h + (EpNum * 20h) + 10h */ + __IO uint32_t DOEPDMAADDR; /*!< Device OUT endpoint-x DMA address register B00h + (EpNum * 20h) + 0Ch */ +} usb_erout; + +typedef struct _usb_regs +{ + usb_gr *gr; /*!< USBFS global registers */ + usb_dr *dr; /*!< Device control and status registers */ + usb_hr *hr; /*!< Host control and status registers */ + usb_erin *er_in[6]; /*!< USB device IN endpoint register */ + usb_erout *er_out[6]; /*!< USB device OUT endpoint register */ + usb_pr *pr[15]; /*!< USB Host channel-x control register */ + + __IO uint32_t *HPCS; /*!< USB host port control and status register */ + __IO uint32_t *DFIFO[USBFS_MAX_TX_FIFOS]; + __IO uint32_t *PWRCLKCTL; /*!< USB power and clock control register */ +} usb_core_regs; + +/* global OTG control and status register bits definitions */ +#define GOTGCS_BSV BIT(19) /*!< B-Session Valid */ +#define GOTGCS_ASV BIT(18) /*!< A-session valid */ +#define GOTGCS_DI BIT(17) /*!< debounce interval */ +#define GOTGCS_CIDPS BIT(16) /*!< id pin status */ +#define GOTGCS_DHNPEN BIT(11) /*!< device HNP enable */ +#define GOTGCS_HHNPEN BIT(10) /*!< host HNP enable */ +#define GOTGCS_HNPREQ BIT(9) /*!< HNP request */ +#define GOTGCS_HNPS BIT(8) /*!< HNP successes */ +#define GOTGCS_SRPREQ BIT(1) /*!< SRP request */ +#define GOTGCS_SRPS BIT(0) /*!< SRP successes */ + +/* global OTG interrupt flag register bits definitions */ +#define GOTGINTF_DF BIT(19) /*!< debounce finish */ +#define GOTGINTF_ADTO BIT(18) /*!< A-device timeout */ +#define GOTGINTF_HNPDET BIT(17) /*!< host negotiation request detected */ +#define GOTGINTF_HNPEND BIT(9) /*!< HNP end */ +#define GOTGINTF_SRPEND BIT(8) /*!< SRP end */ +#define GOTGINTF_SESEND BIT(2) /*!< session end */ + +/* global AHB control and status register bits definitions */ +#define GAHBCS_PTXFTH BIT(8) /*!< periodic Tx FIFO threshold */ +#define GAHBCS_TXFTH BIT(7) /*!< tx FIFO threshold */ +#define GAHBCS_DMAEN BIT(5) /*!< DMA function Enable */ +#define GAHBCS_BURST BITS(1, 4) /*!< the AHB burst type used by DMA */ +#define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */ + +/* global USB control and status register bits definitions */ +#define GUSBCS_FDM BIT(30) /*!< force device mode */ +#define GUSBCS_FHM BIT(29) /*!< force host mode */ +#define GUSBCS_ULPIEOI BIT(21) /*!< ULPI external over-current indicator */ +#define GUSBCS_ULPIEVD BIT(20) /*!< ULPI external VBUS driver */ +#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ +#define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ +#define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ +#define GUSBCS_EMBPHY BIT(6) /*!< embedded PHY selected */ +#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ + +/* global reset control register bits definitions */ +#define GRSTCTL_DMAIDL BIT(31) /*!< DMA idle state */ +#define GRSTCTL_DMABSY BIT(30) /*!< DMA busy */ +#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx FIFO number */ +#define GRSTCTL_TXFF BIT(5) /*!< tx FIFO flush */ +#define GRSTCTL_RXFF BIT(4) /*!< rx FIFO flush */ +#define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */ +#define GRSTCTL_HCSRST BIT(1) /*!< HCLK soft reset */ +#define GRSTCTL_CSRST BIT(0) /*!< core soft reset */ + +/* global interrupt flag register bits definitions */ +#define GINTF_WKUPIF BIT(31) /*!< wakeup interrupt flag */ +#define GINTF_SESIF BIT(30) /*!< session interrupt flag */ +#define GINTF_DISCIF BIT(29) /*!< disconnect interrupt flag */ +#define GINTF_IDPSC BIT(28) /*!< id pin status change */ +#define GINTF_PTXFEIF BIT(26) /*!< periodic tx FIFO empty interrupt flag */ +#define GINTF_HCIF BIT(25) /*!< host channels interrupt flag */ +#define GINTF_HPIF BIT(24) /*!< host port interrupt flag */ +#define GINTF_PXNCIF BIT(21) /*!< periodic transfer not complete interrupt flag */ +#define GINTF_ISOONCIF BIT(21) /*!< isochronous OUT transfer not complete interrupt flag */ +#define GINTF_ISOINCIF BIT(20) /*!< isochronous IN transfer not complete interrupt flag */ +#define GINTF_OEPIF BIT(19) /*!< OUT endpoint interrupt flag */ +#define GINTF_IEPIF BIT(18) /*!< IN endpoint interrupt flag */ +#define GINTF_EOPFIF BIT(15) /*!< end of periodic frame interrupt flag */ +#define GINTF_ISOOPDIF BIT(14) /*!< isochronous OUT packet dropped interrupt flag */ +#define GINTF_ENUMFIF BIT(13) /*!< enumeration finished */ +#define GINTF_RST BIT(12) /*!< USB reset */ +#define GINTF_SP BIT(11) /*!< USB suspend */ +#define GINTF_ESP BIT(10) /*!< early suspend */ +#define GINTF_GONAK BIT(7) /*!< global OUT NAK effective */ +#define GINTF_GNPINAK BIT(6) /*!< global IN non-periodic NAK effective */ +#define GINTF_NPTXFEIF BIT(5) /*!< non-periodic tx FIFO empty interrupt flag */ +#define GINTF_RXFNEIF BIT(4) /*!< rx FIFO non-empty interrupt flag */ +#define GINTF_SOF BIT(3) /*!< start of frame */ +#define GINTF_OTGIF BIT(2) /*!< OTG interrupt flag */ +#define GINTF_MFIF BIT(1) /*!< mode fault interrupt flag */ +#define GINTF_COPM BIT(0) /*!< current operation mode */ + +/* global interrupt enable register bits definitions */ +#define GINTEN_WKUPIE BIT(31) /*!< wakeup interrupt enable */ +#define GINTEN_SESIE BIT(30) /*!< session interrupt enable */ +#define GINTEN_DISCIE BIT(29) /*!< disconnect interrupt enable */ +#define GINTEN_IDPSCIE BIT(28) /*!< id pin status change interrupt enable */ +#define GINTEN_PTXFEIE BIT(26) /*!< periodic tx FIFO empty interrupt enable */ +#define GINTEN_HCIE BIT(25) /*!< host channels interrupt enable */ +#define GINTEN_HPIE BIT(24) /*!< host port interrupt enable */ +#define GINTEN_IPXIE BIT(21) /*!< periodic transfer not complete interrupt enable */ +#define GINTEN_ISOONCIE BIT(21) /*!< isochronous OUT transfer not complete interrupt enable */ +#define GINTEN_ISOINCIE BIT(20) /*!< isochronous IN transfer not complete interrupt enable */ +#define GINTEN_OEPIE BIT(19) /*!< OUT endpoints interrupt enable */ +#define GINTEN_IEPIE BIT(18) /*!< IN endpoints interrupt enable */ +#define GINTEN_EOPFIE BIT(15) /*!< end of periodic frame interrupt enable */ +#define GINTEN_ISOOPDIE BIT(14) /*!< isochronous OUT packet dropped interrupt enable */ +#define GINTEN_ENUMFIE BIT(13) /*!< enumeration finish enable */ +#define GINTEN_RSTIE BIT(12) /*!< USB reset interrupt enable */ +#define GINTEN_SPIE BIT(11) /*!< USB suspend interrupt enable */ +#define GINTEN_ESPIE BIT(10) /*!< early suspend interrupt enable */ +#define GINTEN_GONAKIE BIT(7) /*!< global OUT NAK effective interrupt enable */ +#define GINTEN_GNPINAKIE BIT(6) /*!< global non-periodic IN NAK effective interrupt enable */ +#define GINTEN_NPTXFEIE BIT(5) /*!< non-periodic Tx FIFO empty interrupt enable */ +#define GINTEN_RXFNEIE BIT(4) /*!< receive FIFO non-empty interrupt enable */ +#define GINTEN_SOFIE BIT(3) /*!< start of frame interrupt enable */ +#define GINTEN_OTGIE BIT(2) /*!< OTG interrupt enable */ +#define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ + +/* global receive status read and pop register bits definitions */ +#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */ +#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */ +#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */ +#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */ +#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */ + +/* global receive FIFO length register bits definitions */ +#define GRFLEN_RXFD BITS(0, 15) /*!< rx FIFO depth */ + +/* host non-periodic transmit FIFO length register bits definitions */ +#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */ +#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */ + +/** + * @brief USB IN endpoint 0 transmit FIFO length register bits definitions + */ +#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ +#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ + +/* host non-periodic transmit FIFO/queue status register bits definitions */ +#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */ +#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic Tx request queue space */ +#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic Tx FIFO space */ +#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/ +#define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ +#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ +#define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + +/* global core configuration register bits definitions */ +#define GCCFG_VBUSIG BIT(21) /*!< vbus ignored */ +#define GCCFG_SOFOEN BIT(20) /*!< SOF output enable */ +#define GCCFG_VBUSBCEN BIT(19) /*!< the VBUS B-device comparer enable */ +#define GCCFG_VBUSACEN BIT(18) /*!< the VBUS A-device comparer enable */ +#define GCCFG_PWRON BIT(16) /*!< power on */ + +/* core ID register bits definitions */ +#define CID_CID BITS(0, 31) /*!< core ID */ + +/* host periodic transmit FIFO length register bits definitions */ +#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic Tx FIFO depth */ +#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic Tx RAM start address */ + +/* device IN endpoint transmit FIFO length register bits definitions */ +#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */ +#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ + +/* host control register bits definitions */ +#define HCTL_SPDFSLS BIT(2) /*!< speed limited to FS and LS */ +#define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ + +/* host frame interval register bits definitions */ +#define HFT_FRI BITS(0, 15) /*!< frame interval */ + +/* host frame information remaining register bits definitions */ +#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */ +#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */ + +/* host periodic transmit FIFO/queue status register bits definitions */ +#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic Tx request queue */ +#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic Tx request queue space */ +#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic Tx FIFO space */ +#define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */ +#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ +#define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ +#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ +#define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + + +#define TFQSTAT_TXFS BITS(0, 15) +#define TFQSTAT_CNUM BITS(27, 30) + +/* host all channels interrupt register bits definitions */ +#define HACHINT_HACHINT BITS(0, 11) /*!< host all channel interrupts */ + +/* host all channels interrupt enable register bits definitions */ +#define HACHINTEN_CINTEN BITS(0, 11) /*!< channel interrupt enable */ + +/* host port control and status register bits definitions */ +#define HPCS_PS BITS(17, 18) /*!< port speed */ +#define HPCS_PP BIT(12) /*!< port power */ +#define HPCS_PLST BITS(10, 11) /*!< port line status */ +#define HPCS_PRST BIT(8) /*!< port reset */ +#define HPCS_PSP BIT(7) /*!< port suspend */ +#define HPCS_PREM BIT(6) /*!< port resume */ +#define HPCS_PEDC BIT(3) /*!< port enable/disable change */ +#define HPCS_PE BIT(2) /*!< port enable */ +#define HPCS_PCD BIT(1) /*!< port connect detected */ +#define HPCS_PCST BIT(0) /*!< port connect status */ + +/* host channel-x control register bits definitions */ +#define HCHCTL_CEN BIT(31) /*!< channel enable */ +#define HCHCTL_CDIS BIT(30) /*!< channel disable */ +#define HCHCTL_ODDFRM BIT(29) /*!< odd frame */ +#define HCHCTL_DAR BITS(22, 28) /*!< device address */ +#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */ +#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define HCHCTL_LSD BIT(17) /*!< low-speed device */ +#define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */ +#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ +#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ + +/* host channel-x split transaction register bits definitions */ +#define HCHSTCTL_SPLEN BIT(31) /*!< enable high-speed split transaction */ +#define HCHSTCTL_CSPLT BIT(16) /*!< complete-split enable */ +#define HCHSTCTL_ISOPCE BITS(14, 15) /*!< isochronous OUT payload continuation encoding */ +#define HCHSTCTL_HADDR BITS(7, 13) /*!< HUB address */ +#define HCHSTCTL_PADDR BITS(0, 6) /*!< port address */ + +/* host channel-x interrupt flag register bits definitions */ +#define HCHINTF_DTER BIT(10) /*!< data toggle error */ +#define HCHINTF_REQOVR BIT(9) /*!< request queue overrun */ +#define HCHINTF_BBER BIT(8) /*!< babble error */ +#define HCHINTF_USBER BIT(7) /*!< USB bus Error */ +#define HCHINTF_NYET BIT(6) /*!< NYET */ +#define HCHINTF_ACK BIT(5) /*!< ACK */ +#define HCHINTF_NAK BIT(4) /*!< NAK */ +#define HCHINTF_STALL BIT(3) /*!< STALL */ +#define HCHINTF_DMAER BIT(2) /*!< DMA error */ +#define HCHINTF_CH BIT(1) /*!< channel halted */ +#define HCHINTF_TF BIT(0) /*!< transfer finished */ + +/* host channel-x interrupt enable register bits definitions */ +#define HCHINTEN_DTERIE BIT(10) /*!< data toggle error interrupt enable */ +#define HCHINTEN_REQOVRIE BIT(9) /*!< request queue overrun interrupt enable */ +#define HCHINTEN_BBERIE BIT(8) /*!< babble error interrupt enable */ +#define HCHINTEN_USBERIE BIT(7) /*!< USB bus error interrupt enable */ +#define HCHINTEN_NYETIE BIT(6) /*!< NYET interrupt enable */ +#define HCHINTEN_ACKIE BIT(5) /*!< ACK interrupt enable */ +#define HCHINTEN_NAKIE BIT(4) /*!< NAK interrupt enable */ +#define HCHINTEN_STALLIE BIT(3) /*!< STALL interrupt enable */ +#define HCHINTEN_DMAERIE BIT(2) /*!< DMA error interrupt enable */ +#define HCHINTEN_CHIE BIT(1) /*!< channel halted interrupt enable */ +#define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */ + +/* host channel-x transfer length register bits definitions */ +#define HCHLEN_PING BIT(31) /*!< PING token request */ +#define HCHLEN_DPID BITS(29, 30) /*!< data PID */ +#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ +#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ + +/* host channel-x DMA address register bits definitions */ +#define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ + + +#define PORT_SPEED(x) (((uint32_t)(x) << 17) & HPCS_PS) /*!< Port speed */ + +#define PORT_SPEED_HIGH PORT_SPEED(0) /*!< high speed */ +#define PORT_SPEED_FULL PORT_SPEED(1) /*!< full speed */ +#define PORT_SPEED_LOW PORT_SPEED(2) /*!< low speed */ + +#define PIPE_CTL_DAR(x) (((uint32_t)(x) << 22) & HCHCTL_DAR) /*!< device address */ +#define PIPE_CTL_EPTYPE(x) (((uint32_t)(x) << 18) & HCHCTL_EPTYPE) /*!< endpoint type */ +#define PIPE_CTL_EPNUM(x) (((uint32_t)(x) << 11) & HCHCTL_EPNUM) /*!< endpoint number */ +#define PIPE_CTL_EPDIR(x) (((uint32_t)(x) << 15) & HCHCTL_EPDIR) /*!< endpoint direction */ +#define PIPE_CTL_EPMPL(x) (((uint32_t)(x) << 0) & HCHCTL_MPL) /*!< maximum packet length */ +#define PIPE_CTL_LSD(x) (((uint32_t)(x) << 17) & HCHCTL_LSD) /*!< low-Speed device */ + +#define PIPE_XFER_PCNT(x) (((uint32_t)(x) << 19) & HCHLEN_PCNT) /*!< packet count */ +#define PIPE_XFER_DPID(x) (((uint32_t)(x) << 29) & HCHLEN_DPID) /*!< data PID */ + +#define PIPE_DPID_DATA0 PIPE_XFER_DPID(0) /*!< DATA0 */ +#define PIPE_DPID_DATA1 PIPE_XFER_DPID(2) /*!< DATA1 */ +#define PIPE_DPID_DATA2 PIPE_XFER_DPID(1) /*!< DATA2 */ +#define PIPE_DPID_SETUP PIPE_XFER_DPID(3) /*!< MDATA (non-control)/SETUP (control) */ + +extern const uint32_t PIPE_DPID[]; + +/* device configuration registers bits definitions */ +#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ +#define DCFG_DAR BITS(4, 10) /*!< device address */ +#define DCFG_NZLSOH BIT(2) /*!< non-zero-length status OUT handshake */ +#define DCFG_DS BITS(0, 1) /*!< device speed */ + +/* device control registers bits definitions */ +#define DCTL_POIF BIT(11) /*!< power-on initialization finished */ +#define DCTL_CGONAK BIT(10) /*!< clear global OUT NAK */ +#define DCTL_SGONAK BIT(9) /*!< set global OUT NAK */ +#define DCTL_CGINAK BIT(8) /*!< clear global IN NAK */ +#define DCTL_SGINAK BIT(7) /*!< set global IN NAK */ +#define DCTL_GONS BIT(3) /*!< global OUT NAK status */ +#define DCTL_GINS BIT(2) /*!< global IN NAK status */ +#define DCTL_SD BIT(1) /*!< soft disconnect */ +#define DCTL_RWKUP BIT(0) /*!< remote wakeup */ + +/* device status registers bits definitions */ +#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */ +#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */ +#define DSTAT_SPST BIT(0) /*!< suspend status */ + +/* device IN endpoint common interrupt enable registers bits definitions */ +#define DIEPINTEN_NAKEN BIT(13) /*!< NAK handshake sent by USBHS interrupt enable bit */ +#define DIEPINTEN_TXFEEN BIT(7) /*!< transmit FIFO empty interrupt enable bit */ +#define DIEPINTEN_IEPNEEN BIT(6) /*!< IN endpoint NAK effective interrupt enable bit */ +#define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint Tx FIFO underrun interrupt enable bit */ +#define DIEPINTEN_CITOEN BIT(3) /*!< control In Timeout interrupt enable bit */ +#define DIEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ +#define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ + +/* device OUT endpoint common interrupt enable registers bits definitions */ +#define DOEPINTEN_NYETEN BIT(14) /*!< NYET handshake is sent interrupt enable bit */ +#define DOEPINTEN_BTBSTPEN BIT(6) /*!< back-to-back SETUP packets interrupt enable bit */ +#define DOEPINTEN_EPRXFOVREN BIT(4) /*!< endpoint Rx FIFO overrun interrupt enable bit */ +#define DOEPINTEN_STPFEN BIT(3) /*!< SETUP phase finished interrupt enable bit */ +#define DOEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ +#define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ + +/* device all endpoints interrupt registers bits definitions */ +#define DAEPINT_OEPITB BITS(16, 21) /*!< device all OUT endpoint interrupt bits */ +#define DAEPINT_IEPITB BITS(0, 5) /*!< device all IN endpoint interrupt bits */ + +/* device all endpoints interrupt enable registers bits definitions */ +#define DAEPINTEN_OEPIE BITS(16, 21) /*!< OUT endpoint interrupt enable */ +#define DAEPINTEN_IEPIE BITS(0, 3) /*!< IN endpoint interrupt enable */ + +/* device Vbus discharge time registers bits definitions */ +#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */ + +/* device Vbus pulsing time registers bits definitions */ +#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ + +/* device IN endpoint FIFO empty interrupt enable register bits definitions */ +#define DIEPFEINTEN_IEPTXFEIE BITS(0, 5) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ + +/* device endpoint 0 control register bits definitions */ +#define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */ +#define DEP0CTL_EPD BIT(30) /*!< endpoint disable */ +#define DEP0CTL_SNAK BIT(27) /*!< set NAK */ +#define DEP0CTL_CNAK BIT(26) /*!< clear NAK */ +#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ +#define DEP0CTL_STALL BIT(21) /*!< STALL handshake */ +#define DOEP0CTL_SNOOP BIT(20) /*!< snoop mode */ +#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define DEP0CTL_NAKS BIT(17) /*!< NAK status */ +#define DEP0CTL_EPACT BIT(15) /*!< endpoint active */ +#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ + +/* device endpoint x control register bits definitions */ +#define DEPCTL_EPEN BIT(31) /*!< endpoint enable */ +#define DEPCTL_EPD BIT(30) /*!< endpoint disable */ +#define DEPCTL_SODDFRM BIT(29) /*!< set odd frame */ +#define DEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */ +#define DEPCTL_SEVNFRM BIT(28) /*!< set even frame */ +#define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ +#define DEPCTL_SNAK BIT(27) /*!< set NAK */ +#define DEPCTL_CNAK BIT(26) /*!< clear NAK */ +#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ +#define DEPCTL_STALL BIT(21) /*!< STALL handshake */ +#define DOEPCTL_SNOOP BIT(20) /*!< snoop mode */ +#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define DEPCTL_NAKS BIT(17) /*!< NAK status */ +#define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */ +#define DEPCTL_DPID BIT(16) /*!< endpoint data PID */ +#define DEPCTL_EPACT BIT(15) /*!< endpoint active */ +#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ + +/* device IN endpoint-x interrupt flag register bits definitions */ +#define DIEPINTF_NAK BIT(13) /*!< NAK handshake sent by USBHS */ +#define DIEPINTF_TXFE BIT(7) /*!< transmit FIFO empty */ +#define DIEPINTF_IEPNE BIT(6) /*!< IN endpoint NAK effective */ +#define DIEPINTF_EPTXFUD BIT(4) /*!< endpoint Tx FIFO underrun */ +#define DIEPINTF_CITO BIT(3) /*!< control In Timeout interrupt */ +#define DIEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ +#define DIEPINTF_TF BIT(0) /*!< transfer finished */ + +/* device OUT endpoint-x interrupt flag register bits definitions */ +#define DOEPINTF_NYET BIT(14) /*!< NYET handshake is sent */ +#define DOEPINTF_BTBSTP BIT(6) /*!< back-to-back SETUP packets */ +#define DOEPINTF_EPRXFOVR BIT(4) /*!< endpoint Rx FIFO overrun */ +#define DOEPINTF_STPF BIT(3) /*!< SETUP phase finished */ +#define DOEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ +#define DOEPINTF_TF BIT(0) /*!< transfer finished */ + +/* device IN endpoint 0 transfer length register bits definitions */ +#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */ +#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ + +/* device OUT endpoint 0 transfer length register bits definitions */ +#define DOEP0LEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ +#define DOEP0LEN_PCNT BIT(19) /*!< packet count */ +#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ + +/* device OUT endpoint-x transfer length register bits definitions */ +#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ +#define DOEPLEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ +#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */ +#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */ +#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */ + +/* device IN endpoint-x DMA address register bits definitions */ +#define DIEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ + +/* device OUT endpoint-x DMA address register bits definitions */ +#define DOEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ + +/* device IN endpoint-x transmit FIFO status register bits definitions */ +#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< IN endpoint Tx FIFO space remaining */ + +/* USB power and clock registers bits definition */ +#define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */ +#define PWRCLKCTL_SUCLK BIT(0) /*!< stop the USB clock */ + +#define RSTAT_GOUT_NAK 1U /* global OUT NAK (triggers an interrupt) */ +#define RSTAT_DATA_UPDT 2U /* OUT data packet received */ +#define RSTAT_XFER_COMP 3U /* OUT transfer completed (triggers an interrupt) */ +#define RSTAT_SETUP_COMP 4U /* SETUP transaction completed (triggers an interrupt) */ +#define RSTAT_SETUP_UPDT 6U /* SETUP data packet received */ + +#define DSTAT_EM_HS_PHY_30MHZ_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */ +#define DSTAT_EM_FS_PHY_30MHZ_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */ +#define DSTAT_EM_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */ +#define DSTAT_EM_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */ + +#define DPID_DATA0 0U /* device endpoint data PID is DATA0 */ +#define DPID_DATA1 2U /* device endpoint data PID is DATA1 */ +#define DPID_DATA2 1U /* device endpoint data PID is DATA2 */ +#define DPID_MDATA 3U /* device endpoint data PID is MDATA */ + +#define GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1U)) /*!< AHB burst type used by DMA*/ + +#define DMA_INCR0 GAHBCS_DMAINCR(0U) /*!< single burst type used by DMA*/ +#define DMA_INCR1 GAHBCS_DMAINCR(1U) /*!< 4-beat incrementing burst type used by DMA*/ +#define DMA_INCR4 GAHBCS_DMAINCR(3U) /*!< 8-beat incrementing burst type used by DMA*/ +#define DMA_INCR8 GAHBCS_DMAINCR(5U) /*!< 16-beat incrementing burst type used by DMA*/ +#define DMA_INCR16 GAHBCS_DMAINCR(7U) /*!< 32-beat incrementing burst type used by DMA*/ + +#define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11U)) /*!< end of periodic frame time configuration */ + +#define FRAME_INTERVAL_80 DCFG_PFRI(0U) /*!< 80% of the frame time */ +#define FRAME_INTERVAL_85 DCFG_PFRI(1U) /*!< 85% of the frame time */ +#define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */ +#define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */ + +#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0U)) /*!< device speed configuration */ + +#define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U) /*!< device external PHY high speed */ +#define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U) /*!< device external PHY full speed */ +#define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U) /*!< device internal PHY full speed */ + +#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0U)) /*!< maximum packet length configuration */ + +#define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */ +#define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */ +#define EP0MPL_16 DEP0_MPL(2U) /*!< maximum packet length 16 bytes */ +#define EP0MPL_8 DEP0_MPL(3U) /*!< maximum packet length 8 bytes */ + +#define DOEP0_TLEN(regval) (DOEP0LEN_TLEN & ((regval) << 0)) /*!< Transfer length */ +#define DOEP0_PCNT(regval) (DOEP0LEN_PCNT & ((regval) << 19)) /*!< Packet count */ +#define DOEP0_STPCNT(regval) (DOEP0LEN_STPCNT & ((regval) << 29)) /*!< SETUP packet count */ + +#define USB_ULPI_PHY 1 /*!< ULPI interface external PHY */ +#define USB_EMBEDDED_PHY 2 /*!< Embedded PHY */ + +#define GRXSTS_PKTSTS_IN 2 +#define GRXSTS_PKTSTS_IN_XFER_COMP 3 +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5 +#define GRXSTS_PKTSTS_CH_HALTED 7 + +#define DEVICE_MODE 0 /*!< device mode */ +#define HOST_MODE 1 /*!< host mode */ +#define OTG_MODE 2 /*!< OTG mode */ + +#define HCTL_30_60MHZ 0 /*!< USB clock 30-60MHZ */ +#define HCTL_48MHZ 1 /*!< USB clock 48MHZ */ +#define HCTL_6MHZ 2 /*!< USB clock 6MHZ */ + +enum USB_SPEED { + USB_SPEED_UNKNOWN = 0, /*!< USB speed unknown */ + USB_SPEED_LOW, /*!< USB speed low */ + USB_SPEED_FULL, /*!< USB speed full */ + USB_SPEED_HIGH /*!< USB speed high */ +}; + +#define EP0_OUT ((uint8_t)0x00) /*!< endpoint out 0 */ +#define EP0_IN ((uint8_t)0x80) /*!< endpoint in 0 */ +#define EP1_OUT ((uint8_t)0x01) /*!< endpoint out 1 */ +#define EP1_IN ((uint8_t)0x81) /*!< endpoint in 1 */ +#define EP2_OUT ((uint8_t)0x02) /*!< endpoint out 2 */ +#define EP2_IN ((uint8_t)0x82) /*!< endpoint in 2 */ +#define EP3_OUT ((uint8_t)0x03) /*!< endpoint out 3 */ +#define EP3_IN ((uint8_t)0x83) /*!< endpoint in 3 */ + +#endif /* __DRV_USB_REGS_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usbd_int.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usbd_int.h new file mode 100644 index 0000000..594b3ba --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usbd_int.h @@ -0,0 +1,52 @@ +/*! + \file drv_usbd_int.h + \brief USB device mode interrupt header file + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USBD_INT_H +#define __DRV_USBD_INT_H + +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +/* USB device-mode interrupts global service routine handler */ +void usbd_isr (usb_core_driver *udev); + +#ifdef USB_HS_DEDICATED_EP1_ENABLED + +uint32_t USBD_OTG_EP1IN_ISR_Handler (usb_core_driver *udev); +uint32_t USBD_OTG_EP1OUT_ISR_Handler (usb_core_driver *udev); + +#endif + +#endif /* __DRV_USBD_INT_H */ + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usbh_int.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usbh_int.h new file mode 100644 index 0000000..5af6e9c --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/drv_usbh_int.h @@ -0,0 +1,49 @@ +/*! + \file drv_usbh_int.h.h + \brief USB host mode interrupt management header file + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USBH_INT_H +#define __DRV_USBH_INT_H + +#include "drv_usb_host.h" + +typedef struct _usbh_int_cb +{ + uint8_t (*SOF) (usb_core_driver *pudev); +} usbh_int_cb; + +extern usbh_int_cb *usbh_int_fop; + +uint32_t usbh_isr (usb_core_driver *pudev); + +#endif /* __DRV_USBH_INT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usb_ch9_std.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usb_ch9_std.h new file mode 100644 index 0000000..834e751 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usb_ch9_std.h @@ -0,0 +1,237 @@ +/*! + \file usb_ch9_std.h + \brief USB 2.0 standard defines + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_CH9_STD_H +#define __USB_CH9_STD_H + +#include "usb_conf.h" + +#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /*!< USB device qualifier descriptor length */ +#define USB_DEV_DESC_LEN 0x12U /*!< USB device descriptor length */ +#define USB_CFG_DESC_LEN 0x09U /*!< USB configuration descriptor length */ +#define USB_ITF_DESC_LEN 0x09U /*!< USB interface descriptor length */ +#define USB_EP_DESC_LEN 0x07U /*!< USB endpoint descriptor length */ +#define USB_OTG_DESC_LEN 0x03U /*!< USB device OTG descriptor length */ + +#define USB_SETUP_PACKET_LEN 0x08U /*!< USB setup packet length */ + +/* bit 7 of bmRequestType: data phase transfer direction */ +#define USB_TRX_MASK 0x80U /*!< USB transfer direction mask */ +#define USB_TRX_OUT 0x00U /*!< USB transfer OUT direction */ +#define USB_TRX_IN 0x80U /*!< USB transfer IN direction */ + +/* bit 6..5 of bmRequestType: request type */ +#define USB_REQTYPE_STRD 0x00U /*!< USB standard request */ +#define USB_REQTYPE_CLASS 0x20U /*!< USB class request */ +#define USB_REQTYPE_VENDOR 0x40U /*!< USB vendor request */ +#define USB_REQTYPE_MASK 0x60U /*!< USB request mask */ + +#define USBD_BUS_POWERED 0x00U /*!< USB bus power supply */ +#define USBD_SELF_POWERED 0x01U /*!< USB self power supply */ + +#define USB_STATUS_REMOTE_WAKEUP 2U /*!< USB is in remote wakeup status */ +#define USB_STATUS_SELF_POWERED 1U /*!< USB is in self powered status */ + +/* bit 4..0 of bmRequestType: recipient type */ +enum _usb_recp_type { + USB_RECPTYPE_DEV = 0x0U, /*!< USB device request type */ + USB_RECPTYPE_ITF = 0x1U, /*!< USB interface request type */ + USB_RECPTYPE_EP = 0x2U, /*!< USB endpoint request type */ + USB_RECPTYPE_MASK = 0x3U /*!< USB request type mask */ +}; + +/* bRequest value */ +enum _usb_request { + USB_GET_STATUS = 0x0U, /*!< USB get status request */ + USB_CLEAR_FEATURE = 0x1U, /*!< USB clear feature request */ + USB_RESERVED2 = 0x2U, + USB_SET_FEATURE = 0x3U, /*!< USB set feature request */ + USB_RESERVED4 = 0x4U, + USB_SET_ADDRESS = 0x5U, /*!< USB set address request */ + USB_GET_DESCRIPTOR = 0x6U, /*!< USB get descriptor request */ + USB_SET_DESCRIPTOR = 0x7U, /*!< USB set descriptor request */ + USB_GET_CONFIGURATION = 0x8U, /*!< USB get configuration request */ + USB_SET_CONFIGURATION = 0x9U, /*!< USB set configuration request */ + USB_GET_INTERFACE = 0xAU, /*!< USB get interface request */ + USB_SET_INTERFACE = 0xBU, /*!< USB set interface request */ + USB_SYNCH_FRAME = 0xCU /*!< USB synchronize frame request */ +}; + +/* descriptor types of USB specifications */ +enum _usb_desctype { + USB_DESCTYPE_DEV = 0x1U, /*!< USB device descriptor type */ + USB_DESCTYPE_CONFIG = 0x2U, /*!< USB configuration descriptor type */ + USB_DESCTYPE_STR = 0x3U, /*!< USB string descriptor type */ + USB_DESCTYPE_ITF = 0x4U, /*!< USB interface descriptor type */ + USB_DESCTYPE_EP = 0x5U, /*!< USB endpoint descriptor type */ + USB_DESCTYPE_DEV_QUALIFIER = 0x6U, /*!< USB device qualtfier descriptor type */ + USB_DESCTYPE_OTHER_SPD_CONFIG = 0x7U, /*!< USB other speed configuration descriptor type */ + USB_DESCTYPE_ITF_POWER = 0x8U, /*!< USB interface power descriptor type */ + USB_DESCTYPE_BOS = 0xFU /*!< USB BOS descriptor type */ +}; + +/* USB Endpoint Descriptor bmAttributes bit definitions */ +/* bits 1..0 : transfer type */ +enum _usbx_type { + USB_EP_ATTR_CTL = 0x0U, /*!< USB control transfer type */ + USB_EP_ATTR_ISO = 0x1U, /*!< USB Isochronous transfer type */ + USB_EP_ATTR_BULK = 0x2U, /*!< USB Bulk transfer type */ + USB_EP_ATTR_INT = 0x3U /*!< USB Interrupt transfer type */ +}; + +/* bits 3..2 : Sync type (only if ISOCHRONOUS) */ +#define USB_EP_ATTR_NOSYNC 0x00 /* No Synchronization */ +#define USB_EP_ATTR_ASYNC 0x04 /* Asynchronous */ +#define USB_EP_ATTR_ADAPTIVE 0x08 /* Adaptive */ +#define USB_EP_ATTR_SYNC 0x0C /* Synchronous */ +#define USB_EP_ATTR_SYNCTYPE 0x0C /* Synchronous type */ + +/* bits 5..4 : usage type (only if ISOCHRONOUS) */ +#define USB_EP_ATTR_DATA 0x00 /* Data endpoint */ +#define USB_EP_ATTR_FEEDBACK 0x10 /* Feedback endpoint */ +#define USB_EP_ATTR_IMPLICIT_FEEDBACK_DATA 0x20 /* Implicit feedback Data endpoint */ +#define USB_EP_ATTR_USAGETYPE 0x30 /* Usage type */ + +#define FEATURE_SELECTOR_EP 0x00 /* USB endpoint feature selector */ +#define FEATURE_SELECTOR_DEV 0x01 /* USB device feature selector */ + +#define BYTE_SWAP(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ + (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) + +#define BYTE_LOW(x) ((uint8_t)((x) & 0x00FFU)) +#define BYTE_HIGH(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) + +#define USB_MIN(a, b) (((a) < (b)) ? (a) : (b)) + +#define USB_DEFAULT_CONFIG 0U + +/* USB classes */ +#define USB_CLASS_HID 0x03U /*!< USB HID class */ +#define USB_CLASS_MSC 0x08U /*!< USB MSC class */ + +/* use the following values when USB host need to get descriptor */ +#define USBH_DESC(x) (((x)<< 8U) & 0xFF00U) + +/* as per usb specs 9.2.6.4 :standard request with data request timeout: 5sec + standard request with no data stage timeout : 50ms */ +#define DATA_STAGE_TIMEOUT 5000U /*!< USB data stage timeout*/ +#define NODATA_STAGE_TIMEOUT 50U /*!< USB no data stage timeout*/ + +#pragma pack(1) + +/* USB standard device request structure */ +typedef struct _usb_req { + uint8_t bmRequestType; /*!< type of request */ + uint8_t bRequest; /*!< request of setup packet */ + uint16_t wValue; /*!< value of setup packet */ + uint16_t wIndex; /*!< index of setup packet */ + uint16_t wLength; /*!< length of setup packet */ +} usb_req; + +/* USB setup packet define */ +typedef union _usb_setup { + uint8_t data[8]; + + usb_req req; +} usb_setup; + +/* USB descriptor defines */ + +typedef struct _usb_desc_header { + uint8_t bLength; /*!< size of the descriptor */ + uint8_t bDescriptorType; /*!< type of the descriptor */ +} usb_desc_header; + +typedef struct _usb_desc_dev { + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint16_t bcdUSB; /*!< BCD of the supported USB specification */ + uint8_t bDeviceClass; /*!< USB device class */ + uint8_t bDeviceSubClass; /*!< USB device subclass */ + uint8_t bDeviceProtocol; /*!< USB device protocol */ + uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */ + uint16_t idVendor; /*!< vendor ID for the USB product */ + uint16_t idProduct; /*!< unique product ID for the USB product */ + uint16_t bcdDevice; /*!< product release (version) number */ + uint8_t iManufacturer; /*!< string index for the manufacturer's name */ + uint8_t iProduct; /*!< string index for the product name/details */ + uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */ + uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */ +} usb_desc_dev; + +typedef struct _usb_desc_config { + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */ + uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */ + uint8_t bConfigurationValue; /*!< configuration index of the current configuration */ + uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */ + uint8_t bmAttributes; /*!< configuration attributes */ + uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */ +} usb_desc_config; + +typedef struct _usb_desc_itf { + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */ + uint8_t bAlternateSetting; /*!< alternate setting for the interface number */ + uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */ + uint8_t bInterfaceClass; /*!< interface class ID */ + uint8_t bInterfaceSubClass; /*!< interface subclass ID */ + uint8_t bInterfaceProtocol; /*!< interface protocol ID */ + uint8_t iInterface; /*!< index of the string descriptor describing the interface */ +} usb_desc_itf; + +typedef struct _usb_desc_ep { + usb_desc_header header; /*!< descriptor header, including type and size. */ + + uint8_t bEndpointAddress; /*!< logical address of the endpoint */ + uint8_t bmAttributes; /*!< endpoint attributes */ + uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */ + + uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */ +#ifdef AUDIO_ENDPOINT + uint8_t bRefresh; /*!< reset to 0 */ + uint8_t bSynchAddress; /*!< reset to 0 */ +#endif +} usb_desc_ep; + +typedef struct _usb_desc_LANGID { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint16_t wLANGID; /*!< LANGID code */ +} usb_desc_LANGID; + +#pragma pack() + +#endif /* __USB_CH9_STD_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbd_core.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbd_core.h new file mode 100644 index 0000000..c4ec47a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbd_core.h @@ -0,0 +1,95 @@ +/*! + \file usbd_core.h + \brief USB device mode core functions protype + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_CORE_H +#define __USBD_CORE_H + + +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +typedef enum +{ + USBD_OK = 0, /*!< status OK */ + USBD_BUSY, /*!< status busy */ + USBD_FAIL, /*!< status fail */ +} usbd_status; + +enum _usbd_status { + USBD_DEFAULT = 1, /*!< default status */ + USBD_ADDRESSED = 2, /*!< address send status */ + USBD_CONFIGURED = 3, /*!< configured status */ + USBD_SUSPENDED = 4 /*!< suspended status */ +}; + +/* function declarations */ + +/* device connect */ +void usbd_connect (usb_core_driver *udev); + +/* device disconnect */ +void usbd_disconnect (usb_core_driver *udev); + +/* set USB device address */ +void usbd_addr_set (usb_core_driver *udev, uint8_t addr); + +/* initailizes the USB device-mode stack and load the class driver */ +void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_class_core *class_core); + +/* endpoint initialization */ +uint32_t usbd_ep_setup (usb_core_driver *udev, const usb_desc_ep *ep_desc); + +/* configure the endpoint when it is disabled */ +uint32_t usbd_ep_clear (usb_core_driver *udev, uint8_t ep_addr); + +/* endpoint prepare to receive data */ +uint32_t usbd_ep_recev (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len); + +/* endpoint prepare to transmit data */ +uint32_t usbd_ep_send (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len); + +/* set an endpoint to STALL status */ +uint32_t usbd_ep_stall (usb_core_driver *udev, uint8_t ep_addr); + +/* clear endpoint STALLed status */ +uint32_t usbd_ep_stall_clear (usb_core_driver *udev, uint8_t ep_addr); + +/* flush the endpoint FIFOs */ +uint32_t usbd_fifo_flush (usb_core_driver *udev, uint8_t ep_addr); + +/* get the received data length */ +uint16_t usbd_rxcount_get (usb_core_driver *udev, uint8_t ep_num); + +#endif /* __USBD_CORE_H */ + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbd_enum.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbd_enum.h new file mode 100644 index 0000000..676b961 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbd_enum.h @@ -0,0 +1,114 @@ +/*! + \file usbd_enum.h + \brief USB enumeration definitions + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_ENUM_H +#define __USBD_ENUM_H + +#include "usbd_core.h" +#include "usbd_conf.h" +#include + +#ifndef NULL + #define NULL 0U +#endif + +typedef enum _usb_reqsta { + REQ_SUPP = 0x0U, /* request support */ + REQ_NOTSUPP = 0x1U /* request not support */ +} usb_reqsta; + +/* string descriptor index */ +enum _str_index +{ + STR_IDX_LANGID = 0x0U, /* language ID string index */ + STR_IDX_MFC = 0x1U, /* manufacturer string index */ + STR_IDX_PRODUCT = 0x2U, /* product string index */ + STR_IDX_SERIAL = 0x3U, /* serial string index */ + STR_IDX_CONFIG = 0x4U, /* configuration string index */ + STR_IDX_ITF = 0x5U, /* interface string index */ + STR_IDX_MAX = 0x6U /* string maximum index */ +}; + +typedef enum _usb_pwrsta { + USB_PWRSTA_SELF_POWERED = 0x1U, /* USB is in self powered status */ + USB_PWRSTA_REMOTE_WAKEUP = 0x2U, /* USB is in remote wakeup status */ +} usb_pwrsta; + +typedef enum _usb_feature +{ + USB_FEATURE_EP_HALT = 0x0U, /* USB has endpoint halt feature */ + USB_FEATURE_REMOTE_WAKEUP = 0x1U, /* USB has endpoint remote wakeup feature */ + USB_FEATURE_TEST_MODE = 0x2U /* USB has endpoint test mode feature */ +} usb_feature; + +#define ENG_LANGID 0x0409U /* english language ID */ +#define CHN_LANGID 0x0804U /* chinese language ID */ + +/* USB device exported macros */ +#define CTL_EP(ep) (((ep) == 0x00U) || ((ep) == 0x80U)) + +#define WIDE_STRING(string) _WIDE_STRING(string) +#define _WIDE_STRING(string) L##string + +#define USBD_STRING_DESC(string) \ + (void *)&(const struct { \ + uint8_t _len; \ + uint8_t _type; \ + wchar_t _data[sizeof(string)]; \ + }) { \ + sizeof(WIDE_STRING(string)) + 2U - 2U, \ + USB_DESCTYPE_STR, \ + WIDE_STRING(string) \ + } + +/* function declarations */ + +/* handle USB standard device request */ +usb_reqsta usbd_standard_request (usb_core_driver *udev, usb_req *req); + +/* handle USB device class request */ +usb_reqsta usbd_class_request (usb_core_driver *udev, usb_req *req); + +/* handle USB vendor request */ +usb_reqsta usbd_vendor_request (usb_core_driver *udev, usb_req *req); + +/* handle USB enumeration error */ +void usbd_enum_error (usb_core_driver *udev, usb_req *req); + +/* convert hex 32bits value into unicode char */ +void int_to_unicode (uint32_t value, uint8_t *pbuf, uint8_t len); + +#endif /* __USBD_ENUM_H */ + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbd_transc.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbd_transc.h new file mode 100644 index 0000000..d5cccbd --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbd_transc.h @@ -0,0 +1,64 @@ +/*! + \file usbd_transc.h + \brief USB transaction core functions prototype + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_TRANSC_H +#define __USBD_TRANSC_H + +#include "usbd_core.h" + +/* function declarations */ + +/* USB send data in the control transaction */ +usbd_status usbd_ctl_send (usb_core_driver *udev); + +/* USB receive data in control transaction */ +usbd_status usbd_ctl_recev (usb_core_driver *udev); + +/* USB send control transaction status */ +usbd_status usbd_ctl_status_send (usb_core_driver *udev); + +/* USB control receive status */ +usbd_status usbd_ctl_status_recev (usb_core_driver *udev); + +/* USB setup stage processing */ +uint8_t usbd_setup_transc (usb_core_driver *udev); + +/* data out stage processing */ +uint8_t usbd_out_transc (usb_core_driver *udev, uint8_t ep_num)__attribute__((optimize("O0"))); + +/* data in stage processing */ +uint8_t usbd_in_transc (usb_core_driver *udev, uint8_t ep_num)__attribute__((optimize("O0"))); + +#endif /* __USBD_TRANSC_H */ + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbh_core.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbh_core.h new file mode 100644 index 0000000..6ea1344 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbh_core.h @@ -0,0 +1,219 @@ +/*! + \file usbh_core.h + \brief USB host core state machine header file + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_CORE_H +#define __USBH_CORE_H + +#include "usbh_conf.h" +#include "drv_usb_host.h" + +#define MSC_CLASS 0x08U +#define HID_CLASS 0x03U +#define MSC_PROTOCOL 0x50U +#define CBI_PROTOCOL 0x01U + +#define USBH_MAX_ERROR_COUNT 3U + +#define USBH_DEV_ADDR_DEFAULT 0U +#define USBH_DEV_ADDR 1U + +typedef enum +{ + USBH_OK = 0U, + USBH_BUSY, + USBH_FAIL, + USBH_NOT_SUPPORTED, + USBH_UNRECOVERED_ERROR, + USBH_SPEED_UNKNOWN_ERROR, + USBH_APPLY_DEINIT +} usbh_status; + +/* USB host global operation state */ +typedef enum +{ + HOST_DEFAULT = 0U, + HOST_DETECT_DEV_SPEED, + HOST_DEV_ATTACHED, + HOST_DEV_DETACHED, + HOST_ENUM, + HOST_CLASS_ENUM, + HOST_CLASS_HANDLER, + HOST_USER_INPUT, + HOST_SUSPENDED, + HOST_ERROR +} usb_host_state; + +/* USB host enumeration state */ +typedef enum +{ + ENUM_DEFAULT = 0U, + ENUM_GET_DEV_DESC, + ENUM_SET_ADDR, + ENUM_GET_CFG_DESC, + ENUM_GET_CFG_DESC_SET, + ENUM_GET_STR_DESC, + ENUM_SET_CONFIGURATION, + ENUM_DEV_CONFIGURED +} usbh_enum_state; + +/* USB host control transfer state */ +typedef enum +{ + CTL_IDLE = 0U, + CTL_SETUP, + CTL_DATA_IN, + CTL_DATA_OUT, + CTL_STATUS_IN, + CTL_STATUS_OUT, + CTL_ERROR, + CTL_FINISH +} usbh_ctl_state; + +/* user action state */ +typedef enum +{ + USBH_USER_NO_RESP = 0U, + USBH_USER_RESP_OK = 1U, +} usbh_user_status; + +/* control transfer information */ +typedef struct _usbh_control +{ + uint8_t pipe_in_num; + uint8_t pipe_out_num; + uint8_t max_len; + uint8_t error_count; + + uint8_t *buf; + uint16_t ctl_len; + uint16_t timer; + + usb_setup setup; + usbh_ctl_state ctl_state; +} usbh_control; + +/* USB device property */ +typedef struct +{ + uint8_t addr; + uint32_t speed; + + usb_desc_dev dev_desc; + usb_desc_config cfg_desc; + usb_desc_itf itf_desc[USBH_MAX_INTERFACES_NUM]; + usb_desc_ep ep_desc[USBH_MAX_INTERFACES_NUM][USBH_MAX_EP_NUM]; +} usb_dev_prop; + +/** + * @brief Device class callbacks + */ +typedef struct +{ + usbh_status (*class_init) (usb_core_driver *pudev, void *phost); + void (*class_deinit) (usb_core_driver *pudev, void *phost); + usbh_status (*class_requests) (usb_core_driver *pudev, void *phost); + usbh_status (*class_machine) (usb_core_driver *pudev, void *phost); +} usbh_class_cb; + +/** + * @brief User callbacks + */ +typedef struct +{ + void (*dev_init) (void); + void (*dev_deinit) (void); + void (*dev_attach) (void); + void (*dev_reset) (void); + void (*dev_detach) (void); + void (*dev_over_currented) (void); + void (*dev_speed_detected) (uint32_t dev_speed); + void (*dev_devdesc_assigned) (void *dev_desc); + void (*dev_address_set) (void); + + void (*dev_cfgdesc_assigned) (usb_desc_config *cfg_desc, + usb_desc_itf *itf_desc, + usb_desc_ep *ep_desc); + + void (*dev_mfc_str) (void *mfc_str); + void (*dev_prod_str) (void *prod_str); + void (*dev_seral_str) (void *serial_str); + void (*dev_enumerated) (void); + usbh_user_status (*dev_user_input) (void); + int (*dev_user_app) (void); + void (*dev_not_supported) (void); + void (*dev_error) (void); +} usbh_user_cb; + +/** + * @brief Host information + */ +typedef struct +{ + usb_host_state cur_state; /*!< host state machine value */ + usb_host_state backup_state; /*!< backup of previous state machine value */ + usbh_enum_state enum_state; /*!< enumeration state machine */ + usbh_control control; /*!< USB host control state machine */ + usb_dev_prop dev_prop; /*!< USB device properity */ + + usbh_class_cb *class_cb; /*!< USB class callback */ + usbh_user_cb *usr_cb; /*!< USB user callback */ +} usbh_host; + + +/* USB host stack initializations */ +void usbh_init (usb_core_driver *pudev, usb_core_enum core, usbh_host *puhost); + +/* de-initialize USB host */ +usbh_status usbh_deinit (usb_core_driver *pudev, usbh_host *puhost); + +/* USB host core main state machine process */ +void usbh_core_task (usb_core_driver *pudev, usbh_host *puhost); + +/* handle the error on USB host side */ +void usbh_error_handler (usbh_host *puhost, usbh_status ErrType); + +/* get USB URB state */ +static inline usb_urb_state usbh_urbstate_get (usb_core_driver *pudev, uint8_t pp_num) +{ + return pudev->host.pipe[pp_num].urb_state; +} + +/* get USB transfer data count */ +static inline uint32_t usbh_xfercount_get (usb_core_driver *pudev, uint8_t pp_num) +{ + return pudev->host.backup_xfercount[pp_num]; +} + +#endif /* __USBH_CORE_H */ + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbh_enum.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbh_enum.h new file mode 100644 index 0000000..b82eae2 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbh_enum.h @@ -0,0 +1,78 @@ +/*! + \file usbh_enum.h + \brief USB host mode USB enumeration header file + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_ENUM_H +#define __USBH_ENUM_H + +#include "usb_conf.h" +#include "usbh_core.h" + +/* get the next descriptor header */ +usb_desc_header *usbh_nextdesc_get (uint8_t *pbuf, uint16_t *ptr); + +/* configure USB control status parameters */ +void usbh_ctlstate_config (usbh_host *puhost, uint8_t *buf, uint16_t len); + +/* get device descriptor from the USB device */ +usbh_status usbh_devdesc_get (usb_core_driver *pudev, usbh_host *puhost, uint8_t len); + +/* get configuration descriptor from the USB device */ +usbh_status usbh_cfgdesc_get (usb_core_driver *pudev, usbh_host *puhost, uint16_t len); + +/* get string descriptor from the USB device */ +usbh_status usbh_strdesc_get (usb_core_driver *pudev, + usbh_host *puhost, + uint8_t str_index, + uint8_t *buf, + uint16_t len); + +/* set the configuration value to the connected device */ +usbh_status usbh_setcfg (usb_core_driver *pudev, usbh_host *puhost, uint16_t config); + +/* set the address to the connected device */ +usbh_status usbh_setaddress (usb_core_driver *pudev, usbh_host *puhost, uint8_t dev_addr); + +/* clear or disable a specific feature */ +usbh_status usbh_clrfeature (usb_core_driver *pudev, + usbh_host *puhost, + uint8_t ep_num, + uint8_t pp_num); + +/* set the interface value to the connected device */ +usbh_status usbh_setinterface (usb_core_driver *pudev, + usbh_host *puhost, + uint8_t ep_num, + uint8_t alter_setting); + +#endif /* __USBH_ENUM_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbh_pipe.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbh_pipe.h new file mode 100644 index 0000000..a0d12e7 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbh_pipe.h @@ -0,0 +1,70 @@ +/*! + \file usbh_pipe.h + \brief USB host mode pipe header file + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_PIPE_H +#define __USBH_PIPE_H + +#include "usbh_core.h" + +#define HC_MAX 8U + +#define HC_OK 0x0000U +#define HC_USED 0x8000U +#define HC_ERROR 0xFFFFU +#define HC_USED_MASK 0x7FFFU + +/* allocate a new pipe */ +uint8_t usbh_pipe_allocate (usb_core_driver *pudev, uint8_t ep_addr); + +/* delete all USB host pipe */ +uint8_t usbh_pipe_delete (usb_core_driver *pudev); + +/* free a pipe */ +uint8_t usbh_pipe_free (usb_core_driver *pudev, uint8_t pp_num); + +/* create a pipe */ +uint8_t usbh_pipe_create (usb_core_driver *pudev, + usb_dev_prop *udev, + uint8_t pp_num, + uint8_t ep_type, + uint16_t ep_mpl); + +/* modify a pipe */ +uint8_t usbh_pipe_update (usb_core_driver *pudev, + uint8_t pp_num, + uint8_t dev_addr, + uint32_t dev_speed, + uint16_t ep_mpl); + +#endif /* __USBH_PIPE_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbh_transc.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbh_transc.h new file mode 100644 index 0000000..f76d132 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Include/usbh_transc.h @@ -0,0 +1,54 @@ +/*! + \file usbh_transc.h + \brief USB host mode transactions header file + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_TRANSC_H +#define __USBH_TRANSC_H + +#include "usb_conf.h" +#include "usbh_core.h" + +/* send the setup packet to the USB device */ +usbh_status usbh_ctlsetup_send (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num); + +/* send a data packet to the USB device */ +usbh_status usbh_data_send (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len); + +/* receive a data packet from the USB device */ +usbh_status usbh_data_recev (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len); + +/* USB control transfer handler */ +usbh_status usbh_ctl_handler (usb_core_driver *pudev, usbh_host *puhost); + +#endif /* __USBH_TRANSC_H */ + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_core.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_core.c new file mode 100644 index 0000000..b4cff05 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_core.c @@ -0,0 +1,319 @@ +/*! + \file drv_usb_core.c + \brief USB core driver which can operate in host and device mode + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_core.h" +#include "drv_usb_hw.h" + +/*! + \brief config USB core to soft reset + \param[in] usb_regs: USB core registers + \param[out] none + \retval none +*/ +static void usb_core_reset (usb_core_regs *usb_regs) +{ + /* enable core soft reset */ + usb_regs->gr->GRSTCTL |= GRSTCTL_CSRST; + + /* wait for the core to be soft reset */ + while (usb_regs->gr->GRSTCTL & GRSTCTL_CSRST); + + /* wait for addtional 3 PHY clocks */ + usb_udelay(3); +} + +/*! + \brief config USB core basic + \param[in] usb_basic: pointer to usb capabilities + \param[in] usb_regs: USB core registers + \param[in] usb_core: USB core + \param[out] none + \retval operation status +*/ +usb_status usb_basic_init (usb_core_basic *usb_basic, + usb_core_regs *usb_regs, + usb_core_enum usb_core) +{ + uint32_t i = 0, reg_base = 0; + + /* config USB default transfer mode as FIFO mode */ + usb_basic->transfer_mode = USB_USE_FIFO; + + /* USB default speed is full-speed */ + usb_basic->core_speed = USB_SPEED_FULL; + + usb_basic->core_enum = usb_core; + + switch (usb_core) { + case USB_CORE_ENUM_HS: + reg_base = USBHS_REG_BASE; + + /* set the host channel numbers */ + usb_basic->num_pipe = USBHS_MAX_CHANNEL_COUNT; + + /* set the device endpoint numbers */ + usb_basic->num_ep = USBHS_MAX_EP_COUNT; + +#ifdef USB_ULPI_PHY_ENABLED + usb_basic->phy_itf = USB_ULPI_PHY; +#else + usb_basic->phy_itf = USB_EMBEDDED_PHY; +#endif /* USB_ULPI_PHY_ENABLED */ + +#ifdef USB_HS_INTERNAL_DMA_ENABLED + bp->transfer_mode = USB_USE_DMA; +#endif /* USB_HS_INTERNAL_DMA_ENABLED */ + break; + + case USB_CORE_ENUM_FS: + reg_base = USBFS_REG_BASE; + + /* set the host channel numbers */ + usb_basic->num_pipe = USBFS_MAX_CHANNEL_COUNT; + + /* set the device endpoint numbers */ + usb_basic->num_ep = USBFS_MAX_EP_COUNT; + + /* USBFS core use embedded physical layer */ + usb_basic->phy_itf = USB_EMBEDDED_PHY; + break; + + default: + return USB_FAIL; + } + + usb_basic->sof_enable = USB_SOF_OUTPUT; + usb_basic->low_power = USB_LOW_POWER; + + /* assign main registers address */ + *usb_regs = (usb_core_regs) { + .gr = (usb_gr*) (reg_base + USB_REG_OFFSET_CORE), + .hr = (usb_hr*) (reg_base + USB_REG_OFFSET_HOST), + .dr = (usb_dr*) (reg_base + USB_REG_OFFSET_DEV), + + .HPCS = (uint32_t*) (reg_base + USB_REG_OFFSET_PORT), + .PWRCLKCTL = (uint32_t*) (reg_base + USB_REG_OFFSET_PWRCLKCTL) + }; + + /* assign device endpoint registers address */ + for (i = 0; i < usb_basic->num_ep; i++) { + usb_regs->er_in[i] = (usb_erin *) \ + (reg_base + USB_REG_OFFSET_EP_IN + (i * USB_REG_OFFSET_EP)); + + usb_regs->er_out[i] = (usb_erout *)\ + (reg_base + USB_REG_OFFSET_EP_OUT + (i * USB_REG_OFFSET_EP)); + } + + /* assign host pipe registers address */ + for (i = 0; i < usb_basic->num_pipe; i++) { + usb_regs->pr[i] = (usb_pr *) \ + (reg_base + USB_REG_OFFSET_CH_INOUT + (i * USB_REG_OFFSET_CH)); + + usb_regs->DFIFO[i] = (uint32_t *) \ + (reg_base + USB_DATA_FIFO_OFFSET + (i * USB_DATA_FIFO_SIZE)); + } + + return USB_OK; +} + +/*! + \brief initializes the USB controller registers and + prepares the core device mode or host mode operation + \param[in] bp: usb capabilities + \param[in] core_regs: usb core registers + \param[out] none + \retval operation status +*/ +usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs) +{ + uint32_t reg_value = usb_regs->gr->GCCFG; + + /* disable USB global interrupt */ + usb_regs->gr->GAHBCS &= ~GAHBCS_GINTEN; + + if (USB_ULPI_PHY == usb_basic.phy_itf) { + reg_value &= ~GCCFG_PWRON; + + if (usb_basic.sof_enable) { + reg_value |= GCCFG_SOFOEN; + } + + usb_regs->gr->GCCFG = GCCFG_SOFOEN; + + /* init the ULPI interface */ + usb_regs->gr->GUSBCS &= ~(GUSBCS_EMBPHY | GUSBCS_ULPIEOI); + +#ifdef USBHS_EXTERNAL_VBUS_ENABLED + /* use external VBUS driver */ + usb_regs->gr->GUSBCS |= GUSBCS_ULPIEVD; +#else + /* use internal VBUS driver */ + usb_regs->gr->GUSBCS &= ~GUSBCS_ULPIEVD; +#endif + + /* soft reset the core */ + usb_core_reset (usb_regs); + } else { + usb_regs->gr->GUSBCS |= GUSBCS_EMBPHY; + + /* soft reset the core */ + usb_core_reset (usb_regs); + + /* active the transceiver and enable vbus sensing */ + reg_value = GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; + +#ifndef VBUS_SENSING_ENABLED + reg_value |= GCCFG_VBUSIG; +#endif /* VBUS_SENSING_ENABLED */ + + /* enable SOF output */ + if (usb_basic.sof_enable) { + reg_value |= GCCFG_SOFOEN; + } + + usb_regs->gr->GCCFG = reg_value; + + usb_mdelay(20); + } + + if (USB_USE_DMA == usb_basic.transfer_mode) { + usb_regs->gr->GAHBCS |= GAHBCS_DMAEN; + usb_regs->gr->GAHBCS &= ~GAHBCS_BURST; + usb_regs->gr->GAHBCS |= DMA_INCR8; + } + +#ifdef USE_OTG_MODE + + /* enable USB OTG features */ + usb_regs->gr->GUSBCS |= GUSBCS_HNPCAP | GUSBCS_SRPCAP; + + /* enable the USB wakeup and suspend interrupts */ + usb_regs->gr->GINTF = 0xBFFFFFFFU; + + usb_regs->gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE | \ + GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE; + +#endif /* USE_OTG_MODE */ + + return USB_OK; +} + +/*! + \brief write a packet into the Tx FIFO associated with the endpoint + \param[in] core_regs: usb core registers + \param[in] src_buf: pointer to source buffer + \param[in] fifo_num: FIFO number which is in (0..3) + \param[in] byte_count: packet byte count + \param[out] none + \retval operation status +*/ +usb_status usb_txfifo_write (usb_core_regs *usb_regs, + uint8_t *src_buf, + uint8_t fifo_num, + uint16_t byte_count) +{ + uint32_t word_count = (byte_count + 3U) / 4U; + + __IO uint32_t *fifo = usb_regs->DFIFO[fifo_num]; + + while (word_count-- > 0) { + *fifo = *((__packed uint32_t *)src_buf); + + src_buf += 4U; + } + + return USB_OK; +} + +/*! + \brief read a packet from the Rx FIFO associated with the endpoint + \param[in] core_regs: usb core registers + \param[in] dest_buf: pointer to destination buffer + \param[in] byte_count: packet byte count + \param[out] none + \retval void type pointer +*/ +void *usb_rxfifo_read (usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count) +{ + uint32_t word_count = (byte_count + 3U) / 4U; + + __IO uint32_t *fifo = usb_regs->DFIFO[0]; + + while (word_count-- > 0) { + *(__packed uint32_t *)dest_buf = *fifo; + + dest_buf += 4U; + } + + return ((void *)dest_buf); +} + +/*! + \brief flush a Tx FIFO or all Tx FIFOs + \param[in] core_regs: pointer to usb core registers + \param[in] fifo_num: FIFO number which is in (0..3) + \param[out] none + \retval operation status +*/ +usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num) +{ + usb_regs->gr->GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF; + + /* wait for Tx FIFO flush bit is set */ + while (usb_regs->gr->GRSTCTL & GRSTCTL_TXFF); + + /* wait for 3 PHY clocks*/ + usb_udelay(3); + + return USB_OK; +} + +/*! + \brief flush the entire Rx FIFO + \param[in] core_regs: pointer to usb core registers + \param[out] none + \retval operation status +*/ +usb_status usb_rxfifo_flush (usb_core_regs *usb_regs) +{ + usb_regs->gr->GRSTCTL = GRSTCTL_RXFF; + + /* wait for Rx FIFO flush bit is set */ + while (usb_regs->gr->GRSTCTL & GRSTCTL_RXFF); + + /* wait for 3 PHY clocks */ + usb_udelay(3); + + return USB_OK; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_dev.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_dev.c new file mode 100644 index 0000000..5988ec5 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_dev.c @@ -0,0 +1,749 @@ +/*! + \file drv_usb_dev.c + \brief USB device mode low level driver + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +/* endpoint 0 max packet length */ +static const uint8_t EP0_MAXLEN[4] = { + [DSTAT_EM_HS_PHY_30MHZ_60MHZ] = EP0MPL_64, + [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = EP0MPL_64, + [DSTAT_EM_FS_PHY_48MHZ] = EP0MPL_64, + [DSTAT_EM_LS_PHY_6MHZ] = EP0MPL_8 +}; + +#ifdef USB_FS_CORE + +/* USB endpoint Tx FIFO size */ +static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] = +{ + (uint16_t)TX0_FIFO_FS_SIZE, + (uint16_t)TX1_FIFO_FS_SIZE, + (uint16_t)TX2_FIFO_FS_SIZE, + (uint16_t)TX3_FIFO_FS_SIZE +}; + +#elif defined(USB_HS_CORE) + +uint16_t USBHS_TX_FIFO_SIZE[USBHS_MAX_EP_COUNT] = +{ + (uint16_t)TX0_FIFO_HS_SIZE, + (uint16_t)TX1_FIFO_HS_SIZE, + (uint16_t)TX2_FIFO_HS_SIZE, + (uint16_t)TX3_FIFO_HS_SIZE, + (uint16_t)TX4_FIFO_HS_SIZE, + (uint16_t)TX5_FIFO_HS_SIZE +}; + +#endif /* USBFS_CORE */ + +/*! + \brief initialize USB core registers for device mode + \param[in] udev: pointer to usb device + \param[out] none + \retval operation status +*/ +usb_status usb_devcore_init (usb_core_driver *udev) +{ + uint32_t i, ram_addr = 0; + + /* force to peripheral mode */ + udev->regs.gr->GUSBCS &= ~(GUSBCS_FDM | GUSBCS_FHM); + udev->regs.gr->GUSBCS |= GUSBCS_FDM; + // udev->regs.gr->GUSBCS &= ~(GUSBCS_FHM); + + /* restart the Phy Clock (maybe don't need to...) */ + *udev->regs.PWRCLKCTL = 0U; + + /* config periodic frame interval to default value */ + udev->regs.dr->DCFG &= ~DCFG_EOPFT; + udev->regs.dr->DCFG |= FRAME_INTERVAL_80; + + udev->regs.dr->DCFG &= ~DCFG_DS; + +#ifdef USB_FS_CORE + if (udev->bp.core_enum == USB_CORE_ENUM_FS) { + /* set full-speed PHY */ + udev->regs.dr->DCFG |= USB_SPEED_INP_FULL; + + /* set Rx FIFO size */ + udev->regs.gr->GRFLEN = RX_FIFO_FS_SIZE; + + /* set endpoint 0 Tx FIFO length and RAM address */ + udev->regs.gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)TX0_FIFO_FS_SIZE << 16) | \ + ((uint32_t)RX_FIFO_FS_SIZE); + + ram_addr = RX_FIFO_FS_SIZE; + + /* set endpoint 1 to 3's Tx FIFO length and RAM address */ + for (i = 1; i < USBFS_MAX_EP_COUNT; i++) { + ram_addr += USBFS_TX_FIFO_SIZE[i - 1]; + + udev->regs.gr->DIEPTFLEN[i - 1] = ((uint32_t)USBFS_TX_FIFO_SIZE[i] << 16U) | \ + ram_addr; + } + } +#endif + +#ifdef USB_HS_CORE + if (udev->bp.core == USB_CORE_HS) { + if (udev->bp.core_phy == USB_ULPI_PHY) { + udev->regs.dr->DCFG |= USB_SPEED_EXP_HIGH; + } else {/* set High speed phy in Full speed mode */ + udev->regs.dr->DCFG |= USB_SPEED_EXP_FULL; + } + + /* Set Rx FIFO size */ + udev->regs.gr->GRFLEN &= ~GRFLEN_RXFD; + udev->regs.gr->GRFLEN |= RX_FIFO_HS_SIZE; + + /* Set endpoint 0 Tx FIFO length and RAM address */ + udev->regs.gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)TX0_FIFO_HS_SIZE << 16) | \ + RX_FIFO_HS_SIZE; + + ram_addr = RX_FIFO_HS_SIZE; + + /* Set endpoint 1 to 3's Tx FIFO length and RAM address */ + for (i = 1; i < USBHS_MAX_EP_COUNT; i++) { + ram_addr += USBHS_TX_FIFO_SIZE[i - 1]; + + udev->regs.gr->DIEPTFLEN[i - 1] = ((uint32_t)USBHS_TX_FIFO_SIZE[i] << 16) | \ + ram_addr; + } + } +#endif + + /* make sure all FIFOs are flushed */ + + /* flush all Tx FIFOs */ + usb_txfifo_flush (&udev->regs, 0x10); + + /* flush entire Rx FIFO */ + usb_rxfifo_flush (&udev->regs); + + /* clear all pending device interrupts */ + udev->regs.dr->DIEPINTEN = 0U; + udev->regs.dr->DOEPINTEN = 0U; + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + udev->regs.dr->DAEPINTEN = 0U; + + /* configure all IN/OUT endpoints */ + for (i = 0; i < udev->bp.num_ep; i++) { + if (udev->regs.er_in[i]->DIEPCTL & DEPCTL_EPEN) { + udev->regs.er_in[i]->DIEPCTL |= DEPCTL_EPD | DEPCTL_SNAK; + } else { + udev->regs.er_in[i]->DIEPCTL = 0U; + } + + /* set IN endpoint transfer length to 0 */ + udev->regs.er_in[i]->DIEPLEN = 0U; + + /* clear all pending IN endpoint interrupts */ + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + + if (udev->regs.er_out[i]->DOEPCTL & DEPCTL_EPEN) { + udev->regs.er_out[i]->DOEPCTL |= DEPCTL_EPD | DEPCTL_SNAK; + } else { + udev->regs.er_out[i]->DOEPCTL = 0U; + } + + /* set OUT endpoint transfer length to 0 */ + udev->regs.er_out[i]->DOEPLEN = 0U; + + /* clear all pending OUT endpoint interrupts */ + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + usb_devint_enable (udev); + + return USB_OK; +} + +/*! + \brief enable the USB device mode interrupts + \param[in] udev: pointer to usb device + \param[out] none + \retval operation status +*/ +usb_status usb_devint_enable (usb_core_driver *udev) +{ + /* clear any pending USB OTG interrupts */ + udev->regs.gr->GOTGINTF = 0xFFFFFFFFU; + + /* clear any pending interrupts */ + udev->regs.gr->GINTF = 0xBFFFFFFFU; + + /* enable the USB wakeup and suspend interrupts */ + udev->regs.gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; + + /* enable device_mode-related interrupts */ + if (USB_USE_FIFO == udev->bp.transfer_mode) { + udev->regs.gr->GINTEN |= GINTEN_RXFNEIE; + } + udev->regs.gr->GINTEN |= GINTEN_RSTIE | GINTEN_ENUMFIE | GINTEN_IEPIE |\ + GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_MFIE; + +#ifdef VBUS_SENSING_ENABLED + udev->regs.gr->GINTEN |= GINTEN_SESIE | GINTEN_OTGIE; +#endif /* VBUS_SENSING_ENABLED */ + + /* enable USB global interrupt */ + udev->regs.gr->GAHBCS |= GAHBCS_GINTEN; + + return USB_OK; +} + +/*! + \brief config the USB device to be disconnected + \param[in] udev: pointer to usb device + \param[out] none + \retval operation status +*/ +void usb_dev_disconnect (usb_core_driver *udev) +{ + udev->regs.dr->DCTL |= DCTL_SD; +} + +/*! + \brief config the USB device to be connected + \param[in] udev: pointer to usb device + \param[out] none + \retval operation status +*/ +void usb_dev_connect (usb_core_driver *udev) +{ + udev->regs.dr->DCTL &= ~DCTL_SD; +} + +/*! + \brief set the USB device address + \param[in] udev: pointer to usb device + \param[in] dev_addr: device address for setting + \param[out] none + \retval operation status +*/ +void usb_devaddr_set (usb_core_driver *udev, uint8_t dev_addr) +{ + udev->regs.dr->DCFG &= ~DCFG_DAR; + udev->regs.dr->DCFG |= dev_addr << 4; +} + +/*! + \brief active the usb transaction + \param[in] udev: pointer to usb device + \param[in] transc: the usb transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + __IO uint32_t epinten = 0U; + + /* get the endpoint number */ + uint8_t ep_num = transc->ep_addr.num; + + /* enable endpoint interrupt number */ + if (transc->ep_addr.dir) { + reg_addr = &udev->regs.er_in[ep_num]->DIEPCTL; + + epinten = 1 << ep_num; + } else { + reg_addr = &udev->regs.er_out[ep_num]->DOEPCTL; + + epinten = 1 << (16 + ep_num); + } + + /* if the endpoint is not active, need change the endpoint control register */ + if (!(*reg_addr & DEPCTL_EPACT)) { + *reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM); + + /* set endpoint maximum packet length */ + if (0U == ep_num) { + *reg_addr |= EP0_MAXLEN[udev->regs.dr->DSTAT & DSTAT_ES]; + } else { + *reg_addr |= transc->max_len; + } + + /* activate endpoint */ + *reg_addr |= (transc->ep_type << 18) | (ep_num << 22) | DEPCTL_SD0PID | DEPCTL_EPACT; + } + +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED + if ((ep_num == 1) && (udev->bp.core == USB_HS_CORE_ID)) { + udev->regs.dr->DEP1INTEN |= epinten; + } + else +#endif + { + /* enable the interrupts for this endpoint */ + udev->regs.dr->DAEPINTEN |= epinten; + } + + return USB_OK; +} + +/*! + \brief deactive the usb transaction + \param[in] udev: pointer to usb device + \param[in] transc: the usb transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_deactivate(usb_core_driver *udev, usb_transc *transc) +{ + uint32_t epinten = 0U; + + uint8_t ep_num = transc->ep_addr.num; + + /* disable endpoint interrupt number */ + if (transc->ep_addr.dir) { + epinten = 1 << ep_num; + + udev->regs.er_in[ep_num]->DIEPCTL &= ~DEPCTL_EPACT; + } else { + epinten = 1 << (ep_num + 16); + + udev->regs.er_out[ep_num]->DOEPCTL &= ~DEPCTL_EPACT; + } + +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED + if ((ep_num == 1) && (udev->bp.core == USB_CORE_HS)) { + udev->regs.dr->DEP1INTEN &= ~epinten; + } + else +#endif + { + /* disable the interrupts for this endpoint */ + udev->regs.dr->DAEPINTEN &= ~epinten; + } + + return USB_OK; +} + +/*! + \brief configure usb transaction to start IN transfer + \param[in] udev: pointer to usb device + \param[in] transc: the usb IN transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc) +{ + usb_status status = USB_OK; + + uint8_t ep_num = transc->ep_addr.num; + + __IO uint32_t epctl = udev->regs.er_in[ep_num]->DIEPCTL; + __IO uint32_t eplen = udev->regs.er_in[ep_num]->DIEPLEN; + + eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT); + + /* zero length packet or endpoint 0 */ + if (0U == transc->xfer_len) { + /* set transfer packet count to 1 */ + eplen |= 1 << 19; + } else { + /* set transfer packet count */ + if (0U == ep_num) { + transc->xfer_len = USB_MIN(transc->xfer_len, transc->max_len); + + eplen |= 1 << 19; + } else { + eplen |= ((transc->xfer_len - 1 + transc->max_len) / transc->max_len) << 19; + } + + /* set endpoint transfer length */ + eplen |= transc->xfer_len; + + if (transc->ep_type == USB_EPTYPE_ISOC) { + eplen |= DIEPLEN_MCNT; + } + } + + udev->regs.er_in[ep_num]->DIEPLEN = eplen; + + if (USB_USE_DMA == udev->bp.transfer_mode) { + udev->regs.er_in[ep_num]->DIEPDMAADDR = transc->dma_addr; + } + + if (transc->ep_type == USB_EPTYPE_ISOC) { + if (((udev->regs.dr->DSTAT & DSTAT_FNRSOF) >> 8) & 0x1) { + epctl |= DEPCTL_SD1PID; + } else { + epctl |= DEPCTL_SD0PID; + } + } + + /* enable the endpoint and clear the NAK */ + epctl |= DEPCTL_CNAK | DEPCTL_EPEN; + + udev->regs.er_in[ep_num]->DIEPCTL = epctl; + + if (transc->ep_type != USB_EPTYPE_ISOC) { + /* enable the Tx FIFO empty interrupt for this endpoint */ + if (transc->xfer_len > 0) { + udev->regs.dr->DIEPFEINTEN |= 1 << ep_num; + } + } else { + usb_txfifo_write (&udev->regs, transc->xfer_buf, ep_num, transc->xfer_len); + } + + return status; +} + +/*! + \brief configure usb transaction to start OUT transfer + \param[in] udev: pointer to usb device + \param[in] transc: the usb OUT transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc) +{ + usb_status status = USB_OK; + + uint8_t ep_num = transc->ep_addr.num; + + uint32_t epctl = udev->regs.er_out[ep_num]->DOEPCTL; + uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN; + + eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT); + + /* zero length packet or endpoint 0 */ + if ((0U == transc->xfer_len) || (0U == ep_num)) { + /* set the transfer length to max packet size */ + eplen |= transc->max_len; + + /* set the transfer packet count to 1 */ + eplen |= 1U << 19; + } else { + /* configure the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + uint32_t packet_count = (transc->xfer_len + transc->max_len - 1) / transc->max_len; + + eplen |= packet_count << 19; + eplen |= packet_count * transc->max_len; + } + + udev->regs.er_out[ep_num]->DOEPLEN = eplen; + + if (USB_USE_DMA == udev->bp.transfer_mode) { + udev->regs.er_out[ep_num]->DOEPDMAADDR = transc->dma_addr; + } + + if (transc->ep_type == USB_EPTYPE_ISOC) { + if (transc->frame_num) { + epctl |= DEPCTL_SD1PID; + } else { + epctl |= DEPCTL_SD0PID; + } + } + + /* enable the endpoint and clear the NAK */ + epctl |= DEPCTL_EPEN | DEPCTL_CNAK; + + udev->regs.er_out[ep_num]->DOEPCTL = epctl; + + return status; +} + +/*! + \brief set the usb transaction STALL status + \param[in] udev: pointer to usb device + \param[in] transc: the usb transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_stall (usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + uint8_t ep_num = transc->ep_addr.num; + + if (transc->ep_addr.dir) { + reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL); + + /* set the endpoint disable bit */ + if (*reg_addr & DEPCTL_EPEN) { + *reg_addr |= DEPCTL_EPD; + } + } else { + /* set the endpoint stall bit */ + reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL); + } + + /* set the endpoint stall bit */ + *reg_addr |= DEPCTL_STALL; + + return USB_OK; +} + +/*! + \brief clear the usb transaction STALL status + \param[in] udev: pointer to usb device + \param[in] transc: the usb transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_clrstall(usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + uint8_t ep_num = transc->ep_addr.num; + + if (transc->ep_addr.dir) { + reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL); + } else { + reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL); + } + + /* clear the endpoint stall bits */ + *reg_addr &= ~DEPCTL_STALL; + + /* reset data PID of the periodic endpoints */ + if ((transc->ep_type == USB_EPTYPE_INTR) || (transc->ep_type == USB_EPTYPE_BULK)) { + *reg_addr |= DEPCTL_SD0PID; + } + + return USB_OK; +} + +/*! + \brief read device all OUT endpoint interrupt register + \param[in] udev: pointer to usb device + \param[out] none + \retval none +*/ +uint32_t usb_oepintnum_read (usb_core_driver *udev) +{ + uint32_t value = udev->regs.dr->DAEPINT; + + value &= udev->regs.dr->DAEPINTEN; + + return (value & DAEPINT_OEPITB) >> 16; +} + +/*! + \brief read device OUT endpoint interrupt flag register + \param[in] udev: pointer to usb device + \param[in] ep_num: endpoint number + \param[out] none + \retval none +*/ +uint32_t usb_oepintr_read (usb_core_driver *udev, uint8_t ep_num) +{ + uint32_t value = udev->regs.er_out[ep_num]->DOEPINTF; + + value &= udev->regs.dr->DOEPINTEN; + + return value; +} + +/*! + \brief read device all IN endpoint interrupt register + \param[in] udev: pointer to usb device + \param[out] none + \retval none +*/ +uint32_t usb_iepintnum_read (usb_core_driver *udev) +{ + uint32_t value = udev->regs.dr->DAEPINT; + + value &= udev->regs.dr->DAEPINTEN; + + return value & DAEPINT_IEPITB; +} + + +/*! + \brief read device IN endpoint interrupt flag register + \param[in] udev: pointer to usb device + \param[in] ep_num: endpoint number + \param[out] none + \retval none +*/ +uint32_t usb_iepintr_read (usb_core_driver *udev, uint8_t ep_num) +{ + uint32_t value = 0U, fifoemptymask = 0U, commonintmask = 0U; + + commonintmask = udev->regs.dr->DIEPINTEN; + fifoemptymask = udev->regs.dr->DIEPFEINTEN; + + /* check FIFO empty interrupt enable bit */ + commonintmask |= ((fifoemptymask >> ep_num) & 0x1U) << 7; + + value = udev->regs.er_in[ep_num]->DIEPINTF & commonintmask; + + return value; +} + +/*! + \brief configures OUT endpoint 0 to receive SETUP packets + \param[in] udev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_ctlep_startout (usb_core_driver *udev) +{ + /* set OUT endpoint 0 receive length to 24 bytes, 1 packet and 3 setup packets */ + udev->regs.er_out[0]->DOEPLEN = DOEP0_TLEN(8U * 3U) | DOEP0_PCNT(1U) | DOEP0_STPCNT(3U); + + if (USB_USE_DMA == udev->bp.transfer_mode) { + udev->regs.er_out[0]->DOEPDMAADDR = (uint32_t)&udev->dev.control.req; + + /* endpoint enable */ + udev->regs.er_out[0]->DOEPCTL |= DEPCTL_EPACT | DEPCTL_EPEN; + } +} + +/*! + \brief set remote wakeup signalling + \param[in] udev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_rwkup_set (usb_core_driver *udev) +{ + if (udev->dev.pm.dev_remote_wakeup) { + /* enable remote wakeup signaling */ + udev->regs.dr->DCTL |= DCTL_RWKUP; + } +} + +/*! + \brief reset remote wakeup signalling + \param[in] udev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_rwkup_reset (usb_core_driver *udev) +{ + if (udev->dev.pm.dev_remote_wakeup) { + /* disable remote wakeup signaling */ + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + } +} + +/*! + \brief active remote wakeup signalling + \param[in] udev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_rwkup_active (usb_core_driver *udev) +{ + if (udev->dev.pm.dev_remote_wakeup) { + if (udev->regs.dr->DSTAT & DSTAT_SPST) { + if (udev->bp.low_power) { + /* ungate USB core clock */ + *udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK); + } + + /* active remote wakeup signaling */ + udev->regs.dr->DCTL |= DCTL_RWKUP; + + usb_mdelay(5); + + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + } + } +} + +/*! + \brief active USB core clock + \param[in] udev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_clock_active (usb_core_driver *udev) +{ + if (udev->bp.low_power) { + if (udev->regs.dr->DSTAT & DSTAT_SPST) { + /* un-gate USB Core clock */ + *udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK); + } + } +} + +/*! + \brief usb device suspend + \param[in] udev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_dev_suspend (usb_core_driver *udev) +{ + __IO uint32_t devstat = udev->regs.dr->DSTAT; + + if ((udev->bp.low_power) && (devstat & DSTAT_SPST)) { + /* switch-off the USB clocks */ + *udev->regs.PWRCLKCTL |= PWRCLKCTL_SHCLK; + + /* enter DEEP_SLEEP mode with LDO in low power mode */ + pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); + } +} + +/*! + \brief stop the device and clean up fifos + \param[in] udev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_dev_stop (usb_core_driver *udev) +{ + uint32_t i; + + udev->dev.cur_status = 1; + + /* clear all interrupt flag and enable bits */ + for (i = 0; i < udev->bp.num_ep; i++) { + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + udev->regs.dr->DIEPINTEN = 0U; + udev->regs.dr->DOEPINTEN = 0U; + udev->regs.dr->DAEPINTEN = 0U; + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + + /* flush the FIFO */ + usb_rxfifo_flush (&udev->regs); + usb_txfifo_flush (&udev->regs, 0x10); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_host.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_host.c new file mode 100644 index 0000000..747d40c --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/drv_usb_host.c @@ -0,0 +1,514 @@ +/*! + \file drv_usb_host.c + \brief USB host mode low level driver + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "../Include/drv_usb_hw.h" +#include "../Include/drv_usb_core.h" +#include "../Include/drv_usb_host.h" + +const uint32_t PIPE_DPID[] = { + PIPE_DPID_DATA0, + PIPE_DPID_DATA1 +}; + +//__STATIC_INLINE uint8_t usb_frame_even (usb_core_driver *pudev) +uint32_t usb_frame_even (usb_core_driver *pudev) +{ + return !(pudev->regs.hr->HFINFR & 0x01U); +} + +//__STATIC_INLINE void usb_phyclock_config (usb_core_driver *pudev, uint8_t clock) +void usb_phyclock_config (usb_core_driver *pudev, uint8_t clock) +{ + pudev->regs.hr->HCTL &= ~HCTL_CLKSEL; + pudev->regs.hr->HCTL |= clock; +} + +//__STATIC_INLINE uint32_t usb_port_read (usb_core_driver *pudev) +uint32_t usb_port_read (usb_core_driver *pudev) +{ + return *pudev->regs.HPCS & ~(HPCS_PE | HPCS_PCD | HPCS_PEDC); +} + +//__STATIC_INLINE uint32_t usb_curspeed_get (usb_core_driver *pudev) + +uint32_t usb_curspeed_get (usb_core_driver *pudev) +{ + return *pudev->regs.HPCS & HPCS_PS; +} + +uint32_t usb_curframe_get (usb_core_driver *pudev) +{ + return (pudev->regs.hr->HFINFR & 0xFFFFU); +} + +/*! + \brief initializes USB core for host mode + \param[in] pudev: pointer to selected usb host + \param[out] none + \retval operation status +*/ +usb_status usb_host_init (usb_core_driver *pudev) +{ + uint32_t i = 0, inten = 0U; + + uint32_t nptxfifolen = 0U; + uint32_t ptxfifolen = 0U; + + pudev->regs.gr->GUSBCS &= ~GUSBCS_FDM; + pudev->regs.gr->GUSBCS |= GUSBCS_FHM; + + /* restart the PHY Clock */ + *pudev->regs.PWRCLKCTL = 0U; + + /* initialize host configuration register */ + if (USB_ULPI_PHY == pudev->bp.phy_itf) { + usb_phyclock_config (pudev, HCTL_30_60MHZ); + } else { + usb_phyclock_config (pudev, HCTL_48MHZ); + } + + usb_port_reset (pudev); + + /* support FS/LS only */ + pudev->regs.hr->HCTL &= ~HCTL_SPDFSLS; + + /* configure data FIFOs size */ +#ifdef USB_FS_CORE + if (USB_CORE_ENUM_FS == pudev->bp.core_enum) { + /* set Rx FIFO size */ + pudev->regs.gr->GRFLEN = USB_RX_FIFO_FS_SIZE; + + /* set non-periodic Tx FIFO size and address */ + nptxfifolen |= USB_RX_FIFO_FS_SIZE; + nptxfifolen |= USB_HTX_NPFIFO_FS_SIZE << 16U; + pudev->regs.gr->DIEP0TFLEN_HNPTFLEN = nptxfifolen; + + /* set periodic Tx FIFO size and address */ + ptxfifolen |= USB_RX_FIFO_FS_SIZE + USB_HTX_PFIFO_FS_SIZE; + ptxfifolen |= USB_HTX_PFIFO_FS_SIZE << 16U; + pudev->regs.gr->HPTFLEN = ptxfifolen; + } +#endif /* USB_FS_CORE */ + +#ifdef USB_HS_CORE + if (USB_CORE_HS == pudev->cfg.core) { + /* set Rx FIFO size */ + pudev->regs.gr->GRFLEN = USBHS_RX_FIFO_SIZE; + + /* set non-periodic Tx FIFO size and address */ + nptxfifolen |= USBHS_RX_FIFO_SIZE; + nptxfifolen |= USBHS_HTX_NPFIFO_SIZE; + pudev->regs.gr->DIEP0TFLEN_HNPTFLEN = nptxfifolen; + + /* set periodic Tx FIFO size and address */ + ptxfifolen |= USBHS_RX_FIFO_SIZE + USBHS_HTX_PFIFO_SIZE; + ptxfifolen |= USBHS_HTX_PFIFO_SIZE; + pudev->regs.gr->HPTFLEN = ptxfifolen; + } +#endif + +#ifdef USE_OTG_MODE + + /* clear host set hnp enable in the usb_otg control register */ + pudev->regs.gr->GOTGCS &= ~GOTGCS_HHNPEN; + +#endif + + /* disable all interrupts */ + pudev->regs.gr->GINTEN = 0U; + + /* clear any pending USB OTG interrupts */ + pudev->regs.gr->GOTGINTF = 0xFFFFFFFFU; + + /* enable the USB wakeup and suspend interrupts */ + pudev->regs.gr->GINTF = 0xBFFFFFFFU; + + /* make sure the FIFOs are flushed */ + + /* flush all Tx FIFOs in device or host mode */ + usb_txfifo_flush (&pudev->regs, 0x10U); + + /* flush the entire Rx FIFO */ + usb_rxfifo_flush (&pudev->regs); + + /* clear all pending host channel interrupts */ + for (i = 0U; i < pudev->bp.num_pipe; i++) { + pudev->regs.pr[i]->HCHINTF = 0xFFFFFFFFU; + pudev->regs.pr[i]->HCHINTEN = 0U; + } + +#ifndef USE_OTG_MODE + usb_portvbus_switch (pudev, 1U); +#endif /* USE_OTG_MODE */ + + pudev->regs.gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; + + /* enable host_mode-related interrupts */ + if (USB_USE_FIFO == pudev->bp.transfer_mode) { + inten = GINTEN_RXFNEIE; + } + + inten |= GINTEN_HPIE | GINTEN_HCIE | GINTEN_ISOINCIE; + + pudev->regs.gr->GINTEN |= inten; + + inten = GINTEN_DISCIE | GINTEN_SOFIE; + + pudev->regs.gr->GINTEN &= ~inten; + + pudev->regs.gr->GAHBCS |= GAHBCS_GINTEN; + + return USB_OK; +} + +/*! + \brief control the VBUS to power + \param[in] pudev: pointer to selected usb host + \param[in] state: VBUS state + \param[out] none + \retval none +*/ +void usb_portvbus_switch (usb_core_driver *pudev, uint8_t state) +{ + uint32_t port = 0U; + + /* enable or disable the external charge pump */ + usb_vbus_drive (state); + + /* turn on the host port power. */ + port = usb_port_read (pudev); + + if (!(port & HPCS_PP) && (1U == state)) { + port |= HPCS_PP; + } + + if ((port & HPCS_PP) && (0U == state)) { + port &= ~HPCS_PP; + } + + *pudev->regs.HPCS = port; + + usb_mdelay (200U); +} + +/*! + \brief reset host port + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +uint32_t usb_port_reset (usb_core_driver *pudev) +{ + __IO uint32_t port = usb_port_read (pudev); + + *pudev->regs.HPCS = port | HPCS_PRST; + + usb_mdelay (100U); /* see note */ + + *pudev->regs.HPCS = port & ~HPCS_PRST; + + usb_mdelay (20U); + + return 1; +} + +/*! + \brief initialize host pipe + \param[in] pudev: pointer to usb device + \param[in] pipe_num: host pipe number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status usb_pipe_init (usb_core_driver *pudev, uint8_t pipe_num) +{ + usb_status status = USB_OK; + + __IO uint32_t pp_ctl = 0U; + __IO uint32_t pp_inten = HCHINTEN_TFIE; + + usb_pipe *pp = &pudev->host.pipe[pipe_num]; + + /* clear old interrupt conditions for this host channel */ + pudev->regs.pr[pipe_num]->HCHINTF = 0xFFFFFFFFU; + + if (USB_USE_DMA == pudev->bp.transfer_mode) { + pp_inten |= HCHINTEN_DMAERIE; + } + + if (pp->ep.dir) { + pp_inten |= HCHINTEN_BBERIE; + } + + /* enable channel interrupts required for this transfer */ + switch (pp->ep.type) { + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + pp_inten |= HCHINTEN_STALLIE | HCHINTEN_USBERIE \ + | HCHINTEN_DTERIE | HCHINTEN_NAKIE; + + if (!pp->ep.dir) { + pp_inten |= HCHINTEN_NYETIE; + + if (pp->ping) { + pp_inten |= HCHINTEN_ACKIE; + } + } + break; + + case USB_EPTYPE_INTR: + pp_inten |= HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE \ + | HCHINTEN_NAKIE | HCHINTEN_REQOVRIE; + break; + + case USB_EPTYPE_ISOC: + pp_inten |= HCHINTEN_REQOVRIE | HCHINTEN_ACKIE; + + if (pp->ep.dir) { + pp_inten |= HCHINTEN_USBERIE; + } + break; + + default: + break; + } + + pudev->regs.pr[pipe_num]->HCHINTEN = pp_inten; + + /* enable the top level host channel interrupt */ + pudev->regs.hr->HACHINTEN |= 1U << pipe_num; + + /* make sure host channel interrupts are enabled */ + pudev->regs.gr->GINTEN |= GINTEN_HCIE; + + /* program the host channel control register */ + pp_ctl |= PIPE_CTL_DAR(pp->dev_addr); + pp_ctl |= PIPE_CTL_EPNUM(pp->ep.num); + pp_ctl |= PIPE_CTL_EPDIR(pp->ep.dir); + pp_ctl |= PIPE_CTL_EPTYPE(pp->ep.type); + pp_ctl |= PIPE_CTL_LSD(pp->dev_speed == PORT_SPEED_LOW); + + pp_ctl |= pp->ep.mps; + pp_ctl |= ((uint32_t)(pp->ep.type == USB_EPTYPE_INTR) << 29U) & HCHCTL_ODDFRM; + + pudev->regs.pr[pipe_num]->HCHCTL = pp_ctl; + + return status; +} + +/*! + \brief prepare host channel for transferring packets + \param[in] pudev: pointer to usb device + \param[in] pipe_num: host pipe number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status usb_pipe_xfer (usb_core_driver *pudev, uint8_t pipe_num) +{ + usb_status status = USB_OK; + + uint16_t dword_len = 0U; + uint16_t packet_count = 0U; + + __IO uint32_t pp_ctl = 0U; + + usb_pipe *pp = &pudev->host.pipe[pipe_num]; + + uint16_t max_packet_len = pp->ep.mps; + + /* compute the expected number of packets associated to the transfer */ + if (pp->xfer_len > 0U) { + packet_count = (pp->xfer_len + max_packet_len - 1U) / max_packet_len; + + if (packet_count > HC_MAX_PACKET_COUNT) { + packet_count = HC_MAX_PACKET_COUNT; + pp->xfer_len = packet_count * max_packet_len; + } + } else { + packet_count = 1U; + } + + if (pp->ep.dir) { + pp->xfer_len = packet_count * max_packet_len; + } + + /* initialize the host channel transfer information */ + pudev->regs.pr[pipe_num]->HCHLEN = pp->xfer_len | pp->DPID | PIPE_XFER_PCNT(packet_count); + + if (USB_USE_DMA == pudev->bp.transfer_mode) { + pudev->regs.pr[pipe_num]->HCHDMAADDR = (unsigned int)pp->xfer_buf; + } + + pp_ctl = pudev->regs.pr[pipe_num]->HCHCTL; + + if (usb_frame_even(pudev)) { + pp_ctl |= HCHCTL_ODDFRM; + } else { + pp_ctl &= ~HCHCTL_ODDFRM; + } + + /* set host channel enabled */ + pp_ctl |= HCHCTL_CEN; + pp_ctl &= ~HCHCTL_CDIS; + + pudev->regs.pr[pipe_num]->HCHCTL = pp_ctl; + + if (USB_USE_FIFO == pudev->bp.transfer_mode) { + if ((0U == pp->ep.dir) && (pp->xfer_len > 0U)) { + switch (pp->ep.type) { + /* non-periodic transfer */ + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + dword_len = (pp->xfer_len + 3U) / 4U; + + /* check if there is enough space in fifo space */ + if (dword_len > (pudev->regs.gr->HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { + /* need to process data in nptxfempty interrupt */ + pudev->regs.gr->GINTEN |= GINTEN_NPTXFEIE; + } + break; + + /* periodic transfer */ + case USB_EPTYPE_INTR: + case USB_EPTYPE_ISOC: + dword_len = (pp->xfer_len + 3U) / 4U; + + /* check if there is enough space in fifo space */ + if (dword_len > (pudev->regs.hr->HPTFQSTAT & HPTFQSTAT_PTXFS)) { + /* need to process data in ptxfempty interrupt */ + pudev->regs.gr->GINTEN |= GINTEN_PTXFEIE; + } + break; + + default: + break; + } + + /* write packet into the tx fifo. */ + usb_txfifo_write (&pudev->regs, pp->xfer_buf, pipe_num, pp->xfer_len); + } + } + + return status; +} + +/*! + \brief halt pipe + \param[in] pudev: pointer to usb device + \param[in] pipe_num: host pipe number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status usb_pipe_halt (usb_core_driver *pudev, uint8_t pipe_num) +{ + __IO uint32_t pp_ctl = pudev->regs.pr[pipe_num]->HCHCTL; + + uint8_t ep_type = (pp_ctl & HCHCTL_EPTYPE) >> 18U; + + pp_ctl |= HCHCTL_CEN | HCHCTL_CDIS; + + switch (ep_type) { + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + if (0U == (pudev->regs.gr->HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { + pp_ctl &= ~HCHCTL_CEN; + } + break; + + case USB_EPTYPE_INTR: + case USB_EPTYPE_ISOC: + if (0U == (pudev->regs.hr->HPTFQSTAT & HPTFQSTAT_PTXFS)) { + pp_ctl &= ~HCHCTL_CEN; + } + break; + + default: + break; + } + + pudev->regs.pr[pipe_num]->HCHCTL = pp_ctl; + + return USB_OK; +} + +/*! + \brief configure host pipe to do ping operation + \param[in] pudev: pointer to usb device + \param[in] pipe_num: host pipe number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status usb_pipe_ping (usb_core_driver *pudev, uint8_t pipe_num) +{ + uint32_t pp_ctl = 0U; + + pudev->regs.pr[pipe_num]->HCHLEN = HCHLEN_PING | (HCHLEN_PCNT & (1U << 19U)); + + pp_ctl = pudev->regs.pr[pipe_num]->HCHCTL; + + pp_ctl |= HCHCTL_CEN; + pp_ctl &= ~HCHCTL_CDIS; + + pudev->regs.pr[pipe_num]->HCHCTL = pp_ctl; + + return USB_OK; +} + +/*! + \brief stop the USB host and clean up FIFO + \param[in] none + \param[out] none + \retval none +*/ +void usb_host_stop (usb_core_driver *pudev) +{ + uint32_t i; + __IO uint32_t pp_ctl = 0U; + + pudev->regs.hr->HACHINTEN = 0x0U; + pudev->regs.hr->HACHINT = 0xFFFFFFFFU; + + /* flush out any leftover queued requests. */ + for (i = 0U; i < pudev->bp.num_pipe; i++) { + pp_ctl = pudev->regs.pr[i]->HCHCTL; + + pp_ctl &= ~(HCHCTL_CEN | HCHCTL_EPDIR); + pp_ctl |= HCHCTL_CDIS; + + pudev->regs.pr[i]->HCHCTL = pp_ctl; + } + + /* flush the FIFO */ + usb_rxfifo_flush (&pudev->regs); + usb_txfifo_flush (&pudev->regs, 0x10U); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/drv_usbd_int.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/drv_usbd_int.c new file mode 100644 index 0000000..f2c74c9 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/drv_usbd_int.c @@ -0,0 +1,595 @@ +/*! + \file drv_usbd_int.c + \brief USB device mode interrupt routines + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_conf.h" +#include "drv_usbd_int.h" +#include "usbd_transc.h" + +static uint32_t usbd_int_epout (usb_core_driver *udev); +static uint32_t usbd_int_epin (usb_core_driver *udev); +static uint32_t usbd_int_rxfifo (usb_core_driver *udev); +static uint32_t usbd_int_reset (usb_core_driver *udev); +static uint32_t usbd_int_enumfinish (usb_core_driver *udev); +static uint32_t usbd_int_suspend (usb_core_driver *udev); + +static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num); + +static const uint8_t USB_SPEED[4] = { + [DSTAT_EM_HS_PHY_30MHZ_60MHZ] = USB_SPEED_HIGH, + [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = USB_SPEED_FULL, + [DSTAT_EM_FS_PHY_48MHZ] = USB_SPEED_FULL, + [DSTAT_EM_LS_PHY_6MHZ] = USB_SPEED_LOW +}; + +__IO uint8_t setupc_flag = 0U; + +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED + +/*! + \brief USB dedicated OUT endpoint 1 interrupt service routine handler + \param[in] udev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +uint32_t USBD_OTG_EP1OUT_ISR_Handler (usb_core_driver *udev) +{ + uint32_t oepintr = 0U; + uint32_t oeplen = 0U; + + oepintr = udev->regs.er_out[1]->DOEPINTF; + oepintr &= udev->regs.dr->DOEP1INTEN; + + /* Transfer complete */ + if (oepintr & DOEPINTF_TF) + { + /* Clear the bit in DOEPINTn for this interrupt */ + udev->regs.er_out[1]->DOEPINTF = DOEPINTF_TF; + + if (USB_USE_DMA == udev->bp.transfer_mode) + { + oeplen = udev->regs.er_out[1]->DOEPLEN; + + /* ToDo : handle more than one single MPS size packet */ + udev->dev.transc_out[1].xfer_count = udev->dev.transc_out[1].usb_transc - \ + oeplen & DEPLEN_TLEN; + } + + /* RX COMPLETE */ + USBD_DCD_INT_fops->DataOutStage(udev, 1); + } + + return 1; +} + +/*! + \brief USB dedicated IN endpoint 1 interrupt service routine handler + \param[in] udev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +uint32_t USBD_OTG_EP1IN_ISR_Handler (usb_core_driver *udev) +{ + uint32_t inten, intr, emptyen; + + inten = udev->regs.dr->DIEP1INTEN; + emptyen = udev->regs.dr->DIEPFEINTEN; + + inten |= ((emptyen >> 1 ) & 0x1) << 7; + + intr = udev->regs.er_in[1]->DIEPINTF & inten; + + if (intr & DIEPINTF_TF) + { + udev->regs.dr->DIEPFEINTEN &= ~(0x1 << 1); + + udev->regs.er_in[1]->DIEPINTF = DIEPINTF_TF; + + /* TX COMPLETE */ + USBD_DCD_INT_fops->DataInStage(udev, 1); + } + + if (intr & DIEPINTF_TXFE) + { + DCD_WriteEmptyTxFifo(udev, 1); + + udev->regs.er_in[1]->DIEPINTF = DIEPINTF_TXFE; + } + + return 1; +} + +#endif + + +/*! + \brief USB device-mode interrupts global service routine handler + \param[in] udev: pointer to usb device instance + \param[out] none + \retval none +*/ +void usbd_isr (usb_core_driver *udev) +{ + if (HOST_MODE != (udev->regs.gr->GINTF & GINTF_COPM)) { + uint32_t intr = udev->regs.gr->GINTF & udev->regs.gr->GINTEN; + + /* there are no interrupts, avoid spurious interrupt */ + if (!intr) { + return; + } + + /* OUT endpoints interrupts */ + if (intr & GINTF_OEPIF) { + usbd_int_epout (udev); + } + + /* IN endpoints interrupts */ + if (intr & GINTF_IEPIF) { + usbd_int_epin (udev); + } + + /* suspend interrupt */ + if (intr & GINTF_SP) { + usbd_int_suspend (udev); + } + + /* wakeup interrupt */ + if (intr & GINTF_WKUPIF) { + /* inform upper layer by the resume event */ + udev->dev.cur_status = udev->dev.backup_status; + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_WKUPIF; + } + + /* wakeup interrupt */ + if (intr & GINTF_MFIF) { + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_MFIF; + } + + /* start of frame interrupt */ + if (intr & GINTF_SOF) { + if (udev->dev.class_core->SOF) { + udev->dev.class_core->SOF(udev); + } + + if (0U != setupc_flag) { + setupc_flag ++; + + if (setupc_flag >= 3U) { + usbd_setup_transc (udev); + + setupc_flag = 0U; + } + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_SOF; + } + + /* receive FIFO not empty interrupt */ + if (intr & GINTF_RXFNEIF) { + usbd_int_rxfifo (udev); + } + + /* USB reset interrupt */ + if (intr & GINTF_RST) { + usbd_int_reset (udev); + } + + /* enumeration has been done interrupt */ + if (intr & GINTF_ENUMFIF) { + usbd_int_enumfinish (udev); + } + + /* incomplete synchronization IN transfer interrupt*/ + if (intr & GINTF_ISOINCIF) { + if (NULL != udev->dev.class_core->incomplete_isoc_in) { + udev->dev.class_core->incomplete_isoc_in(udev); + } + + /* Clear interrupt */ + udev->regs.gr->GINTF = GINTF_ISOINCIF; + } + + /* incomplete synchronization OUT transfer interrupt*/ + if (intr & GINTF_ISOONCIF) { + if (NULL != udev->dev.class_core->incomplete_isoc_out) { + udev->dev.class_core->incomplete_isoc_out(udev); + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_ISOONCIF; + } + +#ifdef VBUS_SENSING_ENABLED + + /* Session request interrupt */ + if (intr & GINTF_SESIF) { + udev->regs.gr->GINTF = GINTF_SESIF; + } + + /* OTG mode interrupt */ + if (intr & GINTF_OTGIF) { + if(udev->regs.gr->GOTGINTF & GOTGINTF_SESEND) { + + } + + /* Clear OTG interrupt */ + udev->regs.gr->GINTF = GINTF_OTGIF; + } +#endif + } +} + +/*! + \brief indicates that an OUT endpoint has a pending interrupt + \param[in] udev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_epout (usb_core_driver *udev) +{ + uint32_t epintnum = 0U; + uint32_t ep_num = 0U; + + for (epintnum = usb_oepintnum_read (udev); epintnum; epintnum >>= 1, ep_num++) { + if (epintnum & 0x1) { + __IO uint32_t oepintr = usb_oepintr_read (udev, ep_num); + + /* transfer complete interrupt */ + if (oepintr & DOEPINTF_TF) { + /* clear the bit in DOEPINTF for this interrupt */ + udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_TF; + + if (USB_USE_DMA == udev->bp.transfer_mode) { + __IO uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN; + + udev->dev.transc_out[ep_num].xfer_count = udev->dev.transc_out[ep_num].max_len - \ + eplen & DEPLEN_TLEN; + } + + /* inform upper layer: data ready */ + usbd_out_transc (udev, ep_num); + + if (USB_USE_DMA == udev->bp.transfer_mode) { + if ((0U == ep_num) && (USB_CTL_STATUS_OUT == udev->dev.control.ctl_state)) { + usb_ctlep_startout (udev); + } + } + } + + /* setup phase finished interrupt (control endpoints) */ + if (oepintr & DOEPINTF_STPF) { + /* inform the upper layer that a setup packet is available */ + if ((0U == ep_num) && (0U != setupc_flag)) { + usbd_setup_transc (udev); + + setupc_flag = 0U; + + udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_STPF; + } + } + } + } + + return 1; +} + +/*! + \brief indicates that an IN endpoint has a pending interrupt + \param[in] udev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_epin (usb_core_driver *udev) +{ + uint32_t epintnum = 0U; + uint32_t ep_num = 0U; + + for (epintnum = usb_iepintnum_read (udev); epintnum; epintnum >>= 1, ep_num++) { + if (epintnum & 0x1U) { + __IO uint32_t iepintr = usb_iepintr_read (udev, ep_num); + + if (iepintr & DIEPINTF_TF) { + udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TF; + + /* data transmittion is completed */ + usbd_in_transc (udev, ep_num); + + if (USB_USE_DMA == udev->bp.transfer_mode) { + if ((0U == ep_num) && (USB_CTL_STATUS_IN == udev->dev.control.ctl_state)) { + usb_ctlep_startout (udev); + } + } + } + + if (iepintr & DIEPINTF_TXFE) { + usbd_emptytxfifo_write (udev, ep_num); + + udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TXFE; + } + } + } + + return 1; +} + +/*! + \brief handle the RX status queue level interrupt + \param[in] udev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_rxfifo (usb_core_driver *udev) +{ + usb_transc *transc = NULL; + + uint8_t data_PID = 0; + uint32_t bcount = 0; + + __IO uint32_t devrxstat = 0; + + /* disable the Rx status queue non-empty interrupt */ + udev->regs.gr->GINTEN &= ~GINTEN_RXFNEIE; + + /* get the status from the top of the FIFO */ + devrxstat = udev->regs.gr->GRSTATP; + + transc = &udev->dev.transc_out[devrxstat & GRSTATRP_EPNUM]; + + bcount = (devrxstat & GRSTATRP_BCOUNT) >> 4; + data_PID = (devrxstat & GRSTATRP_DPID) >> 15; + + switch ((devrxstat & GRSTATRP_RPCKST) >> 17) { + case RSTAT_GOUT_NAK: + break; + + case RSTAT_DATA_UPDT: + if (bcount > 0) { + usb_rxfifo_read (&udev->regs, transc->xfer_buf, bcount); + + transc->xfer_buf += bcount; + transc->xfer_count += bcount; + } + break; + + case RSTAT_XFER_COMP: + /* trigger the OUT enpoint interrupt */ + break; + + case RSTAT_SETUP_COMP: + /* trigger the OUT enpoint interrupt */ + break; + + case RSTAT_SETUP_UPDT: + if ((transc->ep_addr.num == 0) && (bcount == 8) && (data_PID == DPID_DATA0)) { + /* copy the setup packet received in FIFO into the setup buffer in RAM */ + usb_rxfifo_read (&udev->regs, (uint8_t *)&udev->dev.control.req, bcount); + + transc->xfer_count += bcount; + + setupc_flag = 1; + } + break; + + default: + break; + } + + /* enable the Rx status queue level interrupt */ + udev->regs.gr->GINTEN |= GINTEN_RXFNEIE; + + return 1; +} + +/*! + \brief handle USB reset interrupt + \param[in] udev: pointer to usb device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_int_reset (usb_core_driver *udev) +{ + uint32_t i; + + /* clear the remote wakeup signaling */ + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + + /* flush the Tx FIFO */ + usb_txfifo_flush (&udev->regs, 0); + + for (i = 0; i < udev->bp.num_ep; i++) { + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + /* clear all pending device endpoint interrupts */ + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + + /* enable endpoint 0 interrupts */ + udev->regs.dr->DAEPINTEN = 1U | (1U << 16); + + /* enable OUT endpoint interrupts */ + udev->regs.dr->DOEPINTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN; + + /* enable IN endpoint interrupts */ + udev->regs.dr->DIEPINTEN = DIEPINTEN_TFEN; + + /* reset device address */ + udev->regs.dr->DCFG &= ~DCFG_DAR; + udev->dev.dev_addr = 0U; + + /* configure endpoint 0 to receive SETUP packets */ + usb_ctlep_startout (udev); + + /* clear USB reset interrupt */ + udev->regs.gr->GINTF = GINTF_RST; + + udev->dev.transc_out[0] = (usb_transc) { + .ep_type = USB_EPTYPE_CTRL, + .max_len = USB_FS_EP0_MAX_LEN + }; + + usb_transc_active (udev, &udev->dev.transc_out[0]); + + udev->dev.transc_in[0] = (usb_transc) { + .ep_addr = { + .dir = 1 + }, + + .ep_type = USB_EPTYPE_CTRL, + .max_len = USB_FS_EP0_MAX_LEN + }; + + usb_transc_active (udev, &udev->dev.transc_in[0]); + + /* upon reset call usr call back */ + udev->dev.cur_status = USBD_DEFAULT; + + return 1; +} + +/*! + \brief handle USB speed enumeration finish interrupt + \param[in] udev: pointer to usb device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_int_enumfinish (usb_core_driver *udev) +{ + uint8_t enum_speed = (uint8_t)((udev->regs.dr->DSTAT & DSTAT_ES) >> 1U); + + udev->regs.dr->DCTL &= ~DCTL_CGINAK; + udev->regs.dr->DCTL |= DCTL_CGINAK; + + udev->regs.gr->GUSBCS &= ~GUSBCS_UTT; + + /* set USB turn-around time based on device speed and PHY interface */ + if (USB_SPEED[enum_speed] == USB_SPEED_HIGH) { + udev->bp.core_speed = USB_SPEED_HIGH; + + udev->regs.gr->GUSBCS |= 0x09 << 10; + } else { + udev->bp.core_speed = USB_SPEED_FULL; + + udev->regs.gr->GUSBCS |= 0x05 << 10; + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_ENUMFIF; + + return 1; +} + +/*! + \brief USB suspend interrupt handler + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_suspend (usb_core_driver *udev) +{ + __IO uint8_t low_power = udev->bp.low_power; + __IO uint8_t suspend = (uint8_t)(udev->regs.dr->DSTAT & DSTAT_SPST); + __IO uint8_t is_configured = (udev->dev.cur_status == USBD_CONFIGURED)? 1U : 0U; + + udev->dev.backup_status = udev->dev.cur_status; + udev->dev.cur_status = USBD_SUSPENDED; + + if (low_power && suspend && is_configured) { + /* switch-off the otg clocks */ + *udev->regs.PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK; + + /* enter DEEP_SLEEP mode with LDO in low power mode */ + pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_SP; + + return 1U; +} + +/*! + \brief check FIFO for the next packet to be loaded + \param[in] udev: pointer to usb device instance + \param[in] ep_num: endpoint identifier which is in (0..3) + \param[out] none + \retval status +*/ +static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num) +{ + usb_transc *transc = NULL; + + uint32_t len = 0; + uint32_t word_count = 0; + + transc = &udev->dev.transc_in[ep_num]; + + len = transc->xfer_len - transc->xfer_count; + + /* get the data length to write */ + if (len > transc->max_len) { + len = transc->max_len; + } + + word_count = (len + 3) / 4; + + while (((udev->regs.er_in[ep_num]->DIEPTFSTAT & DIEPTFSTAT_IEPTFS) > word_count) && \ + (transc->xfer_count < transc->xfer_len)) { + len = transc->xfer_len - transc->xfer_count; + + if (len > transc->max_len) { + len = transc->max_len; + } + + /* write FIFO in word(4bytes) */ + word_count = (len + 3) / 4; + + /* write the FIFO */ + usb_txfifo_write (&udev->regs, transc->xfer_buf, ep_num, len); + + transc->xfer_buf += len; + transc->xfer_count += len; + + if (transc->xfer_count == transc->xfer_len) { + /* disable the device endpoint FIFO empty interrupt */ + udev->regs.dr->DIEPFEINTEN &= ~(0x01 << ep_num); + } + } + + return 1; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/drv_usbh_int.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/drv_usbh_int.c new file mode 100644 index 0000000..7b649a1 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/drv_usbh_int.c @@ -0,0 +1,536 @@ +/*! + \file drv_usbh_int.c + \brief USB host mode interrupt handler file + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "../Include/drv_usb_core.h" +#include "../Include/drv_usb_host.h" +#include "../Include/drv_usbh_int.h" + +#if defined (__GNUC__) /*!< GNU compiler */ + #pragma GCC optimize ("O0") +#endif /* __GNUC__ */ + +static uint32_t usbh_int_port (usb_core_driver *pudev); +static uint32_t usbh_int_pipe (usb_core_driver *pudev); +static uint32_t usbh_int_pipe_in (usb_core_driver *pudev, uint32_t pp_num); +static uint32_t usbh_int_pipe_out (usb_core_driver *pudev, uint32_t pp_num); +static uint32_t usbh_int_rxfifonoempty (usb_core_driver *pudev); +static uint32_t usbh_int_txfifoempty (usb_core_driver *pudev, usb_pipe_mode pp_mode); + +static inline void usb_pp_halt (usb_core_driver *pudev, + uint8_t pp_num, + uint32_t pp_int, + usb_pipe_staus pp_status) +{ + pudev->regs.pr[pp_num]->HCHINTEN |= HCHINTEN_CHIE; + + usb_pipe_halt(pudev, pp_num); + + pudev->regs.pr[pp_num]->HCHINTF = pp_int; + + pudev->host.pipe[pp_num].pp_status = pp_status; +} + +/*! + \brief handle global host interrupt + \param[in] pudev: pointer to usb core instance + \param[out] none + \retval operation status +*/ +uint32_t usbh_isr (usb_core_driver *pudev) +{ + uint32_t Retval = 0U; + + __IO uint32_t intr = 0U; + + /* check if host mode */ + if (HOST_MODE == (pudev->regs.gr->GINTF & GINTF_COPM)) { + intr = usb_coreintr_get(&pudev->regs); + + if (!intr) { + return 0; + } + + if (intr & GINTF_SOF) { + usbh_int_fop->SOF(pudev); + + /* clear interrupt */ + pudev->regs.gr->GINTF = GINTF_SOF; + } + + if (intr & GINTF_RXFNEIF) { + Retval |= usbh_int_rxfifonoempty (pudev); + } + + if (intr & GINTF_NPTXFEIF) { + Retval |= usbh_int_txfifoempty (pudev, PIPE_NON_PERIOD); + } + + if (intr & GINTF_PTXFEIF) { + Retval |= usbh_int_txfifoempty (pudev, PIPE_PERIOD); + } + + if (intr & GINTF_HCIF) { + Retval |= usbh_int_pipe (pudev); + } + + if (intr & GINTF_HPIF) { + Retval |= usbh_int_port (pudev); + } + + if (intr & GINTF_DISCIF) { + pudev->host.connect_status = 0U; + + /* clear interrupt */ + pudev->regs.gr->GINTF = GINTF_DISCIF; + } + + if (intr & GINTF_ISOONCIF) { + pudev->regs.pr[0]->HCHCTL |= HCHCTL_CEN | HCHCTL_CDIS; + + /* clear interrupt */ + pudev->regs.gr->GINTF = GINTF_ISOONCIF; + } + } + + return Retval; +} + +/*! + \brief handle all host channels interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_int_pipe (usb_core_driver *pudev) +{ + uint32_t pp_num = 0U; + uint32_t retval = 0U; + + for (pp_num = 0U; pp_num < pudev->bp.num_pipe; pp_num++) { + if ((pudev->regs.hr->HACHINT & HACHINT_HACHINT) & (1U << pp_num)) { + if (pudev->regs.pr[pp_num]->HCHCTL & HCHCTL_EPDIR) { + retval |= usbh_int_pipe_in (pudev, pp_num); + } else { + retval |= usbh_int_pipe_out (pudev, pp_num); + } + } + } + + return retval; +} + +/*! + \brief handle the TX FIFO empty interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_int_txfifoempty (usb_core_driver *pudev, usb_pipe_mode pp_mode) +{ + uint8_t pp_num = 0U; + uint16_t word_count = 0U, len = 0U; + __IO uint32_t *txfiforeg = 0U, txfifostate = 0U; + + if (PIPE_NON_PERIOD == pp_mode) { + txfiforeg = &pudev->regs.gr->HNPTFQSTAT; + } else if (PIPE_PERIOD == pp_mode) { + txfiforeg = &pudev->regs.hr->HPTFQSTAT; + } else { + return 0U; + } + + txfifostate = *txfiforeg; + + pp_num = (txfifostate & TFQSTAT_CNUM) >> 27U; + + word_count = (pudev->host.pipe[pp_num].xfer_len + 3U) / 4U; + + while (((txfifostate & TFQSTAT_TXFS) > word_count) && (0U != pudev->host.pipe[pp_num].xfer_len)) { + len = (txfifostate & TFQSTAT_TXFS) * 4U; + + if (len > pudev->host.pipe[pp_num].xfer_len) { + /* last packet */ + len = pudev->host.pipe[pp_num].xfer_len; + + if (PIPE_NON_PERIOD == pp_mode) { + pudev->regs.gr->GINTEN &= ~GINTEN_NPTXFEIE; + } else { + pudev->regs.gr->GINTEN &= ~GINTEN_PTXFEIE; + } + } + + word_count = (pudev->host.pipe[pp_num].xfer_len + 3U) / 4U; + usb_txfifo_write (&pudev->regs, pudev->host.pipe[pp_num].xfer_buf, pp_num, len); + + pudev->host.pipe[pp_num].xfer_buf += len; + pudev->host.pipe[pp_num].xfer_len -= len; + pudev->host.pipe[pp_num].xfer_count += len; + + txfifostate = *txfiforeg; + } + + return 1; +} + +/*! + \brief handle the host port interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_int_port (usb_core_driver *pudev) +{ + uint32_t retval = 0U; + + __IO uint32_t port_state = *pudev->regs.HPCS; + + /* clear the interrupt bits in GINTSTS */ + port_state &= ~(HPCS_PE | HPCS_PCD | HPCS_PEDC); + + /* port connect detected */ + if (*pudev->regs.HPCS & HPCS_PCD) { + port_state |= HPCS_PCD; + + pudev->host.connect_status = 1U; + + retval |= 1U; + } + + /* port enable changed */ + if (*pudev->regs.HPCS & HPCS_PEDC) { + port_state |= HPCS_PEDC; + + if (*pudev->regs.HPCS & HPCS_PE) { + uint32_t port_speed = usb_curspeed_get(pudev); + uint32_t clock_type = pudev->regs.hr->HCTL & HCTL_CLKSEL; + + pudev->host.connect_status = 1U; + + if (PORT_SPEED_LOW == port_speed) { + pudev->regs.hr->HFT = 6000U; + + if (HCTL_6MHZ != clock_type) { + if (USB_EMBEDDED_PHY == pudev->bp.phy_itf) { + usb_phyclock_config (pudev, HCTL_6MHZ); + } + } + } else if (PORT_SPEED_FULL == port_speed) { + pudev->regs.hr->HFT = 48000U; + + if (HCTL_48MHZ != clock_type) { + usb_phyclock_config (pudev, HCTL_48MHZ); + } + } else { + /* for high speed device and others */ + } + + pudev->host.port_enabled = 1U; + + pudev->regs.gr->GINTEN |= GINTEN_DISCIE; + } else { + pudev->host.port_enabled = 0U; + } + } + + /* clear port interrupts */ + *pudev->regs.HPCS = port_state; + + return retval; +} + +/*! + \brief handle the OUT channel interrupt + \param[in] pudev: pointer to usb device instance + \param[in] pp_num: host channel number which is in (0..7) + \param[out] none + \retval operation status +*/ +uint32_t usbh_int_pipe_out (usb_core_driver *pudev, uint32_t pp_num) +{ + usb_pr *pp_reg = pudev->regs.pr[pp_num]; + + usb_pipe *pp = &pudev->host.pipe[pp_num]; + + uint32_t intr_pp = pp_reg->HCHINTF & pp_reg->HCHINTEN; + + if (intr_pp & HCHINTF_ACK) { + pp_reg->HCHINTF = HCHINTF_ACK; + } else if (intr_pp & HCHINTF_STALL) { + usb_pp_halt (pudev, pp_num, HCHINTF_STALL, PIPE_STALL); + } else if (intr_pp & HCHINTF_DTER) { + usb_pp_halt (pudev, pp_num, HCHINTF_DTER, PIPE_DTGERR); + pp_reg->HCHINTF = HCHINTF_NAK; + } else if (intr_pp & HCHINTF_REQOVR) { + usb_pp_halt (pudev, pp_num, HCHINTF_REQOVR, PIPE_REQOVR); + } else if (intr_pp & HCHINTF_TF) { + pp->err_count = 0U; + usb_pp_halt (pudev, pp_num, HCHINTF_TF, PIPE_XF); + } else if (intr_pp & HCHINTF_NAK) { + pp->err_count = 0U; + usb_pp_halt (pudev, pp_num, HCHINTF_NAK, PIPE_NAK); + } else if (intr_pp & HCHINTF_USBER) { + pp->err_count++; + usb_pp_halt (pudev, pp_num, HCHINTF_USBER, PIPE_TRACERR); + } else if (intr_pp & HCHINTF_NYET) { + pp->err_count = 0U; + usb_pp_halt (pudev, pp_num, HCHINTF_NYET, PIPE_NYET); + } else if (intr_pp & HCHINTF_CH) { + pudev->regs.pr[pp_num]->HCHINTEN &= ~HCHINTEN_CHIE; + + switch (pp->pp_status) { + case PIPE_XF: + pp->urb_state = URB_DONE; + + if (USB_EPTYPE_BULK == ((pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U)) { + pp->data_toggle_out ^= 1U; + } + break; + + case PIPE_NAK: + pp->urb_state = URB_NOTREADY; + break; + + case PIPE_NYET: + if (1U == pudev->host.pipe[pp_num].ping) { + usb_pipe_ping (pudev, pp_num); + } + + pp->urb_state = URB_NOTREADY; + break; + + case PIPE_STALL: + pp->urb_state = URB_STALL; + break; + + case PIPE_TRACERR: + if (3U == pp->err_count) { + pp->urb_state = URB_ERROR; + pp->err_count = 0U; + } + break; + + default: + break; + } + + pp_reg->HCHINTF = HCHINTF_CH; + } + + return 1; +} + +/*! + \brief handle the IN channel interrupt + \param[in] pudev: pointer to usb device instance + \param[in] pp_num: host channel number which is in (0..7) + \param[out] none + \retval operation status +*/ +uint32_t usbh_int_pipe_in (usb_core_driver *pudev, uint32_t pp_num) +{ + usb_pr *pp_reg = pudev->regs.pr[pp_num]; + + usb_pipe *pp = &pudev->host.pipe[pp_num]; + + __IO uint32_t intr_pp = pp_reg->HCHINTF & pp_reg->HCHINTEN; + + uint8_t ep_type = (pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U; + + if (intr_pp & HCHINTF_ACK) { + pp_reg->HCHINTF = HCHINTF_ACK; + } else if (intr_pp & HCHINTF_STALL) { + usb_pp_halt (pudev, pp_num, HCHINTF_STALL, PIPE_STALL); + pp_reg->HCHINTF = HCHINTF_NAK; + + /* note: When there is a 'STALL', reset also nak, + else, the pudev->host.pp_status = HC_STALL + will be overwritten by 'NAK' in code below */ + intr_pp &= ~HCHINTF_NAK; + } else if (intr_pp & HCHINTF_DTER) { + usb_pp_halt (pudev, pp_num, HCHINTF_DTER, PIPE_DTGERR); + pp_reg->HCHINTF = HCHINTF_NAK; + } + + if (intr_pp & HCHINTF_REQOVR) { + usb_pp_halt (pudev, pp_num, HCHINTF_REQOVR, PIPE_REQOVR); + } else if (intr_pp & HCHINTF_TF) { + if (USB_USE_DMA == pudev->bp.transfer_mode) { + pudev->host.backup_xfercount[pp_num] = pp->xfer_len - pp_reg->HCHLEN & HCHLEN_TLEN; + } + + pp->pp_status = PIPE_XF; + pp->err_count = 0U; + + pp_reg->HCHINTF = HCHINTF_TF; + + switch (ep_type) { + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + usb_pp_halt (pudev, pp_num, HCHINTF_NAK, PIPE_XF); + + pp->data_toggle_in ^= 1U; + break; + + case USB_EPTYPE_INTR: + pp_reg->HCHCTL |= HCHCTL_ODDFRM; + pp->urb_state = URB_DONE; + break; + + default: + break; + } + } else if (intr_pp & HCHINTF_CH) { + pp_reg->HCHINTEN &= ~HCHINTEN_CHIE; + + switch (pp->pp_status) { + case PIPE_XF: + pp->urb_state = URB_DONE; + break; + + case PIPE_STALL: + pp->urb_state = URB_STALL; + break; + + case PIPE_TRACERR: + case PIPE_DTGERR: + pp->err_count = 0U; + pp->urb_state = URB_ERROR; + break; + + default: + if(USB_EPTYPE_INTR == ep_type) { + pp->data_toggle_in ^= 1U; + } + break; + } + + pp_reg->HCHINTF = HCHINTF_CH; + } else if (intr_pp & HCHINTF_BBER) { + pp->err_count++; + usb_pp_halt (pudev, pp_num, HCHINTF_BBER, PIPE_TRACERR); + } else if (intr_pp & HCHINTF_NAK) { + switch (ep_type) { + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + /* re-activate the channel */ + pp_reg->HCHCTL = (pp_reg->HCHCTL | HCHCTL_CEN) & ~HCHCTL_CDIS; + break; + + case USB_EPTYPE_INTR: + pp_reg->HCHINTEN |= HCHINTEN_CHIE; + + usb_pipe_halt(pudev, pp_num); + break; + + default: + break; + } + + pp->pp_status = PIPE_NAK; + + pp_reg->HCHINTF = HCHINTF_NAK; + } + + return 1; +} + +/*! + \brief handle the rx fifo non-empty interrupt + \param[in] pudev: pointer to usb device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_int_rxfifonoempty (usb_core_driver *pudev) +{ + uint32_t count = 0U; + + __IO uint8_t pp_num = 0U; + __IO uint32_t rx_stat = 0U; + + /* disable the rx status queue level interrupt */ + pudev->regs.gr->GINTEN &= ~GINTEN_RXFNEIE; + + rx_stat = pudev->regs.gr->GRSTATP; + pp_num = rx_stat & GRSTATRP_CNUM; + + switch ((rx_stat & GRSTATRP_RPCKST) >> 17U) { + case GRXSTS_PKTSTS_IN: + count = (rx_stat & GRSTATRP_BCOUNT) >> 4U; + + /* read the data into the host buffer. */ + if ((count > 0U) && (NULL != pudev->host.pipe[pp_num].xfer_buf)) { + usb_rxfifo_read (&pudev->regs, pudev->host.pipe[pp_num].xfer_buf, count); + + /* manage multiple transfer packet */ + pudev->host.pipe[pp_num].xfer_buf += count; + pudev->host.pipe[pp_num].xfer_count += count; + + pudev->host.backup_xfercount[pp_num] = pudev->host.pipe[pp_num].xfer_count; + + if (pudev->regs.pr[pp_num]->HCHLEN & HCHLEN_PCNT) { + /* re-activate the channel when more packets are expected */ + __IO uint32_t pp_ctl = pudev->regs.pr[pp_num]->HCHCTL; + + pp_ctl |= HCHCTL_CEN; + pp_ctl &= ~HCHCTL_CDIS; + + pudev->regs.pr[pp_num]->HCHCTL = pp_ctl; + } + } + break; + + case GRXSTS_PKTSTS_IN_XFER_COMP: + break; + + case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: + count = (rx_stat & GRSTATRP_BCOUNT) >> 4U; + + while (count > 0U) { + rx_stat = pudev->regs.gr->GRSTATP; + count--; + } + break; + + case GRXSTS_PKTSTS_CH_HALTED: + break; + + default: + break; + } + + /* enable the rx status queue level interrupt */ + pudev->regs.gr->GINTEN |= GINTEN_RXFNEIE; + + return 1; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbd_core.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbd_core.c new file mode 100644 index 0000000..d7a8eae --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbd_core.c @@ -0,0 +1,329 @@ +/*! + \file usbd_core.c + \brief USB device mode core functions + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "../Include/usbd_core.h" +#include "../Include/drv_usb_hw.h" + +/* endpoint type */ +const uint32_t ep_type[] = { + [USB_EP_ATTR_CTL] = USB_EPTYPE_CTRL, + [USB_EP_ATTR_BULK] = USB_EPTYPE_BULK, + [USB_EP_ATTR_INT] = USB_EPTYPE_INTR, + [USB_EP_ATTR_ISO] = USB_EPTYPE_ISOC +}; + +/*! + \brief initailizes the USB device-mode stack and load the class driver + \param[in] udev: pointer to USB core instance + \param[in] core: usb core type + \param[in] class_core: class driver + \param[out] none + \retval none +*/ +void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_class_core *class_core) +{ + /* device descriptor, class and user callbacks */ + udev->dev.class_core = class_core; + + /* configure USB capabilites */ + usb_basic_init (&udev->bp, &udev->regs, core); + + /* initailizes the USB core*/ + usb_core_init (udev->bp, &udev->regs); + + /* set device disconnect */ + usbd_disconnect (udev); + + /* initailizes device mode */ + usb_devcore_init (udev); + + /* set device connect */ + usbd_connect (udev); + + udev->dev.cur_status = USBD_DEFAULT; +} + +/*! + \brief endpoint initialization + \param[in] udev: pointer to USB core instance + \param[in] ep_desc: pointer to endpoint descriptor + \param[out] none + \retval none +*/ +uint32_t usbd_ep_setup (usb_core_driver *udev, const usb_desc_ep *ep_desc) +{ + usb_transc *transc; + + uint8_t ep_addr = ep_desc->bEndpointAddress; + uint8_t max_len = ep_desc->wMaxPacketSize; + + /* set endpoint direction */ + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + + transc->ep_addr.dir = 1U; + } else { + transc = &udev->dev.transc_out[ep_addr]; + + transc->ep_addr.dir = 0U; + } + + transc->ep_addr.num = EP_ID(ep_addr); + transc->max_len = max_len; + transc->ep_type = ep_type[ep_desc->bmAttributes & USB_EPTYPE_MASK]; + + /* active USB endpoint function */ + usb_transc_active (udev, transc); + + return 0; +} + +/*! + \brief configure the endpoint when it is disabled + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_clear (usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc; + + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + /* deactive USB endpoint function */ + usb_transc_deactivate (udev, transc); + + return 0; +} + + +/*! + \brief endpoint prepare to receive data + \param[in] udev: pointer to usb core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[in] pbuf: user buffer address pointer + \param[in] len: buffer length + \param[out] none + \retval none +*/ +uint32_t usbd_ep_recev (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len) +{ + usb_transc *transc = &udev->dev.transc_out[EP_ID(ep_addr)]; + + /* setup the transfer */ + transc->xfer_buf = pbuf; + transc->xfer_len = len; + transc->xfer_count = 0; + + if (USB_USE_DMA == udev->bp.transfer_mode) { + transc->dma_addr = (uint32_t)pbuf; + } + + /* start the transfer */ + usb_transc_outxfer (udev, transc); + + return 0; +} + +/*! + \brief endpoint prepare to transmit data + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[in] pbuf: transmit buffer address pointer + \param[in] len: buffer length + \param[out] none + \retval none +*/ +uint32_t usbd_ep_send (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len) +{ + usb_transc *transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + + /* setup the transfer */ + transc->xfer_buf = pbuf; + transc->xfer_len = len; + transc->xfer_count = 0; + + if (USB_USE_DMA == udev->bp.transfer_mode) { + transc->dma_addr = (uint32_t)pbuf; + } + + /* start the transfer */ + usb_transc_inxfer (udev, transc); + + return 0; +} + +/*! + \brief set an endpoint to STALL status + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_stall (usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc = NULL; + + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + transc->ep_stall = 1; + + usb_transc_stall (udev, transc); + + return (0); +} + +/*! + \brief clear endpoint STALLed status + \param[in] udev: pointer to usb core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_stall_clear (usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc = NULL; + + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + transc->ep_stall = 0; + + usb_transc_clrstall (udev, transc); + + return (0); +} + +/*! + \brief flush the endpoint FIFOs + \param[in] udev: pointer to usb core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_fifo_flush (usb_core_driver *udev, uint8_t ep_addr) +{ + if (EP_DIR(ep_addr)) { + usb_txfifo_flush (&udev->regs, EP_ID(ep_addr)); + } else { + usb_rxfifo_flush (&udev->regs); + } + + return (0); +} + +/*! + \brief set USB device address + \param[in] udev: pointer to USB core instance + \param[in] addr: device address to set + \param[out] none + \retval none +*/ +void usbd_addr_set (usb_core_driver *udev, uint8_t addr) +{ + usb_devaddr_set(udev, addr); +} + +/*! + \brief get the received data length + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval USB device operation cur_status +*/ +uint16_t usbd_rxcount_get (usb_core_driver *udev, uint8_t ep_num) +{ + return udev->dev.transc_out[ep_num].xfer_count; +} + +/*! + \brief device connect + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void usbd_connect (usb_core_driver *udev) +{ +#ifndef USE_OTG_MODE + /* connect device */ + usb_dev_connect (udev); + usb_mdelay(3); + +#endif /* USE_OTG_MODE */ +} + +/*! + \brief device disconnect + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void usbd_disconnect (usb_core_driver *udev) +{ +#ifndef USE_OTG_MODE + /* disconnect device for 3ms */ + usb_dev_disconnect (udev); + usb_mdelay(3); +#endif /* USE_OTG_MODE */ +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbd_enum.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbd_enum.c new file mode 100644 index 0000000..41990a0 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbd_enum.c @@ -0,0 +1,696 @@ +/*! + \file usbd_enum.c + \brief USB enumeration function + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "../Include/usbd_enum.h" +#include "../Include/usb_ch9_std.h" + +static usb_reqsta _usb_std_getstatus (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setaddress (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setconfiguration (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_getconfiguration (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_getdescriptor (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setfeature (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_clearfeature (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_reserved (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setdescriptor (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_getinterface (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setinterface (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_synchframe (usb_core_driver *udev, usb_req *req); + +static uint8_t* _usb_dev_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +static uint8_t* _usb_config_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +static uint8_t* _usb_str_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +static uint8_t* _usb_bos_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); + +static usb_reqsta (*_std_dev_req[])(usb_core_driver *udev, usb_req *req) = +{ + [USB_GET_STATUS] = _usb_std_getstatus, + [USB_CLEAR_FEATURE] = _usb_std_clearfeature, + [USB_RESERVED2] = _usb_std_reserved, + [USB_SET_FEATURE] = _usb_std_setfeature, + [USB_RESERVED4] = _usb_std_reserved, + [USB_SET_ADDRESS] = _usb_std_setaddress, + [USB_GET_DESCRIPTOR] = _usb_std_getdescriptor, + [USB_SET_DESCRIPTOR] = _usb_std_setdescriptor, + [USB_GET_CONFIGURATION] = _usb_std_getconfiguration, + [USB_SET_CONFIGURATION] = _usb_std_setconfiguration, + [USB_GET_INTERFACE] = _usb_std_getinterface, + [USB_SET_INTERFACE] = _usb_std_setinterface, + [USB_SYNCH_FRAME] = _usb_std_synchframe, +}; + +/* get standard descriptor handler */ +static uint8_t* (*std_desc_get[])(usb_core_driver *udev, uint8_t index, uint16_t *len) = { + [USB_DESCTYPE_DEV - 1] = _usb_dev_desc_get, + [USB_DESCTYPE_CONFIG - 1] = _usb_config_desc_get, + [USB_DESCTYPE_STR - 1] = _usb_str_desc_get +}; + +/*! + \brief handle USB standard device request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +usb_reqsta usbd_standard_request (usb_core_driver *udev, usb_req *req) +{ + return (*_std_dev_req[req->bRequest])(udev, req); +} + +/*! + \brief handle USB device class request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device class request + \param[out] none + \retval USB device request status +*/ +usb_reqsta usbd_class_request (usb_core_driver *udev, usb_req *req) +{ + if (USBD_CONFIGURED == udev->dev.cur_status) { + if (BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) { + /* call device class handle function */ + return (usb_reqsta)udev->dev.class_core->req_proc(udev, req); + } + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB vendor request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB vendor request + \param[out] none + \retval USB device request status +*/ +usb_reqsta usbd_vendor_request (usb_core_driver *udev, usb_req *req) +{ + /* added by user... */ + + return REQ_SUPP; +} + +/*! + \brief no operation, just for reserved + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB vendor request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_reserved (usb_core_driver *udev, usb_req *req) +{ + /* no operation... */ + + return REQ_NOTSUPP; +} + +/*! + \brief get the device descriptor + \param[in] udev: pointer to USB device instance + \param[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_dev_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + *len = udev->dev.desc.dev_desc[0]; + + return udev->dev.desc.dev_desc; +} + +/*! + \brief get the configuration descriptor + \brief[in] udev: pointer to USB device instance + \brief[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_config_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + *len = udev->dev.desc.config_desc[2]; + + return udev->dev.desc.config_desc; +} + +/*! + \brief get the BOS descriptor + \brief[in] udev: pointer to USB device instance + \brief[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_bos_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + *len = udev->dev.desc.bos_desc[2]; + + return udev->dev.desc.bos_desc; +} + +/*! + \brief get string descriptor + \param[in] udev: pointer to USB device instance + \param[in] index: string descriptor index + \param[out] len: pointer to string length + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_str_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + uint8_t *desc = udev->dev.desc.strings[index]; + + *len = desc[0]; + + return desc; +} + +/*! + \brief handle Get_Status request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getstatus (usb_core_driver *udev, usb_req *req) +{ + uint8_t recp = BYTE_LOW(req->wIndex); + + usb_transc *transc = &udev->dev.transc_in[0]; + + static uint8_t status[2] = {0}; + + switch(req->bmRequestType & USB_RECPTYPE_MASK) { + case USB_RECPTYPE_DEV: + if ((USBD_ADDRESSED == udev->dev.cur_status) || \ + (USBD_CONFIGURED == udev->dev.cur_status)) { + + if (udev->dev.pm.power_mode) { + status[0] = USB_STATUS_SELF_POWERED; + } else { + status[0] = 0U; + } + + if (udev->dev.pm.dev_remote_wakeup) { + status[0] |= USB_STATUS_REMOTE_WAKEUP; + } else { + status[0] = 0U; + } + + transc->xfer_buf = status; + transc->remain_len = 2U; + + return REQ_SUPP; + } + break; + + case USB_RECPTYPE_ITF: + if ((USBD_CONFIGURED == udev->dev.cur_status) && (recp <= USBD_ITF_MAX_NUM)) { + transc->xfer_buf = status; + transc->remain_len = 2U; + + return REQ_SUPP; + } + break; + + case USB_RECPTYPE_EP: + if (USBD_CONFIGURED == udev->dev.cur_status) { + if (0x80U == (recp & 0x80U)) { + status[0] = udev->dev.transc_in[EP_ID(recp)].ep_stall; + } else { + status[0] = udev->dev.transc_out[recp].ep_stall; + } + + transc->xfer_buf = status; + transc->remain_len = 2U; + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Clear_Feature request + \param[in] udev: pointer to USB device instance + \param[in] req: USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_clearfeature (usb_core_driver *udev, usb_req *req) +{ + uint8_t ep = 0; + + switch(req->bmRequestType & USB_RECPTYPE_MASK) + { + case USB_RECPTYPE_DEV: + if ((USBD_ADDRESSED == udev->dev.cur_status) || \ + (USBD_CONFIGURED == udev->dev.cur_status)) { + + /* clear device remote wakeup feature */ + if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { + udev->dev.pm.dev_remote_wakeup = 0U; + + return REQ_SUPP; + } + } + break; + + case USB_RECPTYPE_ITF: + break; + + case USB_RECPTYPE_EP: + /* get endpoint address */ + ep = BYTE_LOW(req->wIndex); + + if (USBD_CONFIGURED == udev->dev.cur_status) { + /* clear endpoint halt feature */ + if ((USB_FEATURE_EP_HALT == req->wValue) && (!CTL_EP(ep))) { + usbd_ep_stall_clear (udev, ep); + + udev->dev.class_core->req_proc (udev, req); + } + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Set_Feature request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setfeature (usb_core_driver *udev, usb_req *req) +{ + uint8_t ep = 0; + + switch(req->bmRequestType & USB_RECPTYPE_MASK) + { + case USB_RECPTYPE_DEV: + if ((USBD_ADDRESSED == udev->dev.cur_status) || \ + (USBD_CONFIGURED == udev->dev.cur_status)) { + /* set device remote wakeup feature */ + if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { + udev->dev.pm.dev_remote_wakeup = 1U; + } + + return REQ_SUPP; + } + break; + + case USB_RECPTYPE_ITF: + break; + + case USB_RECPTYPE_EP: + /* get endpoint address */ + ep = BYTE_LOW(req->wIndex); + + if (USBD_CONFIGURED == udev->dev.cur_status) { + /* set endpoint halt feature */ + if ((USB_FEATURE_EP_HALT == req->wValue) && (!CTL_EP(ep))) { + usbd_ep_stall (udev, ep); + } + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Set_Address request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setaddress (usb_core_driver *udev, usb_req *req) +{ + if ((0U == req->wIndex) && (0U == req->wLength)) { + udev->dev.dev_addr = (uint8_t)(req->wValue) & 0x7FU; + + if (udev->dev.cur_status != USBD_CONFIGURED) { + usbd_addr_set (udev, udev->dev.dev_addr); + + if (udev->dev.dev_addr) { + udev->dev.cur_status = USBD_ADDRESSED; + } else { + udev->dev.cur_status = USBD_DEFAULT; + } + + return REQ_SUPP; + } + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Get_Descriptor request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getdescriptor (usb_core_driver *udev, usb_req *req) +{ + uint8_t desc_type = 0; + uint8_t desc_index = 0; + + usb_transc *transc = &udev->dev.transc_in[0]; + + /* get device standard descriptor */ + switch (req->bmRequestType & USB_RECPTYPE_MASK) { + case USB_RECPTYPE_DEV: + desc_type = BYTE_HIGH(req->wValue); + desc_index = BYTE_LOW(req->wValue); + + switch (desc_type) { + case USB_DESCTYPE_DEV: + transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *)&(transc->remain_len)); + + if (64U == req->wLength) { + transc->remain_len = 8U; + } + break; + + case USB_DESCTYPE_CONFIG: + transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *)&(transc->remain_len)); + break; + + case USB_DESCTYPE_STR: + if (desc_index < STR_IDX_MAX) { + transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *)&(transc->remain_len)); + } + break; + + case USB_DESCTYPE_ITF: + case USB_DESCTYPE_EP: + case USB_DESCTYPE_DEV_QUALIFIER: + case USB_DESCTYPE_OTHER_SPD_CONFIG: + case USB_DESCTYPE_ITF_POWER: + break; + + case USB_DESCTYPE_BOS: + transc->xfer_buf = _usb_bos_desc_get(udev, desc_index, (uint16_t *)&(transc->remain_len)); + break; + + default: + break; + } + break; + + case USB_RECPTYPE_ITF: + /* get device class special descriptor */ + return (usb_reqsta)(udev->dev.class_core->req_proc(udev, req)); + + case USB_RECPTYPE_EP: + break; + + default: + break; + } + + if ((0U != transc->remain_len) && (0U != req->wLength)) { + if (transc->remain_len < req->wLength) { + if ((transc->remain_len >= transc->max_len) && (0U == (transc->remain_len % transc->max_len))) { + udev->dev.control.ctl_zlp = 1; + } + } else { + transc->remain_len = req->wLength; + } + + return REQ_SUPP; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Set_Descriptor request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setdescriptor (usb_core_driver *udev, usb_req *req) +{ + /* no handle... */ + return REQ_SUPP; +} + +/*! + \brief handle USB Get_Configuration request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getconfiguration (usb_core_driver *udev, usb_req *req) +{ + usb_transc *transc = &udev->dev.transc_in[0]; + + switch (udev->dev.cur_status) { + case USBD_ADDRESSED: + if (USB_DEFAULT_CONFIG == udev->dev.config) { + transc->xfer_buf = &(udev->dev.config); + transc->remain_len = 1U; + + return REQ_SUPP; + } + break; + + case USBD_CONFIGURED: + if (udev->dev.config != USB_DEFAULT_CONFIG) { + transc->xfer_buf = &(udev->dev.config); + transc->remain_len = 1U; + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Set_Configuration request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setconfiguration (usb_core_driver *udev, usb_req *req) +{ + static uint8_t config; + + config = (uint8_t)(req->wValue); + + if (config <= USBD_CFG_MAX_NUM) { + switch (udev->dev.cur_status) { + case USBD_ADDRESSED: + if (config){ + udev->dev.class_core->init(udev, config); + + udev->dev.config = config; + udev->dev.cur_status = USBD_CONFIGURED; + } + + return REQ_SUPP; + + case USBD_CONFIGURED: + if (USB_DEFAULT_CONFIG == config) { + udev->dev.class_core->deinit(udev, config); + + udev->dev.config = config; + udev->dev.cur_status = USBD_ADDRESSED; + } else if (config != udev->dev.config) { + /* clear old configuration */ + udev->dev.class_core->deinit(udev, config); + + /* set new configuration */ + udev->dev.config = config; + udev->dev.class_core->init(udev, config); + } + + return REQ_SUPP; + + case USBD_DEFAULT: + break; + + default: + break; + } + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Get_Interface request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getinterface (usb_core_driver *udev, usb_req *req) +{ + switch (udev->dev.cur_status) { + case USBD_DEFAULT: + break; + + case USBD_ADDRESSED: + break; + + case USBD_CONFIGURED: + if (BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) { + usb_transc *transc = &udev->dev.transc_in[0]; + + transc->xfer_buf = &(udev->dev.class_core->alter_set); + transc->remain_len = 1U; + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Set_Interface request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setinterface (usb_core_driver *udev, usb_req *req) +{ + switch (udev->dev.cur_status) { + case USBD_DEFAULT: + break; + + case USBD_ADDRESSED: + break; + + case USBD_CONFIGURED: + if (BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) { + udev->dev.class_core->alter_set = req->wValue; + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB SynchFrame request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_synchframe (usb_core_driver *udev, usb_req *req) +{ + /* no handle... */ + return REQ_SUPP; +} + +/*! + \brief handle USB enumeration error + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +void usbd_enum_error (usb_core_driver *udev, usb_req *req) +{ + usbd_ep_stall (udev, 0x80); + usbd_ep_stall (udev, 0x00); + + usb_ctlep_startout(udev); +} + +/*! + \brief convert hex 32bits value into unicode char + \param[in] value: hex 32bits value + \param[in] pbuf: buffer pointer to store unicode char + \param[in] len: value length + \param[out] none + \retval none +*/ +void int_to_unicode (uint32_t value, uint8_t *pbuf, uint8_t len) +{ + uint8_t index = 0; + + for (index = 0; index < len; index++) { + if ((value >> 28) < 0x0A) { + pbuf[2 * index] = (value >> 28) + '0'; + } else { + pbuf[2 * index] = (value >> 28) + 'A' - 10; + } + + value = value << 4; + + pbuf[2 * index + 1] = 0; + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbd_transc.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbd_transc.c new file mode 100644 index 0000000..764b25b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbd_transc.c @@ -0,0 +1,254 @@ +/*! + \file usbd_transc.c + \brief USB transaction core functions + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "../Include/usbd_enum.h" +#include "../Include/usbd_transc.h" + +/*! + \brief USB send data in the control transaction + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_send (usb_core_driver *udev) +{ + usb_transc *transc = &udev->dev.transc_in[0]; + + usbd_ep_send(udev, 0U, transc->xfer_buf, transc->remain_len); + + if (transc->remain_len > transc->max_len) { + udev->dev.control.ctl_state = USB_CTL_DATA_IN; + } else { + udev->dev.control.ctl_state = USB_CTL_LAST_DATA_IN; + } + + return USBD_OK; +} + +/*! + \brief USB receive data in control transaction + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_recev (usb_core_driver *udev) +{ + usb_transc *transc = &udev->dev.transc_out[0]; + + usbd_ep_recev (udev, 0U, transc->xfer_buf, transc->remain_len); + + if (transc->remain_len > transc->max_len) { + udev->dev.control.ctl_state = USB_CTL_DATA_OUT; + } else { + udev->dev.control.ctl_state = USB_CTL_LAST_DATA_OUT; + } + + return USBD_OK; +} + +/*! + \brief USB send control transaction status + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_status_send (usb_core_driver *udev) +{ + udev->dev.control.ctl_state = USB_CTL_STATUS_IN; + + usbd_ep_send (udev, 0U, NULL, 0U); + + usb_ctlep_startout(udev); + + return USBD_OK; +} + +/*! + \brief USB control receive status + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_status_recev (usb_core_driver *udev) +{ + udev->dev.control.ctl_state = USB_CTL_STATUS_OUT; + + usbd_ep_recev (udev, 0, NULL, 0); + + usb_ctlep_startout(udev); + + return USBD_OK; +} + +/*! + \brief USB setup stage processing + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +uint8_t usbd_setup_transc (usb_core_driver *udev) +{ + usb_reqsta reqstat = REQ_NOTSUPP; + + usb_req req = udev->dev.control.req; + + switch (req.bmRequestType & USB_REQTYPE_MASK) { + /* standard device request */ + case USB_REQTYPE_STRD: + reqstat = usbd_standard_request (udev, &req); + break; + + /* device class request */ + case USB_REQTYPE_CLASS: + reqstat = usbd_class_request (udev, &req); + break; + + /* vendor defined request */ + case USB_REQTYPE_VENDOR: + reqstat = usbd_vendor_request (udev, &req); + break; + + default: + break; + } + + if (REQ_SUPP == reqstat) { + if (req.wLength == 0) { + usbd_ctl_status_send (udev); + } else { + if (req.bmRequestType & 0x80) { + usbd_ctl_send (udev); + } else { + usbd_ctl_recev (udev); + } + } + } else { + usbd_enum_error (udev, &req); + } + + return USBD_OK; +} + +/*! + \brief data out stage processing + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier(0..7) + \param[out] none + \retval USB device operation cur_status +*/ +uint8_t usbd_out_transc (usb_core_driver *udev, uint8_t ep_num) +{ + if (ep_num == 0) { + usb_transc *transc = &udev->dev.transc_out[0]; + + switch (udev->dev.control.ctl_state) { + case USB_CTL_DATA_OUT: + /* update transfer length */ + transc->remain_len -= transc->max_len; + + usbd_ctl_recev (udev); + break; + + case USB_CTL_LAST_DATA_OUT: + if (udev->dev.cur_status == USBD_CONFIGURED) { + if (udev->dev.class_core->data_out != NULL) { + udev->dev.class_core->data_out (udev, 0U); + } + } + + transc->remain_len = 0U; + + usbd_ctl_status_send (udev); + break; + + default: + break; + } + } else if ((udev->dev.class_core->data_out != NULL) && (udev->dev.cur_status == USBD_CONFIGURED)) { + udev->dev.class_core->data_out (udev, ep_num); + } + + return USBD_OK; +} + +/*! + \brief data in stage processing + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier(0..7) + \param[out] none + \retval USB device operation cur_status +*/ +uint8_t usbd_in_transc (usb_core_driver *udev, uint8_t ep_num) +{ + if (0U == ep_num) { + usb_transc *transc = &udev->dev.transc_in[0]; + + switch (udev->dev.control.ctl_state) { + case USB_CTL_DATA_IN: + /* update transfer length */ + transc->remain_len -= transc->max_len; + + usbd_ctl_send (udev); + break; + + case USB_CTL_LAST_DATA_IN: + /* last packet is MPS multiple, so send ZLP packet */ + if (udev->dev.control.ctl_zlp) { + usbd_ep_send (udev, 0U, NULL, 0U); + + udev->dev.control.ctl_zlp = 0U; + } else { + if (udev->dev.cur_status == USBD_CONFIGURED) { + if (udev->dev.class_core->data_in != NULL) { + udev->dev.class_core->data_in (udev, 0U); + } + } + + transc->remain_len = 0U; + + usbd_ctl_status_recev (udev); + } + break; + + default: + break; + } + } else { + if ((udev->dev.cur_status == USBD_CONFIGURED) && (udev->dev.class_core->data_in != NULL)) { + udev->dev.class_core->data_in (udev, ep_num); + } + } + + return USBD_OK; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbh_core.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbh_core.c new file mode 100644 index 0000000..a17cfb0 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbh_core.c @@ -0,0 +1,441 @@ +/*! + \file usbh_core.c + \brief USB host core state machine driver + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "../Include/drv_usb_hw.h" +#include "../Include/usbh_pipe.h" +#include "../Include/usbh_enum.h" +#include "../Include/usbh_core.h" +#include "../Include/drv_usbh_int.h" + +uint8_t usbh_sof (usb_core_driver *pudev); + +usbh_int_cb usbh_int_op = +{ + usbh_sof +}; + +usbh_int_cb *usbh_int_fop = &usbh_int_op; + +static usbh_status usbh_enum_task (usb_core_driver *pudev, usbh_host *puhost); + +/*! + \brief USB SOF callback function from the interrupt + \param[in] pudev: pointer to usb core instance + \param[out] none + \retval operation status +*/ +uint8_t usbh_sof (usb_core_driver *pudev) +{ + /* this callback could be used to implement a scheduler process */ + return 0U; +} + +/*! + \brief USB host stack initializations + \param[in] pudev: pointer to usb core instance + \param[in] core: USBFS core or USBHS core + \param[in] puhost: pointer to USB host + \param[out] none + \retval operation status +*/ +void usbh_init (usb_core_driver *pudev, usb_core_enum core, usbh_host *puhost) +{ + uint8_t i = 0U; + + /* host de-initializations */ + usbh_deinit(pudev, puhost); + + pudev->host.connect_status = 0U; + + for (i = 0U; i < USBFS_MAX_TX_FIFOS; i++) { + pudev->host.pipe[i].err_count = 0U; + pudev->host.pipe[i].pp_status = PIPE_IDLE; + pudev->host.backup_xfercount[i] = 0U; + } + + pudev->host.pipe[0].ep.mps = 8U; + + usb_basic_init (&pudev->bp, &pudev->regs, core); + +#ifndef DUAL_ROLE_MODE_ENABLED + + usb_core_init (pudev->bp, &pudev->regs); + + usb_host_init (pudev); + +#endif /* DUAL_ROLE_MODE_ENABLED */ + + /* upon init call usr call back */ + puhost->usr_cb->dev_init(); +} + +/*! + \brief de-initialize USB host + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to USB host + \param[out] none + \retval operation status +*/ +usbh_status usbh_deinit(usb_core_driver *pudev, usbh_host *puhost) +{ + /* software init */ + puhost->cur_state = HOST_DEFAULT; + puhost->backup_state = HOST_DEFAULT; + puhost->enum_state = ENUM_DEFAULT; + + puhost->control.ctl_state = CTL_IDLE; + puhost->control.max_len = USB_FS_EP0_MAX_LEN; + + puhost->dev_prop.addr = USBH_DEV_ADDR_DEFAULT; + puhost->dev_prop.speed = PORT_SPEED_FULL; + + usbh_pipe_free(pudev, puhost->control.pipe_in_num); + usbh_pipe_free(pudev, puhost->control.pipe_out_num); + + return USBH_OK; +} + +/*! + \brief USB host core main state machine process + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to USB host + \param[out] none + \retval none +*/ +void usbh_core_task (usb_core_driver *pudev, usbh_host *puhost) +{ + volatile usbh_status status = USBH_FAIL; + + /* check for host port events */ + if (((0U == pudev->host.connect_status) || (0U == pudev->host.port_enabled)) && (HOST_DEFAULT != puhost->cur_state)) { + if (puhost->cur_state != HOST_DEV_DETACHED) { + puhost->cur_state = HOST_DEV_DETACHED; + } + } + + switch (puhost->cur_state) { + case HOST_DEFAULT: + if (pudev->host.connect_status) { + puhost->cur_state = HOST_DETECT_DEV_SPEED; + + usb_mdelay (100U); + // usb_mdelay (2U); + usb_port_reset (pudev); + + puhost->usr_cb->dev_reset(); + } + break; + + case HOST_DETECT_DEV_SPEED: + if (pudev->host.port_enabled) { + puhost->cur_state = HOST_DEV_ATTACHED; + puhost->dev_prop.speed = usb_curspeed_get (pudev); + puhost->usr_cb->dev_speed_detected(puhost->dev_prop.speed); + + usb_mdelay (50U); + } + break; + + case HOST_DEV_ATTACHED: + puhost->usr_cb->dev_attach(); + puhost->control.pipe_out_num = usbh_pipe_allocate(pudev, 0x00U); + puhost->control.pipe_in_num = usbh_pipe_allocate(pudev, 0x80U); + + /* reset USB device */ + usb_port_reset (pudev); + + /* open IN control pipe */ + usbh_pipe_create (pudev, + &puhost->dev_prop, + puhost->control.pipe_in_num, + USB_EPTYPE_CTRL, + puhost->control.max_len); + + /* open OUT control pipe */ + usbh_pipe_create (pudev, + &puhost->dev_prop, + puhost->control.pipe_out_num, + USB_EPTYPE_CTRL, + puhost->control.max_len); + + puhost->cur_state = HOST_ENUM; + break; + + case HOST_ENUM: + + /* check for enumeration status */ + if (USBH_OK == usbh_enum_task (pudev, puhost)) { + /* the function shall return USBH_OK when full enumeration is complete */ + + /* user callback for end of device basic enumeration */ + puhost->usr_cb->dev_enumerated(); + puhost->cur_state = HOST_USER_INPUT; + } + break; + + case HOST_USER_INPUT: + /* the function should return user response true to move to class state */ + if (USBH_USER_RESP_OK == puhost->usr_cb->dev_user_input()) { + if ((USBH_OK == puhost->class_cb->class_init(pudev, puhost))) { + puhost->cur_state = HOST_CLASS_ENUM; + } + } + break; + + case HOST_CLASS_ENUM: + /* process class standard contol requests state machine */ + status = puhost->class_cb->class_requests(pudev, puhost); + + if (USBH_OK == status) { + puhost->cur_state = HOST_CLASS_HANDLER; + } else { + usbh_error_handler (puhost, status); + } + break; + + case HOST_CLASS_HANDLER: + /* process class state machine */ + status = puhost->class_cb->class_machine(pudev, puhost); + + usbh_error_handler (puhost, status); + break; + + case HOST_SUSPENDED: + break; + + case HOST_ERROR: + /* re-initilaize host for new enumeration */ + usbh_deinit (pudev, puhost); + puhost->usr_cb->dev_deinit(); + puhost->class_cb->class_deinit(pudev, puhost); + break; + + case HOST_DEV_DETACHED: + /* manage user disconnect operations*/ + puhost->usr_cb->dev_detach(); + + /* re-initilaize host for new enumeration */ + usbh_deinit(pudev, puhost); + puhost->usr_cb->dev_deinit(); + puhost->class_cb->class_deinit(pudev, puhost); + usbh_pipe_delete(pudev); + puhost->cur_state = HOST_DEFAULT; + break; + + default: + break; + } +} + +/*! + \brief handle the error on USB host side + \param[in] puhost: pointer to USB host + \param[in] err_type: type of error or busy/OK state + \param[out] none + \retval none +*/ +void usbh_error_handler (usbh_host *puhost, usbh_status err_type) +{ + /* error unrecovered or not supported device speed */ + if ((USBH_SPEED_UNKNOWN_ERROR == err_type) || (USBH_UNRECOVERED_ERROR == err_type)) { + puhost->usr_cb->dev_error(); + + puhost->cur_state = HOST_ERROR; + } else if (USBH_APPLY_DEINIT == err_type) { + puhost->cur_state = HOST_ERROR; + + /* user callback for initalization */ + puhost->usr_cb->dev_init(); + } +} + +/*! + \brief handle the USB enumeration task + \param[in] pudev: pointer to selected USB device + \param[in] puhost: pointer to host + \param[out] none + \retval none +*/ +static usbh_status usbh_enum_task (usb_core_driver *pudev, usbh_host *puhost) +{ + uint8_t str_buf[64]; + + usbh_status status = USBH_BUSY; + + static uint8_t index_mfc_str = 0U, index_prod_str = 0U, index_serial_str = 0U; + + switch (puhost->enum_state) { + case ENUM_DEFAULT: + /* get device descriptor for only 1st 8 bytes : to get ep0 maxpacketsize */ + if (USBH_OK == usbh_devdesc_get (pudev, puhost, 8U)) { + + puhost->control.max_len = puhost->dev_prop.dev_desc.bMaxPacketSize0; + + /* issue reset */ + usb_port_reset (pudev); + + /* modify control channels configuration for maximum packet size */ + usbh_pipe_update (pudev, + puhost->control.pipe_out_num, + 0U, 0U, + puhost->control.max_len); + + usbh_pipe_update (pudev, + puhost->control.pipe_in_num, + 0U, 0U, + puhost->control.max_len); + + puhost->enum_state = ENUM_GET_DEV_DESC; + + } + break; + + case ENUM_GET_DEV_DESC: + /* get full device descriptor */ + if (USBH_OK == usbh_devdesc_get (pudev, puhost, USB_DEV_DESC_LEN)) { + puhost->usr_cb->dev_devdesc_assigned(&puhost->dev_prop.dev_desc); + + index_mfc_str = puhost->dev_prop.dev_desc.iManufacturer; + index_prod_str = puhost->dev_prop.dev_desc.iProduct; + index_serial_str = puhost->dev_prop.dev_desc.iSerialNumber; + + puhost->enum_state = ENUM_SET_ADDR; + } + break; + + case ENUM_SET_ADDR: + /* set address */ + if (USBH_OK == usbh_setaddress (pudev, puhost, USBH_DEV_ADDR)) { + usb_mdelay (2); + + puhost->dev_prop.addr = USBH_DEV_ADDR; + + /* user callback for device address assigned */ + puhost->usr_cb->dev_address_set(); + + /* modify control channels to update device address */ + usbh_pipe_update (pudev, + puhost->control.pipe_in_num, + puhost->dev_prop.addr, + 0U, 0U); + + usbh_pipe_update (pudev, + puhost->control.pipe_out_num, + puhost->dev_prop.addr, + 0U, 0U); + + puhost->enum_state = ENUM_GET_CFG_DESC; + } + break; + + case ENUM_GET_CFG_DESC: + /* get standard configuration descriptor */ + if (USBH_OK == usbh_cfgdesc_get (pudev, puhost, USB_CFG_DESC_LEN)) { + puhost->enum_state = ENUM_GET_CFG_DESC_SET; + } + break; + + case ENUM_GET_CFG_DESC_SET: + /* get full config descriptor (config, interface, endpoints) */ + if (USBH_OK == usbh_cfgdesc_get (pudev, puhost, puhost->dev_prop.cfg_desc.wTotalLength)) { + /* user callback for configuration descriptors available */ + puhost->usr_cb->dev_cfgdesc_assigned (&puhost->dev_prop.cfg_desc, + puhost->dev_prop.itf_desc, + puhost->dev_prop.ep_desc[0]); + + puhost->enum_state = ENUM_GET_STR_DESC; + } + break; + + case ENUM_GET_STR_DESC: + if (index_mfc_str) { + if (USBH_OK == usbh_strdesc_get (pudev, + puhost, + puhost->dev_prop.dev_desc.iManufacturer, + str_buf, + 0xFFU)) { + /* user callback for manufacturing string */ + puhost->usr_cb->dev_mfc_str(str_buf); + + index_mfc_str = 0U; + } + } else { + if (index_prod_str) { + /* check that product string is available */ + if (USBH_OK == usbh_strdesc_get (pudev, + puhost, + puhost->dev_prop.dev_desc.iProduct, + str_buf, + 0xFFU)) { + puhost->usr_cb->dev_prod_str(str_buf); + + index_prod_str = 0U; + } + } else { + if (index_serial_str) { + if (USBH_OK == usbh_strdesc_get (pudev, + puhost, + puhost->dev_prop.dev_desc.iSerialNumber, + str_buf, + 0xFFU)) { + puhost->usr_cb->dev_seral_str(str_buf); + puhost->enum_state = ENUM_SET_CONFIGURATION; + + index_serial_str = 0U; + } + } else { + puhost->enum_state = ENUM_SET_CONFIGURATION; + } + } + } + break; + + case ENUM_SET_CONFIGURATION: + if (USBH_OK == usbh_setcfg (pudev, + puhost, + puhost->dev_prop.cfg_desc.bConfigurationValue)) { + puhost->enum_state = ENUM_DEV_CONFIGURED; + } + break; + + case ENUM_DEV_CONFIGURED: + status = USBH_OK; + break; + + default: + break; + } + + return status; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbh_enum.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbh_enum.c new file mode 100644 index 0000000..fe41560 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbh_enum.c @@ -0,0 +1,549 @@ +/*! + \file usbh_enum.c + \brief USB host mode enumberation driver + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "../Include/usbh_transc.h" +#include "../Include/usbh_enum.h" + +static void usbh_devdesc_parse (usb_desc_dev *cfg_desc, uint8_t *buf, uint16_t len); +static void usbh_cfgset_parse (usb_dev_prop *udev, uint8_t *buf); +static void usbh_cfgdesc_parse (usb_desc_config *cfg_desc, uint8_t *buf); +static void usbh_itfdesc_parse (usb_desc_itf *itf_desc, uint8_t *buf); +static void usbh_epdesc_parse (usb_desc_ep *ep_desc, uint8_t *buf); +static void usbh_strdesc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len); + + +/*! + \brief configure USB control status parameters + \param[in] puhost: pointer to usb host + \param[in] buf: control transfer data buffer pointer + \param[in] len: length of the data buffer + \param[out] none + \retval none +*/ +void usbh_ctlstate_config (usbh_host *puhost, uint8_t *buf, uint16_t len) +{ + /* prepare the transactions */ + puhost->control.buf = buf; + puhost->control.ctl_len = len; + + puhost->control.ctl_state = CTL_SETUP; +} + +/*! + \brief get device descriptor from the USB device + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[in] len: length of the descriptor + \param[out] none + \retval operation status +*/ +usbh_status usbh_devdesc_get (usb_core_driver *pudev, usbh_host *puhost, uint8_t len) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &puhost->control; + + if (CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, + .bRequest = USB_GET_DESCRIPTOR, + .wValue = USBH_DESC(USB_DESCTYPE_DEV), + .wIndex = 0U, + .wLength = len + }; + + usbh_ctlstate_config (puhost, pudev->host.rx_buf, len); + } + + status = usbh_ctl_handler (pudev, puhost); + + if (USBH_OK == status) { + /* commands successfully sent and response received */ + usbh_devdesc_parse (&puhost->dev_prop.dev_desc, pudev->host.rx_buf, len); + } + + return status; +} + +/*! + \brief get configuration descriptor from the USB device + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[in] len: length of the descriptor + \param[out] none + \retval operation status +*/ +usbh_status usbh_cfgdesc_get (usb_core_driver *pudev, usbh_host *puhost, uint16_t len) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &puhost->control; + + if (CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, + .bRequest = USB_GET_DESCRIPTOR, + .wValue = USBH_DESC(USB_DESCTYPE_CONFIG), + .wIndex = 0U, + .wLength = len + }; + + usbh_ctlstate_config (puhost, pudev->host.rx_buf, len); + } + + status = usbh_ctl_handler (pudev, puhost); + + if (USBH_OK == status) { + if (len <= USB_CFG_DESC_LEN) { + usbh_cfgdesc_parse (&puhost->dev_prop.cfg_desc, pudev->host.rx_buf); + } else { + usbh_cfgset_parse (&puhost->dev_prop, pudev->host.rx_buf); + } + } + + return status; +} + +/*! + \brief get string descriptor from the USB device + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[in] str_index: index for the string descriptor + \param[in] buf: buffer pointer to the string descriptor + \param[in] len: length of the descriptor + \param[out] none + \retval operation status +*/ +usbh_status usbh_strdesc_get (usb_core_driver *pudev, + usbh_host *puhost, + uint8_t str_index, + uint8_t *buf, + uint16_t len) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &puhost->control; + + if (CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, + .bRequest = USB_GET_DESCRIPTOR, + .wValue = USBH_DESC(USB_DESCTYPE_STR) | str_index, + .wIndex = 0x0409U, + .wLength = len + }; + + usbh_ctlstate_config (puhost, pudev->host.rx_buf, len); + } + + status = usbh_ctl_handler (pudev, puhost); + + if (USBH_OK == status) { + /* commands successfully sent and response received */ + usbh_strdesc_parse (pudev->host.rx_buf, buf, len); + } + + return status; +} + +/*! + \brief set the address to the connected device + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[in] dev_addr: device address to assign + \param[out] none + \retval operation status +*/ +usbh_status usbh_setaddress (usb_core_driver *pudev, usbh_host *puhost, uint8_t dev_addr) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &puhost->control; + + if (CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, + .bRequest = USB_SET_ADDRESS, + .wValue = (uint16_t)dev_addr, + .wIndex = 0U, + .wLength = 0U + }; + + usbh_ctlstate_config (puhost, NULL, 0U); + } + + status = usbh_ctl_handler (pudev, puhost); + + return status; +} + +/*! + \brief set the configuration value to the connected device + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[in] config_index: configuration value + \param[out] none + \retval operation status +*/ +usbh_status usbh_setcfg (usb_core_driver *pudev, usbh_host *puhost, uint16_t config_index) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &puhost->control; + + if (CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, + .bRequest = USB_SET_CONFIGURATION, + .wValue = config_index, + .wIndex = 0U, + .wLength = 0U + }; + + usbh_ctlstate_config (puhost, NULL, 0U); + } + + status = usbh_ctl_handler (pudev, puhost); + + return status; +} + +/*! + \brief set the interface value to the connected device + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[in] ep_num: endpoint number + \param[in] alter_setting: altnated setting value + \param[out] none + \retval operation status +*/ +usbh_status usbh_setinterface (usb_core_driver *pudev, + usbh_host *puhost, + uint8_t ep_num, + uint8_t set) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &puhost->control; + + if (CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_STRD, + .bRequest = USB_SET_INTERFACE, + .wValue = set, + .wIndex = ep_num, + .wLength = 0U + }; + + usbh_ctlstate_config (puhost, NULL, 0U); + } + + status = usbh_ctl_handler (pudev, puhost); + + return status; +} + +/*! + \brief clear or disable a specific feature + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[in] ep_addr: endpoint address + \param[in] pp_num: pipe number + \param[out] none + \retval operation status +*/ +usbh_status usbh_clrfeature (usb_core_driver *pudev, + usbh_host *puhost, + uint8_t ep_addr, + uint8_t pp_num) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &puhost->control; + + if (CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_EP | USB_REQTYPE_STRD, + .bRequest = USB_CLEAR_FEATURE, + .wValue = FEATURE_SELECTOR_EP, + .wIndex = ep_addr, + .wLength = 0 + }; + + if (EP_DIR(ep_addr)) { + pudev->host.pipe[pp_num].data_toggle_in = 0U; + } else { + pudev->host.pipe[pp_num].data_toggle_out = 0U; + } + + usbh_ctlstate_config (puhost, NULL, 0U); + } + + status = usbh_ctl_handler (pudev, puhost); + + return status; +} + +/*! + \brief parse the device descriptor + \param[in] dev_desc: pointer to usb device descriptor buffer + \param[in] buf: pointer to the source descriptor buffer + \param[in] len: length of the descriptor + \param[out] none + \retval operation status +*/ +static void usbh_devdesc_parse (usb_desc_dev *dev_desc, uint8_t *buf, uint16_t len) +{ + *dev_desc = (usb_desc_dev) { + .header = { + .bLength = *(uint8_t *)(buf + 0U), + .bDescriptorType = *(uint8_t *)(buf + 1U) + }, + + .bcdUSB = BYTE_SWAP(buf + 2U), + .bDeviceClass = *(uint8_t *)(buf + 4U), + .bDeviceSubClass = *(uint8_t *)(buf + 5U), + .bDeviceProtocol = *(uint8_t *)(buf + 6U), + .bMaxPacketSize0 = *(uint8_t *)(buf + 7U) + }; + + if (len > 8U) { + /* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */ + dev_desc->idVendor = BYTE_SWAP(buf + 8U); + dev_desc->idProduct = BYTE_SWAP(buf + 10U); + dev_desc->bcdDevice = BYTE_SWAP(buf + 12U); + dev_desc->iManufacturer = *(uint8_t *)(buf + 14U); + dev_desc->iProduct = *(uint8_t *)(buf + 15U); + dev_desc->iSerialNumber = *(uint8_t *)(buf + 16U); + dev_desc->bNumberConfigurations = *(uint8_t *)(buf + 17U); + } +} + +/*! + \brief parse the configuration descriptor + \param[in] cfg_desc: pointer to usb configuration descriptor buffer + \param[in] buf: pointer to the source descriptor buffer + \param[out] none + \retval operation status +*/ +static void usbh_cfgdesc_parse (usb_desc_config *cfg_desc, uint8_t *buf) +{ + /* parse configuration descriptor */ + *cfg_desc = (usb_desc_config) { + .header = { + .bLength = *(uint8_t *)(buf + 0U), + .bDescriptorType = *(uint8_t *)(buf + 1U), + }, + + .wTotalLength = BYTE_SWAP(buf + 2U), + .bNumInterfaces = *(uint8_t *)(buf + 4U), + .bConfigurationValue = *(uint8_t *)(buf + 5U), + .iConfiguration = *(uint8_t *)(buf + 6U), + .bmAttributes = *(uint8_t *)(buf + 7U), + .bMaxPower = *(uint8_t *)(buf + 8U) + }; +} + +/*! + \brief parse the configuration descriptor set + \param[in] udev: pointer to USB core instance + \param[in] buf: pointer to the source descriptor buffer + \param[out] none + \retval operation status +*/ +static void usbh_cfgset_parse (usb_dev_prop *udev, uint8_t *buf) +{ + usb_desc_ep *ep = NULL; + usb_desc_itf *itf = NULL, itf_value; + + usb_desc_header *pdesc = (usb_desc_header *)buf; + + int8_t itf_index = 0U, ep_index = 0U; + uint16_t ptr; + + uint8_t prev_itf = 0U; + uint16_t prev_ep_len = 0U; + + /* parse configuration descriptor */ + usbh_cfgdesc_parse (&udev->cfg_desc, buf); + + ptr = USB_CFG_DESC_LEN; + + if (udev->cfg_desc.bNumInterfaces > USBH_MAX_INTERFACES_NUM) { + return; + } + + while (ptr < udev->cfg_desc.wTotalLength) { + pdesc = usbh_nextdesc_get ((uint8_t *)pdesc, &ptr); + + if (pdesc->bDescriptorType == USB_DESCTYPE_ITF) { + itf_index = *(((uint8_t *)pdesc) + 2U); + itf = &udev->itf_desc[itf_index]; + + if ((*((uint8_t *)pdesc + 3U)) < 3U) { + usbh_itfdesc_parse (&itf_value, (uint8_t *)pdesc); + + /* parse endpoint descriptors relative to the current interface */ + if (itf_value.bNumEndpoints > USBH_MAX_EP_NUM) { + return; + } + + for (ep_index = 0; ep_index < itf_value.bNumEndpoints; ) { + pdesc = usbh_nextdesc_get ((void*)pdesc, &ptr); + + if (pdesc->bDescriptorType == USB_DESCTYPE_EP) { + ep = &udev->ep_desc[itf_index][ep_index]; + + if (prev_itf != itf_index) { + prev_itf = itf_index; + usbh_itfdesc_parse (itf, (uint8_t *)&itf_value); + } else { + if (prev_ep_len > BYTE_SWAP((uint8_t *)pdesc + 4U)) { + break; + } else { + usbh_itfdesc_parse (itf, (uint8_t *)&itf_value); + } + } + + usbh_epdesc_parse (ep, (uint8_t *)pdesc); + prev_ep_len = BYTE_SWAP((uint8_t *)pdesc + 4U); + ep_index++; + } + } + } + } + } +} + +/*! + \brief parse the interface descriptor + \param[in] itf_desc: pointer to usb interface descriptor buffer + \param[in] buf: pointer to the source descriptor buffer + \param[out] none + \retval operation status +*/ +static void usbh_itfdesc_parse (usb_desc_itf *itf_desc, uint8_t *buf) +{ + *itf_desc = (usb_desc_itf) { + .header = { + .bLength = *(uint8_t *)(buf + 0U), + .bDescriptorType = *(uint8_t *)(buf + 1U), + }, + + .bInterfaceNumber = *(uint8_t *)(buf + 2U), + .bAlternateSetting = *(uint8_t *)(buf + 3U), + .bNumEndpoints = *(uint8_t *)(buf + 4U), + .bInterfaceClass = *(uint8_t *)(buf + 5U), + .bInterfaceSubClass = *(uint8_t *)(buf + 6U), + .bInterfaceProtocol = *(uint8_t *)(buf + 7U), + .iInterface = *(uint8_t *)(buf + 8U) + }; +} + +/*! + \brief parse the endpoint descriptor + \param[in] ep_desc: pointer to usb endpoint descriptor buffer + \param[in] buf: pointer to the source descriptor buffer + \param[out] none + \retval operation status +*/ +static void usbh_epdesc_parse (usb_desc_ep *ep_desc, uint8_t *buf) +{ + *ep_desc = (usb_desc_ep) { + .header = { + .bLength = *(uint8_t *)(buf + 0U), + .bDescriptorType = *(uint8_t *)(buf + 1U) + }, + + .bEndpointAddress = *(uint8_t *)(buf + 2U), + .bmAttributes = *(uint8_t *)(buf + 3U), + .wMaxPacketSize = BYTE_SWAP(buf + 4U), + .bInterval = *(uint8_t *)(buf + 6U) + }; +} + +/*! + \brief parse the string descriptor + \param[in] psrc: source pointer containing the descriptor data + \param[in] pdest: destination address pointer + \param[in] len: length of the descriptor + \param[out] none + \retval operation status +*/ +static void usbh_strdesc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len) +{ + uint16_t str_len = 0U, index = 0U; + + /* the unicode string descriptor is not NULL-terminated. The string length is + * computed by substracting two from the value of the first byte of the descriptor. + */ + + /* check which is lower size, the size of string or the length of bytes read from the device */ + if (USB_DESCTYPE_STR == psrc[1]) { + /* make sure the descriptor is string type */ + + /* psrc[0] contains Size of Descriptor, subtract 2 to get the length of string */ + str_len = USB_MIN(psrc[0] - 2U, len); + + psrc += 2U; /* adjust the offset ignoring the string len and descriptor type */ + + for (index = 0U; index < str_len; index += 2U) { + /* copy only the string and ignore the unicode id, hence add the src */ + *pdest = psrc[index]; + + pdest++; + } + + *pdest = 0U; /* mark end of string */ + } +} + +/*! + \brief get the next descriptor header + \param[in] pbuf: pointer to buffer where the configuration descriptor set is available + \param[in] ptr: data popinter inside the configuration descriptor set + \param[out] none + \retval operation status +*/ +usb_desc_header *usbh_nextdesc_get (uint8_t *pbuf, uint16_t *ptr) +{ + usb_desc_header *pnext; + + *ptr += ((usb_desc_header *)pbuf)->bLength; + + pnext = (usb_desc_header *)((uint8_t *)pbuf + ((usb_desc_header *)pbuf)->bLength); + + return (pnext); +} + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbh_pipe.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbh_pipe.c new file mode 100644 index 0000000..5fb29f3 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbh_pipe.c @@ -0,0 +1,174 @@ +/*! + \file usbh_pipe.c + \brief USB host mode pipe operation driver + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "../Include/usbh_pipe.h" + +static uint16_t usbh_freepipe_get (usb_core_driver *pudev); + +/*! + \brief create a pipe + \param[in] pudev: pointer to usb core instance + \param[in] pp_num: pipe number + \param[in] udev: USB device + \param[in] ep_type: endpoint type + \param[in] ep_mpl: endpoint max packet length + \param[out] none + \retval operation status +*/ +uint8_t usbh_pipe_create (usb_core_driver *pudev, + usb_dev_prop *udev, + uint8_t pp_num, + uint8_t ep_type, + uint16_t ep_mpl) +{ + usb_pipe *pp = &pudev->host.pipe[pp_num]; + + pp->dev_addr = udev->addr; + pp->dev_speed = udev->speed; + pp->ep.type = ep_type; + pp->ep.mps = ep_mpl; + pp->ping = udev->speed == PORT_SPEED_HIGH; + + usb_pipe_init (pudev, pp_num); + + return HC_OK; +} + +/*! + \brief modify a pipe + \param[in] pudev: pointer to usb core instance + \param[in] pp_num: pipe number + \param[in] dev_addr: device address + \param[in] dev_speed: device speed + \param[in] ep_type: endpoint type + \param[in] ep_mpl: endpoint max packet length + \param[out] none + \retval operation status +*/ +uint8_t usbh_pipe_update (usb_core_driver *pudev, + uint8_t pp_num, + uint8_t dev_addr, + uint32_t dev_speed, + uint16_t ep_mpl) +{ + usb_pipe *pp = &pudev->host.pipe[pp_num]; + + if ((pp->dev_addr != dev_addr) && (dev_addr)) { + pp->dev_addr = dev_addr; + } + + if ((pp->dev_speed != dev_speed) && (dev_speed)) { + pp->dev_speed = dev_speed; + } + + if ((pp->ep.mps != ep_mpl) && (ep_mpl)) { + pp->ep.mps = ep_mpl; + } + + usb_pipe_init (pudev, pp_num); + + return HC_OK; +} + +/*! + \brief allocate a new pipe + \param[in] pudev: pointer to usb core instance + \param[in] ep_addr: endpoint address + \param[out] none + \retval operation status +*/ +uint8_t usbh_pipe_allocate (usb_core_driver *pudev, uint8_t ep_addr) +{ + uint16_t pp_num = usbh_freepipe_get (pudev); + + if (HC_ERROR != pp_num) { + pudev->host.pipe[pp_num].in_used = 1U; + pudev->host.pipe[pp_num].ep.dir = EP_DIR(ep_addr); + pudev->host.pipe[pp_num].ep.num = EP_ID(ep_addr); + } + + return pp_num; +} + +/*! + \brief free a pipe + \param[in] pudev: pointer to usb core instance + \param[in] pp_num: pipe number + \param[out] none + \retval operation status +*/ +uint8_t usbh_pipe_free (usb_core_driver *pudev, uint8_t pp_num) +{ + if (pp_num < HC_MAX) { + pudev->host.pipe[pp_num].in_used = 0U; + } + + return USBH_OK; +} + +/*! + \brief delete all USB host pipe + \param[in] pudev: pointer to usb core instance + \param[out] none + \retval operation status +*/ +uint8_t usbh_pipe_delete (usb_core_driver *pudev) +{ + uint8_t pp_num = 0U; + + for (pp_num = 2U; pp_num < HC_MAX; pp_num++) { + pudev->host.pipe[pp_num] = (usb_pipe) {0}; + } + + return USBH_OK; +} + +/*! + \brief get a free pipe number for allocation + \param[in] pudev: pointer to usb core instance + \param[out] none + \retval operation status +*/ +static uint16_t usbh_freepipe_get (usb_core_driver *pudev) +{ + uint8_t pp_num = 0U; + + for (pp_num = 0U; pp_num < HC_MAX; pp_num++) { + if (pudev->host.pipe[pp_num].in_used == 0U) { + return pp_num; + } + } + + return HC_ERROR; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbh_transc.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbh_transc.c new file mode 100644 index 0000000..433f18a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/GD32VF103_usbfs_driver/Source/usbh_transc.c @@ -0,0 +1,391 @@ +/*! + \file usbh_transc.c + \brief USB host mode transactions driver + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "../Include/drv_usb_hw.h" +#include "../Include/usbh_transc.h" + +/*! + \brief prepare a pipe and start a transfer + \param[in] pudev: pointer to usb core instance + \param[in] pp_num: pipe number + \param[out] none + \retval operation status +*/ +static uint32_t usbh_request_submit (usb_core_driver *pudev, uint8_t pp_num) +{ + pudev->host.pipe[pp_num].urb_state = URB_IDLE; + pudev->host.pipe[pp_num].xfer_count = 0U; + + return usb_pipe_xfer (pudev, pp_num); +} + +/*! + \brief send the setup packet to the USB device + \param[in] pudev: pointer to usb core instance + \param[in] buf: data buffer which will be sent to USB device + \param[in] pp_num: pipe number + \param[out] none + \retval operation status +*/ +usbh_status usbh_ctlsetup_send (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num) +{ + usb_pipe *pp = &pudev->host.pipe[pp_num]; + + pp->DPID = PIPE_DPID_SETUP; + pp->xfer_buf = buf; + pp->xfer_len = USB_SETUP_PACKET_LEN; + + return (usbh_status)usbh_request_submit (pudev, pp_num); +} + +/*! + \brief send a data packet to the USB device + \param[in] pudev: pointer to usb core instance + \param[in] buf: data buffer which will be sent to USB device + \param[in] pp_num: pipe number + \param[in] len: length of the data to be sent + \param[out] none + \retval operation status +*/ +usbh_status usbh_data_send (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len) +{ + usb_pipe *pp = &pudev->host.pipe[pp_num]; + + pp->xfer_buf = buf; + pp->xfer_len = len; + + switch (pp->ep.type) { + case USB_EPTYPE_CTRL: + if (0U == len) { + pp->data_toggle_out = 1U; + } + + pp->DPID = PIPE_DPID[pp->data_toggle_out]; + break; + + case USB_EPTYPE_INTR: + pp->DPID = PIPE_DPID[pp->data_toggle_out]; + + pp->data_toggle_out ^= 1U; + break; + + case USB_EPTYPE_BULK: + pp->DPID = PIPE_DPID[pp->data_toggle_out]; + break; + + case USB_EPTYPE_ISOC: + pp->DPID = PIPE_DPID[0]; + break; + + default: + break; + } + + usbh_request_submit (pudev, pp_num); + + return USBH_OK; +} + +/*! + \brief receive a data packet from the USB device + \param[in] pudev: pointer to usb core instance + \param[in] buf: data buffer which will be received from USB device + \param[in] pp_num: pipe number + \param[in] len: length of the data to be received + \param[out] none + \retval operation status +*/ +usbh_status usbh_data_recev (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len) +{ + usb_pipe *pp = &pudev->host.pipe[pp_num]; + + pp->xfer_buf = buf; + pp->xfer_len = len; + + switch (pp->ep.type) { + case USB_EPTYPE_CTRL: + pp->DPID = PIPE_DPID[1]; + break; + + case USB_EPTYPE_INTR: + pp->DPID = PIPE_DPID[pp->data_toggle_in]; + + /* Toggle DATA PID */ + pp->data_toggle_in ^= 1U; + break; + + case USB_EPTYPE_BULK: + pp->DPID = PIPE_DPID[pp->data_toggle_in]; + break; + + case USB_EPTYPE_ISOC: + pp->DPID = PIPE_DPID[0]; + break; + + default: + break; + } + + usbh_request_submit (pudev, pp_num); + + return USBH_OK; +} + +/*! + \brief wait for USB URB(USB request block) state + \param[in] pudev: pointer to USB core instance + \param[in] puhost: pointer to USB host + \param[in] pp_num: pipe number + \param[in] wait_time: wait time + \param[out] none + \retval USB URB state +*/ +static usb_urb_state usbh_urb_wait (usb_core_driver *pudev, usbh_host *puhost, uint8_t pp_num, uint32_t wait_time) +{ + usb_urb_state urb_status = URB_IDLE; + + while (URB_DONE != (urb_status = usbh_urbstate_get(pudev, pp_num))) { + if (URB_NOTREADY == urb_status) { + break; + } else if (URB_STALL == urb_status) { + puhost->control.ctl_state = CTL_SETUP; + break; + } else if (URB_ERROR == urb_status) { + puhost->control.ctl_state = CTL_ERROR; + break; + } else if ((wait_time > 0U) && \ + ((usb_curframe_get(pudev)- puhost->control.timer) > wait_time)) { + /* timeout for in transfer */ + puhost->control.ctl_state = CTL_ERROR; + break; + } else { + /* no operation, just wait */ + } + } + + return urb_status; +} + +/*! + \brief USB setup transaction + \param[in] pudev: pointer to USB core instance + \param[in] puhost: pointer to USB host + \param[out] none + \retval none +*/ +static void usbh_setup_transc (usb_core_driver *pudev, usbh_host *puhost) +{ + usb_urb_state urb_status = URB_IDLE; + + /* send a SETUP packet */ + usbh_ctlsetup_send (pudev, + puhost->control.setup.data, + puhost->control.pipe_out_num); + + urb_status = usbh_urb_wait (pudev, puhost, puhost->control.pipe_out_num, 0U); + + if (URB_DONE == urb_status) { + uint8_t dir = (puhost->control.setup.req.bmRequestType & USB_TRX_MASK); + + if (puhost->control.setup.req.wLength) { + if (USB_TRX_IN == dir) { + puhost->control.ctl_state = CTL_DATA_IN; + } else { + puhost->control.ctl_state = CTL_DATA_OUT; + } + } else { + if (USB_TRX_IN == dir) { + puhost->control.ctl_state = CTL_STATUS_OUT; + } else { + puhost->control.ctl_state = CTL_STATUS_IN; + } + } + + /* set the delay timer to enable timeout for data stage completion */ + puhost->control.timer = usb_curframe_get(pudev); + } +} + +/*! + \brief USB data IN transaction + \param[in] pudev: pointer to USB core instance + \param[in] puhost: pointer to USB host + \param[out] none + \retval none +*/ +static void usbh_data_in_transc (usb_core_driver *pudev, usbh_host *puhost) +{ + usb_urb_state urb_status = URB_IDLE; + + usbh_data_recev (pudev, + puhost->control.buf, + puhost->control.pipe_in_num, + puhost->control.ctl_len); + + urb_status = usbh_urb_wait (pudev, puhost, puhost->control.pipe_in_num, DATA_STAGE_TIMEOUT); + + if (URB_DONE == urb_status) { + puhost->control.ctl_state = CTL_STATUS_OUT; + + puhost->control.timer = usb_curframe_get(pudev); + } +} + +/*! + \brief USB data OUT transaction + \param[in] pudev: pointer to USB core instance + \param[in] puhost: pointer to USB host + \param[out] none + \retval none +*/ +static void usbh_data_out_transc (usb_core_driver *pudev, usbh_host *puhost) +{ + usb_urb_state urb_status = URB_IDLE; + + pudev->host.pipe[puhost->control.pipe_out_num].data_toggle_out = 1U; + + usbh_data_send (pudev, + puhost->control.buf, + puhost->control.pipe_out_num, + puhost->control.ctl_len); + + urb_status = usbh_urb_wait (pudev, puhost, puhost->control.pipe_out_num, DATA_STAGE_TIMEOUT); + + if (URB_DONE == urb_status) { + puhost->control.ctl_state = CTL_STATUS_IN; + + puhost->control.timer = usb_curframe_get(pudev); + } +} + +/*! + \brief USB status IN transaction + \param[in] pudev: pointer to USB core instance + \param[in] puhost: pointer to USB host + \param[out] none + \retval none +*/ +static void usbh_status_in_transc (usb_core_driver *pudev, usbh_host *puhost) +{ + uint8_t pp_num = puhost->control.pipe_in_num; + + usb_urb_state urb_status = URB_IDLE; + + usbh_data_recev (pudev, NULL, pp_num, 0U); + + urb_status = usbh_urb_wait (pudev, puhost, pp_num, NODATA_STAGE_TIMEOUT); + + if (URB_DONE == urb_status) { + puhost->control.ctl_state = CTL_FINISH; + } +} + +/*! + \brief USB status OUT transaction + \param[in] pudev: pointer to USB core instance + \param[in] puhost: pointer to USB host + \param[out] none + \retval none +*/ +static void usbh_status_out_transc (usb_core_driver *pudev, usbh_host *puhost) +{ + uint8_t pp_num = puhost->control.pipe_out_num; + + usb_urb_state urb_status = URB_IDLE; + + pudev->host.pipe[pp_num].data_toggle_out ^= 1U; + + usbh_data_send (pudev, NULL, pp_num, 0U); + + urb_status = usbh_urb_wait (pudev, puhost, pp_num, NODATA_STAGE_TIMEOUT); + + if (URB_DONE == urb_status) { + puhost->control.ctl_state = CTL_FINISH; + } +} + +/*! + \brief USB control transfer handler + \param[in] pudev: pointer to USB core instance + \param[in] puhost: pointer to USB host + \param[out] none + \retval operation status +*/ +usbh_status usbh_ctl_handler (usb_core_driver *pudev, usbh_host *puhost) +{ + usbh_status status = USBH_BUSY; + + switch (puhost->control.ctl_state) { + case CTL_SETUP: + usbh_setup_transc (pudev, puhost); + break; + + case CTL_DATA_IN: + usbh_data_in_transc (pudev, puhost); + break; + + case CTL_DATA_OUT: + usbh_data_out_transc (pudev, puhost); + break; + + case CTL_STATUS_IN: + usbh_status_in_transc (pudev, puhost); + break; + + case CTL_STATUS_OUT: + usbh_status_out_transc (pudev, puhost); + break; + + case CTL_FINISH: + puhost->control.ctl_state = CTL_IDLE; + + status = USBH_OK; + break; + + case CTL_ERROR: + if (++puhost->control.error_count <= USBH_MAX_ERROR_COUNT) { + /* do the transmission again, starting from SETUP packet */ + puhost->control.ctl_state = CTL_SETUP; + } else { + status = USBH_FAIL; + } + break; + + default: + break; + } + + return status; +} + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/n200_eclic.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/n200_eclic.h new file mode 100644 index 0000000..a155748 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/n200_eclic.h @@ -0,0 +1,48 @@ +// See LICENSE file for licence details + +#ifndef N200_ECLIC_H +#define N200_ECLIC_H + +#include + +#define ECLICINTCTLBITS 4 + +//ECLIC memory map +// Offset +// 0x0000 1B RW ecliccfg +#define ECLIC_CFG_OFFSET 0x0 +// 0x0004 4B R eclicinfo +#define ECLIC_INFO_OFFSET 0x4 +// 0x000B 1B RW mintthresh +#define ECLIC_MTH_OFFSET 0xB +// +// 0x1000+4*i 1B/input RW eclicintip[i] +#define ECLIC_INT_IP_OFFSET _AC(0x1000,UL) +// 0x1001+4*i 1B/input RW eclicintie[i] +#define ECLIC_INT_IE_OFFSET _AC(0x1001,UL) +// 0x1002+4*i 1B/input RW eclicintattr[i] +#define ECLIC_INT_ATTR_OFFSET _AC(0x1002,UL) + +#define ECLIC_INT_ATTR_SHV 0x01 +#define ECLIC_INT_ATTR_TRIG_LEVEL 0x00 +#define ECLIC_INT_ATTR_TRIG_EDGE 0x02 +#define ECLIC_INT_ATTR_TRIG_POS 0x00 +#define ECLIC_INT_ATTR_TRIG_NEG 0x04 + +// 0x1003+4*i 1B/input RW eclicintctl[i] +#define ECLIC_INT_CTRL_OFFSET _AC(0x1003,UL) +// +// ... +// +#define ECLIC_ADDR_BASE 0xd2000000 + + +#define ECLIC_CFG_NLBITS_MASK _AC(0x1E,UL) +#define ECLIC_CFG_NLBITS_LSB (1u) + +#define MSIP_HANDLER eclic_msip_handler +#define MTIME_HANDLER eclic_mtip_handler +#define BWEI_HANDLER eclic_bwei_handler +#define PMOVI_HANDLER eclic_pmovi_handler + +#endif diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/n200_func.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/n200_func.c new file mode 100644 index 0000000..b589020 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/n200_func.c @@ -0,0 +1,398 @@ +// See LICENSE for license details. +#include +#include +#include +#include +#include + +#include "riscv_encoding.h" +#include "n200_func.h" + + // Configure PMP to make all the address space accesable and executable +void pmp_open_all_space(){ + // Config entry0 addr to all 1s to make the range cover all space + asm volatile ("li x6, 0xffffffff":::"x6"); + asm volatile ("csrw pmpaddr0, x6":::); + // Config entry0 cfg to make it NAPOT address mode, and R/W/X okay + asm volatile ("li x6, 0x7f":::"x6"); + asm volatile ("csrw pmpcfg0, x6":::); +} + +void switch_m2u_mode(){ + clear_csr (mstatus,MSTATUS_MPP); + //printf("\nIn the m2u function, the mstatus is 0x%x\n", read_csr(mstatus)); + //printf("\nIn the m2u function, the mepc is 0x%x\n", read_csr(mepc)); + asm volatile ("la x6, 1f ":::"x6"); + asm volatile ("csrw mepc, x6":::); + asm volatile ("mret":::); + asm volatile ("1:":::); +} + +uint32_t mtime_lo(void) +{ + return *(volatile uint32_t *)(TIMER_CTRL_ADDR + TIMER_MTIME); +} + + +uint32_t mtime_hi(void) +{ + return *(volatile uint32_t *)(TIMER_CTRL_ADDR + TIMER_MTIME + 4); +} + +uint64_t get_timer_value() +{ + while (1) { + uint32_t hi = mtime_hi(); + uint32_t lo = mtime_lo(); + if (hi == mtime_hi()) + return ((uint64_t)hi << 32) | lo; + } +} + +uint32_t get_timer_freq() +{ + return TIMER_FREQ; +} + +uint64_t get_instret_value() +{ + while (1) { + uint32_t hi = read_csr(minstreth); + uint32_t lo = read_csr(minstret); + if (hi == read_csr(minstreth)) + return ((uint64_t)hi << 32) | lo; + } +} + +uint64_t get_cycle_value() +{ + while (1) { + uint32_t hi = read_csr(mcycleh); + uint32_t lo = read_csr(mcycle); + if (hi == read_csr(mcycleh)) + return ((uint64_t)hi << 32) | lo; + } +} + +uint32_t __attribute__((noinline)) measure_cpu_freq(size_t n) +{ + uint32_t start_mtime, delta_mtime; + uint32_t mtime_freq = get_timer_freq(); + + // Don't start measuruing until we see an mtime tick + uint32_t tmp = mtime_lo(); + do { + start_mtime = mtime_lo(); + } while (start_mtime == tmp); + + uint32_t start_mcycle = read_csr(mcycle); + + do { + delta_mtime = mtime_lo() - start_mtime; + } while (delta_mtime < n); + + uint32_t delta_mcycle = read_csr(mcycle) - start_mcycle; + + return (delta_mcycle / delta_mtime) * mtime_freq + + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime; +} + +uint32_t get_cpu_freq() +{ + uint32_t cpu_freq; + + // warm up + measure_cpu_freq(1); + // measure for real + cpu_freq = measure_cpu_freq(100); + + return cpu_freq; +} + + + +// Note that there are no assertions or bounds checking on these +// parameter values. + + + + +void eclic_init ( uint32_t num_irq ) +{ + + typedef volatile uint32_t vuint32_t; + + //clear cfg register + *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_CFG_OFFSET)=0; + + //clear minthresh register + *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_MTH_OFFSET)=0; + + //clear all IP/IE/ATTR/CTRL bits for all interrupt sources + vuint32_t * ptr; + + vuint32_t * base = (vuint32_t*)(ECLIC_ADDR_BASE + ECLIC_INT_IP_OFFSET); + vuint32_t * upper = (vuint32_t*)(base + num_irq*4); + + for (ptr = base; ptr < upper; ptr=ptr+4){ + *ptr = 0; + } +} + + + +void eclic_enable_interrupt (uint32_t source) { + *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_INT_IE_OFFSET+source*4) = 1; +} + +void eclic_disable_interrupt (uint32_t source){ + *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_INT_IE_OFFSET+source*4) = 0; +} + +void eclic_set_pending(uint32_t source){ + *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_INT_IP_OFFSET+source*4) = 1; +} + +void eclic_clear_pending(uint32_t source){ + *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_INT_IP_OFFSET+source*4) = 0; +} + +void eclic_set_intctrl (uint32_t source, uint8_t intctrl){ + *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_INT_CTRL_OFFSET+source*4) = intctrl; +} + +uint8_t eclic_get_intctrl (uint32_t source){ + return *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_INT_CTRL_OFFSET+source*4); +} + +void eclic_set_intattr (uint32_t source, uint8_t intattr){ + *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_INT_ATTR_OFFSET+source*4) = intattr; +} + +uint8_t eclic_get_intattr (uint32_t source){ + return *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_INT_ATTR_OFFSET+source*4); +} + +void eclic_set_cliccfg (uint8_t cliccfg){ + *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_CFG_OFFSET) = cliccfg; +} + +uint8_t eclic_get_cliccfg (){ + return *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_CFG_OFFSET); +} + +void eclic_set_mth (uint8_t mth){ + *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_MTH_OFFSET) = mth; +} + +uint8_t eclic_get_mth (){ + return *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_MTH_OFFSET); +} + +//sets nlbits +void eclic_set_nlbits(uint8_t nlbits) { + //shift nlbits to correct position + uint8_t nlbits_shifted = nlbits << ECLIC_CFG_NLBITS_LSB; + + //read the current cliccfg + uint8_t old_cliccfg = eclic_get_cliccfg(); + uint8_t new_cliccfg = (old_cliccfg & (~ECLIC_CFG_NLBITS_MASK)) | (ECLIC_CFG_NLBITS_MASK & nlbits_shifted); + + eclic_set_cliccfg(new_cliccfg); +} + +//get nlbits +uint8_t eclic_get_nlbits(void) { + //extract nlbits + uint8_t nlbits = eclic_get_cliccfg(); + nlbits = (nlbits & ECLIC_CFG_NLBITS_MASK) >> ECLIC_CFG_NLBITS_LSB; + return nlbits; +} + +//sets an interrupt level based encoding of nlbits and ECLICINTCTLBITS +void eclic_set_irq_lvl(uint32_t source, uint8_t lvl) { + //extract nlbits + uint8_t nlbits = eclic_get_nlbits(); + if (nlbits > ECLICINTCTLBITS) { + nlbits = ECLICINTCTLBITS; + } + + //shift lvl right to mask off unused bits + lvl = lvl >> (8-nlbits); + //shift lvl into correct bit position + lvl = lvl << (8-nlbits); + + //write to clicintctrl + uint8_t current_intctrl = eclic_get_intctrl(source); + //shift intctrl left to mask off unused bits + current_intctrl = current_intctrl << nlbits; + //shift intctrl into correct bit position + current_intctrl = current_intctrl >> nlbits; + + eclic_set_intctrl(source, (current_intctrl | lvl)); +} + +//gets an interrupt level based encoding of nlbits +uint8_t eclic_get_irq_lvl(uint32_t source) { + //extract nlbits + uint8_t nlbits = eclic_get_nlbits(); + if (nlbits > ECLICINTCTLBITS) { + nlbits = ECLICINTCTLBITS; + } + + uint8_t intctrl = eclic_get_intctrl(source); + + //shift intctrl + intctrl = intctrl >> (8-nlbits); + //shift intctrl + uint8_t lvl = intctrl << (8-nlbits); + + return lvl; +} + +void eclic_set_irq_lvl_abs(uint32_t source, uint8_t lvl_abs) { + //extract nlbits + uint8_t nlbits = eclic_get_nlbits(); + if (nlbits > ECLICINTCTLBITS) { + nlbits = ECLICINTCTLBITS; + } + + //shift lvl_abs into correct bit position + uint8_t lvl = lvl_abs << (8-nlbits); + + //write to clicintctrl + uint8_t current_intctrl = eclic_get_intctrl(source); + //shift intctrl left to mask off unused bits + current_intctrl = current_intctrl << nlbits; + //shift intctrl into correct bit position + current_intctrl = current_intctrl >> nlbits; + + eclic_set_intctrl(source, (current_intctrl | lvl)); +} + +uint8_t eclic_get_irq_lvl_abs(uint32_t source) { + //extract nlbits + uint8_t nlbits = eclic_get_nlbits(); + if (nlbits > ECLICINTCTLBITS) { + nlbits = ECLICINTCTLBITS; + } + + uint8_t intctrl = eclic_get_intctrl(source); + + //shift intctrl + intctrl = intctrl >> (8-nlbits); + //shift intctrl + uint8_t lvl_abs = intctrl; + + return lvl_abs; +} + +//sets an interrupt priority based encoding of nlbits and ECLICINTCTLBITS +uint8_t eclic_set_irq_priority(uint32_t source, uint8_t priority) { + //extract nlbits + uint8_t nlbits = eclic_get_nlbits(); + if (nlbits >= ECLICINTCTLBITS) { + nlbits = ECLICINTCTLBITS; + return 0; + } + + //shift priority into correct bit position + priority = priority << (8 - ECLICINTCTLBITS); + + //write to eclicintctrl + uint8_t current_intctrl = eclic_get_intctrl(source); + //shift intctrl right to mask off unused bits + current_intctrl = current_intctrl >> (8-nlbits); + //shift intctrl into correct bit position + current_intctrl = current_intctrl << (8-nlbits); + + eclic_set_intctrl(source, (current_intctrl | priority)); + + return priority; +} + +//gets an interrupt priority based encoding of nlbits +uint8_t eclic_get_irq_priority(uint32_t source) { + //extract nlbits + uint8_t nlbits = eclic_get_nlbits(); + if (nlbits > ECLICINTCTLBITS) { + nlbits = ECLICINTCTLBITS; + } + + uint8_t intctrl = eclic_get_intctrl(source); + + //shift intctrl + intctrl = intctrl << nlbits; + //shift intctrl + uint8_t priority = intctrl >> (nlbits+(8 - ECLICINTCTLBITS)); + + return priority; +} + +void eclic_mode_enable() { + uint32_t mtvec_value = read_csr(mtvec); + mtvec_value = mtvec_value & 0xFFFFFFC0; + mtvec_value = mtvec_value | 0x00000003; + write_csr(mtvec,mtvec_value); +} + +//sets vector-mode or non-vector mode +void eclic_set_vmode(uint32_t source) { + //read the current attr + uint8_t old_intattr = eclic_get_intattr(source); + // Keep other bits unchanged and only set the LSB bit + uint8_t new_intattr = (old_intattr | 0x1); + + eclic_set_intattr(source,new_intattr); +} + +void eclic_set_nonvmode(uint32_t source) { + //read the current attr + uint8_t old_intattr = eclic_get_intattr(source); + // Keep other bits unchanged and only clear the LSB bit + uint8_t new_intattr = (old_intattr & (~0x1)); + + eclic_set_intattr(source,new_intattr); +} + +//sets interrupt as level sensitive +//Bit 1, trig[0], is defined as "edge-triggered" (0: level-triggered, 1: edge-triggered); +//Bit 2, trig[1], is defined as "negative-edge" (0: positive-edge, 1: negative-edge). + +void eclic_set_level_trig(uint32_t source) { + //read the current attr + uint8_t old_intattr = eclic_get_intattr(source); + // Keep other bits unchanged and only clear the bit 1 + uint8_t new_intattr = (old_intattr & (~0x2)); + + eclic_set_intattr(source,new_intattr); +} + +void eclic_set_posedge_trig(uint32_t source) { + //read the current attr + uint8_t old_intattr = eclic_get_intattr(source); + // Keep other bits unchanged and only set the bit 1 + uint8_t new_intattr = (old_intattr | 0x2); + // Keep other bits unchanged and only clear the bit 2 + new_intattr = (old_intattr & (~0x4)); + + eclic_set_intattr(source,new_intattr); +} + +void eclic_set_negedge_trig(uint32_t source) { + //read the current attr + uint8_t old_intattr = eclic_get_intattr(source); + // Keep other bits unchanged and only set the bit 1 + uint8_t new_intattr = (old_intattr | 0x2); + // Keep other bits unchanged and only set the bit 2 + new_intattr = (old_intattr | 0x4); + + eclic_set_intattr(source,new_intattr); +} + +//void wfe() { +// core_wfe(); +//} + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/n200_func.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/n200_func.h new file mode 100644 index 0000000..6531d0b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/n200_func.h @@ -0,0 +1,109 @@ +// See LICENSE file for licence details + +#ifndef N200_FUNC_H +#define N200_FUNC_H + + +#include +#include "n200_timer.h" +#include "n200_eclic.h" + +#define ECLIC_GROUP_LEVEL0_PRIO4 0 +#define ECLIC_GROUP_LEVEL1_PRIO3 1 +#define ECLIC_GROUP_LEVEL2_PRIO2 2 +#define ECLIC_GROUP_LEVEL3_PRIO1 3 +#define ECLIC_GROUP_LEVEL4_PRIO0 4 + +void pmp_open_all_space(); + +void switch_m2u_mode(); + +uint32_t get_mtime_freq(); + +uint32_t mtime_lo(void); + +uint32_t mtime_hi(void); + +uint64_t get_mtime_value(); + +uint64_t get_instret_value(); + +uint64_t get_cycle_value(); + +uint32_t get_cpu_freq(); + +uint32_t __attribute__((noinline)) measure_cpu_freq(size_t n); + + +/////////////////////////////////////////////////////////////////// +/////// ECLIC relevant functions +/////// +void eclic_init ( uint32_t num_irq ); +uint64_t get_timer_value(); +void eclic_enable_interrupt (uint32_t source); +void eclic_disable_interrupt (uint32_t source); + +void eclic_set_pending(uint32_t source); +void eclic_clear_pending(uint32_t source); + +void eclic_set_intctrl (uint32_t source, uint8_t intctrl); +uint8_t eclic_get_intctrl (uint32_t source); + +void eclic_set_intattr (uint32_t source, uint8_t intattr); +uint8_t eclic_get_intattr (uint32_t source); + +void eclic_set_cliccfg (uint8_t cliccfg); +uint8_t eclic_get_cliccfg (); + +void eclic_set_mth (uint8_t mth); +uint8_t eclic_get_mth(); + +//sets nlbits +void eclic_set_nlbits(uint8_t nlbits); + + +//get nlbits +uint8_t eclic_get_nlbits(); + +void eclic_set_irq_lvl(uint32_t source, uint8_t lvl); +uint8_t eclic_get_irq_lvl(uint32_t source); + +void eclic_set_irq_lvl_abs(uint32_t source, uint8_t lvl_abs); +uint8_t eclic_get_irq_lvl_abs(uint32_t source); + +uint8_t eclic_set_irq_priority(uint32_t source, uint8_t priority); +uint8_t eclic_get_irq_priority(uint32_t source); + +void eclic_mode_enable(); + +void eclic_set_vmode(uint32_t source); +void eclic_set_nonvmode(uint32_t source); + +void eclic_set_level_trig(uint32_t source); +void eclic_set_posedge_trig(uint32_t source); +void eclic_set_negedge_trig(uint32_t source); + + +///** \brief Wait For Interrupt +// +// Wait For Interrupt is a hint instruction that suspends execution +// until one of a number of events occurs. +// */ +__attribute__( ( always_inline ) ) static inline void __WFI(void) { + __asm volatile ("wfi"); +} +// +// +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) static inline void __WFE(void) { + __asm volatile ("csrs 0x810, 0x1"); + __asm volatile ("wfi"); + __asm volatile ("csrc 0x810, 0x1"); +} + + +#endif diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/n200_timer.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/n200_timer.h new file mode 100644 index 0000000..75ef7ca --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/n200_timer.h @@ -0,0 +1,18 @@ +// See LICENSE file for licence details + +#ifndef N200_TIMER_H +#define N200_TIMER_H + +#define TIMER_MSIP 0xFFC +#define TIMER_MSIP_size 0x4 +#define TIMER_MTIMECMP 0x8 +#define TIMER_MTIMECMP_size 0x8 +#define TIMER_MTIME 0x0 +#define TIMER_MTIME_size 0x8 + +#define TIMER_CTRL_ADDR 0xd1000000 +#define TIMER_REG(offset) _REG32(TIMER_CTRL_ADDR, offset) +#define TIMER_FREQ ((uint32_t)SystemCoreClock/4) //units HZ + +#endif + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/riscv_bits.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/riscv_bits.h new file mode 100644 index 0000000..bfe656f --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/riscv_bits.h @@ -0,0 +1,36 @@ +// See LICENSE for license details. +#ifndef _RISCV_BITS_H +#define _RISCV_BITS_H + +#define likely(x) __builtin_expect((x), 1) +#define unlikely(x) __builtin_expect((x), 0) + +#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) +#define ROUNDDOWN(a, b) ((a)/(b)*(b)) + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) + +#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#define STR(x) XSTR(x) +#define XSTR(x) #x + +#if __riscv_xlen == 64 +# define SLL32 sllw +# define STORE sd +# define LOAD ld +# define LWU lwu +# define LOG_REGBYTES 3 +#else +# define SLL32 sll +# define STORE sw +# define LOAD lw +# define LWU lw +# define LOG_REGBYTES 2 +#endif +#define REGBYTES (1 << LOG_REGBYTES) + +#endif diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/riscv_const.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/riscv_const.h new file mode 100644 index 0000000..d5dec8a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/riscv_const.h @@ -0,0 +1,18 @@ +// See LICENSE for license details. +/* Derived from */ + +#ifndef _RISCV_CONST_H +#define _RISCV_CONST_H + +#ifdef __ASSEMBLER__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define _AC(X,Y) (X##Y) +#define _AT(T,X) ((T)(X)) +#endif /* !__ASSEMBLER__*/ + +#define _BITUL(x) (_AC(1,UL) << (x)) +#define _BITULL(x) (_AC(1,ULL) << (x)) + +#endif /* _NUCLEI_CONST_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/riscv_encoding.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/riscv_encoding.h new file mode 100644 index 0000000..fa823eb --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/drivers/riscv_encoding.h @@ -0,0 +1,1368 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_PUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_VM 0x1F000000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS64_SD 0x8000000000000000 + + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_PUM 0x00040000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define MIE_SSIE MIP_SSIP +#define MIE_HSIE MIP_HSIP +#define MIE_MSIE MIP_MSIP +#define MIE_STIE MIP_STIP +#define MIE_HTIE MIP_HTIP +#define MIE_MTIE MIP_MTIP +#define MIE_SEIE MIP_SEIP +#define MIE_HEIE MIP_HEIP +#define MIE_MEIE MIP_MEIP + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define VM_MBARE 0 +#define VM_MBB 1 +#define VM_MBBID 2 +#define VM_SV32 8 +#define VM_SV39 9 +#define VM_SV48 10 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define DEFAULT_NMIVEC 0x00001004 +#define DEFAULT_MTVEC 0x00001010 +#define CONFIG_STRING_ADDR 0x0000100C +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#ifdef __riscv64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_fpu(reg) ({ unsigned long __tmp; \ + asm volatile ("fmv.x.w %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_fpu(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("fmv.w.x " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("fmv.w.x " #reg ", %0" :: "r"(val)); }) + + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ + else \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + + + + + + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_HRET 0x20200073 +#define MASK_HRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VM 0x10400073 +#define MASK_SFENCE_VM 0xfff07fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_S 0xe0000053 +#define MASK_FMV_X_S 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_S_X 0xf0000053 +#define MASK_FMV_S_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_SBADADDR 0x143 +#define CSR_SIP 0x144 +#define CSR_SPTBR 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MIP 0x344 +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MUCOUNTEREN 0x320 +#define CSR_MSCOUNTEREN 0x321 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f + + +#define CSR_MTVT 0x307 +#define CSR_MNXTI 0x345 + +#define CSR_MCOUNTINHIBIT 0x320 + +#define CSR_MNVEC 0x7C3 + +#define CSR_MTVT2 0x7EC +#define CSR_JALMNXTI 0x7ED +#define CSR_PUSHMCAUSE 0x7EE +#define CSR_PUSHMEPC 0x7EF +#define CSR_PUSHMSUBM 0x7EB + +#define CSR_WFE 0x810 +#define CSR_SLEEPVALUE 0x811 +#define CSR_TXEVT 0x812 + +#define CSR_MMISC_CTL 0x7d0 +#define CSR_MSUBM 0x7c4 + + +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, +MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, +MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, +MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, +MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +#endif + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/GD32VF103x4.lds b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/GD32VF103x4.lds new file mode 100644 index 0000000..fc3d331 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/GD32VF103x4.lds @@ -0,0 +1,175 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + /* Run in FLASH */ + flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 16k + ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 6k + + /* Run in RAM */ +/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 4k + ram (wxa!ri) : ORIGIN = 0x20001000, LENGTH = 2K +*/ +} + + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 1K; + + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash + + .ilalign : + { + . = ALIGN(4); + PROVIDE( _ilm_lma = . ); + } >flash AT>flash + + .ialign : + { + PROVIDE( _ilm = . ); + } >flash AT>flash + + .text : + { + *(.rodata .rodata.*) + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash + + . = ALIGN(4); + + PROVIDE (__etext = .); + PROVIDE (_etext = .);/*0x80022c8*/ + PROVIDE (etext = .);/*0x80022c8*/ + PROVIDE( _eilm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash + + . = ALIGN(4); + PROVIDE( _eilm = . ); + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash + + + .data : + { + *(.rdata) + + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); /*0X200052A0 0X200002A0*/ + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram + + . = ALIGN(8); + PROVIDE( _end = . ); /*0X2000,0340*/ + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/GD32VF103x6.lds b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/GD32VF103x6.lds new file mode 100644 index 0000000..3cfe58a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/GD32VF103x6.lds @@ -0,0 +1,175 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + /* Run in FLASH */ + flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 32k + ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 10k + + /* Run in RAM */ +/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 7k + ram (wxa!ri) : ORIGIN = 0x20001C00, LENGTH = 3K +*/ +} + + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 1K; + + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash + + .ilalign : + { + . = ALIGN(4); + PROVIDE( _ilm_lma = . ); + } >flash AT>flash + + .ialign : + { + PROVIDE( _ilm = . ); + } >flash AT>flash + + .text : + { + *(.rodata .rodata.*) + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash + + . = ALIGN(4); + + PROVIDE (__etext = .); + PROVIDE (_etext = .);/*0x80022c8*/ + PROVIDE (etext = .);/*0x80022c8*/ + PROVIDE( _eilm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash + + . = ALIGN(4); + PROVIDE( _eilm = . ); + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash + + + .data : + { + *(.rdata) + + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); /*0X200052A0 0X200002A0*/ + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram + + . = ALIGN(8); + PROVIDE( _end = . ); /*0X2000,0340*/ + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/GD32VF103x8.lds b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/GD32VF103x8.lds new file mode 100644 index 0000000..a10769d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/GD32VF103x8.lds @@ -0,0 +1,175 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + /* Run in FLASH */ + flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 64k + ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 20k + + /* Run in RAM */ +/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 15k + ram (wxa!ri) : ORIGIN = 0x20003C00, LENGTH = 5K +*/ +} + + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash + + .ilalign : + { + . = ALIGN(4); + PROVIDE( _ilm_lma = . ); + } >flash AT>flash + + .ialign : + { + PROVIDE( _ilm = . ); + } >flash AT>flash + + .text : + { + *(.rodata .rodata.*) + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash + + . = ALIGN(4); + + PROVIDE (__etext = .); + PROVIDE (_etext = .);/*0x80022c8*/ + PROVIDE (etext = .);/*0x80022c8*/ + PROVIDE( _eilm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash + + . = ALIGN(4); + PROVIDE( _eilm = . ); + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash + + + .data : + { + *(.rdata) + + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); /*0X200052A0 0X200002A0*/ + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram + + . = ALIGN(8); + PROVIDE( _end = . ); /*0X2000,0340*/ + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/GD32VF103xB.lds b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/GD32VF103xB.lds new file mode 100644 index 0000000..1c32e64 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/GD32VF103xB.lds @@ -0,0 +1,175 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + /* Run in FLASH */ + flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 128k + ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K + + /* Run in RAM */ +/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 24k + ram (wxa!ri) : ORIGIN = 0x20006000, LENGTH = 8K +*/ +} + + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash + + .ilalign : + { + . = ALIGN(4); + PROVIDE( _ilm_lma = . ); + } >flash AT>flash + + .ialign : + { + PROVIDE( _ilm = . ); + } >flash AT>flash + + .text : + { + *(.rodata .rodata.*) + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash + + . = ALIGN(4); + + PROVIDE (__etext = .); + PROVIDE (_etext = .);/*0x80022c8*/ + PROVIDE (etext = .);/*0x80022c8*/ + PROVIDE( _eilm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash + + . = ALIGN(4); + PROVIDE( _eilm = . ); + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash + + + .data : + { + *(.rdata) + + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); /*0X200052A0 0X200002A0*/ + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram + + . = ALIGN(8); + PROVIDE( _end = . ); /*0X2000,0340*/ + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/entry.S b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/entry.S new file mode 100644 index 0000000..a95f968 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/entry.S @@ -0,0 +1,286 @@ +// See LICENSE for license details + +#ifndef ENTRY_S +#define ENTRY_S + +#include "riscv_encoding.h" +#include "riscv_bits.h" +#include "n200_eclic.h" +#include "n200_timer.h" + +############################################### +############################################### +# Disable Interrupt +# +.macro DISABLE_MIE + csrc CSR_MSTATUS, MSTATUS_MIE +.endm + + +############################################### +############################################### +#Save caller registers +.macro SAVE_CONTEXT + +#ifdef __riscv_flen + #if (__riscv_flen==64 ) + addi sp, sp, -20*REGBYTES - 20*FPREGBYTES + #else + addi sp, sp, -20*REGBYTES + #endif +#else + addi sp, sp, -20*REGBYTES +#endif + STORE x1, 0*REGBYTES(sp) + STORE x4, 1*REGBYTES(sp) + STORE x5, 2*REGBYTES(sp) + STORE x6, 3*REGBYTES(sp) + STORE x7, 4*REGBYTES(sp) + STORE x10, 5*REGBYTES(sp) + STORE x11, 6*REGBYTES(sp) + STORE x12, 7*REGBYTES(sp) + STORE x13, 8*REGBYTES(sp) + STORE x14, 9*REGBYTES(sp) + STORE x15, 10*REGBYTES(sp) +#ifndef __riscv_32e + STORE x16, 11*REGBYTES(sp) + STORE x17, 12*REGBYTES(sp) + STORE x28, 13*REGBYTES(sp) + STORE x29, 14*REGBYTES(sp) + STORE x30, 15*REGBYTES(sp) + STORE x31, 16*REGBYTES(sp) +#endif + +#ifdef __riscv_flen + #if (__riscv_flen == 64) + FPSTORE f0, (20*REGBYTES + 0*FPREGBYTES)(sp) + FPSTORE f1, (20*REGBYTES + 1*FPREGBYTES)(sp) + FPSTORE f2, (20*REGBYTES + 2*FPREGBYTES)(sp) + FPSTORE f3, (20*REGBYTES + 3*FPREGBYTES)(sp) + FPSTORE f4, (20*REGBYTES + 4*FPREGBYTES)(sp) + FPSTORE f5, (20*REGBYTES + 5*FPREGBYTES)(sp) + FPSTORE f6, (20*REGBYTES + 6*FPREGBYTES)(sp) + FPSTORE f7, (20*REGBYTES + 7*FPREGBYTES)(sp) + FPSTORE f10, (20*REGBYTES + 8*FPREGBYTES)(sp) + FPSTORE f11, (20*REGBYTES + 9*FPREGBYTES)(sp) + FPSTORE f12, (20*REGBYTES + 10*FPREGBYTES)(sp) + FPSTORE f13, (20*REGBYTES + 11*FPREGBYTES)(sp) + FPSTORE f14, (20*REGBYTES + 12*FPREGBYTES)(sp) + FPSTORE f15, (20*REGBYTES + 13*FPREGBYTES)(sp) + FPSTORE f16, (20*REGBYTES + 14*FPREGBYTES)(sp) + FPSTORE f17, (20*REGBYTES + 15*FPREGBYTES)(sp) + FPSTORE f28, (20*REGBYTES + 16*FPREGBYTES)(sp) + FPSTORE f29, (20*REGBYTES + 17*FPREGBYTES)(sp) + FPSTORE f30, (20*REGBYTES + 18*FPREGBYTES)(sp) + FPSTORE f31, (20*REGBYTES + 19*FPREGBYTES)(sp) + #endif +#endif + + +.endm + + +############################################### +############################################### +#restore caller registers +.macro RESTORE_CONTEXT + LOAD x1, 0*REGBYTES(sp) + LOAD x4, 1*REGBYTES(sp) + LOAD x5, 2*REGBYTES(sp) + LOAD x6, 3*REGBYTES(sp) + LOAD x7, 4*REGBYTES(sp) + LOAD x10, 5*REGBYTES(sp) + LOAD x11, 6*REGBYTES(sp) + LOAD x12, 7*REGBYTES(sp) + LOAD x13, 8*REGBYTES(sp) + LOAD x14, 9*REGBYTES(sp) + LOAD x15, 10*REGBYTES(sp) +#ifndef __riscv_32e + LOAD x16, 11*REGBYTES(sp) + LOAD x17, 12*REGBYTES(sp) + LOAD x28, 13*REGBYTES(sp) + LOAD x29, 14*REGBYTES(sp) + LOAD x30, 15*REGBYTES(sp) + LOAD x31, 16*REGBYTES(sp) +#endif + + +#ifdef __riscv_flen + #if (__riscv_flen==64) +/* Restore fp caller registers */ + FPLOAD f0, (20*REGBYTES + 0*FPREGBYTES)(sp) + FPLOAD f1, (20*REGBYTES + 1*FPREGBYTES)(sp) + FPLOAD f2, (20*REGBYTES + 2*FPREGBYTES)(sp) + FPLOAD f3, (20*REGBYTES + 3*FPREGBYTES)(sp) + FPLOAD f4, (20*REGBYTES + 4*FPREGBYTES)(sp) + FPLOAD f5, (20*REGBYTES + 5*FPREGBYTES)(sp) + FPLOAD f6, (20*REGBYTES + 6*FPREGBYTES)(sp) + FPLOAD f7, (20*REGBYTES + 7*FPREGBYTES)(sp) + FPLOAD f10, (20*REGBYTES + 8*FPREGBYTES)(sp) + FPLOAD f11, (20*REGBYTES + 9*FPREGBYTES)(sp) + FPLOAD f12, (20*REGBYTES + 10*FPREGBYTES)(sp) + FPLOAD f13, (20*REGBYTES + 11*FPREGBYTES)(sp) + FPLOAD f14, (20*REGBYTES + 12*FPREGBYTES)(sp) + FPLOAD f15, (20*REGBYTES + 13*FPREGBYTES)(sp) + FPLOAD f16, (20*REGBYTES + 14*FPREGBYTES)(sp) + FPLOAD f17, (20*REGBYTES + 15*FPREGBYTES)(sp) + FPLOAD f28, (20*REGBYTES + 16*FPREGBYTES)(sp) + FPLOAD f29, (20*REGBYTES + 17*FPREGBYTES)(sp) + FPLOAD f30, (20*REGBYTES + 18*FPREGBYTES)(sp) + FPLOAD f31, (20*REGBYTES + 19*FPREGBYTES)(sp) + #endif +#endif + + +#ifdef __riscv_flen + #if(__riscv_flen == 64 ) + addi sp, sp, 20*REGBYTES + 20*FPREGBYTES + #else + addi sp, sp, 20*REGBYTES + #endif +#else +// De-allocate the stack space + addi sp, sp, 20*REGBYTES +#endif +.endm + +############################################### +############################################### +#restore caller registers +.macro RESTORE_CONTEXT_EXCPT_X5 + LOAD x1, 0*REGBYTES(sp) + LOAD x6, 2*REGBYTES(sp) + LOAD x7, 3*REGBYTES(sp) + LOAD x10, 4*REGBYTES(sp) + LOAD x11, 5*REGBYTES(sp) + LOAD x12, 6*REGBYTES(sp) + LOAD x13, 7*REGBYTES(sp) + LOAD x14, 8*REGBYTES(sp) + LOAD x15, 9*REGBYTES(sp) +#ifndef __riscv_32e + LOAD x16, 10*REGBYTES(sp) + LOAD x17, 11*REGBYTES(sp) + LOAD x28, 12*REGBYTES(sp) + LOAD x29, 13*REGBYTES(sp) + LOAD x30, 14*REGBYTES(sp) + LOAD x31, 15*REGBYTES(sp) +#endif +.endm + +############################################### +############################################### +#restore caller registers +.macro RESTORE_CONTEXT_ONLY_X5 + LOAD x5, 1*REGBYTES(sp) +.endm + +############################################### +############################################### +# Save the mepc and mstatus +# +.macro SAVE_EPC_STATUS + csrr x5, CSR_MEPC + STORE x5, 16*REGBYTES(sp) + csrr x5, CSR_MSTATUS + STORE x5, 17*REGBYTES(sp) + csrr x5, CSR_MSUBM + STORE x5, 18*REGBYTES(sp) +.endm + +############################################### +############################################### +# Restore the mepc and mstatus +# +.macro RESTORE_EPC_STATUS + LOAD x5, 16*REGBYTES(sp) + csrw CSR_MEPC, x5 + LOAD x5, 17*REGBYTES(sp) + csrw CSR_MSTATUS, x5 + LOAD x5, 18*REGBYTES(sp) + csrw CSR_MSUBM, x5 +.endm + + + +############################################### +############################################### +// Trap entry point +// + .section .text.trap + .align 6// In CLIC mode, the trap entry must be 64bytes aligned + .global trap_entry +.weak trap_entry +trap_entry: + // Allocate the stack space + // addi sp, sp, -19*REGBYTES + + // Save the caller saving registers (context) + SAVE_CONTEXT + // Save the MEPC/Mstatus/Msubm reg + SAVE_EPC_STATUS + + // Set the function argument + csrr a0, mcause + mv a1, sp + // Call the function + call handle_trap + + // Restore the MEPC/Mstatus/Msubm reg + RESTORE_EPC_STATUS + // Restore the caller saving registers (context) + RESTORE_CONTEXT + + // De-allocate the stack space + // addi sp, sp, 19*REGBYTES + // Return to regular code + mret + + +############################################### +############################################### +// IRQ entry point +// + .section .text.irq + .align 2 + .global irq_entry +.weak irq_entry +irq_entry: // -------------> This label will be set to MTVT2 register + // Allocate the stack space + + + SAVE_CONTEXT// Save 16 regs + + //------This special CSR read operation, which is actually use mcause as operand to directly store it to memory + csrrwi x0, CSR_PUSHMCAUSE, 17 + //------This special CSR read operation, which is actually use mepc as operand to directly store it to memory + csrrwi x0, CSR_PUSHMEPC, 18 + //------This special CSR read operation, which is actually use Msubm as operand to directly store it to memory + csrrwi x0, CSR_PUSHMSUBM, 19 + +service_loop: + //------This special CSR read/write operation, which is actually Claim the CLIC to find its pending highest + // ID, if the ID is not 0, then automatically enable the mstatus.MIE, and jump to its vector-entry-label, and + // update the link register + csrrw ra, CSR_JALMNXTI, ra + + //RESTORE_CONTEXT_EXCPT_X5 + + #---- Critical section with interrupts disabled ----------------------- + DISABLE_MIE # Disable interrupts + + LOAD x5, 19*REGBYTES(sp) + csrw CSR_MSUBM, x5 + LOAD x5, 18*REGBYTES(sp) + csrw CSR_MEPC, x5 + LOAD x5, 17*REGBYTES(sp) + csrw CSR_MCAUSE, x5 + + + RESTORE_CONTEXT + + + // Return to regular code + mret + + +#endif \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/handlers.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/handlers.c new file mode 100644 index 0000000..0d5132f --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/handlers.c @@ -0,0 +1,32 @@ +//See LICENSE for license details. +#include +#include +#include +#include "riscv_encoding.h" +#include "n200_func.h" + +__attribute__((weak)) uintptr_t handle_nmi() +{ + write(1, "nmi\n", 5); + _exit(1); + return 0; +} + + +__attribute__((weak)) uintptr_t handle_trap(uintptr_t mcause, uintptr_t sp) +{ + if(mcause == 0xFFF) { + handle_nmi(); + } + write(1, "trap\n", 5); + //printf("In trap handler, the mcause is %d\n", mcause); + //printf("In trap handler, the mepc is 0x%x\n", read_csr(mepc)); + //printf("In trap handler, the mtval is 0x%x\n", read_csr(mbadaddr)); + _exit(mcause); + return 0; +} + + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/init.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/init.c new file mode 100644 index 0000000..39a72ab --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/init.c @@ -0,0 +1,34 @@ +//See LICENSE for license details. +#include +#include +#include +#include +#include "riscv_encoding.h" +#include "n200_func.h" + +extern uint32_t disable_mcycle_minstret(); +void _init() +{ + SystemInit(); + + //ECLIC init + eclic_init(ECLIC_NUM_INTERRUPTS); + eclic_mode_enable(); + + //printf("After ECLIC mode enabled, the mtvec value is %x \n\n\r", read_csr(mtvec)); + + // // It must be NOTED: + // // * In the RISC-V arch, if user mode and PMP supported, then by default if PMP is not configured + // // with valid entries, then user mode cannot access any memory, and cannot execute any instructions. + // // * So if switch to user-mode and still want to continue, then you must configure PMP first + //pmp_open_all_space(); + //switch_m2u_mode(); + + /* Before enter into main, add the cycle/instret disable by default to save power, + only use them when needed to measure the cycle/instret */ + disable_mcycle_minstret(); +} + +void _fini() +{ +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/start.S b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/start.S new file mode 100644 index 0000000..d54d01f --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/start.S @@ -0,0 +1,258 @@ +// See LICENSE for license details. + +#include "riscv_encoding.h" + + .section .init + + .weak eclic_msip_handler + .weak eclic_mtip_handler + .weak eclic_bwei_handler + .weak eclic_pmovi_handler + .weak WWDGT_IRQHandler + .weak LVD_IRQHandler + .weak TAMPER_IRQHandler + .weak RTC_IRQHandler + .weak FMC_IRQHandler + .weak RCU_IRQHandler + .weak EXTI0_IRQHandler + .weak EXTI1_IRQHandler + .weak EXTI2_IRQHandler + .weak EXTI3_IRQHandler + .weak EXTI4_IRQHandler + .weak DMA0_Channel0_IRQHandler + .weak DMA0_Channel1_IRQHandler + .weak DMA0_Channel2_IRQHandler + .weak DMA0_Channel3_IRQHandler + .weak DMA0_Channel4_IRQHandler + .weak DMA0_Channel5_IRQHandler + .weak DMA0_Channel6_IRQHandler + .weak ADC0_1_IRQHandler + .weak CAN0_TX_IRQHandler + .weak CAN0_RX0_IRQHandler + .weak CAN0_RX1_IRQHandler + .weak CAN0_EWMC_IRQHandler + .weak EXTI5_9_IRQHandler + .weak TIMER0_BRK_IRQHandler + .weak TIMER0_UP_IRQHandler + .weak TIMER0_TRG_CMT_IRQHandler + .weak TIMER0_Channel_IRQHandler + .weak TIMER1_IRQHandler + .weak TIMER2_IRQHandler + .weak TIMER3_IRQHandler + .weak I2C0_EV_IRQHandler + .weak I2C0_ER_IRQHandler + .weak I2C1_EV_IRQHandler + .weak I2C1_ER_IRQHandler + .weak SPI0_IRQHandler + .weak SPI1_IRQHandler + .weak USART0_IRQHandler + .weak USART1_IRQHandler + .weak USART2_IRQHandler + .weak EXTI10_15_IRQHandler + .weak RTC_Alarm_IRQHandler + .weak USBFS_WKUP_IRQHandler + .weak EXMC_IRQHandler + .weak TIMER4_IRQHandler + .weak SPI2_IRQHandler + .weak UART3_IRQHandler + .weak UART4_IRQHandler + .weak TIMER5_IRQHandler + .weak TIMER6_IRQHandler + .weak DMA1_Channel0_IRQHandler + .weak DMA1_Channel1_IRQHandler + .weak DMA1_Channel2_IRQHandler + .weak DMA1_Channel3_IRQHandler + .weak DMA1_Channel4_IRQHandler + .weak CAN1_TX_IRQHandler + .weak CAN1_RX0_IRQHandler + .weak CAN1_RX1_IRQHandler + .weak CAN1_EWMC_IRQHandler + .weak USBFS_IRQHandler + +vector_base: + j _start + .align 2 + .word 0 + .word 0 + .word eclic_msip_handler + .word 0 + .word 0 + .word 0 + .word eclic_mtip_handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word eclic_bwei_handler + .word eclic_pmovi_handler + .word WWDGT_IRQHandler + .word LVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FMC_IRQHandler + .word RCU_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA0_Channel0_IRQHandler + .word DMA0_Channel1_IRQHandler + .word DMA0_Channel2_IRQHandler + .word DMA0_Channel3_IRQHandler + .word DMA0_Channel4_IRQHandler + .word DMA0_Channel5_IRQHandler + .word DMA0_Channel6_IRQHandler + .word ADC0_1_IRQHandler + .word CAN0_TX_IRQHandler + .word CAN0_RX0_IRQHandler + .word CAN0_RX1_IRQHandler + .word CAN0_EWMC_IRQHandler + .word EXTI5_9_IRQHandler + .word TIMER0_BRK_IRQHandler + .word TIMER0_UP_IRQHandler + .word TIMER0_TRG_CMT_IRQHandler + .word TIMER0_Channel_IRQHandler + .word TIMER1_IRQHandler + .word TIMER2_IRQHandler + .word TIMER3_IRQHandler + .word I2C0_EV_IRQHandler + .word I2C0_ER_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word SPI0_IRQHandler + .word SPI1_IRQHandler + .word USART0_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word EXTI10_15_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBFS_WKUP_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word EXMC_IRQHandler + .word 0 + .word TIMER4_IRQHandler + .word SPI2_IRQHandler + .word UART3_IRQHandler + .word UART4_IRQHandler + .word TIMER5_IRQHandler + .word TIMER6_IRQHandler + .word DMA1_Channel0_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word 0 + .word 0 + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_EWMC_IRQHandler + .word USBFS_IRQHandler + + .globl _start + .type _start,@function + +_start: + + csrc CSR_MSTATUS, MSTATUS_MIE + /* Jump to logical address first to ensure correct operation of RAM region */ + la a0, _start + li a1, 1 + slli a1, a1, 29 + bleu a1, a0, _start0800 + srli a1, a1, 2 + bleu a1, a0, _start0800 + la a0, _start0800 + add a0, a0, a1 + jr a0 + +_start0800: + + /* Set the the NMI base to share with mtvec by setting CSR_MMISC_CTL */ + li t0, 0x200 + csrs CSR_MMISC_CTL, t0 + + /* Intial the mtvt*/ + la t0, vector_base + csrw CSR_MTVT, t0 + + /* Intial the mtvt2 and enable it*/ + la t0, irq_entry + csrw CSR_MTVT2, t0 + csrs CSR_MTVT2, 0x1 + + /* Intial the CSR MTVEC for the Trap ane NMI base addr*/ + la t0, trap_entry + csrw CSR_MTVEC, t0 + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, MSTATUS_FS + csrs mstatus, t0 + csrw fcsr, x0 +#endif + +.option push +.option norelax + la gp, __global_pointer$ +.option pop + la sp, _sp + + /* Load data section */ + la a0, _data_lma + la a1, _data + la a2, _edata + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b +2: + /* Clear bss section */ + la a0, __bss_start + la a1, _end + bgeu a0, a1, 2f +1: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, 1b +2: + /*enable mcycle_minstret*/ + csrci CSR_MCOUNTINHIBIT, 0x5 + /* Call global constructors */ + la a0, __libc_fini_array + call atexit + call __libc_init_array + + + /* argc = argv = 0 */ + li a0, 0 + li a1, 0 + call main + tail exit + +1: + j 1b + + .global disable_mcycle_minstret +disable_mcycle_minstret: + csrsi CSR_MCOUNTINHIBIT, 0x5 + ret + + .global enable_mcycle_minstret +enable_mcycle_minstret: + csrci CSR_MCOUNTINHIBIT, 0x5 + ret + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/your_printf.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/your_printf.c new file mode 100644 index 0000000..bbb95b6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/env_Eclipse/your_printf.c @@ -0,0 +1,5 @@ +int __wrap_printf(const char* fmt, ...) +{ + // You can implement your own printf to reduce the code size, because the printf is really a big function +} + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/_exit.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/_exit.c new file mode 100644 index 0000000..33467d0 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/_exit.c @@ -0,0 +1,17 @@ +/* See LICENSE of license details. */ + +#include + +#include "stub.h" + + +void _exit(int code) +{ + const char message[] = "\nProgram has exited with code:"; + + write(STDERR_FILENO, message, sizeof(message) - 1); + write_hex(STDERR_FILENO, code); + write(STDERR_FILENO, "\n", 1); + + for (;;); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/close.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/close.c new file mode 100644 index 0000000..e50362e --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/close.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int _close(int fd) +{ + return _stub(EBADF); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/fstat.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/fstat.c new file mode 100644 index 0000000..c30d27c --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/fstat.c @@ -0,0 +1,16 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include "stub.h" + +int _fstat(int fd, struct stat* st) +{ + if (isatty(fd)) { + st->st_mode = S_IFCHR; + return 0; + } + + return _stub(EBADF); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/isatty.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/isatty.c new file mode 100644 index 0000000..a590eba --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/isatty.c @@ -0,0 +1,11 @@ +/* See LICENSE of license details. */ + +#include + +int _isatty(int fd) +{ + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + return 1; + + return 0; +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/lseek.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/lseek.c new file mode 100644 index 0000000..f519b51 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/lseek.c @@ -0,0 +1,14 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include "stub.h" + +off_t _lseek(int fd, off_t ptr, int dir) +{ + if (isatty(fd)) + return 0; + + return _stub(EBADF); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/read.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/read.c new file mode 100644 index 0000000..c874f67 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/read.c @@ -0,0 +1,13 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include + +#include "stub.h" + +ssize_t _read(int fd, void* ptr, size_t len) +{ + return _stub(EBADF); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/sbrk.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/sbrk.c new file mode 100644 index 0000000..7d28568 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/sbrk.c @@ -0,0 +1,16 @@ +/* See LICENSE of license details. */ + +#include + +void *_sbrk(ptrdiff_t incr) +{ + extern char _end[]; + extern char _heap_end[]; + static char *curbrk = _end; + + if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) + return NULL - 1; + + curbrk += incr; + return curbrk - incr; +} \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/stub.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/stub.h new file mode 100644 index 0000000..88039e5 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/stub.h @@ -0,0 +1,16 @@ +/* See LICENSE of license details. */ +#ifndef _NUCLEI_SYS_STUB_H +#define _NUCLEI_SYS_STUB_H + +#include +#include + +void write_hex(int fd, unsigned long int hex); + +static inline int _stub(int err) +{ + return -1; +} + + +#endif /* _NUCLEI_SYS_STUB_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/write.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/write.c new file mode 100644 index 0000000..8836b70 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/write.c @@ -0,0 +1,47 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include +#include +#include + +#include "stub.h" +#include "gd32vf103.h" + +typedef unsigned int size_t; + +extern int _put_char(int ch) __attribute__((weak)); + +ssize_t _write(int fd, const void* ptr, size_t len) { + const uint8_t * current = (const uint8_t *) ptr; + +// if (isatty(fd)) + { + for (size_t jj = 0; jj < len; jj++) { + _put_char(current[jj]); + + if (current[jj] == '\n') { + _put_char('\r'); + } + } + return len; + } + + return _stub(EBADF); +} + +int puts(const char* string) { + return _write(0, (const void *) string, strlen(string)); +} + +int _put_char(int ch) +{ + usart_data_transmit(USART0, (uint8_t) ch ); + while (usart_flag_get(USART0, USART_FLAG_TBE)== RESET){ + } + + return ch; +} + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/write_hex.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/write_hex.c new file mode 100644 index 0000000..f7aa9a4 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Firmware/RISCV/stubs/write_hex.c @@ -0,0 +1,18 @@ +/* See LICENSE of license details. */ + +#include +#include + +void write_hex(int fd, unsigned long int hex) +{ + uint8_t ii; + uint8_t jj; + char towrite; + write(fd , "0x", 2); + for (ii = sizeof(unsigned long int) * 2 ; ii > 0; ii--) { + jj = ii - 1; + uint8_t digit = ((hex & (0xF << (jj*4))) >> (jj*4)); + towrite = digit < 0xA ? ('0' + digit) : ('A' + (digit - 0xA)); + write(fd, &towrite, 1); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/eclipse/.cproject b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/eclipse/.cproject new file mode 100644 index 0000000..0dd7ab6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/eclipse/.cproject @@ -0,0 +1,700 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/eclipse/.project b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/eclipse/.project new file mode 100644 index 0000000..ac37c5b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/eclipse/.project @@ -0,0 +1,333 @@ + + + GD32VF103 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Application + 2 + virtual:/virtual + + + Doc + 2 + virtual:/virtual + + + Peripherals + 2 + virtual:/virtual + + + RISCV + 2 + virtual:/virtual + + + Utilities + 2 + virtual:/virtual + + + Application/main.c + 1 + PARENT-1-PROJECT_LOC/main.c + + + Application/systick.c + 1 + PARENT-1-PROJECT_LOC/systick.c + + + Doc/readme.txt + 1 + PARENT-1-PROJECT_LOC/readme.txt + + + Peripherals/Source + 2 + virtual:/virtual + + + Peripherals/system_gd32vf103.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/system_gd32vf103.c + + + RISCV/drivers + 2 + virtual:/virtual + + + RISCV/env_Eclipse + 2 + virtual:/virtual + + + RISCV/stubs + 2 + virtual:/virtual + + + Utilities/gd32vf103v_eval.c + 1 + PARENT-2-PROJECT_LOC/Utilities/gd32vf103v_eval.c + + + Peripherals/Source/gd32vf103_adc.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c + + + Peripherals/Source/gd32vf103_bkp.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c + + + Peripherals/Source/gd32vf103_can.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_can.c + + + Peripherals/Source/gd32vf103_crc.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c + + + Peripherals/Source/gd32vf103_dac.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c + + + Peripherals/Source/gd32vf103_dbg.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c + + + Peripherals/Source/gd32vf103_dma.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c + + + Peripherals/Source/gd32vf103_eclic.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c + + + Peripherals/Source/gd32vf103_exmc.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c + + + Peripherals/Source/gd32vf103_exti.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c + + + Peripherals/Source/gd32vf103_fmc.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c + + + Peripherals/Source/gd32vf103_fwdgt.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c + + + Peripherals/Source/gd32vf103_gpio.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c + + + Peripherals/Source/gd32vf103_i2c.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c + + + Peripherals/Source/gd32vf103_pmu.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c + + + Peripherals/Source/gd32vf103_rcu.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c + + + Peripherals/Source/gd32vf103_rtc.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c + + + Peripherals/Source/gd32vf103_spi.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c + + + Peripherals/Source/gd32vf103_timer.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c + + + Peripherals/Source/gd32vf103_usart.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c + + + Peripherals/Source/gd32vf103_wwdgt.c + 1 + PARENT-2-PROJECT_LOC/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c + + + RISCV/drivers/n200_eclic.h + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/drivers/n200_eclic.h + + + RISCV/drivers/n200_func.c + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/drivers/n200_func.c + + + RISCV/drivers/n200_func.h + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/drivers/n200_func.h + + + RISCV/drivers/n200_timer.h + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/drivers/n200_timer.h + + + RISCV/drivers/riscv_bits.h + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/drivers/riscv_bits.h + + + RISCV/drivers/riscv_const.h + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/drivers/riscv_const.h + + + RISCV/drivers/riscv_encoding.h + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/drivers/riscv_encoding.h + + + RISCV/env_Eclipse/GD32VF103x4.lds + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/env_Eclipse/GD32VF103x4.lds + + + RISCV/env_Eclipse/GD32VF103x6.lds + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/env_Eclipse/GD32VF103x6.lds + + + RISCV/env_Eclipse/GD32VF103x8.lds + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/env_Eclipse/GD32VF103x8.lds + + + RISCV/env_Eclipse/GD32VF103xB.lds + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/env_Eclipse/GD32VF103xB.lds + + + RISCV/env_Eclipse/entry.S + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/env_Eclipse/entry.S + + + RISCV/env_Eclipse/handlers.c + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/env_Eclipse/handlers.c + + + RISCV/env_Eclipse/init.c + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/env_Eclipse/init.c + + + RISCV/env_Eclipse/start.S + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/env_Eclipse/start.S + + + RISCV/env_Eclipse/your_printf.c + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/env_Eclipse/your_printf.c + + + RISCV/stubs/_exit.c + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/stubs/_exit.c + + + RISCV/stubs/close.c + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/stubs/close.c + + + RISCV/stubs/fstat.c + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/stubs/fstat.c + + + RISCV/stubs/isatty.c + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/stubs/isatty.c + + + RISCV/stubs/lseek.c + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/stubs/lseek.c + + + RISCV/stubs/read.c + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/stubs/read.c + + + RISCV/stubs/sbrk.c + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/stubs/sbrk.c + + + RISCV/stubs/stub.h + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/stubs/stub.h + + + RISCV/stubs/write.c + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/stubs/write.c + + + RISCV/stubs/write_hex.c + 1 + PARENT-2-PROJECT_LOC/Firmware/RISCV/stubs/write_hex.c + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/eclipse/.settings/language.settings.xml b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/eclipse/.settings/language.settings.xml new file mode 100644 index 0000000..648135c --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/eclipse/.settings/language.settings.xml @@ -0,0 +1,47 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/eclipse/.settings/org.eclipse.cdt.codan.core.prefs b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/eclipse/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..067d6fd --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/eclipse/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,73 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.codan.checkers.errnoreturn=Warning +org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false} +org.eclipse.cdt.codan.checkers.errreturnvalue=Error +org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"} +org.eclipse.cdt.codan.checkers.nocommentinside=-Error +org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"} +org.eclipse.cdt.codan.checkers.nolinecomment=-Error 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+environment/project/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1146769190.1656381579/CWD/operation=replace +environment/project/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1146769190.1656381579/CWD/value=E\:\\Delivered_Pattern\\GD32501\\fw32501\\GD32VF103_Firmware_Library_V1.0.0\\project\\eclipse\\FLASH +environment/project/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1146769190.1656381579/PWD/delimiter=; +environment/project/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1146769190.1656381579/PWD/operation=replace +environment/project/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1146769190.1656381579/PWD/value=E\:\\Delivered_Pattern\\GD32501\\fw32501\\GD32VF103_Firmware_Library_V1.0.0\\project\\eclipse\\FLASH +environment/project/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1146769190.1656381579/append=true +environment/project/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1146769190.1656381579/appendContributed=true diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/gd32vf103_libopt.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/gd32vf103_libopt.h new file mode 100644 index 0000000..0381461 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/gd32vf103_libopt.h @@ -0,0 +1,61 @@ +/*! + \file gd32vf103_libopt.h + \brief library optional for gd32vf103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_LIBOPT_H +#define GD32VF103_LIBOPT_H + +#include "gd32vf103_adc.h" +#include "gd32vf103_bkp.h" +#include "gd32vf103_can.h" +#include "gd32vf103_crc.h" +#include "gd32vf103_dac.h" +#include "gd32vf103_dma.h" +#include "gd32vf103_eclic.h" +#include "gd32vf103_exmc.h" +#include "gd32vf103_exti.h" +#include "gd32vf103_fmc.h" +#include "gd32vf103_gpio.h" +#include "gd32vf103_i2c.h" +#include "gd32vf103_fwdgt.h" +#include "gd32vf103_dbg.h" +#include "gd32vf103_pmu.h" +#include "gd32vf103_rcu.h" +#include "gd32vf103_rtc.h" +#include "gd32vf103_spi.h" +#include "gd32vf103_timer.h" +#include "gd32vf103_usart.h" +#include "gd32vf103_wwdgt.h" +#include "n200_func.h" + +#endif /* GD32VF103_LIBOPT_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/main.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/main.c new file mode 100644 index 0000000..661eea8 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/main.c @@ -0,0 +1,71 @@ +/*! + \file main.c + \brief running led + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "gd32vf103v_eval.h" +#include "systick.h" +#include + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + gd_eval_led_init(LED1); + gd_eval_led_init(LED2); + gd_eval_led_init(LED3); + gd_eval_led_init(LED4); + + while(1){ + /* turn on led1, turn off led4 */ + gd_eval_led_on(LED1); + gd_eval_led_off(LED4); + delay_1ms(1000); + /* turn on led2, turn off led1 */ + gd_eval_led_on(LED2); + gd_eval_led_off(LED1); + delay_1ms(1000); + /* turn on led3, turn off led2 */ + gd_eval_led_on(LED3); + gd_eval_led_off(LED2); + delay_1ms(1000); + /* turn on led4, turn off led3 */ + gd_eval_led_on(LED4); + gd_eval_led_off(LED3); + delay_1ms(1000); + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/main.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/main.h new file mode 100644 index 0000000..9df3992 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/main.h @@ -0,0 +1,41 @@ +/*! + \file main.h + \brief the header file of main + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __MAIN_H +#define __MAIN_H + +/* led spark function */ +void led_spark(void); + +#endif /* __MAIN_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/readme.txt b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/readme.txt new file mode 100644 index 0000000..2ca093d --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/readme.txt @@ -0,0 +1,40 @@ +/*! + \file readme.txt + \brief description of running led example + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + This example is based on the GD32VF103V-EVAL-V1.0 board, it provides a description +of Running_led. After system start-up, firstly, LED1 on, then, LED2 on, four +LEDs can light periodically. + + On the GD32VF103V-EVAL-V1.0 board,LED1 connected to PC0, LED2 connected to PC2, LED3 +connected to PE0, LED4 connected to PE1. diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/systick.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/systick.c new file mode 100644 index 0000000..4296e59 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/systick.c @@ -0,0 +1,57 @@ +/*! + \file systick.c + \brief the systick configuration file + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103.h" +#include "systick.h" + +/*! + \brief delay a time in milliseconds + \param[in] count: count in milliseconds + \param[out] none + \retval none +*/ +void delay_1ms(uint32_t count) +{ + uint64_t start_mtime, delta_mtime; + + // Don't start measuruing until we see an mtime tick + uint64_t tmp = get_timer_value(); + do { + start_mtime = get_timer_value(); + } while (start_mtime == tmp); + + do { + delta_mtime = get_timer_value() - start_mtime; + }while(delta_mtime <(SystemCoreClock/4000.0 *count )); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/systick.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/systick.h new file mode 100644 index 0000000..9a74c22 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Template/systick.h @@ -0,0 +1,42 @@ +/*! + \file systick.h + \brief the header file of systick + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef SYS_TICK_H +#define SYS_TICK_H + +#include + +void delay_1ms(uint32_t count); + +#endif /* SYS_TICK_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Utilities/LCD_common/lcd_font.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Utilities/LCD_common/lcd_font.c new file mode 100644 index 0000000..5704bd8 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Utilities/LCD_common/lcd_font.c @@ -0,0 +1,711 @@ +/*! + \file lcd_font.c + \brief text fonts driver + + \version 2019-06-05, V1.0.0, demo for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "lcd_font.h" + +unsigned char const ascii_8x16[1536] = { +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x18,0x3C,0x3C,0x3C,0x18,0x18,0x18,0x00,0x18,0x18,0x00,0x00,0x00,0x00, +0x00,0x66,0x66,0x66,0x24,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x6C,0x6C,0xFE,0x6C,0x6C,0x6C,0xFE,0x6C,0x6C,0x00,0x00,0x00,0x00, +0x18,0x18,0x7C,0xC6,0xC2,0xC0,0x7C,0x06,0x86,0xC6,0x7C,0x18,0x18,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0xC2,0xC6,0x0C,0x18,0x30,0x60,0xC6,0x86,0x00,0x00,0x00,0x00, +0x00,0x00,0x38,0x6C,0x6C,0x38,0x76,0xDC,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00, +0x00,0x30,0x30,0x30,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x0C,0x18,0x30,0x30,0x30,0x30,0x30,0x30,0x18,0x0C,0x00,0x00,0x00,0x00, +0x00,0x00,0x30,0x18,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x18,0x30,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x66,0x3C,0xFF,0x3C,0x66,0x00,0x00,0x00,0x00,0x00,0x00, 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+0x00,0x00,0x00,0x00,0x10,0x38,0x6C,0xC6,0xC6,0xC6,0xFE,0x00,0x00,0x00,0x00,0x00 +}; + + + +/* ASCII Table: each character is 16 column (16dots large) and 24 raw (24 dots high) */ +const uint16_t ASCII_Table_16x24[] = +{ +/** + * @brief Space ' ' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '!' + */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '"' + */ + 0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '#' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60, + 0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318, + 0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000, +/** + * @brief '$' + */ + 0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C, + 0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C, + 0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000, +/** + * @brief '%' + */ + 0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611, + 0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460, + 0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000, +/** + * @brief '&' + */ + 0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0, + 0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06, + 0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ''' + */ + 0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '(' + */ + 0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060, + 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, + 0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000, +/** + * @brief ')' + */ + 0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300, + 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, + 0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000, +/** + * @brief '*' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '+' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ',' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, +/** + * @brief '-' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '.' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '/' + */ + 0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300, + 0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0, + 0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '0' + */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C, + 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '1' + */ + 0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '2' + */ + 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800, + 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, + 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '3' + */ + 0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600, + 0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18, + 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '4' + */ + 0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60, + 0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00, + 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '5' + */ + 0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC, + 0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18, + 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '6' + */ + 0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC, + 0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '7' + */ + 0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380, + 0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030, + 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '8' + */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638, + 0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38, + 0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '9' + */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C, + 0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C, + 0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ':' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ';' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000, +/** + * @brief '<' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0, + 0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '=' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '>' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0, + 0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '?' + */ + 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00, + 0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '@' + */ + 0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411, + 0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004, + 0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'A' + */ + 0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60, + 0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C, + 0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'B' + */ + 0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C, + 0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C, + 0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'C' + */ + 0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006, + 0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C, + 0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'D' + */ + 0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006, + 0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06, + 0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'E' + */ + 0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'F' + */ + 0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'G' + */ + 0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003, + 0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C, + 0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'H' + */ + 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'I' + */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'J' + */ + 0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, + 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738, + 0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'K' + */ + 0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6, + 0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806, + 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'L' + */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'M' + */ + 0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836, + 0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6, + 0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'N' + */ + 0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC, + 0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C, + 0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'O' + */ + 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003, + 0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C, + 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'P' + */ + 0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'Q' + */ + 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003, + 0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C, + 0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'R' + */ + 0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806, + 0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006, + 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'S' + */ + 0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C, + 0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C, + 0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'T' + */ + 0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'U' + */ + 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818, + 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'V' + */ + 0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C, + 0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360, + 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'W' + */ + 0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366, + 0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C, + 0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'X' + */ + 0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0, + 0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C, + 0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'Y' + */ + 0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660, + 0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'Z' + */ + 0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600, + 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006, + 0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '[' + */ + 0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, + 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, + 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000, +/** + * @brief '\' + */ + 0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0, + 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300, + 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ']' + */ + 0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, + 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, + 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000, +/** + * @brief '^' + */ + 0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630, + 0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '_' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ''' + */ + 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'a' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8, + 0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C, + 0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'b' + */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8, + 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38, + 0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'c' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0, + 0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30, + 0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'd' + */ + 0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0, + 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30, + 0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'e' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0, + 0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30, + 0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'f' + */ + 0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'g' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8, + 0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18, + 0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000, +/** + * @brief 'h' + */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8, + 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, + 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'i' + */ + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'j' + */ + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000, +/** + * @brief 'k' + */ + 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C, + 0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C, + 0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'l' + */ + 0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'm' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF, + 0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, + 0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'n' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8, + 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, + 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'o' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0, + 0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30, + 0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'p' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8, + 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38, + 0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000, +/** + * @brief 'q' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0, + 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30, + 0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000, +/** + * @brief 'r' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0, + 0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, + 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 's' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0, + 0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 't' + */ + 0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'u' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818, + 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38, + 0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'v' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18, + 0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360, + 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'w' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1, + 0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C, + 0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'x' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38, + 0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30, + 0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'y' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830, + 0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380, + 0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000, +/** + * @brief 'z' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC, + 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, + 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '{' + */ + 0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000, +/** + * @brief '|' + */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, +/** + * @brief '}' + */ + 0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000, +/** + * @brief '~' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +}; diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Utilities/LCD_common/lcd_font.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Utilities/LCD_common/lcd_font.h new file mode 100644 index 0000000..24d49e7 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Utilities/LCD_common/lcd_font.h @@ -0,0 +1,45 @@ +/*! + \file lcd_font.h + \brief the header file of LCD font + + \version 2019-06-05, V1.0.0, demo for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef LCD_FONT_H +#define LCD_FONT_H + +#include + +extern unsigned char const ascii_8x16[1536]; + +extern const uint16_t ASCII_Table_16x24[]; + +#endif /* LCD_FONT_H */ + diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Utilities/gd32vf103v_eval.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Utilities/gd32vf103v_eval.c new file mode 100644 index 0000000..688c9ed --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Utilities/gd32vf103v_eval.c @@ -0,0 +1,247 @@ +/*! + \file gd32vf103v_eval.c + \brief firmware functions to manage leds, keys, COM ports + + \version 2019-06-05, V1.0.0, demo for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103v_eval.h" + +/* private variables */ +static uint32_t GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, + LED3_GPIO_PORT, LED4_GPIO_PORT}; +static uint32_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN, LED4_PIN}; + +static rcu_periph_enum COM_CLK[COMn] = {EVAL_COM0_CLK, EVAL_COM1_CLK}; +static uint32_t COM_TX_PIN[COMn] = {EVAL_COM0_TX_PIN, EVAL_COM1_TX_PIN}; +static uint32_t COM_RX_PIN[COMn] = {EVAL_COM0_RX_PIN, EVAL_COM1_RX_PIN}; +static uint32_t COM_GPIO_PORT[COMn] = {EVAL_COM0_GPIO_PORT, EVAL_COM1_GPIO_PORT}; +static rcu_periph_enum COM_GPIO_CLK[COMn] = {EVAL_COM0_GPIO_CLK, EVAL_COM1_GPIO_CLK}; + +static rcu_periph_enum GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, + LED3_GPIO_CLK, LED4_GPIO_CLK}; + +static uint32_t KEY_PORT[KEYn] = {KEY_A_GPIO_PORT, + KEY_B_GPIO_PORT, + KEY_C_GPIO_PORT, + KEY_D_GPIO_PORT, + KEY_CET_GPIO_PORT}; +static uint32_t KEY_PIN[KEYn] = {KEY_A_PIN, + KEY_B_PIN, + KEY_C_PIN, + KEY_D_PIN, + KEY_CET_PIN}; +static rcu_periph_enum KEY_CLK[KEYn] = {KEY_A_GPIO_CLK, + KEY_B_GPIO_CLK, + KEY_C_GPIO_CLK, + KEY_D_GPIO_CLK, + KEY_CET_GPIO_CLK}; +static exti_line_enum KEY_EXTI_LINE[KEYn] = {KEY_A_EXTI_LINE, + KEY_B_EXTI_LINE, + KEY_C_EXTI_LINE, + KEY_D_EXTI_LINE, + KEY_CET_EXTI_LINE}; +static uint8_t KEY_PORT_SOURCE[KEYn] = {KEY_A_EXTI_PORT_SOURCE, + KEY_B_EXTI_PORT_SOURCE, + KEY_C_EXTI_PORT_SOURCE, + KEY_D_EXTI_PORT_SOURCE, + KEY_CET_EXTI_PORT_SOURCE}; +static uint8_t KEY_PIN_SOURCE[KEYn] = {KEY_A_EXTI_PIN_SOURCE, + KEY_B_EXTI_PIN_SOURCE, + KEY_C_EXTI_PIN_SOURCE, + KEY_D_EXTI_PIN_SOURCE, + KEY_CET_EXTI_PIN_SOURCE}; +static uint8_t KEY_IRQn[KEYn] = {KEY_A_EXTI_IRQn, + KEY_B_EXTI_IRQn, + KEY_C_EXTI_IRQn, + KEY_D_EXTI_IRQn, + KEY_CET_EXTI_IRQn}; + +/*! + \brief configure led GPIO + \param[in] lednum: specify the led to be configured + \arg LED1 + \arg LED2 + \arg LED3 + \arg LED4 + \param[out] none + \retval none +*/ +void gd_eval_led_init(led_typedef_enum lednum) +{ + /* enable the led clock */ + rcu_periph_clock_enable(GPIO_CLK[lednum]); + /* configure led GPIO port */ + gpio_init(GPIO_PORT[lednum], GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN[lednum]); + + GPIO_BC(GPIO_PORT[lednum]) = GPIO_PIN[lednum]; +} + +/*! + \brief turn on selected led + \param[in] lednum: specify the led to be turned on + \arg LED1 + \arg LED2 + \arg LED3 + \arg LED4 + \param[out] none + \retval none +*/ +void gd_eval_led_on(led_typedef_enum lednum) +{ + GPIO_BOP(GPIO_PORT[lednum]) = GPIO_PIN[lednum]; +} + +/*! + \brief turn off selected led + \param[in] lednum: specify the led to be turned off + \arg LED1 + \arg LED2 + \arg LED3 + \arg LED4 + \param[out] none + \retval none +*/ +void gd_eval_led_off(led_typedef_enum lednum) +{ + GPIO_BC(GPIO_PORT[lednum]) = GPIO_PIN[lednum]; +} + +/*! + \brief toggle selected led + \param[in] lednum: specify the led to be toggled + \arg LED1 + \arg LED2 + \arg LED3 + \arg LED4 + \param[out] none + \retval none +*/ +void gd_eval_led_toggle(led_typedef_enum lednum) +{ + gpio_bit_write(GPIO_PORT[lednum], GPIO_PIN[lednum], + (bit_status)(1-gpio_input_bit_get(GPIO_PORT[lednum], GPIO_PIN[lednum]))); +} + +/*! + \brief configure key + \param[in] key_num: specify the key to be configured + \arg KEY_A: wakeup key + \arg KEY_B: tamper key + \arg KEY_C: user key + \arg KEY_D: user key + \arg KEY_CET: user key + \param[in] key_mode: specify button mode + \arg KEY_MODE_GPIO: key will be used as simple IO + \arg KEY_MODE_EXTI: key will be connected to EXTI line with interrupt + \param[out] none + \retval none +*/ + +void gd_eval_key_init(key_typedef_enum key_num, keymode_typedef_enum key_mode) +{ + /* enable the key clock */ + rcu_periph_clock_enable(KEY_CLK[key_num]); + rcu_periph_clock_enable(RCU_AF); + + /* configure button pin as input */ + gpio_init(KEY_PORT[key_num], GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, KEY_PIN[key_num]); + + if (key_mode == KEY_MODE_EXTI) { + /* enable and set key EXTI interrupt to the lowest priority */ + eclic_global_interrupt_enable(); + eclic_irq_enable(KEY_IRQn[key_num],1, 1); + + /* connect key EXTI line to key GPIO pin */ + gpio_exti_source_select(KEY_PORT_SOURCE[key_num], KEY_PIN_SOURCE[key_num]); + + /* configure key EXTI line */ + exti_init(KEY_EXTI_LINE[key_num], EXTI_INTERRUPT, EXTI_TRIG_FALLING); + exti_interrupt_flag_clear(KEY_EXTI_LINE[key_num]); + } +} + +/*! + \brief return the selected key state + \param[in] key: specify the key to be checked + \arg KEY_A: wakeup key + \arg KEY_B: tamper key + \arg KEY_C: user key + \arg KEY_D: user key + \arg KEY_CET: user key + \param[out] none + \retval the key's GPIO pin value +*/ +uint8_t gd_eval_key_state_get(key_typedef_enum key) +{ + return gpio_input_bit_get(KEY_PORT[key], KEY_PIN[key]); +} + +/*! + \brief configure COM port + \param[in] com: COM on the board + \arg EVAL_COM0: COM0 on the board + \arg EVAL_COM1: COM1 on the board + \param[out] none + \retval none +*/ +void gd_eval_com_init(uint32_t com) +{ + uint32_t com_id = 0U; + if(EVAL_COM0 == com){ + com_id = 0U; + }else if(EVAL_COM1 == com){ + com_id = 1U; + } + + /* enable GPIO clock */ + rcu_periph_clock_enable(COM_GPIO_CLK[com_id]); + + /* enable USART clock */ + rcu_periph_clock_enable(COM_CLK[com_id]); + + /* connect port to USARTx_Tx */ + gpio_init(COM_GPIO_PORT[com_id], GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, COM_TX_PIN[com_id]); + + /* connect port to USARTx_Rx */ + gpio_init(COM_GPIO_PORT[com_id], GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, COM_RX_PIN[com_id]); + + /* USART configure */ + usart_deinit(com); + usart_baudrate_set(com, 115200U); + usart_word_length_set(com, USART_WL_8BIT); + usart_stop_bit_set(com, USART_STB_1BIT); + usart_parity_config(com, USART_PM_NONE); + usart_hardware_flow_rts_config(com, USART_RTS_DISABLE); + usart_hardware_flow_cts_config(com, USART_CTS_DISABLE); + usart_receive_config(com, USART_RECEIVE_ENABLE); + usart_transmit_config(com, USART_TRANSMIT_ENABLE); + usart_enable(com); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Utilities/gd32vf103v_eval.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Utilities/gd32vf103v_eval.h new file mode 100644 index 0000000..3a2fcb6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Utilities/gd32vf103v_eval.h @@ -0,0 +1,168 @@ +/*! + \file gd32vf103v_eval.h + \brief definitions for GD32VF103V_EVAL's leds, keys and COM ports hardware resources + + \version 2019-06-05, V1.0.0, demo for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103V_EVAL_H +#define GD32VF103V_EVAL_H + +#ifdef cplusplus + extern "C" { +#endif + +#include "gd32vf103.h" + +/* exported types */ +typedef enum +{ + LED1 = 0, + LED2 = 1, + LED3 = 2, + LED4 = 3 +} led_typedef_enum; + +typedef enum +{ + KEY_A = 0, + KEY_B = 1, + KEY_C = 2, + KEY_D = 3, + KEY_CET = 4 +} key_typedef_enum; + +typedef enum +{ + KEY_MODE_GPIO = 0, + KEY_MODE_EXTI = 1 +} keymode_typedef_enum; + +/* eval board low layer led */ +#define LEDn 4U + +#define LED1_PIN GPIO_PIN_0 +#define LED1_GPIO_PORT GPIOC +#define LED1_GPIO_CLK RCU_GPIOC + +#define LED2_PIN GPIO_PIN_2 +#define LED2_GPIO_PORT GPIOC +#define LED2_GPIO_CLK RCU_GPIOC + +#define LED3_PIN GPIO_PIN_0 +#define LED3_GPIO_PORT GPIOE +#define LED3_GPIO_CLK RCU_GPIOE + +#define LED4_PIN GPIO_PIN_1 +#define LED4_GPIO_PORT GPIOE +#define LED4_GPIO_CLK RCU_GPIOE + +#define COMn 2U + +#define EVAL_COM0 USART0 +#define EVAL_COM0_CLK RCU_USART0 +#define EVAL_COM0_TX_PIN GPIO_PIN_9 +#define EVAL_COM0_RX_PIN GPIO_PIN_10 +#define EVAL_COM0_GPIO_PORT GPIOA +#define EVAL_COM0_GPIO_CLK RCU_GPIOA + +#define EVAL_COM1 USART1 +#define EVAL_COM1_CLK RCU_USART1 +#define EVAL_COM1_TX_PIN GPIO_PIN_2 +#define EVAL_COM1_RX_PIN GPIO_PIN_3 +#define EVAL_COM1_GPIO_PORT GPIOA +#define EVAL_COM1_GPIO_CLK RCU_GPIOA + +#define KEYn 5U + +/* wakeup push-button */ +#define KEY_A_PIN GPIO_PIN_0 +#define KEY_A_GPIO_PORT GPIOA +#define KEY_A_GPIO_CLK RCU_GPIOA +#define KEY_A_EXTI_LINE EXTI_0 +#define KEY_A_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOA +#define KEY_A_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_0 +#define KEY_A_EXTI_IRQn EXTI0_IRQn + +/* tamper push-button */ +#define KEY_B_PIN GPIO_PIN_13 +#define KEY_B_GPIO_PORT GPIOC +#define KEY_B_GPIO_CLK RCU_GPIOC +#define KEY_B_EXTI_LINE EXTI_13 +#define KEY_B_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOC +#define KEY_B_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_13 +#define KEY_B_EXTI_IRQn EXTI10_15_IRQn + +/* user push-button */ +#define KEY_C_PIN GPIO_PIN_14 +#define KEY_C_GPIO_PORT GPIOB +#define KEY_C_GPIO_CLK RCU_GPIOB +#define KEY_C_EXTI_LINE EXTI_14 +#define KEY_C_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOB +#define KEY_C_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_14 +#define KEY_C_EXTI_IRQn EXTI10_15_IRQn + +#define KEY_D_PIN GPIO_PIN_5 +#define KEY_D_GPIO_PORT GPIOC +#define KEY_D_GPIO_CLK RCU_GPIOC +#define KEY_D_EXTI_LINE EXTI_5 +#define KEY_D_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOC +#define KEY_D_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_5 +#define KEY_D_EXTI_IRQn EXTI5_9_IRQn + +#define KEY_CET_PIN GPIO_PIN_4 +#define KEY_CET_GPIO_PORT GPIOC +#define KEY_CET_GPIO_CLK RCU_GPIOC +#define KEY_CET_EXTI_LINE EXTI_4 +#define KEY_CET_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOC +#define KEY_CET_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_4 +#define KEY_CET_EXTI_IRQn EXTI4_IRQn + +/* function declarations */ +/* configure led GPIO */ +void gd_eval_led_init(led_typedef_enum lednum); +/* turn on selected led */ +void gd_eval_led_on(led_typedef_enum lednum); +/* turn off selected led */ +void gd_eval_led_off(led_typedef_enum lednum); +/* toggle the selected led */ +void gd_eval_led_toggle(led_typedef_enum lednum); +/* configure key */ +void gd_eval_key_init(key_typedef_enum key_num, keymode_typedef_enum key_mode); +/* return the selected key state */ +uint8_t gd_eval_key_state_get(key_typedef_enum key); +/* configure COM port */ +void gd_eval_com_init(uint32_t com); + +#ifdef cplusplus +} +#endif + +#endif /* GD32VF103V_EVAL_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Utilities/gd32vf103v_lcd_eval.c b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Utilities/gd32vf103v_lcd_eval.c new file mode 100644 index 0000000..6c96741 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Utilities/gd32vf103v_lcd_eval.c @@ -0,0 +1,607 @@ +/*! + \file gd32vf103v_lcd_eval.c + \brief LCD driver functions + + \version 2019-06-05, V1.0.1, demo for GD32VF103 + \version 2019-09-18, V1.0.2, demo for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32vf103v_lcd_eval.h" +#include "lcd_font.h" + +#define LCD_ILI9320 0x9320 +#define LCD_ILI9325 0x9325 + +#define ABS(X) ((X) > 0 ? (X) : -(X)) + +uint16_t device_code; + +/*! + \brief lcd peripheral initialize + \param[in] none + \param[out] none + \retval none +*/ +void exmc_lcd_init(void) +{ + exmc_norsram_parameter_struct lcd_init_struct; + exmc_norsram_timing_parameter_struct lcd_timing_init_struct; + + /* EXMC clock enable */ + rcu_periph_clock_enable(RCU_EXMC); + rcu_periph_clock_enable(RCU_AF); + /* GPIO clock enable */ + rcu_periph_clock_enable(RCU_GPIOD); + rcu_periph_clock_enable(RCU_GPIOE); + + /* configure EXMC_D[0~15]*/ + /* PD14(EXMC_D0), PD15(EXMC_D1),PD0(EXMC_D2), PD1(EXMC_D3), PD8(EXMC_D13), PD9(EXMC_D14), PD10(EXMC_D15) */ + gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1| GPIO_PIN_8 | GPIO_PIN_9 | + GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15); + + /* PE7(EXMC_D4), PE8(EXMC_D5), PE9(EXMC_D6), PE10(EXMC_D7), PE11(EXMC_D8), PE12(EXMC_D9), + PE13(EXMC_D10), PE14(EXMC_D11), PE15(EXMC_D12) */ + gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | + GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | + GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15); + + /* configure PE2(EXMC_A23) */ + gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2); + + /* configure NOE and NWE */ + gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_4 | GPIO_PIN_5); + + /* configure EXMC NE0 */ + gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_7); + + lcd_timing_init_struct.bus_latency = 2; + lcd_timing_init_struct.asyn_data_setuptime = 10; + lcd_timing_init_struct.asyn_address_holdtime = 2; + lcd_timing_init_struct.asyn_address_setuptime = 5; + + lcd_init_struct.norsram_region = EXMC_BANK0_NORSRAM_REGION0; + lcd_init_struct.asyn_wait = DISABLE; + lcd_init_struct.nwait_signal = DISABLE; + lcd_init_struct.memory_write = ENABLE; + lcd_init_struct.nwait_polarity = EXMC_NWAIT_POLARITY_LOW; + lcd_init_struct.databus_width = EXMC_NOR_DATABUS_WIDTH_16B; + lcd_init_struct.memory_type = EXMC_MEMORY_TYPE_SRAM; + lcd_init_struct.address_data_mux = ENABLE; + lcd_init_struct.read_write_timing = &lcd_timing_init_struct; + + exmc_norsram_init(&lcd_init_struct); + + exmc_norsram_enable(EXMC_BANK0_NORSRAM_REGION0); +} + + +/*! + \brief write data to the selected LCD register + \param[in] register_id: the selected register id + \param[in] value: the register value to be written + \param[out] none + \retval none +*/ + +void lcd_register_write(uint16_t register_id,uint16_t value) +{ + *(__IO uint16_t *) (BANK0_LCD_C)= register_id; + *(__IO uint16_t *) (BANK0_LCD_D)= value; +} + +/*! + \brief read the value of LCD register + \param[in] register_id: the register id + \param[out] none + \retval the register value +*/ +uint16_t lcd_register_read(uint8_t register_id) +{ + uint16_t data; + *(__IO uint16_t *) (BANK0_LCD_C)= register_id; + data = *(__IO uint16_t *) (BANK0_LCD_D); + return data; +} + +/*! + \brief write command to LCD register + \param[in] value: the register value to be written + \param[out] none + \retval none +*/ +void lcd_command_write(uint16_t value) +{ + /* write 16-bit index, then write reg */ + *(__IO uint16_t *) (BANK0_LCD_C) = value; +} + +/*! + \brief prepare to write to the LCD GRAM register(R22h) + \param[in] none + \param[out] none + \retval none +*/ +void lcd_gram_write_prepare(void) +{ + *(__IO uint16_t *) (BANK0_LCD_C) = 0x0022; +} + +/*! + \brief write RGB code to the LCD GRAM register + \param[in] rgb_code: the pixel color in RGB mode (5-6-5) + \param[out] none + \retval none +*/ +void lcd_gram_write(uint16_t rgb_code) +{ + /* write 16-bit GRAM register */ + *(__IO uint16_t *) (BANK0_LCD_D) = rgb_code; +} + +/*! + \brief read data from GRAM + \param[in] none + \param[out] none + \retval GRAM value +*/ +uint16_t lcd_gram_read(void) +{ + uint16_t data; + + /* write GRAM register (R22h) */ + *(__IO uint16_t *) (BANK0_LCD_C) = 0x0022; + /* dummy read (invalid data) */ + data = *(__IO uint16_t *) (BANK0_LCD_D); + + data = *(__IO uint16_t *) (BANK0_LCD_D); + return data; +} + +/*! + \brief initialize the LCD + \param[in] none + \param[out] none + \retval none +*/ +void lcd_init(void) +{ + __IO uint16_t i; + + /* read the LCD controller device code */ + device_code = lcd_register_read(0x0000); + + if(0x8989 == device_code){ // SSD1289 + lcd_register_write(0x0000,0x0001); + lcd_register_write(0x0003,0xA8A4); + lcd_register_write(0x000C,0x0000); + lcd_register_write(0x000D,0x080C); + lcd_register_write(0x000E,0x2B00); + lcd_register_write(0x001E,0x00B0); + lcd_register_write(0x0001,0x2B3F); + lcd_register_write(0x0002,0x0600); + lcd_register_write(0x0010,0x0000); + lcd_register_write(0x0011,0x6070); + lcd_register_write(0x0005,0x0000); + lcd_register_write(0x0006,0x0000); + lcd_register_write(0x0016,0xEF1C); + lcd_register_write(0x0017,0x0003); + lcd_register_write(0x0007,0x0233); + lcd_register_write(0x000B,0x0000); + lcd_register_write(0x000F,0x0000); + lcd_register_write(0x0041,0x0000); + lcd_register_write(0x0042,0x0000); + lcd_register_write(0x0048,0x0000); + lcd_register_write(0x0049,0x013F); + lcd_register_write(0x004A,0x0000); + lcd_register_write(0x004B,0x0000); + lcd_register_write(0x0044,0xEF00); + lcd_register_write(0x0045,0x0000); + lcd_register_write(0x0046,0x013F); + lcd_register_write(0x0030,0x0707); + lcd_register_write(0x0031,0x0204); + lcd_register_write(0x0032,0x0204); + lcd_register_write(0x0033,0x0502); + lcd_register_write(0x0034,0x0507); + lcd_register_write(0x0035,0x0204); + lcd_register_write(0x0036,0x0204); + lcd_register_write(0x0037,0x0502); + lcd_register_write(0x003A,0x0302); + lcd_register_write(0x003B,0x0302); + lcd_register_write(0x0023,0x0000); + lcd_register_write(0x0024,0x0000); + lcd_register_write(0x0025,0x8000); + lcd_register_write(0x004e,0); + lcd_register_write(0x004f,0); + }else if((0x9320 == device_code) || (0x9300 == device_code)){ //ILI9320 + lcd_register_write(0x01,0x0100); //driver output control + lcd_register_write(0x02,0x0700); //lcd driver waveform control + lcd_register_write(0x03,0x1020); //entry mode set + + lcd_register_write(0x04,0x0000); //resizing control + lcd_register_write(0x08,0x0202); //display control 2 + lcd_register_write(0x09,0x0000); //display control 3 + lcd_register_write(0x0a,0x0000); //frame cycle control + lcd_register_write(0x0c,(1<<0)); //extern display interface control 1 + lcd_register_write(0x0d,0x0000); //frame maker position + lcd_register_write(0x0f,0x0000); //extern display interface control 2 + + for(i=50000;i>0;i--); + lcd_register_write(0x07,0x0101); //display control + for(i=50000;i>0;i--); + + lcd_register_write(0x10,(1<<12)|(0<<8)|(1<<7)|(1<<6)|(0<<4)); //power control 1 + lcd_register_write(0x11,0x0007); //power control 2 + lcd_register_write(0x12,(1<<8)|(1<<4)|(0<<0)); //power control 3 + lcd_register_write(0x13,0x0b00); //power control 4 + lcd_register_write(0x29,0x0000); //power control 7 + lcd_register_write(0x2b,(1<<14)|(1<<4)); + lcd_register_write(0x50,0); //set x start + lcd_register_write(0x51,239); //set x end + lcd_register_write(0x52,0); //set y start + lcd_register_write(0x53,319); //set y end + + lcd_register_write(0x60,0x2700); //driver output control + lcd_register_write(0x61,0x0001); //driver output control + lcd_register_write(0x6a,0x0000); //vertical srcoll control + + lcd_register_write(0x80,0x0000); //display position? partial display 1 + lcd_register_write(0x81,0x0000); //ram address start? partial display 1 + lcd_register_write(0x82,0x0000); //ram address end-partial display 1 + lcd_register_write(0x83,0x0000); //display position? partial display 2 + lcd_register_write(0x84,0x0000); //ram address start? partial display 2 + lcd_register_write(0x85,0x0000); //ram address end? partial display 2 + + lcd_register_write(0x90,(0<<7)|(16<<0)); //frame cycle control + lcd_register_write(0x92,0x0000); //panel interface control 2 + lcd_register_write(0x93,0x0001); //panel interface control 3 + lcd_register_write(0x95,0x0110); //frame cycle control + lcd_register_write(0x97,(0<<8)); + lcd_register_write(0x98,0x0000); //frame cycle control + for(i=50000;i>0;i--); + lcd_register_write(0x07,0x0173); + for(i=50000;i>0;i--); + + }else{ + return; + } + + for(i=50000;i>0;i--); +} + +/*! + \brief set the cursor of LCD + \param[in] x: the row-coordinate + \param[in] y: the column-coordinate + \param[out] none + \retval none +*/ +void lcd_cursor_set(uint16_t x,uint16_t y) +{ + lcd_register_write(0x004e,x); + lcd_register_write(0x004f,y); +} + +/*! + \brief clear the LCD screen to the specified color + \param[in] color: specified screen color + \param[out] none + \retval none +*/ +void lcd_clear(uint16_t color) +{ + uint32_t index=0; + if(0x8989 == device_code){ // SSD1289 + lcd_cursor_set(0,0); + /* prepare to write GRAM */ + lcd_gram_write_prepare(); + for(index=0; index LCD_PIXEL_HEIGHT)||(y > LCD_PIXEL_WIDTH)){ + return; + } + if(0x8989 == device_code){ // SSD1289 + lcd_cursor_set(x,y); + lcd_gram_write_prepare(); + lcd_gram_write(point); + }else if((0x9320 == device_code) || (0x9300 == device_code)){ //ILI9320 + lcd_register_write(0x20, x); + lcd_register_write(0x21, y); + lcd_register_write(0x22, point); + } + +} + +/*! + \brief get point GRAM according to the specified position + \param[in] x: the row-coordinate + \param[in] y: the column-coordinate + \param[out] none + \retval GRAM value of point +*/ +uint16_t lcd_point_get(uint16_t x,uint16_t y) +{ + uint16_t data; + + if ((x > LCD_PIXEL_HEIGHT)||(y > LCD_PIXEL_WIDTH)){ + return 0; + } + + lcd_cursor_set(x,y); + data = lcd_gram_read(); + + return data; +} + +/*! + \brief set window area + \param[in] start_x: the start position of row-coordinate + \param[in] start_y: the start position of column-coordinate + \param[in] end_x: the end position of row-coordinate + \param[in] end_y: the end position of column-coordinate + \param[out] none + \retval none +*/ +void lcd_windows_set(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y) +{ + lcd_cursor_set(start_x, start_y); + + lcd_register_write(0x0050, start_x); + lcd_register_write(0x0052, start_y); + lcd_register_write(0x0051, end_x); + lcd_register_write(0x0053, end_y); +} + +/*! + \brief draw a horizontal line on LCD screen + \param[in] x: the row-coordinate + \param[in] start_y: the start column-coordinate + \param[in] end_y: the end column-coordinate + \param[in] color: specified color of the point + \param[in] width: line width + \param[out] none + \retval none +*/ + +void lcd_hline_draw(uint16_t x,uint16_t start_y,uint16_t end_y,uint16_t color,uint16_t width) +{ + uint16_t i, y; + + for (i = 0; i < width; i++) { + uint16_t sx = x + i; + + for (y = start_y; y < end_y; y++) { + lcd_point_set(sx, y, color); + } + } +} + +/*! + \brief draw a vertical line on LCD screen + \param[in] start_x: the start column-coordinate + \param[in] end_x: the end column-coordinate + \param[in] y: the row-coordinate + \param[in] color: specified color of the point + \param[in] width: line width + \param[out] none + \retval none +*/ + +void lcd_vline_draw(uint16_t start_x,uint16_t end_x,uint16_t y,uint16_t color,uint16_t width) +{ + uint16_t i, x; + + for (i = 0; i < width; i++) { + uint16_t sy = y + i; + + for (x = start_x; x < end_x; x++) { + lcd_point_set(x, sy, color); + } + } +} + +/*! + \brief draw a rectangle according to the specified position and color + \param[in] start_x: the start position of row-coordinate + \param[in] start_y: the start position of column-coordinate + \param[in] end_x: the end position of row-coordinate + \param[in] end_y: the end position of column-coordinate + \param[in] point: specified color of the point + \param[out] none + \retval none +*/ +void lcd_rectangle_draw(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t point) +{ + uint16_t x,y; + x=start_x; + y=start_y; + /* draw four lines */ + for(x=start_x;xstart_x;x--){ + lcd_point_set(x,y,point); + } + for(y=end_y;y>start_y;y--){ + lcd_point_set(x,y,point); + } +} + +/*! + \brief fill the specified color to a rectangle + \param[in] start_x: the start position of row-coordinate + \param[in] start_y: the start position of column-coordinate + \param[in] end_x: the end position of row-coordinate + \param[in] end_y: the end position of column-coordinate + \param[in] color: specified color + \param[out] none + \retval none +*/ +void lcd_rectangle_fill(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t color) +{ + uint16_t x, y; + x = start_x; + y = start_y; + + for (x = start_x; x < end_x; x++) { + for (y = start_y; y < end_y; y++) { + lcd_point_set(x, y, color); + } + } +} + +/*! + \brief draw a picture on LCD screen according to the specified position + \param[in] start_x: the start position of row-coordinate + \param[in] start_y: the start position of column-coordinate + \param[in] end_x: the end position of row-coordinate + \param[in] end_y: the end position of column-coordinate + \param[in] pic: the picture pointer + \param[out] none + \retval none +*/ +void lcd_picture_draw(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t *pic) +{ + uint32_t i, total; + uint16_t *picturepointer = pic; + uint16_t x,y; + + x = start_x; + y = start_y; + + total = (end_x - start_x + 1) * (end_y - start_y + 1); + + for(i = 0; i < total; i ++){ + /* set point according to the specified position and color */ + lcd_point_set(x,y,*picturepointer++); + x++; + if(x > end_x){ + y++; + x = start_x; + } + } +} + +/*! + \brief display a char on LCD screen according to the specified position + \param[in] x: the start position of row-coordinate + \param[in] y: the start position of column-coordinate + \param[in] c: the char + \param[in] char_color: the color of char + \param[in] c_format: the structure of char format + font: CHAR_FONT_8_16 or CHAR_FONT_16_24 + direction: CHAR_DIRECTION_HORIZONTAL or CHAR_DIRECTION_VERTICAL + char_color: the color of char + bk_color: the color of background + \param[out] none + \retval none +*/ +void lcd_char_display(uint16_t x,uint16_t y,uint8_t c,char_format_struct c_format) +{ + uint16_t i = 0, j = 0; + uint8_t temp_char = 0; + uint16_t temp_char_16 = 0; + + if(CHAR_FONT_8_16 == c_format.font){ /* 8x16 ASCII */ + for (i = 0; i < 16; i++) { + temp_char = ascii_8x16[((c - 0x20) * 16) + i]; + if(CHAR_DIRECTION_HORIZONTAL == c_format.direction){ + for (j = 0; j < 8; j++) { + if (((temp_char >> (7 - j)) & 0x01) == 0x01) { + /* set point of char */ + lcd_point_set(x - i, y + j, c_format.char_color); + } else { + /* set point of background */ + lcd_point_set(x - i, y + j, c_format.bk_color); + } + } + }else{ + for (j = 0; j < 8; j++) { + if (((temp_char >> (7 - j)) & 0x01) == 0x01) { + /* set point of char */ + lcd_point_set(x + j, y + i, c_format.char_color); + } else { + /* set point of background */ + lcd_point_set(x + j, y + i, c_format.bk_color); + } + } + } + } + }else if(CHAR_FONT_16_24 == c_format.font){ /* 16x24 ASCII */ + for (i = 0; i < 24; i++) { + temp_char_16 = ASCII_Table_16x24[((c - 0x20) * 24) + i]; + if(CHAR_DIRECTION_HORIZONTAL == c_format.direction){ + for (j = 0; j < 16; j++) { + if (((temp_char_16 >> j) & 0x01) == 0x01) { + /* set point of char */ + lcd_point_set(x - i, y + j, c_format.char_color); + } else { + /* set point of background */ + lcd_point_set(x - i, y + j, c_format.bk_color); + } + } + }else{ + for (j = 0; j < 16; j++) { + if (((temp_char_16 >> j) & 0x01) == 0x01) { + /* set point of char */ + lcd_point_set(x + j, y + i, c_format.char_color); + } else { + /* set point of background */ + lcd_point_set(x + j, y + i, c_format.bk_color); + } + } + } + } + } +} diff --git a/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Utilities/gd32vf103v_lcd_eval.h b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Utilities/gd32vf103v_lcd_eval.h new file mode 100644 index 0000000..29ed44b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/GD32VF103_Firmware_Library_V1.0.1/Utilities/gd32vf103v_lcd_eval.h @@ -0,0 +1,237 @@ +/*! + \file gd32vf103v_lcd_eval.h + \brief LCD driver header file + + \version 2019-06-05, V1.0.0, demo for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103V_LCD_EVAL_H +#define GD32VF103V_LCD_EVAL_H + +#include "gd32vf103.h" + +#define BANK0_LCD_C ((uint32_t)0x60000000) /*!< LCD register address */ +#define BANK0_LCD_D ((uint32_t)0x61000000) /*!< LCD data address */ + +/* LCD registers */ +#define R0 0x00 +#define R1 0x01 +#define R2 0x02 +#define R3 0x03 +#define R4 0x04 +#define R5 0x05 +#define R6 0x06 +#define R7 0x07 +#define R8 0x08 +#define R9 0x09 +#define R10 0x0A +#define R11 0x0B +#define R12 0x0C +#define R13 0x0D +#define R14 0x0E +#define R15 0x0F +#define R16 0x10 +#define R17 0x11 +#define R18 0x12 +#define R19 0x13 +#define R20 0x14 +#define R21 0x15 +#define R22 0x16 +#define R23 0x17 +#define R24 0x18 +#define R25 0x19 +#define R26 0x1A +#define R27 0x1B +#define R28 0x1C +#define R29 0x1D +#define R30 0x1E +#define R31 0x1F +#define R32 0x20 +#define R33 0x21 +#define R34 0x22 +#define R35 0x23 +#define R36 0x24 +#define R37 0x25 +#define R40 0x28 +#define R41 0x29 +#define R43 0x2B +#define R45 0x2D +#define R48 0x30 +#define R49 0x31 +#define R50 0x32 +#define R51 0x33 +#define R52 0x34 +#define R53 0x35 +#define R54 0x36 +#define R55 0x37 +#define R56 0x38 +#define R57 0x39 +#define R58 0x3A +#define R59 0x3B +#define R60 0x3C +#define R61 0x3D +#define R62 0x3E +#define R63 0x3F +#define R64 0x40 +#define R65 0x41 +#define R66 0x42 +#define R67 0x43 +#define R68 0x44 +#define R69 0x45 +#define R70 0x46 +#define R71 0x47 +#define R72 0x48 +#define R73 0x49 +#define R74 0x4A +#define R75 0x4B +#define R76 0x4C +#define R77 0x4D +#define R78 0x4E +#define R79 0x4F +#define R80 0x50 +#define R81 0x51 +#define R82 0x52 +#define R83 0x53 +#define R96 0x60 +#define R97 0x61 +#define R106 0x6A +#define R118 0x76 +#define R128 0x80 +#define R129 0x81 +#define R130 0x82 +#define R131 0x83 +#define R132 0x84 +#define R133 0x85 +#define R134 0x86 +#define R135 0x87 +#define R136 0x88 +#define R137 0x89 +#define R139 0x8B +#define R140 0x8C +#define R141 0x8D +#define R143 0x8F +#define R144 0x90 +#define R145 0x91 +#define R146 0x92 +#define R147 0x93 +#define R148 0x94 +#define R149 0x95 +#define R150 0x96 +#define R151 0x97 +#define R152 0x98 +#define R153 0x99 +#define R154 0x9A +#define R157 0x9D +#define R192 0xC0 +#define R193 0xC1 +#define R229 0xE5 + +/* LCD color */ +#define LCD_COLOR_WHITE 0xFFFF +#define LCD_COLOR_BLACK 0x0000 +#define LCD_COLOR_GREY 0xF7DE +#define LCD_COLOR_BLUE 0x001F +#define LCD_COLOR_BLUE2 0x051F +#define LCD_COLOR_RED 0xF800 +#define LCD_COLOR_MAGENTA 0xF81F +#define LCD_COLOR_GREEN 0x07E0 +#define LCD_COLOR_CYAN 0x7FFF +#define LCD_COLOR_YELLOW 0xFFE0 + +/* definitions of LCD lines */ +#define LCD_LINE_0 0 +#define LCD_LINE_1 24 +#define LCD_LINE_2 48 +#define LCD_LINE_3 72 +#define LCD_LINE_4 96 +#define LCD_LINE_5 120 +#define LCD_LINE_6 144 +#define LCD_LINE_7 168 +#define LCD_LINE_8 192 +#define LCD_LINE_9 216 + +#define CHAR_FONT_8_16 ((uint16_t)0x0000U) /*!< the font of char is 8X16 */ +#define CHAR_FONT_16_24 ((uint16_t)0x0001U) /*!< the font of char is 16X24 */ + +#define CHAR_DIRECTION_HORIZONTAL ((uint16_t)0x0000U) /*!< character display direction is horizontal */ +#define CHAR_DIRECTION_VERTICAL ((uint16_t)0x0001U) /*!< character display direction is vertical */ + +#define LCD_PIXEL_WIDTH ((uint16_t)320) +#define LCD_PIXEL_HEIGHT ((uint16_t)240) + +/* char format struct definitions */ +typedef struct +{ + uint16_t font; /*!< the type of font */ + uint16_t direction; /*!< the direction of char */ + uint16_t char_color; /*!< the color of char */ + uint16_t bk_color; /*!< the color of backgroud */ +}char_format_struct; + +/* lcd peripheral initialize */ +void exmc_lcd_init(void); +/* initialize the LCD */ +void lcd_init(void); +/* write data to the selected LCD register */ +void lcd_register_write(uint16_t register_id,uint16_t value); +/* read the value of LCD register */ +uint16_t lcd_register_read(uint8_t register_id); +/* write command to LCD register */ +void lcd_command_write (uint16_t value); +/* prepare to write to the LCD GRAM */ +void lcd_gram_write_prepare(void); +/* write RGB code to the LCD GRAM register */ +void lcd_gram_write(uint16_t rgb_code); +/* read data from GRAM */ +uint16_t lcd_gram_read(void); +/* set the cursor of LCD */ +void lcd_cursor_set(uint16_t x,uint16_t y); +/* clear the LCD screen to the specified color */ +void lcd_clear(uint16_t Color); +/* set the point according to the specified position and color */ +void lcd_point_set(uint16_t x,uint16_t y,uint16_t point); +/* get the point according to the specified position */ +uint16_t lcd_point_get(uint16_t x,uint16_t y); +/* set window area */ +void lcd_windows_set(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y); +/* draw a horizontal line on LCD screen */ +void lcd_hline_draw(uint16_t x,uint16_t start_y,uint16_t end_y,uint16_t color,uint16_t width); +/* draw a vertical line on LCD screen */ +void lcd_vline_draw(uint16_t start_x,uint16_t end_x,uint16_t y,uint16_t color,uint16_t width); +/* draw a rectangle according to the specified position and color */ +void lcd_rectangle_draw(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t point); +/* fill the specified color to a rectangle */ +void lcd_rectangle_fill(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t color); +/* draw a picture on LCD screen according to the specified position */ +void lcd_picture_draw(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t *pic); +/* display a char on LCD screen according to the specified position */ +void lcd_char_display(uint16_t x,uint16_t y,uint8_t c,char_format_struct c_format); + +#endif /* GD32VF103V_LCD_EVAL_H */ diff --git a/firmware/midi2cv/src/drivers/usbfs/midi.c b/firmware/midi2cv/src/drivers/usbfs/midi.c new file mode 100644 index 0000000..9778a39 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/midi.c @@ -0,0 +1,319 @@ +/* + MIT License + + Copyright (c) 2019 nyannkov + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +#include +#include "midi.h" + +typedef enum _Parse_MIDI_Message_Event { + PARSE_MIDI_EVENT_RCV_STS_CH_MSG_1 = 0, + PARSE_MIDI_EVENT_RCV_STS_CH_MSG_2, + PARSE_MIDI_EVENT_RCV_SYS_RT, + PARSE_MIDI_EVENT_RCV_DAT, + PARSE_MIDI_EVENT_RCV_SYS_EX_START, + PARSE_MIDI_EVENT_RCV_SYS_EX_EOX, + NUM_OF_PARSE_MIDI_MESSAGE_EVENT +}Parse_MIDI_Message_Event_t; + +typedef struct _Parse_MIDI_FSM { + Parse_MIDI_Message_State_t next; + void (*pTransStateFunc)(MIDI_Handle_t *phMIDI, uint8_t msg); +}Parse_MIDI_FSM_t; + + +MIDI_Handle_t *MIDI_Alloc(void); +void MIDI_Free(MIDI_Handle_t *phMIDI); + + +static inline Parse_MIDI_Message_Event_t _GetParseMIDIMessageEvent(uint8_t msg) { + + if ( (msg & 0x80) == 0 ) { + return PARSE_MIDI_EVENT_RCV_DAT; + } + else if ( (msg & 0xF0) == 0xF0 ) { + switch ( msg ) { + case 0xF0: + return PARSE_MIDI_EVENT_RCV_SYS_EX_START; + + case 0xF7: + return PARSE_MIDI_EVENT_RCV_SYS_EX_EOX; + + default: + return PARSE_MIDI_EVENT_RCV_SYS_RT; + } + } + else { + + switch ( msg & 0xF0 ) { + case 0x80: + case 0x90: + case 0xA0: + case 0xB0: + case 0xE0: + return PARSE_MIDI_EVENT_RCV_STS_CH_MSG_2; + + case 0xC0: + case 0xD0: + return PARSE_MIDI_EVENT_RCV_STS_CH_MSG_1; + + default: + // unexpected + return PARSE_MIDI_EVENT_RCV_SYS_RT; + } + } + +} + + +static void _StoreChannelMessageStatus(MIDI_Handle_t *phMIDI, uint8_t msg); +static void _StoreChannelMessageData(MIDI_Handle_t *phMIDI, uint8_t msg); +static void _StoreSystemExclusiveMessage(MIDI_Handle_t *phMIDI, uint8_t msg); +static void _ExecChannelMessage1(MIDI_Handle_t *phMIDI, uint8_t msg); +static void _ExecChannelMessage2(MIDI_Handle_t *phMIDI, uint8_t msg); +static void _ExecSystemExclusiveMessage(MIDI_Handle_t *phMIDI, uint8_t msg); + +static const Parse_MIDI_FSM_t _midi_trans_state_tbl[NUM_OF_PARSE_MIDI_MESSAGE_STATE][NUM_OF_PARSE_MIDI_MESSAGE_EVENT] = { + /* IDLE */ + { + {PARSE_MIDI_CH_MSG_1, _StoreChannelMessageStatus}, // RCV_STS_CH_MSG_1 + {PARSE_MIDI_CH_MSG_2_1, _StoreChannelMessageStatus}, // RCV_STS_CH_MSG_2 + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_RT + {PARSE_MIDI_IDLE, NULL}, // RCV_DAT + {PARSE_MIDI_SYS_EX, _StoreSystemExclusiveMessage}, // RCV_SYS_EX_START + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_EX_EOX + }, + /* CH_MSG_1 */ + { + {PARSE_MIDI_IDLE, NULL}, // RCV_STS_CH_MSG_1 + {PARSE_MIDI_IDLE, NULL}, // RCV_STS_CH_MSG_2 + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_RT + {PARSE_MIDI_CH_MSG_RUNNING_1, _ExecChannelMessage1}, // RCV_DAT + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_EX_START + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_EX_EOX + }, + /* CH_MSG_2_1 */ + { + {PARSE_MIDI_IDLE, NULL}, // RCV_STS_CH_MSG_1 + {PARSE_MIDI_IDLE, NULL}, // RCV_STS_CH_MSG_2 + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_RT + {PARSE_MIDI_CH_MSG_2_2, _StoreChannelMessageData}, // RCV_DAT + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_EX_START + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_EX_EOX + }, + /* CH_MSG_2_2 */ + { + {PARSE_MIDI_IDLE, NULL}, // RCV_STS_CH_MSG_1 + {PARSE_MIDI_IDLE, NULL}, // RCV_STS_CH_MSG_2 + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_RT + {PARSE_MIDI_CH_MSG_RUNNING_2, _ExecChannelMessage2}, // RCV_DAT + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_EX_START + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_EX_EOX + }, + /* CH_MSG_RUNNING_1 */ + { + {PARSE_MIDI_CH_MSG_1, _StoreChannelMessageStatus}, // RCV_STS_CH_MSG_1 + {PARSE_MIDI_CH_MSG_2_1, _StoreChannelMessageStatus}, // RCV_STS_CH_MSG_2 + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_RT + {PARSE_MIDI_CH_MSG_RUNNING_1, _ExecChannelMessage1}, // RCV_DAT + {PARSE_MIDI_SYS_EX, NULL}, // RCV_SYS_EX_START + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_EX_EOX + }, + /* CH_MSG_RUNNING_2 */ + { + {PARSE_MIDI_CH_MSG_1, _StoreChannelMessageStatus}, // RCV_STS_CH_MSG_1 + {PARSE_MIDI_CH_MSG_2_1, _StoreChannelMessageStatus}, // RCV_STS_CH_MSG_2 + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_RT + {PARSE_MIDI_CH_MSG_2_2, _StoreChannelMessageData}, // RCV_DAT + {PARSE_MIDI_SYS_EX, NULL}, // RCV_SYS_EX_START + {PARSE_MIDI_IDLE, NULL}, // RCV_SYS_EX_EOX + }, + /* PARSE_MIDI_SYS_EX */ + { + {PARSE_MIDI_SYS_EX, _StoreSystemExclusiveMessage}, // RCV_STS_CH_MSG_1 + {PARSE_MIDI_SYS_EX, _StoreSystemExclusiveMessage}, // RCV_STS_CH_MSG_2 + {PARSE_MIDI_SYS_EX, _StoreSystemExclusiveMessage}, // RCV_SYS_RT + {PARSE_MIDI_SYS_EX, _StoreSystemExclusiveMessage}, // RCV_DAT + {PARSE_MIDI_SYS_EX, _StoreSystemExclusiveMessage}, // RCV_SYS_EX_START + {PARSE_MIDI_IDLE, _ExecSystemExclusiveMessage}, // RCV_SYS_EX_EOX + } +}; + + +MIDI_Handle_t *MIDI_Init(const MIDI_Message_Callbacks_t *pcallbacks ) { + + MIDI_Handle_t *phMIDI = NULL; + phMIDI = MIDI_Alloc(); + + if ( phMIDI != NULL ) { + uint32_t i = 0; + phMIDI->chmsg_buf.msg0 = 0; + phMIDI->chmsg_buf.msg1 = 0; + phMIDI->chmsg_buf.msg2 = 0; + phMIDI->chmsg_buf.pad = 0; + phMIDI->sysex_buf.len = 0; + for ( i = 0; i < MAX_SYS_EX_BUF_SIZE; i++ ) { + phMIDI->sysex_buf.msg[i] = 0; + } + + phMIDI->state = PARSE_MIDI_IDLE; + phMIDI->pcallback = pcallbacks; + } + + return phMIDI; +} + +void MIDI_DeInit( MIDI_Handle_t *phMIDI ) { + + if ( phMIDI != NULL ) { + MIDI_Free(phMIDI); + } +} + +int32_t MIDI_Play(MIDI_Handle_t *phMIDI, const uint8_t *midi_msg, size_t len) { + + uint32_t i = 0; + Parse_MIDI_Message_Event_t event = PARSE_MIDI_EVENT_RCV_STS_CH_MSG_1; + const Parse_MIDI_FSM_t *pfsm = NULL; + + for ( i = 0; i < len; i++ ) { + event = _GetParseMIDIMessageEvent(midi_msg[i]); + + pfsm = &_midi_trans_state_tbl[phMIDI->state][event]; + + if ( pfsm->pTransStateFunc != NULL ) { + pfsm->pTransStateFunc(phMIDI, midi_msg[i]); + } + phMIDI->state = pfsm->next; + } + + return 0; +} + +__WEAK__ MIDI_Handle_t *MIDI_Alloc(void) +{ + static MIDI_Handle_t hMIDI; + return &hMIDI; +} + +__WEAK__ void MIDI_Free(MIDI_Handle_t *phMIDI) +{ + (void)phMIDI; +} + +static void _StoreChannelMessageStatus(MIDI_Handle_t *phMIDI, uint8_t msg) { + phMIDI->chmsg_buf.msg0 = msg; +} + +static void _StoreChannelMessageData(MIDI_Handle_t *phMIDI, uint8_t msg) { + phMIDI->chmsg_buf.msg1 = msg; +} + +static void _StoreSystemExclusiveMessage(MIDI_Handle_t *phMIDI, uint8_t msg) { + MIDI_System_Exclusive_Buffer_t *psys_ex_buf = &phMIDI->sysex_buf; + if ( psys_ex_buf->len < MAX_SYS_EX_BUF_SIZE ) { + psys_ex_buf->msg[(psys_ex_buf->len)++] = msg; + } +} + +static void _ExecChannelMessage1(MIDI_Handle_t *phMIDI, uint8_t msg) { + + const MIDI_ChannelVoiceMessage_t *pchvmsg = &phMIDI->pcallback->channel.voice_msg; + + phMIDI->chmsg_buf.msg1 = msg; + + switch (phMIDI->chmsg_buf.msg0 & 0xF0) { + case 0xC0: + if ( pchvmsg->pProgramChange != NULL ) { + pchvmsg->pProgramChange(phMIDI->chmsg_buf.msg0 & 0x0F, phMIDI->chmsg_buf.msg1); + } + break; + + case 0xD0: + if ( pchvmsg->pChannelPressure != NULL ) { + pchvmsg->pChannelPressure(phMIDI->chmsg_buf.msg0 & 0x0F, phMIDI->chmsg_buf.msg1); + } + break; + + default: + break; + } +} + +static void _ExecChannelMessage2(MIDI_Handle_t *phMIDI, uint8_t msg) { + + const MIDI_ChannelVoiceMessage_t *pchvmsg = &phMIDI->pcallback->channel.voice_msg; + phMIDI->chmsg_buf.msg2 = msg; + + switch (phMIDI->chmsg_buf.msg0 & 0xF0) { + case 0x80: + if ( pchvmsg->pNoteOff != NULL ) { + pchvmsg->pNoteOff(phMIDI->chmsg_buf.msg0 & 0x0F, phMIDI->chmsg_buf.msg1, phMIDI->chmsg_buf.msg2); + gpio_bit_set(GPIOA, GPIO_PIN_2); + } + break; + + case 0x90: + if ( pchvmsg->pNoteOn != NULL ) { + pchvmsg->pNoteOn(phMIDI->chmsg_buf.msg0 & 0x0F, phMIDI->chmsg_buf.msg1, phMIDI->chmsg_buf.msg2); + gpio_bit_reset(GPIOA, GPIO_PIN_2); + } + break; + + case 0xA0: + if ( pchvmsg->pPolyphonicKeyPressure != NULL ) { + pchvmsg->pPolyphonicKeyPressure(phMIDI->chmsg_buf.msg0 & 0x0F, phMIDI->chmsg_buf.msg1, phMIDI->chmsg_buf.msg2); + } + break; + + case 0xB0: + if ( pchvmsg->pControlChange != NULL ) { + pchvmsg->pControlChange(phMIDI->chmsg_buf.msg0 & 0x0F, phMIDI->chmsg_buf.msg1, phMIDI->chmsg_buf.msg2); + } + break; + + case 0xE0: + if ( pchvmsg->pPitchBendChange != NULL ) { + pchvmsg->pPitchBendChange(phMIDI->chmsg_buf.msg0 & 0x0F, phMIDI->chmsg_buf.msg1, phMIDI->chmsg_buf.msg2); + } + break; + + default: + break; + } +} + + +static void _ExecSystemExclusiveMessage(MIDI_Handle_t *phMIDI, uint8_t msg) { + + const MIDI_SystemExclusiveMessage_t *psys_ex = &phMIDI->pcallback->system.exclusive_msg; + MIDI_System_Exclusive_Buffer_t *psys_ex_buf = &phMIDI->sysex_buf; + + (void)msg; + + if ( psys_ex->pSystemExclusive != NULL ) { + psys_ex->pSystemExclusive(psys_ex_buf->msg, psys_ex_buf->len); + } + + // clear + psys_ex_buf->len = 0; +} \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/midi.h b/firmware/midi2cv/src/drivers/usbfs/midi.h new file mode 100644 index 0000000..bfa1af6 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/midi.h @@ -0,0 +1,93 @@ +/* + MIT License + + Copyright (c) 2019 nyannkov + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +#ifndef __MIDI_H__ +#define __MIDI_H__ + +#include "midiconf.h" + +typedef struct _MIDI_Channel_Message_Buffer { + uint8_t msg0; // status byte + uint8_t msg1; // data byte 1 + uint8_t msg2; // data byte 2 + uint8_t pad; // padding +}MIDI_Channel_Message_Buffer_t; + +typedef struct _MIDI_System_Exclusive_Buffer { + uint8_t msg[MAX_SYS_EX_BUF_SIZE]; + size_t len; +}MIDI_System_Exclusive_Buffer_t; + + +typedef enum _Parse_MIDI_Message_State { + PARSE_MIDI_IDLE = 0, + PARSE_MIDI_CH_MSG_1, + PARSE_MIDI_CH_MSG_2_1, + PARSE_MIDI_CH_MSG_2_2, + PARSE_MIDI_CH_MSG_RUNNING_1, + PARSE_MIDI_CH_MSG_RUNNING_2, + PARSE_MIDI_SYS_EX, + NUM_OF_PARSE_MIDI_MESSAGE_STATE +}Parse_MIDI_Message_State_t; + + +typedef struct _MIDI_ChannelVoiceMessage { + void (*pNoteOff)(uint8_t ch, uint8_t kk, uint8_t uu); + void (*pNoteOn)(uint8_t ch, uint8_t kk, uint8_t vv); + void (*pPolyphonicKeyPressure)(uint8_t ch, uint8_t kk, uint8_t vv); + void (*pControlChange)(uint8_t ch, uint8_t cc, uint8_t vv); + void (*pProgramChange)(uint8_t ch, uint8_t pp); + void (*pChannelPressure)(uint8_t ch, uint8_t vv); + void (*pPitchBendChange)(uint8_t ch, uint8_t ll, uint8_t hh); +}MIDI_ChannelVoiceMessage_t; + +typedef struct _MIDI_ChannelMessage { + MIDI_ChannelVoiceMessage_t voice_msg; +}MIDI_ChannelMessage_t; + +typedef struct _MIDI_SystemExclusiveMessage { + void (*pSystemExclusive)(uint8_t *dat, size_t len); +}MIDI_SystemExclusiveMessage_t; + +typedef struct _MIDI_SystemMessage { + MIDI_SystemExclusiveMessage_t exclusive_msg; +}MIDI_SystemMessage_t; + +typedef struct _MIDI_Message_Callbacks { + MIDI_ChannelMessage_t channel; + MIDI_SystemMessage_t system; +}MIDI_Message_Callbacks_t; + +typedef struct _MIDI_Handle { + MIDI_Channel_Message_Buffer_t chmsg_buf; + MIDI_System_Exclusive_Buffer_t sysex_buf; + const MIDI_Message_Callbacks_t *pcallback; + Parse_MIDI_Message_State_t state; +}MIDI_Handle_t; + +extern MIDI_Handle_t *MIDI_Init(const MIDI_Message_Callbacks_t *pcallbacks ); +extern void MIDI_DeInit( MIDI_Handle_t *phMIDI ); +extern int32_t MIDI_Play(MIDI_Handle_t *phMIDI, const uint8_t *midi_msg, size_t len); + +#endif // __MIDI_H__ diff --git a/firmware/midi2cv/src/drivers/usbfs/midi_cdc_core.c b/firmware/midi2cv/src/drivers/usbfs/midi_cdc_core.c new file mode 100644 index 0000000..4307063 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/midi_cdc_core.c @@ -0,0 +1,430 @@ +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ +#include +#include + +#include +#include +#include +#include "usbd_core.h" +#include "drv_usb_hw.h" +#include "usbd_enum.h" +#include "midi_cdc_desc.h" +#include "midi_cdc_core.h" + + +// usb cdc acm data send buffer page +#define USB_CDC_TX_BUF_PAGE_NUM 2 + +// each usb cdc acm data send buffer size +#ifndef USB_CDC_TX_BUF_SIZE +#define USB_CDC_TX_BUF_SIZE (CDC_ACM_DATA_PACKET_SIZE * 10) +#endif + +#define SEND_ENCAPSULATED_COMMAND 0x00 +#define GET_ENCAPSULATED_RESPONSE 0x01 +#define SET_COMM_FEATURE 0x02 +#define GET_COMM_FEATURE 0x03 +#define CLEAR_COMM_FEATURE 0x04 +#define SET_LINE_CODING 0x20 +#define GET_LINE_CODING 0x21 +#define SET_CONTROL_LINE_STATE 0x22 +#define SEND_BREAK 0x23 +#define NO_CMD 0xFF + +// usb cdc acm data send status +typedef enum +{ + USB_CDC_SEND_STATUS_INIT = 0, + USB_CDC_SEND_STATUS_BUSY, + USB_CDC_SEND_STATUS_FINISHED +}usb_cdc_send_status_t; + +typedef struct +{ + uint32_t dwDTERate; /* data terminal rate */ + uint8_t bCharFormat; /* stop bits */ + uint8_t bParityType; /* parity */ + uint8_t bDataBits; /* data bits */ +}line_coding_struct; + + +static uint32_t cdc_cmd = 0xFFU; +static uint8_t usb_cmd_buffer[CDC_ACM_CMD_PACKET_SIZE]; + + +// current usb cdc acm data send status +static usb_cdc_send_status_t usb_cdc_send_status = USB_CDC_SEND_STATUS_INIT; + +// current usb cdc acm data buffer page +static uint8_t current_buffer_page = 0; + +// current usb cdc acm data buffer position +static uint16_t current_end_position = 0; + +// usb cdc acm data send buffer (double buffer) +static uint8_t usb_cdc_tx_buffer[USB_CDC_TX_BUF_PAGE_NUM][USB_CDC_TX_BUF_SIZE]; + +// usb cdc data receive buffer +uint8_t usb_cdc_receive_buffer[CDC_ACM_DATA_PACKET_SIZE]; + +// usb midi receive buffer +uint8_t usb_midi_receive_buffer[AUDIO_MS_PACKET_SIZE]; + +// receive callback functions +static pf_usb_midi_receive_callback_t usb_midi_recv_cb = (pf_usb_midi_receive_callback_t)0; +static pf_usb_cdc_receive_callback_t usb_cdc_recv_cb = (pf_usb_cdc_receive_callback_t)0; + + +static uint8_t midi_cdc_init(usb_dev *udev, uint8_t config_index); +static uint8_t midi_cdc_deinit(usb_dev *udev, uint8_t config_index); +static uint8_t midi_cdc_req_proc(usb_dev *udev, usb_req *req); +static uint8_t midi_cdc_data_in(usb_dev *udev, uint8_t ep_num); +static uint8_t midi_cdc_data_out(usb_dev *udev, uint8_t ep_num); + + +static uint8_t cdc_acm_req_handler (usb_dev *pudev, usb_req *req); +static uint8_t cdc_acm_EP0_RxReady (usb_dev *pudev); + + +static void start_usb_cdc_send_service_irq(void); + + +static line_coding_struct linecoding = +{ + 115200, /* baud rate */ + 0x00, /* stop bits - 1 */ + 0x00, /* parity - none */ + 0x08 /* num of bits 8 */ +}; + +static usb_class_core class_core = +{ + .command = NO_CMD, /*!< device class request command */ + .alter_set = 0, /*!< alternative set */ + .init = midi_cdc_init, /*!< initialize handler */ + .deinit = midi_cdc_deinit, /*!< de-initialize handler */ + .req_proc = midi_cdc_req_proc, /*!< device request handler */ + .data_in = midi_cdc_data_in, /*!< device data in handler */ + .data_out = midi_cdc_data_out, /*!< device data out handler */ + .SOF = NULL, /*!< Start of frame handler */ + .incomplete_isoc_in = NULL, /*!< Incomplete synchronization IN transfer handler */ + .incomplete_isoc_out = NULL, /*!< Incomplete synchronization OUT transfer handler */ +}; + + +void init_usbd_midi(const pf_usb_midi_receive_callback_t midi_recv_cb) +{ + // register_usb_cdc_receive_callback(cdc_recv_cb); + + register_usb_midi_receive_callback(midi_recv_cb); + + eclic_irq_enable(TIMER2_IRQn, 2, 0); + + /* USB device stack configure */ + usbd_init (&g_midi_cdc_udev, USB_CORE_ENUM_FS, &class_core); + + // start_usb_cdc_send_service_irq(); + + /* USB interrupt configure */ + usb_intr_config(); + + /* check if USB device is enumerated successfully */ + while (g_midi_cdc_udev.dev.cur_status != USBD_CONFIGURED) + { + } +} + +// register a callback function to be called when usb midi message received. +void register_usb_midi_receive_callback(const pf_usb_midi_receive_callback_t callback) +{ + usb_midi_recv_cb = callback; +} + +// register a callback function to be called when usb cdc data received. +void register_usb_cdc_receive_callback(const pf_usb_cdc_receive_callback_t callback) +{ + usb_cdc_recv_cb = callback; +} + +int usb_cdc_printf(const char *format, ...) +{ + int written_num = 0; + size_t max_write_num = 0; + + va_list arg; + va_start(arg, format); + + // entry critical section + eclic_global_interrupt_disable(); + max_write_num = USB_CDC_TX_BUF_SIZE - current_end_position; + written_num = vsnprintf( + (char *)&usb_cdc_tx_buffer[current_buffer_page][current_end_position] + ,max_write_num, format, arg); + + if ( ( 0 < written_num ) && ( written_num < max_write_num ) ) + { + current_end_position += written_num; + } + // leave critical section + eclic_global_interrupt_enable(); + + va_end(arg); + + return 0; +} + +// send data and switch send buffer page. +void usb_cdc_send_service_irq(void) +{ + if (RESET != timer_flag_get(TIMER6, TIMER_FLAG_UP)) + { + if (USBD_CONFIGURED == g_midi_cdc_udev.dev.cur_status) + { + // entry critical section + eclic_global_interrupt_disable(); + if ( usb_cdc_send_status != USB_CDC_SEND_STATUS_BUSY ) + { + if ( current_end_position > 0 ) + { + usb_cdc_send_status = USB_CDC_SEND_STATUS_BUSY; + usbd_ep_send(&g_midi_cdc_udev, CDC_IN_EP, &usb_cdc_tx_buffer[current_buffer_page][0] , current_end_position); + current_end_position = 0; + current_buffer_page++; + if ( current_buffer_page >= USB_CDC_TX_BUF_PAGE_NUM ) + { + current_buffer_page = 0; + } + } + } + // leave critical section + eclic_global_interrupt_enable(); + } + + timer_flag_clear(TIMER6, TIMER_FLAG_UP); + } +} + +static uint8_t midi_cdc_init(usb_dev *udev, uint8_t config_index) +{ + midi_cdc_desc_ep_setup(udev); + + // prepare receive data + usbd_ep_recev(udev, MIDI_OUT_EP, usb_midi_receive_buffer, AUDIO_MS_PACKET_SIZE); + usbd_ep_recev(udev, CDC_OUT_EP, usb_cdc_receive_buffer, CDC_ACM_DATA_PACKET_SIZE); + + return 0; +} + + +static uint8_t midi_cdc_deinit(usb_dev *udev, uint8_t config_index) +{ + midi_cdc_desc_ep_clear(udev); + return 0; +} + + +static uint8_t midi_cdc_req_proc(usb_dev *udev, usb_req *req) +{ + switch (req->wIndex) + { + case AUDIO_AC_ITF_NUMBER: + break; + + case AUDIO_MS_ITF_NUMBER: + break; + + case CDC_CDC_ITF_NUMBER: + cdc_acm_req_handler(udev, req); + break; + + case CDC_DATA_ITF_NUMBER: + break; + + default: + break; + } + return 0; +} + + +static uint8_t midi_cdc_data_in(usb_dev *udev, uint8_t ep_num) +{ + if ((CDC_IN_EP & 0x7F) == ep_num) + { + usb_transc *transc = &udev->dev.transc_in[EP_ID(ep_num)]; + + if ((transc->xfer_len % transc->max_len == 0) && (transc->xfer_len != 0)) + { + usbd_ep_send (udev, ep_num, NULL, 0U); + } + else + { + usb_cdc_send_status = USB_CDC_SEND_STATUS_FINISHED; + } + } + + return 0; +} + + +static uint8_t midi_cdc_data_out(usb_dev *udev, uint8_t ep_num) +{ + uint32_t receive_length = 0U; + + if ((EP0_OUT & 0x7F) == ep_num) + { + cdc_acm_EP0_RxReady (udev); + } + else if ((CDC_OUT_EP & 0x7F) == ep_num) + { + receive_length = usbd_rxcount_get(udev, CDC_OUT_EP); + if ( usb_cdc_recv_cb ) + { + usb_cdc_recv_cb(usb_cdc_receive_buffer, receive_length); + } + usbd_ep_recev(udev, CDC_OUT_EP, usb_cdc_receive_buffer, CDC_ACM_DATA_PACKET_SIZE); + } + else if ((MIDI_OUT_EP & 0x7F) == ep_num) + { + receive_length = usbd_rxcount_get(udev, MIDI_OUT_EP); + if ( usb_midi_recv_cb ) + { + usb_midi_recv_cb(usb_midi_receive_buffer, receive_length); + } + usbd_ep_recev(udev, MIDI_OUT_EP, usb_midi_receive_buffer, AUDIO_MS_PACKET_SIZE); + } + else + { + } + + return 0; +} + +/*! + \brief handle the CDC ACM class-specific requests + \param[in] pudev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_req_handler (usb_dev *pudev, usb_req *req) +{ + switch (req->bRequest) + { + case SEND_ENCAPSULATED_COMMAND: + break; + case GET_ENCAPSULATED_RESPONSE: + break; + case SET_COMM_FEATURE: + break; + case GET_COMM_FEATURE: + break; + case CLEAR_COMM_FEATURE: + break; + case SET_LINE_CODING: + /* set the value of the current command to be processed */ + cdc_cmd = req->bRequest; + /* enable EP0 prepare to receive command data packet */ + pudev->dev.transc_out[0].xfer_buf = usb_cmd_buffer; + pudev->dev.transc_out[0].remain_len = req->wLength; + break; + case GET_LINE_CODING: + usb_cmd_buffer[0] = (uint8_t)(linecoding.dwDTERate); + usb_cmd_buffer[1] = (uint8_t)(linecoding.dwDTERate >> 8); + usb_cmd_buffer[2] = (uint8_t)(linecoding.dwDTERate >> 16); + usb_cmd_buffer[3] = (uint8_t)(linecoding.dwDTERate >> 24); + usb_cmd_buffer[4] = linecoding.bCharFormat; + usb_cmd_buffer[5] = linecoding.bParityType; + usb_cmd_buffer[6] = linecoding.bDataBits; + /* send the request data to the host */ + pudev->dev.transc_in[0].xfer_buf = usb_cmd_buffer; + pudev->dev.transc_in[0].remain_len = req->wLength; + break; + case SET_CONTROL_LINE_STATE: + break; + case SEND_BREAK: + break; + default: + break; + } + + return USBD_OK; +} + +/*! + \brief command data received on control endpoint + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_EP0_RxReady (usb_dev *pudev) +{ + if (NO_CMD != cdc_cmd) { + /* process the command data */ + linecoding.dwDTERate = (uint32_t)(usb_cmd_buffer[0] | + (usb_cmd_buffer[1] << 8) | + (usb_cmd_buffer[2] << 16) | + (usb_cmd_buffer[3] << 24)); + + linecoding.bCharFormat = usb_cmd_buffer[4]; + linecoding.bParityType = usb_cmd_buffer[5]; + linecoding.bDataBits = usb_cmd_buffer[6]; + + cdc_cmd = NO_CMD; + } + + return USBD_OK; +} + +// start usb cdc send service routine. +static void start_usb_cdc_send_service_irq(void) +{ + timer_parameter_struct timer_initpara; + + eclic_irq_enable(TIMER6_IRQn, 2, 0); + + timer_struct_para_init(&timer_initpara); + + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.prescaler = 9599;// 96 MHz/ 9600 = 10 kHz + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 10; + + timer_deinit(TIMER6); + timer_init(TIMER6, &timer_initpara); + + timer_update_event_enable(TIMER6); + timer_interrupt_enable(TIMER6,TIMER_INT_UP); + timer_flag_clear(TIMER6, TIMER_FLAG_UP); + timer_update_source_config(TIMER6, TIMER_UPDATE_SRC_GLOBAL); + + /* TIMER6 counter enable */ + timer_enable(TIMER6); +} + diff --git a/firmware/midi2cv/src/drivers/usbfs/midi_cdc_core.h b/firmware/midi2cv/src/drivers/usbfs/midi_cdc_core.h new file mode 100644 index 0000000..f095b48 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/midi_cdc_core.h @@ -0,0 +1,46 @@ +/* + MIT License + + Copyright (c) 2020 nyannkov + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ +#ifndef MIDI_CDC_CORE_H +#define MIDI_CDC_CORE_H + +#include +#include + + + + +typedef int32_t (*pf_usb_midi_receive_callback_t)(const uint8_t *recv_msg, size_t len); +typedef int32_t (*pf_usb_cdc_receive_callback_t)(const uint8_t *recv_data, size_t len); + +extern void register_usb_midi_receive_callback(const pf_usb_midi_receive_callback_t callback); +extern void register_usb_cdc_receive_callback(const pf_usb_cdc_receive_callback_t callback); + +extern void init_usbd_midi(const pf_usb_midi_receive_callback_t midi_recv_cb); + +extern void usb_cdc_send_service_irq(void); + +extern int usb_cdc_printf(const char *format, ...); + +#endif/* MIDI_CDC_CORE_H */ + diff --git a/firmware/midi2cv/src/drivers/usbfs/midi_cdc_desc.c b/firmware/midi2cv/src/drivers/usbfs/midi_cdc_desc.c new file mode 100644 index 0000000..5c09539 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/midi_cdc_desc.c @@ -0,0 +1,386 @@ +/* + MIT License + + Copyright (c) 2020 nyannkov + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ +#include "usbd_core.h" +#include "usbd_enum.h" +#include "midi_cdc_desc.h" + +#define USBD_VID 0xaaaa// replace 0xaaaa with your vid +#define USBD_PID 0xbbbb// replace 0xbbbb with your pid + +#define LITTLE_ENDIAN_16(x) (x) + +static const usb_desc_dev device_descriptor = +{ + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, + .bcdUSB = 0x0200, + .bDeviceClass = 0xEF, + .bDeviceSubClass = 0x02, + .bDeviceProtocol = 0x01, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = LITTLE_ENDIAN_16(0x0100), + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM +}; + +static const usb_descriptor_configuration_set_struct configuration_descriptor= +{ + .config = + {/* Configuration 1 */ + .header = + { + .bLength = 0x09, + .bDescriptorType = USB_DESCTYPE_CONFIG, + }, + .wTotalLength = LITTLE_ENDIAN_16(0x00AF), + .bNumInterfaces = 0x04, /* audio 2 + cdc 2 = 4 */ + .bConfigurationValue = 0x01, + .iConfiguration = 0x00, + .bmAttributes = 0xC0, + .bMaxPower = 0x32, + }, + .usb_iad_audio = + {/* Interface Associated Descriptor */ + .bLength = 0x08, + .bDescriptorType = 0x0B, + .bFirstInterface = AUDIO_AC_ITF_NUMBER, + .bInterfaceCount = 0x02, + .bFunctionClass = 0x01, + .bFunctionSubClass = 0x01, + .bFunctionProtocol = 0x00, + .iFunction = 0x02, + }, + .audio = + {/* Audio device */ + .standard_ac_itf = + {/* Standard AC Interface Descriptor */ + .header = + { + .bLength = 0x09, + .bDescriptorType = USB_DESCTYPE_ITF, + }, + .bInterfaceNumber = AUDIO_AC_ITF_NUMBER, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x00, + .bInterfaceClass = 0x01, + .bInterfaceSubClass = 0x01, + .bInterfaceProtocol = 0x00, + .iInterface = 0x00, + }, + .class_specific_ac_itf = + {/* Class-specific AC Interface Descriptor */ + .bLength = 0x09, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x01, + .bcdADC = LITTLE_ENDIAN_16(0x0100),/* 1.00 */ + .wTotalLength = LITTLE_ENDIAN_16(0x0009), + .bInCollection = 0x01, + .baInterfaceNr = AUDIO_MS_ITF_NUMBER, + }, + .standard_ms_itf = + {/* Standard MS Interface Descriptor */ + .header = + { + .bLength = 0x09, + .bDescriptorType = USB_DESCTYPE_ITF, + }, + .bInterfaceNumber = AUDIO_MS_ITF_NUMBER, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x02, + .bInterfaceClass = 0x01, + .bInterfaceSubClass = 0x03, + .bInterfaceProtocol = 0x00, + .iInterface = 0x00, + }, + .class_specific_ms_itf = + {/* Class-specific MS Interface Descriptor */ + .bLength = 0x07, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x01, + .BcdADC = LITTLE_ENDIAN_16(0x0100), + .wTotalLength = LITTLE_ENDIAN_16(0x0025), + }, + .midi_in_jack_embedded = + {/* MIDI IN Jack Descriptor (Embedded) */ + .bLength = 0x06, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x02, + .bJackType = 0x01,/* embedded */ + .bJackID = 0x01, + .iJack = 0x00, + }, + .midi_in_jack_external = + {/* MIDI In Jack Descriptor (External) */ + .bLength = 0x06, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x02, + .bJackType = 0x02, /* external */ + .bJackID = 0x02, + .iJack = 0x00, + }, + .midi_out_jack_embedded = + {/* MIDI OUT Jack Descriptor (Embedded) */ + .bLength = 0x09, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x03, + .bJackType = 0x01, + .bJackID = 0x03, + .bNtInputPins = 0x01, + .BaSourceID = 0x02, + .BaSourcePin = 0x01, + .iJack = 0x00, + }, + .midi_out_jack_external = + {/* MIDI OUT Jack Descriptor (External) */ + .bLength = 0x09, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x03, + .bJackType = 0x02, + .bJackID = 0x04, + .bNtInputPins = 0x01, + .BaSourceID = 0x01, + .BaSourcePin = 0x01, + .iJack = 0x00, + }, + .bulk_out_ep_desc = + {/* Standard Bulk OUT EndPoint Descriptor */ + .desc_ep = + { + .header = + { + .bLength = 0x09, + .bDescriptorType= 0x05, + }, + .bEndpointAddress = MIDI_OUT_EP, + .bmAttributes = 0x02, + .wMaxPacketSize = LITTLE_ENDIAN_16(AUDIO_MS_PACKET_SIZE), + .bInterval = 0x01, + }, + .bRefresh = 0x00, + .bSynchAddress = 0x00, + }, + .class_specific_ms_bulk_out_ep = + {/* Class-specific Bulk OUT EndPoint Descriptor */ + .bLength = 0x05, + .bDescriptorType = 0x25, + .bDescriptorSubtype = 0x01, + .bNumEmbMIDIJack = 0x01, + .BaAssocJackID = 0x01, + }, + .bulk_in_ep_desc = + {/* Standard Bulk IN EndPoint Descriptor */ + .desc_ep = + { + .header = + { + .bLength = 0x09, + .bDescriptorType= 0x05, + }, + .bEndpointAddress = MIDI_IN_EP, + .bmAttributes = 0x02, + .wMaxPacketSize = LITTLE_ENDIAN_16(AUDIO_MS_PACKET_SIZE), + .bInterval = 0x00, + }, + .bRefresh = 0x00, + .bSynchAddress = 0x00, + }, + .class_specific_ms_bulk_in_ep = + {/* Class-specific Bulk IN EndPoint Descriptor */ + .bLength = 0x05, + .bDescriptorType = 0x25, + .bDescriptorSubtype = 0x01, + .bNumEmbMIDIJack = 0x01, + .BaAssocJackID = 0x03, + }, + }, + .usb_iad_cdc = + {/* Interface Associated Descriptor */ + .bLength = 0x08, + .bDescriptorType = 0x0B, + .bFirstInterface = CDC_CDC_ITF_NUMBER, + .bInterfaceCount = 0x02, + .bFunctionClass = 0x02, + .bFunctionSubClass = 0x02, + .bFunctionProtocol = 0x01, + .iFunction = 0x02, + }, + .cdc = + { + .cdc_cdc_itf = + {/* Interface Descriptor */ + .header = + { + .bLength = 0x09, + .bDescriptorType = 0x04, + }, + .bInterfaceNumber = CDC_CDC_ITF_NUMBER, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x01, + .bInterfaceClass = 0x02, + .bInterfaceSubClass = 0x02, + .bInterfaceProtocol = 0x01, + .iInterface = 0x00, + }, + .header_func_desc = + {/* Header Functional Descriptor */ + .bLength = 0x05, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x00, + .bcdCDC = LITTLE_ENDIAN_16(0x0110), + }, + .call_mng_func_desc = + {/* Call Management Functional Descriptor */ + .bFunctionLength = 0x05, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x01, + .bmCapabilities = 0x00, + .bDataInterface = 0x01, + }, + .acm_func_desc = + {/* ACM Functional Descriptor */ + .bFunctionLength = 0x04, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x02, + .bmCapabilities = 0x02, + }, + .union_func_desc = + {/* Union Functional Descriptor */ + .bFunctionLength = 0x05, + .bDescriptorType = 0x24, + .bDescriptorSubtype = 0x06, + .bMasterInterface = CDC_CDC_ITF_NUMBER, + .bSlaveInterface0 = CDC_DATA_ITF_NUMBER, + }, + .cmd_ep = + {/* Endpoint Descriptor */ + .header = + { + .bLength = 0x07, + .bDescriptorType = 0x05, + }, + .bEndpointAddress = CDC_CMD_EP, + .bmAttributes = 0x03, + .wMaxPacketSize = LITTLE_ENDIAN_16(CDC_ACM_CMD_PACKET_SIZE), + .bInterval = 0x10, + }, + .cdc_data_itf = + {/* Data Class Interface Descriptor */ + .header = + { + .bLength = 0x09, + .bDescriptorType = 0x04, + }, + .bInterfaceNumber = CDC_DATA_ITF_NUMBER, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x02, + .bInterfaceClass = 0x0A, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, + .iInterface = 0x00, + }, + .end_out = + {/* Endpoint OUT Descriptor */ + .header = + { + .bLength = 0x07, + .bDescriptorType = 0x05, + }, + .bEndpointAddress = CDC_OUT_EP, + .bmAttributes = 0x02, + .wMaxPacketSize = LITTLE_ENDIAN_16(CDC_ACM_DATA_PACKET_SIZE), + .bInterval = 0x00, + }, + .end_in = + {/* Endpoint IN Descriptor */ + .header = + { + .bLength = 0x07, + .bDescriptorType = 0x05, + }, + .bEndpointAddress = CDC_IN_EP, + .bmAttributes = 0x02, + .wMaxPacketSize = LITTLE_ENDIAN_16(CDC_ACM_DATA_PACKET_SIZE), + .bInterval = 0x00, + }, + }, +}; + +static const usb_desc_LANGID usbd_language_id_desc = +{ + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + .wLANGID = ENG_LANGID +}; + +static void* const usbd_strings[] = +{ + [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, + [STR_IDX_MFC] = USBD_STRING_DESC("GigaDevice"), + [STR_IDX_PRODUCT] = USBD_STRING_DESC("nano_midi"), + [STR_IDX_SERIAL] = USBD_STRING_DESC("GD32XXX-3.0.0-7z8x9yer") +}; + +usb_core_driver g_midi_cdc_udev = +{ + .dev = + { + .desc = + { + .dev_desc = (uint8_t *)&device_descriptor, + .config_desc = (uint8_t *)&configuration_descriptor, + .strings = usbd_strings + + } + } +}; + +void midi_cdc_desc_ep_setup(usb_dev *udev) +{ + usbd_ep_setup(udev, &configuration_descriptor.audio.bulk_in_ep_desc.desc_ep); + usbd_ep_setup(udev, &configuration_descriptor.audio.bulk_out_ep_desc.desc_ep); + + usbd_ep_setup(udev, &configuration_descriptor.cdc.end_in); + usbd_ep_setup(udev, &configuration_descriptor.cdc.end_out); + usbd_ep_setup(udev, &configuration_descriptor.cdc.cmd_ep); +} + +void midi_cdc_desc_ep_clear(usb_dev *udev) +{ + usbd_ep_clear(udev, configuration_descriptor.audio.bulk_in_ep_desc.desc_ep.bEndpointAddress); + usbd_ep_clear(udev, configuration_descriptor.audio.bulk_out_ep_desc.desc_ep.bEndpointAddress); + + usbd_ep_clear(udev, configuration_descriptor.cdc.end_in.bEndpointAddress); + usbd_ep_clear(udev, configuration_descriptor.cdc.end_out.bEndpointAddress); + usbd_ep_clear(udev, configuration_descriptor.cdc.cmd_ep.bEndpointAddress); +} diff --git a/firmware/midi2cv/src/drivers/usbfs/midi_cdc_desc.h b/firmware/midi2cv/src/drivers/usbfs/midi_cdc_desc.h new file mode 100644 index 0000000..f868e8b --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/midi_cdc_desc.h @@ -0,0 +1,199 @@ +/* + MIT License + + Copyright (c) 2020 nyannkov + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ +#ifndef __MIDI_CDC_DESC_H__ +#define __MIDI_CDC_DESC_H__ + + +#define CDC_ACM_CMD_PACKET_SIZE 0x0008 // 8 byte +#define CDC_ACM_DATA_PACKET_SIZE 0x0040 // 64 byte +#define AUDIO_MS_PACKET_SIZE 0x0040 // 64 byte + +#pragma pack(1) + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint16_t bcdADC; + uint16_t wTotalLength; + uint8_t bInCollection; + uint8_t baInterfaceNr; +} usb_desc_class_specific_ac_itf;/* 9 byte */ + + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint16_t BcdADC; + uint16_t wTotalLength; +} usb_desc_class_specific_ms_itf;/* 7 byte */ + + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bJackType; + uint8_t bJackID; + uint8_t iJack; +} usb_desc_midi_in_jack_desc; /* 6 byte */ + + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bJackType; + uint8_t bJackID; + uint8_t bNtInputPins; + uint8_t BaSourceID; + uint8_t BaSourcePin; + uint8_t iJack; +} usb_desc_midi_out_jack_desc; /* 9 byte */ + + +typedef struct +{ + usb_desc_ep desc_ep; + uint8_t bRefresh; + uint8_t bSynchAddress; +} usb_desc_ep_audio; /* 9 byte */ + + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bNumEmbMIDIJack; + uint8_t BaAssocJackID; +} usb_desc_class_specific_ms_ep; /* 5 byte */ + + +typedef struct +{ + usb_desc_itf standard_ac_itf; + usb_desc_class_specific_ac_itf class_specific_ac_itf; + usb_desc_itf standard_ms_itf; + usb_desc_class_specific_ms_itf class_specific_ms_itf; + usb_desc_midi_in_jack_desc midi_in_jack_embedded; + usb_desc_midi_in_jack_desc midi_in_jack_external; + usb_desc_midi_out_jack_desc midi_out_jack_embedded; + usb_desc_midi_out_jack_desc midi_out_jack_external; + usb_desc_ep_audio bulk_out_ep_desc; + usb_desc_class_specific_ms_ep class_specific_ms_bulk_out_ep; + usb_desc_ep_audio bulk_in_ep_desc; + usb_desc_class_specific_ms_ep class_specific_ms_bulk_in_ep; +} usb_desc_audio; + + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bFirstInterface; + uint8_t bInterfaceCount; + uint8_t bFunctionClass; + uint8_t bFunctionSubClass; + uint8_t bFunctionProtocol; + uint8_t iFunction; +} usb_desc_iad; /* 8 byte */ + + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint16_t bcdCDC; +} usb_desc_header_func_desc; /* 5 byte */ + + +typedef struct +{ + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmCapabilities; + uint8_t bDataInterface; +} usb_desc_call_mng_func_desc; /* 5 byte */ + + +typedef struct +{ + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmCapabilities; +} usb_desc_acm_func_desc; /* 4 byte */ + + +typedef struct +{ + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bMasterInterface; + uint8_t bSlaveInterface0; +} usb_desc_union_func_desc; /* 5 byte */ + + +typedef struct +{ + usb_desc_itf cdc_cdc_itf; + usb_desc_header_func_desc header_func_desc; + usb_desc_call_mng_func_desc call_mng_func_desc; + usb_desc_acm_func_desc acm_func_desc; + usb_desc_union_func_desc union_func_desc; + usb_desc_ep cmd_ep; + usb_desc_itf cdc_data_itf; + usb_desc_ep end_out; + usb_desc_ep end_in; +} usb_desc_cdc; + + +typedef struct +{ + usb_desc_config config; + usb_desc_iad usb_iad_audio; + usb_desc_audio audio; + usb_desc_iad usb_iad_cdc; + usb_desc_cdc cdc; +} usb_descriptor_configuration_set_struct; + +#pragma pack() + + + +extern usb_core_driver g_midi_cdc_udev; + +extern void midi_cdc_desc_ep_setup(usb_dev *udev); +extern void midi_cdc_desc_ep_clear(usb_dev *udev); + +#endif/*__MIDI_CDC_DESC_H__*/ diff --git a/firmware/midi2cv/src/drivers/usbfs/midiconf.h b/firmware/midi2cv/src/drivers/usbfs/midiconf.h new file mode 100644 index 0000000..d4d9152 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/midiconf.h @@ -0,0 +1,37 @@ +/* + MIT License + + Copyright (c) 2019 nyannkov + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +#ifndef __MIDICONF_H__ +#define __MIDICONF_H__ + +#include +#include + +#define __WEAK__ __attribute__((weak)) + +#ifndef MAX_SYS_EX_BUF_SIZE +#define MAX_SYS_EX_BUF_SIZE 256 +#endif + +#endif /* __MIDICONF_H__ */ \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/usb_conf.h b/firmware/midi2cv/src/drivers/usbfs/usb_conf.h new file mode 100644 index 0000000..84fceb2 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/usb_conf.h @@ -0,0 +1,75 @@ +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ +#ifndef __USB_CONF_H__ +#define __USB_CONF_H__ + +#include "gd32vf103.h" + +#ifdef USE_USB_FS +#define USB_FS_CORE +#endif + +#ifdef USB_FS_CORE + #define RX_FIFO_FS_SIZE 128 + #define TX0_FIFO_FS_SIZE 64 + #define TX1_FIFO_FS_SIZE 128 + #define TX2_FIFO_FS_SIZE 0 + #define TX3_FIFO_FS_SIZE 0 +#endif /* USB_FS_CORE */ + +#define USB_SOF_OUTPUT 1 +#define USB_LOW_POWER 1 + +#if defined ( __GNUC__ ) + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ + +#if defined (__GNUC__) /* GNU Compiler */ + #define __ALIGN_END __attribute__ ((aligned (4))) + #define __ALIGN_BEGIN +#else + #define __ALIGN_END + #if defined (__CC_ARM) /* ARM Compiler */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #elif defined (__TASKING__) /* TASKING Compiler */ + #define __ALIGN_BEGIN __align(4) + #endif /* __CC_ARM */ +#endif /* __GNUC__ */ + + +#endif \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/usb_midi_app.c b/firmware/midi2cv/src/drivers/usbfs/usb_midi_app.c new file mode 100644 index 0000000..7359b86 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/usb_midi_app.c @@ -0,0 +1,98 @@ +/* + MIT License + + Copyright (c) 2020 nyannkov + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ +#include "usb_midi_app.h" +#include "midi.h" +//#include "mode4_ymf825.h" +//#include "music_box_ymf825.h" +//#include "single_ymz294.h" + + +#include + +#define MAX_MIDI_HANDLE_LIST_COUNT 2 +#define MIDI_HANDLE_FREE 0 +#define MIDI_HANDLE_OCCUPIED 1 + +#define USB_MIDI_APP_ASSERT(cond) + +typedef struct +{ + uint32_t status; + MIDI_Handle_t hMIDI; +} midi_handle_list_t; + +typedef struct _usb_midi_event_packet +{ + uint8_t header; + uint8_t midi[3]; +} usb_midi_event_packet_t; + +typedef struct +{ + MIDI_Handle_t* (*midi_init)(void); + void (*midi_deinit)(MIDI_Handle_t *phMIDI); +} sound_driver_api_t; + +static midi_handle_list_t hmidi_list[MAX_MIDI_HANDLE_LIST_COUNT]; + + +int32_t usb_midi_proc(const uint8_t *mid_msg, size_t len) +{ + gpio_bit_set(GPIOA, GPIO_PIN_1); + if(gpio_input_bit_get(GPIOA, GPIO_PIN_2)){ + gpio_bit_reset(GPIOA, GPIO_PIN_2); + } else{ + gpio_bit_set(GPIOA, GPIO_PIN_2); + } + return 0; +} + + +MIDI_Handle_t *MIDI_Alloc(void) +{ + uint32_t i = 0; + for ( i = 0; i < MAX_MIDI_HANDLE_LIST_COUNT; i++ ) + { + if ( hmidi_list[i].status == MIDI_HANDLE_FREE ) + { + hmidi_list[i].status = MIDI_HANDLE_OCCUPIED; + return &hmidi_list[i].hMIDI; + } + } + return (MIDI_Handle_t * )0; +} + +void MIDI_Free(MIDI_Handle_t *phMIDI) +{ + uint32_t i = 0; + for ( i = 0; i < MAX_MIDI_HANDLE_LIST_COUNT; i++ ) + { + if ( &hmidi_list[i].hMIDI == phMIDI ) + { + hmidi_list[i].status = MIDI_HANDLE_FREE; + break; + } + } +} + diff --git a/firmware/midi2cv/src/drivers/usbfs/usb_midi_app.h b/firmware/midi2cv/src/drivers/usbfs/usb_midi_app.h new file mode 100644 index 0000000..b4dd370 --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/usb_midi_app.h @@ -0,0 +1,43 @@ +/* + MIT License + + Copyright (c) 2020 nyannkov + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ +#ifndef __USB_MIDI_H__ +#define __USB_MIDI_H__ + +#include +#include + +typedef enum +{ + YMF825_SOUND_DRIVER_MODE4 = 0, + YMF825_SOUND_DRIVER_MUSIC_BOX, + NUM_OF_YMF825_SOUND_DRIVER +} ymf825_sound_driver_t; + + +extern void init_usb_midi_app(void); +extern int32_t usb_midi_proc(const uint8_t *mid_msg, size_t len); +extern int32_t switch_ymf825_sound_driver(ymf825_sound_driver_t driver); +extern ymf825_sound_driver_t get_selected_ymf825_sound_driver(void); + +#endif//__USB_MIDI_H__ diff --git a/firmware/midi2cv/src/drivers/usbfs/usbd_conf.h b/firmware/midi2cv/src/drivers/usbfs/usbd_conf.h new file mode 100644 index 0000000..c30e68a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/usbd_conf.h @@ -0,0 +1,23 @@ +#ifndef __USBD_CONF_H__ +#define __USBD_CONF_H__ + +#include "usb_conf.h" + +#define USBD_CFG_MAX_NUM 1 + + +#define CDC_OUT_EP 0x01U +#define CDC_CMD_EP 0x82U +#define CDC_IN_EP 0x81U + +#define MIDI_OUT_EP 0x02U +#define MIDI_IN_EP 0x83U + +#define AUDIO_AC_ITF_NUMBER 0 +#define AUDIO_MS_ITF_NUMBER 1 +#define CDC_CDC_ITF_NUMBER 2 +#define CDC_DATA_ITF_NUMBER 3 +#define USBD_ITF_MAX_NUM CDC_DATA_ITF_NUMBER + + +#endif//__USBD_CONF_H__ \ No newline at end of file diff --git a/firmware/midi2cv/src/drivers/usbfs/usbd_core.c b/firmware/midi2cv/src/drivers/usbfs/usbd_core.c new file mode 100644 index 0000000..d7a8eae --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/usbd_core.c @@ -0,0 +1,329 @@ +/*! + \file usbd_core.c + \brief USB device mode core functions + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "../Include/usbd_core.h" +#include "../Include/drv_usb_hw.h" + +/* endpoint type */ +const uint32_t ep_type[] = { + [USB_EP_ATTR_CTL] = USB_EPTYPE_CTRL, + [USB_EP_ATTR_BULK] = USB_EPTYPE_BULK, + [USB_EP_ATTR_INT] = USB_EPTYPE_INTR, + [USB_EP_ATTR_ISO] = USB_EPTYPE_ISOC +}; + +/*! + \brief initailizes the USB device-mode stack and load the class driver + \param[in] udev: pointer to USB core instance + \param[in] core: usb core type + \param[in] class_core: class driver + \param[out] none + \retval none +*/ +void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_class_core *class_core) +{ + /* device descriptor, class and user callbacks */ + udev->dev.class_core = class_core; + + /* configure USB capabilites */ + usb_basic_init (&udev->bp, &udev->regs, core); + + /* initailizes the USB core*/ + usb_core_init (udev->bp, &udev->regs); + + /* set device disconnect */ + usbd_disconnect (udev); + + /* initailizes device mode */ + usb_devcore_init (udev); + + /* set device connect */ + usbd_connect (udev); + + udev->dev.cur_status = USBD_DEFAULT; +} + +/*! + \brief endpoint initialization + \param[in] udev: pointer to USB core instance + \param[in] ep_desc: pointer to endpoint descriptor + \param[out] none + \retval none +*/ +uint32_t usbd_ep_setup (usb_core_driver *udev, const usb_desc_ep *ep_desc) +{ + usb_transc *transc; + + uint8_t ep_addr = ep_desc->bEndpointAddress; + uint8_t max_len = ep_desc->wMaxPacketSize; + + /* set endpoint direction */ + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + + transc->ep_addr.dir = 1U; + } else { + transc = &udev->dev.transc_out[ep_addr]; + + transc->ep_addr.dir = 0U; + } + + transc->ep_addr.num = EP_ID(ep_addr); + transc->max_len = max_len; + transc->ep_type = ep_type[ep_desc->bmAttributes & USB_EPTYPE_MASK]; + + /* active USB endpoint function */ + usb_transc_active (udev, transc); + + return 0; +} + +/*! + \brief configure the endpoint when it is disabled + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_clear (usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc; + + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + /* deactive USB endpoint function */ + usb_transc_deactivate (udev, transc); + + return 0; +} + + +/*! + \brief endpoint prepare to receive data + \param[in] udev: pointer to usb core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[in] pbuf: user buffer address pointer + \param[in] len: buffer length + \param[out] none + \retval none +*/ +uint32_t usbd_ep_recev (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len) +{ + usb_transc *transc = &udev->dev.transc_out[EP_ID(ep_addr)]; + + /* setup the transfer */ + transc->xfer_buf = pbuf; + transc->xfer_len = len; + transc->xfer_count = 0; + + if (USB_USE_DMA == udev->bp.transfer_mode) { + transc->dma_addr = (uint32_t)pbuf; + } + + /* start the transfer */ + usb_transc_outxfer (udev, transc); + + return 0; +} + +/*! + \brief endpoint prepare to transmit data + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[in] pbuf: transmit buffer address pointer + \param[in] len: buffer length + \param[out] none + \retval none +*/ +uint32_t usbd_ep_send (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len) +{ + usb_transc *transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + + /* setup the transfer */ + transc->xfer_buf = pbuf; + transc->xfer_len = len; + transc->xfer_count = 0; + + if (USB_USE_DMA == udev->bp.transfer_mode) { + transc->dma_addr = (uint32_t)pbuf; + } + + /* start the transfer */ + usb_transc_inxfer (udev, transc); + + return 0; +} + +/*! + \brief set an endpoint to STALL status + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_stall (usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc = NULL; + + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + transc->ep_stall = 1; + + usb_transc_stall (udev, transc); + + return (0); +} + +/*! + \brief clear endpoint STALLed status + \param[in] udev: pointer to usb core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_stall_clear (usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc = NULL; + + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + transc->ep_stall = 0; + + usb_transc_clrstall (udev, transc); + + return (0); +} + +/*! + \brief flush the endpoint FIFOs + \param[in] udev: pointer to usb core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_fifo_flush (usb_core_driver *udev, uint8_t ep_addr) +{ + if (EP_DIR(ep_addr)) { + usb_txfifo_flush (&udev->regs, EP_ID(ep_addr)); + } else { + usb_rxfifo_flush (&udev->regs); + } + + return (0); +} + +/*! + \brief set USB device address + \param[in] udev: pointer to USB core instance + \param[in] addr: device address to set + \param[out] none + \retval none +*/ +void usbd_addr_set (usb_core_driver *udev, uint8_t addr) +{ + usb_devaddr_set(udev, addr); +} + +/*! + \brief get the received data length + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval USB device operation cur_status +*/ +uint16_t usbd_rxcount_get (usb_core_driver *udev, uint8_t ep_num) +{ + return udev->dev.transc_out[ep_num].xfer_count; +} + +/*! + \brief device connect + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void usbd_connect (usb_core_driver *udev) +{ +#ifndef USE_OTG_MODE + /* connect device */ + usb_dev_connect (udev); + usb_mdelay(3); + +#endif /* USE_OTG_MODE */ +} + +/*! + \brief device disconnect + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void usbd_disconnect (usb_core_driver *udev) +{ +#ifndef USE_OTG_MODE + /* disconnect device for 3ms */ + usb_dev_disconnect (udev); + usb_mdelay(3); +#endif /* USE_OTG_MODE */ +} diff --git a/firmware/midi2cv/src/drivers/usbfs/usbd_core.h b/firmware/midi2cv/src/drivers/usbfs/usbd_core.h new file mode 100644 index 0000000..c4ec47a --- /dev/null +++ b/firmware/midi2cv/src/drivers/usbfs/usbd_core.h @@ -0,0 +1,95 @@ +/*! + \file usbd_core.h + \brief USB device mode core functions protype + + \version 2019-06-05, V1.0.0, firmware for GD32 USBFS&USBHS +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_CORE_H +#define __USBD_CORE_H + + +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +typedef enum +{ + USBD_OK = 0, /*!< status OK */ + USBD_BUSY, /*!< status busy */ + USBD_FAIL, /*!< status fail */ +} usbd_status; + +enum _usbd_status { + USBD_DEFAULT = 1, /*!< default status */ + USBD_ADDRESSED = 2, /*!< address send status */ + USBD_CONFIGURED = 3, /*!< configured status */ + USBD_SUSPENDED = 4 /*!< suspended status */ +}; + +/* function declarations */ + +/* device connect */ +void usbd_connect (usb_core_driver *udev); + +/* device disconnect */ +void usbd_disconnect (usb_core_driver *udev); + +/* set USB device address */ +void usbd_addr_set (usb_core_driver *udev, uint8_t addr); + +/* initailizes the USB device-mode stack and load the class driver */ +void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_class_core *class_core); + +/* endpoint initialization */ +uint32_t usbd_ep_setup (usb_core_driver *udev, const usb_desc_ep *ep_desc); + +/* configure the endpoint when it is disabled */ +uint32_t usbd_ep_clear (usb_core_driver *udev, uint8_t ep_addr); + +/* endpoint prepare to receive data */ +uint32_t usbd_ep_recev (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len); + +/* endpoint prepare to transmit data */ +uint32_t usbd_ep_send (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len); + +/* set an endpoint to STALL status */ +uint32_t usbd_ep_stall (usb_core_driver *udev, uint8_t ep_addr); + +/* clear endpoint STALLed status */ +uint32_t usbd_ep_stall_clear (usb_core_driver *udev, uint8_t ep_addr); + +/* flush the endpoint FIFOs */ +uint32_t usbd_fifo_flush (usb_core_driver *udev, uint8_t ep_addr); + +/* get the received data length */ +uint16_t usbd_rxcount_get (usb_core_driver *udev, uint8_t ep_num); + +#endif /* __USBD_CORE_H */ + diff --git a/firmware/midi2cv/src/gd32vf103.h b/firmware/midi2cv/src/gd32vf103.h new file mode 100644 index 0000000..3aba7a5 --- /dev/null +++ b/firmware/midi2cv/src/gd32vf103.h @@ -0,0 +1,241 @@ +/*! + \file gd32vf103.h + \brief general definitions for GD32VF103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_H +#define GD32VF103_H + +#ifdef cplusplus + extern "C" { +#endif + + /* IO definitions (access restrictions to peripheral registers) */ + /** + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. + */ + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + + /* define value of high speed crystal oscillator (HXTAL) in Hz */ + #if !defined HXTAL_VALUE + #ifdef GD32VF103R_START + #define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */ + #define HXTAL_VALUE_8M HXTAL_VALUE +#elif defined(GD32VF103V_EVAL) || defined(GD32VF103C_START) || defined(GD32VF103T_START) + #define HXTAL_VALUE ((uint32_t)8000000) /*!< value of the external oscillator in Hz */ + #define HXTAL_VALUE_25M HXTAL_VALUE + #else + #error "Please select the target board type used in your application (in gd32vf103.h file)" + #endif + #endif /* high speed crystal oscillator value */ + +/* define startup timeout value of high speed crystal oscillator (HXTAL) */ +#if !defined (HXTAL_STARTUP_TIMEOUT) +#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF) +#endif /* high speed crystal oscillator startup timeout */ + +/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ +#if !defined (IRC8M_VALUE) +#define IRC8M_VALUE ((uint32_t)8000000) +#endif /* internal 8MHz RC oscillator value */ + +/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ +#if !defined (IRC8M_STARTUP_TIMEOUT) +#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) +#endif /* internal 8MHz RC oscillator startup timeout */ + +/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ +#if !defined (IRC40K_VALUE) +#define IRC40K_VALUE ((uint32_t)40000) +#endif /* internal 40KHz RC oscillator value */ + +/* define value of low speed crystal oscillator (LXTAL)in Hz */ +#if !defined (LXTAL_VALUE) +#define LXTAL_VALUE ((uint32_t)32768) +#endif /* low speed crystal oscillator value */ + +/* define interrupt number */ +typedef enum IRQn +{ + + CLIC_INT_RESERVED = 0, /*!< RISC-V reserved */ + CLIC_INT_SFT = 3, /*!< Software interrupt */ + CLIC_INT_TMR = 7, /*!< CPU Timer interrupt */ + CLIC_INT_BWEI = 17, /*!< Bus Error interrupt */ + CLIC_INT_PMOVI = 18, /*!< Performance Monitor */ + + /* interruput numbers */ + WWDGT_IRQn = 19, /*!< window watchDog timer interrupt */ + LVD_IRQn = 20, /*!< LVD through EXTI line detect interrupt */ + TAMPER_IRQn = 21, /*!< tamper through EXTI line detect */ + RTC_IRQn = 22, /*!< RTC alarm interrupt */ + FMC_IRQn = 23, /*!< FMC interrupt */ + RCU_CTC_IRQn = 24, /*!< RCU and CTC interrupt */ + EXTI0_IRQn = 25, /*!< EXTI line 0 interrupts */ + EXTI1_IRQn = 26, /*!< EXTI line 1 interrupts */ + EXTI2_IRQn = 27, /*!< EXTI line 2 interrupts */ + EXTI3_IRQn = 28, /*!< EXTI line 3 interrupts */ + EXTI4_IRQn = 29, /*!< EXTI line 4 interrupts */ + DMA0_Channel0_IRQn = 30, /*!< DMA0 channel0 interrupt */ + DMA0_Channel1_IRQn = 31, /*!< DMA0 channel1 interrupt */ + DMA0_Channel2_IRQn = 32, /*!< DMA0 channel2 interrupt */ + DMA0_Channel3_IRQn = 33, /*!< DMA0 channel3 interrupt */ + DMA0_Channel4_IRQn = 34, /*!< DMA0 channel4 interrupt */ + DMA0_Channel5_IRQn = 35, /*!< DMA0 channel5 interrupt */ + DMA0_Channel6_IRQn = 36, /*!< DMA0 channel6 interrupt */ + ADC0_1_IRQn = 37, /*!< ADC0 and ADC1 interrupt */ + CAN0_TX_IRQn = 38, /*!< CAN0 TX interrupts */ + CAN0_RX0_IRQn = 39, /*!< CAN0 RX0 interrupts */ + CAN0_RX1_IRQn = 40, /*!< CAN0 RX1 interrupts */ + CAN0_EWMC_IRQn = 41, /*!< CAN0 EWMC interrupts */ + EXTI5_9_IRQn = 42, /*!< EXTI[9:5] interrupts */ + TIMER0_BRK_IRQn = 43, /*!< TIMER0 break interrupts */ + TIMER0_UP_IRQn = 44, /*!< TIMER0 update interrupts */ + TIMER0_TRG_CMT_IRQn = 45, /*!< TIMER0 trigger and commutation interrupts */ + TIMER0_Channel_IRQn = 46, /*!< TIMER0 channel capture compare interrupts */ + TIMER1_IRQn = 47, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 48, /*!< TIMER2 interrupt */ + TIMER3_IRQn = 49, /*!< TIMER3 interrupts */ + I2C0_EV_IRQn = 50, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 51, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 52, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 53, /*!< I2C1 error interrupt */ + SPI0_IRQn = 54, /*!< SPI0 interrupt */ + SPI1_IRQn = 55, /*!< SPI1 interrupt */ + USART0_IRQn = 56, /*!< USART0 interrupt */ + USART1_IRQn = 57, /*!< USART1 interrupt */ + USART2_IRQn = 58, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 59, /*!< EXTI[15:10] interrupts */ + RTC_ALARM_IRQn = 60, /*!< RTC alarm interrupt EXTI */ + USBFS_WKUP_IRQn = 61, /*!< USBFS wakeup interrupt */ + + EXMC_IRQn = 67, /*!< EXMC global interrupt */ + + TIMER4_IRQn = 69, /*!< TIMER4 global interrupt */ + SPI2_IRQn = 70, /*!< SPI2 global interrupt */ + UART3_IRQn = 71, /*!< UART3 global interrupt */ + UART4_IRQn = 72, /*!< UART4 global interrupt */ + TIMER5_IRQn = 73, /*!< TIMER5 global interrupt */ + TIMER6_IRQn = 74, /*!< TIMER6 global interrupt */ + DMA1_Channel0_IRQn = 75, /*!< DMA1 channel0 global interrupt */ + DMA1_Channel1_IRQn = 76, /*!< DMA1 channel1 global interrupt */ + DMA1_Channel2_IRQn = 77, /*!< DMA1 channel2 global interrupt */ + DMA1_Channel3_IRQn = 78, /*!< DMA1 channel3 global interrupt */ + DMA1_Channel4_IRQn = 79, /*!< DMA1 channel3 global interrupt */ + + CAN1_TX_IRQn = 82, /*!< CAN1 TX interrupt */ + CAN1_RX0_IRQn = 83, /*!< CAN1 RX0 interrupt */ + CAN1_RX1_IRQn = 84, /*!< CAN1 RX1 interrupt */ + CAN1_EWMC_IRQn = 85, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 86, /*!< USBFS global interrupt */ + + ECLIC_NUM_INTERRUPTS +} IRQn_Type; + +/* includes */ +#include "system_gd32vf103.h" +#include + +/* enum definitions */ +typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; +typedef enum {FALSE = 0, TRUE = !FALSE} bool; +typedef enum {RESET = 0, SET = 1,MAX = 0X7FFFFFFF} FlagStatus; +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; + +/* bit operations */ +#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) +#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) +#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) +#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) + +/* main flash and SRAM memory map */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ +#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */ +#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ +#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ +#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */ + +/* peripheral memory map */ +#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ +#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ +#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */ +#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */ + +/* advanced peripheral bus 1 memory map */ +#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ +#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ +#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ +#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ +#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ +#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ +#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ +#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ +#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */ +#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ +#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ + +/* advanced peripheral bus 2 memory map */ +#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */ +#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ +#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */ +#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ + +/* advanced high performance bus 1 memory map */ +#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */ +#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */ +#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */ +#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ +#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ + +/* define marco USE_STDPERIPH_DRIVER */ +#if !defined USE_STDPERIPH_DRIVER +#define USE_STDPERIPH_DRIVER +#endif +#ifdef USE_STDPERIPH_DRIVER +#include "gd32vf103_libopt.h" +#endif /* USE_STDPERIPH_DRIVER */ + +#ifdef cplusplus +} +#endif +#endif diff --git a/firmware/midi2cv/src/main.c b/firmware/midi2cv/src/main.c new file mode 100644 index 0000000..af19bc9 --- /dev/null +++ b/firmware/midi2cv/src/main.c @@ -0,0 +1,159 @@ +/* + MIT License + + Copyright (c) 2020 nyannkov + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +extern "C" +{ +#include + +//#include "gd32vf103.h" +#include +#include "drivers/usbfs/midi_cdc_core.h" +//#include "freerun_timer.h" +#include "drivers/usbfs/usb_midi_app.h" +//#include "usb_cdc_app.h" +} + +#define BLINK_CYCLE 1000000 + +static void config_eclic(void); +static void enable_periph_clock(void); +static void config_gpio(void); +static void led_blink(void); + +int main(void) +{ + + config_eclic(); + + enable_periph_clock(); + + config_gpio(); + +// init_freerun_timer(); + + // initialize an application of usb midi. +// init_usb_midi_app(); + + // initialize an application of usb cdc. +// init_usb_cdc_app(); + + // start the usb midi cdc device. + init_usbd_midi(usb_midi_proc); + + while(1) + { +// led_blink(); + } + + return 0; +} + +static void enable_periph_clock(void) +{ + // SPI1, LED + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_SPI1); + + // free-running timer + rcu_periph_clock_enable(RCU_TIMER5); + + // USB device + rcu_periph_clock_enable(RCU_TIMER2); + rcu_periph_clock_enable(RCU_TIMER6); + usb_rcu_config(); + +#ifdef USE_SINGLE_YMZ294 + // SPI0 + rcu_periph_clock_enable(RCU_SPI0); + // TIMER1(YMZ294 phiM) + rcu_periph_clock_enable(RCU_TIMER1); // pwm Output +#endif +} + +static void config_gpio(void) +{ + /* SPI1 GPIO config: SCK/PB13, MOSI/PB15 */ + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13 | GPIO_PIN_15); + + // used as SPI1 NSS but configured as GPIO output. + gpio_init(GPIOB, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_12); + + /* SPI1 GPIO config: MISO/PB14 */ + gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_14); + + // RST_N of ymf825 board + gpio_init(GPIOB, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_11); + + // LED + gpio_init(GPIOA, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2); + gpio_init(GPIOA, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_1); + +#ifdef USE_SINGLE_YMZ294 + // YMZ294 AO + gpio_init(GPIOB, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9); + + // YMZ294 /WR and /CS + gpio_init(GPIOA, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0); + + // YMZ294 phiM (4 MHz clock in) + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_1); + + // SN74HC164N /CLR + gpio_init(GPIOA, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_4); + + // SN74HC164N B + gpio_init(GPIOA, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_6); + + /* SPI0 GPIO config:SCK/PA5, MOSI/PA7 */ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_7); +#endif +} + +static void config_eclic(void) +{ + eclic_global_interrupt_enable(); + eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL2_PRIO2); +} + +static void led_blink(void) +{ + static uint32_t cycle_counter = 0; + static int32_t led_output = 0; + + if ( cycle_counter++ >= BLINK_CYCLE ) + { + cycle_counter = 0; + if ( led_output == 0 ) + { + gpio_bit_set(GPIOA, GPIO_PIN_2); + led_output = 1; + } + else + { + gpio_bit_reset(GPIOA, GPIO_PIN_2); + led_output = 0; + } + } +} diff --git a/firmware/midi2cv/src/system_gd32vf103.h b/firmware/midi2cv/src/system_gd32vf103.h new file mode 100644 index 0000000..9626310 --- /dev/null +++ b/firmware/midi2cv/src/system_gd32vf103.h @@ -0,0 +1,60 @@ +/*! + \file system_gd32vf103.h + \brief RISC-V Device Peripheral Access Layer Header File for + GD32VF103 Device Series + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */ + +#ifndef SYSTEM_GD32VF103_H +#define SYSTEM_GD32VF103_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* system clock frequency (core clock) */ +extern uint32_t SystemCoreClock; + +/* function declarations */ +/* initialize the system and update the SystemCoreClock variable */ +extern void SystemInit(void); +/* update the SystemCoreClock with current core clock retrieved from cpu registers */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_GD32VF103_H */ diff --git a/firmware/tools/generateLUT.py b/firmware/tools/generateLUT.py new file mode 100644 index 0000000..91b4f1e --- /dev/null +++ b/firmware/tools/generateLUT.py @@ -0,0 +1,70 @@ +# This program generates LUT (look-up-table) for ADC to frequency conversion +# v0.1 2021-07-30 Johan von Konow +# + +adStart = 1472 #(was 1433) # -3V (midi 0) +adEnd = 3584 #(was 3687) # +8V > midi 127 (7.58V) +samplingFrequency = 44400 +periodLength = 65536 + + +def ad_2_xStep(ad): + return (2*periodLength*(55 * pow(2, (ad-128)/192-39/4))/samplingFrequency) + + +def midi_2_freq(midi): + return (55*pow(2, ((midi-33)/12))) + + +def freq_2_xStep(freq): + return((2*periodLength*freq)/samplingFrequency) + + +def quantize(ad): + i = 0 + while (ad > midiStep[i]): + if(i < len(midiStep)-1): + i += 1 + else: + break + if(ad-midiStep[i-1] > midiStep[i]-ad): + return(midiStep[i]) +# return(i) + else: + return(midiStep[i-1]) +# return(i-1) + + +lut = [] +for x in range(adStart, adEnd + 1): + lut.append(ad_2_xStep(x)) + +midiFreq = [] +for x in range(0, 127+1): + midiFreq.append(midi_2_freq(x)) + +midiStep = [] +for x in range(0, 127+1): + midiStep.append(freq_2_xStep(midi_2_freq(x))) + +q_lut = [] +for x in range(adStart, adEnd + 1): + q_lut.append(quantize(ad_2_xStep(x))) + +# print(ad_2_xStep(2611.2)) + +#print("const uint16_t freq["+str(len(lut)) + "] = {" + ', '.join(str(int(x)) for x in lut) + "};") +#print() +#print("const uint16_t qfreq["+str(len(q_lut)) + "] = {" + ', '.join(str(int(x)) for x in q_lut) + "};") + +print("const float freq["+str(len(lut)) + "] = {" + ', '.join(str(x) for x in lut) + "};") +#print() +#print("const float qfreq["+str(len(q_lut)) + "] = {" + ', '.join(str(x) for x in q_lut) + "};") + +#print(midiStep) +#print(quantize(31137)) +#print(quantize(31139)) + +### test that formula below results in correct quantization (removing need for dedicated q_lut) +#for x in range(adStart, adStart + 20): +# print("x" + str(x) + ":" + str(lut[int((x-adStart+8)/16)*16])) \ No newline at end of file diff --git a/firmware/tools/generateMenu.py b/firmware/tools/generateMenu.py new file mode 100644 index 0000000..a28abdf --- /dev/null +++ b/firmware/tools/generateMenu.py @@ -0,0 +1,106 @@ +# This program generates C code for menu navigation from a human readable menu file +# input file need to use tabs for menu depth (not spaces) +# input files is assumed to have "back" element first at a new level +# input file can contain "|" and position for fixed adresses +# v0.8 2021-06-21 Johan von Konow +# +# example menu: +# settings +# back +# about|131 +# calibrate|132 +# +# ==> generates: +# const char *menuTxt[] = {"settings", "back", "about", "calibrate"}; +# uint8_t menuPre[] = {0, 1, 1, 2}; +# uint8_t menuNxt[] = {0, 2, 3, 3}; +# uint8_t menuSel[] = {2, 0, 131, 132}; + + +filepath = 'menu.txt' # <== file to parse +# open file and create lvl (menu depth / tabCount) txt and jmp array +id = 0 +txt = [] +jmp = [] +lvl = [] +define = [] +for line in open(filepath, "r"): + lvl.append(0) + # avoid removing last char at eof + if line[-1:] != "\n": + line += ("\n") + i = 0 + while line[i] == '\t': + lvl[id] += 1 + i += 1 + # create txt array (name of the menu items) + jmpPos = line.find('|') + txt.append(line[i: jmpPos]) + # create jmp array (fixed jump for functions) + if jmpPos > 0: + jmp.append(int(line[jmpPos + 1: -1])) + define.append(line[i: jmpPos].replace(" ","_") +" " + line[jmpPos + 1: -1]) + else: + jmp.append(0) + id += 1 + +# create id array (for print / debugging assistance) +ida = [] +for x in range(len(lvl)): + ida.append(x) + +# create prev array +pre = [] +for id in range(len(lvl)): + i = 1 + pre.append(id) + if(id - i >= 0): + while lvl[id] < lvl[id-i]: + i += 1 + if(id - i == 0): + break + if(id-i < len(lvl)): + if (lvl[id] == lvl[id-i]): + pre[id] = id-i + +# create next array +nxt = [] +for id in range(len(lvl)): + i = 1 + nxt.append(id) + if(id + i < len(lvl)): + while lvl[id] < lvl[id+i]: + i += 1 + if(id + i >= len(lvl)): + break + if(id+i < len(lvl)): + if (lvl[id] == lvl[id+i]): + nxt[id] = id+i + +# create select array +sel = [] +for id in range(len(lvl)): + sel.append(id) + # enter next lvl?(skips first element (back)) + if(id+2 < len(lvl)): + if (lvl[id] + 1 == lvl[id+1] & lvl[id] + 1 == lvl[id+2]): + sel[id] = id+2 + # back to previous lvl? + if(id > 0): + if (lvl[id] - 1 == lvl[id-1]): + sel[id] = id-1 + # jump to fixed position? + if jmp[id] > 0: + sel[id] = jmp[id] + +#print("row: " + str(ida)) +#print("lev: " + str(lvl)) +#print("jmp: " + str(jmp)) +#print("jmp: " + str(txt)) +#print("define: " + str(define)) +#print() +print("const char *menuTxt[] = {\"" + '\", \"'.join(str(x) for x in txt) + "\"};") +print("uint8_t menuPre[] = {" + ', '.join(str(x) for x in pre) + "};") +print("uint8_t menuNxt[] = {" + ', '.join(str(x) for x in nxt) + "};") +print("uint8_t menuSel[] = {" + ', '.join(str(x) for x in sel) + "};") +print("#define mode_" + "\n#define mode_".join(str(x) for x in define)) diff --git a/firmware/tools/img.py b/firmware/tools/img.py new file mode 100644 index 0000000..db25d95 --- /dev/null +++ b/firmware/tools/img.py @@ -0,0 +1,102 @@ + +import numpy as np +import cv2 # pip install opencv-python +import matplotlib.pyplot as plt # used to show image +import os # used for filesize + + +def show(img, figsize=(10, 10), title="Image"): + figure = plt.figure(figsize=figsize) + plt.imshow(img) + plt.show() + + +def monochrome(img): + encoded = [] + th = 127 + for pixel in img: + if pixel < th: + encoded.append(0) + else: + encoded.append(1) + return np.array(encoded) + + +def xorRowCompress(img, col): + for x in range(1, len(img)-col): + img[len(img)-x] ^= img[len(img)-x-col] + return np.array(img) + + +def RLE_encoding(img): + encoded = [] + count = -1 + prev = 0 + for pixel in img: + if prev != pixel: + encoded.append(count) + prev = pixel + count = -1 + if count == 254: + encoded.append(255) + count = -1 + count += 1 + encoded.append(count) + return np.array(encoded) + + +def combo_decode(encoded): + decoded = [] + preRow = [0] * 240 + pixel = 0 + invert = 0 + x = 0 + for pixelCount in encoded: + if pixelCount < 255: + pixelCount += 1 + invert = 1 + for z in range(pixelCount): + preRow[x] ^= pixel + decoded.append(preRow[x]) + x += 1 + if x == 240: + x = 0 + if invert == 1: + pixel ^= 1 + invert = 0 + return np.array(decoded) + + +fpath = "in.png" +img = cv2.imread(fpath, 0) +shape = img.shape +fimg = img.flatten() +fimg = monochrome(fimg) +ximg = fimg # copy for file size comparison +# show(fimg.reshape(shape)) +xorRowCompress(ximg, 240) +encoded = RLE_encoding(ximg) # <== encoded contains the compressed image + +# decode and show to verify result +oimg = combo_decode(encoded) +show(oimg.reshape(shape)) + +# save with different file formats for file size comparison +cv2.imwrite("out.tif", fimg.reshape(shape)) +cv2.imwrite("out.png", fimg.reshape(shape)) +cv2.imwrite("out.jpg", fimg.reshape(shape)) +f = open("out.jvk", "wb") +for x in encoded.astype(np.uint8): + f.write(x) +f.close() + +# print size of each file +print("16bit size:" + str(len(fimg)*2)) +print("mono size:" + str(len(fimg)/8)) +files = ["out.tif", "out.jpg", "out.png", "out.jvk"] +for f in files: + print(f"File: {f} => Size: {os.path.getsize(f)} Bytes") +print("encoded bytes: "+str(len(encoded))) + +print("\nconst uint8_t img["+str(len(encoded))+"] = {" + ','.join(str(x) + for x in encoded.astype(np.uint8)) + "};") diff --git a/firmware/tools/in.png b/firmware/tools/in.png new file mode 100644 index 0000000000000000000000000000000000000000..03b8c28f8b40a239e77c936ef0c790d022481c57 GIT binary patch literal 741 zcmVEX>4Tx04R}tkv&MmP!xqvQ>7x64t5Yx$xxjvh>AE$6^me@v=v%)FnQ@8G-*gu zTpR`0f`dPcRRqpci*4Yr{qlr_(bA4rW+RV2Jy_M zrE}gV4zrS^5T6r|8+1Y9N3P2*zi}=)Ebz>*kx9)Hhl#~v2g@DIN`^{2O&n2Fjq-)8 z%L?Z$&T6H`TKD8H4Cb|!G}mbjA&w;^kc0>sHIz|-g(&SBDJD{M9`o=II{qZNWO9|k z$gzMbR7j2={11N5)+|g-x=Fzp(EVcDAEQ8E7iiXP`}^3on+e)kfB*E-v9@P zz*v#8*FE0d(>b?)ds_4R0Z<8YnWgrR8vp_CX>@2HM@dakSAh-}0002INkl$L>(6j2UbRK_n^xn3^3{BeBao)$C;rEAf)qV#Zn0 zz?g%^bf*%}5rCc)agFJ58FpK5O*C-}A~Tl0&9w5%ayZ2c&z@(;^UU>JpJH`5_d6^P zH@3qsU#b|o_9?^gO7>WDY$I`h{2MEdrS{Y XB?h)B0`!!J00000NkvXXu0mjfzYaLL literal 0 HcmV?d00001 diff --git a/firmware/tools/menu.txt b/firmware/tools/menu.txt new file mode 100644 index 0000000..6727416 --- /dev/null +++ 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