From 708b07c352fcacee78ca82dd61cee5b4e70b8c38 Mon Sep 17 00:00:00 2001
From: nogieman <lalithchandram@gmail.com>
Date: Fri, 13 Feb 2026 17:42:30 +0530
Subject: [PATCH] refactor(Sigmoid): Refactor code to remove lint warnings -
 Adjusted widths of data registers in `interpolator_engine.v`. - Named
 generated Element wise blocks.

---
 src/rtl/element_wise_op/element_wise_op.v     |  2 -
 src/rtl/element_wise_op/top_element_wise.v    |  8 +-
 src/rtl/tanh_sigmoid/input_range_decoder.v    |  1 -
 src/rtl/tanh_sigmoid/interpolator_engine.v    | 81 +++++++++----------
 .../tanh_sigmoid/tanh_interpolator_engine.v   | 40 ++++-----
 .../tanh_sigmoid/top_Tanh_Sigmoid_Engine.v    | 26 +++---
 6 files changed, 74 insertions(+), 84 deletions(-)

diff --git a/src/rtl/element_wise_op/element_wise_op.v b/src/rtl/element_wise_op/element_wise_op.v
index 3038f427..f8ad1e14 100644
--- a/src/rtl/element_wise_op/element_wise_op.v
+++ b/src/rtl/element_wise_op/element_wise_op.v
@@ -80,7 +80,6 @@ end
   always@(posedge clkin) tanh_sigmoid <= (EltWise_type == `ELTWISE_SIG) ? 1 : 0;
   wire signed [DATA_WIDTH_OB-1:0] w_tanh_output;
   top_Tanh_Sigmoid_Engine#(
-    .DATA_WIDTH(DATA_WIDTH),
     .SCALE_WIDTH(DATA_WIDTH+SHIFT_BITS),
     .LUT_SIZE(),
     .OUT_DATA_WIDTH(DATA_WIDTH_OB)
@@ -208,7 +207,6 @@ end
   always@(posedge clkin) tanh_sigmoid <= (EltWise_type == `ELTWISE_SIG) ? 1 : 0;
   wire signed [DATA_WIDTH_OB-1:0] w_tanh_output;
   top_Tanh_Sigmoid_Engine_lut#(
-    .DATA_WIDTH(DATA_WIDTH),
     .SCALE_WIDTH(DATA_WIDTH+SHIFT_BITS),
     .LUT_SIZE(),
     .OUT_DATA_WIDTH(DATA_WIDTH_OB)
diff --git a/src/rtl/element_wise_op/top_element_wise.v b/src/rtl/element_wise_op/top_element_wise.v
index 8b14d395..0f6c849f 100644
--- a/src/rtl/element_wise_op/top_element_wise.v
+++ b/src/rtl/element_wise_op/top_element_wise.v
@@ -61,7 +61,7 @@ reg [ELTWISE_QUANT_SHIFT-1:0] eltwise_fp_bit_shift_;
 always@(EltWise_type) begin
     case (EltWise_type)
         `ELTWISE_SIG, `ELTWISE_TANH: eltwise_fp_bit_shift_ <= 16;
-        `ELTWISE_ADD, `ELTWISE_SUB, `ELTWISE_MUL: eltwise_fp_bit_shift_ <= ELTWISE_FP_BIT_SHIFT;
+        `ELTWISE_ADD, `ELTWISE_SUB, `ELTWISE_MULT: eltwise_fp_bit_shift_ <= ELTWISE_FP_BIT_SHIFT;
         default: eltwise_fp_bit_shift_ <= ELTWISE_FP_BIT_SHIFT;
     endcase
 end
@@ -160,8 +160,8 @@ EltWise_controller #(
 
 genvar i;
 generate
-    for(i=0;i<N;i=i+1)begin
-      if(i < 8) begin
+    for (i = 0; i < N ;i = i + 1) begin
+      if(i < 8) begin : ELTWISE_INST_DSP
         element_wise_op#(
             .DATA_WIDTH(DATA_WIDTH),
             .ELTWISE_TYPE_WIDTH(ELTWISE_TYPE_WIDTH),
@@ -190,7 +190,7 @@ generate
         );
       /* Duplicate modules from element_wise_op to interpolator_engine have
       been created for lut-based instantiation. */
-      end else begin
+      end else begin : ELTWISE_INST_LUT
         element_wise_op_lut #(
             .DATA_WIDTH(DATA_WIDTH),
             .ELTWISE_TYPE_WIDTH(ELTWISE_TYPE_WIDTH),
diff --git a/src/rtl/tanh_sigmoid/input_range_decoder.v b/src/rtl/tanh_sigmoid/input_range_decoder.v
index c9c9d1e5..20d1121b 100644
--- a/src/rtl/tanh_sigmoid/input_range_decoder.v
+++ b/src/rtl/tanh_sigmoid/input_range_decoder.v
@@ -15,7 +15,6 @@ module input_range_decoder#(
 );
 
     // floating point precision = 16 bits
-    localparam DATA_SAMPLE_MIN = 32'd0; // 0.0 * 2^16
     localparam DATA_SAMPLE_MAX = 32'd229376; // 3.5 * 2^16
 
     reg [DATA_WIDTH-1 : 0] r_data;
diff --git a/src/rtl/tanh_sigmoid/interpolator_engine.v b/src/rtl/tanh_sigmoid/interpolator_engine.v
index 920f6c62..400f6787 100644
--- a/src/rtl/tanh_sigmoid/interpolator_engine.v
+++ b/src/rtl/tanh_sigmoid/interpolator_engine.v
@@ -17,7 +17,6 @@ module interpolator_engine#(
 );
 
     localparam DATA_SAMPLE_MIN = 32'd0;
-    localparam DATA_SAMPLE_MAX = 32'd229376;
     
     // LUTs for data_samples, slope_vaues, and tanh values
     (*syn_ramstyle = "block_ram"*) reg [DATA_WIDTH-1:0] data_samples_lut [0:128];
@@ -84,15 +83,15 @@ module interpolator_engine#(
     end
 
     // Read values from LUTs
-    reg signed [DATA_WIDTH -11 -1:0] data_sample; // reduced width to save resources
-    reg [DATA_WIDTH - 15 -2:0] slope_value;
-    reg signed [DATA_WIDTH-15 -1:0] tanh_value;
+    reg signed [DATA_WIDTH  -1:0] data_sample;
+    reg [(DATA_WIDTH/2)-1:0] slope_value; // reduced width to save resources
+    reg signed [DATA_WIDTH -1:0] tanh_value;
     reg valid_lut_data;
     always@(posedge i_clk) begin
         if(valid_index) begin
-            data_sample <= data_samples_lut[data_sample_index][DATA_WIDTH-11-1:0];
-            slope_value <= slope_values_lut[data_sample_index][DATA_WIDTH-15-2:0];
-            tanh_value <= tanh_values_lut[data_sample_index][DATA_WIDTH-15-1:0];
+            data_sample <= data_samples_lut[data_sample_index][DATA_WIDTH-1:0];
+            slope_value <= slope_values_lut[data_sample_index][(DATA_WIDTH/2)-1:0];
+            tanh_value <= tanh_values_lut[data_sample_index][DATA_WIDTH-1:0];
             valid_lut_data <= 1'b1;
         end
         else valid_lut_data <= 1'b0;
@@ -102,30 +101,29 @@ module interpolator_engine#(
     // pipeline registers to synchronize the input data with the read data from LUTs
     reg [DATA_WIDTH-1:0] r_interpolator_data;
     reg r_interpolator_datavalid;
+
     genvar i;
     generate
-        for (i = 0; i <= 2; i = i + 1) begin : pipeline_regs
+        for (i = 0; i < 2; i = i + 1) begin : pipeline_regs
             reg [DATA_WIDTH-1:0] delay_data_reg;
             reg delay_valid_reg;
-            if(i == 0) begin
+
+            if (i == 0) begin : pipeline_regs1
                 always @(posedge i_clk) begin
-                    delay_data_reg <= i_interpolator_data;
+                    delay_data_reg  <= i_interpolator_data;
                     delay_valid_reg <= i_interpolator_datavalid;
-                end 
-            end 
-            else if(i==2) begin
-                always @(posedge i_clk) begin
-                    r_interpolator_data <= pipeline_regs[i-1].delay_data_reg;
-                    r_interpolator_datavalid <= pipeline_regs[i-1].delay_valid_reg;
                 end
-            end
-            else begin
+            end else begin : pipeline_regs2
                 always @(posedge i_clk) begin
-                    delay_data_reg <= pipeline_regs[i-1].delay_data_reg;
+                    delay_data_reg  <= pipeline_regs[i-1].delay_data_reg;
                     delay_valid_reg <= pipeline_regs[i-1].delay_valid_reg;
                 end
             end
         end
+        always @(posedge i_clk) begin
+            r_interpolator_data      <= pipeline_regs[1].delay_data_reg;
+            r_interpolator_datavalid <= pipeline_regs[1].delay_valid_reg;
+        end
     endgenerate
 
     reg [DATA_WIDTH-1:0] r_scaled_data; // reduced from 2*DATA_WIDTH to save resources.
@@ -141,7 +139,7 @@ module interpolator_engine#(
             3. Add the multiplier result of step 2 with corrsponding tanh_value from lut
     */
 
-    reg signed [DATA_WIDTH/2:0] diff_data;
+    reg signed [(DATA_WIDTH/2):0] diff_data;
     reg diff_valid;
     always@(posedge i_clk) begin
         if(r_interpolator_datavalid & valid_lut_data) begin
@@ -150,7 +148,7 @@ module interpolator_engine#(
         end
         else diff_valid <= 1'b0;
     end
-    reg signed [DATA_WIDTH/2:0] r_slope_value;
+    reg signed [(DATA_WIDTH/2)-1:0] r_slope_value;
     always@(posedge i_clk) r_slope_value <= slope_value;
 
     // Scale the offset difference by the slope value
@@ -197,7 +195,6 @@ module interpolator_engine_lut#(
 );
 
     localparam DATA_SAMPLE_MIN = 32'd0;
-    localparam DATA_SAMPLE_MAX = 32'd229376;
     
     // LUTs for data_samples, slope_vaues, and tanh values
     (*syn_ramstyle = "block_ram"*) reg [DATA_WIDTH-1:0] data_samples_lut [0:128];
@@ -264,48 +261,46 @@ module interpolator_engine_lut#(
     end
 
     // Read values from LUTs
-    reg signed [DATA_WIDTH -11 -1:0] data_sample; // reduced width to save resources
-    reg [DATA_WIDTH - 15 -2:0] slope_value;
-    reg signed [DATA_WIDTH-15 -1:0] tanh_value;
+    reg signed [DATA_WIDTH  -1:0] data_sample;
+    reg [(DATA_WIDTH/2)-1:0] slope_value; // reduced width to save resources
+    reg signed [DATA_WIDTH -1:0] tanh_value;
     reg valid_lut_data;
     always@(posedge i_clk) begin
         if(valid_index) begin
-            data_sample <= data_samples_lut[data_sample_index][DATA_WIDTH-11-1:0];
-            slope_value <= slope_values_lut[data_sample_index][DATA_WIDTH-15-2:0];
-            tanh_value <= tanh_values_lut[data_sample_index][DATA_WIDTH-15-1:0];
+            data_sample <= data_samples_lut[data_sample_index][DATA_WIDTH-1:0];
+            slope_value <= slope_values_lut[data_sample_index][(DATA_WIDTH/2)-1:0];
+            tanh_value <= tanh_values_lut[data_sample_index][DATA_WIDTH-1:0];
             valid_lut_data <= 1'b1;
         end
         else valid_lut_data <= 1'b0;
     end
-
     // Interpolation calculation
     // pipeline registers to synchronize the input data with the read data from LUTs
     reg [DATA_WIDTH-1:0] r_interpolator_data;
     reg r_interpolator_datavalid;
+
     genvar i;
     generate
-        for (i = 0; i <= 2; i = i + 1) begin : pipeline_regs
+        for (i = 0; i < 2; i = i + 1) begin : pipeline_regs
             reg [DATA_WIDTH-1:0] delay_data_reg;
             reg delay_valid_reg;
-            if(i == 0) begin
+
+            if (i == 0) begin : pipeline_regs1
                 always @(posedge i_clk) begin
-                    delay_data_reg <= i_interpolator_data;
+                    delay_data_reg  <= i_interpolator_data;
                     delay_valid_reg <= i_interpolator_datavalid;
-                end 
-            end 
-            else if(i==2) begin
-                always @(posedge i_clk) begin
-                    r_interpolator_data <= pipeline_regs[i-1].delay_data_reg;
-                    r_interpolator_datavalid <= pipeline_regs[i-1].delay_valid_reg;
                 end
-            end
-            else begin
+            end else begin : pipeline_regs2
                 always @(posedge i_clk) begin
-                    delay_data_reg <= pipeline_regs[i-1].delay_data_reg;
+                    delay_data_reg  <= pipeline_regs[i-1].delay_data_reg;
                     delay_valid_reg <= pipeline_regs[i-1].delay_valid_reg;
                 end
             end
         end
+        always @(posedge i_clk) begin
+            r_interpolator_data      <= pipeline_regs[1].delay_data_reg;
+            r_interpolator_datavalid <= pipeline_regs[1].delay_valid_reg;
+        end
     endgenerate
 
     (* syn_use_dsp = "no" *) reg [DATA_WIDTH-1:0] r_scaled_data; // reduced from 2*DATA_WIDTH to save resources.
@@ -321,7 +316,7 @@ module interpolator_engine_lut#(
             3. Add the multiplier result of step 2 with corrsponding tanh_value from lut
     */
 
-    reg signed [DATA_WIDTH/2:0] diff_data;
+    reg signed [(DATA_WIDTH/2):0] diff_data;
     reg diff_valid;
     always@(posedge i_clk) begin
         if(r_interpolator_datavalid & valid_lut_data) begin
@@ -330,7 +325,7 @@ module interpolator_engine_lut#(
         end
         else diff_valid <= 1'b0;
     end
-    reg signed [DATA_WIDTH/2:0] r_slope_value;
+    reg signed [(DATA_WIDTH/2)-1:0] r_slope_value;
     always@(posedge i_clk) r_slope_value <= slope_value;
 
     // Scale the offset difference by the slope value
diff --git a/src/rtl/tanh_sigmoid/tanh_interpolator_engine.v b/src/rtl/tanh_sigmoid/tanh_interpolator_engine.v
index 95579f7b..09642d60 100644
--- a/src/rtl/tanh_sigmoid/tanh_interpolator_engine.v
+++ b/src/rtl/tanh_sigmoid/tanh_interpolator_engine.v
@@ -55,28 +55,28 @@ module tanh_interpolator_engine#(
     reg r_select;
     genvar i;
     generate
-        for (i = 0; i <= 5; i = i + 1) begin : pipeline_regs_select
+        for (i = 0; i < 5; i = i + 1) begin : pipeline_regs_select
             reg delayed_select;
-            if(i == 0) begin
+            if(i == 0) begin : pipeline_regs_select1
                 always @(posedge i_clk) delayed_select <= w_select; 
             end 
-            else if(i==5) begin
-                always @(posedge i_clk) r_select <= pipeline_regs_select[i-1].delayed_select;
-            end
-            else begin
+            else begin : pipeline_regs_select2
                 always @(posedge i_clk) delayed_select <= pipeline_regs_select[i-1].delayed_select;
             end
         end
+        always@(posedge i_clk) begin
+          r_select <= pipeline_regs_select[4].delayed_select;
+        end
     endgenerate
 
     // Output selection logic
     always@(*) begin
       if(r_select) begin
-        o_data       <= w_interpolated_data;
-        o_data_valid <= w_interpolated_data_valid;
+        o_data       = w_interpolated_data;
+        o_data_valid = w_interpolated_data_valid;
       end else begin
-        o_data       <= 0;
-        o_data_valid <= 1'b0;
+        o_data       = 0;
+        o_data_valid = 1'b0;
       end
     end
     
@@ -140,28 +140,28 @@ module tanh_interpolator_engine_lut#(
     reg r_select;
     genvar i;
     generate
-        for (i = 0; i <= 5; i = i + 1) begin : pipeline_regs_select
+        for (i = 0; i < 5; i = i + 1) begin : pipeline_regs_select
             reg delayed_select;
-            if(i == 0) begin
+            if(i == 0) begin : pipeline_regs_select1
                 always @(posedge i_clk) delayed_select <= w_select; 
             end 
-            else if(i==5) begin
-                always @(posedge i_clk) r_select <= pipeline_regs_select[i-1].delayed_select;
-            end
-            else begin
+            else begin : pipeline_regs_select2
                 always @(posedge i_clk) delayed_select <= pipeline_regs_select[i-1].delayed_select;
             end
         end
+        always@(posedge i_clk) begin
+          r_select <= pipeline_regs_select[4].delayed_select;
+        end
     endgenerate
 
     // Output selection logic
     always@(*) begin
       if(r_select) begin
-        o_data       <= w_interpolated_data;
-        o_data_valid <= w_interpolated_data_valid;
+        o_data       = w_interpolated_data;
+        o_data_valid = w_interpolated_data_valid;
       end else begin
-        o_data       <= 0;
-        o_data_valid <= 1'b0;
+        o_data       = 0;
+        o_data_valid = 1'b0;
       end
     end
     
diff --git a/src/rtl/tanh_sigmoid/top_Tanh_Sigmoid_Engine.v b/src/rtl/tanh_sigmoid/top_Tanh_Sigmoid_Engine.v
index 5a416fd6..49456b3f 100644
--- a/src/rtl/tanh_sigmoid/top_Tanh_Sigmoid_Engine.v
+++ b/src/rtl/tanh_sigmoid/top_Tanh_Sigmoid_Engine.v
@@ -1,5 +1,4 @@
 module top_Tanh_Sigmoid_Engine#(
-    parameter DATA_WIDTH    = 8,
     parameter SCALE_WIDTH   = 32,
     parameter FP_BITS       = 16,
     parameter LUT_SIZE      = 128,
@@ -57,18 +56,18 @@ module top_Tanh_Sigmoid_Engine#(
     reg r_sign;
     genvar i;
     generate
-        for (i = 0; i <= 7; i = i + 1) begin : pipeline_regs_sign
+        for (i = 0; i < 7; i = i + 1) begin : pipeline_regs_sign
             reg sign;
-            if(i == 0) begin
+            if(i == 0) begin : pipeline_regs_sign1
                 always @(posedge i_clk) sign <= is_sign; 
             end 
-            else if(i==7) begin
-                always @(posedge i_clk) r_sign <= pipeline_regs_sign[i-1].sign;
-            end
-            else begin
+            else begin : pipeline_regs_sign2
                 always @(posedge i_clk) sign <= pipeline_regs_sign[i-1].sign;
             end
         end
+        always@(posedge i_clk) begin
+          r_sign <= pipeline_regs_sign[6].sign;
+        end
     endgenerate
 
     // Post-processing of tanh interpolator engine output
@@ -85,7 +84,6 @@ module top_Tanh_Sigmoid_Engine#(
 endmodule
 
 module top_Tanh_Sigmoid_Engine_lut#(
-    parameter DATA_WIDTH    = 8,
     parameter SCALE_WIDTH   = 32,
     parameter FP_BITS       = 16,
     parameter LUT_SIZE      = 128,
@@ -143,18 +141,18 @@ module top_Tanh_Sigmoid_Engine_lut#(
     reg r_sign;
     genvar i;
     generate
-        for (i = 0; i <= 7; i = i + 1) begin : pipeline_regs_sign
+        for (i = 0; i < 7; i = i + 1) begin : pipeline_regs_sign
             reg sign;
-            if(i == 0) begin
+            if(i == 0) begin : pipeline_regs_sign1
                 always @(posedge i_clk) sign <= is_sign; 
             end 
-            else if(i==7) begin
-                always @(posedge i_clk) r_sign <= pipeline_regs_sign[i-1].sign;
-            end
-            else begin
+            else begin : pipeline_regs_sign2
                 always @(posedge i_clk) sign <= pipeline_regs_sign[i-1].sign;
             end
         end
+        always@(posedge i_clk) begin
+          r_sign <= pipeline_regs_sign[6].sign;
+        end
     endgenerate
 
     // Post-processing of tanh interpolator engine output