From 2cc2db62425a34859d6676dc71b6ed14565037bf Mon Sep 17 00:00:00 2001 From: Logan Lavigne Date: Mon, 18 Aug 2025 11:36:39 -0300 Subject: [PATCH 1/3] Switched to non-blocking assignments in single and dual port ram primitives --- parmys/third_party/vtr_flow/primitives.v | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/parmys/third_party/vtr_flow/primitives.v b/parmys/third_party/vtr_flow/primitives.v index 678af1ccdb1..78b23e220e6 100644 --- a/parmys/third_party/vtr_flow/primitives.v +++ b/parmys/third_party/vtr_flow/primitives.v @@ -266,9 +266,9 @@ module single_port_ram #( always@(posedge clk) begin if(we) begin - Mem[addr] = data; + Mem[addr] <= data; end - out = Mem[addr]; //New data read-during write behaviour (blocking assignments) + out <= Mem[addr]; //New data read-during write behaviour (blocking assignments) end endmodule // single_port_RAM @@ -314,16 +314,16 @@ module dual_port_ram #( always@(posedge clk) begin //Port 1 if(we1) begin - Mem[addr1] = data1; + Mem[addr1] <= data1; end - out1 = Mem[addr1]; //New data read-during write behaviour (blocking assignments) + out1 <= Mem[addr1]; //New data read-during write behaviour (blocking assignments) end always@(posedge clk) begin //Port 2 if(we2) begin - Mem[addr2] = data2; + Mem[addr2] <= data2; end - out2 = Mem[addr2]; //New data read-during write behaviour (blocking assignments) + out2 <= Mem[addr2]; //New data read-during write behaviour (blocking assignments) end endmodule // dual_port_ram From b9b8cb065519aed43351adf9553c53dbbc3a7ab9 Mon Sep 17 00:00:00 2001 From: Logan Lavigne Date: Mon, 18 Aug 2025 12:49:05 -0300 Subject: [PATCH 2/3] Switching to non-blocking assignments in other primitives file --- vtr_flow/primitives.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/vtr_flow/primitives.v b/vtr_flow/primitives.v index 678af1ccdb1..25cd547fa27 100644 --- a/vtr_flow/primitives.v +++ b/vtr_flow/primitives.v @@ -266,9 +266,9 @@ module single_port_ram #( always@(posedge clk) begin if(we) begin - Mem[addr] = data; + Mem[addr] <= data; end - out = Mem[addr]; //New data read-during write behaviour (blocking assignments) + out <= Mem[addr]; //New data read-during write behaviour (blocking assignments) end endmodule // single_port_RAM @@ -321,9 +321,9 @@ module dual_port_ram #( always@(posedge clk) begin //Port 2 if(we2) begin - Mem[addr2] = data2; + Mem[addr2] <= data2; end - out2 = Mem[addr2]; //New data read-during write behaviour (blocking assignments) + out2 <= Mem[addr2]; //New data read-during write behaviour (blocking assignments) end endmodule // dual_port_ram From f34cce0f9237c19599a195cceb4e1c0107aea3d1 Mon Sep 17 00:00:00 2001 From: Logan Lavigne Date: Mon, 18 Aug 2025 15:09:46 -0300 Subject: [PATCH 3/3] Modifying comments to reflect new changes to single and dual port ram primitives --- parmys/third_party/vtr_flow/primitives.v | 6 +++--- vtr_flow/primitives.v | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/parmys/third_party/vtr_flow/primitives.v b/parmys/third_party/vtr_flow/primitives.v index 78b23e220e6..8957aa344f1 100644 --- a/parmys/third_party/vtr_flow/primitives.v +++ b/parmys/third_party/vtr_flow/primitives.v @@ -268,7 +268,7 @@ module single_port_ram #( if(we) begin Mem[addr] <= data; end - out <= Mem[addr]; //New data read-during write behaviour (blocking assignments) + out <= Mem[addr]; //Old data read-first behaviour (non-blocking assignments) end endmodule // single_port_RAM @@ -316,14 +316,14 @@ module dual_port_ram #( if(we1) begin Mem[addr1] <= data1; end - out1 <= Mem[addr1]; //New data read-during write behaviour (blocking assignments) + out1 <= Mem[addr1]; //Old data read-first behaviour (non-blocking assignments) end always@(posedge clk) begin //Port 2 if(we2) begin Mem[addr2] <= data2; end - out2 <= Mem[addr2]; //New data read-during write behaviour (blocking assignments) + out2 <= Mem[addr2]; //Old data read-first behaviour (non-blocking assignments) end endmodule // dual_port_ram diff --git a/vtr_flow/primitives.v b/vtr_flow/primitives.v index 25cd547fa27..8957aa344f1 100644 --- a/vtr_flow/primitives.v +++ b/vtr_flow/primitives.v @@ -268,7 +268,7 @@ module single_port_ram #( if(we) begin Mem[addr] <= data; end - out <= Mem[addr]; //New data read-during write behaviour (blocking assignments) + out <= Mem[addr]; //Old data read-first behaviour (non-blocking assignments) end endmodule // single_port_RAM @@ -314,16 +314,16 @@ module dual_port_ram #( always@(posedge clk) begin //Port 1 if(we1) begin - Mem[addr1] = data1; + Mem[addr1] <= data1; end - out1 = Mem[addr1]; //New data read-during write behaviour (blocking assignments) + out1 <= Mem[addr1]; //Old data read-first behaviour (non-blocking assignments) end always@(posedge clk) begin //Port 2 if(we2) begin Mem[addr2] <= data2; end - out2 <= Mem[addr2]; //New data read-during write behaviour (blocking assignments) + out2 <= Mem[addr2]; //Old data read-first behaviour (non-blocking assignments) end endmodule // dual_port_ram