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vtr_flow/tasks/regression_tests/vtr_reg_strong
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lines changed Original file line number Diff line number Diff line change 11 arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time
2- k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 2.64 vpr 75.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 135 9 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 77064 9 19 896 28 0 660 163 16 16 256 -1 mcnc_medium -1 -1 7727.83 7087 9508 603 6937 1968 75.3 MiB 2.09 0.00 6.3343 5.39115 -88.0884 -5.39115 nan 0.00 0.00133719 0.00116801 0.0488072 0.0445052 75.3 MiB 2.09 75.3 MiB 1.41 11108 16.8558 2920 4.43096 4709 24240 778883 128039 1.05632e+07 7.27569e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.72644 nan -92.7439 -5.72644 0 0 0.13 -1 -1 75.3 MiB 0.25 0.223627 0.205422 31.2 MiB -1 0.04
2+ k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 2.64 vpr 75.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 130 9 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 77064 9 19 896 28 0 660 163 16 16 256 -1 mcnc_medium -1 -1 7727.83 7087 9508 603 6937 1968 75.3 MiB 2.09 0.00 6.3343 5.39115 -88.0884 -5.39115 nan 0.00 0.00133719 0.00116801 0.0488072 0.0445052 75.3 MiB 2.09 75.3 MiB 1.41 11108 16.8558 2920 4.43096 4709 24240 778883 128039 1.05632e+07 7.27569e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.72644 nan -92.7439 -5.72644 0 0 0.13 -1 -1 75.3 MiB 0.25 0.223627 0.205422 31.2 MiB -1 0.04
33 k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.54 vpr 76.40 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 173 256 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 78236 256 245 954 501 0 760 674 22 22 484 -1 mcnc_large -1 -1 9292.95 7827 56800 1790 18880 36130 76.4 MiB 1.08 0.01 5.23911 4.45825 -854.38 -4.45825 nan 0.00 0.00195959 0.0018456 0.0499366 0.0472422 76.4 MiB 1.08 76.4 MiB 0.81 11106 14.6132 3086 4.06053 2658 7145 291226 67335 2.15576e+07 9.32366e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.93512 nan -901.874 -4.93512 0 0 0.15 -1 -1 76.4 MiB 0.16 0.143878 0.136836 33.7 MiB -1 0.05
44 k6_frac_N10_40nm.xml seq.pre-vpr.blif common 2.76 vpr 76.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 147 41 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 78320 41 35 1006 76 0 714 223 16 16 256 -1 mcnc_medium -1 -1 9169.27 7694 8335 415 5173 2747 76.5 MiB 2.20 0.01 6.36629 5.23793 -151.219 -5.23793 nan 0.00 0.0015282 0.00132775 0.0366109 0.0336215 76.5 MiB 2.20 76.5 MiB 1.46 12142 17.0056 3244 4.54342 4212 22271 689032 117413 1.05632e+07 7.92242e+06 1.26944e+06 4958.75 16 28900 206586 -1 5.65269 nan -156.023 -5.65269 0 0 0.13 -1 -1 76.5 MiB 0.24 0.22311 0.205529 31.8 MiB -1 0.04
Original file line number Diff line number Diff line change 22 k4_n4_v7_bidir.xml styr.blif common 1.37 vpr 62.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64104 10 10 253 263 1 171 92 11 11 121 clb auto 23.5 MiB 0.04 1829.24 1329 4646 728 3820 98 62.6 MiB 0.05 0.00 8.75156 5.65828 -74.3763 -5.65828 5.65828 0.08 0.000539066 0.000438929 0.0158895 0.0133045 -1 -1 -1 -1 14 1972 27 2.43e+06 2.16e+06 -1 -1 0.65 0.146019 0.12287 3402 27531 -1 1970 16 1168 4226 219209 27455 7.33108 7.33108 -92.5065 -7.33108 0 0 -1 -1 0.01 0.07 0.02 -1 -1 0.01 0.0241699 0.0213263
33 k4_n4_v7_longline_bidir.xml styr.blif common 1.77 vpr 63.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64704 10 10 253 263 1 171 92 11 11 121 clb auto 23.6 MiB 0.04 1829.24 1305 3404 389 2964 51 63.2 MiB 0.04 0.00 5.19817 4.46893 -53.8773 -4.46893 4.46893 0.09 0.000510361 0.000414222 0.0114433 0.00959255 -1 -1 -1 -1 18 2312 35 2.43e+06 2.16e+06 -1 -1 1.02 0.19335 0.161505 3282 34431 -1 2326 21 1300 4425 297597 37882 9.34193 9.34193 -107.688 -9.34193 0 0 -1 -1 0.02 0.09 0.03 -1 -1 0.02 0.0293867 0.0256624
44 k4_n4_v7_l1_bidir.xml styr.blif common 1.82 vpr 62.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64084 10 10 253 263 1 171 92 11 11 121 clb auto 23.7 MiB 0.04 1829.24 1283 8993 1996 6843 154 62.6 MiB 0.10 0.00 11.3865 6.82489 -85.7025 -6.82489 6.82489 0.10 0.000535759 0.000437145 0.0267342 0.0222548 -1 -1 -1 -1 10 1437 37 2.43e+06 2.16e+06 -1 -1 0.95 0.1205 0.101293 4482 22551 -1 1348 24 1290 4977 336418 74151 8.81482 8.81482 -100.507 -8.81482 0 0 -1 -1 0.01 0.12 0.02 -1 -1 0.01 0.0332838 0.0290833
5- k4_n4_v7_bidir_pass_gate.xml styr.blif common 2.05 vpr 63.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64736 10 10 253 263 1 171 92 11 11 121 clb auto 23.6 MiB 0.04 1829.24 1294 4025 499 3414 112 63.2 MiB 0.05 0.00 4.50889 3.4607 -44.4554 -3.4607 3.4607 0.09 0.00054143 0.000441935 0.0136548 0.0114763 -1 -1 -1 -1 16 2079 28 2.43e+06 2.16e+06 -1 -1 1.10 0.148452 0.124941 3522 30407 -1 2152 25 1482 5545 978183 174036 26.5946 26.5946 -323.027 -26.5946 0 0 -1 -1 0.01 0.28 0.03 -1 -1 0.01 0.0329671 0.0287146
5+ k4_n4_v7_bidir_pass_gate.xml styr.blif common 2.05 vpr 63.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64736 10 10 253 263 1 171 92 11 11 121 clb auto 23.6 MiB 0.04 1829.24 1294 4025 499 3414 112 63.2 MiB 0.05 0.00 4.50889 3.4607 -44.4554 -3.4607 3.4607 0.09 0.00054143 0.000441935 0.0136548 0.0114763 -1 -1 -1 -1 16 2079 28 2.43e+06 2.16e+06 -1 -1 1.10 0.148452 0.124941 3522 30407 -1 2152 25 1482 5545 978183 174036 26.5946 26.5946 -315 -26.5946 0 0 -1 -1 0.01 0.28 0.03 -1 -1 0.01 0.0329671 0.0287146
Original file line number Diff line number Diff line change 1- arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2- timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.24 vpr 60.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3 .0 on Linux-6.8 .0-63 -generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex /vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 62116 1 4 28 32 2 10 9 4 4 16 clb auto 22.1 MiB 0.00 22 21 774 371 276 127 60.7 MiB 0.01 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.7321e -05 3.993e -05 0.00449915 0.00382008 -1 -1 -1 -1 6 20 5 72000 72000 4025.56 251.598 0.02 0.0106069 0.00872526 660 1032 -1 13 6 19 19 358 106 2.39113 2.39113 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00169671 0.00154408
3- timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.24 vpr 61.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3 .0 on Linux-6.8 .0-63 -generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex /vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 62496 1 4 28 32 2 10 9 4 4 16 clb auto 22.3 MiB 0.00 22 21 774 371 276 127 61.0 MiB 0.01 0.00 2.44626 2.44626 0 0 2.44626 0.01 5.5515e -05 4.7432e -05 0.00516991 0.0044429 -1 -1 -1 -1 6 20 5 72000 72000 4025.56 251.598 0.02 0.0115274 0.00951085 660 1032 -1 13 6 19 19 358 106 2.39113 2.39113 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00167376 0.00152137
4- timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.24 vpr 60.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3 .0 on Linux-6.8 .0-63 -generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex /vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 62372 1 4 28 32 2 10 9 4 4 16 clb auto 22.3 MiB 0.00 22 21 774 371 276 127 60.9 MiB 0.01 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.8008e -05 4.0427e -05 0.0044909 0.00380767 -1 -1 -1 -1 6 20 5 72000 72000 4025.56 251.598 0.02 0.010696 0.00880945 660 1032 -1 13 6 19 19 358 106 2.39113 2.39113 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00173292 0.00158056
1+ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2+ timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.31 vpr 59.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-14410-g2298aeccf-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4 .0 on Linux-5.4 .0-216 -generic x86_64 2025-11-20T13:15:33 qlsof01.quicklogic.com /dsoft/amohaghegh /vtr-verilog-to-routing/vtr_flow/tasks 60656 1 4 28 32 2 10 9 4 4 16 clb auto 19.6 MiB 0.01 22 21 873 428 311 134 59.2 MiB 0.01 0.00 2.44626 2.44626 0 0 2.44626 0.01 2.458e -05 1.572e -05 0.00273353 0.0018351 -1 -1 -1 -1 8 13 5 72000 72000 5593.62 349.601 0.02 0.00613828 0.00449115 672 1128 -1 13 7 21 21 407 128 2.39017 2.39017 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00116253 0.00102398
3+ timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.35 vpr 59.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-14410-g2298aeccf-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4 .0 on Linux-5.4 .0-216 -generic x86_64 2025-11-20T13:15:33 qlsof01.quicklogic.com /dsoft/amohaghegh /vtr-verilog-to-routing/vtr_flow/tasks 60716 1 4 28 32 2 10 9 4 4 16 clb auto 20.0 MiB 0.01 22 21 873 428 311 134 59.3 MiB 0.01 0.00 2.44626 2.44626 0 0 2.44626 0.01 3.2544e -05 2.1892e -05 0.00353219 0.00246357 -1 -1 -1 -1 8 13 5 72000 72000 5593.62 349.601 0.03 0.00883382 0.00661421 672 1128 -1 13 7 21 21 407 128 2.39017 2.39017 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00137061 0.00120949
4+ timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.34 vpr 59.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-14410-g2298aeccf-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4 .0 on Linux-5.4 .0-216 -generic x86_64 2025-11-20T13:15:33 qlsof01.quicklogic.com /dsoft/amohaghegh /vtr-verilog-to-routing/vtr_flow/tasks 60744 1 4 28 32 2 10 9 4 4 16 clb auto 19.9 MiB 0.01 22 21 873 428 311 134 59.3 MiB 0.01 0.00 2.44626 2.44626 0 0 2.44626 0.01 3.1359e -05 2.1167e -05 0.00343982 0.00239892 -1 -1 -1 -1 8 13 5 72000 72000 5593.62 349.601 0.03 0.00864508 0.00649589 672 1128 -1 13 7 21 21 407 128 2.39017 2.39017 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00132596 0.00114927
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