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add a chanz wire and mux to SIV cb 3d arch file
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vtr_flow/arch/multi_die/stratixiv_3d/3d_full_OPIN_inter_die_stratixiv_arch.timing.xml

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@@ -5116,6 +5116,8 @@
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-->
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<switch type="mux" name="seg4_driver" R="450" Cin="0.60e-15" Cout="4.82e-15" Tdel="59e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
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<switch type="mux" name="seg4_inter_layer_driver" R="0.0" Cin="0.0" Cout="0.0" Tdel="138.82e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
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<switch type="mux" name="segz_driver" R="450" Cin="0.60e-15" Cout="4.82e-15" Tdel="59e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
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<!-- KEM: Since the L16 wires are 4x as long as the L4s, it is not unreasonable to have the L16 drivers be at least 3x as
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powerful. -->
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<switch type="mux" name="seg16_driver" R="150" Cin="1.80e-15" Cout="14.5e-15" Tdel="87e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
@@ -5235,6 +5237,10 @@
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<!-- For the same reasons, long wires do not connect to block pins in Stratix IV -->
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<cb type="pattern">0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0</cb>
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</segment>
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<segment name="LZ" freq="0" length="1" type="unidir" Rmetal="201.7" Cmetal="18.0e-15" axis="z">
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<mux name="segz_driver"/>
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</segment>
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</segmentlist>
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<directlist>
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<!--Carry chain propogates downward between LAB blocks-->

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