ghdl_ug: cleanup

Author: umarcor

ghdl_ug/README.md

@@ -9,7 +9,7 @@ ghdl -a hello.vhd
 
 ghdl -e hello_world
 
-./hello_world.exe
+./hello_world
 ```
 
 Notes:
@@ -28,9 +28,9 @@ ghdl -a heartbeat.vhdl
 
 ghdl -e heartbeat
 
-./heartbeat.exe
+./heartbeat
 
-./heartbeat.exe --wave=wave.ghw
+./heartbeat --wave=wave.ghw
 
 gtkwave wave.ghw
 ```
@@ -50,7 +50,7 @@ ghdl -a tb_adder.vhd
 ghdl -e tb_adder
 ./tb_adder
 
-./tb_adder.exe --wave=wave.ghw
+./tb_adder --wave=wave.ghw
 gtkwave wave.ghw
 ```
 

ghdl_ug/tb_adder.vhd

@@ -1,9 +1,5 @@
-library vunit_lib;
-context vunit_lib.vunit_context;
-
 --  A testbench has no ports.
 entity tb_adder is
-  generic (runner_cfg : string);
 end tb_adder;
 
 architecture behav of tb_adder is
@@ -39,7 +35,6 @@ begin
        ('1', '1', '0', '0', '1'),
        ('1', '1', '1', '1', '1'));
   begin
-    test_runner_setup(runner, runner_cfg);
     --  Check each pattern.
     for i in patterns'range loop
       --  Set the inputs.
@@ -56,8 +51,7 @@ begin
     end loop;
     assert false report "end of test" severity note;
     --  Wait forever; this will finish the simulation.
-    --wait;
-    test_runner_cleanup(runner); -- Simulation ends here
+    wait;
   end process;
 
 end behav;

ghdl_ug/tb_adder_vunit.vhd

@@ -0,0 +1,63 @@
+library vunit_lib;
+context vunit_lib.vunit_context;
+
+--  A testbench has no ports.
+entity tb_adder is
+  generic (runner_cfg : string);
+end tb_adder;
+
+architecture behav of tb_adder is
+  --  Declaration of the component that will be instantiated.
+  component adder
+    port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
+  end component;
+
+  --  Specifies which entity is bound with the component.
+  for adder_0: adder use entity work.adder;
+  signal i0, i1, ci, s, co : bit;
+begin
+  --  Component instantiation.
+  adder_0: adder port map (i0 => i0, i1 => i1, ci => ci, s => s, co => co);
+
+  --  This process does the real job.
+  process
+    type pattern_type is record
+      --  The inputs of the adder.
+      i0, i1, ci : bit;
+      --  The expected outputs of the adder.
+      s, co : bit;
+    end record;
+    --  The patterns to apply.
+    type pattern_array is array (natural range <>) of pattern_type;
+    constant patterns : pattern_array :=
+      (('0', '0', '0', '0', '0'),
+       ('0', '0', '1', '1', '0'),
+       ('0', '1', '0', '1', '0'),
+       ('0', '1', '1', '0', '1'),
+       ('1', '0', '0', '1', '0'),
+       ('1', '0', '1', '0', '1'),
+       ('1', '1', '0', '0', '1'),
+       ('1', '1', '1', '1', '1'));
+  begin
+    test_runner_setup(runner, runner_cfg);
+    --  Check each pattern.
+    for i in patterns'range loop
+      --  Set the inputs.
+      i0 <= patterns(i).i0;
+      i1 <= patterns(i).i1;
+      ci <= patterns(i).ci;
+      --  Wait for the results.
+      wait for 1 ns;
+      --  Check the outputs.
+      assert s = patterns(i).s
+        report "bad sum value" severity error;
+      assert co = patterns(i).co
+        report "bad carry out value" severity error;
+    end loop;
+    assert false report "end of test" severity note;
+    --  Wait forever; this will finish the simulation.
+    --wait;
+    test_runner_cleanup(runner); -- Simulation ends here
+  end process;
+
+end behav;