diff --git a/scala/src/d2dadapter/AdapterSM.scala b/scala/src/uciedigital/d2dadapter/AdapterSM.scala similarity index 100% rename from scala/src/d2dadapter/AdapterSM.scala rename to scala/src/uciedigital/d2dadapter/AdapterSM.scala diff --git a/scala/src/d2dadapter/D2DAdapter.scala b/scala/src/uciedigital/d2dadapter/D2DAdapter.scala similarity index 100% rename from scala/src/d2dadapter/D2DAdapter.scala rename to scala/src/uciedigital/d2dadapter/D2DAdapter.scala diff --git a/scala/src/d2dadapter/D2DAdapterConstants.scala b/scala/src/uciedigital/d2dadapter/D2DAdapterConstants.scala similarity index 100% rename from scala/src/d2dadapter/D2DAdapterConstants.scala rename to scala/src/uciedigital/d2dadapter/D2DAdapterConstants.scala diff --git a/scala/src/d2dadapter/D2DMainbandModule.scala b/scala/src/uciedigital/d2dadapter/D2DMainbandModule.scala similarity index 100% rename from scala/src/d2dadapter/D2DMainbandModule.scala rename to scala/src/uciedigital/d2dadapter/D2DMainbandModule.scala diff --git a/scala/src/d2dadapter/D2DSidebandModule.scala b/scala/src/uciedigital/d2dadapter/D2DSidebandModule.scala similarity index 100% rename from scala/src/d2dadapter/D2DSidebandModule.scala rename to scala/src/uciedigital/d2dadapter/D2DSidebandModule.scala diff --git a/scala/src/d2dadapter/StallHandler.scala b/scala/src/uciedigital/d2dadapter/StallHandler.scala similarity index 100% rename from scala/src/d2dadapter/StallHandler.scala rename to scala/src/uciedigital/d2dadapter/StallHandler.scala diff --git a/scala/src/interfaces/FDIInterfaceBundle.scala b/scala/src/uciedigital/interfaces/FDIInterfaceBundle.scala similarity index 100% rename from scala/src/interfaces/FDIInterfaceBundle.scala rename to scala/src/uciedigital/interfaces/FDIInterfaceBundle.scala diff --git a/scala/src/interfaces/RDIInterfaceBundle.scala b/scala/src/uciedigital/interfaces/RDIInterfaceBundle.scala similarity index 100% rename from scala/src/interfaces/RDIInterfaceBundle.scala rename to scala/src/uciedigital/interfaces/RDIInterfaceBundle.scala diff --git a/scala/src/interfaces/Types.scala b/scala/src/uciedigital/interfaces/Types.scala similarity index 100% rename from scala/src/interfaces/Types.scala rename to scala/src/uciedigital/interfaces/Types.scala diff --git a/scala/src/logphy/LogicalPhy.scala b/scala/src/uciedigital/logphy/LogicalPhy.scala similarity index 100% rename from scala/src/logphy/LogicalPhy.scala rename to scala/src/uciedigital/logphy/LogicalPhy.scala diff --git a/scala/src/logphy/elab/CommonModuleElab.scala b/scala/src/uciedigital/logphy/elab/CommonModuleElab.scala similarity index 100% rename from scala/src/logphy/elab/CommonModuleElab.scala rename to scala/src/uciedigital/logphy/elab/CommonModuleElab.scala diff --git a/scala/src/logphy/elab/LinkTrainingElab.scala b/scala/src/uciedigital/logphy/elab/LinkTrainingElab.scala similarity index 100% rename from scala/src/logphy/elab/LinkTrainingElab.scala rename to scala/src/uciedigital/logphy/elab/LinkTrainingElab.scala diff --git a/scala/src/logphy/elab/RdiElab.scala b/scala/src/uciedigital/logphy/elab/RdiElab.scala similarity index 100% rename from scala/src/logphy/elab/RdiElab.scala rename to scala/src/uciedigital/logphy/elab/RdiElab.scala diff --git a/scala/src/logphy/elab/TopLevelElab.scala b/scala/src/uciedigital/logphy/elab/TopLevelElab.scala similarity index 100% rename from scala/src/logphy/elab/TopLevelElab.scala rename to scala/src/uciedigital/logphy/elab/TopLevelElab.scala diff --git a/scala/src/logphy/modules/MainbandLaneController.scala b/scala/src/uciedigital/logphy/modules/MainbandLaneController.scala similarity index 100% rename from scala/src/logphy/modules/MainbandLaneController.scala rename to scala/src/uciedigital/logphy/modules/MainbandLaneController.scala diff --git a/scala/src/logphy/modules/PatternReader.scala b/scala/src/uciedigital/logphy/modules/PatternReader.scala similarity index 100% rename from scala/src/logphy/modules/PatternReader.scala rename to scala/src/uciedigital/logphy/modules/PatternReader.scala diff --git a/scala/src/logphy/modules/PatternWriter.scala b/scala/src/uciedigital/logphy/modules/PatternWriter.scala similarity index 100% rename from scala/src/logphy/modules/PatternWriter.scala rename to scala/src/uciedigital/logphy/modules/PatternWriter.scala diff --git a/scala/src/logphy/modules/PhyControlSignalTranslator.scala b/scala/src/uciedigital/logphy/modules/PhyControlSignalTranslator.scala similarity index 100% rename from scala/src/logphy/modules/PhyControlSignalTranslator.scala rename to scala/src/uciedigital/logphy/modules/PhyControlSignalTranslator.scala diff --git a/scala/src/logphy/modules/PhyLaneTrainer.scala b/scala/src/uciedigital/logphy/modules/PhyLaneTrainer.scala similarity index 100% rename from scala/src/logphy/modules/PhyLaneTrainer.scala rename to scala/src/uciedigital/logphy/modules/PhyLaneTrainer.scala diff --git a/scala/src/logphy/modules/SidebandMessageExchanger.scala b/scala/src/uciedigital/logphy/modules/SidebandMessageExchanger.scala similarity index 100% rename from scala/src/logphy/modules/SidebandMessageExchanger.scala rename to scala/src/uciedigital/logphy/modules/SidebandMessageExchanger.scala diff --git a/scala/src/logphy/modules/UcieLFSR.scala b/scala/src/uciedigital/logphy/modules/UcieLFSR.scala similarity index 100% rename from scala/src/logphy/modules/UcieLFSR.scala rename to scala/src/uciedigital/logphy/modules/UcieLFSR.scala diff --git a/scala/src/logphy/modules/linktraining/LinkTrainingSM.scala b/scala/src/uciedigital/logphy/modules/linktraining/LinkTrainingSM.scala similarity index 100% rename from scala/src/logphy/modules/linktraining/LinkTrainingSM.scala rename to scala/src/uciedigital/logphy/modules/linktraining/LinkTrainingSM.scala diff --git a/scala/src/logphy/modules/linktraining/MBInitSM.scala b/scala/src/uciedigital/logphy/modules/linktraining/MBInitSM.scala similarity index 100% rename from scala/src/logphy/modules/linktraining/MBInitSM.scala rename to scala/src/uciedigital/logphy/modules/linktraining/MBInitSM.scala diff --git a/scala/src/logphy/modules/linktraining/MBTrainSM.scala b/scala/src/uciedigital/logphy/modules/linktraining/MBTrainSM.scala similarity index 100% rename from scala/src/logphy/modules/linktraining/MBTrainSM.scala rename to scala/src/uciedigital/logphy/modules/linktraining/MBTrainSM.scala diff --git a/scala/src/logphy/modules/linktraining/PhyRetrainSidebandHandshake.scala b/scala/src/uciedigital/logphy/modules/linktraining/PhyRetrainSidebandHandshake.scala similarity index 100% rename from scala/src/logphy/modules/linktraining/PhyRetrainSidebandHandshake.scala rename to scala/src/uciedigital/logphy/modules/linktraining/PhyRetrainSidebandHandshake.scala diff --git a/scala/src/logphy/modules/linktraining/RxD2CEyeWidthSweep.scala b/scala/src/uciedigital/logphy/modules/linktraining/RxD2CEyeWidthSweep.scala similarity index 100% rename from scala/src/logphy/modules/linktraining/RxD2CEyeWidthSweep.scala rename to scala/src/uciedigital/logphy/modules/linktraining/RxD2CEyeWidthSweep.scala diff --git a/scala/src/logphy/modules/linktraining/RxD2CPointTest.scala b/scala/src/uciedigital/logphy/modules/linktraining/RxD2CPointTest.scala similarity index 100% rename from scala/src/logphy/modules/linktraining/RxD2CPointTest.scala rename to scala/src/uciedigital/logphy/modules/linktraining/RxD2CPointTest.scala diff --git a/scala/src/logphy/modules/linktraining/SBInit.scala b/scala/src/uciedigital/logphy/modules/linktraining/SBInit.scala similarity index 100% rename from scala/src/logphy/modules/linktraining/SBInit.scala rename to scala/src/uciedigital/logphy/modules/linktraining/SBInit.scala diff --git a/scala/src/logphy/modules/linktraining/TrainError.scala b/scala/src/uciedigital/logphy/modules/linktraining/TrainError.scala similarity index 100% rename from scala/src/logphy/modules/linktraining/TrainError.scala rename to scala/src/uciedigital/logphy/modules/linktraining/TrainError.scala diff --git a/scala/src/logphy/modules/linktraining/TxD2CEyeWidthSweep.scala b/scala/src/uciedigital/logphy/modules/linktraining/TxD2CEyeWidthSweep.scala similarity index 100% rename from scala/src/logphy/modules/linktraining/TxD2CEyeWidthSweep.scala rename to scala/src/uciedigital/logphy/modules/linktraining/TxD2CEyeWidthSweep.scala diff --git a/scala/src/logphy/modules/linktraining/TxD2CPointTest.scala b/scala/src/uciedigital/logphy/modules/linktraining/TxD2CPointTest.scala similarity index 100% rename from scala/src/logphy/modules/linktraining/TxD2CPointTest.scala rename to scala/src/uciedigital/logphy/modules/linktraining/TxD2CPointTest.scala diff --git a/scala/src/logphy/modules/rdi/RDIClockHandshakeRequester.scala b/scala/src/uciedigital/logphy/modules/rdi/RDIClockHandshakeRequester.scala similarity index 100% rename from scala/src/logphy/modules/rdi/RDIClockHandshakeRequester.scala rename to scala/src/uciedigital/logphy/modules/rdi/RDIClockHandshakeRequester.scala diff --git a/scala/src/logphy/modules/rdi/RDIController.scala b/scala/src/uciedigital/logphy/modules/rdi/RDIController.scala similarity index 100% rename from scala/src/logphy/modules/rdi/RDIController.scala rename to scala/src/uciedigital/logphy/modules/rdi/RDIController.scala diff --git a/scala/src/logphy/modules/rdi/RDIStallRequester.scala b/scala/src/uciedigital/logphy/modules/rdi/RDIStallRequester.scala similarity index 100% rename from scala/src/logphy/modules/rdi/RDIStallRequester.scala rename to scala/src/uciedigital/logphy/modules/rdi/RDIStallRequester.scala diff --git a/scala/src/logphy/modules/rdi/RDIStateMachine.scala b/scala/src/uciedigital/logphy/modules/rdi/RDIStateMachine.scala similarity index 100% rename from scala/src/logphy/modules/rdi/RDIStateMachine.scala rename to scala/src/uciedigital/logphy/modules/rdi/RDIStateMachine.scala diff --git a/scala/src/logphy/modules/rdi/RDIWakeHandshakeResponder.scala b/scala/src/uciedigital/logphy/modules/rdi/RDIWakeHandshakeResponder.scala similarity index 100% rename from scala/src/logphy/modules/rdi/RDIWakeHandshakeResponder.scala rename to scala/src/uciedigital/logphy/modules/rdi/RDIWakeHandshakeResponder.scala diff --git a/scala/src/logphy/utils/Bundles.scala b/scala/src/uciedigital/logphy/utils/Bundles.scala similarity index 100% rename from scala/src/logphy/utils/Bundles.scala rename to scala/src/uciedigital/logphy/utils/Bundles.scala diff --git a/scala/src/logphy/utils/PatternLaneMap.scala b/scala/src/uciedigital/logphy/utils/PatternLaneMap.scala similarity index 100% rename from scala/src/logphy/utils/PatternLaneMap.scala rename to scala/src/uciedigital/logphy/utils/PatternLaneMap.scala diff --git a/scala/src/logphy/utils/PatternTypes.scala b/scala/src/uciedigital/logphy/utils/PatternTypes.scala similarity index 100% rename from scala/src/logphy/utils/PatternTypes.scala rename to scala/src/uciedigital/logphy/utils/PatternTypes.scala diff --git a/scala/src/logphy/utils/TrainingTypes.scala b/scala/src/uciedigital/logphy/utils/TrainingTypes.scala similarity index 100% rename from scala/src/logphy/utils/TrainingTypes.scala rename to scala/src/uciedigital/logphy/utils/TrainingTypes.scala diff --git a/scala/src/logphy/utils/Types.scala b/scala/src/uciedigital/logphy/utils/Types.scala similarity index 100% rename from scala/src/logphy/utils/Types.scala rename to scala/src/uciedigital/logphy/utils/Types.scala diff --git a/scala/src/protocol/ProtocolLayer.scala b/scala/src/uciedigital/protocol/ProtocolLayer.scala similarity index 100% rename from scala/src/protocol/ProtocolLayer.scala rename to scala/src/uciedigital/protocol/ProtocolLayer.scala diff --git a/scala/src/protocol/ProtocolMainbandRx.scala b/scala/src/uciedigital/protocol/ProtocolMainbandRx.scala similarity index 100% rename from scala/src/protocol/ProtocolMainbandRx.scala rename to scala/src/uciedigital/protocol/ProtocolMainbandRx.scala diff --git a/scala/src/protocol/ProtocolMainbandTx.scala b/scala/src/uciedigital/protocol/ProtocolMainbandTx.scala similarity index 100% rename from scala/src/protocol/ProtocolMainbandTx.scala rename to scala/src/uciedigital/protocol/ProtocolMainbandTx.scala diff --git a/scala/src/protocol/ProtocolStateController.scala b/scala/src/uciedigital/protocol/ProtocolStateController.scala similarity index 100% rename from scala/src/protocol/ProtocolStateController.scala rename to scala/src/uciedigital/protocol/ProtocolStateController.scala diff --git a/scala/src/protocol/ProtocolTypes.scala b/scala/src/uciedigital/protocol/ProtocolTypes.scala similarity index 100% rename from scala/src/protocol/ProtocolTypes.scala rename to scala/src/uciedigital/protocol/ProtocolTypes.scala diff --git a/scala/src/sideband/D2DSidebandChannel.scala b/scala/src/uciedigital/sideband/D2DSidebandChannel.scala similarity index 100% rename from scala/src/sideband/D2DSidebandChannel.scala rename to scala/src/uciedigital/sideband/D2DSidebandChannel.scala diff --git a/scala/src/sideband/LogPhySidebandChannel.scala b/scala/src/uciedigital/sideband/LogPhySidebandChannel.scala similarity index 100% rename from scala/src/sideband/LogPhySidebandChannel.scala rename to scala/src/uciedigital/sideband/LogPhySidebandChannel.scala diff --git a/scala/src/sideband/ProtocolSidebandChannel.scala b/scala/src/uciedigital/sideband/ProtocolSidebandChannel.scala similarity index 100% rename from scala/src/sideband/ProtocolSidebandChannel.scala rename to scala/src/uciedigital/sideband/ProtocolSidebandChannel.scala diff --git a/scala/src/sideband/modules/SidebandInterfaceNode.scala b/scala/src/uciedigital/sideband/modules/SidebandInterfaceNode.scala similarity index 100% rename from scala/src/sideband/modules/SidebandInterfaceNode.scala rename to scala/src/uciedigital/sideband/modules/SidebandInterfaceNode.scala diff --git a/scala/src/sideband/modules/SidebandInterfaceSerdes.scala b/scala/src/uciedigital/sideband/modules/SidebandInterfaceSerdes.scala similarity index 100% rename from scala/src/sideband/modules/SidebandInterfaceSerdes.scala rename to scala/src/uciedigital/sideband/modules/SidebandInterfaceSerdes.scala diff --git a/scala/src/sideband/modules/SidebandLinkNode.scala b/scala/src/uciedigital/sideband/modules/SidebandLinkNode.scala similarity index 100% rename from scala/src/sideband/modules/SidebandLinkNode.scala rename to scala/src/uciedigital/sideband/modules/SidebandLinkNode.scala diff --git a/scala/src/sideband/modules/SidebandLinkSerdes.scala b/scala/src/uciedigital/sideband/modules/SidebandLinkSerdes.scala similarity index 100% rename from scala/src/sideband/modules/SidebandLinkSerdes.scala rename to scala/src/uciedigital/sideband/modules/SidebandLinkSerdes.scala diff --git a/scala/src/sideband/modules/SidebandPriorityQueue.scala b/scala/src/uciedigital/sideband/modules/SidebandPriorityQueue.scala similarity index 100% rename from scala/src/sideband/modules/SidebandPriorityQueue.scala rename to scala/src/uciedigital/sideband/modules/SidebandPriorityQueue.scala diff --git a/scala/src/sideband/modules/SidebandSwitch.scala b/scala/src/uciedigital/sideband/modules/SidebandSwitch.scala similarity index 100% rename from scala/src/sideband/modules/SidebandSwitch.scala rename to scala/src/uciedigital/sideband/modules/SidebandSwitch.scala diff --git a/scala/src/sideband/utils/SidebandClasses.scala b/scala/src/uciedigital/sideband/utils/SidebandClasses.scala similarity index 100% rename from scala/src/sideband/utils/SidebandClasses.scala rename to scala/src/uciedigital/sideband/utils/SidebandClasses.scala diff --git a/scala/src/sideband/utils/SidebandMessageEncodings.scala b/scala/src/uciedigital/sideband/utils/SidebandMessageEncodings.scala similarity index 100% rename from scala/src/sideband/utils/SidebandMessageEncodings.scala rename to scala/src/uciedigital/sideband/utils/SidebandMessageEncodings.scala diff --git a/scala/src/sideband/utils/SidebandTypes.scala b/scala/src/uciedigital/sideband/utils/SidebandTypes.scala similarity index 100% rename from scala/src/sideband/utils/SidebandTypes.scala rename to scala/src/uciedigital/sideband/utils/SidebandTypes.scala diff --git a/scala/src/top/UcieTop.scala b/scala/src/uciedigital/top/UcieDigitalTop.scala similarity index 80% rename from scala/src/top/UcieTop.scala rename to scala/src/uciedigital/top/UcieDigitalTop.scala index 4113fe3b..02532076 100644 --- a/scala/src/top/UcieTop.scala +++ b/scala/src/uciedigital/top/UcieDigitalTop.scala @@ -1,9 +1,9 @@ /* Description: - UcieTop is the integration wrapper that wires together the protocol layer, + UcieDigitalTop is the integration wrapper that wires together the protocol layer, die-to-die adapter, and logical PHY into a single top-level module. - The main interface parameters live in UcieTopParams. In general: + The main interface parameters live in UcieDigitalTopParams. In general: - FDI/RDI/sideband width parameters define the top-level interface shape. - LogicalPhyTopParams contains the primary tuning knobs for bring-up and training experiments, such as retry width and sideband timeout depth. @@ -17,15 +17,15 @@ import edu.berkeley.cs.uciedigital.interfaces._ import edu.berkeley.cs.uciedigital.logphy._ import edu.berkeley.cs.uciedigital.protocol._ -class UcieTopProtocolIO(protocolParams: ProtocolTopParams) extends Bundle { +class UcieDigitalTopProtocolIO(protocolParams: ProtocolTopParams) extends Bundle { val ctrl = new ProtocolLayerCtrlIO() val status = new ProtocolLayerStatusIO() val mainbandTx = Flipped(Decoupled(new ProtocolRawBeat(protocolParams.fdi.nBytes))) val mainbandRx = Decoupled(new ProtocolRawBeat(protocolParams.fdi.nBytes)) } -class UcieTopIO(params: UcieTopParams) extends Bundle { - val protocol = new UcieTopProtocolIO(params.protocol) +class UcieDigitalTopIO(params: UcieDigitalTopParams) extends Bundle { + val protocol = new UcieDigitalTopProtocolIO(params.protocol) val logPhy = new Bundle { val ctrl = new LogicalPhyCtrlIO(params.logPhy.retryW) val status = new LogicalPhyStatusIO() @@ -33,10 +33,10 @@ class UcieTopIO(params: UcieTopParams) extends Bundle { val analog = new LogicalPhyAnalogIO(params.logPhy.afe, params.logPhy.sideband) } -class UcieTop(params: UcieTopParams = UcieTopParams.default()) extends Module { +class UcieDigitalTop(params: UcieDigitalTopParams = UcieDigitalTopParams.default()) extends Module { private val validatedParams = params.validate() - val io = IO(new UcieTopIO(validatedParams)) + val io = IO(new UcieDigitalTopIO(validatedParams)) val protocolLayer = Module(new ProtocolLayer( params = validatedParams.protocol.layer, diff --git a/scala/src/top/UcieTopElab.scala b/scala/src/uciedigital/top/UcieDigitalTopElab.scala similarity index 82% rename from scala/src/top/UcieTopElab.scala rename to scala/src/uciedigital/top/UcieDigitalTopElab.scala index c24133bd..84bb3d8d 100644 --- a/scala/src/top/UcieTopElab.scala +++ b/scala/src/uciedigital/top/UcieDigitalTopElab.scala @@ -2,7 +2,7 @@ package edu.berkeley.cs.uciedigital.top import circt.stage.ChiselStage -object UcieTopElab { +object UcieDigitalTopElab { private val commonFirtoolOpts = Array( "--disable-all-randomization" ) @@ -37,17 +37,17 @@ object UcieTopElab { } ChiselStage.emitSystemVerilogFile( - new UcieTop(), + new UcieDigitalTop(), args = Array("-td", targetDir), firtoolOpts = firtoolOpts, ) } } -object MainUcieTopDebug extends App { - UcieTopElab.emit("./generatedVerilog/top-debug", debug = true) +object MainUcieDigitalTopDebug extends App { + UcieDigitalTopElab.emit("./generatedVerilog/top-debug", debug = true) } object MainUcieTop extends App { - UcieTopElab.emit("./generatedVerilog/top", debug = false) + UcieDigitalTopElab.emit("./generatedVerilog/top", debug = false) } diff --git a/scala/src/top/UcieTopParams.scala b/scala/src/uciedigital/top/UcieDigitalTopParams.scala similarity index 92% rename from scala/src/top/UcieTopParams.scala rename to scala/src/uciedigital/top/UcieDigitalTopParams.scala index 371f1216..36798979 100644 --- a/scala/src/top/UcieTopParams.scala +++ b/scala/src/uciedigital/top/UcieDigitalTopParams.scala @@ -35,12 +35,12 @@ case class LogicalPhyTopParams( queueDepths: SidebandPriorityQueueDepths = SidebandPriorityQueueDepths(), ) -case class UcieTopParams( +case class UcieDigitalTopParams( protocol: ProtocolTopParams, adapter: AdapterTopParams, logPhy: LogicalPhyTopParams, ) { - def validate(): UcieTopParams = { + def validate(): UcieDigitalTopParams = { require( protocol.fdi == adapter.fdi, s"Protocol FDI params ${protocol.fdi} must match adapter FDI params ${adapter.fdi}" @@ -57,12 +57,12 @@ case class UcieTopParams( } } -object UcieTopParams { - def default(): UcieTopParams = { +object UcieDigitalTopParams { + def default(): UcieDigitalTopParams = { val explicitFdi = FdiParams(nBytes = 64, ncWidth = 32) val explicitRdi = RdiParams(nBytes = 64, ncWidth = 32) - UcieTopParams( + UcieDigitalTopParams( protocol = ProtocolTopParams(fdi = explicitFdi), adapter = AdapterTopParams(fdi = explicitFdi, rdi = explicitRdi), logPhy = LogicalPhyTopParams(rdi = explicitRdi) @@ -79,8 +79,8 @@ object UcieTopParams { retryW: Int = 10, desTimeoutCycles: Int = 512, queueDepths: SidebandPriorityQueueDepths = SidebandPriorityQueueDepths(), - ): UcieTopParams = { - UcieTopParams( + ): UcieDigitalTopParams = { + UcieDigitalTopParams( protocol = ProtocolTopParams( fdi = fdi, layer = protocolLayer diff --git a/scala/src/utils/CircularShiftRegister.scala b/scala/src/uciedigital/utils/CircularShiftRegister.scala similarity index 100% rename from scala/src/utils/CircularShiftRegister.scala rename to scala/src/uciedigital/utils/CircularShiftRegister.scala diff --git a/scala/src/utils/ParallelGaloisLFSR.scala b/scala/src/uciedigital/utils/ParallelGaloisLFSR.scala similarity index 100% rename from scala/src/utils/ParallelGaloisLFSR.scala rename to scala/src/uciedigital/utils/ParallelGaloisLFSR.scala diff --git a/scala/src/utils/README.md b/scala/src/uciedigital/utils/README.md similarity index 100% rename from scala/src/utils/README.md rename to scala/src/uciedigital/utils/README.md diff --git a/scala/src/utils/Ser21.scala b/scala/src/uciedigital/utils/Ser21.scala similarity index 100% rename from scala/src/utils/Ser21.scala rename to scala/src/uciedigital/utils/Ser21.scala diff --git a/scala/src/utils/SkidBuffer.scala b/scala/src/uciedigital/utils/SkidBuffer.scala similarity index 100% rename from scala/src/utils/SkidBuffer.scala rename to scala/src/uciedigital/utils/SkidBuffer.scala diff --git a/scala/test/src/logphy/LinkTrainingSMTest.scala b/scala/test/src/uciedigital/logphy/LinkTrainingSMTest.scala similarity index 100% rename from scala/test/src/logphy/LinkTrainingSMTest.scala rename to scala/test/src/uciedigital/logphy/LinkTrainingSMTest.scala diff --git a/scala/test/src/uciedigital/logphy/MBInitSMTest.scala b/scala/test/src/uciedigital/logphy/MBInitSMTest.scala new file mode 100644 index 00000000..c3641e74 --- /dev/null +++ b/scala/test/src/uciedigital/logphy/MBInitSMTest.scala @@ -0,0 +1,183 @@ +package edu.berkeley.cs.uciedigital.logphy + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import chisel3.util._ +import edu.berkeley.cs.uciedigital.interfaces._ +import edu.berkeley.cs.uciedigital.sideband._ +import org.scalatest.funspec.AnyFunSpec + +class MBInitLoopbackHarness( + afeParams: AfeParams = new AfeParams(), + sbParams: SidebandParams = new SidebandParams() +) extends Module { + val io = IO(new Bundle { + val start = Input(Bool()) + val selfCalDone = Input(Bool()) + + val currentState = Output(MBInitState()) + val done = Output(Bool()) + val error = Output(Bool()) + val interoperableParamsNotFound = Output(Bool()) + }) + + val dut = Module(new MBInitSM(afeParams, sbParams)) + val txPtReq = Module(new TxD2CPointTestRequester(afeParams, sbParams)) + val txPtResp = Module(new TxD2CPointTestResponder(afeParams, sbParams)) + val patternWriter = Module(new PatternWriter(afeParams)) + val patternReader = Module(new PatternReader(afeParams)) + val scrambler = Module(new UcieLFSR(afeParams)) + val descrambler = Module(new UcieLFSR(afeParams)) + val rxQueue = Module(new Queue(UInt(sbParams.sbNodeMsgWidth.W), sbParams.sbLinkAsyncQueueDepth)) + + dut.io.fsmCtrl.start := io.start + dut.io.mbInitCalDone := io.selfCalDone + + dut.io.localPhySettings.valid := true.B + dut.io.localPhySettings.bits.moduleId := 0.U + dut.io.localPhySettings.bits.voltageSwing := 0.U + dut.io.localPhySettings.bits.maxDataRate := SpeedMode.speed16.asUInt + dut.io.localPhySettings.bits.clockMode := 0.U + dut.io.localPhySettings.bits.clockPhase := 0.U + dut.io.localPhySettings.bits.ucieSx8 := 0.U + dut.io.localPhySettings.bits.sbFeatExt := 0.U + dut.io.localPhySettings.bits.txAdjRuntime := 0.U + + txPtReq.io.start := dut.io.txPtTestReqInterfaceIo.start + txPtReq.io.patternType := dut.io.txPtTestReqInterfaceIo.patternType + txPtReq.io.linkTrainingParameters := dut.io.txPtTestReqInterfaceIo.linkTrainingParameters + dut.io.txPtTestReqInterfaceIo.done := txPtReq.io.done + dut.io.txPtTestReqInterfaceIo.ptTestResults := txPtReq.io.txInitPtTestResults + + txPtResp.io.start := dut.io.txPtTestRespInterfaceIo.start + txPtResp.io.patternType := dut.io.txPtTestRespInterfaceIo.patternType + dut.io.txPtTestRespInterfaceIo.done := txPtResp.io.done + + val txClients = Seq( + dut.io.requesterSbLaneIo.tx, + dut.io.responderSbLaneIo.tx, + txPtReq.io.sbLaneIo.tx, + txPtResp.io.sbLaneIo.tx + ) + val chosen = PriorityEncoderOH(VecInit(txClients.map(_.valid))) + val anyTxValid = txClients.map(_.valid).reduce(_ || _) + + rxQueue.io.enq.valid := anyTxValid + rxQueue.io.enq.bits := Mux1H(chosen, txClients.map(_.bits.data)) + txClients.zipWithIndex.foreach { case (client, idx) => + client.ready := rxQueue.io.enq.ready && chosen(idx) + } + + val rxClients = Seq( + dut.io.requesterSbLaneIo.rx, + dut.io.responderSbLaneIo.rx, + txPtReq.io.sbLaneIo.rx, + txPtResp.io.sbLaneIo.rx + ) + rxClients.foreach { client => + client.valid := rxQueue.io.deq.valid + client.bits.data := rxQueue.io.deq.bits + } + rxQueue.io.deq.ready := rxClients.map(_.ready).reduce(_ || _) + + val writerClients = Seq( + (dut.io.usingPatternWriter, dut.io.patternWriterIo), + (txPtReq.io.usingPatternWriter, txPtReq.io.patternWriterIo) + ) + val readerClients = Seq( + (dut.io.usingPatternReader, dut.io.patternReaderIo), + (txPtResp.io.usingPatternReader, txPtResp.io.patternReaderIo) + ) + + patternWriter.io.interfaceIo.req.valid := false.B + patternWriter.io.interfaceIo.req.bits := DontCare + patternWriter.io.interfaceIo.functionalLanes := "b011".U + writerClients.foreach { case (active, clientIo) => + clientIo.resp := patternWriter.io.interfaceIo.resp + clientIo.req.ready := false.B + when(active) { + patternWriter.io.interfaceIo.req.valid := clientIo.req.valid + patternWriter.io.interfaceIo.req.bits := clientIo.req.bits + patternWriter.io.interfaceIo.functionalLanes := clientIo.functionalLanes + clientIo.req.ready := patternWriter.io.interfaceIo.req.ready + } + } + + patternReader.io.interfaceIo.req.valid := false.B + patternReader.io.interfaceIo.req.bits := DontCare + patternReader.io.interfaceIo.functionalLanes := "b011".U + readerClients.foreach { case (active, clientIo) => + clientIo.resp := patternReader.io.interfaceIo.resp + clientIo.req.ready := false.B + when(active) { + patternReader.io.interfaceIo.req.valid := clientIo.req.valid + patternReader.io.interfaceIo.req.bits := clientIo.req.bits + patternReader.io.interfaceIo.functionalLanes := clientIo.functionalLanes + clientIo.req.ready := patternReader.io.interfaceIo.req.ready + } + } + + patternWriter.io.txLfsrCtrl.pattern := scrambler.io.lfsrOutput + patternReader.io.rxLfsrCtrl.pattern := descrambler.io.lfsrOutput + + scrambler.io.increment := VecInit(Seq.fill(afeParams.mbLanes)(patternWriter.io.txLfsrCtrl.increment)) + scrambler.io.resetLfsr := VecInit(Seq.fill(afeParams.mbLanes)(patternWriter.io.txLfsrCtrl.resetLfsr)) + + descrambler.io.increment := VecInit(Seq.fill(afeParams.mbLanes)(patternReader.io.rxLfsrCtrl.increment)) + descrambler.io.resetLfsr := VecInit(Seq.fill(afeParams.mbLanes)(patternReader.io.rxLfsrCtrl.resetLfsr)) + + val zeroMainband = 0.U.asTypeOf(chiselTypeOf(patternReader.io.mbRxLaneIo)) + patternReader.io.mbRxLaneIo := Mux(patternWriter.io.mbTxLaneIo.valid, patternWriter.io.mbTxLaneIo.bits, zeroMainband) + + io.currentState := dut.io.currentState + io.done := dut.io.fsmCtrl.done + io.error := dut.io.fsmCtrl.error + io.interoperableParamsNotFound := dut.io.interoperableParamsNotFound +} + +class MBInitSMTest extends AnyFunSpec with ChiselSim { + describe("MBInitSM") { + it("runs the supported loopback flow with the real pattern engines attached") { + simulate(new MBInitLoopbackHarness()) { dut => + dut.io.start.poke(false.B) + dut.io.selfCalDone.poke(false.B) + dut.clock.step(2) + + dut.io.start.poke(true.B) + + var seenStates = Set.empty[BigInt] + var selfCalIssued = false + var cycles = 0 + while (!dut.io.done.peekBoolean() && !dut.io.error.peekBoolean() && cycles < 30000) { + seenStates += dut.io.currentState.peek().litValue + + if (!selfCalIssued && dut.io.currentState.peek().litValue == MBInitState.sCAL.litValue) { + dut.io.selfCalDone.poke(true.B) + selfCalIssued = true + } else { + dut.io.selfCalDone.poke(false.B) + } + + dut.clock.step() + cycles += 1 + } + + assert( + dut.io.done.peekBoolean() || dut.io.error.peekBoolean(), + s"MBINIT made no forward progress within $cycles cycles" + ) + + Seq( + MBInitState.sPARAM, + MBInitState.sCAL, + MBInitState.sREPAIRCLK, + MBInitState.sREPAIRVAL, + MBInitState.sREVERSALMB, + MBInitState.sREPAIRMB + ).foreach { state => + assert(seenStates.contains(state.litValue), s"Expected to visit $state, saw $seenStates") + } + } + } + } +} diff --git a/scala/test/src/uciedigital/logphy/MBTrainSMTest.scala b/scala/test/src/uciedigital/logphy/MBTrainSMTest.scala new file mode 100644 index 00000000..5979ca8d --- /dev/null +++ b/scala/test/src/uciedigital/logphy/MBTrainSMTest.scala @@ -0,0 +1,238 @@ +package edu.berkeley.cs.uciedigital.logphy + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import chisel3.util._ +import edu.berkeley.cs.uciedigital.interfaces._ +import edu.berkeley.cs.uciedigital.sideband._ +import org.scalatest.funspec.AnyFunSpec + +class MBTrainLoopbackHarness( + afeParams: AfeParams = new AfeParams(), + sbParams: SidebandParams = new SidebandParams() +) extends Module { + val io = IO(new Bundle { + val start = Input(Bool()) + val pllLock = Input(Bool()) + val autoRunLinkOps = Input(Bool()) + val autoCompleteSelfCal = Input(Bool()) + + val currentState = Output(MBTrainState()) + val done = Output(Bool()) + val error = Output(Bool()) + }) + + val dut = Module(new MBTrainSM(afeParams, sbParams)) + val txPtReq = Module(new TxD2CPointTestRequester(afeParams, sbParams)) + val txPtResp = Module(new TxD2CPointTestResponder(afeParams, sbParams)) + val rxPtReq = Module(new RxD2CPointTestRequester(afeParams, sbParams)) + val rxPtResp = Module(new RxD2CPointTestResponder(afeParams, sbParams)) + val patternWriter = Module(new PatternWriter(afeParams)) + val patternReader = Module(new PatternReader(afeParams)) + val scrambler = Module(new UcieLFSR(afeParams)) + val descrambler = Module(new UcieLFSR(afeParams)) + val rxQueue = Module(new Queue(UInt(sbParams.sbNodeMsgWidth.W), sbParams.sbLinkAsyncQueueDepth)) + + dut.io.fsmCtrl.start := io.start + dut.io.goToState.valid := false.B + dut.io.goToState.bits := MBTrainGoToState.goToSPEEDIDLE + dut.io.negotiatedMaxDataRate := SpeedMode.speed16 + dut.io.pllLock := io.pllLock + dut.io.phyInRetrain := false.B + dut.io.interpretBy8Lane := false.B + dut.io.maxErrorThresholdPerLane := 0.U + dut.io.changeInRuntimeLinkCtrlRegs := false.B + dut.io.currLocalTxFunctionalLanes := "b011".U + dut.io.currRemoteTxFunctionalLanes := "b011".U + + dut.io.txEyeSweepReqIntfIo.done := false.B + dut.io.txEyeSweepReqIntfIo.eyeSweepTestResults.valid := false.B + dut.io.txEyeSweepReqIntfIo.eyeSweepTestResults.bits := 0.U.asTypeOf(dut.io.txEyeSweepReqIntfIo.eyeSweepTestResults.bits) + dut.io.txEyeSweepRespIntfIo.done := false.B + + dut.io.rxEyeSweepReqIntfIo.done := false.B + dut.io.rxEyeSweepReqIntfIo.eyeSweepTestResults.valid := false.B + dut.io.rxEyeSweepReqIntfIo.eyeSweepTestResults.bits := 0.U.asTypeOf(dut.io.rxEyeSweepReqIntfIo.eyeSweepTestResults.bits) + dut.io.rxEyeSweepRespIntfIo.done := false.B + dut.io.rxEyeSweepRespIntfIo.remoteEyeSweepTestResults.valid := false.B + dut.io.rxEyeSweepRespIntfIo.remoteEyeSweepTestResults.bits := 0.U.asTypeOf(dut.io.rxEyeSweepRespIntfIo.remoteEyeSweepTestResults.bits) + + txPtReq.io.start := dut.io.txPtTestReqIntfIo.start + txPtReq.io.patternType := dut.io.txPtTestReqIntfIo.patternType + txPtReq.io.linkTrainingParameters := dut.io.txPtTestReqIntfIo.linkTrainingParameters + dut.io.txPtTestReqIntfIo.done := txPtReq.io.done + dut.io.txPtTestReqIntfIo.ptTestResults := txPtReq.io.txInitPtTestResults + + txPtResp.io.start := dut.io.txPtTestRespIntfIo.start + txPtResp.io.patternType := dut.io.txPtTestRespIntfIo.patternType + dut.io.txPtTestRespIntfIo.done := txPtResp.io.done + + rxPtReq.io.start := dut.io.rxPtTestReqIntfIo.start + rxPtReq.io.patternType := dut.io.rxPtTestReqIntfIo.patternType + rxPtReq.io.linkTrainingParameters := dut.io.rxPtTestReqIntfIo.linkTrainingParameters + dut.io.rxPtTestReqIntfIo.done := rxPtReq.io.done + dut.io.rxPtTestReqIntfIo.ptTestResults := rxPtReq.io.rxInitPtTestLocalResults + + rxPtResp.io.start := dut.io.rxPtTestRespIntfIo.start + rxPtResp.io.patternType := dut.io.rxPtTestRespIntfIo.patternType + dut.io.rxPtTestRespIntfIo.done := rxPtResp.io.done + + val txClients = Seq( + dut.io.requesterSbLaneIo.tx, + dut.io.responderSbLaneIo.tx, + txPtReq.io.sbLaneIo.tx, + txPtResp.io.sbLaneIo.tx, + rxPtReq.io.sbLaneIo.tx, + rxPtResp.io.sbLaneIo.tx + ) + val chosen = PriorityEncoderOH(VecInit(txClients.map(_.valid))) + val anyTxValid = txClients.map(_.valid).reduce(_ || _) + + rxQueue.io.enq.valid := anyTxValid + rxQueue.io.enq.bits := Mux1H(chosen, txClients.map(_.bits.data)) + txClients.zipWithIndex.foreach { case (client, idx) => + client.ready := rxQueue.io.enq.ready && chosen(idx) + } + + val rxClients = Seq( + dut.io.requesterSbLaneIo.rx, + dut.io.responderSbLaneIo.rx, + txPtReq.io.sbLaneIo.rx, + txPtResp.io.sbLaneIo.rx, + rxPtReq.io.sbLaneIo.rx, + rxPtResp.io.sbLaneIo.rx + ) + rxClients.foreach { client => + client.valid := rxQueue.io.deq.valid + client.bits.data := rxQueue.io.deq.bits + } + rxQueue.io.deq.ready := rxClients.map(_.ready).reduce(_ || _) + + val writerClients = Seq( + (txPtReq.io.usingPatternWriter, txPtReq.io.patternWriterIo), + (rxPtResp.io.usingPatternWriter, rxPtResp.io.patternWriterIo) + ) + val readerClients = Seq( + (txPtResp.io.usingPatternReader, txPtResp.io.patternReaderIo), + (rxPtReq.io.usingPatternReader, rxPtReq.io.patternReaderIo) + ) + + patternWriter.io.interfaceIo.req.valid := false.B + patternWriter.io.interfaceIo.req.bits := DontCare + patternWriter.io.interfaceIo.functionalLanes := "b011".U + writerClients.foreach { case (active, clientIo) => + clientIo.resp := patternWriter.io.interfaceIo.resp + clientIo.req.ready := false.B + when(active) { + patternWriter.io.interfaceIo.req.valid := clientIo.req.valid + patternWriter.io.interfaceIo.req.bits := clientIo.req.bits + patternWriter.io.interfaceIo.functionalLanes := clientIo.functionalLanes + clientIo.req.ready := patternWriter.io.interfaceIo.req.ready + } + } + + patternReader.io.interfaceIo.req.valid := false.B + patternReader.io.interfaceIo.req.bits := DontCare + patternReader.io.interfaceIo.functionalLanes := "b011".U + readerClients.foreach { case (active, clientIo) => + clientIo.resp := patternReader.io.interfaceIo.resp + clientIo.req.ready := false.B + when(active) { + patternReader.io.interfaceIo.req.valid := clientIo.req.valid + patternReader.io.interfaceIo.req.bits := clientIo.req.bits + patternReader.io.interfaceIo.functionalLanes := clientIo.functionalLanes + clientIo.req.ready := patternReader.io.interfaceIo.req.ready + } + } + + patternWriter.io.txLfsrCtrl.pattern := scrambler.io.lfsrOutput + patternReader.io.rxLfsrCtrl.pattern := descrambler.io.lfsrOutput + + scrambler.io.increment := VecInit(Seq.fill(afeParams.mbLanes)(patternWriter.io.txLfsrCtrl.increment)) + scrambler.io.resetLfsr := VecInit(Seq.fill(afeParams.mbLanes)(patternWriter.io.txLfsrCtrl.resetLfsr)) + + descrambler.io.increment := VecInit(Seq.fill(afeParams.mbLanes)(patternReader.io.rxLfsrCtrl.increment)) + descrambler.io.resetLfsr := VecInit(Seq.fill(afeParams.mbLanes)(patternReader.io.rxLfsrCtrl.resetLfsr)) + + val zeroMainband = 0.U.asTypeOf(chiselTypeOf(patternReader.io.mbRxLaneIo)) + patternReader.io.mbRxLaneIo := Mux(patternWriter.io.mbTxLaneIo.valid, patternWriter.io.mbTxLaneIo.bits, zeroMainband) + + val autoTxSelfCalDone = RegNext(io.autoCompleteSelfCal && dut.io.trainingCtrl.txSelfCalStart, false.B) + val autoRxClkCalDone = RegNext(io.autoCompleteSelfCal && dut.io.trainingCtrl.rxClkCalStart, false.B) + + dut.io.trainingCtrl.txSelfCalDone := autoTxSelfCalDone + dut.io.trainingCtrl.rxClkCalDone := autoRxClkCalDone + + val prevReadyForReq = RegNext(dut.io.trainingCtrl.req.readyForReq, false.B) + val readyForReqRise = dut.io.trainingCtrl.req.readyForReq && !prevReadyForReq + val trainerIssueComplete = RegInit(false.B) + val trainerStartPulse = WireDefault(false.B) + val trainerCompletePulse = WireDefault(false.B) + + when(!io.autoRunLinkOps) { + trainerIssueComplete := false.B + }.elsewhen(readyForReqRise) { + when(!trainerIssueComplete) { + trainerStartPulse := true.B + trainerIssueComplete := true.B + }.otherwise { + trainerCompletePulse := true.B + trainerIssueComplete := false.B + } + } + + dut.io.trainingCtrl.req.start := trainerStartPulse + dut.io.trainingCtrl.req.complete := trainerCompletePulse + dut.io.trainingCtrl.req.testKind := TrainingTestType.PointTest + + io.currentState := dut.io.currentState + io.done := dut.io.fsmCtrl.done + io.error := dut.io.fsmCtrl.error +} + +class MBTrainSMTest extends AnyFunSpec with ChiselSim { + describe("MBTrainSM") { + it("traverses the supported nominal MBTRAIN states with real point-test loopback") { + simulate(new MBTrainLoopbackHarness()) { dut => + dut.io.start.poke(false.B) + dut.io.pllLock.poke(true.B) + dut.io.autoRunLinkOps.poke(true.B) + dut.io.autoCompleteSelfCal.poke(true.B) + dut.clock.step(2) + + dut.io.start.poke(true.B) + + var seenStates = Set.empty[BigInt] + var cycles = 0 + while (!dut.io.done.peekBoolean() && !dut.io.error.peekBoolean() && cycles < 60000) { + val state = dut.io.currentState.peek().litValue + seenStates += state + dut.clock.step() + cycles += 1 + } + + assert( + dut.io.done.peekBoolean() || dut.io.error.peekBoolean(), + s"MBTRAIN made no forward progress within $cycles cycles" + ) + + Seq( + MBTrainState.sVALVREF, + MBTrainState.sDATAVREF, + MBTrainState.sSPEEDIDLE, + MBTrainState.sTXSELFCAL, + MBTrainState.sRXCLKCAL, + MBTrainState.sVALTRAINCENTER, + MBTrainState.sVALTRAINVREF, + MBTrainState.sDATATRAINCENTER1, + MBTrainState.sDATATRAINVREF, + MBTrainState.sRXDESKEW, + MBTrainState.sDATATRAINCENTER2, + MBTrainState.sLINKSPEED + ).foreach { state => + assert(seenStates.contains(state.litValue), s"Expected to visit $state, saw $seenStates") + } + } + } + } +} diff --git a/scala/test/src/logphy/ParallelGaloisLFSRTest.scala b/scala/test/src/uciedigital/logphy/ParallelGaloisLFSRTest.scala similarity index 100% rename from scala/test/src/logphy/ParallelGaloisLFSRTest.scala rename to scala/test/src/uciedigital/logphy/ParallelGaloisLFSRTest.scala diff --git a/scala/test/src/logphy/PhyRetrainSidebandHandshakeTest.scala b/scala/test/src/uciedigital/logphy/PhyRetrainSidebandHandshakeTest.scala similarity index 100% rename from scala/test/src/logphy/PhyRetrainSidebandHandshakeTest.scala rename to scala/test/src/uciedigital/logphy/PhyRetrainSidebandHandshakeTest.scala diff --git a/scala/test/src/logphy/RdiHandshakeIntegrationTest.scala b/scala/test/src/uciedigital/logphy/RdiHandshakeIntegrationTest.scala similarity index 100% rename from scala/test/src/logphy/RdiHandshakeIntegrationTest.scala rename to scala/test/src/uciedigital/logphy/RdiHandshakeIntegrationTest.scala diff --git a/scala/test/src/logphy/SBInitSMTest.scala b/scala/test/src/uciedigital/logphy/SBInitSMTest.scala similarity index 100% rename from scala/test/src/logphy/SBInitSMTest.scala rename to scala/test/src/uciedigital/logphy/SBInitSMTest.scala diff --git a/scala/test/src/phy/PhySpec.scala b/scala/test/src/uciedigital/phy/PhySpec.scala similarity index 100% rename from scala/test/src/phy/PhySpec.scala rename to scala/test/src/uciedigital/phy/PhySpec.scala diff --git a/scala/test/src/phy/PhyTestSpec.scala b/scala/test/src/uciedigital/phy/PhyTestSpec.scala similarity index 100% rename from scala/test/src/phy/PhyTestSpec.scala rename to scala/test/src/uciedigital/phy/PhyTestSpec.scala diff --git a/scala/test/src/protocol/ProtocolLayerTest.scala b/scala/test/src/uciedigital/protocol/ProtocolLayerTest.scala similarity index 100% rename from scala/test/src/protocol/ProtocolLayerTest.scala rename to scala/test/src/uciedigital/protocol/ProtocolLayerTest.scala diff --git a/scala/test/src/sideband/SidebandLinkSerdesTest.scala b/scala/test/src/uciedigital/sideband/SidebandLinkSerdesTest.scala similarity index 100% rename from scala/test/src/sideband/SidebandLinkSerdesTest.scala rename to scala/test/src/uciedigital/sideband/SidebandLinkSerdesTest.scala