From 7de2c945dbad989615befb7cf2ba446ecf870a05 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bj=C3=B6rn=20Gottschall?= <github.mail@bgottschall.de>
Date: Fri, 25 Nov 2022 13:21:35 +0100
Subject: [PATCH 1/2] * initial tracedoctor 1.15.1 commit

---
 src/main/scala/TraceDoctor.scala | 66 ++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)
 create mode 100644 src/main/scala/TraceDoctor.scala

diff --git a/src/main/scala/TraceDoctor.scala b/src/main/scala/TraceDoctor.scala
new file mode 100644
index 00000000..0576b794
--- /dev/null
+++ b/src/main/scala/TraceDoctor.scala
@@ -0,0 +1,66 @@
+package testchipip
+
+import chipsalliance.rocketchip.config.Field
+import chisel3._
+import freechips.rocketchip.diplomacy.{BundleBridgeNexusNode, LazyModuleImp}
+import freechips.rocketchip.rocket.TraceDoctor
+import freechips.rocketchip.subsystem.HasTiles
+import freechips.rocketchip.util.HeterogeneousBag
+
+
+// A per-tile interface that includes the tile's clock and reset
+class TileTraceDoctorIO(val traceWidth: Int) extends Bundle {
+  val clock: Clock = Clock()
+  val reset: Bool = Bool()
+  val data = new TraceDoctor(traceWidth)
+}
+
+// The IO matched on by the TraceDoctor bridge: a wrapper around a heterogenous
+// bag of TileTraceDoctorIO. Each entry is trace associated with a single tile
+class TraceDoctorOutputTop(val traceWidths: Seq[Int]) extends Bundle {
+  val tracedoctors: HeterogeneousBag[TileTraceDoctorIO] = Output(HeterogeneousBag(traceWidths.map(w => new TileTraceDoctorIO(w))))
+}
+
+object TraceDoctorOutputTop {
+  def apply(proto: Seq[TraceDoctor]): TraceDoctorOutputTop =
+    new TraceDoctorOutputTop(proto.map(t => t.traceWidth))
+}
+
+// Use this trait:
+trait CanHaveTraceDoctorIO { this: HasTiles =>
+  val module: CanHaveTraceDoctorIOModuleImp
+  // Bind all the trace nodes to a BB; we'll use this to generate the IO in the imp
+  val traceDoctorNexus = BundleBridgeNexusNode[TraceDoctor]()
+  tiles.foreach { traceDoctorNexus := _.traceDoctorNode }
+}
+case class TraceDoctorPortParams(print: Boolean = false)
+object TraceDoctorPortKey extends Field[Option[TraceDoctorPortParams]](None)
+
+trait CanHaveTraceDoctorIOModuleImp extends LazyModuleImp {
+  val outer: CanHaveTraceDoctorIO with HasTiles
+
+  val traceDoctorIO = p(TraceDoctorPortKey) map ( traceParams => {
+    val traceDoctorSeq = (outer.traceDoctorNexus.in.map(_._1))
+    val tio = IO(Output(TraceDoctorOutputTop(traceDoctorSeq)))
+
+    (tio.tracedoctors zip (outer.tile_prci_domains zip traceDoctorSeq)).foreach { case (port, (prci, tracedoc)) =>
+      port.clock := prci.module.clock
+      port.reset := prci.module.reset.asBool
+      port.data := tracedoc
+    }
+
+    if (traceParams.print) {
+      for ((trace, idx) <- tio.tracedoctors.zipWithIndex ) {
+        withClockAndReset(trace.clock, trace.reset) {
+          when (trace.data.valid) {
+            printf(s"TraceDoctor $idx: %x\n", trace.data.bits.asUInt)
+          }
+        }
+      }
+    }
+    tio
+  })
+}
+
+
+

From 425ac59f126a5d9f822badc623ef3e232abc1ece Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bj=C3=B6rn=20Gottschall?= <github.mail@bgottschall.de>
Date: Wed, 14 Dec 2022 14:34:07 +0100
Subject: [PATCH 2/2] * tracedoctor support for the TracerV trigger

---
 src/main/scala/TraceDoctor.scala | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/main/scala/TraceDoctor.scala b/src/main/scala/TraceDoctor.scala
index 0576b794..2619f733 100644
--- a/src/main/scala/TraceDoctor.scala
+++ b/src/main/scala/TraceDoctor.scala
@@ -13,6 +13,7 @@ class TileTraceDoctorIO(val traceWidth: Int) extends Bundle {
   val clock: Clock = Clock()
   val reset: Bool = Bool()
   val data = new TraceDoctor(traceWidth)
+  val tracerVTrigger: Bool = Bool()
 }
 
 // The IO matched on by the TraceDoctor bridge: a wrapper around a heterogenous
@@ -47,6 +48,11 @@ trait CanHaveTraceDoctorIOModuleImp extends LazyModuleImp {
       port.clock := prci.module.clock
       port.reset := prci.module.reset.asBool
       port.data := tracedoc
+
+      port.tracerVTrigger := false.B
+      midas.targetutils.TriggerSink.whenEnabled(false.B) {
+        port.tracerVTrigger := true.B
+      }
     }
 
     if (traceParams.print) {