From 0eecd503a252ec0314af916613543f855044e912 Mon Sep 17 00:00:00 2001
From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
Date: Thu, 27 Aug 2015 21:46:20 -0300
Subject: [PATCH 01/15] Chisel (on latest version) implementation: SystemC
 Decoupled and Template file (need to be tested).

---
 src/main/resources/template_cpp.txt |  27 +++++++
 src/main/resources/template_h.txt   |  58 +++++++++++++++
 src/main/scala/SCWrapper.scala      | 106 +++++++++++++++++-----------
 src/main/scala/SysC.scala           |  34 +++++----
 4 files changed, 169 insertions(+), 56 deletions(-)
 create mode 100644 src/main/resources/template_cpp.txt
 create mode 100644 src/main/resources/template_h.txt

diff --git a/src/main/resources/template_cpp.txt b/src/main/resources/template_cpp.txt
new file mode 100644
index 00000000..19962870
--- /dev/null
+++ b/src/main/resources/template_cpp.txt
@@ -0,0 +1,27 @@
+#include "{!name!}.h"
+
+void {!name!}::input_thread(void){
+  while(true){
+//    wait(data_written_event);
+    {!input_thread!}
+    {!set_valid_ready!}
+    //Clock Lo
+    c->clock_lo(reset);
+    wait(Step);
+//    data_read_event.notify(SC_ZERO_TIME);
+  }
+}
+
+void {!name!}::output_thread(void){
+//  data_written_event.notify(SC_ZERO_TIME);
+  while(true){
+    wait(data_read_event);
+    {!output_thread!}
+    {!reset_valid_ready!}
+    //Clock Hi
+    c->clock_hi(reset);
+    wait(Step);
+//    data_written_event.notify(SC_ZERO_TIME);
+  }
+}
+
diff --git a/src/main/resources/template_h.txt b/src/main/resources/template_h.txt
new file mode 100644
index 00000000..f1f46445
--- /dev/null
+++ b/src/main/resources/template_h.txt
@@ -0,0 +1,58 @@
+#ifndef __{!name!}__
+#define __{!name!}__
+
+#include <systemc.h>
+#include "{!header_file!}"
+
+// ========================================
+// dat_t needs to have this operator defined, so that
+// I'm allowed to use it with System C.
+// But be warned: I don't quite know what I
+// am doing.
+// ========================================
+template <int w>
+inline ostream& operator << (ostream& os, const dat_t<w>& arg){
+  return os;
+}
+
+SC_MODULE({!name!}){
+  {!component_type!}* c;
+
+  // in ports
+  {!input_ports!}
+  // out ports
+  {!output_ports!}
+  SC_HAS_PROCESS({!name!});
+  {!name!}(sc_module_name a_name, sc_time _step)
+  : sc_module(a_name), Step(_step)
+  {!sctor_list!}
+  {
+    // Initialize Component, Clock in RESET
+    c = new {!component_type!}();
+    c->init();
+    Step = Step/2;
+
+    // Clock Initialization? Don't understand what this is for. Copied from emulator.
+    for(int i = 0; i < 5; i++) {
+      dat_t<1> reset = LIT<1>(1);
+      c->clock_lo(reset);
+      c->clock_hi(reset);
+    }
+
+    //Register Thread
+    SC_THREAD(input_thread);
+//    {!sensitive_list!}
+    SC_THREAD(output_thread);
+  }
+
+  void input_thread(void);
+  void output_thread(void);
+
+//  sc_event data_read_event;
+//  sc_event data_written_event;
+  dat_t<1> reset = LIT<1>(0);
+  dat_t<1> set = LIT<1>(1);
+  sc_time Step;
+};
+
+#endif  //__{!name!}__
diff --git a/src/main/scala/SCWrapper.scala b/src/main/scala/SCWrapper.scala
index d1d659db..2d584419 100644
--- a/src/main/scala/SCWrapper.scala
+++ b/src/main/scala/SCWrapper.scala
@@ -54,21 +54,21 @@ object SCWrapper {
 
   def example_component_def(): ComponentDef = {
     val cdef = new ComponentDef("GCD_t", "GCD")
-    cdef.entries += new CEntry("a", true, "dat_t<1>", "GCD__io_a", "GCD__io_r1", "GCD__io_v1")
-    cdef.entries += new CEntry("z", false, "dat_t<1>", "GCD__io_z", "GCD__io_rz", "GCD__io_vz")
+    cdef.entries += new CEntry("a", true, "dat_t<1>", 1, "GCD__io_a", "GCD__io_r1", "GCD__io_v1")
+    cdef.entries += new CEntry("z", false, "dat_t<1>", 1, "GCD__io_z", "GCD__io_rz", "GCD__io_vz")
     cdef
   }
 
   def example_component_def2(): ComponentDef = {
     val cdef = new ComponentDef("AddFilter_t", "AddFilter")
-    cdef.entries += new CEntry("a", true, "dat_t<16>", "AddFilter__io_a", "AddFilter__io_ar", "AddFilter__io_av")
-    cdef.entries += new CEntry("b", false, "dat_t<16>", "AddFilter__io_b", "AddFilter__io_br", "AddFilter__io_bv")
+    cdef.entries += new CEntry("a", true, "dat_t<16>", 16, "AddFilter__io_a", "AddFilter__io_ar", "AddFilter__io_av")
+    cdef.entries += new CEntry("b", false, "dat_t<16>", 16, "AddFilter__io_b", "AddFilter__io_br", "AddFilter__io_bv")
     cdef
   }
 
-  def genwrapper(c: ComponentDef, filename:  String) {
+  def genwrapper(c: ComponentDef, filename:  String, templatefile: String) {
     //Read in template
-    val template = read_resource("template.txt")
+    val template = read_resource(templatefile)
 
     //Generate replacements
     val replacements = generate_replacements(c)
@@ -81,9 +81,9 @@ object SCWrapper {
     System.out.println(filled)
   }
 
-  def genwrapper(c: ComponentDef, filewriter: java.io.FileWriter){
+  def genwrapper(c: ComponentDef, filewriter: java.io.FileWriter, templatefile: String){
     //Read in template
-    val template = read_resource("template.txt")
+    val template = read_resource(templatefile)
 
     //Generate replacements
     val replacements = generate_replacements(c)
@@ -106,62 +106,80 @@ object SCWrapper {
     replacements += (("name", "SCWrapped" + c.name))
     replacements += (("component_type", c.ctype))
 
-    //I/O Fifos
+    //I/O Ports
     /*begin*/{
-      var input_fifos = ""
-      var output_fifos = ""
+      var input_ports = ""
+      var output_ports = ""
+	  var sctor_list = ""
+      var input_thread = ""
+      var output_thread = ""
+
       for( e <- c.entries) {
-        val decl = "sc_fifo<%s >* %s;\n  ".format(e.ctype, e.name)
+        val decl_in  = "sc_in<sc_uint<%s> > %s__io_%s;\n  ".format(e.cwidth, c.name, e.name)
+        val decl_out = "sc_out<sc_uint<%s> > %s__io_%s;\n  ".format(e.cwidth, c.name, e.name)
+        val thread_in = "c->%s__io_%s = LIT<%s>(%s__io_%s->read());\n    ".format(c.name, e.name, e.cwidth, c.name, e.name)
+        val thread_out = "%s__io_%s->write(c->%s__io_%s.to_ulong());\n    ".format(c.name, e.name, c.name, e.name)
+        //val decl = "sc_fifo<%s >* %s;\n  ".format(e.ctype, e.name)
         if(e.is_input) {
-          input_fifos += decl
+          input_ports += decl_in
+          sctor_list += ", %s__io_%s(\"%s\")".format(c.name, e.name, e.name)
+          //sensitive_list += " << %s__io_%s".format(c.name, e.name)
+          input_thread += thread_in
         } else {
-          output_fifos += decl
+          output_ports += decl_out
+          sctor_list += ", %s__io_%s(\"%s\")".format(c.name, e.name, e.name)
+          output_thread += thread_out
         }
       }
-      replacements += (("input_fifos", input_fifos))
-      replacements += (("output_fifos", output_fifos))
+      replacements += (("input_ports", input_ports))
+      replacements += (("output_ports", output_ports))
+      replacements += (("sctor_list", sctor_list))
+      //sensitive_list += ";"
+      //replacements += (("sensitive_list", sensitive_list))
+      replacements += (("input_thread", input_thread))
+      replacements += (("output_thread", output_thread))
     }
 
-    /*Initialize output fifos*/{
-      //Pull out output fifos
-      val fifos = ArrayBuffer[CEntry]();
+    /*Initialize output ports*/{
+      //Pull out output ports
+      val ports = ArrayBuffer[CEntry]();
       for(e <- c.entries) {
         if(!e.is_input) {
-          fifos += e;
+          ports += e;
         }
       }
       //Initialize
       var init = "";
-      for( i <- 0 until fifos.size) {
-        init += "%s = new sc_fifo<%s >(1);\n  ".format(fifos(i).name, fifos(i).ctype)
+      for( i <- 0 until ports.size) {
+        init += "%s = new sc_fifo**???**<%s >(1);\n  ".format(ports(i).name, ports(i).ctype)
       }
       replacements += (("init_output_fifos", init))
     }
 
     /*Check input queues*/{
-      //Pull out input fifos
+      //Pull out input ports
       val dvar = ArrayBuffer[String]()
       val fvar = ArrayBuffer[String]()
-      val fifos = ArrayBuffer[CEntry]()
+      val ports = ArrayBuffer[CEntry]()
       for( e <- c.entries) {
         if(e.is_input) {
           dvar += genvar("dat")
           fvar += genvar("filled")
-          fifos += e
+          ports += e
         }
       }
       //Initialize
       var init = ""
       var fill = ""
       var check = ""
-      for( i <- 0 until fifos.size) {
-        val ctype = fifos(i).ctype
+      for( i <- 0 until ports.size) {
+        val ctype = ports(i).ctype
         val data = dvar(i)
         val filled = fvar(i)
-        val in = fifos(i).name
-        val in_data = fifos(i).data
-        val ready = fifos(i).ready
-        val valid = fifos(i).valid
+        val in = ports(i).name
+        val in_data = ports(i).data
+        val ready = ports(i).ready
+        val valid = ports(i).valid
         init += "%s %s;\n    ".format(ctype, data)
         init += "int %s = 0;\n    ".format(filled)
         fill += "if(!%s){%s = %s->nb_read(%s);}\n      "format(filled, filled, in, data)
@@ -183,22 +201,22 @@ object SCWrapper {
     }
 
     /*Check Output Queues*/{
-      //Pull out output fifos
-      val fifos = ArrayBuffer[CEntry]()
+      //Pull out output ports
+      val ports = ArrayBuffer[CEntry]()
           for (e <- c.entries) {
             if(!e.is_input) {
-              fifos += e
+              ports += e
             }
           }
       //Check
       var check = ""
       var valid_output = "";
-      for(i <- 0 until fifos.size) {
-        val ctype = fifos(i).ctype
-        val valid = fifos(i).valid
-        val data = fifos(i).data
-        val ready = fifos(i).ready
-        val out = fifos(i).name
+      for(i <- 0 until ports.size) {
+        val ctype = ports(i).ctype
+        val valid = ports(i).valid
+        val data = ports(i).data
+        val ready = ports(i).ready
+        val out = ports(i).name
         check += "c->%s = LIT<1>(%s->num_free() > 0);\n      "format(ready, out)
         // Is this a structured data-type?
         if (ctype == data) {
@@ -220,11 +238,11 @@ object SCWrapper {
 
     // If we have structured FIFO elements, we need to generate the struct definitions
     //  and the ostream "<<" definition to keep SystemC happy.
-    val ostream_lsh = ArrayBuffer[String]()
+/*    val ostream_lsh = ArrayBuffer[String]()
     for((name, struct) <- c.structs) {
       ostream_lsh += struct.toString + "inline ostream& operator << (ostream& os, const %s& arg){  return os; }\n".format(name)
     }
-    replacements += (("ostream_lsh", ostream_lsh.mkString("\n")))
+    replacements += (("ostream_lsh", ostream_lsh.mkString("\n")))	*/
     replacements
   }
 
@@ -309,10 +327,11 @@ object SCWrapper {
   }
 }
 
-class CEntry(a_name: String, input: Boolean, a_type: String, a_data: String, a_ready: String, a_valid: String) {
+class CEntry(a_name: String, input: Boolean, a_type: String, a_width: Int, a_data: String, a_ready: String, a_valid: String) {
    val name = a_name
    val is_input = input
    val ctype = a_type
+   val cwidth = a_width
    val data = a_data
    val ready = a_ready
    val valid = a_valid
@@ -321,6 +340,7 @@ class CEntry(a_name: String, input: Boolean, a_type: String, a_data: String, a_r
      name + " " +
      is_input + " " +
      ctype + " " +
+     cwidth + " " +
      data + " " +
      ready + " " +
      valid
diff --git a/src/main/scala/SysC.scala b/src/main/scala/SysC.scala
index 566a3cfa..73c17e19 100644
--- a/src/main/scala/SysC.scala
+++ b/src/main/scala/SysC.scala
@@ -30,9 +30,7 @@
 
 package Chisel
 
-/** If we have structured/aggregate types as top-level ports, we define suitable structures
-  * for encapsulating their components, in order to treat them as sc_fifo elements.
-  */
+
 class SysCBackend extends CppBackend {
    override def elaborate(c: Module): Unit = {
       super.elaborate(c)
@@ -51,29 +49,35 @@ class SysCBackend extends CppBackend {
             case bits: Bits => {
               val is_input = bits.dir == INPUT
               val vtype = "dat_t<" + bits.width + ">" // direct use of width here?
-              val entry = new CEntry(name, is_input, vtype, bits.name, delt.ready.name, delt.valid.name)
+              val entry = new CEntry(name, is_input, vtype, bits.width, bits.name, delt.ready.name, delt.valid.name)
               cdef.entries += (entry)
             }
             case aggregate: Aggregate => {
               // Collect all the inputs and outputs.
               val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
               if (inputs.length > 0) {
-                val aName = "cs_" + aggregate.name + "_i"
-                cdef.structs(aName)= new CStruct(aName, inputs)
-                val entry = new CEntry(name, true, aName, aName, delt.ready.name, delt.valid.name)
+                val aName = "dat_t<" + aggregate.width + ">"		//"cs_" + aggregate.name + "_i"
+                //cdef.structs(aName)= new CStruct(aName, inputs)
+                val entry = new CEntry(name, true, aName, aggregate.width, aggregate.name, delt.ready.name, delt.valid.name)
                 cdef.entries += (entry)
               }
               val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
               if (outputs.length > 0) {
-                val aName = "cs_" + aggregate.name + "_o"
-                cdef.structs(aName) = new CStruct(aName, outputs)
-                val entry = new CEntry(name, false, aName, aName, delt.ready.name, delt.valid.name)
+                val aName = "dat_t<" + aggregate.width + ">"		//"cs_" + aggregate.name + "_o"
+                //cdef.structs(aName) = new CStruct(aName, outputs)
+                val entry = new CEntry(name, false, aName, aggregate.width, aggregate.name, delt.ready.name, delt.valid.name)
                 cdef.entries += (entry)
               }
             }
             case _ => badElements(name) = elt
           }
         }
+        case bits: Bits => {
+          val is_input = bits.dir == INPUT
+          val vtype = "dat_t<" + bits.width + ">" // direct use of width here?
+          val entry = new CEntry(name, is_input, vtype, bits.width, bits.name, "ready", "valid")
+          cdef.entries += (entry)
+        }
         case _ => badElements(name) = elt
       }
     }
@@ -93,9 +97,13 @@ class SysCBackend extends CppBackend {
       //Print out the component definition.
       println(cdef)
 
-      //Generate the file.
-      val out_p = createOutputFile("SCWrapped" + c.name + ".cpp");
-      SCWrapper.genwrapper(cdef, out_p)
+      //Generate SCWrapped files
+      val out_h = createOutputFile("SCWrapped" + c.name + ".h");
+      val template_h = "template_h.txt"
+      SCWrapper.genwrapper(cdef, out_h, template_h)
+      val out_cpp = createOutputFile("SCWrapped" + c.name + ".cpp");
+      val template_cpp = "template_cpp.txt"
+      SCWrapper.genwrapper(cdef, out_cpp, template_cpp)
     }
   }
 }

From 5fddcfc78fae7dcaeca2b55554091ff84cfcf441 Mon Sep 17 00:00:00 2001
From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
Date: Sat, 29 Aug 2015 20:07:40 -0300
Subject: [PATCH 02/15] Updated Sysc.scala, not funcional yet. Fix Chisel
 version in Makefile.

---
 Makefile                            |  2 +-
 src/main/resources/template_cpp.txt |  6 +++---
 src/main/resources/template_h.txt   |  1 -
 src/main/scala/SysC.scala           | 30 +++++++++++++++++++----------
 4 files changed, 24 insertions(+), 15 deletions(-)

diff --git a/Makefile b/Makefile
index 6e8f99af..5418b1b9 100644
--- a/Makefile
+++ b/Makefile
@@ -9,7 +9,7 @@ CLEAN_DIRS	:= doc
 SRC_DIR	?= .
 #SYSTEMC ?= $(SRC_DIR)/../../systemc/systemc-2.3.1
 SYSCTESTS ?= $(addsuffix .sysctest,$(notdir $(basename $(wildcard $(SRC_DIR)/src/test/scala/SysCTest/*.scala))))
-CHISEL_JAR ?= $(SRC_DIR)/target/scala-2.10/chisel_2.10-2.3-SNAPSHOT.jar
+CHISEL_JAR ?= $(SRC_DIR)/target/scala-2.11/chisel_2.11-2.3-SNAPSHOT.jar
 TEST_OUTPUT_DIR ?= ./test-outputs
 
 .PHONY:	smoke publish-local check clean jenkins-build sysctest coverage scaladoc test
diff --git a/src/main/resources/template_cpp.txt b/src/main/resources/template_cpp.txt
index 19962870..948ef661 100644
--- a/src/main/resources/template_cpp.txt
+++ b/src/main/resources/template_cpp.txt
@@ -4,7 +4,7 @@ void {!name!}::input_thread(void){
   while(true){
 //    wait(data_written_event);
     {!input_thread!}
-    {!set_valid_ready!}
+//    {!set_valid_ready!}
     //Clock Lo
     c->clock_lo(reset);
     wait(Step);
@@ -15,9 +15,9 @@ void {!name!}::input_thread(void){
 void {!name!}::output_thread(void){
 //  data_written_event.notify(SC_ZERO_TIME);
   while(true){
-    wait(data_read_event);
+//    wait(data_read_event);
     {!output_thread!}
-    {!reset_valid_ready!}
+//    {!reset_valid_ready!}
     //Clock Hi
     c->clock_hi(reset);
     wait(Step);
diff --git a/src/main/resources/template_h.txt b/src/main/resources/template_h.txt
index f1f46445..257cd962 100644
--- a/src/main/resources/template_h.txt
+++ b/src/main/resources/template_h.txt
@@ -34,7 +34,6 @@ SC_MODULE({!name!}){
 
     // Clock Initialization? Don't understand what this is for. Copied from emulator.
     for(int i = 0; i < 5; i++) {
-      dat_t<1> reset = LIT<1>(1);
       c->clock_lo(reset);
       c->clock_hi(reset);
     }
diff --git a/src/main/scala/SysC.scala b/src/main/scala/SysC.scala
index 73c17e19..84534c22 100644
--- a/src/main/scala/SysC.scala
+++ b/src/main/scala/SysC.scala
@@ -55,18 +55,28 @@ class SysCBackend extends CppBackend {
             case aggregate: Aggregate => {
               // Collect all the inputs and outputs.
               val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
-              if (inputs.length > 0) {
-                val aName = "dat_t<" + aggregate.width + ">"		//"cs_" + aggregate.name + "_i"
-                //cdef.structs(aName)= new CStruct(aName, inputs)
-                val entry = new CEntry(name, true, aName, aggregate.width, aggregate.name, delt.ready.name, delt.valid.name)
-                cdef.entries += (entry)
-              }
+             // if (inputs.length > 0) {
+				val l = inputs.length
+				for (i <- 1 to l) {
+				  //val aName = "cs_" + aggregate.name + "_i"
+				  val cmpnt = aggregate.flatten.map(_._2)
+				  val vtype = "dat_t<" + 1 + ">" 
+                  //cdef.structs(aName)= new CStruct(aName, inputs)
+                  //val entry = new CEntry(name, true, aName, 1, aggregate.name, delt.ready.name, delt.valid.name)
+                  val entry = new CEntry(name, true, vtype, 1, aggregate.name, "ready", "valid")
+                  cdef.entries += (entry)
+				}
+              //}
               val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
               if (outputs.length > 0) {
-                val aName = "dat_t<" + aggregate.width + ">"		//"cs_" + aggregate.name + "_o"
-                //cdef.structs(aName) = new CStruct(aName, outputs)
-                val entry = new CEntry(name, false, aName, aggregate.width, aggregate.name, delt.ready.name, delt.valid.name)
-                cdef.entries += (entry)
+				for (t <- 0 until outputs.length) {
+                  //val aName = "cs_" + aggregate.name + "_o"
+				  val vtype = "dat_t<" + 1 + ">" 
+                  //cdef.structs(aName) = new CStruct(aName, outputs)
+                  //val entry = new CEntry(name, false, aName, 1, aggregate.name, delt.ready.name, delt.valid.name)
+                  val entry = new CEntry(name, false, vtype, 1, aggregate.name, "ready", "valid")
+                  cdef.entries += (entry)
+				}
               }
             }
             case _ => badElements(name) = elt

From 4fbab60f1b647cacdce47dcbb01d290b38283318 Mon Sep 17 00:00:00 2001
From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
Date: Sun, 30 Aug 2015 21:33:11 -0300
Subject: [PATCH 03/15] SystemC backend running ok for Decoupled protocol
 (needs to be teted with Sodor).

---
 src/main/resources/template_cpp.txt |  2 --
 src/main/scala/SCWrapper.scala      | 22 +++++++++++++++------
 src/main/scala/SysC.scala           | 30 ++++++++++++++---------------
 3 files changed, 30 insertions(+), 24 deletions(-)

diff --git a/src/main/resources/template_cpp.txt b/src/main/resources/template_cpp.txt
index 948ef661..359adff5 100644
--- a/src/main/resources/template_cpp.txt
+++ b/src/main/resources/template_cpp.txt
@@ -4,7 +4,6 @@ void {!name!}::input_thread(void){
   while(true){
 //    wait(data_written_event);
     {!input_thread!}
-//    {!set_valid_ready!}
     //Clock Lo
     c->clock_lo(reset);
     wait(Step);
@@ -17,7 +16,6 @@ void {!name!}::output_thread(void){
   while(true){
 //    wait(data_read_event);
     {!output_thread!}
-//    {!reset_valid_ready!}
     //Clock Hi
     c->clock_hi(reset);
     wait(Step);
diff --git a/src/main/scala/SCWrapper.scala b/src/main/scala/SCWrapper.scala
index 2d584419..7a9d8144 100644
--- a/src/main/scala/SCWrapper.scala
+++ b/src/main/scala/SCWrapper.scala
@@ -115,22 +115,32 @@ object SCWrapper {
       var output_thread = ""
 
       for( e <- c.entries) {
-        val decl_in  = "sc_in<sc_uint<%s> > %s__io_%s;\n  ".format(e.cwidth, c.name, e.name)
-        val decl_out = "sc_out<sc_uint<%s> > %s__io_%s;\n  ".format(e.cwidth, c.name, e.name)
-        val thread_in = "c->%s__io_%s = LIT<%s>(%s__io_%s->read());\n    ".format(c.name, e.name, e.cwidth, c.name, e.name)
-        val thread_out = "%s__io_%s->write(c->%s__io_%s.to_ulong());\n    ".format(c.name, e.name, c.name, e.name)
+        val decl_in  = "sc_in<sc_bv<%s> > %s;\n  ".format(e.cwidth, e.data)
+        val decl_out = "sc_out<sc_bv<%s> > %s;\n  ".format(e.cwidth, e.data)
+        val thread_in = "c->%s = LIT<%s>(%s->read().to_uint64());\n    ".format(e.data, e.cwidth, e.data)
+        val thread_out = "%s->write(c->%s.to_ulong());\n    ".format(e.data, e.data)
         //val decl = "sc_fifo<%s >* %s;\n  ".format(e.ctype, e.name)
         if(e.is_input) {
           input_ports += decl_in
-          sctor_list += ", %s__io_%s(\"%s\")".format(c.name, e.name, e.name)
+          sctor_list += ", %s(\"%s\")\n  ".format(e.data, e.data)
           //sensitive_list += " << %s__io_%s".format(c.name, e.name)
           input_thread += thread_in
         } else {
           output_ports += decl_out
-          sctor_list += ", %s__io_%s(\"%s\")".format(c.name, e.name, e.name)
+          sctor_list += ", %s(\"%s\")\n  ".format(e.data, e.data)
           output_thread += thread_out
         }
       }
+	  output_ports += "sc_out<sc_bv<1> > %s__io_in_ready;\n  ".format(c.name)
+	  output_ports += "sc_out<sc_bv<1> > %s__io_out_valid;\n  ".format(c.name)
+	  sctor_list += ", %s__io_in_ready(\"%s__io_in_ready\")\n  ".format(c.name, c.name)
+	  sctor_list += ", %s__io_out_valid(\"%s__io_out_valid\")".format(c.name, c.name)
+	  input_thread += "c->%s__io_in_valid = set;\n    ".format(c.name)
+	  input_thread += "c->%s__io_out_ready = set;\n    ".format(c.name)
+	  output_thread += "%s__io_out_valid->write(c->%s__io_out_valid.to_ulong());\n    ".format(c.name, c.name)
+	  output_thread += "%s__io_in_ready->write(c->%s__io_in_ready.to_ulong());\n    ".format(c.name, c.name)
+	  output_thread += "c->%s__io_in_valid = reset;\n    ".format(c.name)
+	  output_thread += "c->%s__io_out_ready = reset;".format(c.name)
       replacements += (("input_ports", input_ports))
       replacements += (("output_ports", output_ports))
       replacements += (("sctor_list", sctor_list))
diff --git a/src/main/scala/SysC.scala b/src/main/scala/SysC.scala
index 84534c22..e1c8f39e 100644
--- a/src/main/scala/SysC.scala
+++ b/src/main/scala/SysC.scala
@@ -55,28 +55,26 @@ class SysCBackend extends CppBackend {
             case aggregate: Aggregate => {
               // Collect all the inputs and outputs.
               val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
-             // if (inputs.length > 0) {
-				val l = inputs.length
-				for (i <- 1 to l) {
-				  //val aName = "cs_" + aggregate.name + "_i"
-				  val cmpnt = aggregate.flatten.map(_._2)
-				  val vtype = "dat_t<" + 1 + ">" 
-                  //cdef.structs(aName)= new CStruct(aName, inputs)
-                  //val entry = new CEntry(name, true, aName, 1, aggregate.name, delt.ready.name, delt.valid.name)
-                  val entry = new CEntry(name, true, vtype, 1, aggregate.name, "ready", "valid")
+              if (inputs.length > 0) {
+			    for (in <- inputs) { 
+				  val vtype = "dat_t<" + in._2.width + ">" 
+                  val entry = new CEntry(name, true, vtype, in._2.width, in._2.name, "ready", "valid")
                   cdef.entries += (entry)
 				}
-              //}
+				//val aName = "cs_" + aggregate.name + "_i"
+                //cdef.structs(aName)= new CStruct(aName, inputs)
+                //val entry = new CEntry(name, true, aName, 1, aggregate.name, delt.ready.name, delt.valid.name)
+              }
               val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
               if (outputs.length > 0) {
-				for (t <- 0 until outputs.length) {
-                  //val aName = "cs_" + aggregate.name + "_o"
-				  val vtype = "dat_t<" + 1 + ">" 
-                  //cdef.structs(aName) = new CStruct(aName, outputs)
-                  //val entry = new CEntry(name, false, aName, 1, aggregate.name, delt.ready.name, delt.valid.name)
-                  val entry = new CEntry(name, false, vtype, 1, aggregate.name, "ready", "valid")
+			    for (out <- outputs) { 
+				  val vtype = "dat_t<" + out._2.width + ">" 
+                  val entry = new CEntry(name, false, vtype, out._2.width, out._2.name, "ready", "valid")
                   cdef.entries += (entry)
 				}
+                //val aName = "cs_" + aggregate.name + "_o"
+                //cdef.structs(aName) = new CStruct(aName, outputs)
+                //val entry = new CEntry(name, false, aName, 1, aggregate.name, delt.ready.name, delt.valid.name)
               }
             }
             case _ => badElements(name) = elt

From f73054902b4dc92e6c0ed09e344c48f64253d8a2 Mon Sep 17 00:00:00 2001
From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
Date: Mon, 31 Aug 2015 12:07:08 -0300
Subject: [PATCH 04/15] Updated SysemC backend: fix generation of no decoupled
 modules code

---
 src/main/scala/SysC.scala | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/main/scala/SysC.scala b/src/main/scala/SysC.scala
index e1c8f39e..17b8301f 100644
--- a/src/main/scala/SysC.scala
+++ b/src/main/scala/SysC.scala
@@ -51,6 +51,7 @@ class SysCBackend extends CppBackend {
               val vtype = "dat_t<" + bits.width + ">" // direct use of width here?
               val entry = new CEntry(name, is_input, vtype, bits.width, bits.name, delt.ready.name, delt.valid.name)
               cdef.entries += (entry)
+			  cdef.valid_ready = true
             }
             case aggregate: Aggregate => {
               // Collect all the inputs and outputs.
@@ -76,6 +77,7 @@ class SysCBackend extends CppBackend {
                 //cdef.structs(aName) = new CStruct(aName, outputs)
                 //val entry = new CEntry(name, false, aName, 1, aggregate.name, delt.ready.name, delt.valid.name)
               }
+			  cdef.valid_ready = true
             }
             case _ => badElements(name) = elt
           }
@@ -85,6 +87,7 @@ class SysCBackend extends CppBackend {
           val vtype = "dat_t<" + bits.width + ">" // direct use of width here?
           val entry = new CEntry(name, is_input, vtype, bits.width, bits.name, "ready", "valid")
           cdef.entries += (entry)
+		  cdef.valid_ready = false
         }
         case _ => badElements(name) = elt
       }

From 5e40cab4dfc4a49e44051e7dcf3c5a212471aa2e Mon Sep 17 00:00:00 2001
From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
Date: Mon, 31 Aug 2015 18:51:08 -0300
Subject: [PATCH 05/15] Updadted Chisel SCWrapper.scala.

---
 src/main/scala/SCWrapper.scala | 23 +++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/src/main/scala/SCWrapper.scala b/src/main/scala/SCWrapper.scala
index 7a9d8144..104885aa 100644
--- a/src/main/scala/SCWrapper.scala
+++ b/src/main/scala/SCWrapper.scala
@@ -131,16 +131,18 @@ object SCWrapper {
           output_thread += thread_out
         }
       }
-	  output_ports += "sc_out<sc_bv<1> > %s__io_in_ready;\n  ".format(c.name)
-	  output_ports += "sc_out<sc_bv<1> > %s__io_out_valid;\n  ".format(c.name)
-	  sctor_list += ", %s__io_in_ready(\"%s__io_in_ready\")\n  ".format(c.name, c.name)
-	  sctor_list += ", %s__io_out_valid(\"%s__io_out_valid\")".format(c.name, c.name)
-	  input_thread += "c->%s__io_in_valid = set;\n    ".format(c.name)
-	  input_thread += "c->%s__io_out_ready = set;\n    ".format(c.name)
-	  output_thread += "%s__io_out_valid->write(c->%s__io_out_valid.to_ulong());\n    ".format(c.name, c.name)
-	  output_thread += "%s__io_in_ready->write(c->%s__io_in_ready.to_ulong());\n    ".format(c.name, c.name)
-	  output_thread += "c->%s__io_in_valid = reset;\n    ".format(c.name)
-	  output_thread += "c->%s__io_out_ready = reset;".format(c.name)
+	  if (c.valid_ready == true){
+		sctor_list += ", %s__io_in_ready(\"%s__io_in_ready\")\n  ".format(c.name, c.name)
+		sctor_list += ", %s__io_out_valid(\"%s__io_out_valid\")".format(c.name, c.name)
+		output_ports += "sc_out<sc_bv<1> > %s__io_in_ready;\n  ".format(c.name)
+		output_ports += "sc_out<sc_bv<1> > %s__io_out_valid;\n  ".format(c.name)
+		input_thread += "c->%s__io_in_valid = set;\n    ".format(c.name)
+		input_thread += "c->%s__io_out_ready = set;\n    ".format(c.name)
+		output_thread += "%s__io_out_valid->write(c->%s__io_out_valid.to_ulong());\n    ".format(c.name, c.name)
+		output_thread += "%s__io_in_ready->write(c->%s__io_in_ready.to_ulong());\n    ".format(c.name, c.name)
+		output_thread += "c->%s__io_in_valid = reset;\n    ".format(c.name)
+		output_thread += "c->%s__io_out_ready = reset;".format(c.name)
+	  }
       replacements += (("input_ports", input_ports))
       replacements += (("output_ports", output_ports))
       replacements += (("sctor_list", sctor_list))
@@ -360,6 +362,7 @@ class CEntry(a_name: String, input: Boolean, a_type: String, a_width: Int, a_dat
 class ComponentDef(a_type: String, a_name: String) {
   val ctype: String = a_type
   val name: String = a_name
+  var valid_ready: Boolean = false
   val entries = ArrayBuffer[CEntry]()
   val structs = scala.collection.mutable.LinkedHashMap[String, CStruct]()
 

From 0b47bf33b7164a8cb544efbc9d9347d689c1708b Mon Sep 17 00:00:00 2001
From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
Date: Tue, 1 Sep 2015 15:49:53 -0300
Subject: [PATCH 06/15] Fixes and Updates into SystemC Backand: satus ok,
 tested with AllTypes + FullAdder{Decoupled}.

---
 src/main/resources/template_cpp.txt |  5 --
 src/main/resources/template_h.txt   |  3 --
 src/main/scala/SCWrapper.scala      | 51 +++++++++++----------
 src/main/scala/SysC.scala           | 71 +++++++++++++++++++++--------
 4 files changed, 79 insertions(+), 51 deletions(-)

diff --git a/src/main/resources/template_cpp.txt b/src/main/resources/template_cpp.txt
index 359adff5..13f60767 100644
--- a/src/main/resources/template_cpp.txt
+++ b/src/main/resources/template_cpp.txt
@@ -2,24 +2,19 @@
 
 void {!name!}::input_thread(void){
   while(true){
-//    wait(data_written_event);
     {!input_thread!}
     //Clock Lo
     c->clock_lo(reset);
     wait(Step);
-//    data_read_event.notify(SC_ZERO_TIME);
   }
 }
 
 void {!name!}::output_thread(void){
-//  data_written_event.notify(SC_ZERO_TIME);
   while(true){
-//    wait(data_read_event);
     {!output_thread!}
     //Clock Hi
     c->clock_hi(reset);
     wait(Step);
-//    data_written_event.notify(SC_ZERO_TIME);
   }
 }
 
diff --git a/src/main/resources/template_h.txt b/src/main/resources/template_h.txt
index 257cd962..020ac13e 100644
--- a/src/main/resources/template_h.txt
+++ b/src/main/resources/template_h.txt
@@ -40,15 +40,12 @@ SC_MODULE({!name!}){
 
     //Register Thread
     SC_THREAD(input_thread);
-//    {!sensitive_list!}
     SC_THREAD(output_thread);
   }
 
   void input_thread(void);
   void output_thread(void);
 
-//  sc_event data_read_event;
-//  sc_event data_written_event;
   dat_t<1> reset = LIT<1>(0);
   dat_t<1> set = LIT<1>(1);
   sc_time Step;
diff --git a/src/main/scala/SCWrapper.scala b/src/main/scala/SCWrapper.scala
index 104885aa..e5d2993c 100644
--- a/src/main/scala/SCWrapper.scala
+++ b/src/main/scala/SCWrapper.scala
@@ -54,15 +54,15 @@ object SCWrapper {
 
   def example_component_def(): ComponentDef = {
     val cdef = new ComponentDef("GCD_t", "GCD")
-    cdef.entries += new CEntry("a", true, "dat_t<1>", 1, "GCD__io_a", "GCD__io_r1", "GCD__io_v1")
-    cdef.entries += new CEntry("z", false, "dat_t<1>", 1, "GCD__io_z", "GCD__io_rz", "GCD__io_vz")
+    cdef.entries += new CEntry("a", true, "dat_t<1>", "dat_t<1>", 1, "GCD__io_a", "GCD__io_r1", "GCD__io_v1")
+    cdef.entries += new CEntry("z", false, "dat_t<1>", "dat_t<1>", 1, "GCD__io_z", "GCD__io_rz", "GCD__io_vz")
     cdef
   }
 
   def example_component_def2(): ComponentDef = {
     val cdef = new ComponentDef("AddFilter_t", "AddFilter")
-    cdef.entries += new CEntry("a", true, "dat_t<16>", 16, "AddFilter__io_a", "AddFilter__io_ar", "AddFilter__io_av")
-    cdef.entries += new CEntry("b", false, "dat_t<16>", 16, "AddFilter__io_b", "AddFilter__io_br", "AddFilter__io_bv")
+    cdef.entries += new CEntry("a", true, "dat_t<16>", "dat_t<1>", 16, "AddFilter__io_a", "AddFilter__io_ar", "AddFilter__io_av")
+    cdef.entries += new CEntry("b", false, "dat_t<16>", "dat_t<1>", 16, "AddFilter__io_b", "AddFilter__io_br", "AddFilter__io_bv")
     cdef
   }
 
@@ -115,10 +115,10 @@ object SCWrapper {
       var output_thread = ""
 
       for( e <- c.entries) {
-        val decl_in  = "sc_in<sc_bv<%s> > %s;\n  ".format(e.cwidth, e.data)
-        val decl_out = "sc_out<sc_bv<%s> > %s;\n  ".format(e.cwidth, e.data)
-        val thread_in = "c->%s = LIT<%s>(%s->read().to_uint64());\n    ".format(e.data, e.cwidth, e.data)
-        val thread_out = "%s->write(c->%s.to_ulong());\n    ".format(e.data, e.data)
+        val decl_in  = "sc_in<%s > %s;\n  ".format(e.ctype, e.data)
+        val decl_out = "sc_out<%s > %s;\n  ".format(e.ctype, e.data)
+        val thread_in = "c->%s = LIT<%s>(%s->read()%s);\n    ".format(e.data, e.cwidth, e.data, e.ccast)
+        val thread_out = "%s->write(c->%s%s);\n    ".format(e.data, e.data, e.ccast)
         //val decl = "sc_fifo<%s >* %s;\n  ".format(e.ctype, e.name)
         if(e.is_input) {
           input_ports += decl_in
@@ -339,24 +339,25 @@ object SCWrapper {
   }
 }
 
-class CEntry(a_name: String, input: Boolean, a_type: String, a_width: Int, a_data: String, a_ready: String, a_valid: String) {
-   val name = a_name
-   val is_input = input
-   val ctype = a_type
-   val cwidth = a_width
-   val data = a_data
-   val ready = a_ready
-   val valid = a_valid
+class CEntry(a_name: String, input: Boolean, a_type: String, a_cast: String, a_width: Int, a_data: String, a_ready: String, a_valid: String) {
+  val name = a_name
+  val is_input = input
+  val ctype = a_type
+  val ccast = a_cast
+  val cwidth = a_width
+  val data = a_data
+  val ready = a_ready
+  val valid = a_valid
 
-   override def toString(): String = {
-     name + " " +
-     is_input + " " +
-     ctype + " " +
-     cwidth + " " +
-     data + " " +
-     ready + " " +
-     valid
-   }
+  override def toString(): String = {
+    name + " " +
+    is_input + " " +
+    ctype + " " +
+    cwidth + " " +
+    data + " " +
+    ready + " " +
+    valid
+  }
 }
 
 class ComponentDef(a_type: String, a_name: String) {
diff --git a/src/main/scala/SysC.scala b/src/main/scala/SysC.scala
index 17b8301f..ce94c1a3 100644
--- a/src/main/scala/SysC.scala
+++ b/src/main/scala/SysC.scala
@@ -48,8 +48,11 @@ class SysCBackend extends CppBackend {
           delt.bits match {
             case bits: Bits => {
               val is_input = bits.dir == INPUT
-              val vtype = "dat_t<" + bits.width + ">" // direct use of width here?
-              val entry = new CEntry(name, is_input, vtype, bits.width, bits.name, delt.ready.name, delt.valid.name)
+              val vtype = "sc_uint<" + bits.width + ">"; var tcast = ""
+			  if (is_input) { tcast = ".to_uint64()" }
+			  else { tcast = ".to_ulong()" }
+			  val vcast = tcast
+              val entry = new CEntry(name, is_input, vtype, vcast, bits.width, bits.name, delt.ready.name, delt.valid.name)
               cdef.entries += (entry)
 			  cdef.valid_ready = true
             }
@@ -57,35 +60,67 @@ class SysCBackend extends CppBackend {
               // Collect all the inputs and outputs.
               val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
               if (inputs.length > 0) {
-			    for (in <- inputs) { 
-				  val vtype = "dat_t<" + in._2.width + ">" 
-                  val entry = new CEntry(name, true, vtype, in._2.width, in._2.name, "ready", "valid")
+			    for (in <- inputs) {
+				  var ttype = ""; var tcast = ""
+				   in._2 match {
+					case inUBool: Bool => ttype = "bool"; tcast = ""
+					case inSInt: SInt => ttype = "sc_int<" + in._2.width + ">";  tcast = ".to_uint64()"
+					//Bits is implemented as UInt
+					case inUInt: UInt => ttype = "sc_uint<" + in._2.width + ">"; tcast = ".to_uint64()"
+				  }
+				  val vtype = ttype; val vcast = tcast
+                  val entry = new CEntry(name, true, vtype, vcast, in._2.width, in._2.name, "ready", "valid")
                   cdef.entries += (entry)
 				}
-				//val aName = "cs_" + aggregate.name + "_i"
-                //cdef.structs(aName)= new CStruct(aName, inputs)
-                //val entry = new CEntry(name, true, aName, 1, aggregate.name, delt.ready.name, delt.valid.name)
               }
               val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
               if (outputs.length > 0) {
-			    for (out <- outputs) { 
-				  val vtype = "dat_t<" + out._2.width + ">" 
-                  val entry = new CEntry(name, false, vtype, out._2.width, out._2.name, "ready", "valid")
+			    for (out <- outputs) {
+				  var ttype = ""; var tcast = ""
+				   out._2 match {
+					case outUBool: Bool => ttype = "bool"; tcast = ".to_ulong()"
+					case outSInt: SInt => ttype = "sc_int<" + out._2.width + ">";  tcast = ".to_ulong()"
+					//Bits is implemented as UInt
+					case outUInt: UInt => ttype = "sc_uint<" + out._2.width + ">"; tcast = ".to_ulong()"
+				  }
+				  val vtype = ttype; val vcast = tcast
+                  val entry = new CEntry(name, false, vtype, vcast, out._2.width, out._2.name, "ready", "valid")
                   cdef.entries += (entry)
 				}
-                //val aName = "cs_" + aggregate.name + "_o"
-                //cdef.structs(aName) = new CStruct(aName, outputs)
-                //val entry = new CEntry(name, false, aName, 1, aggregate.name, delt.ready.name, delt.valid.name)
               }
 			  cdef.valid_ready = true
             }
             case _ => badElements(name) = elt
           }
         }
-        case bits: Bits => {
-          val is_input = bits.dir == INPUT
-          val vtype = "dat_t<" + bits.width + ">" // direct use of width here?
-          val entry = new CEntry(name, is_input, vtype, bits.width, bits.name, "ready", "valid")
+        case bool: Bool => {
+          val is_input = bool.dir == INPUT
+          val vtype = "bool"; var tcast = ""
+		  if (is_input) { tcast = "" }
+		  else { tcast = ".to_ulong()" }
+		  val vcast = tcast
+          val entry = new CEntry(name, is_input, vtype, vcast, bool.width, bool.name, "ready", "valid")
+          cdef.entries += (entry)
+		  cdef.valid_ready = false
+        }
+        case sint: SInt => {
+          val is_input = sint.dir == INPUT
+          val vtype = "sc_int<" + sint.width + ">"; var tcast = ""
+		  if (is_input) { tcast = ".to_uint64()" }
+		  else { tcast = ".to_ulong()" }
+		  val vcast = tcast
+          val entry = new CEntry(name, is_input, vtype, vcast, sint.width, sint.name, "ready", "valid")
+          cdef.entries += (entry)
+		  cdef.valid_ready = false
+        }
+		//Bits is implemented as UInt
+        case uint: UInt => {
+          val is_input = uint.dir == INPUT
+          val vtype = "sc_uint<" + uint.width + ">"; var tcast = ""
+		  if (is_input) { tcast = ".to_uint64()" }
+		  else { tcast = ".to_ulong()" }
+		  val vcast = tcast
+          val entry = new CEntry(name, is_input, vtype, vcast, uint.width, uint.name, "ready", "valid")
           cdef.entries += (entry)
 		  cdef.valid_ready = false
         }

From a3d2fdaf628868a6849ab88217b3ba172ac2474b Mon Sep 17 00:00:00 2001
From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
Date: Wed, 2 Sep 2015 10:12:32 -0300
Subject: [PATCH 07/15] Updated SCWrapper.scala. Cheked Chisel generation for
 Decoupled and non-Decoupled signals -> all works fine.

---
 src/main/scala/SCWrapper.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/SCWrapper.scala b/src/main/scala/SCWrapper.scala
index e5d2993c..8b11632a 100644
--- a/src/main/scala/SCWrapper.scala
+++ b/src/main/scala/SCWrapper.scala
@@ -134,8 +134,8 @@ object SCWrapper {
 	  if (c.valid_ready == true){
 		sctor_list += ", %s__io_in_ready(\"%s__io_in_ready\")\n  ".format(c.name, c.name)
 		sctor_list += ", %s__io_out_valid(\"%s__io_out_valid\")".format(c.name, c.name)
-		output_ports += "sc_out<sc_bv<1> > %s__io_in_ready;\n  ".format(c.name)
-		output_ports += "sc_out<sc_bv<1> > %s__io_out_valid;\n  ".format(c.name)
+		output_ports += "sc_out<bool > %s__io_in_ready;\n  ".format(c.name)
+		output_ports += "sc_out<bool > %s__io_out_valid;\n  ".format(c.name)
 		input_thread += "c->%s__io_in_valid = set;\n    ".format(c.name)
 		input_thread += "c->%s__io_out_ready = set;\n    ".format(c.name)
 		output_thread += "%s__io_out_valid->write(c->%s__io_out_valid.to_ulong());\n    ".format(c.name, c.name)

From 896bb247b93365e9b54fdea10d891793c0464bee Mon Sep 17 00:00:00 2001
From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
Date: Wed, 2 Sep 2015 11:10:30 -0300
Subject: [PATCH 08/15] Included a new folder with patches.

---
 ...-version-implementation-SystemC-Deco.patch | 405 ++++++++++++++++++
 ...la-not-funcional-yet.-Fix-Chisel-ver.patch | 109 +++++
 ...running-ok-for-Decoupled-protocol-ne.patch | 125 ++++++
 ...ackend-fix-generation-of-no-decouple.patch |  41 ++
 ...0005-Updadted-Chisel-SCWrapper.scala.patch |  53 +++
 ...s-into-SystemC-Backand-satus-ok-test.patch | 249 +++++++++++
 ...r.scala.-Cheked-Chisel-generation-fo.patch |  28 ++
 .../chisel_systemc_backend_patch.tar.gz       | Bin 0 -> 7891 bytes
 8 files changed, 1010 insertions(+)
 create mode 100644 patches/20150902/0001-Chisel-on-latest-version-implementation-SystemC-Deco.patch
 create mode 100644 patches/20150902/0002-Updated-Sysc.scala-not-funcional-yet.-Fix-Chisel-ver.patch
 create mode 100644 patches/20150902/0003-SystemC-backend-running-ok-for-Decoupled-protocol-ne.patch
 create mode 100644 patches/20150902/0004-Updated-SysemC-backend-fix-generation-of-no-decouple.patch
 create mode 100644 patches/20150902/0005-Updadted-Chisel-SCWrapper.scala.patch
 create mode 100644 patches/20150902/0006-Fixes-and-Updates-into-SystemC-Backand-satus-ok-test.patch
 create mode 100644 patches/20150902/0007-Updated-SCWrapper.scala.-Cheked-Chisel-generation-fo.patch
 create mode 100644 patches/20150902/chisel_systemc_backend_patch.tar.gz

diff --git a/patches/20150902/0001-Chisel-on-latest-version-implementation-SystemC-Deco.patch b/patches/20150902/0001-Chisel-on-latest-version-implementation-SystemC-Deco.patch
new file mode 100644
index 00000000..c797310d
--- /dev/null
+++ b/patches/20150902/0001-Chisel-on-latest-version-implementation-SystemC-Deco.patch
@@ -0,0 +1,405 @@
+From 4e7d87e3d532770d3d315a8be7ae751ae73a60c5 Mon Sep 17 00:00:00 2001
+From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
+Date: Thu, 27 Aug 2015 21:46:20 -0300
+Subject: [PATCH 1/7] Chisel (on latest version) implementation: SystemC
+ Decoupled and Template file (need to be tested).
+
+---
+ src/main/resources/template_cpp.txt |  27 +++++++++
+ src/main/resources/template_h.txt   |  58 ++++++++++++++++++++
+ src/main/scala/SCWrapper.scala      | 106 +++++++++++++++++++++---------------
+ src/main/scala/SysC.scala           |  34 +++++++-----
+ 4 files changed, 169 insertions(+), 56 deletions(-)
+ create mode 100644 src/main/resources/template_cpp.txt
+ create mode 100644 src/main/resources/template_h.txt
+
+diff --git a/src/main/resources/template_cpp.txt b/src/main/resources/template_cpp.txt
+new file mode 100644
+index 0000000..1996287
+--- /dev/null
++++ b/src/main/resources/template_cpp.txt
+@@ -0,0 +1,27 @@
++#include "{!name!}.h"
++
++void {!name!}::input_thread(void){
++  while(true){
++//    wait(data_written_event);
++    {!input_thread!}
++    {!set_valid_ready!}
++    //Clock Lo
++    c->clock_lo(reset);
++    wait(Step);
++//    data_read_event.notify(SC_ZERO_TIME);
++  }
++}
++
++void {!name!}::output_thread(void){
++//  data_written_event.notify(SC_ZERO_TIME);
++  while(true){
++    wait(data_read_event);
++    {!output_thread!}
++    {!reset_valid_ready!}
++    //Clock Hi
++    c->clock_hi(reset);
++    wait(Step);
++//    data_written_event.notify(SC_ZERO_TIME);
++  }
++}
++
+diff --git a/src/main/resources/template_h.txt b/src/main/resources/template_h.txt
+new file mode 100644
+index 0000000..f1f4644
+--- /dev/null
++++ b/src/main/resources/template_h.txt
+@@ -0,0 +1,58 @@
++#ifndef __{!name!}__
++#define __{!name!}__
++
++#include <systemc.h>
++#include "{!header_file!}"
++
++// ========================================
++// dat_t needs to have this operator defined, so that
++// I'm allowed to use it with System C.
++// But be warned: I don't quite know what I
++// am doing.
++// ========================================
++template <int w>
++inline ostream& operator << (ostream& os, const dat_t<w>& arg){
++  return os;
++}
++
++SC_MODULE({!name!}){
++  {!component_type!}* c;
++
++  // in ports
++  {!input_ports!}
++  // out ports
++  {!output_ports!}
++  SC_HAS_PROCESS({!name!});
++  {!name!}(sc_module_name a_name, sc_time _step)
++  : sc_module(a_name), Step(_step)
++  {!sctor_list!}
++  {
++    // Initialize Component, Clock in RESET
++    c = new {!component_type!}();
++    c->init();
++    Step = Step/2;
++
++    // Clock Initialization? Don't understand what this is for. Copied from emulator.
++    for(int i = 0; i < 5; i++) {
++      dat_t<1> reset = LIT<1>(1);
++      c->clock_lo(reset);
++      c->clock_hi(reset);
++    }
++
++    //Register Thread
++    SC_THREAD(input_thread);
++//    {!sensitive_list!}
++    SC_THREAD(output_thread);
++  }
++
++  void input_thread(void);
++  void output_thread(void);
++
++//  sc_event data_read_event;
++//  sc_event data_written_event;
++  dat_t<1> reset = LIT<1>(0);
++  dat_t<1> set = LIT<1>(1);
++  sc_time Step;
++};
++
++#endif  //__{!name!}__
+diff --git a/src/main/scala/SCWrapper.scala b/src/main/scala/SCWrapper.scala
+index d1d659d..2d58441 100644
+--- a/src/main/scala/SCWrapper.scala
++++ b/src/main/scala/SCWrapper.scala
+@@ -54,21 +54,21 @@ object SCWrapper {
+ 
+   def example_component_def(): ComponentDef = {
+     val cdef = new ComponentDef("GCD_t", "GCD")
+-    cdef.entries += new CEntry("a", true, "dat_t<1>", "GCD__io_a", "GCD__io_r1", "GCD__io_v1")
+-    cdef.entries += new CEntry("z", false, "dat_t<1>", "GCD__io_z", "GCD__io_rz", "GCD__io_vz")
++    cdef.entries += new CEntry("a", true, "dat_t<1>", 1, "GCD__io_a", "GCD__io_r1", "GCD__io_v1")
++    cdef.entries += new CEntry("z", false, "dat_t<1>", 1, "GCD__io_z", "GCD__io_rz", "GCD__io_vz")
+     cdef
+   }
+ 
+   def example_component_def2(): ComponentDef = {
+     val cdef = new ComponentDef("AddFilter_t", "AddFilter")
+-    cdef.entries += new CEntry("a", true, "dat_t<16>", "AddFilter__io_a", "AddFilter__io_ar", "AddFilter__io_av")
+-    cdef.entries += new CEntry("b", false, "dat_t<16>", "AddFilter__io_b", "AddFilter__io_br", "AddFilter__io_bv")
++    cdef.entries += new CEntry("a", true, "dat_t<16>", 16, "AddFilter__io_a", "AddFilter__io_ar", "AddFilter__io_av")
++    cdef.entries += new CEntry("b", false, "dat_t<16>", 16, "AddFilter__io_b", "AddFilter__io_br", "AddFilter__io_bv")
+     cdef
+   }
+ 
+-  def genwrapper(c: ComponentDef, filename:  String) {
++  def genwrapper(c: ComponentDef, filename:  String, templatefile: String) {
+     //Read in template
+-    val template = read_resource("template.txt")
++    val template = read_resource(templatefile)
+ 
+     //Generate replacements
+     val replacements = generate_replacements(c)
+@@ -81,9 +81,9 @@ object SCWrapper {
+     System.out.println(filled)
+   }
+ 
+-  def genwrapper(c: ComponentDef, filewriter: java.io.FileWriter){
++  def genwrapper(c: ComponentDef, filewriter: java.io.FileWriter, templatefile: String){
+     //Read in template
+-    val template = read_resource("template.txt")
++    val template = read_resource(templatefile)
+ 
+     //Generate replacements
+     val replacements = generate_replacements(c)
+@@ -106,62 +106,80 @@ object SCWrapper {
+     replacements += (("name", "SCWrapped" + c.name))
+     replacements += (("component_type", c.ctype))
+ 
+-    //I/O Fifos
++    //I/O Ports
+     /*begin*/{
+-      var input_fifos = ""
+-      var output_fifos = ""
++      var input_ports = ""
++      var output_ports = ""
++	  var sctor_list = ""
++      var input_thread = ""
++      var output_thread = ""
++
+       for( e <- c.entries) {
+-        val decl = "sc_fifo<%s >* %s;\n  ".format(e.ctype, e.name)
++        val decl_in  = "sc_in<sc_uint<%s> > %s__io_%s;\n  ".format(e.cwidth, c.name, e.name)
++        val decl_out = "sc_out<sc_uint<%s> > %s__io_%s;\n  ".format(e.cwidth, c.name, e.name)
++        val thread_in = "c->%s__io_%s = LIT<%s>(%s__io_%s->read());\n    ".format(c.name, e.name, e.cwidth, c.name, e.name)
++        val thread_out = "%s__io_%s->write(c->%s__io_%s.to_ulong());\n    ".format(c.name, e.name, c.name, e.name)
++        //val decl = "sc_fifo<%s >* %s;\n  ".format(e.ctype, e.name)
+         if(e.is_input) {
+-          input_fifos += decl
++          input_ports += decl_in
++          sctor_list += ", %s__io_%s(\"%s\")".format(c.name, e.name, e.name)
++          //sensitive_list += " << %s__io_%s".format(c.name, e.name)
++          input_thread += thread_in
+         } else {
+-          output_fifos += decl
++          output_ports += decl_out
++          sctor_list += ", %s__io_%s(\"%s\")".format(c.name, e.name, e.name)
++          output_thread += thread_out
+         }
+       }
+-      replacements += (("input_fifos", input_fifos))
+-      replacements += (("output_fifos", output_fifos))
++      replacements += (("input_ports", input_ports))
++      replacements += (("output_ports", output_ports))
++      replacements += (("sctor_list", sctor_list))
++      //sensitive_list += ";"
++      //replacements += (("sensitive_list", sensitive_list))
++      replacements += (("input_thread", input_thread))
++      replacements += (("output_thread", output_thread))
+     }
+ 
+-    /*Initialize output fifos*/{
+-      //Pull out output fifos
+-      val fifos = ArrayBuffer[CEntry]();
++    /*Initialize output ports*/{
++      //Pull out output ports
++      val ports = ArrayBuffer[CEntry]();
+       for(e <- c.entries) {
+         if(!e.is_input) {
+-          fifos += e;
++          ports += e;
+         }
+       }
+       //Initialize
+       var init = "";
+-      for( i <- 0 until fifos.size) {
+-        init += "%s = new sc_fifo<%s >(1);\n  ".format(fifos(i).name, fifos(i).ctype)
++      for( i <- 0 until ports.size) {
++        init += "%s = new sc_fifo**???**<%s >(1);\n  ".format(ports(i).name, ports(i).ctype)
+       }
+       replacements += (("init_output_fifos", init))
+     }
+ 
+     /*Check input queues*/{
+-      //Pull out input fifos
++      //Pull out input ports
+       val dvar = ArrayBuffer[String]()
+       val fvar = ArrayBuffer[String]()
+-      val fifos = ArrayBuffer[CEntry]()
++      val ports = ArrayBuffer[CEntry]()
+       for( e <- c.entries) {
+         if(e.is_input) {
+           dvar += genvar("dat")
+           fvar += genvar("filled")
+-          fifos += e
++          ports += e
+         }
+       }
+       //Initialize
+       var init = ""
+       var fill = ""
+       var check = ""
+-      for( i <- 0 until fifos.size) {
+-        val ctype = fifos(i).ctype
++      for( i <- 0 until ports.size) {
++        val ctype = ports(i).ctype
+         val data = dvar(i)
+         val filled = fvar(i)
+-        val in = fifos(i).name
+-        val in_data = fifos(i).data
+-        val ready = fifos(i).ready
+-        val valid = fifos(i).valid
++        val in = ports(i).name
++        val in_data = ports(i).data
++        val ready = ports(i).ready
++        val valid = ports(i).valid
+         init += "%s %s;\n    ".format(ctype, data)
+         init += "int %s = 0;\n    ".format(filled)
+         fill += "if(!%s){%s = %s->nb_read(%s);}\n      "format(filled, filled, in, data)
+@@ -183,22 +201,22 @@ object SCWrapper {
+     }
+ 
+     /*Check Output Queues*/{
+-      //Pull out output fifos
+-      val fifos = ArrayBuffer[CEntry]()
++      //Pull out output ports
++      val ports = ArrayBuffer[CEntry]()
+           for (e <- c.entries) {
+             if(!e.is_input) {
+-              fifos += e
++              ports += e
+             }
+           }
+       //Check
+       var check = ""
+       var valid_output = "";
+-      for(i <- 0 until fifos.size) {
+-        val ctype = fifos(i).ctype
+-        val valid = fifos(i).valid
+-        val data = fifos(i).data
+-        val ready = fifos(i).ready
+-        val out = fifos(i).name
++      for(i <- 0 until ports.size) {
++        val ctype = ports(i).ctype
++        val valid = ports(i).valid
++        val data = ports(i).data
++        val ready = ports(i).ready
++        val out = ports(i).name
+         check += "c->%s = LIT<1>(%s->num_free() > 0);\n      "format(ready, out)
+         // Is this a structured data-type?
+         if (ctype == data) {
+@@ -220,11 +238,11 @@ object SCWrapper {
+ 
+     // If we have structured FIFO elements, we need to generate the struct definitions
+     //  and the ostream "<<" definition to keep SystemC happy.
+-    val ostream_lsh = ArrayBuffer[String]()
++/*    val ostream_lsh = ArrayBuffer[String]()
+     for((name, struct) <- c.structs) {
+       ostream_lsh += struct.toString + "inline ostream& operator << (ostream& os, const %s& arg){  return os; }\n".format(name)
+     }
+-    replacements += (("ostream_lsh", ostream_lsh.mkString("\n")))
++    replacements += (("ostream_lsh", ostream_lsh.mkString("\n")))	*/
+     replacements
+   }
+ 
+@@ -309,10 +327,11 @@ object SCWrapper {
+   }
+ }
+ 
+-class CEntry(a_name: String, input: Boolean, a_type: String, a_data: String, a_ready: String, a_valid: String) {
++class CEntry(a_name: String, input: Boolean, a_type: String, a_width: Int, a_data: String, a_ready: String, a_valid: String) {
+    val name = a_name
+    val is_input = input
+    val ctype = a_type
++   val cwidth = a_width
+    val data = a_data
+    val ready = a_ready
+    val valid = a_valid
+@@ -321,6 +340,7 @@ class CEntry(a_name: String, input: Boolean, a_type: String, a_data: String, a_r
+      name + " " +
+      is_input + " " +
+      ctype + " " +
++     cwidth + " " +
+      data + " " +
+      ready + " " +
+      valid
+diff --git a/src/main/scala/SysC.scala b/src/main/scala/SysC.scala
+index 566a3cf..73c17e1 100644
+--- a/src/main/scala/SysC.scala
++++ b/src/main/scala/SysC.scala
+@@ -30,9 +30,7 @@
+ 
+ package Chisel
+ 
+-/** If we have structured/aggregate types as top-level ports, we define suitable structures
+-  * for encapsulating their components, in order to treat them as sc_fifo elements.
+-  */
++
+ class SysCBackend extends CppBackend {
+    override def elaborate(c: Module): Unit = {
+       super.elaborate(c)
+@@ -51,29 +49,35 @@ class SysCBackend extends CppBackend {
+             case bits: Bits => {
+               val is_input = bits.dir == INPUT
+               val vtype = "dat_t<" + bits.width + ">" // direct use of width here?
+-              val entry = new CEntry(name, is_input, vtype, bits.name, delt.ready.name, delt.valid.name)
++              val entry = new CEntry(name, is_input, vtype, bits.width, bits.name, delt.ready.name, delt.valid.name)
+               cdef.entries += (entry)
+             }
+             case aggregate: Aggregate => {
+               // Collect all the inputs and outputs.
+               val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
+               if (inputs.length > 0) {
+-                val aName = "cs_" + aggregate.name + "_i"
+-                cdef.structs(aName)= new CStruct(aName, inputs)
+-                val entry = new CEntry(name, true, aName, aName, delt.ready.name, delt.valid.name)
++                val aName = "dat_t<" + aggregate.width + ">"		//"cs_" + aggregate.name + "_i"
++                //cdef.structs(aName)= new CStruct(aName, inputs)
++                val entry = new CEntry(name, true, aName, aggregate.width, aggregate.name, delt.ready.name, delt.valid.name)
+                 cdef.entries += (entry)
+               }
+               val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
+               if (outputs.length > 0) {
+-                val aName = "cs_" + aggregate.name + "_o"
+-                cdef.structs(aName) = new CStruct(aName, outputs)
+-                val entry = new CEntry(name, false, aName, aName, delt.ready.name, delt.valid.name)
++                val aName = "dat_t<" + aggregate.width + ">"		//"cs_" + aggregate.name + "_o"
++                //cdef.structs(aName) = new CStruct(aName, outputs)
++                val entry = new CEntry(name, false, aName, aggregate.width, aggregate.name, delt.ready.name, delt.valid.name)
+                 cdef.entries += (entry)
+               }
+             }
+             case _ => badElements(name) = elt
+           }
+         }
++        case bits: Bits => {
++          val is_input = bits.dir == INPUT
++          val vtype = "dat_t<" + bits.width + ">" // direct use of width here?
++          val entry = new CEntry(name, is_input, vtype, bits.width, bits.name, "ready", "valid")
++          cdef.entries += (entry)
++        }
+         case _ => badElements(name) = elt
+       }
+     }
+@@ -93,9 +97,13 @@ class SysCBackend extends CppBackend {
+       //Print out the component definition.
+       println(cdef)
+ 
+-      //Generate the file.
+-      val out_p = createOutputFile("SCWrapped" + c.name + ".cpp");
+-      SCWrapper.genwrapper(cdef, out_p)
++      //Generate SCWrapped files
++      val out_h = createOutputFile("SCWrapped" + c.name + ".h");
++      val template_h = "template_h.txt"
++      SCWrapper.genwrapper(cdef, out_h, template_h)
++      val out_cpp = createOutputFile("SCWrapped" + c.name + ".cpp");
++      val template_cpp = "template_cpp.txt"
++      SCWrapper.genwrapper(cdef, out_cpp, template_cpp)
+     }
+   }
+ }
+-- 
+2.1.0
+
diff --git a/patches/20150902/0002-Updated-Sysc.scala-not-funcional-yet.-Fix-Chisel-ver.patch b/patches/20150902/0002-Updated-Sysc.scala-not-funcional-yet.-Fix-Chisel-ver.patch
new file mode 100644
index 00000000..bbb2e7e8
--- /dev/null
+++ b/patches/20150902/0002-Updated-Sysc.scala-not-funcional-yet.-Fix-Chisel-ver.patch
@@ -0,0 +1,109 @@
+From 747f26151cb26ec40e6aa07529584b99c32bc1bd Mon Sep 17 00:00:00 2001
+From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
+Date: Sat, 29 Aug 2015 20:07:40 -0300
+Subject: [PATCH 2/7] Updated Sysc.scala, not funcional yet. Fix Chisel version
+ in Makefile.
+
+---
+ Makefile                            |  2 +-
+ src/main/resources/template_cpp.txt |  6 +++---
+ src/main/resources/template_h.txt   |  1 -
+ src/main/scala/SysC.scala           | 30 ++++++++++++++++++++----------
+ 4 files changed, 24 insertions(+), 15 deletions(-)
+
+diff --git a/Makefile b/Makefile
+index 6e8f99a..5418b1b 100644
+--- a/Makefile
++++ b/Makefile
+@@ -9,7 +9,7 @@ CLEAN_DIRS	:= doc
+ SRC_DIR	?= .
+ #SYSTEMC ?= $(SRC_DIR)/../../systemc/systemc-2.3.1
+ SYSCTESTS ?= $(addsuffix .sysctest,$(notdir $(basename $(wildcard $(SRC_DIR)/src/test/scala/SysCTest/*.scala))))
+-CHISEL_JAR ?= $(SRC_DIR)/target/scala-2.10/chisel_2.10-2.3-SNAPSHOT.jar
++CHISEL_JAR ?= $(SRC_DIR)/target/scala-2.11/chisel_2.11-2.3-SNAPSHOT.jar
+ TEST_OUTPUT_DIR ?= ./test-outputs
+ 
+ .PHONY:	smoke publish-local check clean jenkins-build sysctest coverage scaladoc test
+diff --git a/src/main/resources/template_cpp.txt b/src/main/resources/template_cpp.txt
+index 1996287..948ef66 100644
+--- a/src/main/resources/template_cpp.txt
++++ b/src/main/resources/template_cpp.txt
+@@ -4,7 +4,7 @@ void {!name!}::input_thread(void){
+   while(true){
+ //    wait(data_written_event);
+     {!input_thread!}
+-    {!set_valid_ready!}
++//    {!set_valid_ready!}
+     //Clock Lo
+     c->clock_lo(reset);
+     wait(Step);
+@@ -15,9 +15,9 @@ void {!name!}::input_thread(void){
+ void {!name!}::output_thread(void){
+ //  data_written_event.notify(SC_ZERO_TIME);
+   while(true){
+-    wait(data_read_event);
++//    wait(data_read_event);
+     {!output_thread!}
+-    {!reset_valid_ready!}
++//    {!reset_valid_ready!}
+     //Clock Hi
+     c->clock_hi(reset);
+     wait(Step);
+diff --git a/src/main/resources/template_h.txt b/src/main/resources/template_h.txt
+index f1f4644..257cd96 100644
+--- a/src/main/resources/template_h.txt
++++ b/src/main/resources/template_h.txt
+@@ -34,7 +34,6 @@ SC_MODULE({!name!}){
+ 
+     // Clock Initialization? Don't understand what this is for. Copied from emulator.
+     for(int i = 0; i < 5; i++) {
+-      dat_t<1> reset = LIT<1>(1);
+       c->clock_lo(reset);
+       c->clock_hi(reset);
+     }
+diff --git a/src/main/scala/SysC.scala b/src/main/scala/SysC.scala
+index 73c17e1..84534c2 100644
+--- a/src/main/scala/SysC.scala
++++ b/src/main/scala/SysC.scala
+@@ -55,18 +55,28 @@ class SysCBackend extends CppBackend {
+             case aggregate: Aggregate => {
+               // Collect all the inputs and outputs.
+               val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
+-              if (inputs.length > 0) {
+-                val aName = "dat_t<" + aggregate.width + ">"		//"cs_" + aggregate.name + "_i"
+-                //cdef.structs(aName)= new CStruct(aName, inputs)
+-                val entry = new CEntry(name, true, aName, aggregate.width, aggregate.name, delt.ready.name, delt.valid.name)
+-                cdef.entries += (entry)
+-              }
++             // if (inputs.length > 0) {
++				val l = inputs.length
++				for (i <- 1 to l) {
++				  //val aName = "cs_" + aggregate.name + "_i"
++				  val cmpnt = aggregate.flatten.map(_._2)
++				  val vtype = "dat_t<" + 1 + ">" 
++                  //cdef.structs(aName)= new CStruct(aName, inputs)
++                  //val entry = new CEntry(name, true, aName, 1, aggregate.name, delt.ready.name, delt.valid.name)
++                  val entry = new CEntry(name, true, vtype, 1, aggregate.name, "ready", "valid")
++                  cdef.entries += (entry)
++				}
++              //}
+               val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
+               if (outputs.length > 0) {
+-                val aName = "dat_t<" + aggregate.width + ">"		//"cs_" + aggregate.name + "_o"
+-                //cdef.structs(aName) = new CStruct(aName, outputs)
+-                val entry = new CEntry(name, false, aName, aggregate.width, aggregate.name, delt.ready.name, delt.valid.name)
+-                cdef.entries += (entry)
++				for (t <- 0 until outputs.length) {
++                  //val aName = "cs_" + aggregate.name + "_o"
++				  val vtype = "dat_t<" + 1 + ">" 
++                  //cdef.structs(aName) = new CStruct(aName, outputs)
++                  //val entry = new CEntry(name, false, aName, 1, aggregate.name, delt.ready.name, delt.valid.name)
++                  val entry = new CEntry(name, false, vtype, 1, aggregate.name, "ready", "valid")
++                  cdef.entries += (entry)
++				}
+               }
+             }
+             case _ => badElements(name) = elt
+-- 
+2.1.0
+
diff --git a/patches/20150902/0003-SystemC-backend-running-ok-for-Decoupled-protocol-ne.patch b/patches/20150902/0003-SystemC-backend-running-ok-for-Decoupled-protocol-ne.patch
new file mode 100644
index 00000000..07169482
--- /dev/null
+++ b/patches/20150902/0003-SystemC-backend-running-ok-for-Decoupled-protocol-ne.patch
@@ -0,0 +1,125 @@
+From 34d69817deaaf22f712d0b34425ecae172b686cb Mon Sep 17 00:00:00 2001
+From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
+Date: Sun, 30 Aug 2015 21:33:11 -0300
+Subject: [PATCH 3/7] SystemC backend running ok for Decoupled protocol (needs
+ to be teted with Sodor).
+
+---
+ src/main/resources/template_cpp.txt |  2 --
+ src/main/scala/SCWrapper.scala      | 22 ++++++++++++++++------
+ src/main/scala/SysC.scala           | 30 ++++++++++++++----------------
+ 3 files changed, 30 insertions(+), 24 deletions(-)
+
+diff --git a/src/main/resources/template_cpp.txt b/src/main/resources/template_cpp.txt
+index 948ef66..359adff 100644
+--- a/src/main/resources/template_cpp.txt
++++ b/src/main/resources/template_cpp.txt
+@@ -4,7 +4,6 @@ void {!name!}::input_thread(void){
+   while(true){
+ //    wait(data_written_event);
+     {!input_thread!}
+-//    {!set_valid_ready!}
+     //Clock Lo
+     c->clock_lo(reset);
+     wait(Step);
+@@ -17,7 +16,6 @@ void {!name!}::output_thread(void){
+   while(true){
+ //    wait(data_read_event);
+     {!output_thread!}
+-//    {!reset_valid_ready!}
+     //Clock Hi
+     c->clock_hi(reset);
+     wait(Step);
+diff --git a/src/main/scala/SCWrapper.scala b/src/main/scala/SCWrapper.scala
+index 2d58441..7a9d814 100644
+--- a/src/main/scala/SCWrapper.scala
++++ b/src/main/scala/SCWrapper.scala
+@@ -115,22 +115,32 @@ object SCWrapper {
+       var output_thread = ""
+ 
+       for( e <- c.entries) {
+-        val decl_in  = "sc_in<sc_uint<%s> > %s__io_%s;\n  ".format(e.cwidth, c.name, e.name)
+-        val decl_out = "sc_out<sc_uint<%s> > %s__io_%s;\n  ".format(e.cwidth, c.name, e.name)
+-        val thread_in = "c->%s__io_%s = LIT<%s>(%s__io_%s->read());\n    ".format(c.name, e.name, e.cwidth, c.name, e.name)
+-        val thread_out = "%s__io_%s->write(c->%s__io_%s.to_ulong());\n    ".format(c.name, e.name, c.name, e.name)
++        val decl_in  = "sc_in<sc_bv<%s> > %s;\n  ".format(e.cwidth, e.data)
++        val decl_out = "sc_out<sc_bv<%s> > %s;\n  ".format(e.cwidth, e.data)
++        val thread_in = "c->%s = LIT<%s>(%s->read().to_uint64());\n    ".format(e.data, e.cwidth, e.data)
++        val thread_out = "%s->write(c->%s.to_ulong());\n    ".format(e.data, e.data)
+         //val decl = "sc_fifo<%s >* %s;\n  ".format(e.ctype, e.name)
+         if(e.is_input) {
+           input_ports += decl_in
+-          sctor_list += ", %s__io_%s(\"%s\")".format(c.name, e.name, e.name)
++          sctor_list += ", %s(\"%s\")\n  ".format(e.data, e.data)
+           //sensitive_list += " << %s__io_%s".format(c.name, e.name)
+           input_thread += thread_in
+         } else {
+           output_ports += decl_out
+-          sctor_list += ", %s__io_%s(\"%s\")".format(c.name, e.name, e.name)
++          sctor_list += ", %s(\"%s\")\n  ".format(e.data, e.data)
+           output_thread += thread_out
+         }
+       }
++	  output_ports += "sc_out<sc_bv<1> > %s__io_in_ready;\n  ".format(c.name)
++	  output_ports += "sc_out<sc_bv<1> > %s__io_out_valid;\n  ".format(c.name)
++	  sctor_list += ", %s__io_in_ready(\"%s__io_in_ready\")\n  ".format(c.name, c.name)
++	  sctor_list += ", %s__io_out_valid(\"%s__io_out_valid\")".format(c.name, c.name)
++	  input_thread += "c->%s__io_in_valid = set;\n    ".format(c.name)
++	  input_thread += "c->%s__io_out_ready = set;\n    ".format(c.name)
++	  output_thread += "%s__io_out_valid->write(c->%s__io_out_valid.to_ulong());\n    ".format(c.name, c.name)
++	  output_thread += "%s__io_in_ready->write(c->%s__io_in_ready.to_ulong());\n    ".format(c.name, c.name)
++	  output_thread += "c->%s__io_in_valid = reset;\n    ".format(c.name)
++	  output_thread += "c->%s__io_out_ready = reset;".format(c.name)
+       replacements += (("input_ports", input_ports))
+       replacements += (("output_ports", output_ports))
+       replacements += (("sctor_list", sctor_list))
+diff --git a/src/main/scala/SysC.scala b/src/main/scala/SysC.scala
+index 84534c2..e1c8f39 100644
+--- a/src/main/scala/SysC.scala
++++ b/src/main/scala/SysC.scala
+@@ -55,28 +55,26 @@ class SysCBackend extends CppBackend {
+             case aggregate: Aggregate => {
+               // Collect all the inputs and outputs.
+               val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
+-             // if (inputs.length > 0) {
+-				val l = inputs.length
+-				for (i <- 1 to l) {
+-				  //val aName = "cs_" + aggregate.name + "_i"
+-				  val cmpnt = aggregate.flatten.map(_._2)
+-				  val vtype = "dat_t<" + 1 + ">" 
+-                  //cdef.structs(aName)= new CStruct(aName, inputs)
+-                  //val entry = new CEntry(name, true, aName, 1, aggregate.name, delt.ready.name, delt.valid.name)
+-                  val entry = new CEntry(name, true, vtype, 1, aggregate.name, "ready", "valid")
++              if (inputs.length > 0) {
++			    for (in <- inputs) { 
++				  val vtype = "dat_t<" + in._2.width + ">" 
++                  val entry = new CEntry(name, true, vtype, in._2.width, in._2.name, "ready", "valid")
+                   cdef.entries += (entry)
+ 				}
+-              //}
++				//val aName = "cs_" + aggregate.name + "_i"
++                //cdef.structs(aName)= new CStruct(aName, inputs)
++                //val entry = new CEntry(name, true, aName, 1, aggregate.name, delt.ready.name, delt.valid.name)
++              }
+               val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
+               if (outputs.length > 0) {
+-				for (t <- 0 until outputs.length) {
+-                  //val aName = "cs_" + aggregate.name + "_o"
+-				  val vtype = "dat_t<" + 1 + ">" 
+-                  //cdef.structs(aName) = new CStruct(aName, outputs)
+-                  //val entry = new CEntry(name, false, aName, 1, aggregate.name, delt.ready.name, delt.valid.name)
+-                  val entry = new CEntry(name, false, vtype, 1, aggregate.name, "ready", "valid")
++			    for (out <- outputs) { 
++				  val vtype = "dat_t<" + out._2.width + ">" 
++                  val entry = new CEntry(name, false, vtype, out._2.width, out._2.name, "ready", "valid")
+                   cdef.entries += (entry)
+ 				}
++                //val aName = "cs_" + aggregate.name + "_o"
++                //cdef.structs(aName) = new CStruct(aName, outputs)
++                //val entry = new CEntry(name, false, aName, 1, aggregate.name, delt.ready.name, delt.valid.name)
+               }
+             }
+             case _ => badElements(name) = elt
+-- 
+2.1.0
+
diff --git a/patches/20150902/0004-Updated-SysemC-backend-fix-generation-of-no-decouple.patch b/patches/20150902/0004-Updated-SysemC-backend-fix-generation-of-no-decouple.patch
new file mode 100644
index 00000000..477932e0
--- /dev/null
+++ b/patches/20150902/0004-Updated-SysemC-backend-fix-generation-of-no-decouple.patch
@@ -0,0 +1,41 @@
+From 0ebce712beea0e1f6ee0dfcbb22bee90906c1f3a Mon Sep 17 00:00:00 2001
+From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
+Date: Mon, 31 Aug 2015 12:07:08 -0300
+Subject: [PATCH 4/7] Updated SysemC backend: fix generation of no decoupled
+ modules code
+
+---
+ src/main/scala/SysC.scala | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/src/main/scala/SysC.scala b/src/main/scala/SysC.scala
+index e1c8f39..17b8301 100644
+--- a/src/main/scala/SysC.scala
++++ b/src/main/scala/SysC.scala
+@@ -51,6 +51,7 @@ class SysCBackend extends CppBackend {
+               val vtype = "dat_t<" + bits.width + ">" // direct use of width here?
+               val entry = new CEntry(name, is_input, vtype, bits.width, bits.name, delt.ready.name, delt.valid.name)
+               cdef.entries += (entry)
++			  cdef.valid_ready = true
+             }
+             case aggregate: Aggregate => {
+               // Collect all the inputs and outputs.
+@@ -76,6 +77,7 @@ class SysCBackend extends CppBackend {
+                 //cdef.structs(aName) = new CStruct(aName, outputs)
+                 //val entry = new CEntry(name, false, aName, 1, aggregate.name, delt.ready.name, delt.valid.name)
+               }
++			  cdef.valid_ready = true
+             }
+             case _ => badElements(name) = elt
+           }
+@@ -85,6 +87,7 @@ class SysCBackend extends CppBackend {
+           val vtype = "dat_t<" + bits.width + ">" // direct use of width here?
+           val entry = new CEntry(name, is_input, vtype, bits.width, bits.name, "ready", "valid")
+           cdef.entries += (entry)
++		  cdef.valid_ready = false
+         }
+         case _ => badElements(name) = elt
+       }
+-- 
+2.1.0
+
diff --git a/patches/20150902/0005-Updadted-Chisel-SCWrapper.scala.patch b/patches/20150902/0005-Updadted-Chisel-SCWrapper.scala.patch
new file mode 100644
index 00000000..a04ab6f0
--- /dev/null
+++ b/patches/20150902/0005-Updadted-Chisel-SCWrapper.scala.patch
@@ -0,0 +1,53 @@
+From 920384e827ccda78d7e06915fa32e2c4d462789e Mon Sep 17 00:00:00 2001
+From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
+Date: Mon, 31 Aug 2015 18:51:08 -0300
+Subject: [PATCH 5/7] Updadted Chisel SCWrapper.scala.
+
+---
+ src/main/scala/SCWrapper.scala | 23 +++++++++++++----------
+ 1 file changed, 13 insertions(+), 10 deletions(-)
+
+diff --git a/src/main/scala/SCWrapper.scala b/src/main/scala/SCWrapper.scala
+index 7a9d814..104885a 100644
+--- a/src/main/scala/SCWrapper.scala
++++ b/src/main/scala/SCWrapper.scala
+@@ -131,16 +131,18 @@ object SCWrapper {
+           output_thread += thread_out
+         }
+       }
+-	  output_ports += "sc_out<sc_bv<1> > %s__io_in_ready;\n  ".format(c.name)
+-	  output_ports += "sc_out<sc_bv<1> > %s__io_out_valid;\n  ".format(c.name)
+-	  sctor_list += ", %s__io_in_ready(\"%s__io_in_ready\")\n  ".format(c.name, c.name)
+-	  sctor_list += ", %s__io_out_valid(\"%s__io_out_valid\")".format(c.name, c.name)
+-	  input_thread += "c->%s__io_in_valid = set;\n    ".format(c.name)
+-	  input_thread += "c->%s__io_out_ready = set;\n    ".format(c.name)
+-	  output_thread += "%s__io_out_valid->write(c->%s__io_out_valid.to_ulong());\n    ".format(c.name, c.name)
+-	  output_thread += "%s__io_in_ready->write(c->%s__io_in_ready.to_ulong());\n    ".format(c.name, c.name)
+-	  output_thread += "c->%s__io_in_valid = reset;\n    ".format(c.name)
+-	  output_thread += "c->%s__io_out_ready = reset;".format(c.name)
++	  if (c.valid_ready == true){
++		sctor_list += ", %s__io_in_ready(\"%s__io_in_ready\")\n  ".format(c.name, c.name)
++		sctor_list += ", %s__io_out_valid(\"%s__io_out_valid\")".format(c.name, c.name)
++		output_ports += "sc_out<sc_bv<1> > %s__io_in_ready;\n  ".format(c.name)
++		output_ports += "sc_out<sc_bv<1> > %s__io_out_valid;\n  ".format(c.name)
++		input_thread += "c->%s__io_in_valid = set;\n    ".format(c.name)
++		input_thread += "c->%s__io_out_ready = set;\n    ".format(c.name)
++		output_thread += "%s__io_out_valid->write(c->%s__io_out_valid.to_ulong());\n    ".format(c.name, c.name)
++		output_thread += "%s__io_in_ready->write(c->%s__io_in_ready.to_ulong());\n    ".format(c.name, c.name)
++		output_thread += "c->%s__io_in_valid = reset;\n    ".format(c.name)
++		output_thread += "c->%s__io_out_ready = reset;".format(c.name)
++	  }
+       replacements += (("input_ports", input_ports))
+       replacements += (("output_ports", output_ports))
+       replacements += (("sctor_list", sctor_list))
+@@ -360,6 +362,7 @@ class CEntry(a_name: String, input: Boolean, a_type: String, a_width: Int, a_dat
+ class ComponentDef(a_type: String, a_name: String) {
+   val ctype: String = a_type
+   val name: String = a_name
++  var valid_ready: Boolean = false
+   val entries = ArrayBuffer[CEntry]()
+   val structs = scala.collection.mutable.LinkedHashMap[String, CStruct]()
+ 
+-- 
+2.1.0
+
diff --git a/patches/20150902/0006-Fixes-and-Updates-into-SystemC-Backand-satus-ok-test.patch b/patches/20150902/0006-Fixes-and-Updates-into-SystemC-Backand-satus-ok-test.patch
new file mode 100644
index 00000000..9e6f771b
--- /dev/null
+++ b/patches/20150902/0006-Fixes-and-Updates-into-SystemC-Backand-satus-ok-test.patch
@@ -0,0 +1,249 @@
+From be49342cf2945d343e70abfcae6f50e6a535ade2 Mon Sep 17 00:00:00 2001
+From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
+Date: Tue, 1 Sep 2015 15:49:53 -0300
+Subject: [PATCH 6/7] Fixes and Updates into SystemC Backand: satus ok, tested
+ with AllTypes + FullAdder{Decoupled}.
+
+---
+ src/main/resources/template_cpp.txt |  5 ---
+ src/main/resources/template_h.txt   |  3 --
+ src/main/scala/SCWrapper.scala      | 51 +++++++++++++-------------
+ src/main/scala/SysC.scala           | 71 +++++++++++++++++++++++++++----------
+ 4 files changed, 79 insertions(+), 51 deletions(-)
+
+diff --git a/src/main/resources/template_cpp.txt b/src/main/resources/template_cpp.txt
+index 359adff..13f6076 100644
+--- a/src/main/resources/template_cpp.txt
++++ b/src/main/resources/template_cpp.txt
+@@ -2,24 +2,19 @@
+ 
+ void {!name!}::input_thread(void){
+   while(true){
+-//    wait(data_written_event);
+     {!input_thread!}
+     //Clock Lo
+     c->clock_lo(reset);
+     wait(Step);
+-//    data_read_event.notify(SC_ZERO_TIME);
+   }
+ }
+ 
+ void {!name!}::output_thread(void){
+-//  data_written_event.notify(SC_ZERO_TIME);
+   while(true){
+-//    wait(data_read_event);
+     {!output_thread!}
+     //Clock Hi
+     c->clock_hi(reset);
+     wait(Step);
+-//    data_written_event.notify(SC_ZERO_TIME);
+   }
+ }
+ 
+diff --git a/src/main/resources/template_h.txt b/src/main/resources/template_h.txt
+index 257cd96..020ac13 100644
+--- a/src/main/resources/template_h.txt
++++ b/src/main/resources/template_h.txt
+@@ -40,15 +40,12 @@ SC_MODULE({!name!}){
+ 
+     //Register Thread
+     SC_THREAD(input_thread);
+-//    {!sensitive_list!}
+     SC_THREAD(output_thread);
+   }
+ 
+   void input_thread(void);
+   void output_thread(void);
+ 
+-//  sc_event data_read_event;
+-//  sc_event data_written_event;
+   dat_t<1> reset = LIT<1>(0);
+   dat_t<1> set = LIT<1>(1);
+   sc_time Step;
+diff --git a/src/main/scala/SCWrapper.scala b/src/main/scala/SCWrapper.scala
+index 104885a..e5d2993 100644
+--- a/src/main/scala/SCWrapper.scala
++++ b/src/main/scala/SCWrapper.scala
+@@ -54,15 +54,15 @@ object SCWrapper {
+ 
+   def example_component_def(): ComponentDef = {
+     val cdef = new ComponentDef("GCD_t", "GCD")
+-    cdef.entries += new CEntry("a", true, "dat_t<1>", 1, "GCD__io_a", "GCD__io_r1", "GCD__io_v1")
+-    cdef.entries += new CEntry("z", false, "dat_t<1>", 1, "GCD__io_z", "GCD__io_rz", "GCD__io_vz")
++    cdef.entries += new CEntry("a", true, "dat_t<1>", "dat_t<1>", 1, "GCD__io_a", "GCD__io_r1", "GCD__io_v1")
++    cdef.entries += new CEntry("z", false, "dat_t<1>", "dat_t<1>", 1, "GCD__io_z", "GCD__io_rz", "GCD__io_vz")
+     cdef
+   }
+ 
+   def example_component_def2(): ComponentDef = {
+     val cdef = new ComponentDef("AddFilter_t", "AddFilter")
+-    cdef.entries += new CEntry("a", true, "dat_t<16>", 16, "AddFilter__io_a", "AddFilter__io_ar", "AddFilter__io_av")
+-    cdef.entries += new CEntry("b", false, "dat_t<16>", 16, "AddFilter__io_b", "AddFilter__io_br", "AddFilter__io_bv")
++    cdef.entries += new CEntry("a", true, "dat_t<16>", "dat_t<1>", 16, "AddFilter__io_a", "AddFilter__io_ar", "AddFilter__io_av")
++    cdef.entries += new CEntry("b", false, "dat_t<16>", "dat_t<1>", 16, "AddFilter__io_b", "AddFilter__io_br", "AddFilter__io_bv")
+     cdef
+   }
+ 
+@@ -115,10 +115,10 @@ object SCWrapper {
+       var output_thread = ""
+ 
+       for( e <- c.entries) {
+-        val decl_in  = "sc_in<sc_bv<%s> > %s;\n  ".format(e.cwidth, e.data)
+-        val decl_out = "sc_out<sc_bv<%s> > %s;\n  ".format(e.cwidth, e.data)
+-        val thread_in = "c->%s = LIT<%s>(%s->read().to_uint64());\n    ".format(e.data, e.cwidth, e.data)
+-        val thread_out = "%s->write(c->%s.to_ulong());\n    ".format(e.data, e.data)
++        val decl_in  = "sc_in<%s > %s;\n  ".format(e.ctype, e.data)
++        val decl_out = "sc_out<%s > %s;\n  ".format(e.ctype, e.data)
++        val thread_in = "c->%s = LIT<%s>(%s->read()%s);\n    ".format(e.data, e.cwidth, e.data, e.ccast)
++        val thread_out = "%s->write(c->%s%s);\n    ".format(e.data, e.data, e.ccast)
+         //val decl = "sc_fifo<%s >* %s;\n  ".format(e.ctype, e.name)
+         if(e.is_input) {
+           input_ports += decl_in
+@@ -339,24 +339,25 @@ object SCWrapper {
+   }
+ }
+ 
+-class CEntry(a_name: String, input: Boolean, a_type: String, a_width: Int, a_data: String, a_ready: String, a_valid: String) {
+-   val name = a_name
+-   val is_input = input
+-   val ctype = a_type
+-   val cwidth = a_width
+-   val data = a_data
+-   val ready = a_ready
+-   val valid = a_valid
++class CEntry(a_name: String, input: Boolean, a_type: String, a_cast: String, a_width: Int, a_data: String, a_ready: String, a_valid: String) {
++  val name = a_name
++  val is_input = input
++  val ctype = a_type
++  val ccast = a_cast
++  val cwidth = a_width
++  val data = a_data
++  val ready = a_ready
++  val valid = a_valid
+ 
+-   override def toString(): String = {
+-     name + " " +
+-     is_input + " " +
+-     ctype + " " +
+-     cwidth + " " +
+-     data + " " +
+-     ready + " " +
+-     valid
+-   }
++  override def toString(): String = {
++    name + " " +
++    is_input + " " +
++    ctype + " " +
++    cwidth + " " +
++    data + " " +
++    ready + " " +
++    valid
++  }
+ }
+ 
+ class ComponentDef(a_type: String, a_name: String) {
+diff --git a/src/main/scala/SysC.scala b/src/main/scala/SysC.scala
+index 17b8301..ce94c1a 100644
+--- a/src/main/scala/SysC.scala
++++ b/src/main/scala/SysC.scala
+@@ -48,8 +48,11 @@ class SysCBackend extends CppBackend {
+           delt.bits match {
+             case bits: Bits => {
+               val is_input = bits.dir == INPUT
+-              val vtype = "dat_t<" + bits.width + ">" // direct use of width here?
+-              val entry = new CEntry(name, is_input, vtype, bits.width, bits.name, delt.ready.name, delt.valid.name)
++              val vtype = "sc_uint<" + bits.width + ">"; var tcast = ""
++			  if (is_input) { tcast = ".to_uint64()" }
++			  else { tcast = ".to_ulong()" }
++			  val vcast = tcast
++              val entry = new CEntry(name, is_input, vtype, vcast, bits.width, bits.name, delt.ready.name, delt.valid.name)
+               cdef.entries += (entry)
+ 			  cdef.valid_ready = true
+             }
+@@ -57,35 +60,67 @@ class SysCBackend extends CppBackend {
+               // Collect all the inputs and outputs.
+               val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
+               if (inputs.length > 0) {
+-			    for (in <- inputs) { 
+-				  val vtype = "dat_t<" + in._2.width + ">" 
+-                  val entry = new CEntry(name, true, vtype, in._2.width, in._2.name, "ready", "valid")
++			    for (in <- inputs) {
++				  var ttype = ""; var tcast = ""
++				   in._2 match {
++					case inUBool: Bool => ttype = "bool"; tcast = ""
++					case inSInt: SInt => ttype = "sc_int<" + in._2.width + ">";  tcast = ".to_uint64()"
++					//Bits is implemented as UInt
++					case inUInt: UInt => ttype = "sc_uint<" + in._2.width + ">"; tcast = ".to_uint64()"
++				  }
++				  val vtype = ttype; val vcast = tcast
++                  val entry = new CEntry(name, true, vtype, vcast, in._2.width, in._2.name, "ready", "valid")
+                   cdef.entries += (entry)
+ 				}
+-				//val aName = "cs_" + aggregate.name + "_i"
+-                //cdef.structs(aName)= new CStruct(aName, inputs)
+-                //val entry = new CEntry(name, true, aName, 1, aggregate.name, delt.ready.name, delt.valid.name)
+               }
+               val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
+               if (outputs.length > 0) {
+-			    for (out <- outputs) { 
+-				  val vtype = "dat_t<" + out._2.width + ">" 
+-                  val entry = new CEntry(name, false, vtype, out._2.width, out._2.name, "ready", "valid")
++			    for (out <- outputs) {
++				  var ttype = ""; var tcast = ""
++				   out._2 match {
++					case outUBool: Bool => ttype = "bool"; tcast = ".to_ulong()"
++					case outSInt: SInt => ttype = "sc_int<" + out._2.width + ">";  tcast = ".to_ulong()"
++					//Bits is implemented as UInt
++					case outUInt: UInt => ttype = "sc_uint<" + out._2.width + ">"; tcast = ".to_ulong()"
++				  }
++				  val vtype = ttype; val vcast = tcast
++                  val entry = new CEntry(name, false, vtype, vcast, out._2.width, out._2.name, "ready", "valid")
+                   cdef.entries += (entry)
+ 				}
+-                //val aName = "cs_" + aggregate.name + "_o"
+-                //cdef.structs(aName) = new CStruct(aName, outputs)
+-                //val entry = new CEntry(name, false, aName, 1, aggregate.name, delt.ready.name, delt.valid.name)
+               }
+ 			  cdef.valid_ready = true
+             }
+             case _ => badElements(name) = elt
+           }
+         }
+-        case bits: Bits => {
+-          val is_input = bits.dir == INPUT
+-          val vtype = "dat_t<" + bits.width + ">" // direct use of width here?
+-          val entry = new CEntry(name, is_input, vtype, bits.width, bits.name, "ready", "valid")
++        case bool: Bool => {
++          val is_input = bool.dir == INPUT
++          val vtype = "bool"; var tcast = ""
++		  if (is_input) { tcast = "" }
++		  else { tcast = ".to_ulong()" }
++		  val vcast = tcast
++          val entry = new CEntry(name, is_input, vtype, vcast, bool.width, bool.name, "ready", "valid")
++          cdef.entries += (entry)
++		  cdef.valid_ready = false
++        }
++        case sint: SInt => {
++          val is_input = sint.dir == INPUT
++          val vtype = "sc_int<" + sint.width + ">"; var tcast = ""
++		  if (is_input) { tcast = ".to_uint64()" }
++		  else { tcast = ".to_ulong()" }
++		  val vcast = tcast
++          val entry = new CEntry(name, is_input, vtype, vcast, sint.width, sint.name, "ready", "valid")
++          cdef.entries += (entry)
++		  cdef.valid_ready = false
++        }
++		//Bits is implemented as UInt
++        case uint: UInt => {
++          val is_input = uint.dir == INPUT
++          val vtype = "sc_uint<" + uint.width + ">"; var tcast = ""
++		  if (is_input) { tcast = ".to_uint64()" }
++		  else { tcast = ".to_ulong()" }
++		  val vcast = tcast
++          val entry = new CEntry(name, is_input, vtype, vcast, uint.width, uint.name, "ready", "valid")
+           cdef.entries += (entry)
+ 		  cdef.valid_ready = false
+         }
+-- 
+2.1.0
+
diff --git a/patches/20150902/0007-Updated-SCWrapper.scala.-Cheked-Chisel-generation-fo.patch b/patches/20150902/0007-Updated-SCWrapper.scala.-Cheked-Chisel-generation-fo.patch
new file mode 100644
index 00000000..3389b851
--- /dev/null
+++ b/patches/20150902/0007-Updated-SCWrapper.scala.-Cheked-Chisel-generation-fo.patch
@@ -0,0 +1,28 @@
+From 6097f4bf7e38d2d79a4e7747fa6fd99e585ef046 Mon Sep 17 00:00:00 2001
+From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
+Date: Wed, 2 Sep 2015 10:12:32 -0300
+Subject: [PATCH 7/7] Updated SCWrapper.scala. Cheked Chisel generation for
+ Decoupled and non-Decoupled signals -> all works fine.
+
+---
+ src/main/scala/SCWrapper.scala | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/src/main/scala/SCWrapper.scala b/src/main/scala/SCWrapper.scala
+index e5d2993..8b11632 100644
+--- a/src/main/scala/SCWrapper.scala
++++ b/src/main/scala/SCWrapper.scala
+@@ -134,8 +134,8 @@ object SCWrapper {
+ 	  if (c.valid_ready == true){
+ 		sctor_list += ", %s__io_in_ready(\"%s__io_in_ready\")\n  ".format(c.name, c.name)
+ 		sctor_list += ", %s__io_out_valid(\"%s__io_out_valid\")".format(c.name, c.name)
+-		output_ports += "sc_out<sc_bv<1> > %s__io_in_ready;\n  ".format(c.name)
+-		output_ports += "sc_out<sc_bv<1> > %s__io_out_valid;\n  ".format(c.name)
++		output_ports += "sc_out<bool > %s__io_in_ready;\n  ".format(c.name)
++		output_ports += "sc_out<bool > %s__io_out_valid;\n  ".format(c.name)
+ 		input_thread += "c->%s__io_in_valid = set;\n    ".format(c.name)
+ 		input_thread += "c->%s__io_out_ready = set;\n    ".format(c.name)
+ 		output_thread += "%s__io_out_valid->write(c->%s__io_out_valid.to_ulong());\n    ".format(c.name, c.name)
+-- 
+2.1.0
+
diff --git a/patches/20150902/chisel_systemc_backend_patch.tar.gz b/patches/20150902/chisel_systemc_backend_patch.tar.gz
new file mode 100644
index 0000000000000000000000000000000000000000..95fb0cd7bf194f47905c20d146177880c47891bf
GIT binary patch
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xF?xVi$z^neRT(FQRgGwpF^y?VV;a+##x$lejcH6{8q?cO{{czM>^T6)001RIbY}nn

literal 0
HcmV?d00001


From 5817ea8b51bdee72c54ced392d9d9d2a7f993ccb Mon Sep 17 00:00:00 2001
From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
Date: Wed, 2 Sep 2015 16:41:27 -0300
Subject: [PATCH 09/15] Changed SystemC templates: uses one thread.

---
 src/main/resources/template_cpp.txt | 7 +------
 src/main/resources/template_h.txt   | 8 +++-----
 2 files changed, 4 insertions(+), 11 deletions(-)

diff --git a/src/main/resources/template_cpp.txt b/src/main/resources/template_cpp.txt
index 13f60767..492fd162 100644
--- a/src/main/resources/template_cpp.txt
+++ b/src/main/resources/template_cpp.txt
@@ -1,16 +1,11 @@
 #include "{!name!}.h"
 
-void {!name!}::input_thread(void){
+void {!name!}::component_thread(void){
   while(true){
     {!input_thread!}
     //Clock Lo
     c->clock_lo(reset);
-    wait(Step);
-  }
-}
 
-void {!name!}::output_thread(void){
-  while(true){
     {!output_thread!}
     //Clock Hi
     c->clock_hi(reset);
diff --git a/src/main/resources/template_h.txt b/src/main/resources/template_h.txt
index 020ac13e..b90b9281 100644
--- a/src/main/resources/template_h.txt
+++ b/src/main/resources/template_h.txt
@@ -30,7 +30,7 @@ SC_MODULE({!name!}){
     // Initialize Component, Clock in RESET
     c = new {!component_type!}();
     c->init();
-    Step = Step/2;
+    Step = Step;
 
     // Clock Initialization? Don't understand what this is for. Copied from emulator.
     for(int i = 0; i < 5; i++) {
@@ -39,12 +39,10 @@ SC_MODULE({!name!}){
     }
 
     //Register Thread
-    SC_THREAD(input_thread);
-    SC_THREAD(output_thread);
+    SC_THREAD(component_thread);
   }
 
-  void input_thread(void);
-  void output_thread(void);
+  void component_thread(void);
 
   dat_t<1> reset = LIT<1>(0);
   dat_t<1> set = LIT<1>(1);

From 2112ffe95c9702d6b4f71d3773ab5ce124b5e20f Mon Sep 17 00:00:00 2001
From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
Date: Wed, 16 Sep 2015 18:33:50 -0300
Subject: [PATCH 10/15] Version that compiles and recognizes the HTIFIO class,
 but as a new type (only for test).

---
 src/main/scala/ChiselUtil.scala         |  29 ++++
 src/main/scala/SCWrapper.scala          |  17 ++-
 src/main/scala/SysC.scala               | 171 ++++++++++++++++++------
 src/test/scala/SysCTest/FullAdder.scala |   7 +-
 4 files changed, 176 insertions(+), 48 deletions(-)

diff --git a/src/main/scala/ChiselUtil.scala b/src/main/scala/ChiselUtil.scala
index ac19068b..0c9108b9 100644
--- a/src/main/scala/ChiselUtil.scala
+++ b/src/main/scala/ChiselUtil.scala
@@ -32,6 +32,35 @@ package Chisel
 import scala.math.{ceil, floor, log}
 import scala.collection.mutable.ArrayBuffer
 
+//-------------------------------------------------------------------------[byCAP
+// Moved from riscv-sodor/src/common/htif.scala
+// is it a good idea? not, but for now ...
+// the best way is creating Interfaces
+class CSRReq(addr_width: Int) extends Bundle
+{
+   val rw = Bool()
+   val addr = Bits(width = addr_width)
+   val data = Bits(width = 64)
+   override def clone = { new CSRReq(addr_width).asInstanceOf[this.type] }
+}
+
+class HTIFIO() extends Bundle
+{
+   val reset = Bool(INPUT)
+   val debug_stats_csr = Bool(OUTPUT)
+   val id = UInt(INPUT, 1)
+   val csr_req = Decoupled(new CSRReq(addr_width = 12)).flip
+   val csr_rep = Decoupled(Bits(width = 64))
+   // inter-processor interrupts. Not really necessary for Sodor.
+   val ipi_req = Decoupled(Bits(width = 1))
+   val ipi_rep = Decoupled(Bool()).flip
+   
+   val mem_req = Decoupled(new CSRReq(addr_width = 64)).flip
+   val mem_rep = Valid(Bits(width = 64))
+}
+//-------------------------------------------------------------------------byCAP]
+
+
 /** Compute the log2 rounded up with min value of 1 */
 object log2Up
 {
diff --git a/src/main/scala/SCWrapper.scala b/src/main/scala/SCWrapper.scala
index 8b11632a..1baaba24 100644
--- a/src/main/scala/SCWrapper.scala
+++ b/src/main/scala/SCWrapper.scala
@@ -132,16 +132,21 @@ object SCWrapper {
         }
       }
 	  if (c.valid_ready == true){
-		sctor_list += ", %s__io_in_ready(\"%s__io_in_ready\")\n  ".format(c.name, c.name)
+		sctor_list += ", %s__io_in_valid(\"%s__io_in_valid\")".format(c.name, c.name)
+		sctor_list += ", %s__io_out_ready(\"%s__io_out_ready\")\n  ".format(c.name, c.name)
 		sctor_list += ", %s__io_out_valid(\"%s__io_out_valid\")".format(c.name, c.name)
-		output_ports += "sc_out<bool > %s__io_in_ready;\n  ".format(c.name)
+		sctor_list += ", %s__io_in_ready(\"%s__io_in_ready\")\n  ".format(c.name, c.name)
+
+		input_ports += "sc_in<bool > %s__io_in_valid;\n  ".format(c.name)
+		input_ports += "sc_in<bool > %s__io_out_ready;\n  ".format(c.name)
 		output_ports += "sc_out<bool > %s__io_out_valid;\n  ".format(c.name)
-		input_thread += "c->%s__io_in_valid = set;\n    ".format(c.name)
-		input_thread += "c->%s__io_out_ready = set;\n    ".format(c.name)
+		output_ports += "sc_out<bool > %s__io_in_ready;\n  ".format(c.name)
+		input_thread += "c->%s__io_in_valid = LIT<1>(%s__io_in_valid->read());\n    ".format(c.name, c.name)
+		input_thread += "c->%s__io_out_ready = LIT<1>(%s__io_out_ready->read());\n    ".format(c.name, c.name)
+
+
 		output_thread += "%s__io_out_valid->write(c->%s__io_out_valid.to_ulong());\n    ".format(c.name, c.name)
 		output_thread += "%s__io_in_ready->write(c->%s__io_in_ready.to_ulong());\n    ".format(c.name, c.name)
-		output_thread += "c->%s__io_in_valid = reset;\n    ".format(c.name)
-		output_thread += "c->%s__io_out_ready = reset;".format(c.name)
 	  }
       replacements += (("input_ports", input_ports))
       replacements += (("output_ports", output_ports))
diff --git a/src/main/scala/SysC.scala b/src/main/scala/SysC.scala
index ce94c1a3..dea2a7ea 100644
--- a/src/main/scala/SysC.scala
+++ b/src/main/scala/SysC.scala
@@ -30,7 +30,6 @@
 
 package Chisel
 
-
 class SysCBackend extends CppBackend {
    override def elaborate(c: Module): Unit = {
       super.elaborate(c)
@@ -49,83 +48,177 @@ class SysCBackend extends CppBackend {
             case bits: Bits => {
               val is_input = bits.dir == INPUT
               val vtype = "sc_uint<" + bits.width + ">"; var tcast = ""
-			  if (is_input) { tcast = ".to_uint64()" }
-			  else { tcast = ".to_ulong()" }
-			  val vcast = tcast
+              if (is_input) { tcast = ".to_uint64()" }
+              else { tcast = ".to_ulong()" }
+              val vcast = tcast
               val entry = new CEntry(name, is_input, vtype, vcast, bits.width, bits.name, delt.ready.name, delt.valid.name)
               cdef.entries += (entry)
-			  cdef.valid_ready = true
+              cdef.valid_ready = true
             }
             case aggregate: Aggregate => {
               // Collect all the inputs and outputs.
               val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
               if (inputs.length > 0) {
-			    for (in <- inputs) {
-				  var ttype = ""; var tcast = ""
-				   in._2 match {
-					case inUBool: Bool => ttype = "bool"; tcast = ""
-					case inSInt: SInt => ttype = "sc_int<" + in._2.width + ">";  tcast = ".to_uint64()"
-					//Bits is implemented as UInt
-					case inUInt: UInt => ttype = "sc_uint<" + in._2.width + ">"; tcast = ".to_uint64()"
-				  }
-				  val vtype = ttype; val vcast = tcast
+                for (in <- inputs) {
+                  var ttype = ""; var tcast = ""
+                   in._2 match {
+                    case inBool: Bool => ttype = "bool"; tcast = ""
+                    case inSInt: SInt => ttype = "sc_int<" + in._2.width + ">";  tcast = ".to_uint64()"
+                    //Bits is implemented as UInt
+                    case inUInt: UInt => ttype = "sc_uint<" + in._2.width + ">"; tcast = ".to_uint64()"
+                  }
+                  val vtype = ttype; val vcast = tcast
                   val entry = new CEntry(name, true, vtype, vcast, in._2.width, in._2.name, "ready", "valid")
                   cdef.entries += (entry)
-				}
+                }
               }
               val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
               if (outputs.length > 0) {
-			    for (out <- outputs) {
-				  var ttype = ""; var tcast = ""
-				   out._2 match {
-					case outUBool: Bool => ttype = "bool"; tcast = ".to_ulong()"
-					case outSInt: SInt => ttype = "sc_int<" + out._2.width + ">";  tcast = ".to_ulong()"
-					//Bits is implemented as UInt
-					case outUInt: UInt => ttype = "sc_uint<" + out._2.width + ">"; tcast = ".to_ulong()"
-				  }
-				  val vtype = ttype; val vcast = tcast
+                for (out <- outputs) {
+                  var ttype = ""; var tcast = ""
+                   out._2 match {
+                    case outBool: Bool => ttype = "bool"; tcast = ".to_ulong()"
+                    case outSInt: SInt => ttype = "sc_int<" + out._2.width + ">";  tcast = ".to_ulong()"
+                    //Bits is implemented as UInt
+                    case outUInt: UInt => ttype = "sc_uint<" + out._2.width + ">"; tcast = ".to_ulong()"
+                  }
+                  val vtype = ttype; val vcast = tcast
                   val entry = new CEntry(name, false, vtype, vcast, out._2.width, out._2.name, "ready", "valid")
                   cdef.entries += (entry)
-				}
+                }
               }
-			  cdef.valid_ready = true
+              cdef.valid_ready = true
             }
             case _ => badElements(name) = elt
           }
         }
+        case velt:ValidIO[_] => println("************ ValidIO detected! ************")
+
         case bool: Bool => {
           val is_input = bool.dir == INPUT
           val vtype = "bool"; var tcast = ""
-		  if (is_input) { tcast = "" }
-		  else { tcast = ".to_ulong()" }
-		  val vcast = tcast
+          if (is_input) { tcast = "" }
+          else { tcast = ".to_ulong()" }
+          val vcast = tcast
           val entry = new CEntry(name, is_input, vtype, vcast, bool.width, bool.name, "ready", "valid")
           cdef.entries += (entry)
-		  cdef.valid_ready = false
+          cdef.valid_ready = false
         }
         case sint: SInt => {
           val is_input = sint.dir == INPUT
           val vtype = "sc_int<" + sint.width + ">"; var tcast = ""
-		  if (is_input) { tcast = ".to_uint64()" }
-		  else { tcast = ".to_ulong()" }
-		  val vcast = tcast
+          if (is_input) { tcast = ".to_uint64()" }
+          else { tcast = ".to_ulong()" }
+          val vcast = tcast
           val entry = new CEntry(name, is_input, vtype, vcast, sint.width, sint.name, "ready", "valid")
           cdef.entries += (entry)
-		  cdef.valid_ready = false
+          cdef.valid_ready = false
         }
-		//Bits is implemented as UInt
+        //Bits is implemented as UInt
         case uint: UInt => {
           val is_input = uint.dir == INPUT
           val vtype = "sc_uint<" + uint.width + ">"; var tcast = ""
-		  if (is_input) { tcast = ".to_uint64()" }
-		  else { tcast = ".to_ulong()" }
-		  val vcast = tcast
+          if (is_input) { tcast = ".to_uint64()" }
+          else { tcast = ".to_ulong()" }
+          val vcast = tcast
           val entry = new CEntry(name, is_input, vtype, vcast, uint.width, uint.name, "ready", "valid")
           cdef.entries += (entry)
-		  cdef.valid_ready = false
+          cdef.valid_ready = false
+        }
+        case belt: Bundle => {
+          val mid_bundle = c.io.asInstanceOf[Bundle]
+          for ((bname, belt) <- mid_bundle.elements){
+            belt match{
+              case delt:DecoupledIO[_] => {
+                delt.bits match {
+                  case bits: Bits => {
+                    val is_input = bits.dir == INPUT
+                    val vtype = "sc_uint<" + bits.width + ">"; var tcast = ""
+                    if (is_input) { tcast = ".to_uint64()" }
+                    else { tcast = ".to_ulong()" }
+                    val vcast = tcast
+                    val entry = new CEntry(bname, is_input, vtype, vcast, bits.width, bits.name, delt.ready.name, delt.valid.name)
+                    cdef.entries += (entry)
+                    cdef.valid_ready = true
+                  }
+                  case aggregate: Aggregate => {
+                    // Collect all the inputs and outputs.
+                    val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
+                    if (inputs.length > 0) {
+                      for (in <- inputs) {
+                        var ttype = ""; var tcast = ""
+                         in._2 match {
+                          case inBool: Bool => ttype = "bool"; tcast = ""
+                          case inSInt: SInt => ttype = "sc_int<" + in._2.width + ">";  tcast = ".to_uint64()"
+                          //Bits is implemented as UInt
+                          case inUInt: UInt => ttype = "sc_uint<" + in._2.width + ">"; tcast = ".to_uint64()"
+                        }
+                        val vtype = ttype; val vcast = tcast
+                        val entry = new CEntry(bname, true, vtype, vcast, in._2.width, in._2.name, "ready", "valid")
+                        cdef.entries += (entry)
+                      }
+                    }
+                    val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
+                    if (outputs.length > 0) {
+                      for (out <- outputs) {
+                        var ttype = ""; var tcast = ""
+                         out._2 match {
+                          case outBool: Bool => ttype = "bool"; tcast = ".to_ulong()"
+                          case outSInt: SInt => ttype = "sc_int<" + out._2.width + ">";  tcast = ".to_ulong()"
+                          //Bits is implemented as UInt
+                          case outUInt: UInt => ttype = "sc_uint<" + out._2.width + ">"; tcast = ".to_ulong()"
+                        }
+                        val vtype = ttype; val vcast = tcast
+                        val entry = new CEntry(bname, false, vtype, vcast, out._2.width, out._2.name, "ready", "valid")
+                        cdef.entries += (entry)
+                      }
+                    }
+                    cdef.valid_ready = true
+                  }
+                  case _ => badElements(bname) = belt
+                }
+              }
+              case bool: Bool => {
+                val is_input = bool.dir == INPUT
+                val vtype = "bool"; var tcast = ""
+                if (is_input) { tcast = "" }
+                else { tcast = ".to_ulong()" }
+                val vcast = tcast
+                val entry = new CEntry(bname, is_input, vtype, vcast, bool.width, bool.name, "ready", "valid")
+                cdef.entries += (entry)
+                cdef.valid_ready = false
+              }
+              case sint: SInt => {
+                val is_input = sint.dir == INPUT
+                val vtype = "sc_int<" + sint.width + ">"; var tcast = ""
+                if (is_input) { tcast = ".to_uint64()" }
+                else { tcast = ".to_ulong()" }
+                val vcast = tcast
+                val entry = new CEntry(bname, is_input, vtype, vcast, sint.width, sint.name, "ready", "valid")
+                cdef.entries += (entry)
+                cdef.valid_ready = false
+              }
+              //Bits is implemented as UInt
+              case uint: UInt => {
+                val is_input = uint.dir == INPUT
+                val vtype = "sc_uint<" + uint.width + ">"; var tcast = ""
+                if (is_input) { tcast = ".to_uint64()" }
+                else { tcast = ".to_ulong()" }
+                val vcast = tcast
+                val entry = new CEntry(bname, is_input, vtype, vcast, uint.width, uint.name, "ready", "valid")
+                cdef.entries += (entry)
+                cdef.valid_ready = false
+              }
+              case htif: HTIFIO => {
+                println("************ HTIFIO detected! ************")
+              }
+              case _ => badElements(bname) = belt
+            }
+          }
         }
         case _ => badElements(name) = elt
       }
+
     }
 
     if (badElements.size > 0) {
diff --git a/src/test/scala/SysCTest/FullAdder.scala b/src/test/scala/SysCTest/FullAdder.scala
index 28d73f2b..1e14a314 100644
--- a/src/test/scala/SysCTest/FullAdder.scala
+++ b/src/test/scala/SysCTest/FullAdder.scala
@@ -63,9 +63,6 @@ class FullAdderTests(c: FullAdder) extends Tester(c) {
     val a    = rnd.nextInt(2)
     val b    = rnd.nextInt(2)
     val cin  = rnd.nextInt(2)
-    val res  = a + b + cin
-    val sum  = res & 1
-    val cout = (res >> 1) & 1
     var transfer = false
     poke(c.io.in.valid, 0)
     poke(c.io.out.ready, 0)
@@ -81,6 +78,10 @@ class FullAdderTests(c: FullAdder) extends Tester(c) {
     poke(c.io.in.valid, 1)
     poke(c.io.out.ready, 1)
 
+    val res  = a + b + cin
+    val sum  = res & 1
+    val cout = (res >> 1) & 1
+
     do {
       transfer = (peek(c.io.out.valid) == 1)
       step(1)

From 7a25b779bfc1bd8640160b4ab2f7d235c76114d6 Mon Sep 17 00:00:00 2001
From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
Date: Mon, 28 Sep 2015 10:06:22 -0300
Subject: [PATCH 11/15] Updadted {SysC,SCWWrapper}.scala to suport ValidIO,
 DecoupledIO and HTIFIO.

---
 src/main/scala/SCWrapper.scala |  52 +++--
 src/main/scala/SysC.scala      | 396 ++++++++++++++++++++++-----------
 2 files changed, 299 insertions(+), 149 deletions(-)

diff --git a/src/main/scala/SCWrapper.scala b/src/main/scala/SCWrapper.scala
index 1baaba24..5c99ea96 100644
--- a/src/main/scala/SCWrapper.scala
+++ b/src/main/scala/SCWrapper.scala
@@ -110,7 +110,7 @@ object SCWrapper {
     /*begin*/{
       var input_ports = ""
       var output_ports = ""
-	  var sctor_list = ""
+	    var sctor_list = ""
       var input_thread = ""
       var output_thread = ""
 
@@ -131,23 +131,27 @@ object SCWrapper {
           output_thread += thread_out
         }
       }
-	  if (c.valid_ready == true){
-		sctor_list += ", %s__io_in_valid(\"%s__io_in_valid\")".format(c.name, c.name)
-		sctor_list += ", %s__io_out_ready(\"%s__io_out_ready\")\n  ".format(c.name, c.name)
-		sctor_list += ", %s__io_out_valid(\"%s__io_out_valid\")".format(c.name, c.name)
-		sctor_list += ", %s__io_in_ready(\"%s__io_in_ready\")\n  ".format(c.name, c.name)
-
-		input_ports += "sc_in<bool > %s__io_in_valid;\n  ".format(c.name)
-		input_ports += "sc_in<bool > %s__io_out_ready;\n  ".format(c.name)
-		output_ports += "sc_out<bool > %s__io_out_valid;\n  ".format(c.name)
-		output_ports += "sc_out<bool > %s__io_in_ready;\n  ".format(c.name)
-		input_thread += "c->%s__io_in_valid = LIT<1>(%s__io_in_valid->read());\n    ".format(c.name, c.name)
-		input_thread += "c->%s__io_out_ready = LIT<1>(%s__io_out_ready->read());\n    ".format(c.name, c.name)
-
-
-		output_thread += "%s__io_out_valid->write(c->%s__io_out_valid.to_ulong());\n    ".format(c.name, c.name)
-		output_thread += "%s__io_in_ready->write(c->%s__io_in_ready.to_ulong());\n    ".format(c.name, c.name)
-	  }
+	    if (c.valid_ready == 1 || c.valid_ready == 2){  // 1= only valid signal -> ValidIO
+		    sctor_list += ", %s__io_in_valid(\"%s__io_in_valid\")\n  ".format(c.name, c.name)
+		    sctor_list += ", %s__io_out_valid(\"%s__io_out_valid\")\n  ".format(c.name, c.name)
+
+		    input_ports += "sc_in<bool > %s__io_in_valid;\n  ".format(c.name)
+		    output_ports += "sc_out<bool > %s__io_out_valid;\n  ".format(c.name)
+		    input_thread += "c->%s__io_in_valid = LIT<1>(%s__io_in_valid->read());\n    ".format(c.name, c.name)
+
+		    output_thread += "%s__io_out_valid->write(c->%s__io_out_valid.to_ulong());\n    ".format(c.name, c.name)
+	    }
+	    if (c.valid_ready == 2){  // 2= both valid & ready signals -> DecoupledIO
+		    sctor_list += ", %s__io_out_ready(\"%s__io_out_ready\")\n  ".format(c.name, c.name)
+		    sctor_list += ", %s__io_in_ready(\"%s__io_in_ready\")\n  ".format(c.name, c.name)
+
+		    input_ports += "sc_in<bool > %s__io_out_ready;\n  ".format(c.name)
+		    output_ports += "sc_out<bool > %s__io_in_ready;\n  ".format(c.name)
+		    input_thread += "c->%s__io_out_ready = LIT<1>(%s__io_out_ready->read());\n    ".format(c.name, c.name)
+
+		    output_thread += "%s__io_in_ready->write(c->%s__io_in_ready.to_ulong());\n    ".format(c.name, c.name)
+
+      }
       replacements += (("input_ports", input_ports))
       replacements += (("output_ports", output_ports))
       replacements += (("sctor_list", sctor_list))
@@ -220,11 +224,11 @@ object SCWrapper {
     /*Check Output Queues*/{
       //Pull out output ports
       val ports = ArrayBuffer[CEntry]()
-          for (e <- c.entries) {
-            if(!e.is_input) {
-              ports += e
-            }
-          }
+      for (e <- c.entries) {
+        if(!e.is_input) {
+          ports += e
+        }
+      }
       //Check
       var check = ""
       var valid_output = "";
@@ -368,7 +372,7 @@ class CEntry(a_name: String, input: Boolean, a_type: String, a_cast: String, a_w
 class ComponentDef(a_type: String, a_name: String) {
   val ctype: String = a_type
   val name: String = a_name
-  var valid_ready: Boolean = false
+  var valid_ready: Int = 0
   val entries = ArrayBuffer[CEntry]()
   val structs = scala.collection.mutable.LinkedHashMap[String, CStruct]()
 
diff --git a/src/main/scala/SysC.scala b/src/main/scala/SysC.scala
index dea2a7ea..76459d69 100644
--- a/src/main/scala/SysC.scala
+++ b/src/main/scala/SysC.scala
@@ -31,194 +31,340 @@
 package Chisel
 
 class SysCBackend extends CppBackend {
-   override def elaborate(c: Module): Unit = {
+    def bool_fun (name: String, bool: Bool): CEntry = {
+      val is_input = bool.dir == INPUT
+      val vtype = "bool"; var tcast = ""
+      if (is_input) { tcast = "" }
+      else { tcast = ".to_ulong()" }
+      val vcast = tcast
+      val entry = new CEntry(name, is_input, vtype, vcast, bool.width, bool.name, "ready", "valid")
+      entry
+    }
+    def sint_fun (name: String, sint: SInt): CEntry = {
+      val is_input = sint.dir == INPUT
+      val vtype = "sc_int<" + sint.width + ">"; var tcast = ""
+      if (is_input) { tcast = ".to_uint64()" }
+      else { tcast = ".to_ulong()" }
+      val vcast = tcast
+      val entry = new CEntry(name, is_input, vtype, vcast, sint.width, sint.name, "ready", "valid")
+      entry
+    }
+    // UInt: Bits is a virtual UInt class
+    def uint_fun (name: String, uint: UInt): CEntry = {
+      val is_input = uint.dir == INPUT
+      val vtype = "sc_uint<" + uint.width + ">"; var tcast = ""
+      if (is_input) { tcast = ".to_uint64()" }
+      else { tcast = ".to_ulong()" }
+      val vcast = tcast
+      val entry = new CEntry(name, is_input, vtype, vcast, uint.width, uint.name, "ready", "valid")
+      entry
+    }
+    // Used for Decoupled type
+    def bits_fun (name: String, bits: Bits, ready_name: String, valid_name: String): CEntry = {
+      val is_input = bits.dir == INPUT
+      val vtype = "sc_uint<" + bits.width + ">"; var tcast = ""
+      if (is_input) { tcast = ".to_uint64()" }
+      else { tcast = ".to_ulong()" }
+      val vcast = tcast
+      val entry = new CEntry(name, is_input, vtype, vcast, bits.width, bits.name, ready_name, valid_name)
+      entry
+    }
+
+    override def elaborate(c: Module): Unit = {
       super.elaborate(c)
       println(c)
       println(c.name)
 
-      //Create component definition for System C
+    //Create component definition for System C
     val top_bundle = c.io.asInstanceOf[Bundle] //Is this safe?
     //  No, but it will throw an exception that should explain the issue reasonably
     val cdef = new ComponentDef(c.name + "_t", c.name)
     val badElements = scala.collection.mutable.HashMap[String, Data]()
     for ((name, elt) <- top_bundle.elements) {
       elt match {
+        case bool: Bool => {
+          val entry = bool_fun(name, bool)
+          cdef.entries += (entry)
+          cdef.valid_ready = 0
+        }
+        case sint: SInt => {
+          val entry = sint_fun(name, sint)
+          cdef.entries += (entry)
+          cdef.valid_ready = 0
+        }
+        // UInt & Bits
+        case uint: UInt => {
+          val entry = uint_fun(name, uint)
+          cdef.entries += (entry)
+          cdef.valid_ready = 0
+        }
+
+        case velt:ValidIO[_] => {
+          velt.bits match {
+            case bits: Bits => {
+              val entry = bits_fun(name, bits, "ready", velt.valid.name)
+              cdef.entries += (entry)
+              cdef.valid_ready = 1
+            }
+            case aggregate: Aggregate => {
+              // Collect all the inputs and outputs.
+              val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
+              if (inputs.length > 0) {
+                for (in <- inputs) {
+                  in._2 match {
+                    case inBool: Bool => {
+                      val entry = bool_fun(name, inBool)
+                      cdef.entries += (entry)
+                      cdef.valid_ready = 1
+                    }
+                    case inSInt: SInt => {
+                      val entry = sint_fun(name, inSInt)
+                      cdef.entries += (entry)
+                      cdef.valid_ready = 1
+                    }
+                    //Also used for Bits
+                    case inUInt: UInt => {
+                      val entry = uint_fun(name, inUInt)
+                      cdef.entries += (entry)
+                      cdef.valid_ready = 1
+                    }
+                  }
+                }
+              }
+              val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
+              if (outputs.length > 0) {
+                for (out <- outputs) {
+                   out._2 match {
+                    case inBool: Bool => {
+                      val entry = bool_fun(name, inBool)
+                      cdef.entries += (entry)
+                      cdef.valid_ready = 1
+                    }
+                    case inSInt: SInt => {
+                      val entry = sint_fun(name, inSInt)
+                      cdef.entries += (entry)
+                      cdef.valid_ready = 1
+                    }
+                    //Also used for Bits
+                    case inUInt: UInt => {
+                      val entry = uint_fun(name, inUInt)
+                      cdef.entries += (entry)
+                      cdef.valid_ready = 1
+                    }
+                  }
+                }
+              }
+            }
+            case _ => badElements(name) = elt
+          }
+        }
+
         case delt:DecoupledIO[_] => {
           delt.bits match {
             case bits: Bits => {
-              val is_input = bits.dir == INPUT
-              val vtype = "sc_uint<" + bits.width + ">"; var tcast = ""
-              if (is_input) { tcast = ".to_uint64()" }
-              else { tcast = ".to_ulong()" }
-              val vcast = tcast
-              val entry = new CEntry(name, is_input, vtype, vcast, bits.width, bits.name, delt.ready.name, delt.valid.name)
+              val entry = bits_fun(name, bits, delt.ready.name, delt.valid.name)
               cdef.entries += (entry)
-              cdef.valid_ready = true
+              cdef.valid_ready = 2
             }
             case aggregate: Aggregate => {
               // Collect all the inputs and outputs.
               val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
               if (inputs.length > 0) {
                 for (in <- inputs) {
-                  var ttype = ""; var tcast = ""
-                   in._2 match {
-                    case inBool: Bool => ttype = "bool"; tcast = ""
-                    case inSInt: SInt => ttype = "sc_int<" + in._2.width + ">";  tcast = ".to_uint64()"
-                    //Bits is implemented as UInt
-                    case inUInt: UInt => ttype = "sc_uint<" + in._2.width + ">"; tcast = ".to_uint64()"
+                  in._2 match {
+                    case inBool: Bool => {
+                      val entry = bool_fun(name, inBool)
+                      cdef.entries += (entry)
+                      cdef.valid_ready = 2
+                    }
+                    case inSInt: SInt => {
+                      val entry = sint_fun(name, inSInt)
+                      cdef.entries += (entry)
+                      cdef.valid_ready = 2
+                    }
+                    //Also used for Bits
+                    case inUInt: UInt => {
+                      val entry = uint_fun(name, inUInt)
+                      cdef.entries += (entry)
+                      cdef.valid_ready = 2
+                    }
                   }
-                  val vtype = ttype; val vcast = tcast
-                  val entry = new CEntry(name, true, vtype, vcast, in._2.width, in._2.name, "ready", "valid")
-                  cdef.entries += (entry)
                 }
               }
               val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
               if (outputs.length > 0) {
                 for (out <- outputs) {
-                  var ttype = ""; var tcast = ""
                    out._2 match {
-                    case outBool: Bool => ttype = "bool"; tcast = ".to_ulong()"
-                    case outSInt: SInt => ttype = "sc_int<" + out._2.width + ">";  tcast = ".to_ulong()"
-                    //Bits is implemented as UInt
-                    case outUInt: UInt => ttype = "sc_uint<" + out._2.width + ">"; tcast = ".to_ulong()"
+                    case inBool: Bool => {
+                      val entry = bool_fun(name, inBool)
+                      cdef.entries += (entry)
+                      cdef.valid_ready = 2
+                    }
+                    case inSInt: SInt => {
+                      val entry = sint_fun(name, inSInt)
+                      cdef.entries += (entry)
+                      cdef.valid_ready = 2
+                    }
+                    //Also used for Bits
+                    case inUInt: UInt => {
+                      val entry = uint_fun(name, inUInt)
+                      cdef.entries += (entry)
+                      cdef.valid_ready = 2
+                    }
                   }
-                  val vtype = ttype; val vcast = tcast
-                  val entry = new CEntry(name, false, vtype, vcast, out._2.width, out._2.name, "ready", "valid")
-                  cdef.entries += (entry)
                 }
               }
-              cdef.valid_ready = true
             }
             case _ => badElements(name) = elt
           }
         }
-        case velt:ValidIO[_] => println("************ ValidIO detected! ************")
 
-        case bool: Bool => {
-          val is_input = bool.dir == INPUT
-          val vtype = "bool"; var tcast = ""
-          if (is_input) { tcast = "" }
-          else { tcast = ".to_ulong()" }
-          val vcast = tcast
-          val entry = new CEntry(name, is_input, vtype, vcast, bool.width, bool.name, "ready", "valid")
-          cdef.entries += (entry)
-          cdef.valid_ready = false
-        }
-        case sint: SInt => {
-          val is_input = sint.dir == INPUT
-          val vtype = "sc_int<" + sint.width + ">"; var tcast = ""
-          if (is_input) { tcast = ".to_uint64()" }
-          else { tcast = ".to_ulong()" }
-          val vcast = tcast
-          val entry = new CEntry(name, is_input, vtype, vcast, sint.width, sint.name, "ready", "valid")
-          cdef.entries += (entry)
-          cdef.valid_ready = false
-        }
-        //Bits is implemented as UInt
-        case uint: UInt => {
-          val is_input = uint.dir == INPUT
-          val vtype = "sc_uint<" + uint.width + ">"; var tcast = ""
-          if (is_input) { tcast = ".to_uint64()" }
-          else { tcast = ".to_ulong()" }
-          val vcast = tcast
-          val entry = new CEntry(name, is_input, vtype, vcast, uint.width, uint.name, "ready", "valid")
-          cdef.entries += (entry)
-          cdef.valid_ready = false
-        }
-        case belt: Bundle => {
-          val mid_bundle = c.io.asInstanceOf[Bundle]
-          for ((bname, belt) <- mid_bundle.elements){
-            belt match{
+        case belt: HTIFIO => {
+          val htif_bundle = belt.asInstanceOf[Bundle]
+          for ((hname, helt) <- htif_bundle.elements){
+            helt match{
+              case bool: Bool => {
+                val entry = bool_fun(hname, bool)
+                cdef.entries += (entry)
+                cdef.valid_ready = 0
+              }
+              case sint: SInt => {
+                val entry = sint_fun(hname, sint)
+                cdef.entries += (entry)
+                cdef.valid_ready = 0
+              }
+              // UInt & Bits
+              case uint: UInt => {
+                val entry = uint_fun(hname, uint)
+                cdef.entries += (entry)
+                cdef.valid_ready = 0
+              }
+
+              case velt:ValidIO[_] => {
+                velt.bits match {
+                  case bits: Bits => {
+                    val entry = bits_fun(hname, bits, "ready", velt.valid.name)
+                    cdef.entries += (entry)
+                    cdef.valid_ready = 1
+                  }
+                  case aggregate: Aggregate => {
+                    // Collect all the inputs and outputs.
+                    val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
+                    if (inputs.length > 0) {
+                      for (in <- inputs) {
+                        in._2 match {
+                          case inBool: Bool => {
+                            val entry = bool_fun(hname, inBool)
+                            cdef.entries += (entry)
+                            cdef.valid_ready = 1
+                          }
+                          case inSInt: SInt => {
+                            val entry = sint_fun(hname, inSInt)
+                            cdef.entries += (entry)
+                            cdef.valid_ready = 1
+                          }
+                          //Also used for Bits
+                          case inUInt: UInt => {
+                            val entry = uint_fun(hname, inUInt)
+                            cdef.entries += (entry)
+                            cdef.valid_ready = 1
+                          }
+                        }
+                      }
+                    }
+                    val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
+                    if (outputs.length > 0) {
+                      for (out <- outputs) {
+                         out._2 match {
+                          case inBool: Bool => {
+                            val entry = bool_fun(hname, inBool)
+                            cdef.entries += (entry)
+                            cdef.valid_ready = 1
+                          }
+                          case inSInt: SInt => {
+                            val entry = sint_fun(hname, inSInt)
+                            cdef.entries += (entry)
+                            cdef.valid_ready = 1
+                          }
+                          //Also used for Bits
+                          case inUInt: UInt => {
+                            val entry = uint_fun(hname, inUInt)
+                            cdef.entries += (entry)
+                            cdef.valid_ready = 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                  case _ => badElements(hname) = elt
+                }
+              }
+
               case delt:DecoupledIO[_] => {
                 delt.bits match {
                   case bits: Bits => {
-                    val is_input = bits.dir == INPUT
-                    val vtype = "sc_uint<" + bits.width + ">"; var tcast = ""
-                    if (is_input) { tcast = ".to_uint64()" }
-                    else { tcast = ".to_ulong()" }
-                    val vcast = tcast
-                    val entry = new CEntry(bname, is_input, vtype, vcast, bits.width, bits.name, delt.ready.name, delt.valid.name)
+                    val entry = bits_fun(hname, bits, delt.ready.name, delt.valid.name)
                     cdef.entries += (entry)
-                    cdef.valid_ready = true
+                    cdef.valid_ready = 2
                   }
                   case aggregate: Aggregate => {
                     // Collect all the inputs and outputs.
                     val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
                     if (inputs.length > 0) {
                       for (in <- inputs) {
-                        var ttype = ""; var tcast = ""
-                         in._2 match {
-                          case inBool: Bool => ttype = "bool"; tcast = ""
-                          case inSInt: SInt => ttype = "sc_int<" + in._2.width + ">";  tcast = ".to_uint64()"
-                          //Bits is implemented as UInt
-                          case inUInt: UInt => ttype = "sc_uint<" + in._2.width + ">"; tcast = ".to_uint64()"
+                        in._2 match {
+                          case inBool: Bool => {
+                            val entry = bool_fun(hname, inBool)
+                            cdef.entries += (entry)
+                            cdef.valid_ready = 2
+                          }
+                          case inSInt: SInt => {
+                            val entry = sint_fun(hname, inSInt)
+                            cdef.entries += (entry)
+                            cdef.valid_ready = 2
+                          }
+                          //Also used for Bits
+                          case inUInt: UInt => {
+                            val entry = uint_fun(hname, inUInt)
+                            cdef.entries += (entry)
+                            cdef.valid_ready = 2
+                          }
                         }
-                        val vtype = ttype; val vcast = tcast
-                        val entry = new CEntry(bname, true, vtype, vcast, in._2.width, in._2.name, "ready", "valid")
-                        cdef.entries += (entry)
                       }
                     }
                     val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
                     if (outputs.length > 0) {
                       for (out <- outputs) {
-                        var ttype = ""; var tcast = ""
                          out._2 match {
-                          case outBool: Bool => ttype = "bool"; tcast = ".to_ulong()"
-                          case outSInt: SInt => ttype = "sc_int<" + out._2.width + ">";  tcast = ".to_ulong()"
-                          //Bits is implemented as UInt
-                          case outUInt: UInt => ttype = "sc_uint<" + out._2.width + ">"; tcast = ".to_ulong()"
+                          case inBool: Bool => {
+                            val entry = bool_fun(hname, inBool)
+                            cdef.entries += (entry)
+                            cdef.valid_ready = 2
+                          }
+                          case inSInt: SInt => {
+                            val entry = sint_fun(hname, inSInt)
+                            cdef.entries += (entry)
+                            cdef.valid_ready = 2
+                          }
+                          //Also used for Bits
+                          case inUInt: UInt => {
+                            val entry = uint_fun(hname, inUInt)
+                            cdef.entries += (entry)
+                            cdef.valid_ready = 2
+                          }
                         }
-                        val vtype = ttype; val vcast = tcast
-                        val entry = new CEntry(bname, false, vtype, vcast, out._2.width, out._2.name, "ready", "valid")
-                        cdef.entries += (entry)
                       }
                     }
-                    cdef.valid_ready = true
                   }
-                  case _ => badElements(bname) = belt
+                  case _ => badElements(hname) = helt
                 }
               }
-              case bool: Bool => {
-                val is_input = bool.dir == INPUT
-                val vtype = "bool"; var tcast = ""
-                if (is_input) { tcast = "" }
-                else { tcast = ".to_ulong()" }
-                val vcast = tcast
-                val entry = new CEntry(bname, is_input, vtype, vcast, bool.width, bool.name, "ready", "valid")
-                cdef.entries += (entry)
-                cdef.valid_ready = false
-              }
-              case sint: SInt => {
-                val is_input = sint.dir == INPUT
-                val vtype = "sc_int<" + sint.width + ">"; var tcast = ""
-                if (is_input) { tcast = ".to_uint64()" }
-                else { tcast = ".to_ulong()" }
-                val vcast = tcast
-                val entry = new CEntry(bname, is_input, vtype, vcast, sint.width, sint.name, "ready", "valid")
-                cdef.entries += (entry)
-                cdef.valid_ready = false
-              }
-              //Bits is implemented as UInt
-              case uint: UInt => {
-                val is_input = uint.dir == INPUT
-                val vtype = "sc_uint<" + uint.width + ">"; var tcast = ""
-                if (is_input) { tcast = ".to_uint64()" }
-                else { tcast = ".to_ulong()" }
-                val vcast = tcast
-                val entry = new CEntry(bname, is_input, vtype, vcast, uint.width, uint.name, "ready", "valid")
-                cdef.entries += (entry)
-                cdef.valid_ready = false
-              }
-              case htif: HTIFIO => {
-                println("************ HTIFIO detected! ************")
-              }
-              case _ => badElements(bname) = belt
+              case _ => badElements(hname) = helt
             }
           }
         }
         case _ => badElements(name) = elt
       }
-
     }
 
     if (badElements.size > 0) {

From ec1cf1bb3777381dfe9506423a0fb999be55c7b9 Mon Sep 17 00:00:00 2001
From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
Date: Wed, 7 Oct 2015 09:37:03 -0300
Subject: [PATCH 12/15] Updated HTIFIO support.

---
 src/main/scala/SCWrapper.scala |  47 +++++++------
 src/main/scala/SysC.scala      | 116 ++++++++++++---------------------
 2 files changed, 67 insertions(+), 96 deletions(-)

diff --git a/src/main/scala/SCWrapper.scala b/src/main/scala/SCWrapper.scala
index 5c99ea96..67678872 100644
--- a/src/main/scala/SCWrapper.scala
+++ b/src/main/scala/SCWrapper.scala
@@ -113,6 +113,7 @@ object SCWrapper {
 	    var sctor_list = ""
       var input_thread = ""
       var output_thread = ""
+      var fname = ""
 
       for( e <- c.entries) {
         val decl_in  = "sc_in<%s > %s;\n  ".format(e.ctype, e.data)
@@ -130,28 +131,32 @@ object SCWrapper {
           sctor_list += ", %s(\"%s\")\n  ".format(e.data, e.data)
           output_thread += thread_out
         }
+        // Generate ready and valid signals when necessary
+        if (e.name != fname){
+          fname = e.name
+          if (e.valid != ""){
+		        sctor_list += ", %s(\"%s\")\n  ".format(e.valid, e.valid)
+            if(e.is_input){
+  		        input_ports += "sc_in<bool > %s;\n  ".format(e.valid)
+  		        input_thread += "c->%s = LIT<1>(%s->read());\n    ".format(e.valid, e.valid)
+            }else{
+		          output_ports += "sc_out<bool > %s;\n  ".format(e.valid)
+  		        output_thread += "%s->write(c->%s.to_ulong());\n    ".format(e.valid, e.valid)
+            }
+            if (e.ready != ""){
+  		        sctor_list += ", %s(\"%s\")\n  ".format(e.ready, e.ready)
+              if(e.is_input){
+    		        input_ports += "sc_in<bool > %s;\n  ".format(e.ready)
+    		        input_thread += "c->%s = LIT<1>(%s->read());\n    ".format(e.ready, e.ready)
+              }else{
+		            output_ports += "sc_out<bool > %s;\n  ".format(e.ready)
+    		        output_thread += "%s->write(c->%s.to_ulong());\n    ".format(e.ready, e.ready)
+              }
+            }
+          }
+        }
       }
-	    if (c.valid_ready == 1 || c.valid_ready == 2){  // 1= only valid signal -> ValidIO
-		    sctor_list += ", %s__io_in_valid(\"%s__io_in_valid\")\n  ".format(c.name, c.name)
-		    sctor_list += ", %s__io_out_valid(\"%s__io_out_valid\")\n  ".format(c.name, c.name)
-
-		    input_ports += "sc_in<bool > %s__io_in_valid;\n  ".format(c.name)
-		    output_ports += "sc_out<bool > %s__io_out_valid;\n  ".format(c.name)
-		    input_thread += "c->%s__io_in_valid = LIT<1>(%s__io_in_valid->read());\n    ".format(c.name, c.name)
-
-		    output_thread += "%s__io_out_valid->write(c->%s__io_out_valid.to_ulong());\n    ".format(c.name, c.name)
-	    }
-	    if (c.valid_ready == 2){  // 2= both valid & ready signals -> DecoupledIO
-		    sctor_list += ", %s__io_out_ready(\"%s__io_out_ready\")\n  ".format(c.name, c.name)
-		    sctor_list += ", %s__io_in_ready(\"%s__io_in_ready\")\n  ".format(c.name, c.name)
 
-		    input_ports += "sc_in<bool > %s__io_out_ready;\n  ".format(c.name)
-		    output_ports += "sc_out<bool > %s__io_in_ready;\n  ".format(c.name)
-		    input_thread += "c->%s__io_out_ready = LIT<1>(%s__io_out_ready->read());\n    ".format(c.name, c.name)
-
-		    output_thread += "%s__io_in_ready->write(c->%s__io_in_ready.to_ulong());\n    ".format(c.name, c.name)
-
-      }
       replacements += (("input_ports", input_ports))
       replacements += (("output_ports", output_ports))
       replacements += (("sctor_list", sctor_list))
@@ -362,6 +367,7 @@ class CEntry(a_name: String, input: Boolean, a_type: String, a_cast: String, a_w
     name + " " +
     is_input + " " +
     ctype + " " +
+    ccast + " " +
     cwidth + " " +
     data + " " +
     ready + " " +
@@ -372,7 +378,6 @@ class CEntry(a_name: String, input: Boolean, a_type: String, a_cast: String, a_w
 class ComponentDef(a_type: String, a_name: String) {
   val ctype: String = a_type
   val name: String = a_name
-  var valid_ready: Int = 0
   val entries = ArrayBuffer[CEntry]()
   val structs = scala.collection.mutable.LinkedHashMap[String, CStruct]()
 
diff --git a/src/main/scala/SysC.scala b/src/main/scala/SysC.scala
index 76459d69..a2f02b9d 100644
--- a/src/main/scala/SysC.scala
+++ b/src/main/scala/SysC.scala
@@ -31,42 +31,42 @@
 package Chisel
 
 class SysCBackend extends CppBackend {
-    def bool_fun (name: String, bool: Bool): CEntry = {
+    def bool_fun (name: String, bool: Bool, ready: String, valid: String): CEntry = {
       val is_input = bool.dir == INPUT
       val vtype = "bool"; var tcast = ""
       if (is_input) { tcast = "" }
       else { tcast = ".to_ulong()" }
       val vcast = tcast
-      val entry = new CEntry(name, is_input, vtype, vcast, bool.width, bool.name, "ready", "valid")
+      val entry = new CEntry(name, is_input, vtype, vcast, bool.width, bool.name, ready, valid)
       entry
     }
-    def sint_fun (name: String, sint: SInt): CEntry = {
+    def sint_fun (name: String, sint: SInt, ready: String, valid: String): CEntry = {
       val is_input = sint.dir == INPUT
       val vtype = "sc_int<" + sint.width + ">"; var tcast = ""
       if (is_input) { tcast = ".to_uint64()" }
       else { tcast = ".to_ulong()" }
       val vcast = tcast
-      val entry = new CEntry(name, is_input, vtype, vcast, sint.width, sint.name, "ready", "valid")
+      val entry = new CEntry(name, is_input, vtype, vcast, sint.width, sint.name, ready, valid)
       entry
     }
     // UInt: Bits is a virtual UInt class
-    def uint_fun (name: String, uint: UInt): CEntry = {
+    def uint_fun (name: String, uint: UInt, ready: String, valid: String): CEntry = {
       val is_input = uint.dir == INPUT
       val vtype = "sc_uint<" + uint.width + ">"; var tcast = ""
       if (is_input) { tcast = ".to_uint64()" }
       else { tcast = ".to_ulong()" }
       val vcast = tcast
-      val entry = new CEntry(name, is_input, vtype, vcast, uint.width, uint.name, "ready", "valid")
+      val entry = new CEntry(name, is_input, vtype, vcast, uint.width, uint.name, ready, valid)
       entry
     }
-    // Used for Decoupled type
-    def bits_fun (name: String, bits: Bits, ready_name: String, valid_name: String): CEntry = {
+    // Used for Decoupled and Valid types
+    def bits_fun (name: String, bits: Bits, ready: String, valid: String): CEntry = {
       val is_input = bits.dir == INPUT
       val vtype = "sc_uint<" + bits.width + ">"; var tcast = ""
       if (is_input) { tcast = ".to_uint64()" }
       else { tcast = ".to_ulong()" }
       val vcast = tcast
-      val entry = new CEntry(name, is_input, vtype, vcast, bits.width, bits.name, ready_name, valid_name)
+      val entry = new CEntry(name, is_input, vtype, vcast, bits.width, bits.name, ready, valid)
       entry
     }
 
@@ -83,28 +83,24 @@ class SysCBackend extends CppBackend {
     for ((name, elt) <- top_bundle.elements) {
       elt match {
         case bool: Bool => {
-          val entry = bool_fun(name, bool)
+          val entry = bool_fun(name, bool, "", "")
           cdef.entries += (entry)
-          cdef.valid_ready = 0
         }
         case sint: SInt => {
-          val entry = sint_fun(name, sint)
+          val entry = sint_fun(name, sint, "", "")
           cdef.entries += (entry)
-          cdef.valid_ready = 0
         }
         // UInt & Bits
         case uint: UInt => {
-          val entry = uint_fun(name, uint)
+          val entry = uint_fun(name, uint, "", "")
           cdef.entries += (entry)
-          cdef.valid_ready = 0
         }
 
         case velt:ValidIO[_] => {
           velt.bits match {
             case bits: Bits => {
-              val entry = bits_fun(name, bits, "ready", velt.valid.name)
+              val entry = bits_fun(name, bits, "", velt.valid.name)
               cdef.entries += (entry)
-              cdef.valid_ready = 1
             }
             case aggregate: Aggregate => {
               // Collect all the inputs and outputs.
@@ -113,20 +109,17 @@ class SysCBackend extends CppBackend {
                 for (in <- inputs) {
                   in._2 match {
                     case inBool: Bool => {
-                      val entry = bool_fun(name, inBool)
+                      val entry = bool_fun(name, inBool, "", velt.valid.name)
                       cdef.entries += (entry)
-                      cdef.valid_ready = 1
                     }
                     case inSInt: SInt => {
-                      val entry = sint_fun(name, inSInt)
+                      val entry = sint_fun(name, inSInt, "", velt.valid.name)
                       cdef.entries += (entry)
-                      cdef.valid_ready = 1
                     }
                     //Also used for Bits
                     case inUInt: UInt => {
-                      val entry = uint_fun(name, inUInt)
+                      val entry = uint_fun(name, inUInt, "", velt.valid.name)
                       cdef.entries += (entry)
-                      cdef.valid_ready = 1
                     }
                   }
                 }
@@ -136,20 +129,17 @@ class SysCBackend extends CppBackend {
                 for (out <- outputs) {
                    out._2 match {
                     case inBool: Bool => {
-                      val entry = bool_fun(name, inBool)
+                      val entry = bool_fun(name, inBool, "", velt.valid.name)
                       cdef.entries += (entry)
-                      cdef.valid_ready = 1
                     }
                     case inSInt: SInt => {
-                      val entry = sint_fun(name, inSInt)
+                      val entry = sint_fun(name, inSInt, "", velt.valid.name)
                       cdef.entries += (entry)
-                      cdef.valid_ready = 1
                     }
                     //Also used for Bits
                     case inUInt: UInt => {
-                      val entry = uint_fun(name, inUInt)
+                      val entry = uint_fun(name, inUInt, "", velt.valid.name)
                       cdef.entries += (entry)
-                      cdef.valid_ready = 1
                     }
                   }
                 }
@@ -164,7 +154,6 @@ class SysCBackend extends CppBackend {
             case bits: Bits => {
               val entry = bits_fun(name, bits, delt.ready.name, delt.valid.name)
               cdef.entries += (entry)
-              cdef.valid_ready = 2
             }
             case aggregate: Aggregate => {
               // Collect all the inputs and outputs.
@@ -173,20 +162,17 @@ class SysCBackend extends CppBackend {
                 for (in <- inputs) {
                   in._2 match {
                     case inBool: Bool => {
-                      val entry = bool_fun(name, inBool)
+                      val entry = bool_fun(name, inBool, delt.ready.name, delt.valid.name)
                       cdef.entries += (entry)
-                      cdef.valid_ready = 2
                     }
                     case inSInt: SInt => {
-                      val entry = sint_fun(name, inSInt)
+                      val entry = sint_fun(name, inSInt, delt.ready.name, delt.valid.name)
                       cdef.entries += (entry)
-                      cdef.valid_ready = 2
                     }
                     //Also used for Bits
                     case inUInt: UInt => {
-                      val entry = uint_fun(name, inUInt)
+                      val entry = uint_fun(name, inUInt, delt.ready.name, delt.valid.name)
                       cdef.entries += (entry)
-                      cdef.valid_ready = 2
                     }
                   }
                 }
@@ -196,20 +182,17 @@ class SysCBackend extends CppBackend {
                 for (out <- outputs) {
                    out._2 match {
                     case inBool: Bool => {
-                      val entry = bool_fun(name, inBool)
+                      val entry = bool_fun(name, inBool, delt.ready.name, delt.valid.name)
                       cdef.entries += (entry)
-                      cdef.valid_ready = 2
                     }
                     case inSInt: SInt => {
-                      val entry = sint_fun(name, inSInt)
+                      val entry = sint_fun(name, inSInt, delt.ready.name, delt.valid.name)
                       cdef.entries += (entry)
-                      cdef.valid_ready = 2
                     }
                     //Also used for Bits
                     case inUInt: UInt => {
-                      val entry = uint_fun(name, inUInt)
+                      val entry = uint_fun(name, inUInt, delt.ready.name, delt.valid.name)
                       cdef.entries += (entry)
-                      cdef.valid_ready = 2
                     }
                   }
                 }
@@ -224,28 +207,24 @@ class SysCBackend extends CppBackend {
           for ((hname, helt) <- htif_bundle.elements){
             helt match{
               case bool: Bool => {
-                val entry = bool_fun(hname, bool)
+                val entry = bool_fun(hname, bool, "", "")
                 cdef.entries += (entry)
-                cdef.valid_ready = 0
               }
               case sint: SInt => {
-                val entry = sint_fun(hname, sint)
+                val entry = sint_fun(hname, sint, "", "")
                 cdef.entries += (entry)
-                cdef.valid_ready = 0
               }
               // UInt & Bits
               case uint: UInt => {
-                val entry = uint_fun(hname, uint)
+                val entry = uint_fun(hname, uint, "", "")
                 cdef.entries += (entry)
-                cdef.valid_ready = 0
               }
 
               case velt:ValidIO[_] => {
                 velt.bits match {
                   case bits: Bits => {
-                    val entry = bits_fun(hname, bits, "ready", velt.valid.name)
+                    val entry = bits_fun(hname, bits, "", velt.valid.name)
                     cdef.entries += (entry)
-                    cdef.valid_ready = 1
                   }
                   case aggregate: Aggregate => {
                     // Collect all the inputs and outputs.
@@ -254,20 +233,17 @@ class SysCBackend extends CppBackend {
                       for (in <- inputs) {
                         in._2 match {
                           case inBool: Bool => {
-                            val entry = bool_fun(hname, inBool)
+                            val entry = bool_fun(hname, inBool, "", velt.valid.name)
                             cdef.entries += (entry)
-                            cdef.valid_ready = 1
                           }
                           case inSInt: SInt => {
-                            val entry = sint_fun(hname, inSInt)
+                            val entry = sint_fun(hname, inSInt, "", velt.valid.name)
                             cdef.entries += (entry)
-                            cdef.valid_ready = 1
                           }
                           //Also used for Bits
                           case inUInt: UInt => {
-                            val entry = uint_fun(hname, inUInt)
+                            val entry = uint_fun(hname, inUInt, "", velt.valid.name)
                             cdef.entries += (entry)
-                            cdef.valid_ready = 1
                           }
                         }
                       }
@@ -277,20 +253,17 @@ class SysCBackend extends CppBackend {
                       for (out <- outputs) {
                          out._2 match {
                           case inBool: Bool => {
-                            val entry = bool_fun(hname, inBool)
+                            val entry = bool_fun(hname, inBool, "", velt.valid.name)
                             cdef.entries += (entry)
-                            cdef.valid_ready = 1
                           }
                           case inSInt: SInt => {
-                            val entry = sint_fun(hname, inSInt)
+                            val entry = sint_fun(hname, inSInt, "", velt.valid.name)
                             cdef.entries += (entry)
-                            cdef.valid_ready = 1
                           }
                           //Also used for Bits
                           case inUInt: UInt => {
-                            val entry = uint_fun(hname, inUInt)
+                            val entry = uint_fun(hname, inUInt, "", velt.valid.name)
                             cdef.entries += (entry)
-                            cdef.valid_ready = 1
                           }
                         }
                       }
@@ -305,7 +278,6 @@ class SysCBackend extends CppBackend {
                   case bits: Bits => {
                     val entry = bits_fun(hname, bits, delt.ready.name, delt.valid.name)
                     cdef.entries += (entry)
-                    cdef.valid_ready = 2
                   }
                   case aggregate: Aggregate => {
                     // Collect all the inputs and outputs.
@@ -314,20 +286,17 @@ class SysCBackend extends CppBackend {
                       for (in <- inputs) {
                         in._2 match {
                           case inBool: Bool => {
-                            val entry = bool_fun(hname, inBool)
+                            val entry = bool_fun(hname, inBool, delt.ready.name, delt.valid.name)
                             cdef.entries += (entry)
-                            cdef.valid_ready = 2
                           }
                           case inSInt: SInt => {
-                            val entry = sint_fun(hname, inSInt)
+                            val entry = sint_fun(hname, inSInt, delt.ready.name, delt.valid.name)
                             cdef.entries += (entry)
-                            cdef.valid_ready = 2
                           }
                           //Also used for Bits
                           case inUInt: UInt => {
-                            val entry = uint_fun(hname, inUInt)
+                            val entry = uint_fun(hname, inUInt, delt.ready.name, delt.valid.name)
                             cdef.entries += (entry)
-                            cdef.valid_ready = 2
                           }
                         }
                       }
@@ -337,20 +306,17 @@ class SysCBackend extends CppBackend {
                       for (out <- outputs) {
                          out._2 match {
                           case inBool: Bool => {
-                            val entry = bool_fun(hname, inBool)
+                            val entry = bool_fun(hname, inBool, delt.ready.name, delt.valid.name)
                             cdef.entries += (entry)
-                            cdef.valid_ready = 2
                           }
                           case inSInt: SInt => {
-                            val entry = sint_fun(hname, inSInt)
+                            val entry = sint_fun(hname, inSInt, delt.ready.name, delt.valid.name)
                             cdef.entries += (entry)
-                            cdef.valid_ready = 2
                           }
                           //Also used for Bits
                           case inUInt: UInt => {
-                            val entry = uint_fun(hname, inUInt)
+                            val entry = uint_fun(hname, inUInt, delt.ready.name, delt.valid.name)
                             cdef.entries += (entry)
-                            cdef.valid_ready = 2
                           }
                         }
                       }

From 2df645a0e802263c3e27db81abbd02366126f6f2 Mon Sep 17 00:00:00 2001
From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
Date: Fri, 9 Oct 2015 15:53:08 -0300
Subject: [PATCH 13/15] Updated HTIFIO support (Bundle).

---
 src/main/resources/template_cpp.txt |  4 +++-
 src/main/scala/ChiselUtil.scala     | 29 -----------------------------
 src/main/scala/SysC.scala           |  2 +-
 3 files changed, 4 insertions(+), 31 deletions(-)

diff --git a/src/main/resources/template_cpp.txt b/src/main/resources/template_cpp.txt
index 492fd162..28838341 100644
--- a/src/main/resources/template_cpp.txt
+++ b/src/main/resources/template_cpp.txt
@@ -6,9 +6,11 @@ void {!name!}::component_thread(void){
     //Clock Lo
     c->clock_lo(reset);
 
-    {!output_thread!}
     //Clock Hi
     c->clock_hi(reset);
+
+    {!output_thread!}
+
     wait(Step);
   }
 }
diff --git a/src/main/scala/ChiselUtil.scala b/src/main/scala/ChiselUtil.scala
index 0c9108b9..ac19068b 100644
--- a/src/main/scala/ChiselUtil.scala
+++ b/src/main/scala/ChiselUtil.scala
@@ -32,35 +32,6 @@ package Chisel
 import scala.math.{ceil, floor, log}
 import scala.collection.mutable.ArrayBuffer
 
-//-------------------------------------------------------------------------[byCAP
-// Moved from riscv-sodor/src/common/htif.scala
-// is it a good idea? not, but for now ...
-// the best way is creating Interfaces
-class CSRReq(addr_width: Int) extends Bundle
-{
-   val rw = Bool()
-   val addr = Bits(width = addr_width)
-   val data = Bits(width = 64)
-   override def clone = { new CSRReq(addr_width).asInstanceOf[this.type] }
-}
-
-class HTIFIO() extends Bundle
-{
-   val reset = Bool(INPUT)
-   val debug_stats_csr = Bool(OUTPUT)
-   val id = UInt(INPUT, 1)
-   val csr_req = Decoupled(new CSRReq(addr_width = 12)).flip
-   val csr_rep = Decoupled(Bits(width = 64))
-   // inter-processor interrupts. Not really necessary for Sodor.
-   val ipi_req = Decoupled(Bits(width = 1))
-   val ipi_rep = Decoupled(Bool()).flip
-   
-   val mem_req = Decoupled(new CSRReq(addr_width = 64)).flip
-   val mem_rep = Valid(Bits(width = 64))
-}
-//-------------------------------------------------------------------------byCAP]
-
-
 /** Compute the log2 rounded up with min value of 1 */
 object log2Up
 {
diff --git a/src/main/scala/SysC.scala b/src/main/scala/SysC.scala
index a2f02b9d..065f9a34 100644
--- a/src/main/scala/SysC.scala
+++ b/src/main/scala/SysC.scala
@@ -202,7 +202,7 @@ class SysCBackend extends CppBackend {
           }
         }
 
-        case belt: HTIFIO => {
+        case belt: Bundle => {
           val htif_bundle = belt.asInstanceOf[Bundle]
           for ((hname, helt) <- htif_bundle.elements){
             helt match{

From 583260e4b90a90345fed9abbe86d3891227a36e1 Mon Sep 17 00:00:00 2001
From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
Date: Mon, 12 Oct 2015 20:15:04 -0300
Subject: [PATCH 14/15] Updated and fixed SystemC Chisel code generation.

---
 src/main/scala/SCWrapper.scala |  28 ++---
 src/main/scala/SysC.scala      | 206 ++++++++++++++++++---------------
 2 files changed, 125 insertions(+), 109 deletions(-)

diff --git a/src/main/scala/SCWrapper.scala b/src/main/scala/SCWrapper.scala
index 67678872..35569977 100644
--- a/src/main/scala/SCWrapper.scala
+++ b/src/main/scala/SCWrapper.scala
@@ -54,15 +54,15 @@ object SCWrapper {
 
   def example_component_def(): ComponentDef = {
     val cdef = new ComponentDef("GCD_t", "GCD")
-    cdef.entries += new CEntry("a", true, "dat_t<1>", "dat_t<1>", 1, "GCD__io_a", "GCD__io_r1", "GCD__io_v1")
-    cdef.entries += new CEntry("z", false, "dat_t<1>", "dat_t<1>", 1, "GCD__io_z", "GCD__io_rz", "GCD__io_vz")
+    cdef.entries += new CEntry("a", true, "dat_t<1>", "dat_t<1>", 1, "GCD__io_a")
+    cdef.entries += new CEntry("z", false, "dat_t<1>", "dat_t<1>", 1, "GCD__io_z")
     cdef
   }
 
   def example_component_def2(): ComponentDef = {
     val cdef = new ComponentDef("AddFilter_t", "AddFilter")
-    cdef.entries += new CEntry("a", true, "dat_t<16>", "dat_t<1>", 16, "AddFilter__io_a", "AddFilter__io_ar", "AddFilter__io_av")
-    cdef.entries += new CEntry("b", false, "dat_t<16>", "dat_t<1>", 16, "AddFilter__io_b", "AddFilter__io_br", "AddFilter__io_bv")
+    cdef.entries += new CEntry("a", true, "dat_t<16>", "dat_t<1>", 16, "AddFilter__io_a")
+    cdef.entries += new CEntry("b", false, "dat_t<16>", "dat_t<1>", 16, "AddFilter__io_b")
     cdef
   }
 
@@ -132,7 +132,7 @@ object SCWrapper {
           output_thread += thread_out
         }
         // Generate ready and valid signals when necessary
-        if (e.name != fname){
+/*        if (e.name != fname){
           fname = e.name
           if (e.valid != ""){
 		        sctor_list += ", %s(\"%s\")\n  ".format(e.valid, e.valid)
@@ -154,7 +154,7 @@ object SCWrapper {
               }
             }
           }
-        }
+        } */
       }
 
       replacements += (("input_ports", input_ports))
@@ -204,8 +204,8 @@ object SCWrapper {
         val filled = fvar(i)
         val in = ports(i).name
         val in_data = ports(i).data
-        val ready = ports(i).ready
-        val valid = ports(i).valid
+        val ready = "ready"     //ports(i).ready
+        val valid = "valid"     //ports(i).valid
         init += "%s %s;\n    ".format(ctype, data)
         init += "int %s = 0;\n    ".format(filled)
         fill += "if(!%s){%s = %s->nb_read(%s);}\n      "format(filled, filled, in, data)
@@ -239,9 +239,9 @@ object SCWrapper {
       var valid_output = "";
       for(i <- 0 until ports.size) {
         val ctype = ports(i).ctype
-        val valid = ports(i).valid
+        val valid = "valid"     //ports(i).valid
         val data = ports(i).data
-        val ready = ports(i).ready
+        val ready = "ready"     //ports(i).ready
         val out = ports(i).name
         check += "c->%s = LIT<1>(%s->num_free() > 0);\n      "format(ready, out)
         // Is this a structured data-type?
@@ -353,15 +353,13 @@ object SCWrapper {
   }
 }
 
-class CEntry(a_name: String, input: Boolean, a_type: String, a_cast: String, a_width: Int, a_data: String, a_ready: String, a_valid: String) {
+class CEntry(a_name: String, input: Boolean, a_type: String, a_cast: String, a_width: Int, a_data: String) {
   val name = a_name
   val is_input = input
   val ctype = a_type
   val ccast = a_cast
   val cwidth = a_width
   val data = a_data
-  val ready = a_ready
-  val valid = a_valid
 
   override def toString(): String = {
     name + " " +
@@ -369,9 +367,7 @@ class CEntry(a_name: String, input: Boolean, a_type: String, a_cast: String, a_w
     ctype + " " +
     ccast + " " +
     cwidth + " " +
-    data + " " +
-    ready + " " +
-    valid
+    data
   }
 }
 
diff --git a/src/main/scala/SysC.scala b/src/main/scala/SysC.scala
index 065f9a34..adb5708b 100644
--- a/src/main/scala/SysC.scala
+++ b/src/main/scala/SysC.scala
@@ -31,42 +31,42 @@
 package Chisel
 
 class SysCBackend extends CppBackend {
-    def bool_fun (name: String, bool: Bool, ready: String, valid: String): CEntry = {
+    def bool_fun (name: String, bool: Bool): CEntry = {
       val is_input = bool.dir == INPUT
       val vtype = "bool"; var tcast = ""
       if (is_input) { tcast = "" }
       else { tcast = ".to_ulong()" }
       val vcast = tcast
-      val entry = new CEntry(name, is_input, vtype, vcast, bool.width, bool.name, ready, valid)
+      val entry = new CEntry(name, is_input, vtype, vcast, bool.width, bool.name)
       entry
     }
-    def sint_fun (name: String, sint: SInt, ready: String, valid: String): CEntry = {
+    def sint_fun (name: String, sint: SInt): CEntry = {
       val is_input = sint.dir == INPUT
       val vtype = "sc_int<" + sint.width + ">"; var tcast = ""
       if (is_input) { tcast = ".to_uint64()" }
       else { tcast = ".to_ulong()" }
       val vcast = tcast
-      val entry = new CEntry(name, is_input, vtype, vcast, sint.width, sint.name, ready, valid)
+      val entry = new CEntry(name, is_input, vtype, vcast, sint.width, sint.name)
       entry
     }
     // UInt: Bits is a virtual UInt class
-    def uint_fun (name: String, uint: UInt, ready: String, valid: String): CEntry = {
+    def uint_fun (name: String, uint: UInt): CEntry = {
       val is_input = uint.dir == INPUT
       val vtype = "sc_uint<" + uint.width + ">"; var tcast = ""
       if (is_input) { tcast = ".to_uint64()" }
       else { tcast = ".to_ulong()" }
       val vcast = tcast
-      val entry = new CEntry(name, is_input, vtype, vcast, uint.width, uint.name, ready, valid)
+      val entry = new CEntry(name, is_input, vtype, vcast, uint.width, uint.name)
       entry
     }
     // Used for Decoupled and Valid types
-    def bits_fun (name: String, bits: Bits, ready: String, valid: String): CEntry = {
+    def bits_fun (name: String, bits: Bits): CEntry = {
       val is_input = bits.dir == INPUT
       val vtype = "sc_uint<" + bits.width + ">"; var tcast = ""
       if (is_input) { tcast = ".to_uint64()" }
       else { tcast = ".to_ulong()" }
       val vcast = tcast
-      val entry = new CEntry(name, is_input, vtype, vcast, bits.width, bits.name, ready, valid)
+      val entry = new CEntry(name, is_input, vtype, vcast, bits.width, bits.name)
       entry
     }
 
@@ -83,23 +83,27 @@ class SysCBackend extends CppBackend {
     for ((name, elt) <- top_bundle.elements) {
       elt match {
         case bool: Bool => {
-          val entry = bool_fun(name, bool, "", "")
+          val entry = bool_fun(name, bool)
           cdef.entries += (entry)
         }
         case sint: SInt => {
-          val entry = sint_fun(name, sint, "", "")
+          val entry = sint_fun(name, sint)
           cdef.entries += (entry)
         }
         // UInt & Bits
         case uint: UInt => {
-          val entry = uint_fun(name, uint, "", "")
+          val entry = uint_fun(name, uint)
           cdef.entries += (entry)
         }
 
         case velt:ValidIO[_] => {
+          { // Generate Valid signal
+            val ventry = bool_fun(velt.valid.name, velt.valid)
+            cdef.entries += (ventry)
+          }
           velt.bits match {
             case bits: Bits => {
-              val entry = bits_fun(name, bits, "", velt.valid.name)
+              val entry = bits_fun(name, bits)
               cdef.entries += (entry)
             }
             case aggregate: Aggregate => {
@@ -109,16 +113,16 @@ class SysCBackend extends CppBackend {
                 for (in <- inputs) {
                   in._2 match {
                     case inBool: Bool => {
-                      val entry = bool_fun(name, inBool, "", velt.valid.name)
+                      val entry = bool_fun(name, inBool)
                       cdef.entries += (entry)
                     }
                     case inSInt: SInt => {
-                      val entry = sint_fun(name, inSInt, "", velt.valid.name)
+                      val entry = sint_fun(name, inSInt)
                       cdef.entries += (entry)
                     }
                     //Also used for Bits
                     case inUInt: UInt => {
-                      val entry = uint_fun(name, inUInt, "", velt.valid.name)
+                      val entry = uint_fun(name, inUInt)
                       cdef.entries += (entry)
                     }
                   }
@@ -128,31 +132,37 @@ class SysCBackend extends CppBackend {
               if (outputs.length > 0) {
                 for (out <- outputs) {
                    out._2 match {
-                    case inBool: Bool => {
-                      val entry = bool_fun(name, inBool, "", velt.valid.name)
+                    case outBool: Bool => {
+                      val entry = bool_fun(name, outBool)
                       cdef.entries += (entry)
                     }
-                    case inSInt: SInt => {
-                      val entry = sint_fun(name, inSInt, "", velt.valid.name)
+                    case outSInt: SInt => {
+                      val entry = sint_fun(name, outSInt)
                       cdef.entries += (entry)
                     }
                     //Also used for Bits
-                    case inUInt: UInt => {
-                      val entry = uint_fun(name, inUInt, "", velt.valid.name)
+                    case outUInt: UInt => {
+                      val entry = uint_fun(name, outUInt)
                       cdef.entries += (entry)
                     }
                   }
                 }
               }
             }
-            case _ => badElements(name) = elt
+            case _ => badElements(name) = velt
           }
         }
 
         case delt:DecoupledIO[_] => {
+          { // Generate Ready and Valid signals
+            val rentry = bool_fun(delt.ready.name, delt.ready)
+            cdef.entries += (rentry)
+            val ventry = bool_fun(delt.valid.name, delt.valid)
+            cdef.entries += (ventry)
+          }
           delt.bits match {
             case bits: Bits => {
-              val entry = bits_fun(name, bits, delt.ready.name, delt.valid.name)
+              val entry = bits_fun(name, bits)
               cdef.entries += (entry)
             }
             case aggregate: Aggregate => {
@@ -162,16 +172,16 @@ class SysCBackend extends CppBackend {
                 for (in <- inputs) {
                   in._2 match {
                     case inBool: Bool => {
-                      val entry = bool_fun(name, inBool, delt.ready.name, delt.valid.name)
+                      val entry = bool_fun(name, inBool)
                       cdef.entries += (entry)
                     }
                     case inSInt: SInt => {
-                      val entry = sint_fun(name, inSInt, delt.ready.name, delt.valid.name)
+                      val entry = sint_fun(name, inSInt)
                       cdef.entries += (entry)
                     }
                     //Also used for Bits
                     case inUInt: UInt => {
-                      val entry = uint_fun(name, inUInt, delt.ready.name, delt.valid.name)
+                      val entry = uint_fun(name, inUInt)
                       cdef.entries += (entry)
                     }
                   }
@@ -181,148 +191,158 @@ class SysCBackend extends CppBackend {
               if (outputs.length > 0) {
                 for (out <- outputs) {
                    out._2 match {
-                    case inBool: Bool => {
-                      val entry = bool_fun(name, inBool, delt.ready.name, delt.valid.name)
+                    case outBool: Bool => {
+                      val entry = bool_fun(name, outBool)
                       cdef.entries += (entry)
                     }
-                    case inSInt: SInt => {
-                      val entry = sint_fun(name, inSInt, delt.ready.name, delt.valid.name)
+                    case outSInt: SInt => {
+                      val entry = sint_fun(name, outSInt)
                       cdef.entries += (entry)
                     }
                     //Also used for Bits
-                    case inUInt: UInt => {
-                      val entry = uint_fun(name, inUInt, delt.ready.name, delt.valid.name)
+                    case outUInt: UInt => {
+                      val entry = uint_fun(name, outUInt)
                       cdef.entries += (entry)
                     }
                   }
                 }
               }
             }
-            case _ => badElements(name) = elt
+            case _ => badElements(name) = delt
           }
         }
 
         case belt: Bundle => {
-          val htif_bundle = belt.asInstanceOf[Bundle]
-          for ((hname, helt) <- htif_bundle.elements){
+          val belt_bundle = belt.asInstanceOf[Bundle]
+          for ((hname, helt) <- belt_bundle.elements){
             helt match{
-              case bool: Bool => {
-                val entry = bool_fun(hname, bool, "", "")
+              case bbool: Bool => {
+                val entry = bool_fun(hname, bbool)
                 cdef.entries += (entry)
               }
-              case sint: SInt => {
-                val entry = sint_fun(hname, sint, "", "")
+              case bsint: SInt => {
+                val entry = sint_fun(hname, bsint)
                 cdef.entries += (entry)
               }
               // UInt & Bits
-              case uint: UInt => {
-                val entry = uint_fun(hname, uint, "", "")
+              case buint: UInt => {
+                val entry = uint_fun(hname, buint)
                 cdef.entries += (entry)
               }
 
-              case velt:ValidIO[_] => {
-                velt.bits match {
-                  case bits: Bits => {
-                    val entry = bits_fun(hname, bits, "", velt.valid.name)
+              case bvelt:ValidIO[_] => {
+                { // Generate Valid signal
+                  val ventry = bool_fun(bvelt.valid.name, bvelt.valid)
+                  cdef.entries += (ventry)
+                }
+                bvelt.bits match {
+                  case bvbits: Bits => {
+                    val entry = bits_fun(hname, bvbits)
                     cdef.entries += (entry)
                   }
-                  case aggregate: Aggregate => {
+                  case bvaggregate: Aggregate => {
                     // Collect all the inputs and outputs.
-                    val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
-                    if (inputs.length > 0) {
-                      for (in <- inputs) {
-                        in._2 match {
-                          case inBool: Bool => {
-                            val entry = bool_fun(hname, inBool, "", velt.valid.name)
+                    val bvinputs = bvaggregate.flatten.filter(_._2.dir == INPUT)
+                    if (bvinputs.length > 0) {
+                      for (bvin <- bvinputs) {
+                        bvin._2 match {
+                          case bvinBool: Bool => {
+                            val entry = bool_fun(hname, bvinBool)
                             cdef.entries += (entry)
                           }
-                          case inSInt: SInt => {
-                            val entry = sint_fun(hname, inSInt, "", velt.valid.name)
+                          case bvinSInt: SInt => {
+                            val entry = sint_fun(hname, bvinSInt)
                             cdef.entries += (entry)
                           }
                           //Also used for Bits
-                          case inUInt: UInt => {
-                            val entry = uint_fun(hname, inUInt, "", velt.valid.name)
+                          case bvinUInt: UInt => {
+                            val entry = uint_fun(hname, bvinUInt)
                             cdef.entries += (entry)
                           }
                         }
                       }
                     }
-                    val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
-                    if (outputs.length > 0) {
-                      for (out <- outputs) {
-                         out._2 match {
-                          case inBool: Bool => {
-                            val entry = bool_fun(hname, inBool, "", velt.valid.name)
+                    val bvoutputs = bvaggregate.flatten.filter(_._2.dir == OUTPUT)
+                    if (bvoutputs.length > 0) {
+                      for (bvout <- bvoutputs) {
+                         bvout._2 match {
+                          case bvoutBool: Bool => {
+                            val entry = bool_fun(hname, bvoutBool)
                             cdef.entries += (entry)
                           }
-                          case inSInt: SInt => {
-                            val entry = sint_fun(hname, inSInt, "", velt.valid.name)
+                          case bvoutSInt: SInt => {
+                            val entry = sint_fun(hname, bvoutSInt)
                             cdef.entries += (entry)
                           }
                           //Also used for Bits
-                          case inUInt: UInt => {
-                            val entry = uint_fun(hname, inUInt, "", velt.valid.name)
+                          case bvoutUInt: UInt => {
+                            val entry = uint_fun(hname, bvoutUInt)
                             cdef.entries += (entry)
                           }
                         }
                       }
                     }
                   }
-                  case _ => badElements(hname) = elt
+                  case _ => badElements(hname) = bvelt
                 }
               }
 
-              case delt:DecoupledIO[_] => {
-                delt.bits match {
-                  case bits: Bits => {
-                    val entry = bits_fun(hname, bits, delt.ready.name, delt.valid.name)
+              case bdelt:DecoupledIO[_] => {
+                { // Generate Ready and Valid signals
+                  val rentry = bool_fun(bdelt.ready.name, bdelt.ready)
+                  cdef.entries += (rentry)
+                  val ventry = bool_fun(bdelt.valid.name, bdelt.valid)
+                  cdef.entries += (ventry)
+                }
+                bdelt.bits match {
+                  case bdbits: Bits => {
+                    val entry = bits_fun(hname, bdbits)
                     cdef.entries += (entry)
                   }
-                  case aggregate: Aggregate => {
+                  case bdaggregate: Aggregate => {
                     // Collect all the inputs and outputs.
-                    val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
-                    if (inputs.length > 0) {
-                      for (in <- inputs) {
-                        in._2 match {
-                          case inBool: Bool => {
-                            val entry = bool_fun(hname, inBool, delt.ready.name, delt.valid.name)
+                    val bdinputs = bdaggregate.flatten.filter(_._2.dir == INPUT)
+                    if (bdinputs.length > 0) {
+                      for (bdin <- bdinputs) {
+                        bdin._2 match {
+                          case bdinBool: Bool => {
+                            val entry = bool_fun(hname, bdinBool)
                             cdef.entries += (entry)
                           }
-                          case inSInt: SInt => {
-                            val entry = sint_fun(hname, inSInt, delt.ready.name, delt.valid.name)
+                          case bdinSInt: SInt => {
+                            val entry = sint_fun(hname, bdinSInt)
                             cdef.entries += (entry)
                           }
                           //Also used for Bits
-                          case inUInt: UInt => {
-                            val entry = uint_fun(hname, inUInt, delt.ready.name, delt.valid.name)
+                          case bdinUInt: UInt => {
+                            val entry = uint_fun(hname, bdinUInt)
                             cdef.entries += (entry)
                           }
                         }
                       }
                     }
-                    val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
-                    if (outputs.length > 0) {
-                      for (out <- outputs) {
-                         out._2 match {
-                          case inBool: Bool => {
-                            val entry = bool_fun(hname, inBool, delt.ready.name, delt.valid.name)
+                    val bdoutputs = bdaggregate.flatten.filter(_._2.dir == OUTPUT)
+                    if (bdoutputs.length > 0) {
+                      for (bdout <- bdoutputs) {
+                         bdout._2 match {
+                          case bdoutBool: Bool => {
+                            val entry = bool_fun(hname, bdoutBool)
                             cdef.entries += (entry)
                           }
-                          case inSInt: SInt => {
-                            val entry = sint_fun(hname, inSInt, delt.ready.name, delt.valid.name)
+                          case bdoutSInt: SInt => {
+                            val entry = sint_fun(hname, bdoutSInt)
                             cdef.entries += (entry)
                           }
                           //Also used for Bits
-                          case inUInt: UInt => {
-                            val entry = uint_fun(hname, inUInt, delt.ready.name, delt.valid.name)
+                          case bdoutUInt: UInt => {
+                            val entry = uint_fun(hname, bdoutUInt)
                             cdef.entries += (entry)
                           }
                         }
                       }
                     }
                   }
-                  case _ => badElements(hname) = helt
+                  case _ => badElements(hname) = bdelt
                 }
               }
               case _ => badElements(hname) = helt

From d56589d27e89e51157facb8de5717d0b828609d9 Mon Sep 17 00:00:00 2001
From: Carlos Alberto Petry <carlos.petry@ic.unicamp.br>
Date: Fri, 4 Dec 2015 15:12:07 -0200
Subject: [PATCH 15/15] Included support to Vec data type. Minor updates.

---
 src/main/scala/SysC.scala | 483 ++++++++++++++++++--------------------
 1 file changed, 224 insertions(+), 259 deletions(-)

diff --git a/src/main/scala/SysC.scala b/src/main/scala/SysC.scala
index adb5708b..195ec533 100644
--- a/src/main/scala/SysC.scala
+++ b/src/main/scala/SysC.scala
@@ -31,45 +31,167 @@
 package Chisel
 
 class SysCBackend extends CppBackend {
-    def bool_fun (name: String, bool: Bool): CEntry = {
-      val is_input = bool.dir == INPUT
-      val vtype = "bool"; var tcast = ""
-      if (is_input) { tcast = "" }
-      else { tcast = ".to_ulong()" }
-      val vcast = tcast
-      val entry = new CEntry(name, is_input, vtype, vcast, bool.width, bool.name)
-      entry
-    }
-    def sint_fun (name: String, sint: SInt): CEntry = {
-      val is_input = sint.dir == INPUT
-      val vtype = "sc_int<" + sint.width + ">"; var tcast = ""
-      if (is_input) { tcast = ".to_uint64()" }
-      else { tcast = ".to_ulong()" }
-      val vcast = tcast
-      val entry = new CEntry(name, is_input, vtype, vcast, sint.width, sint.name)
-      entry
-    }
-    // UInt: Bits is a virtual UInt class
-    def uint_fun (name: String, uint: UInt): CEntry = {
-      val is_input = uint.dir == INPUT
-      val vtype = "sc_uint<" + uint.width + ">"; var tcast = ""
-      if (is_input) { tcast = ".to_uint64()" }
-      else { tcast = ".to_ulong()" }
-      val vcast = tcast
-      val entry = new CEntry(name, is_input, vtype, vcast, uint.width, uint.name)
-      entry
-    }
-    // Used for Decoupled and Valid types
-    def bits_fun (name: String, bits: Bits): CEntry = {
-      val is_input = bits.dir == INPUT
-      val vtype = "sc_uint<" + bits.width + ">"; var tcast = ""
-      if (is_input) { tcast = ".to_uint64()" }
-      else { tcast = ".to_ulong()" }
-      val vcast = tcast
-      val entry = new CEntry(name, is_input, vtype, vcast, bits.width, bits.name)
-      entry
+  def bool_fun (name: String, bool: Bool): CEntry = {
+    val is_input = bool.dir == INPUT
+    val vtype = "bool"; var tcast = ""
+    if (is_input) { tcast = "" }
+    else { tcast = ".to_ulong()" }
+    val vcast = tcast
+    val entry = new CEntry(name, is_input, vtype, vcast, bool.width, bool.name)
+    entry
+  }
+
+  def sint_fun (name: String, sint: SInt): CEntry = {
+    val is_input = sint.dir == INPUT
+    val vtype = "sc_int<" + sint.width + ">"; var tcast = ""
+    if (is_input) { tcast = ".to_uint64()" }
+    else { tcast = ".to_ulong()" }
+    val vcast = tcast
+    val entry = new CEntry(name, is_input, vtype, vcast, sint.width, sint.name)
+    entry
+  }
+
+  // UInt: Bits is a virtual UInt class
+  def uint_fun (name: String, uint: UInt): CEntry = {
+    val is_input = uint.dir == INPUT
+    val vtype = "sc_uint<" + uint.width + ">"; var tcast = ""
+    if (is_input) { tcast = ".to_uint64()" }
+    else { tcast = ".to_ulong()" }
+    val vcast = tcast
+    val entry = new CEntry(name, is_input, vtype, vcast, uint.width, uint.name)
+    entry
+  }
+
+  // Used for Decoupled and Valid types
+  def bits_fun (name: String, bits: Bits): CEntry = {
+    val is_input = bits.dir == INPUT
+    val vtype = "sc_uint<" + bits.width + ">"; var tcast = ""
+    if (is_input) { tcast = ".to_uint64()" }
+    else { tcast = ".to_ulong()" }
+    val vcast = tcast
+    val entry = new CEntry(name, is_input, vtype, vcast, bits.width, bits.name)
+    entry
+  }
+
+  def valid_fun (velt: ValidIO[_], cdef: ComponentDef, name: String): Boolean = {
+    var velt_bad = false
+    // Generate Valid signal
+    val ventry = bool_fun(velt.valid.name, velt.valid)
+    cdef.entries += (ventry)
+    velt.bits match {
+      case bits: Bits => {
+        val entry = bits_fun(name, bits)
+        cdef.entries += (entry)
+      }
+      case aggregate: Aggregate => {
+        // Collect all the inputs and outputs.
+        val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
+        if (inputs.length > 0) {
+          for (in <- inputs) {
+            in._2 match {
+              case inBool: Bool => {
+                val entry = bool_fun(name, inBool)
+                cdef.entries += (entry)
+              }
+              case inSInt: SInt => {
+                val entry = sint_fun(name, inSInt)
+                cdef.entries += (entry)
+              }
+              //Also used for Bits
+              case inUInt: UInt => {
+                val entry = uint_fun(name, inUInt)
+                cdef.entries += (entry)
+              }
+            }
+          }
+        }
+        val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
+        if (outputs.length > 0) {
+          for (out <- outputs) {
+             out._2 match {
+              case outBool: Bool => {
+                val entry = bool_fun(name, outBool)
+                cdef.entries += (entry)
+              }
+              case outSInt: SInt => {
+                val entry = sint_fun(name, outSInt)
+                cdef.entries += (entry)
+              }
+              //Also used for Bits
+              case outUInt: UInt => {
+                val entry = uint_fun(name, outUInt)
+                cdef.entries += (entry)
+              }
+            }
+          }
+        }
+      }
+      case _ => velt_bad = true
     }
+    velt_bad
+  }
+
+  def decoupled_fun (delt: DecoupledIO[_], cdef: ComponentDef, name: String): Boolean = {
+    var delt_bad = false
+    // Generate Ready and Valid signals
+    val rentry = bool_fun(delt.ready.name, delt.ready)
+    cdef.entries += (rentry)
+    val ventry = bool_fun(delt.valid.name, delt.valid)
+    cdef.entries += (ventry)
 
+    delt.bits match {
+      case bits: Bits => {
+        val entry = bits_fun(name, bits)
+        cdef.entries += (entry)
+      }
+      case aggregate: Aggregate => {
+        // Collect all the inputs and outputs.
+        val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
+        if (inputs.length > 0) {
+          for (in <- inputs) {
+            in._2 match {
+              case inBool: Bool => {
+                val entry = bool_fun(name, inBool)
+                cdef.entries += (entry)
+              }
+              case inSInt: SInt => {
+                val entry = sint_fun(name, inSInt)
+                cdef.entries += (entry)
+              }
+              //Also used for Bits
+              case inUInt: UInt => {
+                val entry = uint_fun(name, inUInt)
+                cdef.entries += (entry)
+              }
+            }
+          }
+        }
+        val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
+        if (outputs.length > 0) {
+          for (out <- outputs) {
+             out._2 match {
+              case outBool: Bool => {
+                val entry = bool_fun(name, outBool)
+                cdef.entries += (entry)
+              }
+              case outSInt: SInt => {
+                val entry = sint_fun(name, outSInt)
+                cdef.entries += (entry)
+              }
+              //Also used for Bits
+              case outUInt: UInt => {
+                val entry = uint_fun(name, outUInt)
+                cdef.entries += (entry)
+              }
+            }
+          }
+        }
+      }
+      case _ => delt_bad = true
+    }
+    delt_bad
+  }
+//==================================================================================
     override def elaborate(c: Module): Unit = {
       super.elaborate(c)
       println(c)
@@ -86,10 +208,12 @@ class SysCBackend extends CppBackend {
           val entry = bool_fun(name, bool)
           cdef.entries += (entry)
         }
+
         case sint: SInt => {
           val entry = sint_fun(name, sint)
           cdef.entries += (entry)
         }
+
         // UInt & Bits
         case uint: UInt => {
           val entry = uint_fun(name, uint)
@@ -97,119 +221,13 @@ class SysCBackend extends CppBackend {
         }
 
         case velt:ValidIO[_] => {
-          { // Generate Valid signal
-            val ventry = bool_fun(velt.valid.name, velt.valid)
-            cdef.entries += (ventry)
-          }
-          velt.bits match {
-            case bits: Bits => {
-              val entry = bits_fun(name, bits)
-              cdef.entries += (entry)
-            }
-            case aggregate: Aggregate => {
-              // Collect all the inputs and outputs.
-              val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
-              if (inputs.length > 0) {
-                for (in <- inputs) {
-                  in._2 match {
-                    case inBool: Bool => {
-                      val entry = bool_fun(name, inBool)
-                      cdef.entries += (entry)
-                    }
-                    case inSInt: SInt => {
-                      val entry = sint_fun(name, inSInt)
-                      cdef.entries += (entry)
-                    }
-                    //Also used for Bits
-                    case inUInt: UInt => {
-                      val entry = uint_fun(name, inUInt)
-                      cdef.entries += (entry)
-                    }
-                  }
-                }
-              }
-              val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
-              if (outputs.length > 0) {
-                for (out <- outputs) {
-                   out._2 match {
-                    case outBool: Bool => {
-                      val entry = bool_fun(name, outBool)
-                      cdef.entries += (entry)
-                    }
-                    case outSInt: SInt => {
-                      val entry = sint_fun(name, outSInt)
-                      cdef.entries += (entry)
-                    }
-                    //Also used for Bits
-                    case outUInt: UInt => {
-                      val entry = uint_fun(name, outUInt)
-                      cdef.entries += (entry)
-                    }
-                  }
-                }
-              }
-            }
-            case _ => badElements(name) = velt
-          }
+          val velt_bad = valid_fun(velt, cdef, name)
+          if (velt_bad) badElements(name) = velt
         }
 
         case delt:DecoupledIO[_] => {
-          { // Generate Ready and Valid signals
-            val rentry = bool_fun(delt.ready.name, delt.ready)
-            cdef.entries += (rentry)
-            val ventry = bool_fun(delt.valid.name, delt.valid)
-            cdef.entries += (ventry)
-          }
-          delt.bits match {
-            case bits: Bits => {
-              val entry = bits_fun(name, bits)
-              cdef.entries += (entry)
-            }
-            case aggregate: Aggregate => {
-              // Collect all the inputs and outputs.
-              val inputs = aggregate.flatten.filter(_._2.dir == INPUT)
-              if (inputs.length > 0) {
-                for (in <- inputs) {
-                  in._2 match {
-                    case inBool: Bool => {
-                      val entry = bool_fun(name, inBool)
-                      cdef.entries += (entry)
-                    }
-                    case inSInt: SInt => {
-                      val entry = sint_fun(name, inSInt)
-                      cdef.entries += (entry)
-                    }
-                    //Also used for Bits
-                    case inUInt: UInt => {
-                      val entry = uint_fun(name, inUInt)
-                      cdef.entries += (entry)
-                    }
-                  }
-                }
-              }
-              val outputs = aggregate.flatten.filter(_._2.dir == OUTPUT)
-              if (outputs.length > 0) {
-                for (out <- outputs) {
-                   out._2 match {
-                    case outBool: Bool => {
-                      val entry = bool_fun(name, outBool)
-                      cdef.entries += (entry)
-                    }
-                    case outSInt: SInt => {
-                      val entry = sint_fun(name, outSInt)
-                      cdef.entries += (entry)
-                    }
-                    //Also used for Bits
-                    case outUInt: UInt => {
-                      val entry = uint_fun(name, outUInt)
-                      cdef.entries += (entry)
-                    }
-                  }
-                }
-              }
-            }
-            case _ => badElements(name) = delt
-          }
+          val delt_bad = decoupled_fun(delt, cdef, name)
+          if (delt_bad) badElements(name) = delt
         }
 
         case belt: Bundle => {
@@ -229,126 +247,73 @@ class SysCBackend extends CppBackend {
                 val entry = uint_fun(hname, buint)
                 cdef.entries += (entry)
               }
-
               case bvelt:ValidIO[_] => {
-                { // Generate Valid signal
-                  val ventry = bool_fun(bvelt.valid.name, bvelt.valid)
-                  cdef.entries += (ventry)
-                }
-                bvelt.bits match {
-                  case bvbits: Bits => {
-                    val entry = bits_fun(hname, bvbits)
-                    cdef.entries += (entry)
-                  }
-                  case bvaggregate: Aggregate => {
-                    // Collect all the inputs and outputs.
-                    val bvinputs = bvaggregate.flatten.filter(_._2.dir == INPUT)
-                    if (bvinputs.length > 0) {
-                      for (bvin <- bvinputs) {
-                        bvin._2 match {
-                          case bvinBool: Bool => {
-                            val entry = bool_fun(hname, bvinBool)
-                            cdef.entries += (entry)
-                          }
-                          case bvinSInt: SInt => {
-                            val entry = sint_fun(hname, bvinSInt)
-                            cdef.entries += (entry)
-                          }
-                          //Also used for Bits
-                          case bvinUInt: UInt => {
-                            val entry = uint_fun(hname, bvinUInt)
-                            cdef.entries += (entry)
-                          }
-                        }
-                      }
-                    }
-                    val bvoutputs = bvaggregate.flatten.filter(_._2.dir == OUTPUT)
-                    if (bvoutputs.length > 0) {
-                      for (bvout <- bvoutputs) {
-                         bvout._2 match {
-                          case bvoutBool: Bool => {
-                            val entry = bool_fun(hname, bvoutBool)
-                            cdef.entries += (entry)
-                          }
-                          case bvoutSInt: SInt => {
-                            val entry = sint_fun(hname, bvoutSInt)
-                            cdef.entries += (entry)
-                          }
-                          //Also used for Bits
-                          case bvoutUInt: UInt => {
-                            val entry = uint_fun(hname, bvoutUInt)
-                            cdef.entries += (entry)
-                          }
-                        }
-                      }
-                    }
-                  }
-                  case _ => badElements(hname) = bvelt
-                }
+                val bvelt_bad = valid_fun(bvelt, cdef, name)
+                if (bvelt_bad) badElements(name) = bvelt
               }
-
               case bdelt:DecoupledIO[_] => {
-                { // Generate Ready and Valid signals
-                  val rentry = bool_fun(bdelt.ready.name, bdelt.ready)
-                  cdef.entries += (rentry)
-                  val ventry = bool_fun(bdelt.valid.name, bdelt.valid)
-                  cdef.entries += (ventry)
-                }
-                bdelt.bits match {
-                  case bdbits: Bits => {
-                    val entry = bits_fun(hname, bdbits)
-                    cdef.entries += (entry)
-                  }
-                  case bdaggregate: Aggregate => {
-                    // Collect all the inputs and outputs.
-                    val bdinputs = bdaggregate.flatten.filter(_._2.dir == INPUT)
-                    if (bdinputs.length > 0) {
-                      for (bdin <- bdinputs) {
-                        bdin._2 match {
-                          case bdinBool: Bool => {
-                            val entry = bool_fun(hname, bdinBool)
-                            cdef.entries += (entry)
-                          }
-                          case bdinSInt: SInt => {
-                            val entry = sint_fun(hname, bdinSInt)
-                            cdef.entries += (entry)
-                          }
-                          //Also used for Bits
-                          case bdinUInt: UInt => {
-                            val entry = uint_fun(hname, bdinUInt)
-                            cdef.entries += (entry)
-                          }
-                        }
-                      }
-                    }
-                    val bdoutputs = bdaggregate.flatten.filter(_._2.dir == OUTPUT)
-                    if (bdoutputs.length > 0) {
-                      for (bdout <- bdoutputs) {
-                         bdout._2 match {
-                          case bdoutBool: Bool => {
-                            val entry = bool_fun(hname, bdoutBool)
-                            cdef.entries += (entry)
-                          }
-                          case bdoutSInt: SInt => {
-                            val entry = sint_fun(hname, bdoutSInt)
-                            cdef.entries += (entry)
-                          }
-                          //Also used for Bits
-                          case bdoutUInt: UInt => {
-                            val entry = uint_fun(hname, bdoutUInt)
-                            cdef.entries += (entry)
-                          }
-                        }
-                      }
-                    }
-                  }
-                  case _ => badElements(hname) = bdelt
-                }
+                val bdelt_bad = decoupled_fun(bdelt, cdef, name)
+                if (bdelt_bad) badElements(name) = bdelt
               }
               case _ => badElements(hname) = helt
             }
           }
         }
+
+        case vecelt: Vec[_] => {
+          val inputs = vecelt.flatten.filter(_._2.dir == INPUT)
+          for (in <- inputs) {
+            in._2 match {
+              case inBool: Bool => {
+                val entry = bool_fun(name, inBool)
+                cdef.entries += (entry)
+              }
+              case inSInt: SInt => {
+                val entry = sint_fun(name, inSInt)
+                cdef.entries += (entry)
+              }
+              //Also used for Bits
+              case inUInt: UInt => {
+                val entry = uint_fun(name, inUInt)
+                cdef.entries += (entry)
+              }
+              case vecvelt:ValidIO[_] => {
+                val vecvelt_bad = valid_fun(vecvelt, cdef, name)
+                if (vecvelt_bad) badElements(name) = vecvelt
+              }
+              case vecdelt:DecoupledIO[_] => {
+                val vecdelt_bad = decoupled_fun(vecdelt, cdef, name)
+                if (vecdelt_bad) badElements(name) = vecdelt
+              }
+            }
+          }
+          val outputs = vecelt.flatten.filter(_._2.dir == OUTPUT)
+          for (out <- outputs) {
+            out._2 match {
+              case outBool: Bool => {
+                val entry = bool_fun(name, outBool)
+                cdef.entries += (entry)
+              }
+              case outSInt: SInt => {
+                val entry = sint_fun(name, outSInt)
+                cdef.entries += (entry)
+              }
+              //Also used for Bits
+              case outUInt: UInt => {
+                val entry = uint_fun(name, outUInt)
+                cdef.entries += (entry)
+              }
+              case vecvelt:ValidIO[_] => {
+                val vecvelt_bad = valid_fun(vecvelt, cdef, name)
+                if (vecvelt_bad) badElements(name) = vecvelt
+              }
+              case vecdelt:DecoupledIO[_] => {
+                val vecdelt_bad = decoupled_fun(vecdelt, cdef, name)
+                if (vecdelt_bad) badElements(name) = vecdelt
+              }
+            }
+          }
+        }
         case _ => badElements(name) = elt
       }
     }