diff --git a/src/main/scala/Backend.scala b/src/main/scala/Backend.scala
index ddfd1e4c..686e11dc 100644
--- a/src/main/scala/Backend.scala
+++ b/src/main/scala/Backend.scala
@@ -204,6 +204,8 @@ class Backend extends FileSystemUtilities{
       comp dfs {
         case reg: Reg if reg.name.isEmpty =>
           reg setName "R" + reg.component.nextIndex
+        case clk: Clock if clk.name == "" =>
+          clk setName "C" + clk.component.nextIndex
         case mem: Mem[_] if mem.name.isEmpty =>
           mem setName "T" + mem.component.nextIndex
         case node: Node if !node.isTypeNode && node.name.isEmpty && node.compOpt != None =>
@@ -221,6 +223,8 @@ class Backend extends FileSystemUtilities{
       comp dfs {
         case reg: Reg =>
           reg setName namespace.getUniqueName(reg.name)
+        case clk: Clock =>
+          clk setName namespace.getUniqueName(clk.name)
         case mem: Mem[_] =>
           mem setName namespace.getUniqueName(mem.name)
         case node: Node if !node.isTypeNode && !node.isLit && !node.isIo => {
@@ -266,6 +270,8 @@ class Backend extends FileSystemUtilities{
         node.name
       case _: Reg =>
         if (node.named) node.name else "R" + node.emitIndex
+      case _: Clock =>
+        if (node.named) node.name else "C" + node.emitIndex
       case _ =>
         if (node.named) node.name else "T" + node.emitIndex
     }
diff --git a/src/main/scala/Verilog.scala b/src/main/scala/Verilog.scala
index a567ec16..e84d9bc2 100644
--- a/src/main/scala/Verilog.scala
+++ b/src/main/scala/Verilog.scala
@@ -100,10 +100,8 @@ class VerilogBackend extends Backend {
   override def emitRef(node: Node): String = {
     node match {
       case x: Literal => emitLit(x.value, x.needWidth())
-      case _: Reg =>
-        if (node.name != "") node.name else "R" + node.emitIndex
       case _ =>
-        if (node.name != "") node.name else "T" + node.emitIndex
+          super.emitRef(node)
     }
   }
 
diff --git a/src/test/resources/MultiClockSuite_Comp_1.v b/src/test/resources/MultiClockSuite_Comp_1.v
index 9de9480c..870d022b 100644
--- a/src/test/resources/MultiClockSuite_Comp_1.v
+++ b/src/test/resources/MultiClockSuite_Comp_1.v
@@ -1,4 +1,4 @@
-module MultiClockSuite_ClockedSubComp_1(input T0,
+module MultiClockSuite_ClockedSubComp_1(input C0,
     input  io_ready,
     output io_valid
 );
@@ -17,12 +17,12 @@ module MultiClockSuite_ClockedSubComp_1(input T0,
 
   assign io_valid = stored;
 
-  always @(posedge T0) begin
+  always @(posedge C0) begin
     stored <= io_ready;
   end
 endmodule
 
-module MultiClockSuite_Comp_1(input T0,
+module MultiClockSuite_Comp_1(input C0,
     input  io_data0,
     input  io_data1,
     output io_result
@@ -34,7 +34,7 @@ module MultiClockSuite_Comp_1(input T0,
 
   assign T0 = io_data0 & io_data1;
   assign io_result = sub_io_valid;
-  MultiClockSuite_ClockedSubComp_1 sub(.T0(T0),
+  MultiClockSuite_ClockedSubComp_1 sub(.C0(C0),
        .io_ready( T0 ),
        .io_valid( sub_io_valid )
   );