[P0] Conv test numerical value mismatch

[guosran]

Summary

The expected numerical return is not produced. The CPU-visible packet from tile 2 is CMD_COMPLETE with data=0, while the test expects 4200 for an all-ones A/B preload.

Current code has been committed to: zeonica-conv-validation.

Current Evidence

Observed packets:

cpu_pkt: cycle 42145 src 9 cmd 14 data 0
cpu_pkt: cycle 42146 src 2 cmd 14 data 0

Expected sink packet:

src=2 cmd=CMD_COMPLETE data=4200 predicate=1

Received:

src=2 cmd=CMD_COMPLETE data=0 predicate=0

Interpretation

The likely failing area is the final return path around core 2:

• YAML has RETURN_VALUE on core 2 at time_step: 12, index_per_ii: 2, invalid_iterations: 2.
• Generated core 2 config includes:
  • addr 1: OPT_GRT_PRED
  • addr 2: OPT_RET
• The visible src=2,data=0 appears to be the tile completion packet, not a valid RETURN_VALUE carrying the accumulated value.
• Extending total ctrl steps by 20 delayed completion but still returned data=0, so this does not appear to be a simple off-by-one total-cycle cutoff.

Visualization

[tancheng]

how to reproduce this? @guosran

Or you can investigate this first?

(it sounds the return is indeed executed, but the returned value is wrong, implying prologue issue)

[guosran]

The code is on zeonica-conv-validation.

Using yaml file: validation/test/conv/tmp-generated-instructions.yaml

Repro command:

CGRA_USE_VERILATOR=1 CGRA_MAX_CYCLES=43000 \
  pytest cgra/test/CgraRTL_conv4x4_test_from_yaml.py -vv --tb=short -s

Expected return:

src=2 cmd=CMD_COMPLETE data=4200 predicate=1

Observed return:

cpu_pkt: cycle 42145 src 9 cmd 14 data 0
cpu_pkt: cycle 42146 src 2 cmd 14 data 0

The test reaches the return packet, but the returned value is wrong:

expected: src=2 cmd=0e data=00001068.1.0.0
received: src=2 cmd=0e data=00000000.0.0.0

I also checked whether this is a memory preload issue by adding a preload probe:

CGRA_USE_VERILATOR=1 CGRA_PRELOAD_PROBE=1 CGRA_MAX_CYCLES=25000 \
CGRA_PRELOAD_DRAIN_CYCLES=10000 \
  pytest cgra/test/CgraRTL_conv4x4_test_from_yaml.py -vv --tb=short -s

Probe result:

cpu_pkt: cycle 18406 src 0 cmd 11 data 1
cpu_pkt: cycle 18408 src 0 cmd 11 data 1

This probes the A/B base addresses and returns the expected preload value, so the input memory preload path looks valid.

I also tried adding extra drain cycles before starting the kernel and adding extra total control steps. The return still becomes data=0; only the completion cycle shifts later.

It looks consistent with a prologue / predicate / return-value path issue: the RETURN_VALUE instruction executes, but the value/predicate reaching the return is wrong.

[tancheng]

Hi @guosran, why there are two returned values?

[yyan7223]

@guosran, seems there are 2 problems:

1. Assumes the ADD operation below is for the accumulation (as the waveform shows that another ADD is used for the loop indexing)
   https://github.com/guosran/VectorCGRA/blob/3b546dacaa2bb2bad832bef485449810640787b8/validation/test/conv/tmp-generated-instructions.yaml#L136-L152
   Can you double check how the accumulation result of current iteration is routed or locally registered to provide the input for the accumulation of the next iteration?

2. How you send configs to tiles if:
   https://github.com/guosran/VectorCGRA/blob/3b546dacaa2bb2bad832bef485449810640787b8/cgra/test/CgraRTL_conv4x4_test_from_yaml.py#L144
   immediately after preloading the data.

[tancheng]

@guosran any update on this~?

[guosran]

@guosran any update on this~?

Still investigating.

Preload looks valid. The failure now appears to be in the final predicate/value routing.