diff --git a/.gitignore b/.gitignore
index beabe4bd..4cb7754b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -30,7 +30,7 @@ flash.img*
compile.sh
src/platform/__board.rs
.config
+.cursorrules
.vscode/extensions.json
-
# systemtest
rootfs1.zip*
\ No newline at end of file
diff --git a/.vscode/settings-example.json b/.vscode/settings-example.json
index 0d5c1d9e..721b79ac 100644
--- a/.vscode/settings-example.json
+++ b/.vscode/settings-example.json
@@ -14,6 +14,6 @@
// "rust-analyzer.cargo.target": "riscv64gc-unknown-none-elf",
// "rust-analyzer.cargo.target": "loongarch64-unknown-none",
"rust-analyzer.cargo.features": [
- "gicv3 pl011 iommu pci pt_layout_qemu"
+ "gicv3 pl011 iommu pci"
]
}
\ No newline at end of file
diff --git a/CHANGELOG.md b/CHANGELOG.md
index 39de98d6..b5feeac9 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -2,19 +2,31 @@
> ⚠️ Please update this file for any changes to the hvisor project along with your name and GitHub profile link under the CURRENT section.
-## CURRENT - v0.1.2
+## CURRENT - v0.2
+
+- [platform] **riscv64**: Add support for Megrez / Milk-V platforms (zone0/zone1 boot, uart2, virtio, Ethernet, SATA passthrough, NPU, updated device-tree). ([Jingyu Liu](https://github.com/liulog))
+- [platform] **riscv64**: Add support for SiFive HiFive Premier P550. ([Jingyu Liu](https://github.com/liulog))
+- [platform] **aarch64**: Add support for Phytium-Pi. ([Zixu Bao](https://github.com/Baozixu99))
+- [platform] **aarch64**: Improve QEMU GICv2/GICv3 configurations and add zone1-linux support. ([agicy](https://github.com/agicy))
+- [platform] **loongarch64**: Add support for Loongson 3A5 / 3A6 platforms and improve clock and trap handling. ([wheatfox](https://github.com/enkerewpo))
+- [feature] Add **aarch32** support. ([Guowei Li](https://github.com/KouweiLee))
+- [feature] **riscv64** enhancements: g-stage dynamic detection, eic770x_soc, and syscrg emulation. ([Jingyu Liu](https://github.com/liulog))
+- [infra] Unify UART / MPIDR mapping, centralize IOMMU configuration, remove redundant arch feature flags, and tidy Cargo/zone/hypercall code. ([Nehckl](https://github.com/Inquisitor-201), [Ren HangQi](https://github.com/ForeverYolo))
+- [infra/tool] **aarch64**: Optimized the structure of GIC parameters ([Ren HangQi](https://github.com/ForeverYolo))
+- [ci/misc] Update dependencies, add ccache support, and improve build/tooling workflows. ([Jingyu Liu](https://github.com/liulog))
+
+## History Release
+
+### hvisor v0.1.2
- [feature] riscv64: add virtio support in qemu-aia to boot zone1. ([CHonghao](https://github.com/CHonghaohao))
- [feature] pci support for loongarch64 ([wheatfox](https://github.com/enkerewpo), [Zhongkai Xu](https://github.com/ZhongkaiXu))
- [ci] support running CI with the latest hvisor-tool and the configuration files in hvisor ([CHonghao](https://github.com/CHonghaohao))
-- [feature] enable dynamic CPU detection for ARM platforms via device tree ([GuanTouYu](https://github.com/FlowerBlackG))
- [platform] support for rk3568 ([dallasxy](https://github.com/dallasxy))
- [feature] riscv64: add virtio support ([Jingyu Liu](https://github.com/liulog))
- [feature] riscv64: add vplic struct ([Jingyu Liu](https://github.com/liulog))
- [feature] riscv64: add aclint support ([Jingyu Liu](https://github.com/liulog))
-## History Release
-
### hvisor v0.1.1
- [platform] seperate board definitions into `platform` folder with re-designed cargo feature system for hvisor ([wheatfox](https://github.com/enkerewpo))
diff --git a/Cargo.lock b/Cargo.lock
index fbc66c14..c59334ea 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -61,9 +61,9 @@ checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a"
[[package]]
name = "bitflags"
-version = "2.5.0"
+version = "2.9.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "cf4b9d6a944f767f8e5e0db018570623c85f3d925ac718db4e06d0187adb21c1"
+checksum = "1b8e56985ec62d17e9c1001dc89c88ecd7dc08e47eba5ec7c29c7b5eeecde967"
[[package]]
name = "bitmap-allocator"
@@ -94,6 +94,12 @@ dependencies = [
"spin 0.7.1",
]
+[[package]]
+name = "byteorder"
+version = "1.5.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1fd0f2584146f6f2ef48085050886acf353beff7305ebd1ae69500e27c67f64b"
+
[[package]]
name = "cfg-if"
version = "1.0.0"
@@ -122,42 +128,29 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "361a90feb7004eca4019fb28352a9465666b24f840f5c3cddf0ff13920590b89"
[[package]]
-name = "endian-type-rs"
-version = "0.1.4"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b6419a5c75e40011b9fe0174db3fe24006ab122fbe1b7e9cc5974b338a755c76"
-
-[[package]]
-name = "fallible-iterator"
-version = "0.2.0"
+name = "funty"
+version = "2.0.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4443176a9f2c162692bd3d352d745ef9413eec5782a80d8fd6f8a1ac692a07f7"
-
-[[package]]
-name = "fdt"
-version = "0.1.5"
+checksum = "e6d5a32815ae3f33302d95fdcb2ce17862f8c65363dcfd29360480ba1001fc9c"
[[package]]
-name = "fdt-rs"
-version = "0.4.5"
+name = "hash32"
+version = "0.3.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "581d3afdd654deb68c19fcbe4bc411910cc64067d4a13d8637bda7722cb9c2ea"
+checksum = "47d60b12902ba28e2730cd37e95b8c9223af2808df9e902d4df49588d1470606"
dependencies = [
- "endian-type-rs",
- "fallible-iterator",
- "memoffset",
- "num-derive",
- "num-traits",
- "rustc_version",
- "static_assertions",
- "unsafe_unwrap",
+ "byteorder",
]
[[package]]
-name = "funty"
-version = "2.0.0"
+name = "heapless"
+version = "0.8.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e6d5a32815ae3f33302d95fdcb2ce17862f8c65363dcfd29360480ba1001fc9c"
+checksum = "0bfb9eb618601c89945a70e254898da93b13be0388091d42117462b265bb3fad"
+dependencies = [
+ "hash32",
+ "stable_deref_trait",
+]
[[package]]
name = "hvisor"
@@ -165,14 +158,13 @@ version = "0.1.0"
dependencies = [
"aarch64-cpu",
"bit_field 0.10.2",
- "bitflags 2.5.0",
+ "bitflags 2.9.1",
"bitmap-allocator",
"bitvec",
"buddy_system_allocator",
"cfg-if",
"cortex-a",
- "fdt",
- "fdt-rs",
+ "heapless",
"lazy_static",
"log",
"loongArch64",
@@ -187,7 +179,7 @@ dependencies = [
"riscv-peripheral",
"sbi-rt",
"sbi-spec 0.0.8",
- "spin 0.9.8",
+ "spin 0.10.0",
"tock-registers",
"x2apic",
"x86",
@@ -221,12 +213,12 @@ checksum = "90ed8c1e510134f979dbc4f070f87d4313098b704861a105fe34231c70a3901c"
[[package]]
name = "loongArch64"
-version = "0.2.4"
+version = "0.2.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "dd48200d465466664e4e899b204b77b5447d60b1ababdad3a2c49ae85417b552"
+checksum = "7c9f0d275c70310e2a9d2fc23250c5ac826a73fa828a5f256401f85c5c554283"
dependencies = [
"bit_field 0.10.2",
- "bitflags 1.3.2",
+ "bitflags 2.9.1",
]
[[package]]
@@ -235,35 +227,6 @@ version = "2.7.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "6c8640c5d730cb13ebd907d8d04b52f55ac9a2eec55b440c8892f40d56c76c1d"
-[[package]]
-name = "memoffset"
-version = "0.5.6"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "043175f069eda7b85febe4a74abbaeff828d9f8b448515d3151a14a3542811aa"
-dependencies = [
- "autocfg",
-]
-
-[[package]]
-name = "num-derive"
-version = "0.3.3"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "876a53fff98e03a936a674b29568b0e605f06b29372c2489ff4de23f1949743d"
-dependencies = [
- "proc-macro2",
- "quote",
- "syn 1.0.109",
-]
-
-[[package]]
-name = "num-traits"
-version = "0.2.19"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "071dfc062690e90b734c0b2273ce72ad0ffa95f0c74596bc250dcfd960262841"
-dependencies = [
- "autocfg",
-]
-
[[package]]
name = "numeric-enum-macro"
version = "0.2.0"
@@ -389,7 +352,7 @@ checksum = "e8c4aa1ea1af6dcc83a61be12e8189f9b293c3ba5a487778a4cd89fb060fdbbc"
dependencies = [
"proc-macro2",
"quote",
- "syn 2.0.100",
+ "syn",
]
[[package]]
@@ -490,29 +453,18 @@ checksum = "13287b4da9d1207a4f4929ac390916d64eacfe236a487e9a9f5b3be392be5162"
[[package]]
name = "spin"
-version = "0.9.8"
+version = "0.10.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "6980e8d7511241f8acf4aebddbb1ff938df5eebe98691418c4468d0b72a96a67"
+checksum = "d5fe4ccb98d9c292d56fec89a5e07da7fc4cf0dc11e156b41793132775d3e591"
dependencies = [
"lock_api",
]
[[package]]
-name = "static_assertions"
-version = "1.1.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a2eb9349b6444b326872e140eb1cf5e7c522154d69e7a0ffb0fb81c06b37543f"
-
-[[package]]
-name = "syn"
-version = "1.0.109"
+name = "stable_deref_trait"
+version = "1.2.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "72b64191b275b66ffe2469e8af2c1cfe3bafa67b529ead792a6d0160888b4237"
-dependencies = [
- "proc-macro2",
- "quote",
- "unicode-ident",
-]
+checksum = "a8f112729512f8e442d81f95a8a7ddf2b7c6b8a1a6f509a95864142b30cab2d3"
[[package]]
name = "syn"
@@ -543,12 +495,6 @@ version = "1.0.18"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "5a5f39404a5da50712a4c1eecf25e90dd62b613502b7e925fd4e4d19b5c96512"
-[[package]]
-name = "unsafe_unwrap"
-version = "0.1.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1230ec65f13e0f9b28d789da20d2d419511893ea9dac2c1f4ef67b8b14e5da80"
-
[[package]]
name = "volatile"
version = "0.4.6"
diff --git a/Cargo.toml b/Cargo.toml
index 69e9e842..f61cca26 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -7,7 +7,7 @@ edition = "2021"
[dependencies]
log = "0.4"
-spin = "0.9"
+spin = "0.10.0"
bitflags = "2.1"
bit_field = "0.10"
numeric-enum-macro = "0.2"
@@ -15,15 +15,11 @@ buddy_system_allocator = "0.8"
tock-registers = "0.8"
lazy_static = { version = "1.4", features = ["spin_no_std"] }
bitmap-allocator = { git = "https://github.com/rcore-os/bitmap-allocator", rev = "03bd9909" }
-fdt = { path = "./vendor/fdt" }
qemu-exit = "3.0.2"
cortex-a = "8.1.1"
cfg-if = "1.0"
bitvec = { version="1.0.1", default-features = false, features = ["atomic", "alloc"] }
-
-[dependencies.fdt-rs]
-version = "0.4.5"
-default-features = false
+heapless = { version = "0.8.0 "}
[target.'cfg(target_arch = "aarch64")'.dependencies]
aarch64-cpu = "9.4.0"
@@ -31,7 +27,7 @@ psci = { version = "0.1.0", default-features = false, features = ["smc"]}
[target.'cfg(target_arch = "riscv64")'.dependencies]
sbi-rt = { version = "0.0.3", features = ["legacy"] }
-sbi-spec = "0.0.8"
+sbi-spec = { version = "0.0.8", features = ["legacy"]}
riscv = "0.13.0"
riscv_h = { package = "riscv", git = "https://github.com/rcore-os/riscv", features = ["inline-asm"] }
riscv-decode = "0.2.1"
@@ -39,7 +35,7 @@ riscv-peripheral = "0.2.1"
riscv-pac = "0.2.0"
[target.'cfg(target_arch = "loongarch64")'.dependencies]
-loongArch64 = "0.2.4"
+loongArch64 = "0.2.5"
[target.'cfg(target_arch = "x86_64")'.dependencies]
x86 = "0.52.0"
@@ -62,20 +58,8 @@ pl011 = []
xuartps = []
imx_uart = []
uart_16550 = []
-
-# pagetable layout
-pt_layout_qemu = []
-pt_layout_rk3568 = []
-pt_layout_rk3588 = []
-pt_layout_zcu102 = []
-
-# cpu
-mpidr_rockchip = []
-
-# uart infos
-uart_base_rk3568 = []
-uart_base_rk3588 = []
-uart_base_ok6254 = []
+sifive_ccache = []
+eic7700_sysreg = []
############## riscv64 #############
# irqchip driver
@@ -84,13 +68,20 @@ aia = []
aclint = []
# extensions
sstc = []
+# platform specific
+eic770x_soc = []
+
########### loongarch64 ############
# irqchip driver
loongson_7a2000 = []
# uart driver
loongson_uart = []
+# cpu (not used for now)
+loongson_3a5000 = []
+loongson_3a6000 = []
[profile.dev]
# panic = "abort" # avoid cargo test failure, this is a bug of cargo
debug = 2
+opt-level = 0
\ No newline at end of file
diff --git a/README-zh.md b/README-zh.md
index 4d4949ff..45c0c6ed 100644
--- a/README-zh.md
+++ b/README-zh.md
@@ -30,23 +30,28 @@ hvisor 是一个用 Rust 实现的 Type-1 裸机虚拟机监控器，采用分
## 设备支持
-| **类别** | **设备** | **支持架构** | **备注 |
-| ------------------ | --------------------- | ----------------------------------- | ---------------------------------------- |
-| **Virtio 设备** | virtio-blk | `aarch64`, `riscv64` | |
-| | virtio-net | `aarch64` | |
-| | virtio-console | `aarch64`, `riscv64`, `loongarch64` | |
-| | virtio-gpu | `aarch64` | 仅支持 QEMU |
-| **串行设备/UARTs** | PL011 | `aarch64` | |
-| | imx-uart | `aarch64` | NXP i.MX8MP |
-| | NS16550A | `loongarch64` | |
-| | xuartps | `aarch64` | Xilinx Ultrascale+ MPSoC ZCU102 |
+| **类别** | **设备** | **支持架构** | **备注** |
+| ------------------ | --------------------- | ----------------------------------- | -------------------------------------- |
+| **Virtio 设备** | virtio-blk | `aarch64`, `riscv64`, `loongarch64` | |
+| | virtio-net | `aarch64` | |
+| | virtio-console | `aarch64`, `riscv64`, `loongarch64` | |
+| | virtio-gpu | `aarch64` | 仅支持 QEMU |
+| **串行设备/UARTs** | PL011 | `aarch64` | |
+| | imx-uart | `aarch64` | NXP i.MX8MP |
+| | NS16550A | `loongarch64` | |
+| | xuartps | `aarch64` | Xilinx Ultrascale+ MPSoC ZCU102 |
| | uart16550 | `aarch64` | Rockchip RK3568/RK3588, Forlinx OK6254-C |
-| **中断控制器** | GIC irq controller | `aarch64` | |
-| | 7A2000 irq controller | `loongarch64` | |
-| | PLIC | `riscv64` | |
-| | AIA | `riscv64` | 仅支持 MSI 模式 |
-| **PCIe 直通** | PCIe | `aarch64`, `riscv64` | |
-| **GPU 直通** | GPU | `aarch64` | NXP i.MX8MP |
+| **中断控制器** | GIC irq controller | `aarch64` | |
+| | 7A2000 irq controller | `loongarch64` | |
+| | PLIC | `riscv64` | |
+| | AIA | `riscv64` | 仅支持 MSI 模式 |
+| **设备直通(Zone0)** | All | All | |
+| **设备直通(ZoneU)** | PCIe | `aarch64`, `riscv64`, `loongarch64` | 待测试 |
+| | GPU / HDMI | `aarch64`, `loongarch64` | NXP i.MX8MP, 3A6000 |
+| | eMMC | `aarch64`, `riscv64` | NXP i.MX8MP |
+| | USB | `aarch64` | NXP i.MX8MP |
+| | SATA | `riscv64`, `loongarch64` | megrez, 3A6000 |
+| | Ethernet | `aarch64`, `riscv64`, `loongarch64` | NXP i.MX8MP, megrez, 3A6000 |
## 板卡支持
@@ -58,26 +63,59 @@ hvisor 是一个用 Rust 实现的 Type-1 裸机虚拟机监控器，采用分
- [x] Rockchip RK3588
- [x] Rockchip RK3568
- [x] Forlinx OK6254-C
+- [x] Phytium Pi
### riscv64
- [x] QEMU virt riscv64
+- [x] Milk-V Megrez
+- [x] Sifive Hifive Premier P550
- [ ] FPGA 香山（昆明湖）on S2C Prodigy S7-19PS-2
-- [ ] FPGA RocketChip on Xilinx Ultrascale+ MPSoC ZCU102
### loongarch64
-- [x] Loongson 3A5000+7A2000
-- [ ] Loongson 3A6000
+- [x] Loongson 3A5000（7A2000 桥片）
+- [x] Loongson 3A6000（7A2000 桥片）
+
+### x86_64
+
+- [ ] QEMU virt x86_64
+- [ ] ASUS NUC14MNK
+
+## Guest OS 支持
+
+- [x] Linux 6.13
+- [x] Zephyr AArch64
+- [x] Zephyr AArch32
+- [x] RT-Thread
+- [ ] Android
+- [ ] OpenHarmony
## 开始使用
-请参阅 hvisor 文档中的 **《hvisor 快速上手指南》**，了解所有支持平台的构建和运行教程：[hvisor 文档](https://hvisor.syswonder.org/)
+请参阅 hvisor 文档，获取所有支持平台的快速上手指南、构建和运行说明：[hvisor 文档](https://hvisor.syswonder.org/)
## 路线图
-- 支持在 NXP i.MX8MP 硬件平台上实现 Android nonroot
-- 支持在 `x86_64` 架构上运行 hvisor
+- 支持 `x86_64` 架构
+- 支持 Android
+- 支持 OpenHarmony
+- 支持 ARMv9
+- 支持 GICv4
+- 支持缓存着色
+- 支持 SR-IOV
+- 支持 USB / NPU zoneU 直通
+- 支持 Nvidia GPU zoneU 直通
+- Web Management tool
+- 设备树配置工具
+- 支持 Nvidia Orin
+- 支持 Nvidia Thor
+- 支持 Raspberry Pi 5
+- 支持 IOMMU 虚拟化
+- 支持 PCIe 总线虚拟化
+- 支持 时钟控制器 虚拟化
+- 支持 pinctrl 虚拟化
+- 支持无 zone0 启动 zoneU / zoneR
## 致谢
diff --git a/README.md b/README.md
index 098a054e..4ff31974 100644
--- a/README.md
+++ b/README.md
@@ -9,7 +9,6 @@
-
@@ -20,7 +19,7 @@ hvisor is a Type-1 bare-metal virtual machine monitor implemented in Rust, featu
## Features
- **Separation Kernel Design**: The virtual machine is divided into three regions: zone0 (management zone), zoneU (user zone), and zoneR (real-time zone), with strict isolation between them.
-- **Simple and Lightweight**: hvisor is implemented in Rust with a minimal design.
+- **Simple and Lightweight**: Implemented in Rust with a minimal design.
- CPU Virtualization: Static partitioning of physical CPUs (pCPUs), without dynamic scheduling.
- Memory Virtualization: Pre-allocated virtual machine memory space via configuration files.
- I/O Virtualization: Supports device passthrough and virtio paravirtualization.
@@ -30,23 +29,28 @@ hvisor is a Type-1 bare-metal virtual machine monitor implemented in Rust, featu
## Device Support
-| **Category** | **Device** | **Supported Architectures** | **Notes** |
-| ------------------------- | --------------------- | ------------------------------------ | ---------------------------------------- |
-| **Virtio Devices** | virtio-blk | `aarch64`, `riscv64`, `loongarch64` | |
-| | virtio-net | `aarch64` | |
-| | virtio-console | `aarch64`, `riscv64`, `loongarch64` | |
-| | virtio-gpu | `aarch64` | Only supports QEMU |
-| **Serial Devices/UARTs** | PL011 | `aarch64` | |
-| | imx-uart | `aarch64` | NXP i.MX8MP |
-| | NS16550A | `loongarch64` | |
-| | xuartps | `aarch64` | Xilinx Ultrascale+ MPSoC ZCU102 |
-| | uart16550 | `aarch64` | Rockchip RK3568/RK3588, Forlinx OK6254-C |
-| **Interrupt Controllers** | GIC irq controller | `aarch64` | |
-| | 7A2000 irq controller | `loongarch64` | |
-| | PLIC | `riscv64` | |
-| | AIA | `riscv64` | Only supports MSI mode |
-| **PCIe Passthrough** | PCIe | `aarch64`, `riscv64`, `loongarch64` | |
-| **GPU Passthrough** | GPU | `aarch64` | NXP i.MX8MP |
+| **Category** | **Device** | **Supported Architectures** | **Notes** |
+|----------------------------------|------------------------|---------------------------------------|----------------------------------------|
+| **Virtio Devices** | virtio-blk | `aarch64`, `riscv64`, `loongarch64` | |
+| | virtio-net | `aarch64` | |
+| | virtio-console | `aarch64`, `riscv64`, `loongarch64` | |
+| | virtio-gpu | `aarch64` | QEMU only |
+| **Serial Devices/UARTs** | PL011 | `aarch64` | |
+| | imx-uart | `aarch64` | NXP i.MX8MP |
+| | NS16550A | `loongarch64` | |
+| | xuartps | `aarch64` | Xilinx Ultrascale+ MPSoC ZCU102 |
+| | uart16550 | `aarch64` | Rockchip RK3568/RK3588, Forlinx OK6254-C|
+| **Interrupt Controllers** | GIC irq controller | `aarch64` | |
+| | 7A2000 irq controller | `loongarch64` | |
+| | PLIC | `riscv64` | |
+| | AIA | `riscv64` | MSI mode only |
+| **Device Passthrough(Zone0)** | All | All | |
+| **Device Passthrough(ZoneU)** | PCIe | `aarch64`, `riscv64`, `loongarch64` | Testing needed |
+| | GPU / HDMI | `aarch64`, `loongarch64` | NXP i.MX8MP, 3A6000 |
+| | eMMC | `aarch64`, `riscv64` | NXP i.MX8MP |
+| | USB | `aarch64` | NXP i.MX8MP |
+| | SATA | `riscv64`, `loongarch64` | megrez, 3A6000 |
+| | Ethernet | `aarch64`, `riscv64`, `loongarch64` | NXP i.MX8MP, megrez, 3A6000 |
## Supported Boards
@@ -58,27 +62,60 @@ hvisor is a Type-1 bare-metal virtual machine monitor implemented in Rust, featu
- [x] Rockchip RK3588
- [x] Rockchip RK3568
- [x] Forlinx OK6254-C
+- [x] Phytium Pi
### riscv64
- [x] QEMU virt riscv64
+- [x] Milk-V Megrez
+- [x] Sifive Hifive Premier P550
- [ ] FPGA XiangShan(KunMingHu) on S2C Prodigy S7-19PS-2
-- [ ] FPGA RocketChip on Xilinx Ultrascale+ MPSoC ZCU102
### loongarch64
- [x] Loongson 3A5000 (7A2000 bridge chip)
-- [ ] Loongson 3A6000 (7A2000 bridge chip)
+- [x] Loongson 3A6000 (7A2000 bridge chip)
+
+### x86_64
+
+- [ ] QEMU virt x86_64
+- [ ] ASUS NUC14MNK
+
+## Supported Guest OS
+
+- [x] Linux 6.13
+- [x] Zephyr AArch64
+- [x] Zephyr AArch32
+- [x] RT-Thread
+- [ ] Android
+- [ ] OpenHarmony
## Getting Started
-Please refer to the hvisor documentation for the quick start guide, which includes build and run instructions for all supported platforms: [hvisor Documentation](https://hvisor.syswonder.org/)
+Please refer to the hvisor documentation for quick start guides, build and run instructions for all supported platforms: [hvisor Documentation](https://hvisor.syswonder.org/)
## Roadmap
-- Support for Android non-root on the NXP i.MX8MP hardware platform
-- Support for running hvisor on the `x86_64` architecture
+- Support for `x86_64` architecture
+- Support for Android
+- Support for OpenHarmony
+- Support for ARMv9
+- Support for GICv4
+- Support for Cache Coloring
+- Support for SR-IOV
+- Support for USB / NPU zoneU passthrough
+- Support for Nvidia GPU zoneU passthrough
+- Web Management tool
+- Device Tree configuration tool
+- Support for Nvidia Orin
+- Support for Nvidia Thor
+- Support for Raspberry Pi 5
+- Support for IOMMU virtualization
+- Support for PCIe bus virtualization
+- Support for Clock Controller virtualization
+- Support for pinctrl virtualization
+- Support for booting zoneU / zoneR without zone0
## Acknowledgments
-Some implementations of this project reference [RVM1.5](https://github.com/rcore-os/RVM1.5) and [jailhouse](https://github.com/siemens/jailhouse).
+Some implementations of this project reference [RVM1.5](https://github.com/rcore-os/RVM1.5) and [jailhouse](https://github.com/siemens/jailhouse).
\ No newline at end of file
diff --git a/platform/aarch64/imx8mp/board.rs b/platform/aarch64/imx8mp/board.rs
index 555001f0..63a29473 100644
--- a/platform/aarch64/imx8mp/board.rs
+++ b/platform/aarch64/imx8mp/board.rs
@@ -13,11 +13,36 @@
//
// Authors:
//
-use crate::{arch::zone::HvArchZoneConfig, config::*};
+use crate::{
+ arch::{
+ mmu::MemoryType,
+ zone::{GicConfig, Gicv3Config, HvArchZoneConfig},
+ },
+ config::*,
+};
pub const BOARD_NAME: &str = "imx8mp";
pub const BOARD_NCPUS: usize = 4;
+pub const BOARD_UART_BASE: u64 = 0x30890000;
+
+#[rustfmt::skip]
+pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [
+ 0x0, // cpu0
+ 0x1, // cpu1
+ 0x2, // cpu2
+ 0x3, // cpu3
+];
+
+/// The physical memory layout of the board.
+/// Each address should align to 2M (0x200000).
+/// Addresses must be in ascending order.
+#[rustfmt::skip]
+pub const BOARD_PHYSMEM_LIST: &[(u64, u64, MemoryType)] = &[
+ // ( start, end, type)
+ ( 0x0, 0x40000000, MemoryType::Device),
+ ( 0x40000000, 0x100000000, MemoryType::Normal),
+];
pub const ROOT_ZONE_DTB_ADDR: u64 = 0xa0000000;
pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0xa0400000;
@@ -90,19 +115,15 @@ pub const ROOT_ZONE_IRQS: [u32; 28] = [
];
pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig {
- gicd_base: 0x38800000,
- gicd_size: 0x10000,
- gicr_base: 0x38880000,
- gicr_size: 0xc0000,
- gicc_base: 0,
- gicc_size: 0,
- gicc_offset: 0x0,
- gich_base: 0,
- gich_size: 0,
- gicv_base: 0,
- gicv_size: 0,
- gits_base: 0,
- gits_size: 0,
+ is_aarch32: 0,
+ gic_config: GicConfig::Gicv3(Gicv3Config {
+ gicd_base: 0x38800000,
+ gicd_size: 0x10000,
+ gicr_base: 0x38880000,
+ gicr_size: 0xc0000,
+ gits_base: 0,
+ gits_size: 0,
+ }),
};
pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = [];
diff --git a/platform/aarch64/ok6254-c/board.rs b/platform/aarch64/ok6254-c/board.rs
index 862f0292..a3b76054 100644
--- a/platform/aarch64/ok6254-c/board.rs
+++ b/platform/aarch64/ok6254-c/board.rs
@@ -14,10 +14,36 @@
// Authors:
//
-use crate::{arch::zone::HvArchZoneConfig, config::*};
+use crate::{
+ arch::{
+ mmu::MemoryType,
+ zone::{GicConfig, Gicv3Config, HvArchZoneConfig},
+ },
+ config::*,
+};
pub const BOARD_NAME: &str = "ok6254";
pub const BOARD_NCPUS: usize = 4;
+pub const BOARD_UART_BASE: u64 = 0x2800000;
+
+
+#[rustfmt::skip]
+pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [
+ 0x0, // cpu0
+ 0x1, // cpu1
+ 0x2, // cpu2
+ 0x3, // cpu3
+];
+
+/// The physical memory layout of the board.
+/// Each address should align to 2M (0x200000).
+/// Addresses must be in ascending order.
+#[rustfmt::skip]
+pub const BOARD_PHYSMEM_LIST: &[(u64, u64, MemoryType)] = &[
+ // ( start, end, type)
+ ( 0x0, 0x80000000, MemoryType::Device),
+ ( 0x80000000, 0x100000000, MemoryType::Normal),
+];
pub const ROOT_ZONE_DTB_ADDR: u64 = 0x88000000; // DTB load address
pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x82000000; // kernel load address
@@ -106,19 +132,15 @@ pub const ROOT_ZONE_IRQS: [u32; 13] = [
];
pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig {
- gicd_base: 0x1800000,
- gicd_size: 0x10000,
- gicr_base: 0x1880000,
- gicr_size: 0xc0000,
- gicc_base: 0x0,
- gicc_size: 0x0,
- gicc_offset: 0x0,
- gich_base: 0x0,
- gich_size: 0x0,
- gicv_base: 0x0,
- gicv_size: 0x00000,
- gits_base: 0x1820000,
- gits_size: 0x10000,
+ is_aarch32: 0,
+ gic_config: GicConfig::Gicv3(Gicv3Config {
+ gicd_base: 0x1800000,
+ gicd_size: 0x10000,
+ gicr_base: 0x1880000,
+ gicr_size: 0xc0000,
+ gits_base: 0,
+ gits_size: 0,
+ }),
};
pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = [];
diff --git a/platform/aarch64/ok6254-c/cargo/features b/platform/aarch64/ok6254-c/cargo/features
index f646f8e2..afa59489 100644
--- a/platform/aarch64/ok6254-c/cargo/features
+++ b/platform/aarch64/ok6254-c/cargo/features
@@ -1,3 +1,2 @@
gicv3
uart_16550
-uart_base_ok6254
diff --git a/platform/aarch64/phytium-pi/board.rs b/platform/aarch64/phytium-pi/board.rs
new file mode 100644
index 00000000..aa102509
--- /dev/null
+++ b/platform/aarch64/phytium-pi/board.rs
@@ -0,0 +1,149 @@
+// Copyright (c) 2025 Syswonder
+// hvisor is licensed under Mulan PSL v2.
+// You can use this software according to the terms and conditions of the Mulan PSL v2.
+// You may obtain a copy of Mulan PSL v2 at:
+// http://license.coscl.org.cn/MulanPSL2
+// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+// FIT FOR A PARTICULAR PURPOSE.
+// See the Mulan PSL v2 for more details.
+//
+// Syswonder Website:
+// https://www.syswonder.org
+//
+// Authors:
+//
+use crate::{
+ arch::{
+ mmu::MemoryType,
+ zone::{GicConfig, Gicv3Config, HvArchZoneConfig},
+ },
+ config::*,
+};
+
+pub const BOARD_NAME: &str = "phytium-pi";
+
+pub const BOARD_NCPUS: usize = 4;
+pub const BOARD_UART_BASE: u64 = 0x2800d000;
+
+#[rustfmt::skip]
+pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [
+ 0x200, // cpu0
+ 0x201, // cpu1
+ 0x00, // cpu2
+ 0x100, // cpu3
+];
+
+/// The physical memory layout of the board.
+/// Each address should align to 2M (0x200000).
+/// Addresses must be in ascending order.
+#[rustfmt::skip]
+pub const BOARD_PHYSMEM_LIST: &[(u64, u64, MemoryType)] = &[
+ // ( start, end, type)
+ ( 0x0, 0x40000000, MemoryType::Device),
+ ( 0x40000000, 0x100000000, MemoryType::Normal),
+];
+
+pub const ROOT_ZONE_DTB_ADDR: u64 = 0xa0000000;
+pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0xa0400000;
+pub const ROOT_ZONE_ENTRY: u64 = 0xa0400000;
+pub const ROOT_ZONE_CPUS: u64 = (1 << 1) | (1 << 0);
+
+pub const ROOT_ZONE_NAME: &str = "root-linux";
+
+pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 11] = [
+ // ram
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_RAM,
+ physical_start: 0x80000000,
+ virtual_start: 0x80000000,
+ size: 0x80000000,
+ },
+ // soc@0
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x28000000,
+ virtual_start: 0x28000000,
+ size: 0x00100000,
+ },
+ //iommu
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x30000000,
+ virtual_start: 0x30000000,
+ size: 0x800000,
+ },
+ // ethernet0
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x3200c000,
+ virtual_start: 0x3200c000,
+ size: 0x00002000, // 8KB
+ },
+ // USB
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x31800000, // usb2@31800000
+ virtual_start: 0x31800000,
+ size: 0x00080000, // 512KB
+ },
+ // USB2 @32800000 - Host Mode
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x32800000,
+ virtual_start: 0x32800000,
+ size: 0x00040000, // 256KB
+ },
+ // USB2 @32840000 - Host Mode
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x32840000,
+ virtual_start: 0x32840000,
+ size: 0x00040000, // 256KB
+ },
+ // USB3 @31a08000 - XHCI Controller
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x31a08000,
+ virtual_start: 0x31a08000,
+ size: 0x00018000, // 96KB
+ },
+ // USB3 @31a28000 - XHCI Controller
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x31a28000,
+ virtual_start: 0x31a28000,
+ size: 0x00018000, // 96KB
+ },
+ //mailbox
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x32a00000,
+ virtual_start: 0x32a00000,
+ size: 0x1000,
+ },
+ //sram
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x32a10000,
+ virtual_start: 0x32a10000,
+ size: 0x2000,
+ },
+];
+//46-usb2,54-mailbox 64-usb2,87-net,104、105-mmc,116-uart,133、138-i2c,191-spi
+pub const ROOT_ZONE_IRQS: [u32; 14] =
+ [46, 54, 64, 65, 75, 76, 78, 87, 104, 105, 116, 133, 138, 191];
+
+pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig {
+ is_aarch32: 0,
+ gic_config: GicConfig::Gicv3(Gicv3Config {
+ gicd_base: 0x30800000,
+ gicd_size: 0x20000,
+ gicr_base: 0x30880000,
+ gicr_size: 0x80000,
+ gits_base: 0,
+ gits_size: 0,
+ }),
+};
+
+pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = [];
diff --git a/platform/aarch64/phytium-pi/cargo/config.template.toml b/platform/aarch64/phytium-pi/cargo/config.template.toml
new file mode 100644
index 00000000..1f1cd637
--- /dev/null
+++ b/platform/aarch64/phytium-pi/cargo/config.template.toml
@@ -0,0 +1,6 @@
+[target.aarch64-unknown-none]
+rustflags = [
+ "-Clink-arg=-Tplatform/__ARCH__/__BOARD__/linker.ld",
+ "-Ctarget-feature=+v8a,+strict-align,-neon,-fp-armv8",
+ "-Cforce-frame-pointers=yes",
+]
\ No newline at end of file
diff --git a/platform/aarch64/phytium-pi/cargo/features b/platform/aarch64/phytium-pi/cargo/features
new file mode 100644
index 00000000..416c6913
--- /dev/null
+++ b/platform/aarch64/phytium-pi/cargo/features
@@ -0,0 +1,2 @@
+gicv3
+pl011
\ No newline at end of file
diff --git a/platform/aarch64/phytium-pi/configs/zone1-linux-virtio.json b/platform/aarch64/phytium-pi/configs/zone1-linux-virtio.json
new file mode 100644
index 00000000..88352d9a
--- /dev/null
+++ b/platform/aarch64/phytium-pi/configs/zone1-linux-virtio.json
@@ -0,0 +1,31 @@
+{
+ "zones": [
+ {
+ "id": 1,
+ "memory_region": [
+ {
+ "zone0_ipa": "0xb0000000",
+ "zonex_ipa": "0xb0000000",
+ "size": "0x30000000"
+ }
+ ],
+ "devices": [
+ {
+ "type": "blk",
+ "addr": "0xa003c00",
+ "len": "0x200",
+ "irq": 78,
+ "img": "rootfs2.ext4",
+ "status": "enable"
+ },
+ {
+ "type": "console",
+ "addr": "0xa003800",
+ "len": "0x200",
+ "irq": 76,
+ "status": "enable"
+ }
+ ]
+ }
+ ]
+}
diff --git a/platform/aarch64/phytium-pi/configs/zone1-linux.json b/platform/aarch64/phytium-pi/configs/zone1-linux.json
new file mode 100644
index 00000000..5bf7d154
--- /dev/null
+++ b/platform/aarch64/phytium-pi/configs/zone1-linux.json
@@ -0,0 +1,54 @@
+{
+ "arch": "arm64",
+ "name": "linux2",
+ "zone_id": 1,
+ "cpus": [2,3],
+ "memory_regions": [
+ {
+ "type": "ram",
+ "physical_start": "0xb0000000",
+ "virtual_start": "0xb0000000",
+ "size": "0x30000000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x32a00000",
+ "virtual_start": "0x32a00000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x32a10000",
+ "virtual_start": "0x32a10000",
+ "size": "0x2000"
+ },
+ {
+ "type": "virtio",
+ "physical_start": "0xa003c00",
+ "virtual_start": "0xa003c00",
+ "size": "0x200"
+ },
+ {
+ "type": "virtio",
+ "physical_start": "0xa003800",
+ "virtual_start": "0xa003800",
+ "size": "0x200"
+ }
+ ],
+ "interrupts": [54,64,66,74,76, 78],
+ "ivc_configs": [],
+ "kernel_filepath": "./Image",
+ "dtb_filepath": "./linux2.dtb",
+ "kernel_load_paddr": "0xb0400000",
+ "dtb_load_paddr": "0xb0000000",
+ "entry_point": "0xb0400000",
+ "arch_config": {
+ "gic_version": "v3",
+ "gicd_base": "0x30800000",
+ "gicd_size": "0x20000",
+ "gicr_base": "0x30880000",
+ "gicr_size": "0x80000",
+ "gits_base": "0x0",
+ "gits_size": "0x0"
+ }
+}
diff --git a/platform/aarch64/phytium-pi/image/dts/Makefile b/platform/aarch64/phytium-pi/image/dts/Makefile
new file mode 100644
index 00000000..2f795e7f
--- /dev/null
+++ b/platform/aarch64/phytium-pi/image/dts/Makefile
@@ -0,0 +1,8 @@
+DTS_FILES := $(wildcard *.dts)
+DTB_FILES := $(DTS_FILES:.dts=.dtb)
+
+all: $(DTB_FILES)
+%.dtb: %.dts
+ dtc -I dts -O dtb $< -o $@
+clean:
+ rm -f $(DTB_FILES)
\ No newline at end of file
diff --git a/platform/aarch64/phytium-pi/image/dts/linux1.dts b/platform/aarch64/phytium-pi/image/dts/linux1.dts
new file mode 100644
index 00000000..9b7bb491
--- /dev/null
+++ b/platform/aarch64/phytium-pi/image/dts/linux1.dts
@@ -0,0 +1,1561 @@
+/dts-v1/;
+
+/memreserve/ 0x0000000080000000 0x0000000000010000;
+/ {
+ compatible = "phytium,pe2204";
+ interrupt-parent = <0x01>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ model = "Phytium Pi Board";
+
+ aliases {
+ // serial0 = "/soc/uart@2800c000";
+ serial1 = "/soc/uart@2800d000";
+ // serial2 = "/soc/uart@2800e000";
+ // serial3 = "/soc/uart@2800f000";
+ ethernet0 = "/soc/ethernet@3200c000";
+ // ethernet1 = "/soc/ethernet@3200e000";
+ // ethernet2 = "/soc/ethernet@32010000";
+ // ethernet3 = "/soc/ethernet@32012000";
+ // serial4 = "/soc/uart@28014000";
+ // serial7 = "/soc/uart@2802A000";
+ // serial8 = "/soc/uart@28032000";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ sys_poweroff = <0x84000008>;
+ sys_reset = <0x84000009>;
+ };
+
+ firmware {
+
+ scmi {
+ compatible = "arm,scmi";
+ mboxes = <0x02 0x00>;
+ mbox-names = "tx";
+ shmem = <0x03>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ phandle = <0x18>;
+
+ protocol@13 {
+ reg = <0x13>;
+ #clock-cells = <0x01>;
+ phandle = <0x09>;
+ };
+
+ protocol@15 {
+ reg = <0x15>;
+ #thermal-sensor-cells = <0x01>;
+ phandle = <0x04>;
+ };
+ };
+
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ thermal-zones {
+
+ sensor0 {
+ polling-delay-passive = <0x64>;
+ polling-delay = <0x3e8>;
+ thermal-sensors = <0x04 0x00>;
+ };
+
+ sensor1 {
+ polling-delay-passive = <0x64>;
+ polling-delay = <0x3e8>;
+ thermal-sensors = <0x04 0x01>;
+ };
+ };
+
+ cpus {
+ #address-cells = <0x02>;
+ #size-cells = <0x00>;
+ phandle = <0x19>;
+
+ cpu-map {
+ // cluster0 {
+
+ // core0 {
+ // cpu = <0x05>;
+ // };
+ // };
+
+ // cluster1 {
+
+ // core0 {
+ // cpu = <0x06>;
+ // };
+ // };
+
+ cluster2 {
+
+ core0 {
+ cpu = <0x07>;
+ };
+
+ core1 {
+ cpu = <0x08>;
+ };
+ };
+ };
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "phytium,ftc310\0arm,armv8";
+ reg = <0x00 0x200>;
+ enable-method = "psci";
+ clocks = <0x09 0x02>;
+ capacity-dmips-mhz = <0xb22>;
+ phandle = <0x07>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "phytium,ftc310\0arm,armv8";
+ reg = <0x00 0x201>;
+ enable-method = "psci";
+ clocks = <0x09 0x02>;
+ capacity-dmips-mhz = <0xb22>;
+ phandle = <0x08>;
+ };
+ // cpu@100 {
+ // device_type = "cpu";
+ // compatible = "phytium,ftc664\0arm,armv8";
+ // reg = <0x00 0x00>;
+ // enable-method = "psci";
+ // clocks = <0x09 0x00>;
+ // capacity-dmips-mhz = <0x161c>;
+ // phandle = <0x05>;
+ // };
+
+ // cpu@101 {
+ // device_type = "cpu";
+ // compatible = "phytium,ftc664\0arm,armv8";
+ // reg = <0x00 0x100>;
+ // enable-method = "psci";
+ // clocks = <0x09 0x01>;
+ // capacity-dmips-mhz = <0x161c>;
+ // phandle = <0x06>;
+ // };
+
+ };
+
+ interrupt-controller@30800000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <0x03>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ interrupt-controller;
+ reg = <0x00 0x30800000 0x00 0x20000 0x00 0x30880000 0x00 0x80000>;
+ // reg = <0x00 0x30800000 0x00 0x20000 0x00 0x30880000 0x00 0x80000 0x00 0x30840000 0x00 0x10000 0x00 0x30850000 0x00 0x10000 0x00 0x30860000 0x00 0x10000>;
+ interrupts = <0x01 0x09 0x08>;
+ phandle = <0x01>;
+
+ // gic-its@30820000 {
+ // compatible = "arm,gic-v3-its";
+ // msi-controller;
+ // reg = <0x00 0x30820000 0x00 0x20000>;
+ // phandle = <0x0f>;
+ // };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0x01 0x07 0x08>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
+ clock-frequency = <0x2faf080>;
+ };
+
+ clocks {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ clk48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x2dc6c00>;
+ phandle = <0x13>;
+ };
+
+ clk50mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x2faf080>;
+ phandle = <0x0d>;
+ };
+
+ clk100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x5f5e100>;
+ phandle = <0x0c>;
+ };
+
+ clk200mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0xbebc200>;
+ phandle = <0x11>;
+ };
+
+ clk250mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0xee6b280>;
+ phandle = <0x12>;
+ };
+
+ clk300mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x11e1a300>;
+ phandle = <0x0b>;
+ };
+
+ clk600mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x23c34600>;
+ phandle = <0x0e>;
+ };
+
+ clk1200mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x47868c00>;
+ phandle = <0x0a>;
+ };
+ };
+
+ iommu@30000000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x00 0x30000000 0x00 0x800000>;
+ interrupts = <0x00 0xf0 0x01 0x00 0xef 0x01 0x00 0xec 0x01 0x00 0xf2 0x01>;
+ interrupt-names = "eventq\0priq\0cmdq-sync\0gerror";
+ dma-coherent;
+ #iommu-cells = <0x01>;
+ phandle = <0x10>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ dma-coherent;
+ ranges;
+ phandle = <0x1a>;
+
+ mmc@28000000 {
+ compatible = "phytium,mci";
+ reg = <0x00 0x28000000 0x00 0x1000>;
+ interrupts = <0x00 0x48 0x04>;
+ clocks = <0x0a>;
+ clock-names = "phytium_mci_clk";
+ status = "okay";
+ bus-width = <0x04>;
+ max-frequency = <0x2faf080>;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ no-mmc;
+ phandle = <0x1b>;
+ };
+
+ mmc@28001000 {
+ compatible = "phytium,mci";
+ reg = <0x00 0x28001000 0x00 0x1000>;
+ interrupts = <0x00 0x49 0x04>;
+ clocks = <0x0a>;
+ clock-names = "phytium_mci_clk";
+ status = "okay";
+ bus-width = <0x04>;
+ max-frequency = <0x2faf080>;
+ #sd-uhs-sdr25;
+ #sd-uhs-sdr50;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ no-mmc;
+ no-sd;
+ non-removable;
+ phandle = <0x1c>;
+ };
+
+ nand@28002000 {
+ compatible = "phytium,nfc";
+ reg = <0x00 0x28002000 0x00 0x1000>;
+ interrupts = <0x00 0x4a 0x04>;
+ status = "disabled";
+ phandle = <0x1d>;
+ };
+
+ ddma@28003000 {
+ compatible = "phytium,ddma";
+ reg = <0x00 0x28003000 0x00 0x1000>;
+ interrupts = <0x00 0x4b 0x04>;
+ #dma-cells = <0x02>;
+ dma-channels = <0x08>;
+ phandle = <0x1e>;
+ };
+
+ ddma@28004000 {
+ compatible = "phytium,ddma";
+ reg = <0x00 0x28004000 0x00 0x1000>;
+ interrupts = <0x00 0x4c 0x04>;
+ #dma-cells = <0x02>;
+ dma-channels = <0x08>;
+ phandle = <0x1f>;
+ };
+
+ spi@28008000 {
+ compatible = "phytium,qspi-nor";
+ reg = <0x00 0x28008000 0x00 0x1000 0x00 0x00 0x00 0xfffffff>;
+ reg-names = "qspi\0qspi_mm";
+ clocks = <0x0b>;
+ status = "okay";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ phandle = <0x20>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x00>;
+ spi-rx-bus-width = <0x01>;
+ spi-max-frequency = <0x1312d00>;
+ status = "okay";
+ };
+ };
+
+ // uart@2800c000 {
+ // compatible = "arm,pl011\0arm,primecell";
+ // reg = <0x00 0x2800c000 0x00 0x1000>;
+ // interrupts = <0x00 0x53 0x04>;
+ // clocks = <0x0c 0x0c>;
+ // clock-names = "uartclk\0apb_pclk";
+ // status = "okay";
+ // phandle = <0x21>;
+ // };
+
+ uart@2800d000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x2800d000 0x00 0x1000>;
+ interrupts = <0x00 0x54 0x04>;
+ clocks = <0x0c 0x0c>;
+ clock-names = "uartclk\0apb_pclk";
+ status = "okay";
+ phandle = <0x22>;
+ };
+
+ // uart@2800e000 {
+ // compatible = "arm,pl011\0arm,primecell";
+ // reg = <0x00 0x2800e000 0x00 0x1000>;
+ // interrupts = <0x00 0x55 0x04>;
+ // clocks = <0x0c 0x0c>;
+ // clock-names = "uartclk\0apb_pclk";
+ // status = "okay";
+ // phandle = <0x23>;
+ // };
+
+ // uart@2800f000 {
+ // compatible = "arm,pl011\0arm,primecell";
+ // reg = <0x00 0x2800f000 0x00 0x1000>;
+ // interrupts = <0x00 0x56 0x04>;
+ // clocks = <0x0c 0x0c>;
+ // clock-names = "uartclk\0apb_pclk";
+ // status = "okay";
+ // phandle = <0x24>;
+ // };
+
+ lpc@28010000 {
+ compatible = "simple-mfd\0syscon";
+ reg = <0x00 0x28010000 0x00 0x1000>;
+ reg-io-width = <0x04>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x00 0x28010000 0x1000>;
+ phandle = <0x25>;
+
+ kcs@24 {
+ compatible = "phytium,kcs-bmc";
+ reg = <0x24 0x01 0x30 0x01 0x3c 0x01>;
+ interrupts = <0x00 0x58 0x04>;
+ status = "disabled";
+ phandle = <0x26>;
+ };
+
+ kcs@28 {
+ compatible = "phytium,kcs-bmc";
+ reg = <0x28 0x01 0x34 0x01 0x40 0x01>;
+ interrupts = <0x00 0x58 0x04>;
+ status = "disabled";
+ phandle = <0x27>;
+ };
+
+ kcs@2c {
+ compatible = "phytium,kcs-bmc";
+ reg = <0x2c 0x01 0x38 0x01 0x44 0x01>;
+ interrupts = <0x00 0x58 0x04>;
+ status = "disabled";
+ phandle = <0x28>;
+ };
+
+ kcs@8c {
+ compatible = "phytium,kcs-bmc";
+ reg = <0x8c 0x01 0x90 0x01 0x94 0x01>;
+ interrupts = <0x00 0x58 0x04>;
+ status = "disabled";
+ phandle = <0x29>;
+ };
+
+ bt@48 {
+ compatible = "phytium,bt-bmc";
+ reg = <0x48 0x20>;
+ interrupts = <0x00 0x58 0x04>;
+ status = "disabled";
+ phandle = <0x2a>;
+ };
+ };
+
+ gpio@28034000 {
+ compatible = "phytium,gpio";
+ reg = <0x00 0x28034000 0x00 0x1000>;
+ interrupts = <0x00 0x6c 0x04 0x00 0x6d 0x04 0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04 0x00 0x71 0x04 0x00 0x72 0x04 0x00 0x73 0x04 0x00 0x74 0x04 0x00 0x75 0x04 0x00 0x76 0x04 0x00 0x77 0x04 0x00 0x78 0x04 0x00 0x79 0x04 0x00 0x7a 0x04 0x00 0x7b 0x04>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x2b>;
+
+ porta {
+ compatible = "phytium,gpio-port";
+ reg = <0x00>;
+ ngpios = <0x10>;
+ };
+ };
+
+ gpio@28035000 {
+ compatible = "phytium,gpio";
+ reg = <0x00 0x28035000 0x00 0x1000>;
+ interrupts = <0x00 0x7c 0x04 0x00 0x7d 0x04 0x00 0x7e 0x04 0x00 0x7f 0x04 0x00 0x80 0x04 0x00 0x81 0x04 0x00 0x82 0x04 0x00 0x83 0x04 0x00 0x84 0x04 0x00 0x85 0x04 0x00 0x86 0x04 0x00 0x87 0x04 0x00 0x88 0x04 0x00 0x89 0x04 0x00 0x8a 0x04 0x00 0x8b 0x04>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x15>;
+
+ porta {
+ compatible = "phytium,gpio-port";
+ reg = <0x00>;
+ ngpios = <0x10>;
+ };
+ };
+
+ gpio@28036000 {
+ compatible = "phytium,gpio";
+ reg = <0x00 0x28036000 0x00 0x1000>;
+ interrupts = <0x00 0x8c 0x04 0x00 0x8d 0x04 0x00 0x8e 0x04 0x00 0x8f 0x04 0x00 0x90 0x04 0x00 0x91 0x04 0x00 0x92 0x04 0x00 0x93 0x04 0x00 0x94 0x04 0x00 0x95 0x04 0x00 0x96 0x04 0x00 0x97 0x04 0x00 0x98 0x04 0x00 0x99 0x04 0x00 0x9a 0x04 0x00 0x9b 0x04>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x14>;
+
+ porta {
+ compatible = "phytium,gpio-port";
+ reg = <0x00>;
+ ngpios = <0x10>;
+ };
+ };
+
+ gpio@28037000 {
+ compatible = "phytium,gpio";
+ reg = <0x00 0x28037000 0x00 0x1000>;
+ interrupts = <0x00 0x9c 0x04>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x2c>;
+
+ porta {
+ compatible = "phytium,gpio-port";
+ reg = <0x00>;
+ ngpios = <0x10>;
+ };
+ };
+
+ gpio@28038000 {
+ compatible = "phytium,gpio";
+ reg = <0x00 0x28038000 0x00 0x1000>;
+ interrupts = <0x00 0x9d 0x04>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x2d>;
+
+ porta {
+ compatible = "phytium,gpio-port";
+ reg = <0x00>;
+ ngpios = <0x10>;
+ };
+ };
+
+ gpio@28039000 {
+ compatible = "phytium,gpio";
+ reg = <0x00 0x28039000 0x00 0x1000>;
+ interrupts = <0x00 0x9e 0x04>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x2e>;
+
+ porta {
+ compatible = "phytium,gpio-port";
+ reg = <0x00>;
+ ngpios = <0x10>;
+ };
+ };
+
+ spi@2803a000 {
+ compatible = "phytium,spi";
+ reg = <0x00 0x2803a000 0x00 0x1000>;
+ interrupts = <0x00 0x9f 0x04>;
+ clocks = <0x0d>;
+ num-cs = <0x04>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ global-cs = <0x01>;
+ phandle = <0x2f>;
+ };
+
+ spi@2803b000 {
+ compatible = "phytium,spi";
+ reg = <0x00 0x2803b000 0x00 0x1000>;
+ interrupts = <0x00 0xa0 0x04>;
+ clocks = <0x0d>;
+ num-cs = <0x04>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "disabled";
+ phandle = <0x30>;
+ };
+
+ spi@2803c000 {
+ compatible = "phytium,spi";
+ reg = <0x00 0x2803c000 0x00 0x1000>;
+ interrupts = <0x00 0xa1 0x04>;
+ clocks = <0x0d>;
+ num-cs = <0x04>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "disabled";
+ phandle = <0x31>;
+ };
+
+ spi@2803d000 {
+ compatible = "phytium,spi";
+ reg = <0x00 0x2803d000 0x00 0x1000>;
+ interrupts = <0x00 0xa2 0x04>;
+ clocks = <0x0d>;
+ num-cs = <0x04>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "disabled";
+ phandle = <0x32>;
+ };
+
+ watchdog@28040000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x00 0x28041000 0x00 0x1000 0x00 0x28040000 0x00 0x1000>;
+ interrupts = <0x00 0xa4 0x04>;
+ timeout-sec = <0x1e>;
+ status = "okay";
+ phandle = <0x33>;
+ };
+
+ watchdog@28042000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x00 0x28043000 0x00 0x1000 0x00 0x28042000 0x00 0x1000>;
+ interrupts = <0x00 0xa5 0x04>;
+ timeout-sec = <0x1e>;
+ status = "okay";
+ phandle = <0x34>;
+ };
+
+ pwm@2804a000 {
+ compatible = "phytium,pwm";
+ reg = <0x00 0x2804a000 0x00 0x1000>;
+ interrupts = <0x00 0xad 0x04>;
+ clocks = <0x0d>;
+ status = "okay";
+ phytium,db = <0x00 0x00 0x64 0x3e8 0x3e8 0x00>;
+ phandle = <0x35>;
+ };
+
+ pwm@2804b000 {
+ compatible = "phytium,pwm";
+ reg = <0x00 0x2804b000 0x00 0x1000>;
+ interrupts = <0x00 0xae 0x04>;
+ clocks = <0x0d>;
+ status = "okay";
+ phytium,db = <0x00 0x00 0x64 0x3e8 0x3e8 0x00>;
+ phandle = <0x36>;
+ };
+
+ tacho@28054000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28054000 0x00 0x1000>;
+ interrupts = <0x00 0xc2 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x37>;
+ };
+
+ tacho@28055000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28055000 0x00 0x1000>;
+ interrupts = <0x00 0xc3 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x38>;
+ };
+
+ tacho@28056000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28056000 0x00 0x1000>;
+ interrupts = <0x00 0xc4 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x39>;
+ };
+
+ tacho@28057000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28057000 0x00 0x1000>;
+ interrupts = <0x00 0xc5 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x3a>;
+ };
+
+ tacho@28058000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28058000 0x00 0x1000>;
+ interrupts = <0x00 0xc6 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x3b>;
+ };
+
+ tacho@28059000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28059000 0x00 0x1000>;
+ interrupts = <0x00 0xc7 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x3c>;
+ };
+
+ tacho@2805a000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2805a000 0x00 0x1000>;
+ interrupts = <0x00 0xc8 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x3d>;
+ };
+
+ tacho@2805b000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2805b000 0x00 0x1000>;
+ interrupts = <0x00 0xc9 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x3e>;
+ };
+
+ tacho@2805c000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2805c000 0x00 0x1000>;
+ interrupts = <0x00 0xca 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x3f>;
+ };
+
+ tacho@2805d000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2805d000 0x00 0x1000>;
+ interrupts = <0x00 0xcb 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x40>;
+ };
+
+ tacho@2805e000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2805e000 0x00 0x1000>;
+ interrupts = <0x00 0xcc 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x41>;
+ };
+
+ tacho@2805f000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2805f000 0x00 0x1000>;
+ interrupts = <0x00 0xcd 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x42>;
+ };
+
+ tacho@28060000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28060000 0x00 0x1000>;
+ interrupts = <0x00 0xce 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x43>;
+ };
+
+ tacho@28061000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28061000 0x00 0x1000>;
+ interrupts = <0x00 0xcf 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x44>;
+ };
+
+ tacho@28062000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28062000 0x00 0x1000>;
+ interrupts = <0x00 0xd0 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x45>;
+ };
+
+ tacho@28063000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28063000 0x00 0x1000>;
+ interrupts = <0x00 0xd1 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x46>;
+ };
+
+ tacho@28064000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28064000 0x00 0x1000>;
+ interrupts = <0x00 0xd2 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x47>;
+ };
+
+ tacho@28065000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28065000 0x00 0x1000>;
+ interrupts = <0x00 0xd3 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x48>;
+ };
+
+ tacho@28066000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28066000 0x00 0x1000>;
+ interrupts = <0x00 0xd4 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x49>;
+ };
+
+ tacho@28067000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28067000 0x00 0x1000>;
+ interrupts = <0x00 0xd5 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x4a>;
+ };
+
+ tacho@28068000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28068000 0x00 0x1000>;
+ interrupts = <0x00 0xd6 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x4b>;
+ };
+
+ tacho@28069000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28069000 0x00 0x1000>;
+ interrupts = <0x00 0xd7 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x4c>;
+ };
+
+ tacho@2806a000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2806a000 0x00 0x1000>;
+ interrupts = <0x00 0xd8 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x4d>;
+ };
+
+ tacho@2806b000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2806b000 0x00 0x1000>;
+ interrupts = <0x00 0xd9 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x4e>;
+ };
+
+ tacho@2806c000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2806c000 0x00 0x1000>;
+ interrupts = <0x00 0xda 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x4f>;
+ };
+
+ tacho@2806d000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2806d000 0x00 0x1000>;
+ interrupts = <0x00 0xdb 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x50>;
+ };
+
+ tacho@2806e000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2806e000 0x00 0x1000>;
+ interrupts = <0x00 0xdc 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x51>;
+ };
+
+ tacho@2806f000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2806f000 0x00 0x1000>;
+ interrupts = <0x00 0xdd 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x52>;
+ };
+
+ tacho@28070000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28070000 0x00 0x1000>;
+ interrupts = <0x00 0xde 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x53>;
+ };
+
+ tacho@28071000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28071000 0x00 0x1000>;
+ interrupts = <0x00 0xdf 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x54>;
+ };
+
+ tacho@28072000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28072000 0x00 0x1000>;
+ interrupts = <0x00 0xe0 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x55>;
+ };
+
+ tacho@28073000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28073000 0x00 0x1000>;
+ interrupts = <0x00 0xe1 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x56>;
+ };
+
+ tacho@28074000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28074000 0x00 0x1000>;
+ interrupts = <0x00 0xe2 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x57>;
+ };
+
+ tacho@28075000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28075000 0x00 0x1000>;
+ interrupts = <0x00 0xe3 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x58>;
+ };
+
+ tacho@28076000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28076000 0x00 0x1000>;
+ interrupts = <0x00 0xe4 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x59>;
+ };
+
+ tacho@28077000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28077000 0x00 0x1000>;
+ interrupts = <0x00 0xe5 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x5a>;
+ };
+
+ tacho@28078000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28078000 0x00 0x1000>;
+ interrupts = <0x00 0xe6 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x5b>;
+ };
+
+ tacho@28079000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28079000 0x00 0x1000>;
+ interrupts = <0x00 0xe7 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x5c>;
+ };
+
+
+ usb2@31800000 {
+ compatible = "phytium,usb2";
+ reg = <0x00 0x31800000 0x00 0x80000 0x00 0x31990000 0x00 0x10000>;
+ interrupts = <0x00 0x20 0x04>;
+ status = "disabled"; //和hvisor冲突
+ dr_mode = "host";
+ phandle = <0x5d>;
+ };
+
+ usb2@31880000 {
+ compatible = "phytium,usb2";
+ reg = <0x00 0x31880000 0x00 0x80000 0x00 0x319a0000 0x00 0x10000>;
+ interrupts = <0x00 0x21 0x04>;
+ status = "disabled";
+ dr_mode = "peripheral";
+ phandle = <0x5e>;
+ };
+
+ usb2@31900000 {
+ compatible = "phytium,usb2";
+ reg = <0x00 0x31900000 0x00 0x80000 0x00 0x319b0000 0x00 0x10000>;
+ interrupts = <0x00 0x22 0x04>;
+ status = "disabled";
+ dr_mode = "peripheral";
+ phandle = <0x5f>;
+ };
+
+ usb2@32800000 {
+ compatible = "phytium,usb2";
+ reg = <0x00 0x32800000 0x00 0x40000 0x00 0x32880000 0x00 0x40000>;
+ interrupts = <0x00 0x0e 0x04>;
+ status = "okay";
+ dr_mode = "host";
+ phandle = <0x60>;
+ };
+
+ usb2@32840000 {
+ compatible = "phytium,usb2";
+ reg = <0x00 0x32840000 0x00 0x40000 0x00 0x328c0000 0x00 0x40000>;
+ interrupts = <0x00 0x0f 0x04>;
+ status = "okay";
+ dr_mode = "host";
+ phandle = <0x61>;
+ };
+ //数字控制器，用于连接和控制显示器
+ // dc@32000000 {
+ // compatible = "phytium,dc";
+ // reg = <0x00 0x32000000 0x00 0x8000>;
+ // interrupts = <0x00 0x2c 0x04>;
+ // status = "disabled";
+ // pipe_mask = [01];
+ // edp_mask = [00];
+ // phandle = <0x62>;
+ // };
+ //用于数字音频数据传输
+ i2s_dp0@32009000 {
+ compatible = "phytium,i2s";
+ reg = <0x00 0x32009000 0x00 0x1000 0x00 0x32008000 0x00 0x1000>;
+ interrupts = <0x00 0x2f 0x04>;
+ clocks = <0x0e>;
+ clock-names = "i2s_clk";
+ dai-name = "phytium-i2s-dp0";
+ status = "disabled";
+ phandle = <0x63>;
+ };
+
+ i2s_dp1@3200B000 {
+ compatible = "phytium,i2s";
+ reg = <0x00 0x3200b000 0x00 0x1000 0x00 0x3200a000 0x00 0x1000>;
+ interrupts = <0x00 0x30 0x04>;
+ clocks = <0x0e>;
+ clock-names = "i2s_clk";
+ dai-name = "phytium-i2s-dp1";
+ status = "disabled";
+ phandle = <0x64>;
+ };
+ //和显示端口相关的设备，可能用于连接显示器或其他显示设备
+ pmdk_dp {
+ compatible = "phytium,pmdk-dp";
+ status = "disabled";
+ num-dp = <0x01>;
+ dp-mask = [01];
+ phandle = <0x65>;
+ };
+
+ mailbox@32a00000 {
+ compatible = "phytium,mbox";
+ reg = <0x00 0x32a00000 0x00 0x1000>;
+ interrupts = <0x00 0x16 0x04>;
+ #mbox-cells = <0x01>;
+ phandle = <0x02>;
+ };
+
+ rng@32a36000 {
+ compatible = "phytium,rng";
+ reg = <0x00 0x32a36000 0x00 0x1000>;
+ status = "disabled";
+ phandle = <0x66>;
+ };
+
+ sram@32a10000 {
+ compatible = "phytium,pe220x-sram-ns\0mmio-sram";
+ reg = <0x00 0x32a10000 0x00 0x2000>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x00 0x32a10000 0x2000>;
+ phandle = <0x67>;
+
+ scp-shmem@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x1000 0x400>;
+ phandle = <0x68>;
+ };
+
+ scp-shmem@1 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x1400 0x400>;
+ phandle = <0x03>;
+ };
+ };
+ //通过 DMA 控制器，系统可以在内存和外设之间进行快速的数据交换
+ // gdma@32b34000 {
+ // compatible = "phytium,gdma";
+ // dma-channels = <0x10>;
+ // max-outstanding = <0x10>;
+ // reg = <0x00 0x32b34000 0x00 0x1000>;
+ // interrupts = <0x00 0xea 0x04>;
+ // #dma-cells = <0x01>;
+ // phandle = <0x69>;
+ // };
+
+ spinlock@32b36000 {
+ compatible = "phytium,hwspinlock";
+ reg = <0x00 0x32b36000 0x00 0x1000>;
+ #hwlock-cells = <0x01>;
+ nr-locks = <0x20>;
+ status = "disabled";
+ phandle = <0x6a>;
+ };
+
+ pcie@40000000 {
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ #address-cells = <0x03>;
+ #size-cells = <0x02>;
+ #interrupt-cells = <0x01>;
+ reg = <0x00 0x40000000 0x00 0x10000000>;
+ msi-parent = <0x0f>;
+ bus-range = <0x00 0xff>;
+ interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+ interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x04 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x00 0x00 0x05 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x00 0x00 0x06 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x00 0x00 0x07 0x04>;
+ ranges = <0x1000000 0x00 0x00 0x00 0x50000000 0x00 0xf00000 0x2000000 0x00 0x58000000 0x00 0x58000000 0x00 0x28000000 0x3000000 0x10 0x00 0x10 0x00 0x10 0x00>;
+ iommu-map = <0x00 0x10 0x00 0x10000>;
+ status = "disabled";
+ phandle = <0x6b>;
+ };
+
+ edac@32b28000 {
+ compatible = "phytium,pe220x-edac";
+ reg = <0x00 0x32b28000 0x00 0x1000 0x00 0x31400000 0x00 0x1000 0x00 0x31401000 0x00 0x1000>;
+ interrupts = <0x00 0x00 0x04 0x00 0x01 0x04>;
+ status = "disabled";
+ phandle = <0x6c>;
+ };
+
+ hda@28006000 {
+ compatible = "phytium,hda";
+ reg = <0x00 0x28006000 0x00 0x1000>;
+ interrupts = <0x00 0x4e 0x04>;
+ status = "disabled";
+ phandle = <0x6d>;
+ };
+
+ i2s@28009000 {
+ compatible = "phytium,i2s";
+ reg = <0x00 0x28009000 0x00 0x1000 0x00 0x28005000 0x00 0x1000>;
+ interrupts = <0x00 0x4d 0x04>;
+ clocks = <0x0e>;
+ clock-names = "i2s_clk";
+ status = "okay";
+ #sound-dai-cells = <0x00>;
+ dai-name = "phytium-i2s-lsd";
+ phandle = <0x16>;
+ };
+
+ can@2800a000 {
+ compatible = "phytium,canfd";
+ reg = <0x00 0x2800a000 0x00 0x1000>;
+ interrupts = <0x00 0x51 0x04>;
+ clocks = <0x11>;
+ clock-names = "can_clk";
+ tx-fifo-depth = <0x40>;
+ rx-fifo-depth = <0x40>;
+ status = "okay";
+ phandle = <0x6e>;
+ };
+
+ can@2800b000 {
+ compatible = "phytium,canfd";
+ reg = <0x00 0x2800b000 0x00 0x1000>;
+ interrupts = <0x00 0x52 0x04>;
+ clocks = <0x11>;
+ clock-names = "can_clk";
+ tx-fifo-depth = <0x40>;
+ rx-fifo-depth = <0x40>;
+ status = "okay";
+ phandle = <0x6f>;
+ };
+
+ keypad@2807a000 {
+ compatible = "phytium,keypad";
+ reg = <0x00 0x2807a000 0x00 0x1000>;
+ interrupts = <0x00 0xbd 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x70>;
+ };
+
+ usb3@31a08000 {
+ compatible = "phytium,pe220x-xhci";
+ reg = <0x00 0x31a08000 0x00 0x18000>;
+ interrupts = <0x00 0x10 0x04>;
+ status = "okay";
+ phandle = <0x71>;
+ };
+
+ usb3@31a28000 {
+ compatible = "phytium,pe220x-xhci";
+ reg = <0x00 0x31a28000 0x00 0x18000>;
+ interrupts = <0x00 0x11 0x04>;
+ status = "okay";
+ phandle = <0x72>;
+ };
+ //SATA 控制器
+ sata@31a40000 {
+ compatible = "generic-ahci";
+ reg = <0x00 0x31a40000 0x00 0x1000>;
+ interrupts = <0x00 0x2a 0x04>;
+ status = "disabled";
+ phandle = <0x73>;
+ };
+
+ sata@32014000 {
+ compatible = "generic-ahci";
+ reg = <0x00 0x32014000 0x00 0x1000>;
+ interrupts = <0x00 0x2b 0x04>;
+ status = "disabled";
+ phandle = <0x74>;
+ };
+
+ ethernet@3200c000 {
+ compatible = "cdns,phytium-gem-1.0";
+ reg = <0x00 0x3200c000 0x00 0x2000>;
+ interrupts = <0x00 0x37 0x04 0x00 0x38 0x04 0x00 0x39 0x04 0x00 0x3a 0x04 0x00 0x1c 0x04 0x00 0x1d 0x04 0x00 0x1e 0x04 0x00 0x1f 0x04>;
+ clock-names = "pclk\0hclk\0tx_clk\0tsu_clk";
+ clocks = <0x12 0x13 0x13 0x12>;
+ magic-packet;
+ support-tsn;
+ status = "okay";
+ phy-mode = "sgmii";
+ use-mii;
+ phandle = <0x75>;
+ };
+
+ // ethernet@3200e000 {
+ // compatible = "cdns,phytium-gem-1.0";
+ // reg = <0x00 0x3200e000 0x00 0x2000>;
+ // interrupts = <0x00 0x3b 0x04 0x00 0x3c 0x04 0x00 0x3d 0x04 0x00 0x3e 0x04>;
+ // clock-names = "pclk\0hclk\0tx_clk\0tsu_clk";
+ // clocks = <0x12 0x13 0x13 0x12>;
+ // magic-packet;
+ // status = "disabled";
+ // phy-mode = "sgmii";
+ // use-mii;
+ // phandle = <0x76>;
+ // };
+
+ // ethernet@32010000 {
+ // compatible = "cdns,phytium-gem-1.0";
+ // reg = <0x00 0x32010000 0x00 0x2000>;
+ // interrupts = <0x00 0x40 0x04 0x00 0x41 0x04 0x00 0x42 0x04 0x00 0x43 0x04>;
+ // clock-names = "pclk\0hclk\0tx_clk\0tsu_clk";
+ // clocks = <0x12 0x13 0x13 0x12>;
+ // magic-packet;
+ // status = "disabled";
+ // phandle = <0x77>;
+ // };
+
+ // ethernet@32012000 {
+ // compatible = "cdns,phytium-gem-1.0";
+ // reg = <0x00 0x32012000 0x00 0x2000>;
+ // interrupts = <0x00 0x44 0x04 0x00 0x45 0x04 0x00 0x46 0x04 0x00 0x47 0x04>;
+ // clock-names = "pclk\0hclk\0tx_clk\0tsu_clk";
+ // clocks = <0x12 0x13 0x13 0x12>;
+ // magic-packet;
+ // status = "disabled";
+ // phandle = <0x78>;
+ // };
+
+ vpu@32b00000 {
+ compatible = "phytium,vpu";
+ reg = <0x00 0x32b00000 0x00 0x20000>;
+ interrupts = <0x00 0x0c 0x04>;
+ status = "disabled";
+ phandle = <0x79>;
+ };
+
+ i2c@28026000 {
+ compatible = "phytium,i2c";
+ reg = <0x00 0x28026000 0x00 0x1000>;
+ interrupts = <0x00 0x65 0x04>;
+ clocks = <0x0d>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x7a>;
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+ };
+
+ i2c@28030000 {
+ compatible = "phytium,i2c";
+ reg = <0x00 0x28030000 0x00 0x1000>;
+ interrupts = <0x00 0x6a 0x04>;
+ clocks = <0x0d>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x7b>;
+
+ es8336@10 {
+ det-gpios = <0x14 0x0b 0x00>;
+ sel-gpios = <0x14 0x07 0x00>;
+ #sound-dai-cells = <0x00>;
+ compatible = "everest,es8336";
+ reg = <0x10>;
+ phandle = <0x17>;
+ };
+ };
+
+ // uart@28014000 {
+ // compatible = "arm,pl011\0arm,primecell";
+ // reg = <0x00 0x28014000 0x00 0x1000>;
+ // interrupts = <0x00 0x5c 0x04>;
+ // clocks = <0x0d 0x0d>;
+ // clock-names = "uartclk\0apb_pclk";
+ // status = "okay";
+ // phandle = <0x7c>;
+ // };
+
+ i2c@28016000 {
+ compatible = "phytium,i2c";
+ reg = <0x00 0x28016000 0x00 0x1000>;
+ interrupts = <0x00 0x5d 0x04>;
+ clocks = <0x0d>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x7d>;
+ };
+
+ i2c@28024000 {
+ compatible = "phytium,i2c";
+ reg = <0x00 0x28024000 0x00 0x1000>;
+ interrupts = <0x00 0x64 0x04>;
+ clocks = <0x0d>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x7e>;
+ };
+
+ // uart@2802A000 {
+ // compatible = "arm,pl011\0arm,primecell";
+ // reg = <0x00 0x2802a000 0x00 0x1000>;
+ // interrupts = <0x00 0x67 0x04>;
+ // clocks = <0x0d 0x0d>;
+ // clock-names = "uartclk\0apb_pclk";
+ // status = "okay";
+ // phandle = <0x7f>;
+ // };
+
+ // uart@28032000 {
+ // compatible = "arm,pl011\0arm,primecell";
+ // reg = <0x00 0x28032000 0x00 0x1000>;
+ // interrupts = <0x00 0x6b 0x04>;
+ // clocks = <0x0d 0x0d>;
+ // clock-names = "uartclk\0apb_pclk";
+ // status = "okay";
+ // phandle = <0x80>;
+ // };
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ bootargs = "clk_ignore_unused console=ttyAMA1,115200 earlycon=pl011,0x2800d000,115200 root=/dev/mmcblk0p1 rw rootwait init=/bin/sh";
+ };
+
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x00 0x80000000>;
+ };
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ hvisor@90100000 {
+ no-map;
+ reg = <0x00 0x90100000 0x00 0x400000>;
+ };
+ dtbfile@90000000 {
+ no-map;
+ reg = <0x00 0x90000000 0x00 0x080000>;
+ };
+ nonroot@b0000000 {
+ no-map;
+ reg = <0x00 0xb0000000 0x00 0x30000000>;
+ };
+ };
+
+ hvisor_virtio_device {
+ compatible = "hvisor";
+ interrupt-parent = <0x01>;
+ interrupts = <0x00 0x20 0x01>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ sysled {
+ label = "sysled";
+ gpios = <0x15 0x08 0x00>;
+ linux,default-trigger = "none";
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "phytium,pe220x-i2s-audio";
+ simple-audio-card,pin-switches = "mic-in";
+ simple-audio-card,widgets = "Microphone\0mic-in";
+ simple-audio-card,routing = "MIC2\0mic-in";
+ phandle = <0x81>;
+
+ simple-audio-card,cpu {
+ sound-dai = <0x16>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <0x17>;
+ };
+ };
+
+ __symbols__ {
+ scmi = "/firmware/scmi";
+ scmi_dvfs = "/firmware/scmi/protocol@13";
+ scmi_sensors0 = "/firmware/scmi/protocol@15";
+ cpu = "/cpus";
+ cpu_l0 = "/cpus/cpu@0";
+ cpu_l1 = "/cpus/cpu@1";
+ cpu_b0 = "/cpus/cpu@100";
+ cpu_b1 = "/cpus/cpu@101";
+ gic = "/interrupt-controller@30800000";
+ its = "/interrupt-controller@30800000/gic-its@30820000";
+ sysclk_48mhz = "/clocks/clk48mhz";
+ sysclk_50mhz = "/clocks/clk50mhz";
+ sysclk_100mhz = "/clocks/clk100mhz";
+ sysclk_200mhz = "/clocks/clk200mhz";
+ sysclk_250mhz = "/clocks/clk250mhz";
+ sysclk_300mhz = "/clocks/clk300mhz";
+ sysclk_600mhz = "/clocks/clk600mhz";
+ sysclk_1200mhz = "/clocks/clk1200mhz";
+ smmu = "/iommu@30000000";
+ soc = "/soc";
+ mmc0 = "/soc/mmc@28000000";
+ mmc1 = "/soc/mmc@28001000";
+ nand0 = "/soc/nand@28002000";
+ ddma0 = "/soc/ddma@28003000";
+ ddma1 = "/soc/ddma@28004000";
+ qspi0 = "/soc/spi@28008000";
+ // uart0 = "/soc/uart@2800c000";
+ uart1 = "/soc/uart@2800d000";
+ // uart2 = "/soc/uart@2800e000";
+ // uart3 = "/soc/uart@2800f000";
+ lpc = "/soc/lpc@28010000";
+ kcs0 = "/soc/lpc@28010000/kcs@24";
+ kcs1 = "/soc/lpc@28010000/kcs@28";
+ kcs2 = "/soc/lpc@28010000/kcs@2c";
+ kcs3 = "/soc/lpc@28010000/kcs@8c";
+ bt = "/soc/lpc@28010000/bt@48";
+ gpio0 = "/soc/gpio@28034000";
+ gpio1 = "/soc/gpio@28035000";
+ gpio2 = "/soc/gpio@28036000";
+ gpio3 = "/soc/gpio@28037000";
+ gpio4 = "/soc/gpio@28038000";
+ gpio5 = "/soc/gpio@28039000";
+ spi0 = "/soc/spi@2803a000";
+ spi1 = "/soc/spi@2803b000";
+ spi2 = "/soc/spi@2803c000";
+ spi3 = "/soc/spi@2803d000";
+ watchdog0 = "/soc/watchdog@28040000";
+ watchdog1 = "/soc/watchdog@28042000";
+ pwm0 = "/soc/pwm@2804a000";
+ pwm1 = "/soc/pwm@2804b000";
+ tacho0 = "/soc/tacho@28054000";
+ tacho1 = "/soc/tacho@28055000";
+ tacho2 = "/soc/tacho@28056000";
+ tacho3 = "/soc/tacho@28057000";
+ tacho4 = "/soc/tacho@28058000";
+ tacho5 = "/soc/tacho@28059000";
+ tacho6 = "/soc/tacho@2805a000";
+ tacho7 = "/soc/tacho@2805b000";
+ tacho8 = "/soc/tacho@2805c000";
+ tacho9 = "/soc/tacho@2805d000";
+ tacho10 = "/soc/tacho@2805e000";
+ tacho11 = "/soc/tacho@2805f000";
+ tacho12 = "/soc/tacho@28060000";
+ tacho13 = "/soc/tacho@28061000";
+ tacho14 = "/soc/tacho@28062000";
+ tacho15 = "/soc/tacho@28063000";
+ tacho16 = "/soc/tacho@28064000";
+ tacho17 = "/soc/tacho@28065000";
+ tacho18 = "/soc/tacho@28066000";
+ tacho19 = "/soc/tacho@28067000";
+ tacho20 = "/soc/tacho@28068000";
+ tacho21 = "/soc/tacho@28069000";
+ tacho22 = "/soc/tacho@2806a000";
+ tacho23 = "/soc/tacho@2806b000";
+ tacho24 = "/soc/tacho@2806c000";
+ tacho25 = "/soc/tacho@2806d000";
+ tacho26 = "/soc/tacho@2806e000";
+ tacho27 = "/soc/tacho@2806f000";
+ tacho28 = "/soc/tacho@28070000";
+ tacho29 = "/soc/tacho@28071000";
+ tacho30 = "/soc/tacho@28072000";
+ tacho31 = "/soc/tacho@28073000";
+ tacho32 = "/soc/tacho@28074000";
+ tacho33 = "/soc/tacho@28075000";
+ tacho34 = "/soc/tacho@28076000";
+ tacho35 = "/soc/tacho@28077000";
+ tacho36 = "/soc/tacho@28078000";
+ tacho37 = "/soc/tacho@28079000";
+ usb2_0 = "/soc/usb2@31800000";
+ usb2_1 = "/soc/usb2@31880000";
+ usb2_2 = "/soc/usb2@31900000";
+ usb2_3 = "/soc/usb2@32800000";
+ usb2_4 = "/soc/usb2@32840000";
+ // dc0 = "/soc/dc@32000000";
+ i2s_dp0 = "/soc/i2s_dp0@32009000";
+ i2s_dp1 = "/soc/i2s_dp1@3200B000";
+ pmdk_dp = "/soc/pmdk_dp";
+ mbox = "/soc/mailbox@32a00000";
+ rng0 = "/soc/rng@32a36000";
+ sram = "/soc/sram@32a10000";
+ cpu_scp_lpri = "/soc/sram@32a10000/scp-shmem@0";
+ cpu_scp_hpri = "/soc/sram@32a10000/scp-shmem@1";
+ // gdma = "/soc/gdma@32b34000";
+ hwspinlock = "/soc/spinlock@32b36000";
+ pcie = "/soc/pcie@40000000";
+ edac = "/soc/edac@32b28000";
+ hda0 = "/soc/hda@28006000";
+ i2s0 = "/soc/i2s@28009000";
+ can0 = "/soc/can@2800a000";
+ can1 = "/soc/can@2800b000";
+ keypad = "/soc/keypad@2807a000";
+ usb3_0 = "/soc/usb3@31a08000";
+ usb3_1 = "/soc/usb3@31a28000";
+ sata0 = "/soc/sata@31a40000";
+ sata1 = "/soc/sata@32014000";
+ macb0 = "/soc/ethernet@3200c000";
+ // macb1 = "/soc/ethernet@3200e000";
+ // macb2 = "/soc/ethernet@32010000";
+ // macb3 = "/soc/ethernet@32012000";
+ vpu0 = "/soc/vpu@32b00000";
+ mio9 = "/soc/i2c@28026000";
+ mio14 = "/soc/i2c@28030000";
+ codec0 = "/soc/i2c@28030000/es8336@10";
+ // mio0 = "/soc/uart@28014000";
+ mio1 = "/soc/i2c@28016000";
+ mio8 = "/soc/i2c@28024000";
+ // mio11 = "/soc/uart@2802A000";
+ // mio15 = "/soc/uart@28032000";
+ sound_card = "/sound";
+ };
+};
diff --git a/platform/aarch64/phytium-pi/image/dts/linux2.dts b/platform/aarch64/phytium-pi/image/dts/linux2.dts
new file mode 100644
index 00000000..1d2e9326
--- /dev/null
+++ b/platform/aarch64/phytium-pi/image/dts/linux2.dts
@@ -0,0 +1,389 @@
+/dts-v1/;
+
+/memreserve/ 0x0000000080000000 0x0000000000010000;
+/ {
+ compatible = "phytium,pe2204";
+ interrupt-parent = <0x01>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ model = "Phytium Pi Board";
+
+ aliases {
+ serial1 = "/soc/uart@2800d000";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ sys_poweroff = <0x84000008>;
+ sys_reset = <0x84000009>;
+ };
+
+ firmware {
+
+ scmi {
+ compatible = "arm,scmi";
+ mboxes = <0x02 0x00>;
+ mbox-names = "tx";
+ shmem = <0x03>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ phandle = <0x18>;
+
+ protocol@13 {
+ reg = <0x13>;
+ #clock-cells = <0x01>;
+ phandle = <0x09>;
+ };
+
+ protocol@15 {
+ reg = <0x15>;
+ #thermal-sensor-cells = <0x01>;
+ phandle = <0x04>;
+ };
+ };
+
+ // optee {
+ // compatible = "linaro,optee-tz";
+ // method = "smc";
+ // };
+ };
+
+ cpus {
+ #address-cells = <0x02>;
+ #size-cells = <0x00>;
+ phandle = <0x19>;
+
+ cpu-map {
+
+ cluster0 {
+
+ core0 {
+ cpu = <0x05>;
+ };
+ };
+
+ cluster1 {
+
+ core0 {
+ cpu = <0x06>;
+ };
+ };
+
+ // cluster2 {
+
+ // core0 {
+ // cpu = <0x07>;
+ // };
+
+ // core1 {
+ // cpu = <0x08>;
+ // };
+ // };
+
+
+ };
+
+ // cpu@0 {
+ // device_type = "cpu";
+ // compatible = "phytium,ftc310\0arm,armv8";
+ // reg = <0x00 0x200>;
+ // enable-method = "psci";
+ // clocks = <0x09 0x02>;
+ // capacity-dmips-mhz = <0xb22>;
+ // phandle = <0x07>;
+ // };
+
+ // cpu@1 {
+ // device_type = "cpu";
+ // compatible = "phytium,ftc310\0arm,armv8";
+ // reg = <0x00 0x201>;
+ // enable-method = "psci";
+ // clocks = <0x09 0x02>;
+ // capacity-dmips-mhz = <0xb22>;
+ // phandle = <0x08>;
+ // };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "phytium,ftc664\0arm,armv8";
+ reg = <0x00 0x00>;
+ enable-method = "psci";
+ clocks = <0x09 0x00>;
+ capacity-dmips-mhz = <0x161c>;
+ phandle = <0x05>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "phytium,ftc664\0arm,armv8";
+ reg = <0x00 0x100>;
+ enable-method = "psci";
+ clocks = <0x09 0x01>;
+ capacity-dmips-mhz = <0x161c>;
+ phandle = <0x06>;
+ };
+ };
+
+
+
+ interrupt-controller@30800000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <0x03>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ interrupt-controller;
+ reg = <0x00 0x30800000 0x00 0x20000 0x00 0x30880000 0x00 0x80000>;
+ // reg = <0x00 0x30800000 0x00 0x20000 0x00 0x30880000 0x00 0x80000 0x00 0x30840000 0x00 0x10000 0x00 0x30850000 0x00 0x10000 0x00 0x30860000 0x00 0x10000>;
+ interrupts = <0x01 0x09 0x08>;
+ phandle = <0x01>;
+
+ // gic-its@30820000 {
+ // compatible = "arm,gic-v3-its";
+ // msi-controller;
+ // reg = <0x00 0x30820000 0x00 0x20000>;
+ // phandle = <0x0f>;
+ // };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0x01 0x07 0x08>;
+ };
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
+ clock-frequency = <0x2faf080>;
+ };
+
+
+ clocks {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ clk48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x2dc6c00>;
+ phandle = <0x13>;
+ };
+
+ clk50mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x2faf080>;
+ phandle = <0x0d>;
+ };
+
+ clk100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x5f5e100>;
+ phandle = <0x0c>;
+ };
+
+ clk200mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0xbebc200>;
+ phandle = <0x11>;
+ };
+
+ clk250mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0xee6b280>;
+ phandle = <0x12>;
+ };
+
+ clk300mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x11e1a300>;
+ phandle = <0x0b>;
+ };
+
+ clk600mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x23c34600>;
+ phandle = <0x0e>;
+ };
+
+ clk1200mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x47868c00>;
+ phandle = <0x0a>;
+ };
+ };
+
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ dma-coherent;
+ ranges;
+ phandle = <0x1a>;
+ // mmc@28000000 {
+ // compatible = "phytium,mci";
+ // reg = <0x00 0x28000000 0x00 0x1000>;
+ // interrupts = <0x00 0x48 0x04>;
+ // clocks = <0x0a>;
+ // clock-names = "phytium_mci_clk";
+ // status = "okay";
+ // bus-width = <0x04>;
+ // max-frequency = <0x2faf080>;
+ // cap-sdio-irq;
+ // cap-sd-highspeed;
+ // no-mmc;
+ // phandle = <0x1b>;
+ // };
+
+ // mmc@28001000 {
+ // compatible = "phytium,mci";
+ // reg = <0x00 0x28001000 0x00 0x1000>;
+ // interrupts = <0x00 0x49 0x04>;
+ // clocks = <0x0a>;
+ // clock-names = "phytium_mci_clk";
+ // status = "okay";
+ // bus-width = <0x04>;
+ // max-frequency = <0x2faf080>;
+ // #sd-uhs-sdr25;
+ // #sd-uhs-sdr50;
+ // cap-sdio-irq;
+ // cap-sd-highspeed;
+ // no-mmc;
+ // no-sd;
+ // non-removable;
+ // phandle = <0x1c>;
+ // };
+ // uart@2800d000 {
+ // compatible = "arm,pl011\0arm,primecell";
+ // reg = <0x00 0x2800d000 0x00 0x1000>;
+ // interrupts = <0x00 0x54 0x04>;
+ // clocks = <0x0c 0x0c>;
+ // clock-names = "uartclk\0apb_pclk";
+ // status = "okay";
+ // phandle = <0x22>;
+ // };
+ mailbox@32a00000 {
+ compatible = "phytium,mbox";
+ reg = <0x00 0x32a00000 0x00 0x1000>;
+ interrupts = <0x00 0x16 0x04>;
+ #mbox-cells = <0x01>;
+ phandle = <0x02>;
+ };
+
+ sram@32a10000 {
+ compatible = "phytium,pe220x-sram-ns\0mmio-sram";
+ reg = <0x00 0x32a10000 0x00 0x2000>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x00 0x32a10000 0x2000>;
+ phandle = <0x67>;
+
+ scp-shmem@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x1000 0x400>;
+ phandle = <0x68>;
+ };
+
+ scp-shmem@1 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x1400 0x400>;
+ phandle = <0x03>;
+ };
+ };
+ // i2c@28026000 {
+ // compatible = "phytium,i2c";
+ // reg = <0x00 0x28026000 0x00 0x1000>;
+ // interrupts = <0x00 0x65 0x04>;
+ // clocks = <0x0d>;
+ // #address-cells = <0x01>;
+ // #size-cells = <0x00>;
+ // status = "okay";
+ // phandle = <0x7a>;
+
+ // rtc@68 {
+ // compatible = "dallas,ds1339";
+ // reg = <0x68>;
+ // };
+ // };
+
+ };
+
+ // virtio blk
+ virtio_mmio@a003c00 {
+ dma-coherent;
+ interrupt-parent = <0x01>;
+ interrupts = <0x0 0x2e 0x1>;
+ reg = <0x0 0xa003c00 0x0 0x200>;
+ compatible = "virtio,mmio";
+ };
+ //virtio serial
+ virtio_mmio@a003800 {
+ dma-coherent;
+ interrupt-parent = <0x01>;
+ interrupts = <0x0 0x2c 0x1>;
+ reg = <0x0 0xa003800 0x0 0x200>;
+ compatible = "virtio,mmio";
+ };
+ hvisor_virtio_device {
+ compatible = "hvisor";
+ interrupt-parent = <0x01>;
+ interrupts = <0x00 0x20 0x01>;
+ };
+
+
+ chosen {
+
+ stdout-path = "/virtio_mmio@a003800";
+ bootargs = "clk_ignore_unused earlycon=virtio,mmio,0xa003800 console=hvc0 root=/dev/vda rootwait rw init=/bin/sh";
+ // stdout-path = "serial1:115200n8";
+ // bootargs = "clk_ignore_unused console=ttyAMA1,115200 earlycon=pl011,0x2800d000,115200 root=/dev/vda rw rootwait init=/bin/sh";
+
+ };
+
+
+ memory@b0000000 {
+ device_type = "memory";
+ reg = <0x0 0xb0000000 0x00 0x30000000>;
+ };
+
+ __symbols__ {
+ scmi = "/firmware/scmi";
+ scmi_dvfs = "/firmware/scmi/protocol@13";
+ scmi_sensors0 = "/firmware/scmi/protocol@15";
+ cpu = "/cpus";
+ cpu_l0 = "/cpus/cpu@0";
+ cpu_l1 = "/cpus/cpu@1";
+ cpu_b0 = "/cpus/cpu@100";
+ cpu_b1 = "/cpus/cpu@101";
+ gic = "/interrupt-controller@30800000";
+ // its = "/interrupt-controller@30800000/gic-its@30820000";
+ sysclk_48mhz = "/clocks/clk48mhz";
+ sysclk_50mhz = "/clocks/clk50mhz";
+ sysclk_100mhz = "/clocks/clk100mhz";
+ sysclk_200mhz = "/clocks/clk200mhz";
+ sysclk_250mhz = "/clocks/clk250mhz";
+ sysclk_300mhz = "/clocks/clk300mhz";
+ sysclk_600mhz = "/clocks/clk600mhz";
+ sysclk_1200mhz = "/clocks/clk1200mhz";
+ soc = "/soc";
+ // mmc0 = "/soc/mmc@28000000";
+ // mmc1 = "/soc/mmc@28001000";
+ // uart1 = "/soc/uart@2800d000";
+ mbox = "/soc/mailbox@32a00000";
+ sram = "/soc/sram@32a10000";
+ cpu_scp_lpri = "/soc/sram@32a10000/scp-shmem@0";
+ cpu_scp_hpri = "/soc/sram@32a10000/scp-shmem@1";
+ // mio9 = "/soc/i2c@28026000";
+ };
+};
diff --git a/platform/aarch64/phytium-pi/image/dts/phytium-pi-board-v2.dts b/platform/aarch64/phytium-pi/image/dts/phytium-pi-board-v2.dts
new file mode 100644
index 00000000..457e171e
--- /dev/null
+++ b/platform/aarch64/phytium-pi/image/dts/phytium-pi-board-v2.dts
@@ -0,0 +1,1534 @@
+/dts-v1/;
+
+/memreserve/ 0x0000000080000000 0x0000000000010000;
+/ {
+ compatible = "phytium,pe2204";
+ interrupt-parent = <0x01>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ model = "Phytium Pi Board";
+
+ aliases {
+ serial0 = "/soc/uart@2800c000";
+ serial1 = "/soc/uart@2800d000";
+ serial2 = "/soc/uart@2800e000";
+ serial3 = "/soc/uart@2800f000";
+ ethernet0 = "/soc/ethernet@3200c000";
+ ethernet1 = "/soc/ethernet@3200e000";
+ ethernet2 = "/soc/ethernet@32010000";
+ ethernet3 = "/soc/ethernet@32012000";
+ serial4 = "/soc/uart@28014000";
+ serial7 = "/soc/uart@2802A000";
+ serial8 = "/soc/uart@28032000";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ sys_poweroff = <0x84000008>;
+ sys_reset = <0x84000009>;
+ };
+
+ firmware {
+
+ scmi {
+ compatible = "arm,scmi";
+ mboxes = <0x02 0x00>;
+ mbox-names = "tx";
+ shmem = <0x03>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ phandle = <0x18>;
+
+ protocol@13 {
+ reg = <0x13>;
+ #clock-cells = <0x01>;
+ phandle = <0x09>;
+ };
+
+ protocol@15 {
+ reg = <0x15>;
+ #thermal-sensor-cells = <0x01>;
+ phandle = <0x04>;
+ };
+ };
+
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ thermal-zones {
+
+ sensor0 {
+ polling-delay-passive = <0x64>;
+ polling-delay = <0x3e8>;
+ thermal-sensors = <0x04 0x00>;
+ };
+
+ sensor1 {
+ polling-delay-passive = <0x64>;
+ polling-delay = <0x3e8>;
+ thermal-sensors = <0x04 0x01>;
+ };
+ };
+
+ cpus {
+ #address-cells = <0x02>;
+ #size-cells = <0x00>;
+ phandle = <0x19>;
+
+ cpu-map {
+
+ cluster0 {
+
+ core0 {
+ cpu = <0x05>;
+ };
+ };
+
+ cluster1 {
+
+ core0 {
+ cpu = <0x06>;
+ };
+ };
+
+ cluster2 {
+
+ core0 {
+ cpu = <0x07>;
+ };
+
+ core1 {
+ cpu = <0x08>;
+ };
+ };
+ };
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "phytium,ftc310\0arm,armv8";
+ reg = <0x00 0x200>;
+ enable-method = "psci";
+ clocks = <0x09 0x02>;
+ capacity-dmips-mhz = <0xb22>;
+ phandle = <0x07>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "phytium,ftc310\0arm,armv8";
+ reg = <0x00 0x201>;
+ enable-method = "psci";
+ clocks = <0x09 0x02>;
+ capacity-dmips-mhz = <0xb22>;
+ phandle = <0x08>;
+ };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "phytium,ftc664\0arm,armv8";
+ reg = <0x00 0x00>;
+ enable-method = "psci";
+ clocks = <0x09 0x00>;
+ capacity-dmips-mhz = <0x161c>;
+ phandle = <0x05>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "phytium,ftc664\0arm,armv8";
+ reg = <0x00 0x100>;
+ enable-method = "psci";
+ clocks = <0x09 0x01>;
+ capacity-dmips-mhz = <0x161c>;
+ phandle = <0x06>;
+ };
+ };
+
+ interrupt-controller@30800000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <0x03>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ interrupt-controller;
+ reg = <0x00 0x30800000 0x00 0x20000 0x00 0x30880000 0x00 0x80000 0x00 0x30840000 0x00 0x10000 0x00 0x30850000 0x00 0x10000 0x00 0x30860000 0x00 0x10000>;
+ interrupts = <0x01 0x09 0x08>;
+ phandle = <0x01>;
+
+ gic-its@30820000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ reg = <0x00 0x30820000 0x00 0x20000>;
+ phandle = <0x0f>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0x01 0x07 0x08>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
+ clock-frequency = <0x2faf080>;
+ };
+
+ clocks {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ clk48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x2dc6c00>;
+ phandle = <0x13>;
+ };
+
+ clk50mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x2faf080>;
+ phandle = <0x0d>;
+ };
+
+ clk100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x5f5e100>;
+ phandle = <0x0c>;
+ };
+
+ clk200mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0xbebc200>;
+ phandle = <0x11>;
+ };
+
+ clk250mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0xee6b280>;
+ phandle = <0x12>;
+ };
+
+ clk300mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x11e1a300>;
+ phandle = <0x0b>;
+ };
+
+ clk600mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x23c34600>;
+ phandle = <0x0e>;
+ };
+
+ clk1200mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x47868c00>;
+ phandle = <0x0a>;
+ };
+ };
+
+ iommu@30000000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x00 0x30000000 0x00 0x800000>;
+ interrupts = <0x00 0xf0 0x01 0x00 0xef 0x01 0x00 0xec 0x01 0x00 0xf2 0x01>;
+ interrupt-names = "eventq\0priq\0cmdq-sync\0gerror";
+ dma-coherent;
+ #iommu-cells = <0x01>;
+ phandle = <0x10>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ dma-coherent;
+ ranges;
+ phandle = <0x1a>;
+
+ mmc@28000000 {
+ compatible = "phytium,mci";
+ reg = <0x00 0x28000000 0x00 0x1000>;
+ interrupts = <0x00 0x48 0x04>;
+ clocks = <0x0a>;
+ clock-names = "phytium_mci_clk";
+ status = "okay";
+ bus-width = <0x04>;
+ max-frequency = <0x2faf080>;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ no-mmc;
+ phandle = <0x1b>;
+ };
+
+ mmc@28001000 {
+ compatible = "phytium,mci";
+ reg = <0x00 0x28001000 0x00 0x1000>;
+ interrupts = <0x00 0x49 0x04>;
+ clocks = <0x0a>;
+ clock-names = "phytium_mci_clk";
+ status = "okay";
+ bus-width = <0x04>;
+ max-frequency = <0x2faf080>;
+ #sd-uhs-sdr25;
+ #sd-uhs-sdr50;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ no-mmc;
+ no-sd;
+ non-removable;
+ phandle = <0x1c>;
+ };
+
+ nand@28002000 {
+ compatible = "phytium,nfc";
+ reg = <0x00 0x28002000 0x00 0x1000>;
+ interrupts = <0x00 0x4a 0x04>;
+ status = "disabled";
+ phandle = <0x1d>;
+ };
+
+ ddma@28003000 {
+ compatible = "phytium,ddma";
+ reg = <0x00 0x28003000 0x00 0x1000>;
+ interrupts = <0x00 0x4b 0x04>;
+ #dma-cells = <0x02>;
+ dma-channels = <0x08>;
+ phandle = <0x1e>;
+ };
+
+ ddma@28004000 {
+ compatible = "phytium,ddma";
+ reg = <0x00 0x28004000 0x00 0x1000>;
+ interrupts = <0x00 0x4c 0x04>;
+ #dma-cells = <0x02>;
+ dma-channels = <0x08>;
+ phandle = <0x1f>;
+ };
+
+ spi@28008000 {
+ compatible = "phytium,qspi-nor";
+ reg = <0x00 0x28008000 0x00 0x1000 0x00 0x00 0x00 0xfffffff>;
+ reg-names = "qspi\0qspi_mm";
+ clocks = <0x0b>;
+ status = "okay";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ phandle = <0x20>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x00>;
+ spi-rx-bus-width = <0x01>;
+ spi-max-frequency = <0x1312d00>;
+ status = "okay";
+ };
+ };
+
+ uart@2800c000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x2800c000 0x00 0x1000>;
+ interrupts = <0x00 0x53 0x04>;
+ clocks = <0x0c 0x0c>;
+ clock-names = "uartclk\0apb_pclk";
+ status = "okay";
+ phandle = <0x21>;
+ };
+
+ uart@2800d000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x2800d000 0x00 0x1000>;
+ interrupts = <0x00 0x54 0x04>;
+ clocks = <0x0c 0x0c>;
+ clock-names = "uartclk\0apb_pclk";
+ status = "okay";
+ phandle = <0x22>;
+ };
+
+ uart@2800e000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x2800e000 0x00 0x1000>;
+ interrupts = <0x00 0x55 0x04>;
+ clocks = <0x0c 0x0c>;
+ clock-names = "uartclk\0apb_pclk";
+ status = "okay";
+ phandle = <0x23>;
+ };
+
+ uart@2800f000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x2800f000 0x00 0x1000>;
+ interrupts = <0x00 0x56 0x04>;
+ clocks = <0x0c 0x0c>;
+ clock-names = "uartclk\0apb_pclk";
+ status = "okay";
+ phandle = <0x24>;
+ };
+
+ lpc@28010000 {
+ compatible = "simple-mfd\0syscon";
+ reg = <0x00 0x28010000 0x00 0x1000>;
+ reg-io-width = <0x04>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x00 0x28010000 0x1000>;
+ phandle = <0x25>;
+
+ kcs@24 {
+ compatible = "phytium,kcs-bmc";
+ reg = <0x24 0x01 0x30 0x01 0x3c 0x01>;
+ interrupts = <0x00 0x58 0x04>;
+ status = "disabled";
+ phandle = <0x26>;
+ };
+
+ kcs@28 {
+ compatible = "phytium,kcs-bmc";
+ reg = <0x28 0x01 0x34 0x01 0x40 0x01>;
+ interrupts = <0x00 0x58 0x04>;
+ status = "disabled";
+ phandle = <0x27>;
+ };
+
+ kcs@2c {
+ compatible = "phytium,kcs-bmc";
+ reg = <0x2c 0x01 0x38 0x01 0x44 0x01>;
+ interrupts = <0x00 0x58 0x04>;
+ status = "disabled";
+ phandle = <0x28>;
+ };
+
+ kcs@8c {
+ compatible = "phytium,kcs-bmc";
+ reg = <0x8c 0x01 0x90 0x01 0x94 0x01>;
+ interrupts = <0x00 0x58 0x04>;
+ status = "disabled";
+ phandle = <0x29>;
+ };
+
+ bt@48 {
+ compatible = "phytium,bt-bmc";
+ reg = <0x48 0x20>;
+ interrupts = <0x00 0x58 0x04>;
+ status = "disabled";
+ phandle = <0x2a>;
+ };
+ };
+
+ gpio@28034000 {
+ compatible = "phytium,gpio";
+ reg = <0x00 0x28034000 0x00 0x1000>;
+ interrupts = <0x00 0x6c 0x04 0x00 0x6d 0x04 0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04 0x00 0x71 0x04 0x00 0x72 0x04 0x00 0x73 0x04 0x00 0x74 0x04 0x00 0x75 0x04 0x00 0x76 0x04 0x00 0x77 0x04 0x00 0x78 0x04 0x00 0x79 0x04 0x00 0x7a 0x04 0x00 0x7b 0x04>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x2b>;
+
+ porta {
+ compatible = "phytium,gpio-port";
+ reg = <0x00>;
+ ngpios = <0x10>;
+ };
+ };
+
+ gpio@28035000 {
+ compatible = "phytium,gpio";
+ reg = <0x00 0x28035000 0x00 0x1000>;
+ interrupts = <0x00 0x7c 0x04 0x00 0x7d 0x04 0x00 0x7e 0x04 0x00 0x7f 0x04 0x00 0x80 0x04 0x00 0x81 0x04 0x00 0x82 0x04 0x00 0x83 0x04 0x00 0x84 0x04 0x00 0x85 0x04 0x00 0x86 0x04 0x00 0x87 0x04 0x00 0x88 0x04 0x00 0x89 0x04 0x00 0x8a 0x04 0x00 0x8b 0x04>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x15>;
+
+ porta {
+ compatible = "phytium,gpio-port";
+ reg = <0x00>;
+ ngpios = <0x10>;
+ };
+ };
+
+ gpio@28036000 {
+ compatible = "phytium,gpio";
+ reg = <0x00 0x28036000 0x00 0x1000>;
+ interrupts = <0x00 0x8c 0x04 0x00 0x8d 0x04 0x00 0x8e 0x04 0x00 0x8f 0x04 0x00 0x90 0x04 0x00 0x91 0x04 0x00 0x92 0x04 0x00 0x93 0x04 0x00 0x94 0x04 0x00 0x95 0x04 0x00 0x96 0x04 0x00 0x97 0x04 0x00 0x98 0x04 0x00 0x99 0x04 0x00 0x9a 0x04 0x00 0x9b 0x04>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x14>;
+
+ porta {
+ compatible = "phytium,gpio-port";
+ reg = <0x00>;
+ ngpios = <0x10>;
+ };
+ };
+
+ gpio@28037000 {
+ compatible = "phytium,gpio";
+ reg = <0x00 0x28037000 0x00 0x1000>;
+ interrupts = <0x00 0x9c 0x04>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x2c>;
+
+ porta {
+ compatible = "phytium,gpio-port";
+ reg = <0x00>;
+ ngpios = <0x10>;
+ };
+ };
+
+ gpio@28038000 {
+ compatible = "phytium,gpio";
+ reg = <0x00 0x28038000 0x00 0x1000>;
+ interrupts = <0x00 0x9d 0x04>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x2d>;
+
+ porta {
+ compatible = "phytium,gpio-port";
+ reg = <0x00>;
+ ngpios = <0x10>;
+ };
+ };
+
+ gpio@28039000 {
+ compatible = "phytium,gpio";
+ reg = <0x00 0x28039000 0x00 0x1000>;
+ interrupts = <0x00 0x9e 0x04>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x2e>;
+
+ porta {
+ compatible = "phytium,gpio-port";
+ reg = <0x00>;
+ ngpios = <0x10>;
+ };
+ };
+
+ spi@2803a000 {
+ compatible = "phytium,spi";
+ reg = <0x00 0x2803a000 0x00 0x1000>;
+ interrupts = <0x00 0x9f 0x04>;
+ clocks = <0x0d>;
+ num-cs = <0x04>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ global-cs = <0x01>;
+ phandle = <0x2f>;
+ };
+
+ spi@2803b000 {
+ compatible = "phytium,spi";
+ reg = <0x00 0x2803b000 0x00 0x1000>;
+ interrupts = <0x00 0xa0 0x04>;
+ clocks = <0x0d>;
+ num-cs = <0x04>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "disabled";
+ phandle = <0x30>;
+ };
+
+ spi@2803c000 {
+ compatible = "phytium,spi";
+ reg = <0x00 0x2803c000 0x00 0x1000>;
+ interrupts = <0x00 0xa1 0x04>;
+ clocks = <0x0d>;
+ num-cs = <0x04>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "disabled";
+ phandle = <0x31>;
+ };
+
+ spi@2803d000 {
+ compatible = "phytium,spi";
+ reg = <0x00 0x2803d000 0x00 0x1000>;
+ interrupts = <0x00 0xa2 0x04>;
+ clocks = <0x0d>;
+ num-cs = <0x04>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "disabled";
+ phandle = <0x32>;
+ };
+
+ watchdog@28040000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x00 0x28041000 0x00 0x1000 0x00 0x28040000 0x00 0x1000>;
+ interrupts = <0x00 0xa4 0x04>;
+ timeout-sec = <0x1e>;
+ status = "okay";
+ phandle = <0x33>;
+ };
+
+ watchdog@28042000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x00 0x28043000 0x00 0x1000 0x00 0x28042000 0x00 0x1000>;
+ interrupts = <0x00 0xa5 0x04>;
+ timeout-sec = <0x1e>;
+ status = "okay";
+ phandle = <0x34>;
+ };
+
+ pwm@2804a000 {
+ compatible = "phytium,pwm";
+ reg = <0x00 0x2804a000 0x00 0x1000>;
+ interrupts = <0x00 0xad 0x04>;
+ clocks = <0x0d>;
+ status = "okay";
+ phytium,db = <0x00 0x00 0x64 0x3e8 0x3e8 0x00>;
+ phandle = <0x35>;
+ };
+
+ pwm@2804b000 {
+ compatible = "phytium,pwm";
+ reg = <0x00 0x2804b000 0x00 0x1000>;
+ interrupts = <0x00 0xae 0x04>;
+ clocks = <0x0d>;
+ status = "okay";
+ phytium,db = <0x00 0x00 0x64 0x3e8 0x3e8 0x00>;
+ phandle = <0x36>;
+ };
+
+ tacho@28054000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28054000 0x00 0x1000>;
+ interrupts = <0x00 0xc2 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x37>;
+ };
+
+ tacho@28055000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28055000 0x00 0x1000>;
+ interrupts = <0x00 0xc3 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x38>;
+ };
+
+ tacho@28056000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28056000 0x00 0x1000>;
+ interrupts = <0x00 0xc4 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x39>;
+ };
+
+ tacho@28057000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28057000 0x00 0x1000>;
+ interrupts = <0x00 0xc5 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x3a>;
+ };
+
+ tacho@28058000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28058000 0x00 0x1000>;
+ interrupts = <0x00 0xc6 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x3b>;
+ };
+
+ tacho@28059000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28059000 0x00 0x1000>;
+ interrupts = <0x00 0xc7 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x3c>;
+ };
+
+ tacho@2805a000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2805a000 0x00 0x1000>;
+ interrupts = <0x00 0xc8 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x3d>;
+ };
+
+ tacho@2805b000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2805b000 0x00 0x1000>;
+ interrupts = <0x00 0xc9 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x3e>;
+ };
+
+ tacho@2805c000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2805c000 0x00 0x1000>;
+ interrupts = <0x00 0xca 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x3f>;
+ };
+
+ tacho@2805d000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2805d000 0x00 0x1000>;
+ interrupts = <0x00 0xcb 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x40>;
+ };
+
+ tacho@2805e000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2805e000 0x00 0x1000>;
+ interrupts = <0x00 0xcc 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x41>;
+ };
+
+ tacho@2805f000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2805f000 0x00 0x1000>;
+ interrupts = <0x00 0xcd 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x42>;
+ };
+
+ tacho@28060000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28060000 0x00 0x1000>;
+ interrupts = <0x00 0xce 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x43>;
+ };
+
+ tacho@28061000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28061000 0x00 0x1000>;
+ interrupts = <0x00 0xcf 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x44>;
+ };
+
+ tacho@28062000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28062000 0x00 0x1000>;
+ interrupts = <0x00 0xd0 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x45>;
+ };
+
+ tacho@28063000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28063000 0x00 0x1000>;
+ interrupts = <0x00 0xd1 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x46>;
+ };
+
+ tacho@28064000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28064000 0x00 0x1000>;
+ interrupts = <0x00 0xd2 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x47>;
+ };
+
+ tacho@28065000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28065000 0x00 0x1000>;
+ interrupts = <0x00 0xd3 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x48>;
+ };
+
+ tacho@28066000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28066000 0x00 0x1000>;
+ interrupts = <0x00 0xd4 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x49>;
+ };
+
+ tacho@28067000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28067000 0x00 0x1000>;
+ interrupts = <0x00 0xd5 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x4a>;
+ };
+
+ tacho@28068000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28068000 0x00 0x1000>;
+ interrupts = <0x00 0xd6 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x4b>;
+ };
+
+ tacho@28069000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28069000 0x00 0x1000>;
+ interrupts = <0x00 0xd7 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x4c>;
+ };
+
+ tacho@2806a000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2806a000 0x00 0x1000>;
+ interrupts = <0x00 0xd8 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x4d>;
+ };
+
+ tacho@2806b000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2806b000 0x00 0x1000>;
+ interrupts = <0x00 0xd9 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x4e>;
+ };
+
+ tacho@2806c000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2806c000 0x00 0x1000>;
+ interrupts = <0x00 0xda 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x4f>;
+ };
+
+ tacho@2806d000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2806d000 0x00 0x1000>;
+ interrupts = <0x00 0xdb 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x50>;
+ };
+
+ tacho@2806e000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2806e000 0x00 0x1000>;
+ interrupts = <0x00 0xdc 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x51>;
+ };
+
+ tacho@2806f000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x2806f000 0x00 0x1000>;
+ interrupts = <0x00 0xdd 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x52>;
+ };
+
+ tacho@28070000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28070000 0x00 0x1000>;
+ interrupts = <0x00 0xde 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x53>;
+ };
+
+ tacho@28071000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28071000 0x00 0x1000>;
+ interrupts = <0x00 0xdf 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x54>;
+ };
+
+ tacho@28072000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28072000 0x00 0x1000>;
+ interrupts = <0x00 0xe0 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x55>;
+ };
+
+ tacho@28073000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28073000 0x00 0x1000>;
+ interrupts = <0x00 0xe1 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x56>;
+ };
+
+ tacho@28074000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28074000 0x00 0x1000>;
+ interrupts = <0x00 0xe2 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x57>;
+ };
+
+ tacho@28075000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28075000 0x00 0x1000>;
+ interrupts = <0x00 0xe3 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x58>;
+ };
+
+ tacho@28076000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28076000 0x00 0x1000>;
+ interrupts = <0x00 0xe4 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x59>;
+ };
+
+ tacho@28077000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28077000 0x00 0x1000>;
+ interrupts = <0x00 0xe5 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x5a>;
+ };
+
+ tacho@28078000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28078000 0x00 0x1000>;
+ interrupts = <0x00 0xe6 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x5b>;
+ };
+
+ tacho@28079000 {
+ compatible = "phytium,tacho";
+ reg = <0x00 0x28079000 0x00 0x1000>;
+ interrupts = <0x00 0xe7 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x5c>;
+ };
+
+ usb2@31800000 {
+ compatible = "phytium,usb2";
+ reg = <0x00 0x31800000 0x00 0x80000 0x00 0x31990000 0x00 0x10000>;
+ interrupts = <0x00 0x20 0x04>;
+ status = "okay";
+ dr_mode = "host";
+ phandle = <0x5d>;
+ };
+
+ usb2@31880000 {
+ compatible = "phytium,usb2";
+ reg = <0x00 0x31880000 0x00 0x80000 0x00 0x319a0000 0x00 0x10000>;
+ interrupts = <0x00 0x21 0x04>;
+ status = "disabled";
+ dr_mode = "peripheral";
+ phandle = <0x5e>;
+ };
+
+ usb2@31900000 {
+ compatible = "phytium,usb2";
+ reg = <0x00 0x31900000 0x00 0x80000 0x00 0x319b0000 0x00 0x10000>;
+ interrupts = <0x00 0x22 0x04>;
+ status = "disabled";
+ dr_mode = "peripheral";
+ phandle = <0x5f>;
+ };
+
+ usb2@32800000 {
+ compatible = "phytium,usb2";
+ reg = <0x00 0x32800000 0x00 0x40000 0x00 0x32880000 0x00 0x40000>;
+ interrupts = <0x00 0x0e 0x04>;
+ status = "okay";
+ dr_mode = "host";
+ phandle = <0x60>;
+ };
+
+ usb2@32840000 {
+ compatible = "phytium,usb2";
+ reg = <0x00 0x32840000 0x00 0x40000 0x00 0x328c0000 0x00 0x40000>;
+ interrupts = <0x00 0x0f 0x04>;
+ status = "okay";
+ dr_mode = "host";
+ phandle = <0x61>;
+ };
+
+ dc@32000000 {
+ compatible = "phytium,dc";
+ reg = <0x00 0x32000000 0x00 0x8000>;
+ interrupts = <0x00 0x2c 0x04>;
+ status = "okay";
+ pipe_mask = [01];
+ edp_mask = [00];
+ phandle = <0x62>;
+ };
+
+ i2s_dp0@32009000 {
+ compatible = "phytium,i2s";
+ reg = <0x00 0x32009000 0x00 0x1000 0x00 0x32008000 0x00 0x1000>;
+ interrupts = <0x00 0x2f 0x04>;
+ clocks = <0x0e>;
+ clock-names = "i2s_clk";
+ dai-name = "phytium-i2s-dp0";
+ status = "okay";
+ phandle = <0x63>;
+ };
+
+ i2s_dp1@3200B000 {
+ compatible = "phytium,i2s";
+ reg = <0x00 0x3200b000 0x00 0x1000 0x00 0x3200a000 0x00 0x1000>;
+ interrupts = <0x00 0x30 0x04>;
+ clocks = <0x0e>;
+ clock-names = "i2s_clk";
+ dai-name = "phytium-i2s-dp1";
+ status = "disabled";
+ phandle = <0x64>;
+ };
+
+ pmdk_dp {
+ compatible = "phytium,pmdk-dp";
+ status = "okay";
+ num-dp = <0x01>;
+ dp-mask = [01];
+ phandle = <0x65>;
+ };
+
+ mailbox@32a00000 {
+ compatible = "phytium,mbox";
+ reg = <0x00 0x32a00000 0x00 0x1000>;
+ interrupts = <0x00 0x16 0x04>;
+ #mbox-cells = <0x01>;
+ phandle = <0x02>;
+ };
+
+ rng@32a36000 {
+ compatible = "phytium,rng";
+ reg = <0x00 0x32a36000 0x00 0x1000>;
+ status = "okay";
+ phandle = <0x66>;
+ };
+
+ sram@32a10000 {
+ compatible = "phytium,pe220x-sram-ns\0mmio-sram";
+ reg = <0x00 0x32a10000 0x00 0x2000>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x00 0x32a10000 0x2000>;
+ phandle = <0x67>;
+
+ scp-shmem@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x1000 0x400>;
+ phandle = <0x68>;
+ };
+
+ scp-shmem@1 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x1400 0x400>;
+ phandle = <0x03>;
+ };
+ };
+
+ gdma@32b34000 {
+ compatible = "phytium,gdma";
+ dma-channels = <0x10>;
+ max-outstanding = <0x10>;
+ reg = <0x00 0x32b34000 0x00 0x1000>;
+ interrupts = <0x00 0xea 0x04>;
+ #dma-cells = <0x01>;
+ phandle = <0x69>;
+ };
+
+ spinlock@32b36000 {
+ compatible = "phytium,hwspinlock";
+ reg = <0x00 0x32b36000 0x00 0x1000>;
+ #hwlock-cells = <0x01>;
+ nr-locks = <0x20>;
+ status = "disabled";
+ phandle = <0x6a>;
+ };
+
+ pcie@40000000 {
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ #address-cells = <0x03>;
+ #size-cells = <0x02>;
+ #interrupt-cells = <0x01>;
+ reg = <0x00 0x40000000 0x00 0x10000000>;
+ msi-parent = <0x0f>;
+ bus-range = <0x00 0xff>;
+ interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+ interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x04 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x00 0x00 0x05 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x00 0x00 0x06 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x00 0x00 0x07 0x04>;
+ ranges = <0x1000000 0x00 0x00 0x00 0x50000000 0x00 0xf00000 0x2000000 0x00 0x58000000 0x00 0x58000000 0x00 0x28000000 0x3000000 0x10 0x00 0x10 0x00 0x10 0x00>;
+ iommu-map = <0x00 0x10 0x00 0x10000>;
+ status = "okay";
+ phandle = <0x6b>;
+ };
+
+ edac@32b28000 {
+ compatible = "phytium,pe220x-edac";
+ reg = <0x00 0x32b28000 0x00 0x1000 0x00 0x31400000 0x00 0x1000 0x00 0x31401000 0x00 0x1000>;
+ interrupts = <0x00 0x00 0x04 0x00 0x01 0x04>;
+ status = "disabled";
+ phandle = <0x6c>;
+ };
+
+ hda@28006000 {
+ compatible = "phytium,hda";
+ reg = <0x00 0x28006000 0x00 0x1000>;
+ interrupts = <0x00 0x4e 0x04>;
+ status = "disabled";
+ phandle = <0x6d>;
+ };
+
+ i2s@28009000 {
+ compatible = "phytium,i2s";
+ reg = <0x00 0x28009000 0x00 0x1000 0x00 0x28005000 0x00 0x1000>;
+ interrupts = <0x00 0x4d 0x04>;
+ clocks = <0x0e>;
+ clock-names = "i2s_clk";
+ status = "okay";
+ #sound-dai-cells = <0x00>;
+ dai-name = "phytium-i2s-lsd";
+ phandle = <0x16>;
+ };
+
+ can@2800a000 {
+ compatible = "phytium,canfd";
+ reg = <0x00 0x2800a000 0x00 0x1000>;
+ interrupts = <0x00 0x51 0x04>;
+ clocks = <0x11>;
+ clock-names = "can_clk";
+ tx-fifo-depth = <0x40>;
+ rx-fifo-depth = <0x40>;
+ status = "okay";
+ phandle = <0x6e>;
+ };
+
+ can@2800b000 {
+ compatible = "phytium,canfd";
+ reg = <0x00 0x2800b000 0x00 0x1000>;
+ interrupts = <0x00 0x52 0x04>;
+ clocks = <0x11>;
+ clock-names = "can_clk";
+ tx-fifo-depth = <0x40>;
+ rx-fifo-depth = <0x40>;
+ status = "okay";
+ phandle = <0x6f>;
+ };
+
+ keypad@2807a000 {
+ compatible = "phytium,keypad";
+ reg = <0x00 0x2807a000 0x00 0x1000>;
+ interrupts = <0x00 0xbd 0x04>;
+ clocks = <0x0d>;
+ status = "disabled";
+ phandle = <0x70>;
+ };
+
+ usb3@31a08000 {
+ compatible = "phytium,pe220x-xhci";
+ reg = <0x00 0x31a08000 0x00 0x18000>;
+ interrupts = <0x00 0x10 0x04>;
+ status = "okay";
+ phandle = <0x71>;
+ };
+
+ usb3@31a28000 {
+ compatible = "phytium,pe220x-xhci";
+ reg = <0x00 0x31a28000 0x00 0x18000>;
+ interrupts = <0x00 0x11 0x04>;
+ status = "okay";
+ phandle = <0x72>;
+ };
+
+ sata@31a40000 {
+ compatible = "generic-ahci";
+ reg = <0x00 0x31a40000 0x00 0x1000>;
+ interrupts = <0x00 0x2a 0x04>;
+ status = "okay";
+ phandle = <0x73>;
+ };
+
+ sata@32014000 {
+ compatible = "generic-ahci";
+ reg = <0x00 0x32014000 0x00 0x1000>;
+ interrupts = <0x00 0x2b 0x04>;
+ status = "disabled";
+ phandle = <0x74>;
+ };
+
+ ethernet@3200c000 {
+ compatible = "cdns,phytium-gem-1.0";
+ reg = <0x00 0x3200c000 0x00 0x2000>;
+ interrupts = <0x00 0x37 0x04 0x00 0x38 0x04 0x00 0x39 0x04 0x00 0x3a 0x04 0x00 0x1c 0x04 0x00 0x1d 0x04 0x00 0x1e 0x04 0x00 0x1f 0x04>;
+ clock-names = "pclk\0hclk\0tx_clk\0tsu_clk";
+ clocks = <0x12 0x13 0x13 0x12>;
+ magic-packet;
+ support-tsn;
+ status = "okay";
+ phy-mode = "sgmii";
+ use-mii;
+ phandle = <0x75>;
+ };
+
+ ethernet@3200e000 {
+ compatible = "cdns,phytium-gem-1.0";
+ reg = <0x00 0x3200e000 0x00 0x2000>;
+ interrupts = <0x00 0x3b 0x04 0x00 0x3c 0x04 0x00 0x3d 0x04 0x00 0x3e 0x04>;
+ clock-names = "pclk\0hclk\0tx_clk\0tsu_clk";
+ clocks = <0x12 0x13 0x13 0x12>;
+ magic-packet;
+ status = "okay";
+ phy-mode = "sgmii";
+ use-mii;
+ phandle = <0x76>;
+ };
+
+ ethernet@32010000 {
+ compatible = "cdns,phytium-gem-1.0";
+ reg = <0x00 0x32010000 0x00 0x2000>;
+ interrupts = <0x00 0x40 0x04 0x00 0x41 0x04 0x00 0x42 0x04 0x00 0x43 0x04>;
+ clock-names = "pclk\0hclk\0tx_clk\0tsu_clk";
+ clocks = <0x12 0x13 0x13 0x12>;
+ magic-packet;
+ status = "disabled";
+ phandle = <0x77>;
+ };
+
+ ethernet@32012000 {
+ compatible = "cdns,phytium-gem-1.0";
+ reg = <0x00 0x32012000 0x00 0x2000>;
+ interrupts = <0x00 0x44 0x04 0x00 0x45 0x04 0x00 0x46 0x04 0x00 0x47 0x04>;
+ clock-names = "pclk\0hclk\0tx_clk\0tsu_clk";
+ clocks = <0x12 0x13 0x13 0x12>;
+ magic-packet;
+ status = "disabled";
+ phandle = <0x78>;
+ };
+
+ vpu@32b00000 {
+ compatible = "phytium,vpu";
+ reg = <0x00 0x32b00000 0x00 0x20000>;
+ interrupts = <0x00 0x0c 0x04>;
+ status = "okay";
+ phandle = <0x79>;
+ };
+
+ i2c@28026000 {
+ compatible = "phytium,i2c";
+ reg = <0x00 0x28026000 0x00 0x1000>;
+ interrupts = <0x00 0x65 0x04>;
+ clocks = <0x0d>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x7a>;
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+ };
+
+ i2c@28030000 {
+ compatible = "phytium,i2c";
+ reg = <0x00 0x28030000 0x00 0x1000>;
+ interrupts = <0x00 0x6a 0x04>;
+ clocks = <0x0d>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x7b>;
+
+ es8336@10 {
+ det-gpios = <0x14 0x0b 0x00>;
+ sel-gpios = <0x14 0x07 0x00>;
+ #sound-dai-cells = <0x00>;
+ compatible = "everest,es8336";
+ reg = <0x10>;
+ phandle = <0x17>;
+ };
+ };
+
+ uart@28014000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x28014000 0x00 0x1000>;
+ interrupts = <0x00 0x5c 0x04>;
+ clocks = <0x0d 0x0d>;
+ clock-names = "uartclk\0apb_pclk";
+ status = "okay";
+ phandle = <0x7c>;
+ };
+
+ i2c@28016000 {
+ compatible = "phytium,i2c";
+ reg = <0x00 0x28016000 0x00 0x1000>;
+ interrupts = <0x00 0x5d 0x04>;
+ clocks = <0x0d>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x7d>;
+ };
+
+ i2c@28024000 {
+ compatible = "phytium,i2c";
+ reg = <0x00 0x28024000 0x00 0x1000>;
+ interrupts = <0x00 0x64 0x04>;
+ clocks = <0x0d>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "okay";
+ phandle = <0x7e>;
+ };
+
+ uart@2802A000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x2802a000 0x00 0x1000>;
+ interrupts = <0x00 0x67 0x04>;
+ clocks = <0x0d 0x0d>;
+ clock-names = "uartclk\0apb_pclk";
+ status = "okay";
+ phandle = <0x7f>;
+ };
+
+ uart@28032000 {
+ compatible = "arm,pl011\0arm,primecell";
+ reg = <0x00 0x28032000 0x00 0x1000>;
+ interrupts = <0x00 0x6b 0x04>;
+ clocks = <0x0d 0x0d>;
+ clock-names = "uartclk\0apb_pclk";
+ status = "okay";
+ phandle = <0x80>;
+ };
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@00 {
+ device_type = "memory";
+ reg = <0x00 0x80000000 0x02 0x00>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ sysled {
+ label = "sysled";
+ gpios = <0x15 0x08 0x00>;
+ linux,default-trigger = "none";
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "phytium,pe220x-i2s-audio";
+ simple-audio-card,pin-switches = "mic-in";
+ simple-audio-card,widgets = "Microphone\0mic-in";
+ simple-audio-card,routing = "MIC2\0mic-in";
+ phandle = <0x81>;
+
+ simple-audio-card,cpu {
+ sound-dai = <0x16>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <0x17>;
+ };
+ };
+
+ __symbols__ {
+ scmi = "/firmware/scmi";
+ scmi_dvfs = "/firmware/scmi/protocol@13";
+ scmi_sensors0 = "/firmware/scmi/protocol@15";
+ cpu = "/cpus";
+ cpu_l0 = "/cpus/cpu@0";
+ cpu_l1 = "/cpus/cpu@1";
+ cpu_b0 = "/cpus/cpu@100";
+ cpu_b1 = "/cpus/cpu@101";
+ gic = "/interrupt-controller@30800000";
+ its = "/interrupt-controller@30800000/gic-its@30820000";
+ sysclk_48mhz = "/clocks/clk48mhz";
+ sysclk_50mhz = "/clocks/clk50mhz";
+ sysclk_100mhz = "/clocks/clk100mhz";
+ sysclk_200mhz = "/clocks/clk200mhz";
+ sysclk_250mhz = "/clocks/clk250mhz";
+ sysclk_300mhz = "/clocks/clk300mhz";
+ sysclk_600mhz = "/clocks/clk600mhz";
+ sysclk_1200mhz = "/clocks/clk1200mhz";
+ smmu = "/iommu@30000000";
+ soc = "/soc";
+ mmc0 = "/soc/mmc@28000000";
+ mmc1 = "/soc/mmc@28001000";
+ nand0 = "/soc/nand@28002000";
+ ddma0 = "/soc/ddma@28003000";
+ ddma1 = "/soc/ddma@28004000";
+ qspi0 = "/soc/spi@28008000";
+ uart0 = "/soc/uart@2800c000";
+ uart1 = "/soc/uart@2800d000";
+ uart2 = "/soc/uart@2800e000";
+ uart3 = "/soc/uart@2800f000";
+ lpc = "/soc/lpc@28010000";
+ kcs0 = "/soc/lpc@28010000/kcs@24";
+ kcs1 = "/soc/lpc@28010000/kcs@28";
+ kcs2 = "/soc/lpc@28010000/kcs@2c";
+ kcs3 = "/soc/lpc@28010000/kcs@8c";
+ bt = "/soc/lpc@28010000/bt@48";
+ gpio0 = "/soc/gpio@28034000";
+ gpio1 = "/soc/gpio@28035000";
+ gpio2 = "/soc/gpio@28036000";
+ gpio3 = "/soc/gpio@28037000";
+ gpio4 = "/soc/gpio@28038000";
+ gpio5 = "/soc/gpio@28039000";
+ spi0 = "/soc/spi@2803a000";
+ spi1 = "/soc/spi@2803b000";
+ spi2 = "/soc/spi@2803c000";
+ spi3 = "/soc/spi@2803d000";
+ watchdog0 = "/soc/watchdog@28040000";
+ watchdog1 = "/soc/watchdog@28042000";
+ pwm0 = "/soc/pwm@2804a000";
+ pwm1 = "/soc/pwm@2804b000";
+ tacho0 = "/soc/tacho@28054000";
+ tacho1 = "/soc/tacho@28055000";
+ tacho2 = "/soc/tacho@28056000";
+ tacho3 = "/soc/tacho@28057000";
+ tacho4 = "/soc/tacho@28058000";
+ tacho5 = "/soc/tacho@28059000";
+ tacho6 = "/soc/tacho@2805a000";
+ tacho7 = "/soc/tacho@2805b000";
+ tacho8 = "/soc/tacho@2805c000";
+ tacho9 = "/soc/tacho@2805d000";
+ tacho10 = "/soc/tacho@2805e000";
+ tacho11 = "/soc/tacho@2805f000";
+ tacho12 = "/soc/tacho@28060000";
+ tacho13 = "/soc/tacho@28061000";
+ tacho14 = "/soc/tacho@28062000";
+ tacho15 = "/soc/tacho@28063000";
+ tacho16 = "/soc/tacho@28064000";
+ tacho17 = "/soc/tacho@28065000";
+ tacho18 = "/soc/tacho@28066000";
+ tacho19 = "/soc/tacho@28067000";
+ tacho20 = "/soc/tacho@28068000";
+ tacho21 = "/soc/tacho@28069000";
+ tacho22 = "/soc/tacho@2806a000";
+ tacho23 = "/soc/tacho@2806b000";
+ tacho24 = "/soc/tacho@2806c000";
+ tacho25 = "/soc/tacho@2806d000";
+ tacho26 = "/soc/tacho@2806e000";
+ tacho27 = "/soc/tacho@2806f000";
+ tacho28 = "/soc/tacho@28070000";
+ tacho29 = "/soc/tacho@28071000";
+ tacho30 = "/soc/tacho@28072000";
+ tacho31 = "/soc/tacho@28073000";
+ tacho32 = "/soc/tacho@28074000";
+ tacho33 = "/soc/tacho@28075000";
+ tacho34 = "/soc/tacho@28076000";
+ tacho35 = "/soc/tacho@28077000";
+ tacho36 = "/soc/tacho@28078000";
+ tacho37 = "/soc/tacho@28079000";
+ usb2_0 = "/soc/usb2@31800000";
+ usb2_1 = "/soc/usb2@31880000";
+ usb2_2 = "/soc/usb2@31900000";
+ usb2_3 = "/soc/usb2@32800000";
+ usb2_4 = "/soc/usb2@32840000";
+ dc0 = "/soc/dc@32000000";
+ i2s_dp0 = "/soc/i2s_dp0@32009000";
+ i2s_dp1 = "/soc/i2s_dp1@3200B000";
+ pmdk_dp = "/soc/pmdk_dp";
+ mbox = "/soc/mailbox@32a00000";
+ rng0 = "/soc/rng@32a36000";
+ sram = "/soc/sram@32a10000";
+ cpu_scp_lpri = "/soc/sram@32a10000/scp-shmem@0";
+ cpu_scp_hpri = "/soc/sram@32a10000/scp-shmem@1";
+ gdma = "/soc/gdma@32b34000";
+ hwspinlock = "/soc/spinlock@32b36000";
+ pcie = "/soc/pcie@40000000";
+ edac = "/soc/edac@32b28000";
+ hda0 = "/soc/hda@28006000";
+ i2s0 = "/soc/i2s@28009000";
+ can0 = "/soc/can@2800a000";
+ can1 = "/soc/can@2800b000";
+ keypad = "/soc/keypad@2807a000";
+ usb3_0 = "/soc/usb3@31a08000";
+ usb3_1 = "/soc/usb3@31a28000";
+ sata0 = "/soc/sata@31a40000";
+ sata1 = "/soc/sata@32014000";
+ macb0 = "/soc/ethernet@3200c000";
+ macb1 = "/soc/ethernet@3200e000";
+ macb2 = "/soc/ethernet@32010000";
+ macb3 = "/soc/ethernet@32012000";
+ vpu0 = "/soc/vpu@32b00000";
+ mio9 = "/soc/i2c@28026000";
+ mio14 = "/soc/i2c@28030000";
+ codec0 = "/soc/i2c@28030000/es8336@10";
+ mio0 = "/soc/uart@28014000";
+ mio1 = "/soc/i2c@28016000";
+ mio8 = "/soc/i2c@28024000";
+ mio11 = "/soc/uart@2802A000";
+ mio15 = "/soc/uart@28032000";
+ sound_card = "/sound";
+ };
+};
diff --git a/platform/aarch64/phytium-pi/linker.ld b/platform/aarch64/phytium-pi/linker.ld
new file mode 100644
index 00000000..80e9014e
--- /dev/null
+++ b/platform/aarch64/phytium-pi/linker.ld
@@ -0,0 +1,49 @@
+ENTRY(arch_entry)
+BASE_ADDRESS = 0x90100000;
+
+SECTIONS
+{
+ . = BASE_ADDRESS;
+ skernel = .;
+
+ stext = .;
+ .text : {
+ *(.text.entry)
+ *(.text .text.*)
+ }
+
+ . = ALIGN(4K);
+ etext = .;
+ srodata = .;
+ .rodata : {
+ *(.rodata .rodata.*)
+ *(.srodata .srodata.*)
+ }
+
+ . = ALIGN(4K);
+ erodata = .;
+ sdata = .;
+ .data : {
+ *(.data .data.*)
+ *(.sdata .sdata.*)
+ }
+
+ . = ALIGN(4K);
+ edata = .;
+ .bss : {
+ *(.bss.stack)
+ sbss = .;
+ *(.bss .bss.*)
+ *(.sbss .sbss.*)
+ }
+
+ . = ALIGN(4K);
+ ebss = .;
+ ekernel = .;
+
+ /DISCARD/ : {
+ *(.eh_frame)
+ }
+ . = ALIGN(4K);
+ __core_end = .;
+}
\ No newline at end of file
diff --git a/platform/aarch64/phytium-pi/platform.mk b/platform/aarch64/phytium-pi/platform.mk
new file mode 100644
index 00000000..061516bc
--- /dev/null
+++ b/platform/aarch64/phytium-pi/platform.mk
@@ -0,0 +1,53 @@
+QEMU := qemu-system-aarch64
+
+ifeq ($(findstring gicv3, $(FEATURES)),gicv3)
+ UBOOT := $(image_dir)/bootloader/u-boot-atf.bin
+ zone0_dtb := $(image_dir)/devicetree/linux1.dtb
+ QEMU_ARGS := -machine virt,secure=on,gic-version=3,virtualization=on,iommu=smmuv3
+ MESSAGE := "Note: Feature contains gicv3"
+else
+ UBOOT := $(image_dir)/bootloader/u-boot-v2.bin
+ zone0_dtb := $(image_dir)/devicetree/linux1-v2.dtb
+ QEMU_ARGS := -machine virt,secure=on,gic-version=2,virtualization=on,iommu=smmuv3
+ MESSAGE := "Note: Feature contains gicv2"
+endif
+
+FSIMG1 := $(image_dir)/virtdisk/rootfs1.ext4
+FSIMG2 := $(image_dir)/virtdisk/rootfs2.ext4
+
+zone0_kernel := $(image_dir)/kernel/Image
+
+QEMU_ARGS += -global arm-smmuv3.stage=2
+
+QEMU_ARGS += -cpu cortex-a72
+QEMU_ARGS += -smp 4
+QEMU_ARGS += -m 2G
+QEMU_ARGS += -nographic
+QEMU_ARGS += -bios $(UBOOT)
+
+QEMU_ARGS += -device loader,file="$(hvisor_bin)",addr=0x90100000,force-raw=on
+QEMU_ARGS += -device loader,file="$(zone0_kernel)",addr=0xa0400000,force-raw=on
+QEMU_ARGS += -device loader,file="$(zone0_dtb)",addr=0xa0000000,force-raw=on
+
+QEMU_ARGS += -drive if=none,file=$(FSIMG1),id=Xa003e000,format=raw
+QEMU_ARGS += -device virtio-blk-device,drive=Xa003e000,bus=virtio-mmio-bus.31
+
+$(hvisor_bin): elf
+ @if ! command -v mkimage > /dev/null; then \
+ sudo apt update && sudo apt install u-boot-tools; \
+ fi && \
+ $(OBJCOPY) $(hvisor_elf) --strip-all -O binary $(hvisor_bin).tmp && \
+ mkimage -n hvisor_img -A arm64 -O linux -C none -T kernel -a 0x90100000 \
+ -e 0x90100000 -d $(hvisor_bin).tmp $(hvisor_bin) && \
+ rm -rf $(hvisor_bin).tmp
+
+QEMU_ARGS += -netdev type=user,id=net1
+QEMU_ARGS += -device virtio-net-pci,netdev=net1,disable-legacy=on,disable-modern=off,iommu_platform=on
+
+# QEMU_ARGS += -device pci-testdev
+
+QEMU_ARGS += -netdev type=user,id=net2
+QEMU_ARGS += -device virtio-net-pci,netdev=net2,disable-legacy=on,disable-modern=off,iommu_platform=on
+
+QEMU_ARGS += -netdev type=user,id=net3
+QEMU_ARGS += -device virtio-net-pci,netdev=net3,disable-legacy=on,disable-modern=off,iommu_platform=on
\ No newline at end of file
diff --git a/platform/aarch64/qemu-gicv2/board.rs b/platform/aarch64/qemu-gicv2/board.rs
index c9d6f8f8..98cae2b2 100644
--- a/platform/aarch64/qemu-gicv2/board.rs
+++ b/platform/aarch64/qemu-gicv2/board.rs
@@ -13,11 +13,34 @@
//
// Authors:
//
-use crate::{arch::zone::HvArchZoneConfig, config::*};
+use crate::{
+ arch::{mmu::MemoryType, zone::{HvArchZoneConfig,GicConfig,Gicv2Config}},
+ config::*,
+};
pub const BOARD_NAME: &str = "qemu-gicv2";
pub const BOARD_NCPUS: usize = 4;
+pub const BOARD_UART_BASE: u64 = 0x9000000;
+
+#[rustfmt::skip]
+pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [
+ 0x0, // cpu0
+ 0x1, // cpu1
+ 0x2, // cpu2
+ 0x3, // cpu3
+];
+
+/// The physical memory layout of the board.
+/// Each address should align to 2M (0x200000).
+/// Addresses must be in ascending order.
+#[rustfmt::skip]
+pub const BOARD_PHYSMEM_LIST: &[(u64, u64, MemoryType)] = &[
+ // ( start, end, type)
+ ( 0x0, 0x10000000, MemoryType::Device),
+ ( 0x40000000, 0x100000000, MemoryType::Normal),
+ (0x4010000000, 0x4020000000, MemoryType::Device),
+];
pub const ROOT_ZONE_DTB_ADDR: u64 = 0xa0000000;
pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0xa0400000;
@@ -52,21 +75,21 @@ pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 3] = [
pub const ROOT_ZONE_IRQS: [u32; 9] = [33, 64, 77, 79, 35, 36, 37, 38, 65];
pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig {
- gicd_base: 0x8000000,
- gicd_size: 0x10000,
- gicr_base: 0x80a0000,
- gicr_size: 0xf60000,
- gicc_base: 0x8010000,
- gicc_size: 0x10000,
- gicc_offset: 0x0,
- gich_base: 0x8030000,
- gich_size: 0x10000,
- gicv_base: 0x8040000,
- gicv_size: 0x10000,
- gits_base: 0x8080000,
- gits_size: 0x20000,
+ is_aarch32: 0,
+ gic_config: GicConfig::Gicv2(Gicv2Config {
+ gicd_base: 0x8000000,
+ gicd_size: 0x10000,
+ gicc_base: 0x8010000,
+ gicc_size: 0x10000,
+ gicc_offset: 0x0,
+ gich_base: 0x8030000,
+ gich_size: 0x10000,
+ gicv_base: 0x8040000,
+ gicv_size: 0x10000,
+ }),
};
+
pub const ROOT_PCI_CONFIG: HvPciConfig = HvPciConfig {
ecam_base: 0x4010000000,
ecam_size: 0x10000000,
diff --git a/platform/aarch64/qemu-gicv2/cargo/features b/platform/aarch64/qemu-gicv2/cargo/features
index bd682521..a5c58808 100644
--- a/platform/aarch64/qemu-gicv2/cargo/features
+++ b/platform/aarch64/qemu-gicv2/cargo/features
@@ -2,4 +2,3 @@ gicv2
pl011
iommu
pci
-pt_layout_qemu
\ No newline at end of file
diff --git a/platform/aarch64/qemu-gicv2/configs/zone1-linux-virtio.json b/platform/aarch64/qemu-gicv2/configs/zone1-linux-virtio.json
new file mode 100644
index 00000000..2e659ee3
--- /dev/null
+++ b/platform/aarch64/qemu-gicv2/configs/zone1-linux-virtio.json
@@ -0,0 +1,31 @@
+{
+ "zones": [
+ {
+ "id": 1,
+ "memory_region": [
+ {
+ "zone0_ipa": "0x50000000",
+ "zonex_ipa": "0x50000000",
+ "size": "0x30000000"
+ }
+ ],
+ "devices": [
+ {
+ "type": "console",
+ "addr": "0xa003a00",
+ "len": "0x200",
+ "irq": 76,
+ "status": "enable"
+ },
+ {
+ "type": "blk",
+ "addr": "0xa003e00",
+ "len": "0x200",
+ "irq": 78,
+ "img": "zone1-linux-rootfs.ext4",
+ "status": "enable"
+ }
+ ]
+ }
+ ]
+}
\ No newline at end of file
diff --git a/platform/aarch64/qemu-gicv2/configs/zone1-linux.json b/platform/aarch64/qemu-gicv2/configs/zone1-linux.json
new file mode 100644
index 00000000..f2b3ca64
--- /dev/null
+++ b/platform/aarch64/qemu-gicv2/configs/zone1-linux.json
@@ -0,0 +1,52 @@
+{
+ "arch": "arm64",
+ "name": "zone1-linux",
+ "zone_id": 1,
+ "cpus": [
+ 2,
+ 3
+ ],
+ "memory_regions": [
+ {
+ "type": "ram",
+ "physical_start": "0x50000000",
+ "virtual_start": "0x50000000",
+ "size": "0x30000000"
+ },
+ {
+ "type": "virtio",
+ "physical_start": "0xa003a00",
+ "virtual_start": "0xa003a00",
+ "size": "0x200"
+ },
+ {
+ "type": "virtio",
+ "physical_start": "0xa003e00",
+ "virtual_start": "0xa003e00",
+ "size": "0x200"
+ }
+ ],
+ "interrupts": [
+ 76,
+ 78
+ ],
+ "ivc_configs": [],
+ "kernel_filepath": "zone1-linux-kernel",
+ "kernel_args": "",
+ "dtb_filepath": "zone1-linux.dtb",
+ "kernel_load_paddr": "0x50400000",
+ "dtb_load_paddr": "0x50000000",
+ "entry_point": "0x50400000",
+ "arch_config": {
+ "gic_version": "v2",
+ "gicd_base": "0x8000000",
+ "gicd_size": "0x10000",
+ "gicc_base": "0x8010000",
+ "gicc_size": "0x10000",
+ "gicc_offset": "0x0",
+ "gich_base": "0x8030000",
+ "gich_size": "0x10000",
+ "gicv_base": "0x8040000",
+ "gicv_size": "0x10000"
+ }
+}
\ No newline at end of file
diff --git a/platform/aarch64/qemu-gicv2/image/dts/zone0.dts b/platform/aarch64/qemu-gicv2/image/dts/zone0.dts
index f6cc5a69..c17e8e7f 100644
--- a/platform/aarch64/qemu-gicv2/image/dts/zone0.dts
+++ b/platform/aarch64/qemu-gicv2/image/dts/zone0.dts
@@ -35,7 +35,18 @@
memory@50000000 {
device_type = "memory";
- reg = <0x00 0x50000000 0x00 0x80000000>;
+ reg = <0x00 0x50000000 0x00 0x70000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ nonroot@50000000 {
+ no-map;
+ reg = <0x00 0x50000000 0x00 0x30000000>;
+ };
};
intc@8000000 {
@@ -91,7 +102,13 @@
};
chosen {
- bootargs = "earlycon console=ttyAMA0 root=/dev/vda mem=768M rw";
+ bootargs = "clk_ignore_unused earlycon console=ttyAMA0 root=/dev/vda iomem=relaxed rw";
stdout-path = "/pl011@9000000";
};
-};
\ No newline at end of file
+
+ hvisor_virtio_device {
+ compatible = "hvisor";
+ interrupt-parent = <0x01>;
+ interrupts = <0x00 0x20 0x01>;
+ };
+};
diff --git a/platform/aarch64/qemu-gicv2/image/dts/zone1-linux.dts b/platform/aarch64/qemu-gicv2/image/dts/zone1-linux.dts
new file mode 100644
index 00000000..9aed7f51
--- /dev/null
+++ b/platform/aarch64/qemu-gicv2/image/dts/zone1-linux.dts
@@ -0,0 +1,84 @@
+/dts-v1/;
+
+/ {
+ #size-cells = <0x02>;
+ #address-cells = <0x02>;
+ interrupt-parent = <0x01>;
+ model = "linux,dummy-virt";
+ compatible = "linux,dummy-virt";
+
+ cpus {
+ #size-cells = <0x00>;
+ #address-cells = <0x01>;
+
+ cpu@2 {
+ reg = <0x02>;
+ enable-method = "psci";
+ compatible = "arm,cortex-a72";
+ device_type = "cpu";
+ };
+
+ cpu@3 {
+ reg = <0x03>;
+ enable-method = "psci";
+ compatible = "arm,cortex-a72";
+ device_type = "cpu";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ memory@50000000 {
+ device_type = "memory";
+ reg = <0x0 0x50000000 0x0 0x30000000>;
+ };
+
+ gic@8000000 {
+ phandle = <0x01>;
+ reg = <0x00 0x8000000 0x00 0x10000 0x00 0x8010000 0x00 0x10000 0x00 0x8030000 0x00 0x10000 0x00 0x8040000 0x00 0x10000>;
+ compatible = "arm,cortex-a15-gic";
+ interrupt-controller;
+ #interrupt-cells = <0x03>;
+ };
+
+ apb-pclk {
+ phandle = <0x8000>;
+ clock-output-names = "clk24mhz";
+ clock-frequency = <0x16e3600>;
+ #clock-cells = <0x00>;
+ compatible = "fixed-clock";
+ };
+
+ timer {
+ interrupt-parent = <0x01>;
+ interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>;
+ always-on;
+ compatible = "arm,armv8-timer", "arm,armv7-timer";
+ };
+
+ // virtio serial
+ virtio_mmio@a003a00 {
+ dma-coherent;
+ interrupt-parent = <0x01>;
+ interrupts = <0x00 0x2d 0x01>;
+ reg = <0x00 0xa003a00 0x00 0x200>;
+ compatible = "virtio,mmio";
+ };
+
+ // virtio-blk
+ virtio_mmio@a003e00 {
+ dma-coherent;
+ interrupt-parent = <0x01>;
+ interrupts = <0x00 0x2f 0x01>;
+ reg = <0x00 0xa003e00 0x00 0x200>;
+ compatible = "virtio,mmio";
+ };
+
+ chosen {
+ bootargs = "earlycon console=hvc0 root=/dev/vda rw";
+ stdout-path = "/virtio_mmio@a003a00";
+ };
+};
diff --git a/platform/aarch64/qemu-gicv3/board.rs b/platform/aarch64/qemu-gicv3/board.rs
index 9ff4be52..124b9dca 100644
--- a/platform/aarch64/qemu-gicv3/board.rs
+++ b/platform/aarch64/qemu-gicv3/board.rs
@@ -13,11 +13,36 @@
//
// Authors:
//
-use crate::{arch::zone::HvArchZoneConfig, config::*};
-
+use crate::{
+ arch::{
+ mmu::MemoryType,
+ zone::{GicConfig, Gicv3Config, HvArchZoneConfig},
+ },
+ config::*,
+};
pub const BOARD_NAME: &str = "qemu-gicv3";
pub const BOARD_NCPUS: usize = 4;
+pub const BOARD_UART_BASE: u64 = 0x9000000;
+
+#[rustfmt::skip]
+pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [
+ 0x0, // cpu0
+ 0x1, // cpu1
+ 0x2, // cpu2
+ 0x3, // cpu3
+];
+
+/// The physical memory layout of the board.
+/// Each address should align to 2M (0x200000).
+/// Addresses must be in ascending order.
+#[rustfmt::skip]
+pub const BOARD_PHYSMEM_LIST: &[(u64, u64, MemoryType)] = &[
+ // ( start, end, type)
+ ( 0x0, 0x10000000, MemoryType::Device),
+ ( 0x40000000, 0x100000000, MemoryType::Normal),
+ (0x4010000000, 0x4020000000, MemoryType::Device),
+];
pub const ROOT_ZONE_DTB_ADDR: u64 = 0xa0000000;
pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0xa0400000;
@@ -52,19 +77,15 @@ pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 3] = [
pub const ROOT_ZONE_IRQS: [u32; 9] = [33, 64, 77, 79, 35, 36, 37, 38, 65];
pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig {
- gicd_base: 0x8000000,
- gicd_size: 0x10000,
- gicr_base: 0x80a0000,
- gicr_size: 0xf60000,
- gicc_base: 0x8010000,
- gicc_size: 0x10000,
- gicc_offset: 0x0,
- gich_base: 0x8030000,
- gich_size: 0x10000,
- gicv_base: 0x8040000,
- gicv_size: 0x10000,
- gits_base: 0x8080000,
- gits_size: 0x20000,
+ is_aarch32: 0,
+ gic_config: GicConfig::Gicv3(Gicv3Config {
+ gicd_base: 0x8000000,
+ gicd_size: 0x10000,
+ gicr_base: 0x80a0000,
+ gicr_size: 0xf60000,
+ gits_base: 0x8080000,
+ gits_size: 0x20000,
+ }),
};
pub const ROOT_PCI_CONFIG: HvPciConfig = HvPciConfig {
diff --git a/platform/aarch64/qemu-gicv3/cargo/features b/platform/aarch64/qemu-gicv3/cargo/features
index 942d603a..eb18579e 100644
--- a/platform/aarch64/qemu-gicv3/cargo/features
+++ b/platform/aarch64/qemu-gicv3/cargo/features
@@ -2,4 +2,3 @@ gicv3
pl011
iommu
pci
-pt_layout_qemu
\ No newline at end of file
diff --git a/platform/aarch64/qemu-gicv3/image/dts/zone0.dts b/platform/aarch64/qemu-gicv3/image/dts/zone0.dts
index 3b6d88fb..1c9d79cb 100644
--- a/platform/aarch64/qemu-gicv3/image/dts/zone0.dts
+++ b/platform/aarch64/qemu-gicv3/image/dts/zone0.dts
@@ -50,7 +50,7 @@
reg = <0x0 0x50000000 0x0 0x70000000>;
};
- intc@80000000 {
+ intc@8000000 {
phandle = <0x01>;
interrupts = <0x01 0x09 0x04>;
reg = <0x00 0x8000000 0x00 0x10000 0x00 0x80a0000 0x00 0xf60000>;
@@ -330,7 +330,7 @@
virtio_mmio@a003c00 {
dma-coherent;
- interrupt-parent = <0x01>;
+ interrupt-parent = <0x01>;
interrupts = <0x0 0x2e 0x1>;
reg = <0x0 0xa003c00 0x0 0x200>;
compatible = "virtio,mmio";
@@ -347,7 +347,6 @@
chosen {
bootargs = "clk_ignore_unused earlycon console=ttyAMA0 root=/dev/vda iomem=relaxed rw";
- // bootargs = "root=/dev/vda mem=768M";
stdout-path = "/pl011@9000000";
};
diff --git a/platform/aarch64/qemu-gicv3/image/dts/zone1-linux.dts b/platform/aarch64/qemu-gicv3/image/dts/zone1-linux.dts
index 8c8b0e06..e2d4a8af 100644
--- a/platform/aarch64/qemu-gicv3/image/dts/zone1-linux.dts
+++ b/platform/aarch64/qemu-gicv3/image/dts/zone1-linux.dts
@@ -37,7 +37,7 @@
reg = <0x0 0x50000000 0x0 0x30000000>;
};
- gic@80000000 {
+ gic@8000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <0x03>;
interrupt-controller;
@@ -126,8 +126,6 @@
chosen {
bootargs = "earlycon console=hvc0 root=/dev/vda rw";
- // bootargs = "root=/dev/vda mem=768M";
stdout-path = "/virtio_mmio@a003800";
};
-
};
diff --git a/platform/aarch64/qemu-gicv3/image/dts/zone1-ruxos.dts b/platform/aarch64/qemu-gicv3/image/dts/zone1-ruxos.dts
index 91c39503..05c008c2 100644
--- a/platform/aarch64/qemu-gicv3/image/dts/zone1-ruxos.dts
+++ b/platform/aarch64/qemu-gicv3/image/dts/zone1-ruxos.dts
@@ -68,7 +68,7 @@
interrupt-affinity = <0x03 0x04>;
};
- gic@80000000 {
+ gic@8000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <0x03>;
interrupt-controller;
diff --git a/platform/aarch64/rk3568/board.rs b/platform/aarch64/rk3568/board.rs
index 12845b62..84f07a71 100644
--- a/platform/aarch64/rk3568/board.rs
+++ b/platform/aarch64/rk3568/board.rs
@@ -14,11 +14,36 @@
// Authors:
//
-use crate::{arch::zone::HvArchZoneConfig, config::*};
+use crate::{
+ arch::{
+ mmu::MemoryType,
+ zone::{GicConfig, Gicv3Config, HvArchZoneConfig},
+ },
+ config::*,
+};
pub const BOARD_NAME: &str = "rk3568";
pub const BOARD_NCPUS: usize = 4;
+pub const BOARD_UART_BASE: u64 = 0xfe660000;
+
+#[rustfmt::skip]
+pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [
+ 0x0, // cpu0
+ 0x100, // cpu1
+ 0x200, // cpu2
+ 0x300, // cpu3
+];
+
+/// The physical memory layout of the board.
+/// Each address should align to 2M (0x200000).
+/// Addresses must be in ascending order.
+#[rustfmt::skip]
+pub const BOARD_PHYSMEM_LIST: &[(u64, u64, MemoryType)] = &[
+ // ( start, end, type)
+ ( 0x0, 0xf0000000, MemoryType::Normal),
+ ( 0xf0000000, 0x100000000, MemoryType::Device),
+];
pub const ROOT_ZONE_DTB_ADDR: u64 = 0xa0000000;
pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x60080000 ;
@@ -166,20 +191,17 @@ pub const ROOT_ZONE_IRQS: [u32; 20] = [
0x84, 0x98, 0x40, 0x104, 0x105, 0x106, 0x107, 0x2d, 0x2e, 0x2b, 0x2a, 0x29, 0x33, 0x96, 0x11c, 0x44, 0x43, 0x42, 0x41, 0x8d];
pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig {
- gicd_base: 0xfd400000,
- gicd_size: 0x10000,
- gicr_base: 0xfd460000,
- gicr_size: 0xc0000,
- gicc_base: 0,
- gicc_size: 0,
- gicc_offset: 0x0,
- gich_base: 0,
- gich_size: 0,
- gicv_base: 0,
- gicv_size: 0,
- gits_base: 0,
- gits_size: 0,
+ is_aarch32: 0,
+ gic_config: GicConfig::Gicv3(Gicv3Config {
+ gicd_base: 0xfd400000,
+ gicd_size: 0x10000,
+ gicr_base: 0xfd460000,
+ gicr_size: 0xc0000,
+ gits_base: 0,
+ gits_size: 0,
+ }),
};
+
pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = [];
pub const ROOT_PCI_DEVS: [u64; 0] = [];
diff --git a/platform/aarch64/rk3568/cargo/features b/platform/aarch64/rk3568/cargo/features
index ca7d4a3d..afa59489 100644
--- a/platform/aarch64/rk3568/cargo/features
+++ b/platform/aarch64/rk3568/cargo/features
@@ -1,5 +1,2 @@
gicv3
uart_16550
-uart_base_rk3568
-pt_layout_rk3568
-mpidr_rockchip
\ No newline at end of file
diff --git a/platform/aarch64/rk3588/board.rs b/platform/aarch64/rk3588/board.rs
index 95680030..b12c6ec1 100644
--- a/platform/aarch64/rk3588/board.rs
+++ b/platform/aarch64/rk3588/board.rs
@@ -13,7 +13,13 @@
//
// Authors:
//
-use crate::{arch::zone::HvArchZoneConfig, config::*};
+use crate::{
+ arch::{
+ mmu::MemoryType,
+ zone::{GicConfig, Gicv3Config, HvArchZoneConfig},
+ },
+ config::*,
+};
// [ 17.796762] node 0: [mem 0x0000000000200000-0x000000000047ffff]
// [ 17.797335] node 0: [mem 0x0000000000480000-0x000000000087ffff]
@@ -26,6 +32,30 @@ use crate::{arch::zone::HvArchZoneConfig, config::*};
pub const BOARD_NAME: &str = "rk3588";
pub const BOARD_NCPUS: usize = 8;
+pub const BOARD_UART_BASE: u64 = 0xfeb50000;
+
+#[rustfmt::skip]
+pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [
+ 0x0, // cpu0
+ 0x100, // cpu1
+ 0x200, // cpu2
+ 0x300, // cpu3
+ 0x400, // cpu4
+ 0x500, // cpu5
+ 0x600, // cpu6
+ 0x700, // cpu7
+];
+
+/// The physical memory layout of the board.
+/// Each address should align to 2M (0x200000).
+/// Addresses must be in ascending order.
+#[rustfmt::skip]
+pub const BOARD_PHYSMEM_LIST: &[(u64, u64, MemoryType)] = &[
+ // ( start, end, type)
+ ( 0x0, 0xf0000000, MemoryType::Normal),
+ ( 0xf0000000, 0x100000000, MemoryType::Device),
+ ( 0x100000000, 0x3fc000000, MemoryType::Normal)
+];
pub const ROOT_ZONE_DTB_ADDR: u64 = 0x10000000;
pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x09400000;
@@ -146,19 +176,15 @@ pub const ROOT_ZONE_IRQS: [u32; 29] = [
];
pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig {
- gicd_base: 0xfe600000,
- gicd_size: 0x10000,
- gicr_base: 0xfe680000,
- gicr_size: 0x100000,
- gicc_base: 0x8010000,
- gicc_size: 0x10000,
- gicc_offset: 0x0,
- gich_base: 0x8030000,
- gich_size: 0x10000,
- gicv_base: 0x8040000,
- gicv_size: 0x10000,
- gits_base: 0x8080000,
- gits_size: 0x20000,
+ is_aarch32: 0,
+ gic_config: GicConfig::Gicv3(Gicv3Config {
+ gicd_base: 0xfe600000,
+ gicd_size: 0x10000,
+ gicr_base: 0xfe680000,
+ gicr_size: 0x100000,
+ gits_base: 0x8080000,
+ gits_size: 0x20000,
+ }),
};
pub const ROOT_PCI_CONFIG: HvPciConfig = HvPciConfig {
diff --git a/platform/aarch64/rk3588/cargo/features b/platform/aarch64/rk3588/cargo/features
index 79646680..afa59489 100644
--- a/platform/aarch64/rk3588/cargo/features
+++ b/platform/aarch64/rk3588/cargo/features
@@ -1,5 +1,2 @@
gicv3
uart_16550
-uart_base_rk3588
-pt_layout_rk3588
-mpidr_rockchip
\ No newline at end of file
diff --git a/platform/aarch64/zcu102/board.rs b/platform/aarch64/zcu102/board.rs
index 54049234..b3527283 100644
--- a/platform/aarch64/zcu102/board.rs
+++ b/platform/aarch64/zcu102/board.rs
@@ -12,13 +12,35 @@
// https://www.syswonder.org
//
// Authors:
-//
+// ForeverYolo <2572131118@qq.com>
use crate::config::HvConfigMemoryRegion;
-use crate::{arch::zone::HvArchZoneConfig, config::*};
+use crate::{
+ arch::{mmu::MemoryType, zone::{GicConfig, Gicv2Config, HvArchZoneConfig},},
+ config::*,
+};
pub const BOARD_NAME: &str = "zcu102";
pub const BOARD_NCPUS: usize = 4;
+pub const BOARD_UART_BASE: u64 = 0xff000000;
+
+#[rustfmt::skip]
+pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [
+ 0x0, // cpu0
+ 0x1, // cpu1
+ 0x2, // cpu2
+ 0x3, // cpu3
+];
+
+/// The physical memory layout of the board.
+/// Each address should align to 2M (0x200000).
+/// Addresses must be in ascending order.
+#[rustfmt::skip]
+pub const BOARD_PHYSMEM_LIST: &[(u64, u64, MemoryType)] = &[
+ // ( start, end, type)
+ ( 0x0, 0xf0000000, MemoryType::Normal),
+ ( 0xf0000000, 0x100000000, MemoryType::Device),
+];
pub const ROOT_ZONE_DTB_ADDR: u64 = 0x04000000;
pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x00200000;
@@ -27,7 +49,7 @@ pub const ROOT_ZONE_CPUS: u64 = (1 << 0) | (1 << 1);
pub const ROOT_ZONE_NAME: &str = "root-linux";
-pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 5] = [
+pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 9] = [
// HvConfigMemoryRegion {
// mem_type: MEM_TYPE_RAM,
// physical_start: 0x800000000,
@@ -64,24 +86,48 @@ pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 5] = [
virtual_start: 0xff170000,
size: 0x1000,
}, // mmc0
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0xff0e0000,
+ virtual_start: 0xff0e0000,
+ size: 0x1000,
+ }, // ethernet
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0xff020000,
+ virtual_start: 0xff020000,
+ size: 0x1000,
+ }, // i2c
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0xff030000,
+ virtual_start: 0xff030000,
+ size: 0x1000,
+ }, // i2c
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0xff0a0000,
+ virtual_start: 0xff0a0000,
+ size: 0x1000,
+ }, // gpio
];
-pub const ROOT_ZONE_IRQS: [u32; 8] = [53, 81, 67, 175, 176, 177, 178, 64];
+pub const ROOT_ZONE_IRQS: [u32; 11] = [53, 81, 175, 176, 177, 178, 64, 50, 48, 49, 95];
+// serial-mmc-pmu-pmu-pmu-pmu-(hvisor_virtio_device)-gpio-i2c(ff030000)-i2c(ff020000)-ethernet
pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig {
- gicd_base: 0xf9010000,
- gicd_size: 0x10000,
- gicr_base: 0x80a0000,
- gicr_size: 0xf60000,
- gits_base: 0x20000,
- gits_size: 0x20000,
- gicc_base: 0xf9020000,
- gicc_size: 0x20000,
- gicc_offset: 0xf000,
- gich_base: 0xf9040000,
- gich_size: 0x20000,
- gicv_base: 0xf9060000,
- gicv_size: 0x20000,
+ is_aarch32: 0,
+ gic_config: GicConfig::Gicv2(Gicv2Config {
+ gicd_base: 0xf9010000,
+ gicd_size: 0x10000,
+ gicc_base: 0xf9020000,
+ gicc_size: 0x20000,
+ gicc_offset: 0xf000,
+ gich_base: 0xf9040000,
+ gich_size: 0x20000,
+ gicv_base: 0xf9060000,
+ gicv_size: 0x20000,
+ }),
};
pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = [];
diff --git a/platform/aarch64/zcu102/cargo/features b/platform/aarch64/zcu102/cargo/features
index a80ec9cb..4189d149 100644
--- a/platform/aarch64/zcu102/cargo/features
+++ b/platform/aarch64/zcu102/cargo/features
@@ -1,3 +1,2 @@
gicv2
xuartps
-pt_layout_zcu102
\ No newline at end of file
diff --git a/platform/aarch64/zcu102/image/dts/zone0.dts b/platform/aarch64/zcu102/image/dts/zone0.dts
index acb890cc..cb0df1bd 100644
--- a/platform/aarch64/zcu102/image/dts/zone0.dts
+++ b/platform/aarch64/zcu102/image/dts/zone0.dts
@@ -33,28 +33,6 @@
phandle = <0x07>;
};
- cpu@2 {
- compatible = "arm,cortex-a53";
- device_type = "cpu";
- enable-method = "psci";
- reg = <0x02>;
- operating-points-v2 = <0x01>;
- cpu-idle-states = <0x02>;
- next-level-cache = <0x03>;
- phandle = <0x08>;
- };
-
- cpu@3 {
- compatible = "arm,cortex-a53";
- device_type = "cpu";
- enable-method = "psci";
- reg = <0x03>;
- operating-points-v2 = <0x01>;
- cpu-idle-states = <0x02>;
- next-level-cache = <0x03>;
- phandle = <0x09>;
- };
-
l2-cache {
compatible = "cache";
cache-level = <0x02>;
@@ -76,27 +54,6 @@
};
};
- zynqmp-ipi {
- bootph-all;
- compatible = "xlnx,zynqmp-ipi-mailbox";
- interrupt-parent = <0x05>;
- interrupts = <0x00 0x23 0x04>;
- xlnx,ipi-id = <0x00>;
- #address-cells = <0x02>;
- #size-cells = <0x02>;
- ranges;
- phandle = <0x40>;
-
- mailbox@ff9905c0 {
- bootph-all;
- reg = <0x00 0xff9905c0 0x00 0x20 0x00 0xff9905e0 0x00 0x20 0x00 0xff990e80 0x00 0x20 0x00 0xff990ea0 0x00 0x20>;
- reg-names = "local_request_region\0local_response_region\0remote_request_region\0remote_response_region";
- #mbox-cells = <0x01>;
- xlnx,ipi-id = <0x04>;
- phandle = <0x0a>;
- };
- };
-
pmu {
compatible = "arm,armv8-pmuv3";
interrupt-parent = <0x05>;
@@ -111,10 +68,18 @@
memory@0 {
device_type = "memory";
- // reg = <0x00 0x00 0x00 0x7ff00000 0x08 0x00 0x00 0x80000000>;
- reg = <0x00 0x00 0x00 0x40000000>;
+ reg = <0x00 0x00 0x00 0x40000000 0x00 0x50000000 0x00 0x25000000>;
};
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ nonroot@50000000 {
+ no-map;
+ reg = <0x00 0x50000000 0x00 0x25000000>;
+ };
+ };
timer {
compatible = "arm,armv8-timer";
@@ -128,14 +93,6 @@
phandle = <0x11>;
};
- fpga-region {
- compatible = "fpga-region";
- fpga-mgr = <0x10>;
- #address-cells = <0x02>;
- #size-cells = <0x02>;
- ranges;
- phandle = <0x57>;
- };
axi {
compatible = "simple-bus";
@@ -157,6 +114,18 @@
phandle = <0x05>;
};
+ smmu@fd800000 {
+ compatible = "arm,mmu-500";
+ reg = <0x00 0xfd800000 0x00 0x20000>;
+ #iommu-cells = <0x01>;
+ status = "disabled";
+ #global-interrupts = <0x01>;
+ interrupt-parent = <0x05>;
+ interrupts = <0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04>;
+ phandle = <0x14>;
+ };
+
+
serial@ff000000 {
bootph-all;
compatible = "xlnx,zynqmp-uart\0cdns,uart-r1p12";
@@ -199,16 +168,158 @@
xlnx,mio-bank = <0x01>;
phandle = <0x8e>;
};
+
+ ethernet@ff0e0000 {
+ compatible = "xlnx,zynqmp-gem\0cdns,gem";
+ status = "okay";
+ interrupt-parent = <0x05>;
+ interrupts = <0x00 0x3f 0x04 0x00 0x3f 0x04>;
+ reg = <0x00 0xff0e0000 0x00 0x1000>;
+ clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ iommus = <0x14 0x877>;
+ power-domains = <0x12 0x20>;
+ resets = <0x11 0x20>;
+ reset-names = "gem3_rst";
+ clocks = <0x04 0x1f 0x04 0x6b 0x04 0x30 0x04 0x34 0x04 0x2c>;
+ assigned-clocks = <0x04 0x2c>;
+ phy-handle = <0x15>;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x16>;
+ phy-mode = "rgmii-id";
+ xlnx,ptp-enet-clock = <0x00>;
+ local-mac-address = [ff ff ff ff ff ff];
+ phandle = <0x74>;
+
+ mdio {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ phandle = <0x75>;
+
+ ethernet-phy@c {
+ #phy-cells = <0x01>;
+ compatible = "ethernet-phy-id2000.a231";
+ reg = <0x0c>;
+ ti,rx-internal-delay = <0x08>;
+ ti,tx-internal-delay = <0x0a>;
+ ti,fifo-depth = <0x01>;
+ ti,dp83867-rxctrl-strap-quirk;
+ reset-gpios = <0x17 0x06 0x01>;
+ phandle = <0x15>;
+ };
+ };
+ };
- smmu@fd800000 {
- compatible = "arm,mmu-500";
- reg = <0x00 0xfd800000 0x00 0x20000>;
- #iommu-cells = <0x01>;
- status = "disabled";
- #global-interrupts = <0x01>;
+
+ i2c@ff030000 {
+ compatible = "cdns,i2c-r1p14";
+ status = "okay";
interrupt-parent = <0x05>;
- interrupts = <0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04>;
- phandle = <0x14>;
+ interrupts = <0x00 0x12 0x04>;
+ clock-frequency = <0x61a80>;
+ reg = <0x00 0xff030000 0x00 0x1000>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ power-domains = <0x12 0x26>;
+ clocks = <0x04 0x3e>;
+ pinctrl-names = "default\0gpio";
+ pinctrl-0 = <0x1c>;
+ pinctrl-1 = <0x1d>;
+ scl-gpios = <0x1b 0x10 0x06>;
+ sda-gpios = <0x1b 0x11 0x06>;
+ phandle = <0x78>;
+
+ i2c-mux@74 {
+ compatible = "nxp,pca9548";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x74>;
+
+ i2c@0 {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00>;
+
+ eeprom@54 {
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ phandle = <0x79>;
+
+ board-sn@0 {
+ reg = <0x00 0x14>;
+ phandle = <0x7a>;
+ };
+
+ eth-mac@20 {
+ reg = <0x20 0x06>;
+ phandle = <0x7b>;
+ };
+
+ board-name@d0 {
+ reg = <0xd0 0x06>;
+ phandle = <0x7c>;
+ };
+
+ board-revision@e0 {
+ reg = <0xe0 0x03>;
+ phandle = <0x7d>;
+ };
+ };
+ };
+ };
+ };
+
+
+ i2c@ff020000 {
+ compatible = "cdns,i2c-r1p14";
+ status = "okay";
+ interrupt-parent = <0x05>;
+ interrupts = <0x00 0x11 0x04>;
+ clock-frequency = <0x61a80>;
+ reg = <0x00 0xff020000 0x00 0x1000>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ power-domains = <0x12 0x25>;
+ clocks = <0x04 0x3d>;
+ pinctrl-names = "default\0gpio";
+ pinctrl-0 = <0x19>;
+ pinctrl-1 = <0x1a>;
+ scl-gpios = <0x1b 0x0e 0x06>;
+ sda-gpios = <0x1b 0x0f 0x06>;
+ phandle = <0x76>;
+
+ gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ gpio-line-names = "PS_GTR_LAN_SEL0\0PS_GTR_LAN_SEL1\0PS_GTR_LAN_SEL2\0PS_GTR_LAN_SEL3\0PCI_CLK_DIR_SEL\0IIC_MUX_RESET_B\0GEM3_EXP_RESET_B\0\0\0\0\0\0\0\0\0";
+ phandle = <0x17>;
+ };
+ };
+
+
+ gpio@ff0a0000 {
+ compatible = "xlnx,zynqmp-gpio-1.0";
+ status = "okay";
+ #gpio-cells = <0x02>;
+ gpio-controller;
+ interrupt-parent = <0x05>;
+ interrupts = <0x00 0x10 0x04>;
+ interrupt-controller;
+ #interrupt-cells = <0x02>;
+ reg = <0x00 0xff0a0000 0x00 0x1000>;
+ power-domains = <0x12 0x2e>;
+ clocks = <0x04 0x1f>;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x18>;
+ emio-gpio-width = <0x20>;
+ gpio-mask-high = <0x00>;
+ gpio-mask-low = <0x5600>;
+ phandle = <0x1b>;
};
};
@@ -252,9 +363,18 @@
phandle = <0x0e>;
};
+ ref48M {
+ compatible = "fixed-clock";
+ #clock-cells = <0x00>;
+ clock-frequency = <0x2dc6c00>;
+ phandle = <0x1e>;
+ };
+
aliases {
mmc0 = "/axi/mmc@ff170000";
serial0 = "/axi/serial@ff000000";
+ ethernet0 = "/axi/ethernet@ff0e0000";
+ i2c1 = "/axi/i2c@ff030000";
};
firmware {
@@ -266,26 +386,42 @@
#power-domain-cells = <0x01>;
phandle = <0x12>;
- zynqmp-power {
- bootph-all;
- compatible = "xlnx,zynqmp-power";
- interrupt-parent = <0x05>;
- interrupts = <0x00 0x23 0x04>;
- mboxes = <0x0a 0x00 0x0a 0x01>;
- mbox-names = "tx\0rx";
- phandle = <0x42>;
- };
-
- pcap {
- compatible = "xlnx,zynqmp-pcap-fpga";
- phandle = <0x10>;
- };
-
pinctrl {
compatible = "xlnx,zynqmp-pinctrl";
status = "okay";
phandle = <0x56>;
+ i2c0-default {
+ phandle = <0x19>;
+
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <0x01>;
+ power-source = <0x01>;
+ };
+ };
+
+ i2c0-gpio {
+ phandle = <0x1a>;
+
+ mux {
+ groups = "gpio0_14_grp\0gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp\0gpio0_15_grp";
+ slew-rate = <0x01>;
+ power-source = <0x01>;
+ };
+ };
+
uart0-default {
phandle = <0x25>;
@@ -352,8 +488,120 @@
power-source = <0x01>;
};
};
+
+ gpio-default {
+ phandle = <0x18>;
+
+ mux-sw {
+ function = "gpio0";
+ groups = "gpio0_22_grp\0gpio0_23_grp";
+ };
+
+ conf-sw {
+ groups = "gpio0_22_grp\0gpio0_23_grp";
+ slew-rate = <0x01>;
+ power-source = <0x01>;
+ };
+
+ mux-msp {
+ function = "gpio0";
+ groups = "gpio0_13_grp\0gpio0_38_grp";
+ };
+
+ conf-msp {
+ groups = "gpio0_13_grp\0gpio0_38_grp";
+ slew-rate = <0x01>;
+ power-source = <0x01>;
+ };
+
+ conf-pull-up {
+ pins = "MIO22\0MIO23";
+ bias-pull-up;
+ };
+
+ conf-pull-none {
+ pins = "MIO13\0MIO38";
+ bias-disable;
+ };
+ };
+
+ i2c1-default {
+ phandle = <0x1c>;
+
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <0x01>;
+ power-source = <0x01>;
+ };
+ };
+
+ i2c1-gpio {
+ phandle = <0x1d>;
+
+ mux {
+ groups = "gpio0_16_grp\0gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp\0gpio0_17_grp";
+ slew-rate = <0x01>;
+ power-source = <0x01>;
+ };
+ };
+
+ gem3-default {
+ phandle = <0x16>;
+
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <0x01>;
+ power-source = <0x01>;
+ };
+
+ conf-rx {
+ pins = "MIO70\0MIO71\0MIO72\0MIO73\0MIO74\0MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64\0MIO65\0MIO66\0MIO67\0MIO68\0MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <0x01>;
+ power-source = <0x01>;
+ bias-disable;
+ };
+ };
};
+ gpio {
+ compatible = "xlnx,zynqmp-gpio-modepin";
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ phandle = <0x27>;
+ };
clock-controller {
bootph-all;
@@ -368,9 +616,14 @@
chosen {
bootargs = "earlycon console=ttyPS0,115200 root=/dev/mmcblk0p2 rootwait rw";
- // linux,initrd-start = <0x4000000>;
- // linux,initrd-end = <0x4536393>;
- // linux,initrd-end = <0x4800000>;
stdout-path = "serial0:115200n8";
};
-};
\ No newline at end of file
+
+ hvisor_virtio_device {
+ compatible = "hvisor";
+ interrupt-parent = <0x05>;
+ interrupts = <0x00 0x20 0x01>;
+ };
+
+
+};
diff --git a/platform/aarch64/zcu102/image/dts/zone1-linux.dts b/platform/aarch64/zcu102/image/dts/zone1.dts
similarity index 90%
rename from platform/aarch64/zcu102/image/dts/zone1-linux.dts
rename to platform/aarch64/zcu102/image/dts/zone1.dts
index a779d080..42dccdce 100644
--- a/platform/aarch64/zcu102/image/dts/zone1-linux.dts
+++ b/platform/aarch64/zcu102/image/dts/zone1.dts
@@ -6,7 +6,7 @@
#size-cells = <0x02>;
model = "ZynqMP ZCU102 RevB";
- cpus {
+ cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
@@ -65,18 +65,18 @@
method = "smc";
};
- memory@0 {
+ memory@0 {
device_type = "memory";
reg = <0x00 0x50000000 0x00 0x25000000>;
};
- timer {
+ timer {
compatible = "arm,armv8-timer";
interrupt-parent = <0x05>;
interrupts = <0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08 0x01 0x0a 0xf08>;
};
- axi {
+ axi {
compatible = "simple-bus";
bootph-all;
#address-cells = <0x02>;
@@ -95,32 +95,29 @@
num_interrupts = <0x60>;
phandle = <0x05>;
};
- };
-
+ };
- aliases {
+ aliases {
};
- // virtio blk
virtio_mmio@ff9d0000 {
dma-coherent;
interrupt-parent = <0x05>;
- interrupts = <0x0 0x2e 0x1>;
- reg = <0x0 0xff9d0000 0x0 0x200>;
+ interrupts = <0x00 0x2e 0x01>;
+ reg = <0x00 0xff9d0000 0x00 0x200>;
compatible = "virtio,mmio";
};
- // virtio serial
virtio_mmio@ff9e0000 {
dma-coherent;
interrupt-parent = <0x05>;
- interrupts = <0x0 0x2c 0x1>;
- reg = <0x0 0xff9e0000 0x0 0x200>;
+ interrupts = <0x00 0x2c 0x01>;
+ reg = <0x00 0xff9e0000 0x00 0x200>;
compatible = "virtio,mmio";
};
- chosen {
+ chosen {
bootargs = "earlycon=virtio,mmio,0xff9e0000 console=hvc0 root=/dev/vda rootwait rw";
stdout-path = "/virtio_mmio@0xff9e0000";
};
-};
\ No newline at end of file
+};
diff --git a/platform/loongarch64/ls3a5000/board.rs b/platform/loongarch64/ls3a5000/board.rs
index c68c5535..184dc110 100644
--- a/platform/loongarch64/ls3a5000/board.rs
+++ b/platform/loongarch64/ls3a5000/board.rs
@@ -22,7 +22,7 @@ pub const BOARD_NCPUS: usize = 4;
pub const ROOT_ZONE_DTB_ADDR: u64 = 0x10000f000;
pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x200000;
-pub const ROOT_ZONE_ENTRY: u64 = 0x9000000000da4000;
+pub const ROOT_ZONE_ENTRY: u64 = 0x9000000000d8c000;
pub const ROOT_ZONE_CPUS: u64 = 1 << 0;
pub const ROOT_ZONE_NAME: &str = "root-linux-la64";
diff --git a/platform/loongarch64/ls3a5000/cargo/features b/platform/loongarch64/ls3a5000/cargo/features
index 9ff5f4f9..a4727de5 100644
--- a/platform/loongarch64/ls3a5000/cargo/features
+++ b/platform/loongarch64/ls3a5000/cargo/features
@@ -1,3 +1,4 @@
+loongson_3a5000
loongson_7a2000
loongson_uart
pci
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a5000/configs/virtio.json b/platform/loongarch64/ls3a5000/configs/virtio.json
new file mode 100644
index 00000000..488affaf
--- /dev/null
+++ b/platform/loongarch64/ls3a5000/configs/virtio.json
@@ -0,0 +1,100 @@
+{
+ "zones": [
+ {
+ "id": 1,
+ "memory_region": [
+ {
+ "zone0_ipa": "0xc0000000",
+ "zonex_ipa": "0xc0000000",
+ "size": "0x10000000"
+ },
+ {
+ "zone0_ipa": "0xd0000000",
+ "zonex_ipa": "0xd0000000",
+ "size": "0x10000000"
+ }
+ ],
+ "devices": [
+ {
+ "type": "console",
+ "addr": "0x30001000",
+ "len": "0x200",
+ "irq": 4,
+ "status": "enable"
+ },
+ {
+ "type": "blk",
+ "addr": "0x30002000",
+ "len": "0x200",
+ "irq": 5,
+ "img": "/tool/linux1-disk.ext4",
+ "status": "enable"
+ }
+ ]
+ },
+ {
+ "id": 2,
+ "memory_region": [
+ {
+ "zone0_ipa": "0xa0000000",
+ "zonex_ipa": "0xa0000000",
+ "size": "0x10000000"
+ },
+ {
+ "zone0_ipa": "0xb0000000",
+ "zonex_ipa": "0xb0000000",
+ "size": "0x10000000"
+ }
+ ],
+ "devices": [
+ {
+ "type": "console",
+ "addr": "0x30001000",
+ "len": "0x200",
+ "irq": 4,
+ "status": "enable"
+ },
+ {
+ "type": "blk",
+ "addr": "0x30002000",
+ "len": "0x200",
+ "irq": 5,
+ "img": "/tool/linux2-disk.ext4",
+ "status": "enable"
+ }
+ ]
+ },
+ {
+ "id": 3,
+ "memory_region": [
+ {
+ "zone0_ipa": "0x100000000",
+ "zonex_ipa": "0x100000000",
+ "size": "0x10000000"
+ },
+ {
+ "zone0_ipa": "0x110000000",
+ "zonex_ipa": "0x110000000",
+ "size": "0x10000000"
+ }
+ ],
+ "devices": [
+ {
+ "type": "console",
+ "addr": "0x30001000",
+ "len": "0x200",
+ "irq": 4,
+ "status": "enable"
+ },
+ {
+ "type": "blk",
+ "addr": "0x30002000",
+ "len": "0x200",
+ "irq": 5,
+ "img": "/tool/linux3-disk.ext4",
+ "status": "enable"
+ }
+ ]
+ }
+ ]
+}
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a5000/configs/zone1-linux.json b/platform/loongarch64/ls3a5000/configs/zone1-linux.json
index 91d1928a..e56d3424 100644
--- a/platform/loongarch64/ls3a5000/configs/zone1-linux.json
+++ b/platform/loongarch64/ls3a5000/configs/zone1-linux.json
@@ -1,45 +1,129 @@
{
"arch": "loongarch64",
- "name": "linux2",
- "zone_id": 3,
+ "name": "linux1",
+ "zone_id": 1,
"cpus": [
- 3
+ 1
],
"memory_regions": [
{
"type": "ram",
"physical_start": "0xc0000000",
- "virtual_start": "0x00000000",
+ "virtual_start": "0xc0000000",
"size": "0x10000000"
},
{
"type": "ram",
"physical_start": "0xd0000000",
- "virtual_start": "0x90000000",
+ "virtual_start": "0xd0000000",
"size": "0x10000000"
},
{
"type": "io",
"physical_start": "0x1fe00000",
"virtual_start": "0x1fe00000",
- "size": "0x4000"
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x10080000",
+ "virtual_start": "0x10080000",
+ "size": "0x1000"
},
{
"type": "virtio",
"physical_start": "0x30001000",
"virtual_start": "0x30001000",
"size": "0x200"
+ },
+ {
+ "type": "virtio",
+ "physical_start": "0x30002000",
+ "virtual_start": "0x30002000",
+ "size": "0x200"
+ },
+ {
+ "type": "io",
+ "physical_start": "0xffffffff0000",
+ "virtual_start": "0xffffffff0000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x10000000",
+ "virtual_start": "0x10000000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x100d0000",
+ "virtual_start": "0x100d0000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x10010000",
+ "virtual_start": "0x10010000",
+ "size": "0x00010000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0x1000",
+ "virtual_start": "0x0",
+ "size": "0x10000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0xf0000",
+ "virtual_start": "0xf0000",
+ "size": "0x10000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0x140000000",
+ "virtual_start": "0x140000000",
+ "size": "0x800000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0x140800000",
+ "virtual_start": "0x140800000",
+ "size": "0x800000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0x141000000",
+ "virtual_start": "0x141000000",
+ "size": "0x800000"
}
],
"interrupts": [
- 4
+ 4,
+ 5
],
- "kernel_filepath": "/tool/vmlinux.bin",
+ "ivc_configs": [],
+ "kernel_args": "NOT_USED_YET",
+ "kernel_filepath": "/tool/nonroot/vmlinux-linux1.bin",
"dtb_filepath": "/tool/test.bin",
"kernel_load_paddr": "0xc0200000",
"dtb_load_paddr": "0xc0000000",
- "entry_point": "0x9000000000e75000",
+ "entry_point": "0x90000000c0dff000",
"arch_config": {
"dummy": "0x1234"
- }
+ },
+ "pci_config": {
+ "ecam_base": "0xfe00000000",
+ "ecam_size": "0x20000000",
+ "io_base": "0x18408000",
+ "io_size": "0x8000",
+ "pci_io_base": "0x00008000",
+ "mem32_base": "0x0",
+ "mem32_size": "0x0",
+ "pci_mem32_base": "0x0",
+ "mem64_base": "0x60000000",
+ "mem64_size": "0x20000000",
+ "pci_mem64_base": "0x60000000"
+ },
+ "num_pci_devs": 1,
+ "alloc_pci_devs": [1537]
}
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a5000/configs/zone1-virtio.json b/platform/loongarch64/ls3a5000/configs/zone1-virtio.json
deleted file mode 100644
index 8435566b..00000000
--- a/platform/loongarch64/ls3a5000/configs/zone1-virtio.json
+++ /dev/null
@@ -1,28 +0,0 @@
-{
- "zones": [
- {
- "id": 3,
- "memory_region": [
- {
- "zone0_ipa": "0xc0000000",
- "zonex_ipa": "0x00000000",
- "size": "0x10000000"
- },
- {
- "zone0_ipa": "0xd0000000",
- "zonex_ipa": "0x90000000",
- "size": "0x10000000"
- }
- ],
- "devices": [
- {
- "type": "console",
- "addr": "0x30001000",
- "len": "0x200",
- "irq": 4,
- "status": "enable"
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a5000/configs/zone2-linux.json b/platform/loongarch64/ls3a5000/configs/zone2-linux.json
new file mode 100644
index 00000000..8255f01e
--- /dev/null
+++ b/platform/loongarch64/ls3a5000/configs/zone2-linux.json
@@ -0,0 +1,117 @@
+{
+ "arch": "loongarch64",
+ "name": "linux2",
+ "zone_id": 2,
+ "cpus": [
+ 2
+ ],
+ "memory_regions": [
+ {
+ "type": "ram",
+ "physical_start": "0xa0000000",
+ "virtual_start": "0xa0000000",
+ "size": "0x10000000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0xb0000000",
+ "virtual_start": "0xb0000000",
+ "size": "0x10000000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x1fe00000",
+ "virtual_start": "0x1fe00000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x10080000",
+ "virtual_start": "0x10080000",
+ "size": "0x1000"
+ },
+ {
+ "type": "virtio",
+ "physical_start": "0x30001000",
+ "virtual_start": "0x30001000",
+ "size": "0x200"
+ },
+ {
+ "type": "virtio",
+ "physical_start": "0x30002000",
+ "virtual_start": "0x30002000",
+ "size": "0x200"
+ },
+ {
+ "type": "io",
+ "physical_start": "0xffffffff0000",
+ "virtual_start": "0xffffffff0000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x10000000",
+ "virtual_start": "0x10000000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x100d0000",
+ "virtual_start": "0x100d0000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x10010000",
+ "virtual_start": "0x10010000",
+ "size": "0x00010000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0x1000",
+ "virtual_start": "0x0",
+ "size": "0x10000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0xf0000",
+ "virtual_start": "0xf0000",
+ "size": "0x10000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0x140800000",
+ "virtual_start": "0x140800000",
+ "size": "0x800000"
+ }
+ ],
+ "interrupts": [
+ 4,
+ 5
+ ],
+ "ivc_configs": [],
+ "kernel_args": "NOT_USED_YET",
+ "kernel_filepath": "/tool/nonroot/vmlinux-linux2.bin",
+ "dtb_filepath": "/tool/test.bin",
+ "kernel_load_paddr": "0xa0200000",
+ "dtb_load_paddr": "0xa0000000",
+ "entry_point": "0x90000000a0dff000",
+ "arch_config": {
+ "dummy": "0x1234"
+ },
+ "pci_config": {
+ "ecam_base": "0xfe00000000",
+ "ecam_size": "0x20000000",
+ "io_base": "0x18408000",
+ "io_size": "0x8000",
+ "pci_io_base": "0x00008000",
+ "mem32_base": "0x0",
+ "mem32_size": "0x0",
+ "pci_mem32_base": "0x0",
+ "mem64_base": "0x60000000",
+ "mem64_size": "0x20000000",
+ "pci_mem64_base": "0x60000000"
+ },
+ "num_pci_devs": 1,
+ "alloc_pci_devs": [1538]
+}
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a5000/configs/zone3-linux.json b/platform/loongarch64/ls3a5000/configs/zone3-linux.json
new file mode 100644
index 00000000..fcb03239
--- /dev/null
+++ b/platform/loongarch64/ls3a5000/configs/zone3-linux.json
@@ -0,0 +1,117 @@
+{
+ "arch": "loongarch64",
+ "name": "linux3",
+ "zone_id": 3,
+ "cpus": [
+ 3
+ ],
+ "memory_regions": [
+ {
+ "type": "ram",
+ "physical_start": "0x100000000",
+ "virtual_start": "0x100000000",
+ "size": "0x10000000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0x110000000",
+ "virtual_start": "0x110000000",
+ "size": "0x10000000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x1fe00000",
+ "virtual_start": "0x1fe00000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x10080000",
+ "virtual_start": "0x10080000",
+ "size": "0x1000"
+ },
+ {
+ "type": "virtio",
+ "physical_start": "0x30001000",
+ "virtual_start": "0x30001000",
+ "size": "0x200"
+ },
+ {
+ "type": "virtio",
+ "physical_start": "0x30002000",
+ "virtual_start": "0x30002000",
+ "size": "0x200"
+ },
+ {
+ "type": "io",
+ "physical_start": "0xffffffff0000",
+ "virtual_start": "0xffffffff0000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x10000000",
+ "virtual_start": "0x10000000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x100d0000",
+ "virtual_start": "0x100d0000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x10010000",
+ "virtual_start": "0x10010000",
+ "size": "0x00010000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0x1000",
+ "virtual_start": "0x0",
+ "size": "0x10000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0xf0000",
+ "virtual_start": "0xf0000",
+ "size": "0x10000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0x141000000",
+ "virtual_start": "0x141000000",
+ "size": "0x800000"
+ }
+ ],
+ "interrupts": [
+ 4,
+ 5
+ ],
+ "ivc_configs": [],
+ "kernel_args": "NOT_USED_YET",
+ "kernel_filepath": "/tool/nonroot/vmlinux-linux3.bin",
+ "dtb_filepath": "/tool/test.bin",
+ "kernel_load_paddr": "0x100200000",
+ "dtb_load_paddr": "0x100000000",
+ "entry_point": "0x9000000100dff000",
+ "arch_config": {
+ "dummy": "0x1234"
+ },
+ "pci_config": {
+ "ecam_base": "0xfe00000000",
+ "ecam_size": "0x20000000",
+ "io_base": "0x18408000",
+ "io_size": "0x8000",
+ "pci_io_base": "0x00008000",
+ "mem32_base": "0x0",
+ "mem32_size": "0x0",
+ "pci_mem32_base": "0x0",
+ "mem64_base": "0x60000000",
+ "mem64_size": "0x20000000",
+ "pci_mem64_base": "0x60000000"
+ },
+ "num_pci_devs": 1,
+ "alloc_pci_devs": [1539]
+}
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a5000/image/dts/Makefile b/platform/loongarch64/ls3a5000/image/dts/Makefile
new file mode 100644
index 00000000..ed0d0749
--- /dev/null
+++ b/platform/loongarch64/ls3a5000/image/dts/Makefile
@@ -0,0 +1,14 @@
+DTS_FILES := $(wildcard *.dts)
+DTB_FILES := $(DTS_FILES:.dts=.dtb)
+
+all: $(DTB_FILES)
+
+%.dts.1: %.dts
+# preprocess all includes into a single dts with suffix .1
+ cpp -I include -nostdinc -E -x assembler-with-cpp $< > $@
+
+%.dtb: %.dts.1
+ dtc -I dts -O dtb $< -o $@
+
+clean:
+ rm -f $(DTB_FILES)
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a5000/image/dts/include/irq.h b/platform/loongarch64/ls3a5000/image/dts/include/irq.h
new file mode 100644
index 00000000..9e3d183e
--- /dev/null
+++ b/platform/loongarch64/ls3a5000/image/dts/include/irq.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * This header provides constants for most IRQ bindings.
+ *
+ * Most IRQ bindings include a flags cell as part of the IRQ specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
+
+#define IRQ_TYPE_NONE 0
+#define IRQ_TYPE_EDGE_RISING 1
+#define IRQ_TYPE_EDGE_FALLING 2
+#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
+#define IRQ_TYPE_LEVEL_HIGH 4
+#define IRQ_TYPE_LEVEL_LOW 8
+
+#endif
diff --git a/platform/loongarch64/ls3a5000/image/dts/include/loongson-3a5000.dtsi b/platform/loongarch64/ls3a5000/image/dts/include/loongson-3a5000.dtsi
new file mode 100644
index 00000000..9a135f1d
--- /dev/null
+++ b/platform/loongarch64/ls3a5000/image/dts/include/loongson-3a5000.dtsi
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+* Copyright (C) 2023 Loongson Technology Corporation Limited
+*/
+
+/dts-v1/;
+
+// #include
+#include "irq.h"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "loongson,loongson3";
+ device_type = "cpu";
+ reg = <0x0>;
+ l2-cache = <&vcache0>;
+ next-level-cache = <&scache0>;
+ numa-node-id = <0>;
+ };
+ vcache0: l2-cache0 {
+ compatible = "cache";
+ next-level-cache = <&scache0>;
+ };
+ vcache1: l2-cache1 {
+ compatible = "cache";
+ next-level-cache = <&scache0>;
+ };
+ vcache2: l2-cache2 {
+ compatible = "cache";
+ next-level-cache = <&scache0>;
+ };
+ vcache3: l2-cache3 {
+ compatible = "cache";
+ next-level-cache = <&scache0>;
+ };
+ vcache4: l2-cache4 {
+ compatible = "cache";
+ next-level-cache = <&scache1>;
+ };
+ vcache5: l2-cache5 {
+ compatible = "cache";
+ next-level-cache = <&scache1>;
+ };
+ vcache6: l2-cache6 {
+ compatible = "cahce";
+ next-level-cache = <&scache1>;
+ };
+ vcache7: l2-cache7 {
+ compatible = "cache";
+ next-level-cache = <&scache1>;
+ };
+ vcache8: l2-cache8 {
+ compatible = "cache";
+ next-level-cache = <&scache2>;
+ };
+ vcache9: l2-cache9 {
+ compatible = "cache";
+ next-level-cache = <&scache2>;
+ };
+ vcachea: l2-cachea {
+ compatible = "cache";
+ next-level-cache = <&scache2>;
+ };
+ vcacheb: l2-cacheb {
+ compatible = "cache";
+ next-level-cache = <&scache2>;
+ };
+ vcachec: l2-cachec {
+ compatible = "cache";
+ next-level-cache = <&scache3>;
+ };
+ vcached: l2-cached {
+ compatible = "cache";
+ next-level-cache = <&scache3>;
+ };
+ vcachee: l2-cachee {
+ compatible = "cache";
+ next-level-cache = <&scache3>;
+ };
+ vcachef: l2-cachef {
+ compatible = "cache";
+ next-level-cache = <&scache3>;
+ };
+ scache0: l3-cache0 {
+ compatible = "cache";
+ };
+ scache1: l3-cache1 {
+ compatible = "cache";
+ };
+ scache2: l3-cache2 {
+ compatible = "cache";
+ };
+ scache3: l3-cache3 {
+ compatible = "cache";
+ };
+ };
+};
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpuintc: interrupt-controller {
+ compatible = "loongson,cpu-interrupt-controller";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ phandle = <0x8001>;
+ };
+
+ board: platform {
+ compatible = "loongson,nbus", "simple-bus";
+
+ ranges = <
+ 0x00 0x10000000 0x00 0x10000000 0x00 0x10000000
+ 0x00 0x02000000 0x00 0x02000000 0x00 0x02000000
+ 0x00 0x20000000 0x00 0x20000000 0x00 0x10000000
+ 0x00 0x40000000 0x00 0x40000000 0x00 0x40000000
+ 0xfe 0x00000000 0xfe 0x00000000 0x00 0x40000000
+ >;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ // liointc: interrupt-controller@1fe01400 {
+ // compatible = "loongson,liointc-1.0";
+ // reg = <0x0 0x1fe01400 0x0 0x64>;
+ // interrupt-controller;
+ // #interrupt-cells = <2>;
+ // interrupt-parent = <&cpuintc>;
+ // interrupts = <2>;
+ // interrupt-names = "int0";
+ // loongson,parent_int_map =
+ // <0x00000000>, /* int0 */
+ // <0xffffffff>, /* int1 */
+ // <0x00000000>, /* int2 */
+ // <0x00000000>; /* int3 */
+ // };
+
+ eiointc: interrupt-controller@1fe01600 {
+ compatible = "loongson,ls2k2000-eiointc";
+ reg = <0x0 0x1fe01600 0x0 0xea00>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <3>;
+ phandle = <0x8002>;
+ // status = "disabled";
+ };
+
+ pic: interrupt-controller@10000000 {
+ compatible = "loongson,pch-pic-1.0";// Platform Controller Hub - Programmable Interrupt Controller
+ reg = <0x0 0x10000000 0x0 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ loongson,pic-base-vec = <0>;
+ interrupt-parent = <&eiointc>;
+ phandle = <0x8003>;
+ // status = "disabled";
+ };
+
+ // root's msi
+ // msi: msi-controller@1fe01140 {
+ // compatible = "loongson,pch-msi-1.0";
+ // reg = <0x0 0x1fe01140 0x0 0x8>;
+ // interrupt-controller;
+ // #interrupt-cells = <1>;
+ // msi-controller;
+ // loongson,msi-base-vec = <64>;
+ // loongson,msi-num-vecs = <48>; // [64-111(48),112-159(48),160-207(48),208-255(48)]
+ // interrupt-parent = <&eiointc>;
+ // phandle = <0x8004>;
+ // // status = "disabled";
+ // };
+
+ rtc0: rtc@100d0100 {
+ compatible = "loongson,ls7a-rtc";// Real Time Clock
+ reg = <0x0 0x100d0100 0x0 0x100>;
+ interrupt-parent = <&pic>;// pic-rtc0
+ interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
+ // status = "disabled";
+ };
+
+ ref_100m: clock-ref-100m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "ref_100m";
+ };
+
+ uart0: serial@1fe001e0 {
+ compatible = "ns16550a";
+ reg = <0x0 0x1fe001e0 0x0 0x100>;
+ clock-frequency = <100000000>;// 100M
+ // interrupt-parent = <&pic>;
+ // interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; // from ACPI ASL Interrupt number
+ // interrupt-parent = <&liointc>;
+ // interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ uart1: serial@10080000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x10080000 0x0 0x100>;
+ clock-frequency = <50000000>;// 50M (according to ACPI ASL)
+ interrupt-parent = <&pic>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ status = "disabled";
+ };
+ };
+};
diff --git a/platform/loongarch64/ls3a5000/image/dts/zone0.dts b/platform/loongarch64/ls3a5000/image/dts/zone0.dts
index 038403c6..faa2cf4f 100644
--- a/platform/loongarch64/ls3a5000/image/dts/zone0.dts
+++ b/platform/loongarch64/ls3a5000/image/dts/zone0.dts
@@ -1,36 +1,59 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2023 Loongson Technology Corporation Limited
-* Modified for hvisor by wheatfox(enkerewpo@hotmail.com) syswonder.org 2024
+* Modified for hvisor by wheatfox(wheatfox17@icloud.com) syswonder.org 2024
*/
/dts-v1/;
#include "loongson-3a5000.dtsi"
+// if you changed this, remember to change the aliases at chosen/stdout-path
+&uart1 {
+ // status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
/ {
compatible = "loongson,ls3a5000-root", "loongson,ls3a5000";
- model = "Loongson-3A5000 hvisor root zone board";
+ model = "Loongson3 hvisor root zone board";
aliases {
- serial0 = &uart0;
+ serial = &uart0;
};
chosen {
- stdout-path = "serial0:115200n8";
- bootargs = "earlycon console=ttyS0,115200n8 initramfs_async=false rootwait debug";
+ stdout-path = "serial:115200n8";
+
+ // initramfs
+ bootargs = "earlycon console=ttyS0,115200n8 initramfs_async=false rootwait debug nohlt";
+
+ // SSD root, on SSD partition 4 with ext4 format
+ // bootargs = "earlycon console=ttyS0,115200n8 root=/dev/nvme0n1p4 rootwait rw nohlt";
};
memory@200000 {
device_type = "memory";
- reg = <0 0x00200000 0 0x0ee00000
+ reg = <
+ 0 0x00200000 0 0x0ee00000
0 0x90000000 0 0x10000000
- 0 0xf0000000 0 0x10000000
+
0 0xc0000000 0 0x30000000
- >;
+ 0 0xa0000000 0 0x20000000
+
+ 0x1 0x00000000 0 0x20000000
+ 0x1 0x60000000 0 0x10000000
+
+ 0x1 0x40000000 0 0x800000
+
+ 0 0xf0000000 0 0x10000000
+ >;// the last part will alwarys be system ram! (with extra inneer reserved memory) so we have to add one extra region at the end.
};
- hvisor_device {
+ hvisor_virtio_device {
compatible = "hvisor";
interrupt-parent = <&cpuintc>;
interrupts = <4>;
@@ -40,13 +63,162 @@
#address-cells = <0x02>;
#size-cells = <0x02>;
ranges;
- nonroot0xc0000000 {
+ nonroot1 {
no-map;
- reg = <0x00 0xc0000000 0x00 0x30000000>;
+ reg = <0x00 0xc0000000 0x00 0x20000000>;
+ };
+ nonroot2 {
+ no-map;
+ reg = <0x00 0xa0000000 0x00 0x20000000>;
+ };
+ nonroot3 {
+ no-map;
+ reg = <0x01 0x00000000 0x00 0x20000000>;
+ };
+ shmem@0 {
+ no-map;
+ reg = <0x1 0x40000000 0 0x800000>;
};
};
+
+ msi: msi-controller@1fe01140 {
+ compatible = "loongson,pch-msi-1.0";
+ reg = <0x0 0x1fe01140 0x0 0x8>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ msi-controller;
+ loongson,msi-base-vec = <64>;
+ loongson,msi-num-vecs = <48>;// [64-111(48),112-159(48),160-207(48),208-255(48)]
+ interrupt-parent = <&eiointc>;
+ phandle = <0x8004>;
+ // status = "disabled";
+ };
+
+ pcie@1a000000 {
+ compatible = "loongson,ls7a-pci";
+
+ // status = "disabled"; // use this to enable/disable the PCIe devices
+
+ // configuration space
+ reg =
+ <0x00 0x1a000000 0x0 0x20000000>,
+ <0xfe 0x00000000 0x0 0x20000000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ msi-parent = <&msi>;
+ bus-range = <0x0 0xff>;
+
+ // PCIe resources
+ ranges =
+ <0x01000000 0x0 0x00008000 0x0 0x18408000 0x0 0x00008000>,// 0x01000000 (IO) [PCIe space base address][CPU space address][size]
+ <0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>;// 0x02000000 (MEM) [PCIe space base address][CPU space address][size]
+
+ // interrputs
+ interrupt-map-mask = <0xff00 0x00 0x00 0x7>;
+ interrupt-map =
+ <
+ 0x1800 0x00 0x00 0x01 0x8003 12 IRQ_TYPE_LEVEL_HIGH// 3,0 a
+ 0x1800 0x00 0x00 0x02 0x8003 13 IRQ_TYPE_LEVEL_HIGH// 3,0 b
+
+ 0x2000 0x00 0x00 0x01 0x8003 49 IRQ_TYPE_LEVEL_HIGH// 4,0 a
+ 0x2100 0x00 0x00 0x01 0x8003 48 IRQ_TYPE_LEVEL_HIGH// 4,1 b
+
+ 0x2800 0x00 0x00 0x01 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 a
+ 0x2800 0x00 0x00 0x02 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 b
+ 0x2800 0x00 0x00 0x03 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 c
+ 0x2800 0x00 0x00 0x04 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 d
+
+ 0x2900 0x00 0x00 0x01 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 a
+ 0x2900 0x00 0x00 0x02 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 b
+ 0x2900 0x00 0x00 0x03 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 c
+ 0x2900 0x00 0x00 0x04 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 d
+
+ 0x3000 0x00 0x00 0x01 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 a
+ 0x3000 0x00 0x00 0x02 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 b
+ 0x3000 0x00 0x00 0x03 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 c
+ 0x3000 0x00 0x00 0x04 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 d
+
+ 0x3100 0x00 0x00 0x01 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 a
+ 0x3100 0x00 0x00 0x02 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 b
+ 0x3100 0x00 0x00 0x03 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 c
+ 0x3100 0x00 0x00 0x04 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 d
+
+ 0x3200 0x00 0x00 0x01 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 a
+ 0x3200 0x00 0x00 0x02 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 b
+ 0x3200 0x00 0x00 0x03 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 c
+ 0x3200 0x00 0x00 0x04 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 d
+
+ 0x3800 0x00 0x00 0x01 0x8003 78 IRQ_TYPE_LEVEL_HIGH// 7,0 a
+ 0x3800 0x00 0x00 0x02 0x8003 79 IRQ_TYPE_LEVEL_HIGH// 7,0 b
+
+ 0x4000 0x00 0x00 0x01 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 a
+ 0x4000 0x00 0x00 0x02 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 b
+ 0x4000 0x00 0x00 0x03 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 c
+ 0x4000 0x00 0x00 0x04 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 d
+
+ 0x4800 0x00 0x00 0x01 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 a
+ 0x4800 0x00 0x00 0x02 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 b
+ 0x4800 0x00 0x00 0x03 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 c
+ 0x4800 0x00 0x00 0x04 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 d
+
+ 0x5000 0x00 0x00 0x01 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 a
+ 0x5000 0x00 0x00 0x02 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 b
+ 0x5000 0x00 0x00 0x03 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 c
+ 0x5000 0x00 0x00 0x04 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 d
+
+ 0x5800 0x00 0x00 0x01 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 a
+ 0x5800 0x00 0x00 0x02 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 b
+ 0x5800 0x00 0x00 0x03 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 c
+ 0x5800 0x00 0x00 0x04 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 d
+
+ 0x6000 0x00 0x00 0x01 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 a
+ 0x6000 0x00 0x00 0x02 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 b
+ 0x6000 0x00 0x00 0x03 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 c
+ 0x6000 0x00 0x00 0x04 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 d
+
+ 0x6800 0x00 0x00 0x01 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 a
+ 0x6800 0x00 0x00 0x02 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 b
+ 0x6800 0x00 0x00 0x03 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 c
+ 0x6800 0x00 0x00 0x04 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 d
+
+ 0x7000 0x00 0x00 0x01 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 a
+ 0x7000 0x00 0x00 0x02 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 b
+ 0x7000 0x00 0x00 0x03 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 c
+ 0x7000 0x00 0x00 0x04 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 d
+
+ 0x7800 0x00 0x00 0x01 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 a
+ 0x7800 0x00 0x00 0x02 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 b
+ 0x7800 0x00 0x00 0x03 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 c
+ 0x7800 0x00 0x00 0x04 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 d
+
+ 0x8000 0x00 0x00 0x01 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 a
+ 0x8000 0x00 0x00 0x02 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 b
+ 0x8000 0x00 0x00 0x03 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 c
+ 0x8000 0x00 0x00 0x04 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 d
+
+ 0x9800 0x00 0x00 0x01 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 a
+ 0x9800 0x00 0x00 0x02 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 b
+ 0x9800 0x00 0x00 0x03 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 c
+ 0x9800 0x00 0x00 0x04 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 d
+
+ 0xa000 0x00 0x00 0x01 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 a
+ 0xa000 0x00 0x00 0x02 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 b
+ 0xa000 0x00 0x00 0x03 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 c
+ 0xa000 0x00 0x00 0x04 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 d
+
+ 0xb800 0x00 0x00 0x01 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 a
+ 0xb800 0x00 0x00 0x02 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 b
+ 0xb800 0x00 0x00 0x03 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 c
+ 0xb800 0x00 0x00 0x04 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 d
+
+ 0xc800 0x00 0x00 0x01 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 a
+ 0xc800 0x00 0x00 0x02 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 b
+ 0xc800 0x00 0x00 0x03 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 c
+ 0xc800 0x00 0x00 0x04 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 d
+ >;
+
+ #interrupt-cells = <0x01>;
+ };
};
-
-&uart0 {
- status = "okay";
-};
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a5000/image/dts/zone1-linux.dts b/platform/loongarch64/ls3a5000/image/dts/zone1-linux.dts
index 377116b2..98b5e2db 100644
--- a/platform/loongarch64/ls3a5000/image/dts/zone1-linux.dts
+++ b/platform/loongarch64/ls3a5000/image/dts/zone1-linux.dts
@@ -1,35 +1,75 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2023 Loongson Technology Corporation Limited
-* Modified for hvisor by wheatfox(enkerewpo@hotmail.com) syswonder.org 2024
+* Modified for hvisor by wheatfox(wheatfox17@icloud.com) syswonder.org 2024
*/
/dts-v1/;
#include "loongson-3a5000.dtsi"
+
+&uart1 {
+ status = "okay";
+};
+
+
/ {
compatible = "loongson,ls3a5000-root", "loongson,ls3a5000";
- model = "Loongson-3A5000 hvisor nonroot zone board";
+ model = "Loongson3 hvisor nonroot zone board";
aliases {
- serial0 = &uart0;
+ serial = &uart1;
};
chosen {
- // stdout-path = "serial0:115200n8";
- bootargs = "earlycon console=ttyS0,115200n8 initramfs_async=false rootwait debug";
- // stdout-path = "/virtio_mmio@30001000";
- // bootargs = "earlycon console=hvc0 rootwait debug";
+ // initramfs
+ bootargs = "earlycon console=ttyS0,115200n8 initramfs_async=false rootwait debug loglevel=8 earlyprintk nohlt";
+
+ // SSD root, a {zone_name}-disk.ext4 virtio blk file on SSD root_hvisor partition
+ // bootargs = "earlycon console=ttyS0,115200n8 rootwait root=/dev/vda rw";
};
memory@200000 {
device_type = "memory";
- reg = <0 0x00200000 0 0x0ee00000
- 0 0x90000000 0 0x10000000
+ reg = <0 0xc0200000 0 0x0ee00000
+ 0 0xd0000000 0 0x10000000
+ 0x1 0x40000000 0 0x800000
+ 0x1 0x40800000 0 0x800000
+ 0x1 0x41000000 0 0x800000
>;
};
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ shmem@0 {
+ no-map;
+ reg = <0x1 0x40000000 0 0x800000>;
+ };
+ shmem@1 {
+ no-map;
+ reg = <0x1 0x40800000 0 0x800000>;
+ };
+ shmem@2 {
+ no-map;
+ reg = <0x1 0x41000000 0 0x800000>;
+ };
+ };
+
+ msi: msi-controller@1fe01140 {
+ compatible = "loongson,pch-msi-1.0";
+ reg = <0x0 0x1fe01140 0x0 0x8>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ msi-controller;
+ loongson,msi-base-vec = <112>;
+ loongson,msi-num-vecs = <48>; // [64-111(48),112-159(48),160-207(48),208-255(48)]
+ interrupt-parent = <&eiointc>;
+ phandle = <0x8004>;
+ };
+
// virtio console
virtio_mmio@30001000 {
dma-coherent;
@@ -39,8 +79,141 @@
reg = <0x0 0x30001000 0x0 0x200>;
status = "okay";
};
+ // virtio blk
+ virtio_mmio@30002000 {
+ dma-coherent;
+ compatible = "virtio,mmio";
+ // interrupt-parent = <&cpuintc>;
+ // interrupts = <5>;// = hwirq
+ interrupt-parent = <&cpuintc>;
+ interrupts = <5>;// = hwirq
+ reg = <0x0 0x30002000 0x0 0x200>;
+ status = "okay";
+ };
+
+ pcie@1a000000 {
+ compatible = "loongson,ls7a-pci";
+
+ // configuration space
+ reg =
+ <0x00 0x1a000000 0x0 0x20000000>,
+ <0xfe 0x00000000 0x0 0x20000000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ msi-parent = <&msi>;
+ bus-range = <0x0 0xff>;
+
+ // PCIe resources
+ ranges =
+ <0x01000000 0x0 0x00008000 0x0 0x18408000 0x0 0x00008000>,// 0x01000000 (IO) [PCIe space base address][CPU space address][size]
+ <0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>;// 0x02000000 (MEM) [PCIe space base address][CPU space address][size]
+
+ // interrputs
+ interrupt-map-mask = <0xff00 0x00 0x00 0x7>;
+ interrupt-map =
+ <
+ 0x1800 0x00 0x00 0x01 0x8003 12 IRQ_TYPE_LEVEL_HIGH// 3,0 a
+ 0x1800 0x00 0x00 0x02 0x8003 13 IRQ_TYPE_LEVEL_HIGH// 3,0 b
+
+ 0x2000 0x00 0x00 0x01 0x8003 49 IRQ_TYPE_LEVEL_HIGH// 4,0 a
+ 0x2100 0x00 0x00 0x01 0x8003 48 IRQ_TYPE_LEVEL_HIGH// 4,1 b
+
+ 0x2800 0x00 0x00 0x01 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 a
+ 0x2800 0x00 0x00 0x02 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 b
+ 0x2800 0x00 0x00 0x03 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 c
+ 0x2800 0x00 0x00 0x04 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 d
+
+ 0x2900 0x00 0x00 0x01 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 a
+ 0x2900 0x00 0x00 0x02 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 b
+ 0x2900 0x00 0x00 0x03 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 c
+ 0x2900 0x00 0x00 0x04 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 d
+
+ 0x3000 0x00 0x00 0x01 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 a
+ 0x3000 0x00 0x00 0x02 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 b
+ 0x3000 0x00 0x00 0x03 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 c
+ 0x3000 0x00 0x00 0x04 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 d
+
+ 0x3100 0x00 0x00 0x01 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 a
+ 0x3100 0x00 0x00 0x02 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 b
+ 0x3100 0x00 0x00 0x03 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 c
+ 0x3100 0x00 0x00 0x04 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 d
+
+ 0x3200 0x00 0x00 0x01 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 a
+ 0x3200 0x00 0x00 0x02 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 b
+ 0x3200 0x00 0x00 0x03 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 c
+ 0x3200 0x00 0x00 0x04 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 d
+
+ 0x3800 0x00 0x00 0x01 0x8003 78 IRQ_TYPE_LEVEL_HIGH// 7,0 a
+ 0x3800 0x00 0x00 0x02 0x8003 79 IRQ_TYPE_LEVEL_HIGH// 7,0 b
+
+ 0x4000 0x00 0x00 0x01 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 a
+ 0x4000 0x00 0x00 0x02 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 b
+ 0x4000 0x00 0x00 0x03 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 c
+ 0x4000 0x00 0x00 0x04 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 d
+
+ 0x4800 0x00 0x00 0x01 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 a
+ 0x4800 0x00 0x00 0x02 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 b
+ 0x4800 0x00 0x00 0x03 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 c
+ 0x4800 0x00 0x00 0x04 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 d
+
+ 0x5000 0x00 0x00 0x01 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 a
+ 0x5000 0x00 0x00 0x02 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 b
+ 0x5000 0x00 0x00 0x03 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 c
+ 0x5000 0x00 0x00 0x04 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 d
+
+ 0x5800 0x00 0x00 0x01 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 a
+ 0x5800 0x00 0x00 0x02 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 b
+ 0x5800 0x00 0x00 0x03 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 c
+ 0x5800 0x00 0x00 0x04 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 d
+
+ 0x6000 0x00 0x00 0x01 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 a
+ 0x6000 0x00 0x00 0x02 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 b
+ 0x6000 0x00 0x00 0x03 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 c
+ 0x6000 0x00 0x00 0x04 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 d
+
+ 0x6800 0x00 0x00 0x01 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 a
+ 0x6800 0x00 0x00 0x02 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 b
+ 0x6800 0x00 0x00 0x03 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 c
+ 0x6800 0x00 0x00 0x04 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 d
+
+ 0x7000 0x00 0x00 0x01 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 a
+ 0x7000 0x00 0x00 0x02 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 b
+ 0x7000 0x00 0x00 0x03 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 c
+ 0x7000 0x00 0x00 0x04 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 d
+
+ 0x7800 0x00 0x00 0x01 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 a
+ 0x7800 0x00 0x00 0x02 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 b
+ 0x7800 0x00 0x00 0x03 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 c
+ 0x7800 0x00 0x00 0x04 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 d
+
+ 0x8000 0x00 0x00 0x01 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 a
+ 0x8000 0x00 0x00 0x02 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 b
+ 0x8000 0x00 0x00 0x03 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 c
+ 0x8000 0x00 0x00 0x04 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 d
+
+ 0x9800 0x00 0x00 0x01 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 a
+ 0x9800 0x00 0x00 0x02 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 b
+ 0x9800 0x00 0x00 0x03 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 c
+ 0x9800 0x00 0x00 0x04 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 d
+
+ 0xa000 0x00 0x00 0x01 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 a
+ 0xa000 0x00 0x00 0x02 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 b
+ 0xa000 0x00 0x00 0x03 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 c
+ 0xa000 0x00 0x00 0x04 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 d
+
+ 0xb800 0x00 0x00 0x01 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 a
+ 0xb800 0x00 0x00 0x02 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 b
+ 0xb800 0x00 0x00 0x03 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 c
+ 0xb800 0x00 0x00 0x04 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 d
+
+ 0xc800 0x00 0x00 0x01 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 a
+ 0xc800 0x00 0x00 0x02 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 b
+ 0xc800 0x00 0x00 0x03 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 c
+ 0xc800 0x00 0x00 0x04 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 d
+ >;
+
+ #interrupt-cells = <0x01>;
+ };
};
-
-&uart0 {
- status = "okay";
-};
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a5000/image/dts/zone2-linux.dts b/platform/loongarch64/ls3a5000/image/dts/zone2-linux.dts
new file mode 100644
index 00000000..a8504086
--- /dev/null
+++ b/platform/loongarch64/ls3a5000/image/dts/zone2-linux.dts
@@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+* Copyright (C) 2023 Loongson Technology Corporation Limited
+* Modified for hvisor by wheatfox(wheatfox17@icloud.com) syswonder.org 2024
+*/
+
+/dts-v1/;
+
+#include "loongson-3a5000.dtsi"
+
+
+&uart1 {
+ status = "okay";
+ // set the above 'uart1' to 'uart0' if you don't have a COM connection right now
+};
+
+
+/ {
+ compatible = "loongson,ls3a5000-root", "loongson,ls3a5000";
+ model = "Loongson3 hvisor nonroot zone board";
+
+ aliases {
+ serial = &uart1;
+ };
+
+ chosen {
+ // initramfs
+ bootargs = "earlycon console=ttyS0,115200n8 initramfs_async=false rootwait debug loglevel=8 earlyprintk nohlt";
+
+ // SSD root, a {zone_name}-disk.ext4 virtio blk file on SSD root_hvisor partition
+ // bootargs = "earlycon console=ttyS0,115200n8 rootwait root=/dev/vda rw";
+ };
+
+ memory@200000 {
+ device_type = "memory";
+ reg = <0 0xa0200000 0 0x0ee00000
+ 0 0xb0000000 0 0x10000000
+ 0x1 0x40800000 0 0x800000
+ >;
+ };
+
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ shmem@0 {
+ no-map;
+ reg = <0x1 0x40800000 0 0x800000>;
+ };
+ };
+
+ msi: msi-controller@1fe01140 {
+ compatible = "loongson,pch-msi-1.0";
+ reg = <0x0 0x1fe01140 0x0 0x8>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ msi-controller;
+ loongson,msi-base-vec = <160>;
+ loongson,msi-num-vecs = <48>;// [64-111(48),112-159(48),160-207(48),208-255(48)]
+ interrupt-parent = <&eiointc>;
+ phandle = <0x8004>;
+ };
+
+ // virtio console
+ virtio_mmio@30001000 {
+ dma-coherent;
+ compatible = "virtio,mmio";
+ interrupt-parent = <&cpuintc>;
+ interrupts = <4>;// = hwirq
+ reg = <0x0 0x30001000 0x0 0x200>;
+ status = "okay";
+ };
+ // virtio blk
+ virtio_mmio@30002000 {
+ dma-coherent;
+ compatible = "virtio,mmio";
+ // interrupt-parent = <&cpuintc>;
+ // interrupts = <5>;// = hwirq
+ interrupt-parent = <&cpuintc>;
+ interrupts = <5>;// = hwirq
+ reg = <0x0 0x30002000 0x0 0x200>;
+ status = "okay";
+ };
+
+ pcie@1a000000 {
+ compatible = "loongson,ls7a-pci";
+
+ // configuration space
+ reg =
+ <0x00 0x1a000000 0x0 0x20000000>,
+ <0xfe 0x00000000 0x0 0x20000000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ msi-parent = <&msi>;
+ bus-range = <0x0 0xff>;
+
+ // PCIe resources
+ ranges =
+ <0x01000000 0x0 0x00008000 0x0 0x18408000 0x0 0x00008000>,// 0x01000000 (IO) [PCIe space base address][CPU space address][size]
+ <0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>;// 0x02000000 (MEM) [PCIe space base address][CPU space address][size]
+
+ // interrputs
+ interrupt-map-mask = <0xff00 0x00 0x00 0x7>;
+ interrupt-map =
+ <
+ 0x1800 0x00 0x00 0x01 0x8003 12 IRQ_TYPE_LEVEL_HIGH// 3,0 a
+ 0x1800 0x00 0x00 0x02 0x8003 13 IRQ_TYPE_LEVEL_HIGH// 3,0 b
+
+ 0x2000 0x00 0x00 0x01 0x8003 49 IRQ_TYPE_LEVEL_HIGH// 4,0 a
+ 0x2100 0x00 0x00 0x01 0x8003 48 IRQ_TYPE_LEVEL_HIGH// 4,1 b
+
+ 0x2800 0x00 0x00 0x01 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 a
+ 0x2800 0x00 0x00 0x02 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 b
+ 0x2800 0x00 0x00 0x03 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 c
+ 0x2800 0x00 0x00 0x04 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 d
+
+ 0x2900 0x00 0x00 0x01 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 a
+ 0x2900 0x00 0x00 0x02 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 b
+ 0x2900 0x00 0x00 0x03 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 c
+ 0x2900 0x00 0x00 0x04 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 d
+
+ 0x3000 0x00 0x00 0x01 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 a
+ 0x3000 0x00 0x00 0x02 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 b
+ 0x3000 0x00 0x00 0x03 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 c
+ 0x3000 0x00 0x00 0x04 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 d
+
+ 0x3100 0x00 0x00 0x01 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 a
+ 0x3100 0x00 0x00 0x02 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 b
+ 0x3100 0x00 0x00 0x03 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 c
+ 0x3100 0x00 0x00 0x04 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 d
+
+ 0x3200 0x00 0x00 0x01 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 a
+ 0x3200 0x00 0x00 0x02 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 b
+ 0x3200 0x00 0x00 0x03 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 c
+ 0x3200 0x00 0x00 0x04 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 d
+
+ 0x3800 0x00 0x00 0x01 0x8003 78 IRQ_TYPE_LEVEL_HIGH// 7,0 a
+ 0x3800 0x00 0x00 0x02 0x8003 79 IRQ_TYPE_LEVEL_HIGH// 7,0 b
+
+ 0x4000 0x00 0x00 0x01 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 a
+ 0x4000 0x00 0x00 0x02 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 b
+ 0x4000 0x00 0x00 0x03 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 c
+ 0x4000 0x00 0x00 0x04 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 d
+
+ 0x4800 0x00 0x00 0x01 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 a
+ 0x4800 0x00 0x00 0x02 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 b
+ 0x4800 0x00 0x00 0x03 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 c
+ 0x4800 0x00 0x00 0x04 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 d
+
+ 0x5000 0x00 0x00 0x01 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 a
+ 0x5000 0x00 0x00 0x02 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 b
+ 0x5000 0x00 0x00 0x03 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 c
+ 0x5000 0x00 0x00 0x04 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 d
+
+ 0x5800 0x00 0x00 0x01 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 a
+ 0x5800 0x00 0x00 0x02 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 b
+ 0x5800 0x00 0x00 0x03 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 c
+ 0x5800 0x00 0x00 0x04 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 d
+
+ 0x6000 0x00 0x00 0x01 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 a
+ 0x6000 0x00 0x00 0x02 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 b
+ 0x6000 0x00 0x00 0x03 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 c
+ 0x6000 0x00 0x00 0x04 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 d
+
+ 0x6800 0x00 0x00 0x01 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 a
+ 0x6800 0x00 0x00 0x02 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 b
+ 0x6800 0x00 0x00 0x03 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 c
+ 0x6800 0x00 0x00 0x04 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 d
+
+ 0x7000 0x00 0x00 0x01 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 a
+ 0x7000 0x00 0x00 0x02 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 b
+ 0x7000 0x00 0x00 0x03 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 c
+ 0x7000 0x00 0x00 0x04 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 d
+
+ 0x7800 0x00 0x00 0x01 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 a
+ 0x7800 0x00 0x00 0x02 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 b
+ 0x7800 0x00 0x00 0x03 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 c
+ 0x7800 0x00 0x00 0x04 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 d
+
+ 0x8000 0x00 0x00 0x01 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 a
+ 0x8000 0x00 0x00 0x02 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 b
+ 0x8000 0x00 0x00 0x03 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 c
+ 0x8000 0x00 0x00 0x04 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 d
+
+ 0x9800 0x00 0x00 0x01 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 a
+ 0x9800 0x00 0x00 0x02 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 b
+ 0x9800 0x00 0x00 0x03 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 c
+ 0x9800 0x00 0x00 0x04 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 d
+
+ 0xa000 0x00 0x00 0x01 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 a
+ 0xa000 0x00 0x00 0x02 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 b
+ 0xa000 0x00 0x00 0x03 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 c
+ 0xa000 0x00 0x00 0x04 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 d
+
+ 0xb800 0x00 0x00 0x01 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 a
+ 0xb800 0x00 0x00 0x02 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 b
+ 0xb800 0x00 0x00 0x03 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 c
+ 0xb800 0x00 0x00 0x04 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 d
+
+ 0xc800 0x00 0x00 0x01 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 a
+ 0xc800 0x00 0x00 0x02 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 b
+ 0xc800 0x00 0x00 0x03 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 c
+ 0xc800 0x00 0x00 0x04 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 d
+ >;
+
+ #interrupt-cells = <0x01>;
+ };
+};
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a5000/image/dts/zone3-linux.dts b/platform/loongarch64/ls3a5000/image/dts/zone3-linux.dts
new file mode 100644
index 00000000..376995aa
--- /dev/null
+++ b/platform/loongarch64/ls3a5000/image/dts/zone3-linux.dts
@@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+* Copyright (C) 2023 Loongson Technology Corporation Limited
+* Modified for hvisor by wheatfox(wheatfox17@icloud.com) syswonder.org 2024
+*/
+
+/dts-v1/;
+
+#include "loongson-3a5000.dtsi"
+
+
+&uart1 {
+ status = "okay";
+ // set the above 'uart1' to 'uart0' if you don't have a COM connection right now
+};
+
+
+/ {
+ compatible = "loongson,ls3a5000-root", "loongson,ls3a5000";
+ model = "Loongson3 hvisor nonroot zone board";
+
+ aliases {
+ serial = &uart1;
+ };
+
+ chosen {
+ // initramfs
+ bootargs = "earlycon console=ttyS0,115200n8 initramfs_async=false rootwait debug loglevel=8 earlyprintk nohlt";
+
+ // SSD root, a {zone_name}-disk.ext4 virtio blk file on SSD root_hvisor partition
+ // bootargs = "earlycon console=ttyS0,115200n8 rootwait root=/dev/vda rw";
+ };
+
+ memory@200000 {
+ device_type = "memory";
+ reg = <0x1 0x00200000 0 0x0ee00000
+ 0x1 0x10000000 0 0x10000000
+ 0x1 0x41000000 0 0x800000
+ >;
+ };
+
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ shmem@0 {
+ no-map;
+ reg = <0x1 0x41000000 0 0x800000>;
+ };
+ };
+
+ msi: msi-controller@1fe01140 {
+ compatible = "loongson,pch-msi-1.0";
+ reg = <0x0 0x1fe01140 0x0 0x8>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ msi-controller;
+ loongson,msi-base-vec = <208>;
+ loongson,msi-num-vecs = <48>;// [64-111(48),112-159(48),160-207(48),208-255(48)]
+ interrupt-parent = <&eiointc>;
+ phandle = <0x8004>;
+ };
+
+ // virtio console
+ virtio_mmio@30001000 {
+ dma-coherent;
+ compatible = "virtio,mmio";
+ interrupt-parent = <&cpuintc>;
+ interrupts = <4>;// = hwirq
+ reg = <0x0 0x30001000 0x0 0x200>;
+ status = "okay";
+ };
+ // virtio blk
+ virtio_mmio@30002000 {
+ dma-coherent;
+ compatible = "virtio,mmio";
+ // interrupt-parent = <&cpuintc>;
+ // interrupts = <5>;// = hwirq
+ interrupt-parent = <&cpuintc>;
+ interrupts = <5>;// = hwirq
+ reg = <0x0 0x30002000 0x0 0x200>;
+ status = "okay";
+ };
+
+ pcie@1a000000 {
+ compatible = "loongson,ls7a-pci";
+
+ // configuration space
+ reg =
+ <0x00 0x1a000000 0x0 0x20000000>,
+ <0xfe 0x00000000 0x0 0x20000000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ msi-parent = <&msi>;
+ bus-range = <0x0 0xff>;
+
+ // PCIe resources
+ ranges =
+ <0x01000000 0x0 0x00008000 0x0 0x18408000 0x0 0x00008000>,// 0x01000000 (IO) [PCIe space base address][CPU space address][size]
+ <0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>;// 0x02000000 (MEM) [PCIe space base address][CPU space address][size]
+
+ // interrputs
+ interrupt-map-mask = <0xff00 0x00 0x00 0x7>;
+ interrupt-map =
+ <
+ 0x1800 0x00 0x00 0x01 0x8003 12 IRQ_TYPE_LEVEL_HIGH// 3,0 a
+ 0x1800 0x00 0x00 0x02 0x8003 13 IRQ_TYPE_LEVEL_HIGH// 3,0 b
+
+ 0x2000 0x00 0x00 0x01 0x8003 49 IRQ_TYPE_LEVEL_HIGH// 4,0 a
+ 0x2100 0x00 0x00 0x01 0x8003 48 IRQ_TYPE_LEVEL_HIGH// 4,1 b
+
+ 0x2800 0x00 0x00 0x01 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 a
+ 0x2800 0x00 0x00 0x02 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 b
+ 0x2800 0x00 0x00 0x03 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 c
+ 0x2800 0x00 0x00 0x04 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 d
+
+ 0x2900 0x00 0x00 0x01 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 a
+ 0x2900 0x00 0x00 0x02 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 b
+ 0x2900 0x00 0x00 0x03 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 c
+ 0x2900 0x00 0x00 0x04 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 d
+
+ 0x3000 0x00 0x00 0x01 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 a
+ 0x3000 0x00 0x00 0x02 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 b
+ 0x3000 0x00 0x00 0x03 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 c
+ 0x3000 0x00 0x00 0x04 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 d
+
+ 0x3100 0x00 0x00 0x01 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 a
+ 0x3100 0x00 0x00 0x02 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 b
+ 0x3100 0x00 0x00 0x03 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 c
+ 0x3100 0x00 0x00 0x04 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 d
+
+ 0x3200 0x00 0x00 0x01 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 a
+ 0x3200 0x00 0x00 0x02 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 b
+ 0x3200 0x00 0x00 0x03 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 c
+ 0x3200 0x00 0x00 0x04 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 d
+
+ 0x3800 0x00 0x00 0x01 0x8003 78 IRQ_TYPE_LEVEL_HIGH// 7,0 a
+ 0x3800 0x00 0x00 0x02 0x8003 79 IRQ_TYPE_LEVEL_HIGH// 7,0 b
+
+ 0x4000 0x00 0x00 0x01 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 a
+ 0x4000 0x00 0x00 0x02 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 b
+ 0x4000 0x00 0x00 0x03 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 c
+ 0x4000 0x00 0x00 0x04 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 d
+
+ 0x4800 0x00 0x00 0x01 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 a
+ 0x4800 0x00 0x00 0x02 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 b
+ 0x4800 0x00 0x00 0x03 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 c
+ 0x4800 0x00 0x00 0x04 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 d
+
+ 0x5000 0x00 0x00 0x01 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 a
+ 0x5000 0x00 0x00 0x02 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 b
+ 0x5000 0x00 0x00 0x03 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 c
+ 0x5000 0x00 0x00 0x04 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 d
+
+ 0x5800 0x00 0x00 0x01 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 a
+ 0x5800 0x00 0x00 0x02 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 b
+ 0x5800 0x00 0x00 0x03 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 c
+ 0x5800 0x00 0x00 0x04 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 d
+
+ 0x6000 0x00 0x00 0x01 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 a
+ 0x6000 0x00 0x00 0x02 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 b
+ 0x6000 0x00 0x00 0x03 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 c
+ 0x6000 0x00 0x00 0x04 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 d
+
+ 0x6800 0x00 0x00 0x01 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 a
+ 0x6800 0x00 0x00 0x02 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 b
+ 0x6800 0x00 0x00 0x03 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 c
+ 0x6800 0x00 0x00 0x04 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 d
+
+ 0x7000 0x00 0x00 0x01 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 a
+ 0x7000 0x00 0x00 0x02 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 b
+ 0x7000 0x00 0x00 0x03 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 c
+ 0x7000 0x00 0x00 0x04 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 d
+
+ 0x7800 0x00 0x00 0x01 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 a
+ 0x7800 0x00 0x00 0x02 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 b
+ 0x7800 0x00 0x00 0x03 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 c
+ 0x7800 0x00 0x00 0x04 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 d
+
+ 0x8000 0x00 0x00 0x01 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 a
+ 0x8000 0x00 0x00 0x02 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 b
+ 0x8000 0x00 0x00 0x03 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 c
+ 0x8000 0x00 0x00 0x04 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 d
+
+ 0x9800 0x00 0x00 0x01 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 a
+ 0x9800 0x00 0x00 0x02 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 b
+ 0x9800 0x00 0x00 0x03 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 c
+ 0x9800 0x00 0x00 0x04 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 d
+
+ 0xa000 0x00 0x00 0x01 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 a
+ 0xa000 0x00 0x00 0x02 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 b
+ 0xa000 0x00 0x00 0x03 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 c
+ 0xa000 0x00 0x00 0x04 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 d
+
+ 0xb800 0x00 0x00 0x01 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 a
+ 0xb800 0x00 0x00 0x02 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 b
+ 0xb800 0x00 0x00 0x03 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 c
+ 0xb800 0x00 0x00 0x04 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 d
+
+ 0xc800 0x00 0x00 0x01 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 a
+ 0xc800 0x00 0x00 0x02 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 b
+ 0xc800 0x00 0x00 0x03 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 c
+ 0xc800 0x00 0x00 0x04 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 d
+ >;
+
+ #interrupt-cells = <0x01>;
+ };
+};
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a5000/platform.mk b/platform/loongarch64/ls3a5000/platform.mk
index 2121f29b..e2abe865 100644
--- a/platform/loongarch64/ls3a5000/platform.mk
+++ b/platform/loongarch64/ls3a5000/platform.mk
@@ -1,5 +1,5 @@
# hvisor for loongarch64 makefile
-# wheatfox(enkerewpo@hotmail.com) 2024.6
+# wheatfox(wheatfox17@icloud.com) 2024.6
# HVISOR ENTRY
HVISOR_ENTRY_PA := 0x9000000080000000
diff --git a/platform/loongarch64/ls3a6000/.gitkeep b/platform/loongarch64/ls3a6000/.gitkeep
deleted file mode 100644
index e69de29b..00000000
diff --git a/platform/loongarch64/ls3a6000/board.rs b/platform/loongarch64/ls3a6000/board.rs
new file mode 100644
index 00000000..184dc110
--- /dev/null
+++ b/platform/loongarch64/ls3a6000/board.rs
@@ -0,0 +1,216 @@
+// Copyright (c) 2025 Syswonder
+// hvisor is licensed under Mulan PSL v2.
+// You can use this software according to the terms and conditions of the Mulan PSL v2.
+// You may obtain a copy of Mulan PSL v2 at:
+// http://license.coscl.org.cn/MulanPSL2
+// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+// FIT FOR A PARTICULAR PURPOSE.
+// See the Mulan PSL v2 for more details.
+//
+// Syswonder Website:
+// https://www.syswonder.org
+//
+// Authors:
+// Yulong Han
+//
+use crate::{arch::zone::HvArchZoneConfig, config::*};
+
+pub const BOARD_NAME: &str = "ls3a5000";
+
+pub const BOARD_NCPUS: usize = 4;
+
+pub const ROOT_ZONE_DTB_ADDR: u64 = 0x10000f000;
+pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x200000;
+pub const ROOT_ZONE_ENTRY: u64 = 0x9000000000d8c000;
+pub const ROOT_ZONE_CPUS: u64 = 1 << 0;
+
+pub const ROOT_ZONE_NAME: &str = "root-linux-la64";
+
+pub const ROOT_ZONE_MEMORY_REGIONS: &[HvConfigMemoryRegion] = &[
+ /* memory regions */
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_RAM,
+ physical_start: 0x00200000,
+ virtual_start: 0x00200000,
+ size: 0x0ee00000,
+ }, // ram
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_RAM,
+ physical_start: 0x90000000,
+ virtual_start: 0x90000000,
+ size: 0x10000000,
+ }, // ram
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_RAM,
+ physical_start: 0xf000_0000,
+ virtual_start: 0xf000_0000,
+ size: 0x1000_0000,
+ }, // ram
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_RAM,
+ physical_start: 0x1_6000_0000,
+ virtual_start: 0x1_6000_0000,
+ size: 0x1000_0000,
+ }, // linux0
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_RAM,
+ physical_start: 0xc000_0000,
+ virtual_start: 0xc000_0000,
+ size: 0x3000_0000,
+ }, // linux1
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_RAM,
+ physical_start: 0xa000_0000,
+ virtual_start: 0xa000_0000,
+ size: 0x2000_0000,
+ }, // linux2
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_RAM,
+ physical_start: 0x1_0000_0000,
+ virtual_start: 0x1_0000_0000,
+ size: 0x2000_0000,
+ }, // linux3
+ /* devices and controllers */
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x1fe00000,
+ virtual_start: 0x1fe00000,
+ size: 0x1000,
+ }, // uart0
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x10080000,
+ virtual_start: 0x10080000,
+ size: 0x1000,
+ }, // uart1, passthrough now
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x100d0000,
+ virtual_start: 0x100d0000,
+ size: 0x1000,
+ }, // rtc, passthrough now
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x10000000,
+ virtual_start: 0x10000000,
+ size: 0x1000,
+ }, // pch-pic irq controller
+ /* PCI related stuffs ... */
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x1a000000,
+ // virtual_start: 0x1a000000,
+ // size: 0x02000000,
+ // }, // pci
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0xefe_0000_0000,
+ // virtual_start: 0xfe_0000_0000,
+ // size: 0x20000000,
+ // }, // pci config space (HT)
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x18408000,
+ // virtual_start: 0x18408000,
+ // size: 0x00008000,
+ // }, // pci io resource
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x60000000,
+ // virtual_start: 0x60000000,
+ // size: 0x20000000,
+ // }, // pci mem resource
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x1001_0000,
+ virtual_start: 0x1001_0000,
+ size: 0x0001_0000,
+ }, // ?
+ /* map special regions - 2024.4.12 */
+ // linux's strscpy called gpa at 0x9000_0000_0000_0000 which is ldx x, 0x9000_0000_0000_0000(a1) + 0x0(a0) why ?
+ // __memcpy_fromio 0xf0000 why?
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_RAM,
+ physical_start: 0x1000,
+ virtual_start: 0x0,
+ size: 0x10000,
+ }, // 0x0
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_RAM,
+ physical_start: 0xf0000,
+ virtual_start: 0xf0000,
+ size: 0x10000,
+ }, // 0xf0000
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_RAM,
+ physical_start: 0x1_4000_0000,
+ virtual_start: 0x1_4000_0000,
+ size: 0x80_0000, // linux1-root
+ }, // SHARD_MEM
+];
+
+pub const ROOT_ZONE_IRQS: [u32; 0] = [];
+pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { dummy: 0 };
+pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = [];
+
+pub const ROOT_PCI_CONFIG: HvPciConfig = HvPciConfig {
+ ecam_base: 0xfe00000000,
+ ecam_size: 0x20000000,
+ io_base: 0x18408000,
+ io_size: 0x8000,
+ pci_io_base: 0x00008000,
+ mem32_base: 0x0,
+ mem32_size: 0x0,
+ pci_mem32_base: 0x0,
+ mem64_base: 0x60000000,
+ mem64_size: 0x20000000,
+ pci_mem64_base: 0x60000000,
+};
+
+/* 00:00.0, 00:00.1, 00:00.2, 00:00.3, 00:04.0, 00:04.1*/
+/* 00:05.0, 00:05.1, 00:06.0, 00:06.1, 00:06.2 */
+/* 00:07.0, 00:08.0, 00:09.0, 00:0a.0, 00:0b.0 */
+/* 00:0c.0, 00:0d.0, 00:0f.0, 00:10.0, 00:13.0 */
+/* 00:16.0, 00:19.0, 02:00.0, 05:00.0 */
+/* BUS 8 on X16 slot */
+/* 08:00.0, 08:00.1, 08:00.2, 08:00.3 net */
+/* BUS 6 on X4 slot */
+/* 06:00.0, 06:00.1, 06:00.2, 06:00.3 net */
+pub const ROOT_PCI_DEVS: [u64; 26] = [
+ 0,
+ 1,
+ 2,
+ 3,
+ 4 << 3,
+ (4 << 3) + 1,
+ 5 << 3,
+ (5 << 3) + 1,
+ // 00:06.xx is VGA and Graphics card
+ (6 << 3),
+ (6 << 3) + 1,
+ (6 << 3) + 2,
+ 7 << 3,
+ 8 << 3, // bus 0 device 8: AHCI
+ 9 << 3,
+ 0xa << 3,
+ 0xb << 3,
+ 0xc << 3,
+ 0xd << 3,
+ 0xf << 3,
+ 0x10 << 3,
+ 0x13 << 3,
+ 0x16 << 3,
+ 0x19 << 3,
+ 2 << 8,
+ 5 << 8,
+ // bus 6 (x4 slot) is PCIe network card
+ // (8 << 8), // bus 8 net
+ (6 << 8), // bus 6 net
+];
+
+// bus << 8 | dev << 5 | func << 3
+
+// pub const ROOT_PCI_DEVS: [u64; 0] = [];
+
+// "alloc_pci_devs": [0,1,2,3,32,33,40,41,56,64,72,80,88,96,104,120,128,152,176,200,512,1280,2051]
diff --git a/platform/loongarch64/ls3a6000/cargo/config.template.toml b/platform/loongarch64/ls3a6000/cargo/config.template.toml
new file mode 100644
index 00000000..5f7fa378
--- /dev/null
+++ b/platform/loongarch64/ls3a6000/cargo/config.template.toml
@@ -0,0 +1,6 @@
+[target.loongarch64-unknown-none]
+linker = "loongarch64-unknown-linux-gnu-gcc"
+rustflags = [
+ "-Clink-arg=-Tplatform/__ARCH__/__BOARD__/linker.ld",
+ "-Cforce-frame-pointers=yes",
+]
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a6000/cargo/features b/platform/loongarch64/ls3a6000/cargo/features
new file mode 100644
index 00000000..e2e853ee
--- /dev/null
+++ b/platform/loongarch64/ls3a6000/cargo/features
@@ -0,0 +1,4 @@
+loongson_3a6000
+loongson_7a2000
+loongson_uart
+pci
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a6000/configs/virtio.json b/platform/loongarch64/ls3a6000/configs/virtio.json
new file mode 100644
index 00000000..488affaf
--- /dev/null
+++ b/platform/loongarch64/ls3a6000/configs/virtio.json
@@ -0,0 +1,100 @@
+{
+ "zones": [
+ {
+ "id": 1,
+ "memory_region": [
+ {
+ "zone0_ipa": "0xc0000000",
+ "zonex_ipa": "0xc0000000",
+ "size": "0x10000000"
+ },
+ {
+ "zone0_ipa": "0xd0000000",
+ "zonex_ipa": "0xd0000000",
+ "size": "0x10000000"
+ }
+ ],
+ "devices": [
+ {
+ "type": "console",
+ "addr": "0x30001000",
+ "len": "0x200",
+ "irq": 4,
+ "status": "enable"
+ },
+ {
+ "type": "blk",
+ "addr": "0x30002000",
+ "len": "0x200",
+ "irq": 5,
+ "img": "/tool/linux1-disk.ext4",
+ "status": "enable"
+ }
+ ]
+ },
+ {
+ "id": 2,
+ "memory_region": [
+ {
+ "zone0_ipa": "0xa0000000",
+ "zonex_ipa": "0xa0000000",
+ "size": "0x10000000"
+ },
+ {
+ "zone0_ipa": "0xb0000000",
+ "zonex_ipa": "0xb0000000",
+ "size": "0x10000000"
+ }
+ ],
+ "devices": [
+ {
+ "type": "console",
+ "addr": "0x30001000",
+ "len": "0x200",
+ "irq": 4,
+ "status": "enable"
+ },
+ {
+ "type": "blk",
+ "addr": "0x30002000",
+ "len": "0x200",
+ "irq": 5,
+ "img": "/tool/linux2-disk.ext4",
+ "status": "enable"
+ }
+ ]
+ },
+ {
+ "id": 3,
+ "memory_region": [
+ {
+ "zone0_ipa": "0x100000000",
+ "zonex_ipa": "0x100000000",
+ "size": "0x10000000"
+ },
+ {
+ "zone0_ipa": "0x110000000",
+ "zonex_ipa": "0x110000000",
+ "size": "0x10000000"
+ }
+ ],
+ "devices": [
+ {
+ "type": "console",
+ "addr": "0x30001000",
+ "len": "0x200",
+ "irq": 4,
+ "status": "enable"
+ },
+ {
+ "type": "blk",
+ "addr": "0x30002000",
+ "len": "0x200",
+ "irq": 5,
+ "img": "/tool/linux3-disk.ext4",
+ "status": "enable"
+ }
+ ]
+ }
+ ]
+}
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a6000/configs/zone1-linux.json b/platform/loongarch64/ls3a6000/configs/zone1-linux.json
new file mode 100644
index 00000000..e56d3424
--- /dev/null
+++ b/platform/loongarch64/ls3a6000/configs/zone1-linux.json
@@ -0,0 +1,129 @@
+{
+ "arch": "loongarch64",
+ "name": "linux1",
+ "zone_id": 1,
+ "cpus": [
+ 1
+ ],
+ "memory_regions": [
+ {
+ "type": "ram",
+ "physical_start": "0xc0000000",
+ "virtual_start": "0xc0000000",
+ "size": "0x10000000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0xd0000000",
+ "virtual_start": "0xd0000000",
+ "size": "0x10000000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x1fe00000",
+ "virtual_start": "0x1fe00000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x10080000",
+ "virtual_start": "0x10080000",
+ "size": "0x1000"
+ },
+ {
+ "type": "virtio",
+ "physical_start": "0x30001000",
+ "virtual_start": "0x30001000",
+ "size": "0x200"
+ },
+ {
+ "type": "virtio",
+ "physical_start": "0x30002000",
+ "virtual_start": "0x30002000",
+ "size": "0x200"
+ },
+ {
+ "type": "io",
+ "physical_start": "0xffffffff0000",
+ "virtual_start": "0xffffffff0000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x10000000",
+ "virtual_start": "0x10000000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x100d0000",
+ "virtual_start": "0x100d0000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x10010000",
+ "virtual_start": "0x10010000",
+ "size": "0x00010000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0x1000",
+ "virtual_start": "0x0",
+ "size": "0x10000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0xf0000",
+ "virtual_start": "0xf0000",
+ "size": "0x10000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0x140000000",
+ "virtual_start": "0x140000000",
+ "size": "0x800000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0x140800000",
+ "virtual_start": "0x140800000",
+ "size": "0x800000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0x141000000",
+ "virtual_start": "0x141000000",
+ "size": "0x800000"
+ }
+ ],
+ "interrupts": [
+ 4,
+ 5
+ ],
+ "ivc_configs": [],
+ "kernel_args": "NOT_USED_YET",
+ "kernel_filepath": "/tool/nonroot/vmlinux-linux1.bin",
+ "dtb_filepath": "/tool/test.bin",
+ "kernel_load_paddr": "0xc0200000",
+ "dtb_load_paddr": "0xc0000000",
+ "entry_point": "0x90000000c0dff000",
+ "arch_config": {
+ "dummy": "0x1234"
+ },
+ "pci_config": {
+ "ecam_base": "0xfe00000000",
+ "ecam_size": "0x20000000",
+ "io_base": "0x18408000",
+ "io_size": "0x8000",
+ "pci_io_base": "0x00008000",
+ "mem32_base": "0x0",
+ "mem32_size": "0x0",
+ "pci_mem32_base": "0x0",
+ "mem64_base": "0x60000000",
+ "mem64_size": "0x20000000",
+ "pci_mem64_base": "0x60000000"
+ },
+ "num_pci_devs": 1,
+ "alloc_pci_devs": [1537]
+}
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a6000/configs/zone2-linux.json b/platform/loongarch64/ls3a6000/configs/zone2-linux.json
new file mode 100644
index 00000000..8255f01e
--- /dev/null
+++ b/platform/loongarch64/ls3a6000/configs/zone2-linux.json
@@ -0,0 +1,117 @@
+{
+ "arch": "loongarch64",
+ "name": "linux2",
+ "zone_id": 2,
+ "cpus": [
+ 2
+ ],
+ "memory_regions": [
+ {
+ "type": "ram",
+ "physical_start": "0xa0000000",
+ "virtual_start": "0xa0000000",
+ "size": "0x10000000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0xb0000000",
+ "virtual_start": "0xb0000000",
+ "size": "0x10000000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x1fe00000",
+ "virtual_start": "0x1fe00000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x10080000",
+ "virtual_start": "0x10080000",
+ "size": "0x1000"
+ },
+ {
+ "type": "virtio",
+ "physical_start": "0x30001000",
+ "virtual_start": "0x30001000",
+ "size": "0x200"
+ },
+ {
+ "type": "virtio",
+ "physical_start": "0x30002000",
+ "virtual_start": "0x30002000",
+ "size": "0x200"
+ },
+ {
+ "type": "io",
+ "physical_start": "0xffffffff0000",
+ "virtual_start": "0xffffffff0000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x10000000",
+ "virtual_start": "0x10000000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x100d0000",
+ "virtual_start": "0x100d0000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x10010000",
+ "virtual_start": "0x10010000",
+ "size": "0x00010000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0x1000",
+ "virtual_start": "0x0",
+ "size": "0x10000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0xf0000",
+ "virtual_start": "0xf0000",
+ "size": "0x10000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0x140800000",
+ "virtual_start": "0x140800000",
+ "size": "0x800000"
+ }
+ ],
+ "interrupts": [
+ 4,
+ 5
+ ],
+ "ivc_configs": [],
+ "kernel_args": "NOT_USED_YET",
+ "kernel_filepath": "/tool/nonroot/vmlinux-linux2.bin",
+ "dtb_filepath": "/tool/test.bin",
+ "kernel_load_paddr": "0xa0200000",
+ "dtb_load_paddr": "0xa0000000",
+ "entry_point": "0x90000000a0dff000",
+ "arch_config": {
+ "dummy": "0x1234"
+ },
+ "pci_config": {
+ "ecam_base": "0xfe00000000",
+ "ecam_size": "0x20000000",
+ "io_base": "0x18408000",
+ "io_size": "0x8000",
+ "pci_io_base": "0x00008000",
+ "mem32_base": "0x0",
+ "mem32_size": "0x0",
+ "pci_mem32_base": "0x0",
+ "mem64_base": "0x60000000",
+ "mem64_size": "0x20000000",
+ "pci_mem64_base": "0x60000000"
+ },
+ "num_pci_devs": 1,
+ "alloc_pci_devs": [1538]
+}
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a6000/configs/zone3-linux.json b/platform/loongarch64/ls3a6000/configs/zone3-linux.json
new file mode 100644
index 00000000..fcb03239
--- /dev/null
+++ b/platform/loongarch64/ls3a6000/configs/zone3-linux.json
@@ -0,0 +1,117 @@
+{
+ "arch": "loongarch64",
+ "name": "linux3",
+ "zone_id": 3,
+ "cpus": [
+ 3
+ ],
+ "memory_regions": [
+ {
+ "type": "ram",
+ "physical_start": "0x100000000",
+ "virtual_start": "0x100000000",
+ "size": "0x10000000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0x110000000",
+ "virtual_start": "0x110000000",
+ "size": "0x10000000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x1fe00000",
+ "virtual_start": "0x1fe00000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x10080000",
+ "virtual_start": "0x10080000",
+ "size": "0x1000"
+ },
+ {
+ "type": "virtio",
+ "physical_start": "0x30001000",
+ "virtual_start": "0x30001000",
+ "size": "0x200"
+ },
+ {
+ "type": "virtio",
+ "physical_start": "0x30002000",
+ "virtual_start": "0x30002000",
+ "size": "0x200"
+ },
+ {
+ "type": "io",
+ "physical_start": "0xffffffff0000",
+ "virtual_start": "0xffffffff0000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x10000000",
+ "virtual_start": "0x10000000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x100d0000",
+ "virtual_start": "0x100d0000",
+ "size": "0x1000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x10010000",
+ "virtual_start": "0x10010000",
+ "size": "0x00010000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0x1000",
+ "virtual_start": "0x0",
+ "size": "0x10000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0xf0000",
+ "virtual_start": "0xf0000",
+ "size": "0x10000"
+ },
+ {
+ "type": "ram",
+ "physical_start": "0x141000000",
+ "virtual_start": "0x141000000",
+ "size": "0x800000"
+ }
+ ],
+ "interrupts": [
+ 4,
+ 5
+ ],
+ "ivc_configs": [],
+ "kernel_args": "NOT_USED_YET",
+ "kernel_filepath": "/tool/nonroot/vmlinux-linux3.bin",
+ "dtb_filepath": "/tool/test.bin",
+ "kernel_load_paddr": "0x100200000",
+ "dtb_load_paddr": "0x100000000",
+ "entry_point": "0x9000000100dff000",
+ "arch_config": {
+ "dummy": "0x1234"
+ },
+ "pci_config": {
+ "ecam_base": "0xfe00000000",
+ "ecam_size": "0x20000000",
+ "io_base": "0x18408000",
+ "io_size": "0x8000",
+ "pci_io_base": "0x00008000",
+ "mem32_base": "0x0",
+ "mem32_size": "0x0",
+ "pci_mem32_base": "0x0",
+ "mem64_base": "0x60000000",
+ "mem64_size": "0x20000000",
+ "pci_mem64_base": "0x60000000"
+ },
+ "num_pci_devs": 1,
+ "alloc_pci_devs": [1539]
+}
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a6000/image/dts/Makefile b/platform/loongarch64/ls3a6000/image/dts/Makefile
new file mode 100644
index 00000000..ed0d0749
--- /dev/null
+++ b/platform/loongarch64/ls3a6000/image/dts/Makefile
@@ -0,0 +1,14 @@
+DTS_FILES := $(wildcard *.dts)
+DTB_FILES := $(DTS_FILES:.dts=.dtb)
+
+all: $(DTB_FILES)
+
+%.dts.1: %.dts
+# preprocess all includes into a single dts with suffix .1
+ cpp -I include -nostdinc -E -x assembler-with-cpp $< > $@
+
+%.dtb: %.dts.1
+ dtc -I dts -O dtb $< -o $@
+
+clean:
+ rm -f $(DTB_FILES)
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a6000/image/dts/include/irq.h b/platform/loongarch64/ls3a6000/image/dts/include/irq.h
new file mode 100644
index 00000000..9e3d183e
--- /dev/null
+++ b/platform/loongarch64/ls3a6000/image/dts/include/irq.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * This header provides constants for most IRQ bindings.
+ *
+ * Most IRQ bindings include a flags cell as part of the IRQ specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
+
+#define IRQ_TYPE_NONE 0
+#define IRQ_TYPE_EDGE_RISING 1
+#define IRQ_TYPE_EDGE_FALLING 2
+#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
+#define IRQ_TYPE_LEVEL_HIGH 4
+#define IRQ_TYPE_LEVEL_LOW 8
+
+#endif
diff --git a/platform/loongarch64/ls3a6000/image/dts/include/loongson-3a5000.dtsi b/platform/loongarch64/ls3a6000/image/dts/include/loongson-3a5000.dtsi
new file mode 100644
index 00000000..3880aca0
--- /dev/null
+++ b/platform/loongarch64/ls3a6000/image/dts/include/loongson-3a5000.dtsi
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+* Copyright (C) 2023 Loongson Technology Corporation Limited
+*/
+
+/dts-v1/;
+
+// #include
+#include "irq.h"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "loongson,loongson3";
+ device_type = "cpu";
+ reg = <0x0>;
+ l2-cache = <&vcache0>;
+ next-level-cache = <&scache0>;
+ numa-node-id = <0>;
+ };
+ vcache0: l2-cache0 {
+ compatible = "cache";
+ next-level-cache = <&scache0>;
+ };
+ vcache1: l2-cache1 {
+ compatible = "cache";
+ next-level-cache = <&scache0>;
+ };
+ vcache2: l2-cache2 {
+ compatible = "cache";
+ next-level-cache = <&scache0>;
+ };
+ vcache3: l2-cache3 {
+ compatible = "cache";
+ next-level-cache = <&scache0>;
+ };
+ vcache4: l2-cache4 {
+ compatible = "cache";
+ next-level-cache = <&scache1>;
+ };
+ vcache5: l2-cache5 {
+ compatible = "cache";
+ next-level-cache = <&scache1>;
+ };
+ vcache6: l2-cache6 {
+ compatible = "cache";
+ next-level-cache = <&scache1>;
+ };
+ vcache7: l2-cache7 {
+ compatible = "cache";
+ next-level-cache = <&scache1>;
+ };
+ vcache8: l2-cache8 {
+ compatible = "cache";
+ next-level-cache = <&scache2>;
+ };
+ vcache9: l2-cache9 {
+ compatible = "cache";
+ next-level-cache = <&scache2>;
+ };
+ vcachea: l2-cachea {
+ compatible = "cache";
+ next-level-cache = <&scache2>;
+ };
+ vcacheb: l2-cacheb {
+ compatible = "cache";
+ next-level-cache = <&scache2>;
+ };
+ vcachec: l2-cachec {
+ compatible = "cache";
+ next-level-cache = <&scache3>;
+ };
+ vcached: l2-cached {
+ compatible = "cache";
+ next-level-cache = <&scache3>;
+ };
+ vcachee: l2-cachee {
+ compatible = "cache";
+ next-level-cache = <&scache3>;
+ };
+ vcachef: l2-cachef {
+ compatible = "cache";
+ next-level-cache = <&scache3>;
+ };
+ scache0: l3-cache0 {
+ compatible = "cache";
+ };
+ scache1: l3-cache1 {
+ compatible = "cache";
+ };
+ scache2: l3-cache2 {
+ compatible = "cache";
+ };
+ scache3: l3-cache3 {
+ compatible = "cache";
+ };
+ };
+};
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpuintc: interrupt-controller {
+ compatible = "loongson,cpu-interrupt-controller";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ phandle = <0x8001>;
+ };
+
+ board: platform {
+ compatible = "loongson,nbus", "simple-bus";
+
+ ranges = <
+ 0x00 0x10000000 0x00 0x10000000 0x00 0x10000000
+ 0x00 0x02000000 0x00 0x02000000 0x00 0x02000000
+ 0x00 0x20000000 0x00 0x20000000 0x00 0x10000000
+ 0x00 0x40000000 0x00 0x40000000 0x00 0x40000000
+ 0xfe 0x00000000 0xfe 0x00000000 0x00 0x40000000
+ >;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ // liointc: interrupt-controller@1fe01400 {
+ // compatible = "loongson,liointc-1.0";
+ // reg = <0x0 0x1fe01400 0x0 0x64>;
+ // interrupt-controller;
+ // #interrupt-cells = <2>;
+ // interrupt-parent = <&cpuintc>;
+ // interrupts = <2>;
+ // interrupt-names = "int0";
+ // loongson,parent_int_map =
+ // <0x00000000>, /* int0 */
+ // <0xffffffff>, /* int1 */
+ // <0x00000000>, /* int2 */
+ // <0x00000000>; /* int3 */
+ // };
+
+ eiointc: interrupt-controller@1fe01600 {
+ compatible = "loongson,ls2k2000-eiointc";
+ reg = <0x0 0x1fe01600 0x0 0xea00>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <3>;
+ phandle = <0x8002>;
+ // status = "disabled";
+ };
+
+ pic: interrupt-controller@10000000 {
+ compatible = "loongson,pch-pic-1.0";// Platform Controller Hub - Programmable Interrupt Controller
+ reg = <0x0 0x10000000 0x0 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ loongson,pic-base-vec = <0>;
+ interrupt-parent = <&eiointc>;
+ phandle = <0x8003>;
+ // status = "disabled";
+ };
+
+ // root's msi
+ // msi: msi-controller@1fe01140 {
+ // compatible = "loongson,pch-msi-1.0";
+ // reg = <0x0 0x1fe01140 0x0 0x8>;
+ // interrupt-controller;
+ // #interrupt-cells = <1>;
+ // msi-controller;
+ // loongson,msi-base-vec = <64>;
+ // loongson,msi-num-vecs = <48>; // [64-111(48),112-159(48),160-207(48),208-255(48)]
+ // interrupt-parent = <&eiointc>;
+ // phandle = <0x8004>;
+ // // status = "disabled";
+ // };
+
+ rtc0: rtc@100d0100 {
+ compatible = "loongson,ls7a-rtc";// Real Time Clock
+ reg = <0x0 0x100d0100 0x0 0x100>;
+ interrupt-parent = <&pic>;// pic-rtc0
+ interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
+ // status = "disabled";
+ };
+
+ ref_100m: clock-ref-100m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "ref_100m";
+ };
+
+ uart0: serial@1fe001e0 {
+ compatible = "ns16550a";
+ reg = <0x0 0x1fe001e0 0x0 0x100>;
+ clock-frequency = <100000000>;// 100M
+ // interrupt-parent = <&pic>;
+ // interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; // from ACPI ASL Interrupt number
+ // interrupt-parent = <&liointc>;
+ // interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ uart1: serial@10080000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x10080000 0x0 0x100>;
+ clock-frequency = <50000000>;// 50M (according to ACPI ASL)
+ interrupt-parent = <&pic>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ status = "disabled";
+ };
+ };
+};
diff --git a/platform/loongarch64/ls3a6000/image/dts/zone0.dts b/platform/loongarch64/ls3a6000/image/dts/zone0.dts
new file mode 100644
index 00000000..faa2cf4f
--- /dev/null
+++ b/platform/loongarch64/ls3a6000/image/dts/zone0.dts
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+* Copyright (C) 2023 Loongson Technology Corporation Limited
+* Modified for hvisor by wheatfox(wheatfox17@icloud.com) syswonder.org 2024
+*/
+
+/dts-v1/;
+
+#include "loongson-3a5000.dtsi"
+
+// if you changed this, remember to change the aliases at chosen/stdout-path
+&uart1 {
+ // status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/ {
+ compatible = "loongson,ls3a5000-root", "loongson,ls3a5000";
+ model = "Loongson3 hvisor root zone board";
+
+ aliases {
+ serial = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial:115200n8";
+
+ // initramfs
+ bootargs = "earlycon console=ttyS0,115200n8 initramfs_async=false rootwait debug nohlt";
+
+ // SSD root, on SSD partition 4 with ext4 format
+ // bootargs = "earlycon console=ttyS0,115200n8 root=/dev/nvme0n1p4 rootwait rw nohlt";
+ };
+
+ memory@200000 {
+ device_type = "memory";
+ reg = <
+ 0 0x00200000 0 0x0ee00000
+ 0 0x90000000 0 0x10000000
+
+ 0 0xc0000000 0 0x30000000
+ 0 0xa0000000 0 0x20000000
+
+ 0x1 0x00000000 0 0x20000000
+ 0x1 0x60000000 0 0x10000000
+
+ 0x1 0x40000000 0 0x800000
+
+ 0 0xf0000000 0 0x10000000
+ >;// the last part will alwarys be system ram! (with extra inneer reserved memory) so we have to add one extra region at the end.
+ };
+
+ hvisor_virtio_device {
+ compatible = "hvisor";
+ interrupt-parent = <&cpuintc>;
+ interrupts = <4>;
+ };
+
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ nonroot1 {
+ no-map;
+ reg = <0x00 0xc0000000 0x00 0x20000000>;
+ };
+ nonroot2 {
+ no-map;
+ reg = <0x00 0xa0000000 0x00 0x20000000>;
+ };
+ nonroot3 {
+ no-map;
+ reg = <0x01 0x00000000 0x00 0x20000000>;
+ };
+ shmem@0 {
+ no-map;
+ reg = <0x1 0x40000000 0 0x800000>;
+ };
+ };
+
+ msi: msi-controller@1fe01140 {
+ compatible = "loongson,pch-msi-1.0";
+ reg = <0x0 0x1fe01140 0x0 0x8>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ msi-controller;
+ loongson,msi-base-vec = <64>;
+ loongson,msi-num-vecs = <48>;// [64-111(48),112-159(48),160-207(48),208-255(48)]
+ interrupt-parent = <&eiointc>;
+ phandle = <0x8004>;
+ // status = "disabled";
+ };
+
+ pcie@1a000000 {
+ compatible = "loongson,ls7a-pci";
+
+ // status = "disabled"; // use this to enable/disable the PCIe devices
+
+ // configuration space
+ reg =
+ <0x00 0x1a000000 0x0 0x20000000>,
+ <0xfe 0x00000000 0x0 0x20000000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ msi-parent = <&msi>;
+ bus-range = <0x0 0xff>;
+
+ // PCIe resources
+ ranges =
+ <0x01000000 0x0 0x00008000 0x0 0x18408000 0x0 0x00008000>,// 0x01000000 (IO) [PCIe space base address][CPU space address][size]
+ <0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>;// 0x02000000 (MEM) [PCIe space base address][CPU space address][size]
+
+ // interrputs
+ interrupt-map-mask = <0xff00 0x00 0x00 0x7>;
+ interrupt-map =
+ <
+ 0x1800 0x00 0x00 0x01 0x8003 12 IRQ_TYPE_LEVEL_HIGH// 3,0 a
+ 0x1800 0x00 0x00 0x02 0x8003 13 IRQ_TYPE_LEVEL_HIGH// 3,0 b
+
+ 0x2000 0x00 0x00 0x01 0x8003 49 IRQ_TYPE_LEVEL_HIGH// 4,0 a
+ 0x2100 0x00 0x00 0x01 0x8003 48 IRQ_TYPE_LEVEL_HIGH// 4,1 b
+
+ 0x2800 0x00 0x00 0x01 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 a
+ 0x2800 0x00 0x00 0x02 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 b
+ 0x2800 0x00 0x00 0x03 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 c
+ 0x2800 0x00 0x00 0x04 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 d
+
+ 0x2900 0x00 0x00 0x01 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 a
+ 0x2900 0x00 0x00 0x02 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 b
+ 0x2900 0x00 0x00 0x03 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 c
+ 0x2900 0x00 0x00 0x04 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 d
+
+ 0x3000 0x00 0x00 0x01 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 a
+ 0x3000 0x00 0x00 0x02 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 b
+ 0x3000 0x00 0x00 0x03 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 c
+ 0x3000 0x00 0x00 0x04 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 d
+
+ 0x3100 0x00 0x00 0x01 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 a
+ 0x3100 0x00 0x00 0x02 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 b
+ 0x3100 0x00 0x00 0x03 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 c
+ 0x3100 0x00 0x00 0x04 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 d
+
+ 0x3200 0x00 0x00 0x01 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 a
+ 0x3200 0x00 0x00 0x02 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 b
+ 0x3200 0x00 0x00 0x03 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 c
+ 0x3200 0x00 0x00 0x04 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 d
+
+ 0x3800 0x00 0x00 0x01 0x8003 78 IRQ_TYPE_LEVEL_HIGH// 7,0 a
+ 0x3800 0x00 0x00 0x02 0x8003 79 IRQ_TYPE_LEVEL_HIGH// 7,0 b
+
+ 0x4000 0x00 0x00 0x01 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 a
+ 0x4000 0x00 0x00 0x02 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 b
+ 0x4000 0x00 0x00 0x03 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 c
+ 0x4000 0x00 0x00 0x04 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 d
+
+ 0x4800 0x00 0x00 0x01 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 a
+ 0x4800 0x00 0x00 0x02 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 b
+ 0x4800 0x00 0x00 0x03 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 c
+ 0x4800 0x00 0x00 0x04 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 d
+
+ 0x5000 0x00 0x00 0x01 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 a
+ 0x5000 0x00 0x00 0x02 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 b
+ 0x5000 0x00 0x00 0x03 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 c
+ 0x5000 0x00 0x00 0x04 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 d
+
+ 0x5800 0x00 0x00 0x01 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 a
+ 0x5800 0x00 0x00 0x02 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 b
+ 0x5800 0x00 0x00 0x03 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 c
+ 0x5800 0x00 0x00 0x04 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 d
+
+ 0x6000 0x00 0x00 0x01 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 a
+ 0x6000 0x00 0x00 0x02 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 b
+ 0x6000 0x00 0x00 0x03 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 c
+ 0x6000 0x00 0x00 0x04 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 d
+
+ 0x6800 0x00 0x00 0x01 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 a
+ 0x6800 0x00 0x00 0x02 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 b
+ 0x6800 0x00 0x00 0x03 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 c
+ 0x6800 0x00 0x00 0x04 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 d
+
+ 0x7000 0x00 0x00 0x01 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 a
+ 0x7000 0x00 0x00 0x02 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 b
+ 0x7000 0x00 0x00 0x03 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 c
+ 0x7000 0x00 0x00 0x04 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 d
+
+ 0x7800 0x00 0x00 0x01 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 a
+ 0x7800 0x00 0x00 0x02 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 b
+ 0x7800 0x00 0x00 0x03 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 c
+ 0x7800 0x00 0x00 0x04 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 d
+
+ 0x8000 0x00 0x00 0x01 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 a
+ 0x8000 0x00 0x00 0x02 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 b
+ 0x8000 0x00 0x00 0x03 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 c
+ 0x8000 0x00 0x00 0x04 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 d
+
+ 0x9800 0x00 0x00 0x01 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 a
+ 0x9800 0x00 0x00 0x02 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 b
+ 0x9800 0x00 0x00 0x03 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 c
+ 0x9800 0x00 0x00 0x04 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 d
+
+ 0xa000 0x00 0x00 0x01 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 a
+ 0xa000 0x00 0x00 0x02 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 b
+ 0xa000 0x00 0x00 0x03 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 c
+ 0xa000 0x00 0x00 0x04 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 d
+
+ 0xb800 0x00 0x00 0x01 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 a
+ 0xb800 0x00 0x00 0x02 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 b
+ 0xb800 0x00 0x00 0x03 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 c
+ 0xb800 0x00 0x00 0x04 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 d
+
+ 0xc800 0x00 0x00 0x01 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 a
+ 0xc800 0x00 0x00 0x02 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 b
+ 0xc800 0x00 0x00 0x03 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 c
+ 0xc800 0x00 0x00 0x04 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 d
+ >;
+
+ #interrupt-cells = <0x01>;
+ };
+};
diff --git a/platform/loongarch64/ls3a6000/image/dts/zone1-linux.dts b/platform/loongarch64/ls3a6000/image/dts/zone1-linux.dts
new file mode 100644
index 00000000..98b5e2db
--- /dev/null
+++ b/platform/loongarch64/ls3a6000/image/dts/zone1-linux.dts
@@ -0,0 +1,219 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+* Copyright (C) 2023 Loongson Technology Corporation Limited
+* Modified for hvisor by wheatfox(wheatfox17@icloud.com) syswonder.org 2024
+*/
+
+/dts-v1/;
+
+#include "loongson-3a5000.dtsi"
+
+
+&uart1 {
+ status = "okay";
+};
+
+
+/ {
+ compatible = "loongson,ls3a5000-root", "loongson,ls3a5000";
+ model = "Loongson3 hvisor nonroot zone board";
+
+ aliases {
+ serial = &uart1;
+ };
+
+ chosen {
+ // initramfs
+ bootargs = "earlycon console=ttyS0,115200n8 initramfs_async=false rootwait debug loglevel=8 earlyprintk nohlt";
+
+ // SSD root, a {zone_name}-disk.ext4 virtio blk file on SSD root_hvisor partition
+ // bootargs = "earlycon console=ttyS0,115200n8 rootwait root=/dev/vda rw";
+ };
+
+ memory@200000 {
+ device_type = "memory";
+ reg = <0 0xc0200000 0 0x0ee00000
+ 0 0xd0000000 0 0x10000000
+ 0x1 0x40000000 0 0x800000
+ 0x1 0x40800000 0 0x800000
+ 0x1 0x41000000 0 0x800000
+ >;
+ };
+
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ shmem@0 {
+ no-map;
+ reg = <0x1 0x40000000 0 0x800000>;
+ };
+ shmem@1 {
+ no-map;
+ reg = <0x1 0x40800000 0 0x800000>;
+ };
+ shmem@2 {
+ no-map;
+ reg = <0x1 0x41000000 0 0x800000>;
+ };
+ };
+
+ msi: msi-controller@1fe01140 {
+ compatible = "loongson,pch-msi-1.0";
+ reg = <0x0 0x1fe01140 0x0 0x8>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ msi-controller;
+ loongson,msi-base-vec = <112>;
+ loongson,msi-num-vecs = <48>; // [64-111(48),112-159(48),160-207(48),208-255(48)]
+ interrupt-parent = <&eiointc>;
+ phandle = <0x8004>;
+ };
+
+ // virtio console
+ virtio_mmio@30001000 {
+ dma-coherent;
+ compatible = "virtio,mmio";
+ interrupt-parent = <&cpuintc>;
+ interrupts = <4>;// = hwirq
+ reg = <0x0 0x30001000 0x0 0x200>;
+ status = "okay";
+ };
+ // virtio blk
+ virtio_mmio@30002000 {
+ dma-coherent;
+ compatible = "virtio,mmio";
+ // interrupt-parent = <&cpuintc>;
+ // interrupts = <5>;// = hwirq
+ interrupt-parent = <&cpuintc>;
+ interrupts = <5>;// = hwirq
+ reg = <0x0 0x30002000 0x0 0x200>;
+ status = "okay";
+ };
+
+ pcie@1a000000 {
+ compatible = "loongson,ls7a-pci";
+
+ // configuration space
+ reg =
+ <0x00 0x1a000000 0x0 0x20000000>,
+ <0xfe 0x00000000 0x0 0x20000000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ msi-parent = <&msi>;
+ bus-range = <0x0 0xff>;
+
+ // PCIe resources
+ ranges =
+ <0x01000000 0x0 0x00008000 0x0 0x18408000 0x0 0x00008000>,// 0x01000000 (IO) [PCIe space base address][CPU space address][size]
+ <0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>;// 0x02000000 (MEM) [PCIe space base address][CPU space address][size]
+
+ // interrputs
+ interrupt-map-mask = <0xff00 0x00 0x00 0x7>;
+ interrupt-map =
+ <
+ 0x1800 0x00 0x00 0x01 0x8003 12 IRQ_TYPE_LEVEL_HIGH// 3,0 a
+ 0x1800 0x00 0x00 0x02 0x8003 13 IRQ_TYPE_LEVEL_HIGH// 3,0 b
+
+ 0x2000 0x00 0x00 0x01 0x8003 49 IRQ_TYPE_LEVEL_HIGH// 4,0 a
+ 0x2100 0x00 0x00 0x01 0x8003 48 IRQ_TYPE_LEVEL_HIGH// 4,1 b
+
+ 0x2800 0x00 0x00 0x01 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 a
+ 0x2800 0x00 0x00 0x02 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 b
+ 0x2800 0x00 0x00 0x03 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 c
+ 0x2800 0x00 0x00 0x04 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 d
+
+ 0x2900 0x00 0x00 0x01 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 a
+ 0x2900 0x00 0x00 0x02 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 b
+ 0x2900 0x00 0x00 0x03 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 c
+ 0x2900 0x00 0x00 0x04 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 d
+
+ 0x3000 0x00 0x00 0x01 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 a
+ 0x3000 0x00 0x00 0x02 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 b
+ 0x3000 0x00 0x00 0x03 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 c
+ 0x3000 0x00 0x00 0x04 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 d
+
+ 0x3100 0x00 0x00 0x01 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 a
+ 0x3100 0x00 0x00 0x02 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 b
+ 0x3100 0x00 0x00 0x03 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 c
+ 0x3100 0x00 0x00 0x04 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 d
+
+ 0x3200 0x00 0x00 0x01 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 a
+ 0x3200 0x00 0x00 0x02 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 b
+ 0x3200 0x00 0x00 0x03 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 c
+ 0x3200 0x00 0x00 0x04 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 d
+
+ 0x3800 0x00 0x00 0x01 0x8003 78 IRQ_TYPE_LEVEL_HIGH// 7,0 a
+ 0x3800 0x00 0x00 0x02 0x8003 79 IRQ_TYPE_LEVEL_HIGH// 7,0 b
+
+ 0x4000 0x00 0x00 0x01 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 a
+ 0x4000 0x00 0x00 0x02 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 b
+ 0x4000 0x00 0x00 0x03 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 c
+ 0x4000 0x00 0x00 0x04 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 d
+
+ 0x4800 0x00 0x00 0x01 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 a
+ 0x4800 0x00 0x00 0x02 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 b
+ 0x4800 0x00 0x00 0x03 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 c
+ 0x4800 0x00 0x00 0x04 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 d
+
+ 0x5000 0x00 0x00 0x01 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 a
+ 0x5000 0x00 0x00 0x02 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 b
+ 0x5000 0x00 0x00 0x03 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 c
+ 0x5000 0x00 0x00 0x04 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 d
+
+ 0x5800 0x00 0x00 0x01 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 a
+ 0x5800 0x00 0x00 0x02 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 b
+ 0x5800 0x00 0x00 0x03 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 c
+ 0x5800 0x00 0x00 0x04 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 d
+
+ 0x6000 0x00 0x00 0x01 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 a
+ 0x6000 0x00 0x00 0x02 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 b
+ 0x6000 0x00 0x00 0x03 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 c
+ 0x6000 0x00 0x00 0x04 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 d
+
+ 0x6800 0x00 0x00 0x01 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 a
+ 0x6800 0x00 0x00 0x02 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 b
+ 0x6800 0x00 0x00 0x03 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 c
+ 0x6800 0x00 0x00 0x04 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 d
+
+ 0x7000 0x00 0x00 0x01 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 a
+ 0x7000 0x00 0x00 0x02 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 b
+ 0x7000 0x00 0x00 0x03 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 c
+ 0x7000 0x00 0x00 0x04 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 d
+
+ 0x7800 0x00 0x00 0x01 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 a
+ 0x7800 0x00 0x00 0x02 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 b
+ 0x7800 0x00 0x00 0x03 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 c
+ 0x7800 0x00 0x00 0x04 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 d
+
+ 0x8000 0x00 0x00 0x01 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 a
+ 0x8000 0x00 0x00 0x02 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 b
+ 0x8000 0x00 0x00 0x03 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 c
+ 0x8000 0x00 0x00 0x04 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 d
+
+ 0x9800 0x00 0x00 0x01 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 a
+ 0x9800 0x00 0x00 0x02 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 b
+ 0x9800 0x00 0x00 0x03 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 c
+ 0x9800 0x00 0x00 0x04 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 d
+
+ 0xa000 0x00 0x00 0x01 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 a
+ 0xa000 0x00 0x00 0x02 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 b
+ 0xa000 0x00 0x00 0x03 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 c
+ 0xa000 0x00 0x00 0x04 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 d
+
+ 0xb800 0x00 0x00 0x01 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 a
+ 0xb800 0x00 0x00 0x02 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 b
+ 0xb800 0x00 0x00 0x03 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 c
+ 0xb800 0x00 0x00 0x04 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 d
+
+ 0xc800 0x00 0x00 0x01 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 a
+ 0xc800 0x00 0x00 0x02 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 b
+ 0xc800 0x00 0x00 0x03 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 c
+ 0xc800 0x00 0x00 0x04 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 d
+ >;
+
+ #interrupt-cells = <0x01>;
+ };
+};
diff --git a/platform/loongarch64/ls3a6000/image/dts/zone2-linux.dts b/platform/loongarch64/ls3a6000/image/dts/zone2-linux.dts
new file mode 100644
index 00000000..a8504086
--- /dev/null
+++ b/platform/loongarch64/ls3a6000/image/dts/zone2-linux.dts
@@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+* Copyright (C) 2023 Loongson Technology Corporation Limited
+* Modified for hvisor by wheatfox(wheatfox17@icloud.com) syswonder.org 2024
+*/
+
+/dts-v1/;
+
+#include "loongson-3a5000.dtsi"
+
+
+&uart1 {
+ status = "okay";
+ // set the above 'uart1' to 'uart0' if you don't have a COM connection right now
+};
+
+
+/ {
+ compatible = "loongson,ls3a5000-root", "loongson,ls3a5000";
+ model = "Loongson3 hvisor nonroot zone board";
+
+ aliases {
+ serial = &uart1;
+ };
+
+ chosen {
+ // initramfs
+ bootargs = "earlycon console=ttyS0,115200n8 initramfs_async=false rootwait debug loglevel=8 earlyprintk nohlt";
+
+ // SSD root, a {zone_name}-disk.ext4 virtio blk file on SSD root_hvisor partition
+ // bootargs = "earlycon console=ttyS0,115200n8 rootwait root=/dev/vda rw";
+ };
+
+ memory@200000 {
+ device_type = "memory";
+ reg = <0 0xa0200000 0 0x0ee00000
+ 0 0xb0000000 0 0x10000000
+ 0x1 0x40800000 0 0x800000
+ >;
+ };
+
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ shmem@0 {
+ no-map;
+ reg = <0x1 0x40800000 0 0x800000>;
+ };
+ };
+
+ msi: msi-controller@1fe01140 {
+ compatible = "loongson,pch-msi-1.0";
+ reg = <0x0 0x1fe01140 0x0 0x8>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ msi-controller;
+ loongson,msi-base-vec = <160>;
+ loongson,msi-num-vecs = <48>;// [64-111(48),112-159(48),160-207(48),208-255(48)]
+ interrupt-parent = <&eiointc>;
+ phandle = <0x8004>;
+ };
+
+ // virtio console
+ virtio_mmio@30001000 {
+ dma-coherent;
+ compatible = "virtio,mmio";
+ interrupt-parent = <&cpuintc>;
+ interrupts = <4>;// = hwirq
+ reg = <0x0 0x30001000 0x0 0x200>;
+ status = "okay";
+ };
+ // virtio blk
+ virtio_mmio@30002000 {
+ dma-coherent;
+ compatible = "virtio,mmio";
+ // interrupt-parent = <&cpuintc>;
+ // interrupts = <5>;// = hwirq
+ interrupt-parent = <&cpuintc>;
+ interrupts = <5>;// = hwirq
+ reg = <0x0 0x30002000 0x0 0x200>;
+ status = "okay";
+ };
+
+ pcie@1a000000 {
+ compatible = "loongson,ls7a-pci";
+
+ // configuration space
+ reg =
+ <0x00 0x1a000000 0x0 0x20000000>,
+ <0xfe 0x00000000 0x0 0x20000000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ msi-parent = <&msi>;
+ bus-range = <0x0 0xff>;
+
+ // PCIe resources
+ ranges =
+ <0x01000000 0x0 0x00008000 0x0 0x18408000 0x0 0x00008000>,// 0x01000000 (IO) [PCIe space base address][CPU space address][size]
+ <0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>;// 0x02000000 (MEM) [PCIe space base address][CPU space address][size]
+
+ // interrputs
+ interrupt-map-mask = <0xff00 0x00 0x00 0x7>;
+ interrupt-map =
+ <
+ 0x1800 0x00 0x00 0x01 0x8003 12 IRQ_TYPE_LEVEL_HIGH// 3,0 a
+ 0x1800 0x00 0x00 0x02 0x8003 13 IRQ_TYPE_LEVEL_HIGH// 3,0 b
+
+ 0x2000 0x00 0x00 0x01 0x8003 49 IRQ_TYPE_LEVEL_HIGH// 4,0 a
+ 0x2100 0x00 0x00 0x01 0x8003 48 IRQ_TYPE_LEVEL_HIGH// 4,1 b
+
+ 0x2800 0x00 0x00 0x01 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 a
+ 0x2800 0x00 0x00 0x02 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 b
+ 0x2800 0x00 0x00 0x03 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 c
+ 0x2800 0x00 0x00 0x04 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 d
+
+ 0x2900 0x00 0x00 0x01 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 a
+ 0x2900 0x00 0x00 0x02 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 b
+ 0x2900 0x00 0x00 0x03 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 c
+ 0x2900 0x00 0x00 0x04 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 d
+
+ 0x3000 0x00 0x00 0x01 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 a
+ 0x3000 0x00 0x00 0x02 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 b
+ 0x3000 0x00 0x00 0x03 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 c
+ 0x3000 0x00 0x00 0x04 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 d
+
+ 0x3100 0x00 0x00 0x01 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 a
+ 0x3100 0x00 0x00 0x02 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 b
+ 0x3100 0x00 0x00 0x03 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 c
+ 0x3100 0x00 0x00 0x04 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 d
+
+ 0x3200 0x00 0x00 0x01 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 a
+ 0x3200 0x00 0x00 0x02 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 b
+ 0x3200 0x00 0x00 0x03 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 c
+ 0x3200 0x00 0x00 0x04 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 d
+
+ 0x3800 0x00 0x00 0x01 0x8003 78 IRQ_TYPE_LEVEL_HIGH// 7,0 a
+ 0x3800 0x00 0x00 0x02 0x8003 79 IRQ_TYPE_LEVEL_HIGH// 7,0 b
+
+ 0x4000 0x00 0x00 0x01 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 a
+ 0x4000 0x00 0x00 0x02 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 b
+ 0x4000 0x00 0x00 0x03 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 c
+ 0x4000 0x00 0x00 0x04 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 d
+
+ 0x4800 0x00 0x00 0x01 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 a
+ 0x4800 0x00 0x00 0x02 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 b
+ 0x4800 0x00 0x00 0x03 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 c
+ 0x4800 0x00 0x00 0x04 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 d
+
+ 0x5000 0x00 0x00 0x01 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 a
+ 0x5000 0x00 0x00 0x02 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 b
+ 0x5000 0x00 0x00 0x03 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 c
+ 0x5000 0x00 0x00 0x04 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 d
+
+ 0x5800 0x00 0x00 0x01 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 a
+ 0x5800 0x00 0x00 0x02 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 b
+ 0x5800 0x00 0x00 0x03 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 c
+ 0x5800 0x00 0x00 0x04 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 d
+
+ 0x6000 0x00 0x00 0x01 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 a
+ 0x6000 0x00 0x00 0x02 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 b
+ 0x6000 0x00 0x00 0x03 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 c
+ 0x6000 0x00 0x00 0x04 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 d
+
+ 0x6800 0x00 0x00 0x01 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 a
+ 0x6800 0x00 0x00 0x02 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 b
+ 0x6800 0x00 0x00 0x03 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 c
+ 0x6800 0x00 0x00 0x04 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 d
+
+ 0x7000 0x00 0x00 0x01 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 a
+ 0x7000 0x00 0x00 0x02 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 b
+ 0x7000 0x00 0x00 0x03 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 c
+ 0x7000 0x00 0x00 0x04 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 d
+
+ 0x7800 0x00 0x00 0x01 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 a
+ 0x7800 0x00 0x00 0x02 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 b
+ 0x7800 0x00 0x00 0x03 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 c
+ 0x7800 0x00 0x00 0x04 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 d
+
+ 0x8000 0x00 0x00 0x01 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 a
+ 0x8000 0x00 0x00 0x02 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 b
+ 0x8000 0x00 0x00 0x03 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 c
+ 0x8000 0x00 0x00 0x04 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 d
+
+ 0x9800 0x00 0x00 0x01 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 a
+ 0x9800 0x00 0x00 0x02 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 b
+ 0x9800 0x00 0x00 0x03 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 c
+ 0x9800 0x00 0x00 0x04 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 d
+
+ 0xa000 0x00 0x00 0x01 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 a
+ 0xa000 0x00 0x00 0x02 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 b
+ 0xa000 0x00 0x00 0x03 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 c
+ 0xa000 0x00 0x00 0x04 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 d
+
+ 0xb800 0x00 0x00 0x01 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 a
+ 0xb800 0x00 0x00 0x02 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 b
+ 0xb800 0x00 0x00 0x03 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 c
+ 0xb800 0x00 0x00 0x04 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 d
+
+ 0xc800 0x00 0x00 0x01 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 a
+ 0xc800 0x00 0x00 0x02 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 b
+ 0xc800 0x00 0x00 0x03 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 c
+ 0xc800 0x00 0x00 0x04 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 d
+ >;
+
+ #interrupt-cells = <0x01>;
+ };
+};
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a6000/image/dts/zone3-linux.dts b/platform/loongarch64/ls3a6000/image/dts/zone3-linux.dts
new file mode 100644
index 00000000..376995aa
--- /dev/null
+++ b/platform/loongarch64/ls3a6000/image/dts/zone3-linux.dts
@@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+* Copyright (C) 2023 Loongson Technology Corporation Limited
+* Modified for hvisor by wheatfox(wheatfox17@icloud.com) syswonder.org 2024
+*/
+
+/dts-v1/;
+
+#include "loongson-3a5000.dtsi"
+
+
+&uart1 {
+ status = "okay";
+ // set the above 'uart1' to 'uart0' if you don't have a COM connection right now
+};
+
+
+/ {
+ compatible = "loongson,ls3a5000-root", "loongson,ls3a5000";
+ model = "Loongson3 hvisor nonroot zone board";
+
+ aliases {
+ serial = &uart1;
+ };
+
+ chosen {
+ // initramfs
+ bootargs = "earlycon console=ttyS0,115200n8 initramfs_async=false rootwait debug loglevel=8 earlyprintk nohlt";
+
+ // SSD root, a {zone_name}-disk.ext4 virtio blk file on SSD root_hvisor partition
+ // bootargs = "earlycon console=ttyS0,115200n8 rootwait root=/dev/vda rw";
+ };
+
+ memory@200000 {
+ device_type = "memory";
+ reg = <0x1 0x00200000 0 0x0ee00000
+ 0x1 0x10000000 0 0x10000000
+ 0x1 0x41000000 0 0x800000
+ >;
+ };
+
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ shmem@0 {
+ no-map;
+ reg = <0x1 0x41000000 0 0x800000>;
+ };
+ };
+
+ msi: msi-controller@1fe01140 {
+ compatible = "loongson,pch-msi-1.0";
+ reg = <0x0 0x1fe01140 0x0 0x8>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ msi-controller;
+ loongson,msi-base-vec = <208>;
+ loongson,msi-num-vecs = <48>;// [64-111(48),112-159(48),160-207(48),208-255(48)]
+ interrupt-parent = <&eiointc>;
+ phandle = <0x8004>;
+ };
+
+ // virtio console
+ virtio_mmio@30001000 {
+ dma-coherent;
+ compatible = "virtio,mmio";
+ interrupt-parent = <&cpuintc>;
+ interrupts = <4>;// = hwirq
+ reg = <0x0 0x30001000 0x0 0x200>;
+ status = "okay";
+ };
+ // virtio blk
+ virtio_mmio@30002000 {
+ dma-coherent;
+ compatible = "virtio,mmio";
+ // interrupt-parent = <&cpuintc>;
+ // interrupts = <5>;// = hwirq
+ interrupt-parent = <&cpuintc>;
+ interrupts = <5>;// = hwirq
+ reg = <0x0 0x30002000 0x0 0x200>;
+ status = "okay";
+ };
+
+ pcie@1a000000 {
+ compatible = "loongson,ls7a-pci";
+
+ // configuration space
+ reg =
+ <0x00 0x1a000000 0x0 0x20000000>,
+ <0xfe 0x00000000 0x0 0x20000000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ msi-parent = <&msi>;
+ bus-range = <0x0 0xff>;
+
+ // PCIe resources
+ ranges =
+ <0x01000000 0x0 0x00008000 0x0 0x18408000 0x0 0x00008000>,// 0x01000000 (IO) [PCIe space base address][CPU space address][size]
+ <0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>;// 0x02000000 (MEM) [PCIe space base address][CPU space address][size]
+
+ // interrputs
+ interrupt-map-mask = <0xff00 0x00 0x00 0x7>;
+ interrupt-map =
+ <
+ 0x1800 0x00 0x00 0x01 0x8003 12 IRQ_TYPE_LEVEL_HIGH// 3,0 a
+ 0x1800 0x00 0x00 0x02 0x8003 13 IRQ_TYPE_LEVEL_HIGH// 3,0 b
+
+ 0x2000 0x00 0x00 0x01 0x8003 49 IRQ_TYPE_LEVEL_HIGH// 4,0 a
+ 0x2100 0x00 0x00 0x01 0x8003 48 IRQ_TYPE_LEVEL_HIGH// 4,1 b
+
+ 0x2800 0x00 0x00 0x01 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 a
+ 0x2800 0x00 0x00 0x02 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 b
+ 0x2800 0x00 0x00 0x03 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 c
+ 0x2800 0x00 0x00 0x04 0x8003 51 IRQ_TYPE_LEVEL_HIGH// 5,0 d
+
+ 0x2900 0x00 0x00 0x01 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 a
+ 0x2900 0x00 0x00 0x02 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 b
+ 0x2900 0x00 0x00 0x03 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 c
+ 0x2900 0x00 0x00 0x04 0x8003 50 IRQ_TYPE_LEVEL_HIGH// 5,1 d
+
+ 0x3000 0x00 0x00 0x01 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 a
+ 0x3000 0x00 0x00 0x02 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 b
+ 0x3000 0x00 0x00 0x03 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 c
+ 0x3000 0x00 0x00 0x04 0x8003 29 IRQ_TYPE_LEVEL_HIGH// 6,0 d
+
+ 0x3100 0x00 0x00 0x01 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 a
+ 0x3100 0x00 0x00 0x02 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 b
+ 0x3100 0x00 0x00 0x03 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 c
+ 0x3100 0x00 0x00 0x04 0x8003 28 IRQ_TYPE_LEVEL_HIGH// 6,1 d
+
+ 0x3200 0x00 0x00 0x01 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 a
+ 0x3200 0x00 0x00 0x02 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 b
+ 0x3200 0x00 0x00 0x03 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 c
+ 0x3200 0x00 0x00 0x04 0x8003 23 IRQ_TYPE_LEVEL_HIGH// 6,2 d
+
+ 0x3800 0x00 0x00 0x01 0x8003 78 IRQ_TYPE_LEVEL_HIGH// 7,0 a
+ 0x3800 0x00 0x00 0x02 0x8003 79 IRQ_TYPE_LEVEL_HIGH// 7,0 b
+
+ 0x4000 0x00 0x00 0x01 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 a
+ 0x4000 0x00 0x00 0x02 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 b
+ 0x4000 0x00 0x00 0x03 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 c
+ 0x4000 0x00 0x00 0x04 0x8003 16 IRQ_TYPE_LEVEL_HIGH// 8,0 d
+
+ 0x4800 0x00 0x00 0x01 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 a
+ 0x4800 0x00 0x00 0x02 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 b
+ 0x4800 0x00 0x00 0x03 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 c
+ 0x4800 0x00 0x00 0x04 0x8003 32 IRQ_TYPE_LEVEL_HIGH// 9,0 d
+
+ 0x5000 0x00 0x00 0x01 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 a
+ 0x5000 0x00 0x00 0x02 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 b
+ 0x5000 0x00 0x00 0x03 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 c
+ 0x5000 0x00 0x00 0x04 0x8003 33 IRQ_TYPE_LEVEL_HIGH// a,0 d
+
+ 0x5800 0x00 0x00 0x01 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 a
+ 0x5800 0x00 0x00 0x02 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 b
+ 0x5800 0x00 0x00 0x03 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 c
+ 0x5800 0x00 0x00 0x04 0x8003 34 IRQ_TYPE_LEVEL_HIGH// b,0 d
+
+ 0x6000 0x00 0x00 0x01 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 a
+ 0x6000 0x00 0x00 0x02 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 b
+ 0x6000 0x00 0x00 0x03 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 c
+ 0x6000 0x00 0x00 0x04 0x8003 35 IRQ_TYPE_LEVEL_HIGH// c,0 d
+
+ 0x6800 0x00 0x00 0x01 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 a
+ 0x6800 0x00 0x00 0x02 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 b
+ 0x6800 0x00 0x00 0x03 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 c
+ 0x6800 0x00 0x00 0x04 0x8003 36 IRQ_TYPE_LEVEL_HIGH// d,0 d
+
+ 0x7000 0x00 0x00 0x01 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 a
+ 0x7000 0x00 0x00 0x02 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 b
+ 0x7000 0x00 0x00 0x03 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 c
+ 0x7000 0x00 0x00 0x04 0x8003 37 IRQ_TYPE_LEVEL_HIGH// e,0 d
+
+ 0x7800 0x00 0x00 0x01 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 a
+ 0x7800 0x00 0x00 0x02 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 b
+ 0x7800 0x00 0x00 0x03 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 c
+ 0x7800 0x00 0x00 0x04 0x8003 40 IRQ_TYPE_LEVEL_HIGH// f,0 d
+
+ 0x8000 0x00 0x00 0x01 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 a
+ 0x8000 0x00 0x00 0x02 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 b
+ 0x8000 0x00 0x00 0x03 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 c
+ 0x8000 0x00 0x00 0x04 0x8003 41 IRQ_TYPE_LEVEL_HIGH// 10,0 d
+
+ 0x9800 0x00 0x00 0x01 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 a
+ 0x9800 0x00 0x00 0x02 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 b
+ 0x9800 0x00 0x00 0x03 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 c
+ 0x9800 0x00 0x00 0x04 0x8003 38 IRQ_TYPE_LEVEL_HIGH// 13,0 d
+
+ 0xa000 0x00 0x00 0x01 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 a
+ 0xa000 0x00 0x00 0x02 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 b
+ 0xa000 0x00 0x00 0x03 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 c
+ 0xa000 0x00 0x00 0x04 0x8003 39 IRQ_TYPE_LEVEL_HIGH// 14,0 d
+
+ 0xb800 0x00 0x00 0x01 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 a
+ 0xb800 0x00 0x00 0x02 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 b
+ 0xb800 0x00 0x00 0x03 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 c
+ 0xb800 0x00 0x00 0x04 0x8003 19 IRQ_TYPE_LEVEL_HIGH// 17,0 d
+
+ 0xc800 0x00 0x00 0x01 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 a
+ 0xc800 0x00 0x00 0x02 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 b
+ 0xc800 0x00 0x00 0x03 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 c
+ 0xc800 0x00 0x00 0x04 0x8003 22 IRQ_TYPE_LEVEL_HIGH// 19,0 d
+ >;
+
+ #interrupt-cells = <0x01>;
+ };
+};
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a6000/linker.ld b/platform/loongarch64/ls3a6000/linker.ld
new file mode 100644
index 00000000..2c1cf5a7
--- /dev/null
+++ b/platform/loongarch64/ls3a6000/linker.ld
@@ -0,0 +1,59 @@
+ENTRY(arch_entry)
+BASE_ADDRESS = 0x90000001f0000000;
+
+
+SECTIONS
+{
+ . = BASE_ADDRESS;
+ skernel = .;
+
+ stext = .;
+ .text : {
+ *(.text.entry)
+ *(.text .text.*)
+ }
+
+ . = ALIGN(4K);
+ .trap_entry : {
+ *(.trap_entry)
+ . = ALIGN(4K);
+ *(.tlbrefill_entry)
+ }
+
+ . = ALIGN(4K);
+ etext = .;
+ srodata = .;
+ .rodata : {
+ *(.rodata .rodata.*)
+ *(.srodata .srodata.*)
+ }
+
+ . = ALIGN(4K);
+ erodata = .;
+ sdata = .;
+ .data : {
+ *(.data .data.*)
+ *(.sdata .sdata.*)
+
+ }
+ . = ALIGN(4K);
+ edata = .;
+
+ .bss : {
+ *(.bss.stack)
+ sbss = .;
+ *(.bss .bss.*)
+ *(.sbss .sbss.*)
+ }
+
+ . = ALIGN(4K);
+ ebss = .;
+
+ ekernel = .;
+
+ /DISCARD/ : {
+ *(.eh_frame)
+ }
+ . = ALIGN(4K);
+ __core_end = .;
+}
\ No newline at end of file
diff --git a/platform/loongarch64/ls3a6000/platform.mk b/platform/loongarch64/ls3a6000/platform.mk
new file mode 100644
index 00000000..e2abe865
--- /dev/null
+++ b/platform/loongarch64/ls3a6000/platform.mk
@@ -0,0 +1,25 @@
+# hvisor for loongarch64 makefile
+# wheatfox(wheatfox17@icloud.com) 2024.6
+
+# HVISOR ENTRY
+HVISOR_ENTRY_PA := 0x9000000080000000
+
+# zone0_kernel := $(image_dir)/kernel/Image
+# zone0_dtb := $(image_dir)/devicetree/linux.dtb
+
+# QEMU for loongarch64 doesn't support LVZ extension yet
+# so no qemu related stuff here, we have to debug it on
+# REAL hardware with UEFI firmware interface
+
+# QEMU := qemu-system-loongarch64
+# QEMU_ARGS := -machine virt
+# QEMU_ARGS += -bios default
+# QEMU_ARGS += -smp 4
+# QEMU_ARGS += -m 2G
+# QEMU_ARGS += -nographic
+# QEMU_ARGS += -kernel $(hvisor_bin)
+# QEMU_ARGS += -device loader,file="$(zone0_kernel)",addr=0x90000000,force-raw=on
+# QEMU_ARGS += -device loader,file="$(zone0_dtb)",addr=0x8f000000,force-raw=on
+
+$(hvisor_bin): elf
+ $(OBJCOPY) $(hvisor_elf) --strip-all -O binary $@
\ No newline at end of file
diff --git a/platform/riscv64/hifive-premier-p550/board.rs b/platform/riscv64/hifive-premier-p550/board.rs
new file mode 100644
index 00000000..05cb782a
--- /dev/null
+++ b/platform/riscv64/hifive-premier-p550/board.rs
@@ -0,0 +1,164 @@
+// Copyright (c) 2025 Syswonder
+// hvisor is licensed under Mulan PSL v2.
+// You can use this software according to the terms and conditions of the Mulan PSL v2.
+// You may obtain a copy of Mulan PSL v2 at:
+// http://license.coscl.org.cn/MulanPSL2
+// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+// FIT FOR A PARTICULAR PURPOSE.
+// See the Mulan PSL v2 for more details.
+//
+// Syswonder Website:
+// https://www.syswonder.org
+//
+// Authors:
+//
+use crate::{arch::zone::HvArchZoneConfig, config::*};
+
+#[allow(unused)]
+pub const BOARD_NAME: &str = "hifive-premier-p550";
+
+pub const BOARD_NCPUS: usize = 4;
+pub const PLIC_BASE: usize = 0xc000000;
+pub const BOARD_PLIC_INTERRUPTS_NUM: usize = 1023; // except irq 0
+pub const SIFIVE_CCACHE_BASE: usize = 0x2010000; // SiFive composable cache controller
+pub const SIFIVE_CCACHE_SIZE: usize = 0x4000; // 16KB
+
+pub const ROOT_ZONE_DTB_ADDR: u64 = 0x8f000000;
+pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x90000000;
+pub const ROOT_ZONE_ENTRY: u64 = 0x90000000;
+pub const ROOT_ZONE_CPUS: u64 = 0x1;
+
+pub const ROOT_ZONE_NAME: &str = "root-linux";
+
+pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 7] = [
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_RAM,
+ physical_start: 0x80000000,
+ virtual_start: 0x80000000,
+ size: 0x8000_0000,
+ }, // ram
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x50900000,
+ virtual_start: 0x50900000,
+ size: 0x10000,
+ }, // serial0
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x51810000,
+ // virtual_start: 0x51810000,
+ // size: 0x8000,
+ // }, // scu
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x50c00000,
+ // virtual_start: 0x50c00000,
+ // size: 0x100000,
+ // }, // iommu
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x51c00000,
+ // virtual_start: 0x51c00000,
+ // size: 0x400000,
+ // }, // npu
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x51c00000,
+ // virtual_start: 0x51c00000,
+ // size: 0x400000,
+ // }, // npu
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x50920000,
+ // virtual_start: 0x50920000,
+ // size: 0x10000,
+ // }, // serial2
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x50460000,
+ virtual_start: 0x50460000,
+ size: 0x10000,
+ }, // mmc
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x50440000,
+ virtual_start: 0x50440000,
+ size: 0x2000,
+ }, // hsp_sp_top_csr
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x51828000,
+ virtual_start: 0x51828000,
+ size: 0x80000,
+ }, // sys-crg (clock-controller, reset-controller) (SD card needs)
+ // Cache controller is needed, otherwise terminal will report "VFS: cannot open root device..."
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x2010000,
+ virtual_start: 0x2010000,
+ size: 0x4000,
+ }, // L3 cache-controller, now hvisor has virtual sifive ccache.
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x8000000,
+ // virtual_start: 0x8000000,
+ // size: 0x400000,
+ // }, // L3 Loosely-Integrated Memory (L3 LIM)
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0xc0_0000_0000,
+ virtual_start: 0xc0_0000_0000,
+ // mem-port -> sys-port (here easily equal to mem size), this is needed for uncache access in eic7700x soc.
+ size: 0x4_0000_0000,
+ }, // Sys-port. (here related to DMA)
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x104000,
+ // virtual_start: 0x104000,
+ // size: 0x4000,
+ // }, // pL2Cache. (cpu0)
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x108000,
+ // virtual_start: 0x108000,
+ // size: 0x4000,
+ // }, // pL2Cache. (cpu1)
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x50420000,
+ // virtual_start: 0x50420000,
+ // size: 0x10000,
+ // }, // sata
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x51600000,
+ // virtual_start: 0x51600000,
+ // size: 0x200000,
+ // }, // pinctrl
+];
+
+// Note: all here's irqs are hardware irqs,
+// only these irq can be transferred to the physical PLIC.
+pub const HW_IRQS: [u32; 3] = [
+ 0x4f, // emmc
+ 0x51, // sd-card
+ 0x64 // uart0
+];
+
+// irqs belong to the root zone.
+pub const ROOT_ZONE_IRQS: [u32; 2] = [
+ 0x51, // sd-card
+ 0x64 // uart0
+];
+
+pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig {
+ plic_base: 0xc000000,
+ plic_size: 0x4000000,
+ aplic_base: 0xd000000,
+ aplic_size: 0x8000,
+};
+
+// Virtio zone1 cmd:
+// nohup ./hvisor virtio start zone1-linux-virtio.json &
+// ./hvisor zone start zone1-linux.json
diff --git a/platform/riscv64/hifive-premier-p550/boot.scr b/platform/riscv64/hifive-premier-p550/boot.scr
new file mode 100644
index 00000000..b6aff6ab
Binary files /dev/null and b/platform/riscv64/hifive-premier-p550/boot.scr differ
diff --git a/platform/riscv64/hifive-premier-p550/boot.txt b/platform/riscv64/hifive-premier-p550/boot.txt
new file mode 100644
index 00000000..3c41e341
--- /dev/null
+++ b/platform/riscv64/hifive-premier-p550/boot.txt
@@ -0,0 +1,10 @@
+setenv serverip 192.168.137.10;
+setenv ipaddr 192.168.137.11;
+setenv netmask 255.255.255.0;
+setenv hvisor_addr 0x80200000;
+setenv zone0_fdt_addr 0x8f000000;
+setenv zone0_kernel_addr 0x90000000;
+tftpboot ${hvisor_addr} ${serverip}:hvisor.bin;
+tftpboot ${zone0_fdt_addr} ${serverip}:zone0.dtb;
+tftpboot ${zone0_kernel_addr} ${serverip}:Image;
+bootm ${hvisor_addr} - ${fdt_addr};
diff --git a/platform/riscv64/hifive-premier-p550/cargo/config.template.toml b/platform/riscv64/hifive-premier-p550/cargo/config.template.toml
new file mode 100644
index 00000000..f5d5b55c
--- /dev/null
+++ b/platform/riscv64/hifive-premier-p550/cargo/config.template.toml
@@ -0,0 +1,6 @@
+[target.riscv64gc-unknown-none-elf]
+runner = "platform/__ARCH__/__BOARD__/test/runner.sh"
+rustflags = [
+ "-Clink-arg=-Tplatform/__ARCH__/__BOARD__/linker.ld",
+ "-Cforce-frame-pointers=yes",
+]
\ No newline at end of file
diff --git a/platform/riscv64/hifive-premier-p550/cargo/features b/platform/riscv64/hifive-premier-p550/cargo/features
new file mode 100644
index 00000000..d72ea9ac
--- /dev/null
+++ b/platform/riscv64/hifive-premier-p550/cargo/features
@@ -0,0 +1,4 @@
+eic770x_soc
+plic
+eic7700_sysreg
+sifive_ccache
diff --git a/platform/riscv64/hifive-premier-p550/configs/zone1-linux-virtio.json b/platform/riscv64/hifive-premier-p550/configs/zone1-linux-virtio.json
new file mode 100644
index 00000000..777b119d
--- /dev/null
+++ b/platform/riscv64/hifive-premier-p550/configs/zone1-linux-virtio.json
@@ -0,0 +1,23 @@
+{
+ "zones": [
+ {
+ "id": 1,
+ "memory_region": [
+ {
+ "zone0_ipa": "0x83000000",
+ "zonex_ipa": "0x83000000",
+ "size": "0x0C000000"
+ }
+ ],
+ "devices": [
+ {
+ "type": "console",
+ "addr": "0x10007000",
+ "len": "0x1000",
+ "irq": 7,
+ "status": "enable"
+ }
+ ]
+ }
+ ]
+}
\ No newline at end of file
diff --git a/platform/riscv64/hifive-premier-p550/configs/zone1-linux.json b/platform/riscv64/hifive-premier-p550/configs/zone1-linux.json
new file mode 100644
index 00000000..0e8bc05b
--- /dev/null
+++ b/platform/riscv64/hifive-premier-p550/configs/zone1-linux.json
@@ -0,0 +1,63 @@
+{
+ "arch": "riscv",
+ "name": "linux2",
+ "zone_id": 1,
+ "cpus": [1],
+ "memory_regions": [
+ {
+ "type": "ram",
+ "physical_start": "0x83000000",
+ "virtual_start": "0x83000000",
+ "size": "0x0C000000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x50450000",
+ "virtual_start": "0x50450000",
+ "size": "0x10000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x50440000",
+ "virtual_start": "0x50440000",
+ "size": "0x2000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x2010000",
+ "virtual_start": "0x2010000",
+ "size": "0x4000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x51828000",
+ "virtual_start": "0x51828000",
+ "size": "0x80000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0xc000000000",
+ "virtual_start": "0xc000000000",
+ "size": "0x80000000"
+ },
+ {
+ "type": "virtio",
+ "physical_start": "0x10007000",
+ "virtual_start": "0x10007000",
+ "size": "0x1000"
+ }
+ ],
+ "interrupts": [7, 79],
+ "ivc_configs": [],
+ "kernel_filepath": "./Image",
+ "dtb_filepath": "./zone1-linux.dtb",
+ "kernel_load_paddr": "0x84000000",
+ "dtb_load_paddr": "0x83000000",
+ "entry_point": "0x84000000",
+ "arch_config": {
+ "plic_base": "0xc000000",
+ "plic_size": "0x4000000",
+ "aplic_base": "0xd000000",
+ "aplic_size": "0x8000"
+ }
+}
\ No newline at end of file
diff --git a/platform/riscv64/hifive-premier-p550/image/dts/Makefile b/platform/riscv64/hifive-premier-p550/image/dts/Makefile
new file mode 100644
index 00000000..2f795e7f
--- /dev/null
+++ b/platform/riscv64/hifive-premier-p550/image/dts/Makefile
@@ -0,0 +1,8 @@
+DTS_FILES := $(wildcard *.dts)
+DTB_FILES := $(DTS_FILES:.dts=.dtb)
+
+all: $(DTB_FILES)
+%.dtb: %.dts
+ dtc -I dts -O dtb $< -o $@
+clean:
+ rm -f $(DTB_FILES)
\ No newline at end of file
diff --git a/platform/riscv64/hifive-premier-p550/image/dts/eic7700-hifive-premier-p550.dts b/platform/riscv64/hifive-premier-p550/image/dts/eic7700-hifive-premier-p550.dts
new file mode 100644
index 00000000..fd290b8a
--- /dev/null
+++ b/platform/riscv64/hifive-premier-p550/image/dts/eic7700-hifive-premier-p550.dts
@@ -0,0 +1,5797 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "sifive,hifive-premier-p550\0eswin,eic7700";
+ model = "SiFive HiFive Premier P550";
+
+ opp-table@cpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+ phandle = <0x04>;
+
+ opp-24000000 {
+ opp-hz = <0x00 0x16e3600>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-100000000 {
+ opp-hz = <0x00 0x5f5e100>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-200000000 {
+ opp-hz = <0x00 0xbebc200>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-400000000 {
+ opp-hz = <0x00 0x17d78400>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-500000000 {
+ opp-hz = <0x00 0x1dcd6500>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-600000000 {
+ opp-hz = <0x00 0x23c34600>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-700000000 {
+ opp-hz = <0x00 0x29b92700>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-800000000 {
+ opp-hz = <0x00 0x2faf0800>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-900000000 {
+ opp-hz = <0x00 0x35a4e900>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-1000000000 {
+ opp-hz = <0x00 0x3b9aca00>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-1200000000 {
+ opp-hz = <0x00 0x47868c00>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-1300000000 {
+ opp-hz = <0x00 0x4d7c6d00>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-1400000000 {
+ opp-hz = <0x00 0x53724e00>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-1500000000 {
+ opp-hz = <0x00 0x59682f00>;
+ opp-microvolt = <0xdbba0>;
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-1600000000 {
+ opp-hz = <0x00 0x5f5e1000>;
+ opp-microvolt = <0xdbba0>;
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-1700000000 {
+ opp-hz = <0x00 0x6553f100>;
+ opp-microvolt = <0xdbba0>;
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-1800000000 {
+ opp-hz = <0x00 0x6b49d200>;
+ opp-microvolt = <0xdbba0>;
+ clock-latency-ns = <0x11170>;
+ };
+ };
+
+ opp-table@dsp {
+ compatible = "operating-points-v2";
+ phandle = <0x25>;
+
+ opp@520000000 {
+ opp-hz = <0x00 0x1efe9200>;
+ opp-microvolt = "\0\f5";
+ };
+
+ opp@1040000000 {
+ opp-hz = <0x00 0x3dfd2400>;
+ opp-microvolt = "\0\f5";
+ };
+ };
+
+ opp-table@npu {
+ compatible = "operating-points-v2";
+ phandle = <0x22>;
+
+ opp@1040000000 {
+ opp-hz = <0x00 0x3dfd2400>;
+ opp-microvolt = <0xdbba0>;
+ };
+
+ opp@1500000000 {
+ opp-hz = <0x00 0x59682f00>;
+ opp-microvolt = <0x100590>;
+ };
+ };
+
+ opp-table@g2d {
+ compatible = "operating-points-v2";
+ phandle = <0x2b>;
+
+ opp@260000000 {
+ opp-hz = <0x00 0xf7f4900>;
+ opp-microvolt = "\0\f5";
+ };
+
+ opp@520000000 {
+ opp-hz = <0x00 0x1efe9200>;
+ opp-microvolt = "\0\f5";
+ };
+
+ opp@693333334 {
+ opp-hz = <0x00 0x29536d56>;
+ opp-microvolt = "\0\f5";
+ };
+
+ opp@1040000000 {
+ opp-hz = <0x00 0x3dfd2400>;
+ opp-microvolt = "\0\f5";
+ };
+ };
+
+ opp-table@vi {
+ compatible = "operating-points-v2";
+ phandle = <0x6c>;
+
+ opp@800000000 {
+ opp-hz = <0x00 0x2faf0800>;
+ opp-microvolt = "\0\f5";
+ };
+
+ opp@400000000 {
+ opp-hz = <0x00 0x17d78400>;
+ opp-microvolt = "\0\f5";
+ };
+
+ opp@200000000 {
+ opp-hz = <0x00 0xbebc200>;
+ opp-microvolt = "\0\f5";
+ };
+ };
+
+ opp-table@venc {
+ compatible = "operating-points-v2";
+ phandle = <0x32>;
+
+ opp@800000000 {
+ opp-hz = <0x00 0x2faf0800>;
+ opp-microvolt = "\0\f5";
+ };
+
+ opp@400000000 {
+ opp-hz = <0x00 0x17d78400>;
+ opp-microvolt = "\0\f5";
+ };
+
+ opp@200000000 {
+ opp-hz = <0x00 0xbebc200>;
+ opp-microvolt = "\0\f5";
+ };
+ };
+
+ opp-table@vdec {
+ compatible = "operating-points-v2";
+ phandle = <0x31>;
+
+ opp@800000000 {
+ opp-hz = <0x00 0x2faf0800>;
+ opp-microvolt = "\0\f5";
+ };
+
+ opp@400000000 {
+ opp-hz = <0x00 0x17d78400>;
+ opp-microvolt = "\0\f5";
+ };
+
+ opp@200000000 {
+ opp-hz = <0x00 0xbebc200>;
+ opp-microvolt = "\0\f5";
+ };
+ };
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ timebase-frequency = <0xf4240>;
+
+ idle-states {
+
+ cpu-retentive {
+ compatible = "riscv,idle-state";
+ riscv,sbi-suspend-param = <0x00>;
+ entry-latency-us = <0x14>;
+ exit-latency-us = <0x28>;
+ min-residency-us = <0x50>;
+ phandle = <0x05>;
+ };
+ };
+
+ cpu@0 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x01>;
+ reg = <0x00>;
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x02>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f4>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0c>;
+ };
+ };
+
+ cpu@1 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x06>;
+ reg = <0x01>;
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x07>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f5>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0d>;
+ };
+ };
+
+ cpu@2 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x08>;
+ reg = <0x02>;
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x09>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f6>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0e>;
+ };
+ };
+
+ cpu@3 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x0a>;
+ reg = <0x03>;
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x0b>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f7>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0f>;
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "SiFive,FU800-soc\0fu800-soc\0sifive-soc\0simple-bus";
+ ranges;
+
+ pmu@0 {
+ riscv,raw-event-to-mhpmcounters = <0x00 0x00 0xffffffff 0xff 0x1f8 0x00 0x01 0xffffffff 0xfff800ff 0x1f8 0x00 0x02 0xffffffff 0xffffc0ff 0x1f8>;
+ riscv,event-to-mhpmcounters = <0x01 0x01 0x01 0x02 0x02 0x02 0x04 0x06 0x1f8 0x10009 0x10009 0x1f8 0x10019 0x10019 0x1f8 0x10021 0x10021 0x1f8>;
+ riscv,event-to-mhpmevent = <0x04 0x00 0x202 0x05 0x00 0x4000 0x06 0x00 0x2001 0x10009 0x00 0x102 0x10019 0x00 0x1002 0x10021 0x00 0x802>;
+ compatible = "riscv,pmu0\0riscv,pmu";
+ interrupts-extended = <0x0c 0x0d 0x0d 0x0d 0x0e 0x0d 0x0f 0x0d>;
+ numa-node-id = <0x00>;
+ };
+
+ authentication-controller {
+ compatible = "sifive,authentication0";
+ sifive,auth-types = "fuse";
+ };
+
+ axi4-sys-port@40000000 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "sifive,axi4-sys-port\0sifive,axi4-port\0sifive,sys-port\0simple-external-bus\0simple-bus";
+ ranges = <0x40000000 0x00 0x40000000 0x40000000>;
+ sifive,port-width-bytes = <0x10>;
+ };
+
+ axi4-sys-port@8000000000 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "sifive,axi4-sys-port\0sifive,axi4-port\0sifive,sys-port\0simple-external-bus\0simple-bus";
+ ranges = <0x80 0x00 0x80 0x00 0x180 0x00>;
+ sifive,port-width-bytes = <0x10>;
+ };
+
+ basic-bus-blocker@200000 {
+ compatible = "sifive,basic-bus-blocker1";
+ reg = <0x00 0x200000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ basic-bus-blocker@202000 {
+ compatible = "sifive,basic-bus-blocker1";
+ reg = <0x00 0x202000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ basic-bus-blocker@204000 {
+ compatible = "sifive,basic-bus-blocker1";
+ reg = <0x00 0x204000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ burst-bundler@10010000 {
+ compatible = "sifive,burst-bundler0";
+ reg = <0x00 0x10010000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ bus-error-unit@hart0 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <0x10>;
+ interrupts = <0x205>;
+ reg = <0x00 0x1700000 0x00 0x1000>;
+ reg-names = "control";
+ numa-node-id = <0x00>;
+ phandle = <0x02>;
+ };
+
+ bus-error-unit@hart1 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <0x10>;
+ interrupts = <0x206>;
+ reg = <0x00 0x1701000 0x00 0x1000>;
+ reg-names = "control";
+ numa-node-id = <0x00>;
+ phandle = <0x07>;
+ };
+
+ bus-error-unit@hart2 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <0x10>;
+ interrupts = <0x207>;
+ reg = <0x00 0x1702000 0x00 0x1000>;
+ reg-names = "control";
+ numa-node-id = <0x00>;
+ phandle = <0x09>;
+ };
+
+ bus-error-unit@hart3 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <0x10>;
+ interrupts = <0x208>;
+ reg = <0x00 0x1703000 0x00 0x1000>;
+ reg-names = "control";
+ numa-node-id = <0x00>;
+ phandle = <0x0b>;
+ };
+
+ cache-controller@2010000 {
+ cache-block-size = <0x40>;
+ cache-level = <0x03>;
+ cache-sets = <0x1000>;
+ cache-size = <0x400000>;
+ cache-unified;
+ compatible = "sifive,ccache1\0cache\0sifive,fu740-c000-ccache";
+ interrupt-parent = <0x10>;
+ interrupts = <0x01 0x03 0x04 0x02>;
+ next-level-cache = <0x11 0x12 0x13>;
+ reg = <0x00 0x2010000 0x00 0x4000 0x00 0x8000000 0x00 0x400000>;
+ reg-names = "control\0sideband";
+ sifive,a-mshr-count = <0x3c>;
+ sifive,bank-count = <0x04>;
+ sifive,ecc-granularity = <0x08>;
+ sifive,max-master-id = <0x0d>;
+ sifive,perfmon-counters = <0x06>;
+ numa-node-id = <0x00>;
+ phandle = <0x14>;
+ };
+
+ debug-controller@0 {
+ compatible = "sifive,debug-100\0riscv,debug-100";
+ debug-attach = "jtag";
+ reg = <0x00 0x00 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ error-device@1000 {
+ compatible = "sifive,error0";
+ reg = <0x00 0x1000 0x00 0x3000 0x00 0x5000 0x00 0x13000 0x00 0x19000 0x00 0xe7000 0x00 0x114000 0x00 0xec000 0x00 0x201000 0x00 0x1000 0x00 0x203000 0x00 0x1000 0x00 0x205000 0x00 0x14fb000 0x00 0x1704000 0x00 0x8fc000 0x00 0x2014000 0x00 0x5fec000 0x00 0x8400000 0x00 0x3c00000 0x00 0x10000000 0x00 0x3000 0x00 0x10004000 0x00 0xc000 0x00 0x10011000 0x00 0x1f000 0x00 0x10034000 0x00 0x9fcc000 0x00 0x1a400000 0x00 0x5c00000>;
+ };
+
+ error-device@10003000 {
+ compatible = "sifive,error0";
+ reg = <0x00 0x10003000 0x00 0x1000>;
+ phandle = <0x11>;
+ };
+
+ interrupt-controller@c000000 {
+ #interrupt-cells = <0x01>;
+ compatible = "sifive,plic-1.0.0";
+ interrupt-controller;
+ interrupts-extended = <0x0c 0xffffffff 0x0c 0x09 0x0d 0xffffffff 0x0d 0x09 0x0e 0xffffffff 0x0e 0x09 0x0f 0xffffffff 0x0f 0x09>;
+ reg = <0x00 0xc000000 0x00 0x4000000>;
+ reg-names = "control";
+ riscv,max-priority = <0x07>;
+ riscv,ndev = <0x208>;
+ numa-node-id = <0x00>;
+ phandle = <0x10>;
+ };
+
+ order-obliterator@10030000 {
+ compatible = "sifive,order-obliterator0";
+ interrupt-parent = <0x10>;
+ interrupts = <0x204>;
+ reg = <0x00 0x10030000 0x00 0x4000>;
+ reg-names = "control";
+ };
+
+ pl2@104000 {
+ cache-block-size = <0x40>;
+ cache-level = <0x02>;
+ cache-sets = <0x200>;
+ cache-size = <0x40000>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0\0cache";
+ next-level-cache = <0x14>;
+ reg = <0x00 0x104000 0x00 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <0x10>;
+ sifive,perfmon-counters = <0x06>;
+ numa-node-id = <0x00>;
+ phandle = <0x01>;
+ };
+
+ pl2@108000 {
+ cache-block-size = <0x40>;
+ cache-level = <0x02>;
+ cache-sets = <0x200>;
+ cache-size = <0x40000>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0\0cache";
+ next-level-cache = <0x14>;
+ reg = <0x00 0x108000 0x00 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <0x10>;
+ sifive,perfmon-counters = <0x06>;
+ numa-node-id = <0x00>;
+ phandle = <0x06>;
+ };
+
+ pl2@10c000 {
+ cache-block-size = <0x40>;
+ cache-level = <0x02>;
+ cache-sets = <0x200>;
+ cache-size = <0x40000>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0\0cache";
+ next-level-cache = <0x14>;
+ reg = <0x00 0x10c000 0x00 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <0x10>;
+ sifive,perfmon-counters = <0x06>;
+ numa-node-id = <0x00>;
+ phandle = <0x08>;
+ };
+
+ pl2@110000 {
+ cache-block-size = <0x40>;
+ cache-level = <0x02>;
+ cache-sets = <0x200>;
+ cache-size = <0x40000>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0\0cache";
+ next-level-cache = <0x14>;
+ reg = <0x00 0x110000 0x00 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <0x10>;
+ sifive,perfmon-counters = <0x06>;
+ numa-node-id = <0x00>;
+ phandle = <0x0a>;
+ };
+
+ rom@1a000000 {
+ compatible = "ucbbar,cacheable-zero0";
+ reg = <0x00 0x1a000000 0x00 0x400000>;
+ phandle = <0x12>;
+ };
+
+ rom@3a000000 {
+ compatible = "ucbbar,cacheable-zero0";
+ reg = <0x00 0x3a000000 0x00 0x400000>;
+ phandle = <0x13>;
+ };
+
+ subsystem_pbus_clock {
+ #clock-cells = <0x00>;
+ clock-frequency = <0x989680>;
+ clock-output-names = "subsystem_pbus_clock";
+ compatible = "fixed-clock";
+ };
+
+ teststatus@4000 {
+ compatible = "sifive,test0";
+ reg = <0x00 0x4000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ tl-address-adjuster@20000000 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "sifive,tl-inter-sys-port\0sifive,tl-port\0simple-external-bus\0simple-bus";
+ ranges = <0x20000000 0x00 0x20000000 0x1a000000 0x3a400000 0x00 0x3a400000 0x5c00000>;
+ sifive,port-width-bytes = <0x08>;
+ };
+
+ tl-inter-mem-master-port@80000000 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "sifive,tl-inter-mem-master-port\0sifive,tl-port\0sifive,inter-mem-master-port\0simple-external-bus\0simple-bus";
+ ranges = <0x00 0x80000000 0x00 0x80000000 0x7f 0x80000000>;
+ sifive,port-width-bytes = <0x20>;
+ };
+
+ trace-encoder-0@100000 {
+ compatible = "sifive,trace0";
+ reg = <0x00 0x100000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ trace-encoder-1@101000 {
+ compatible = "sifive,trace0";
+ reg = <0x00 0x101000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ trace-encoder-2@102000 {
+ compatible = "sifive,trace0";
+ reg = <0x00 0x102000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ trace-encoder-3@103000 {
+ compatible = "sifive,trace0";
+ reg = <0x00 0x103000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ trace-funnel-0@18000 {
+ compatible = "sifive,trace0";
+ reg = <0x00 0x18000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ serial@0x50900000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00 0x50900000 0x00 0x10000>;
+ clock-frequency = <0xbebc200>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x64>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ phandle = <0x2a>;
+ };
+
+ serial@0x50910000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00 0x50910000 0x00 0x10000>;
+ clock-frequency = <0xbebc200>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x65>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ };
+
+ serial@0x50920000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00 0x50920000 0x00 0x10000>;
+ clock-frequency = <0xbebc200>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x66>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ };
+
+ serial@0x50930000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00 0x50930000 0x00 0x10000>;
+ clock-frequency = <0xbebc200>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x67>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ numa-node-id = <0x00>;
+ status = "disabled";
+ };
+
+ serial@0x50940000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00 0x50940000 0x00 0x10000>;
+ clock-frequency = <0xbebc200>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x68>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ numa-node-id = <0x00>;
+ status = "disabled";
+ };
+
+ scu_sys_con@0x51810000 {
+ compatible = "eswin,win2030-scu-sys-con\0syscon\0simple-mfd";
+ #syscon-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x51810000 0x00 0x8000>;
+ numa-node-id = <0x00>;
+ phandle = <0x17>;
+
+ noc@51810324 {
+ compatible = "eswin,win2030-noc-wdt";
+ interrupt-parent = <0x10>;
+ interrupts = <0x188 0x189 0x18a 0x18b 0x18c 0x18d 0x18e 0x18f 0x190 0x191 0x192 0x193 0x194 0x195 0x196 0x197 0x198 0x199 0x19a 0x19b 0x19c 0x19d 0x19e 0x19f 0x1a0 0x1a1 0x1a2 0x1a3 0x1a4 0x1a5 0x1a6 0x1a7 0x1a8 0x1a9 0x1aa>;
+ eswin,syscrg_csr = <0x15 0x100 0xffff>;
+ status = "okay";
+ };
+ };
+
+ sys-crg@51828000 {
+ compatible = "eswin,win2030-sys-crg\0syscon\0simple-mfd";
+ reg = <0x00 0x51828000 0x00 0x80000>;
+ numa-node-id = <0x00>;
+ phandle = <0x15>;
+
+ reset-controller {
+ compatible = "eswin,win2030-reset";
+ #reset-cells = <0x02>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ phandle = <0x18>;
+ };
+
+ clock-controller {
+ compatible = "eswin,win2030-clock";
+ #clock-cells = <0x01>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ cpu-voltage-gpios = <0x16 0x1e 0x00>;
+ phandle = <0x03>;
+ };
+ };
+
+ hfclk {
+ #clock-cells = <0x00>;
+ compatible = "fixed-clock";
+ clock-frequency = <0xbebc200>;
+ clock-output-names = "hfclk";
+ numa-node-id = <0x00>;
+ };
+
+ hsp_sp_top_csr@0x50440000 {
+ compatible = "eswin,win2030-hsp-sp-csr\0syscon";
+ numa-node-id = <0x00>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x50440000 0x00 0x2000>;
+ phandle = <0x1a>;
+ };
+
+ iommu@50c00000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x00 0x50c00000 0x00 0x100000>;
+ eswin,syscfg = <0x17 0x3fc>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x164 0x168 0x165 0x166>;
+ interrupt-names = "eventq\0gerror\0priq\0cmdq-sync";
+ #iommu-cells = <0x01>;
+ resets = <0x18 0x05 0x01 0x18 0x05 0x02 0x18 0x05 0x10 0x18 0x05 0x20 0x18 0x05 0x40 0x18 0x05 0x80 0x18 0x05 0x100 0x18 0x05 0x200 0x18 0x05 0x400 0x18 0x05 0x800>;
+ reset-names = "axi_rst\0cfg_rst\0tbu0_rst\0tbu1_rst\0tbu2_rst\0tbu3_rst\0tbu4_rst\0tbu5_rst\0tbu6_rst\0tbu7_rst";
+ status = "okay";
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ phandle = <0x19>;
+ };
+
+ pmu@50c02000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x00 0x50c02000 0x00 0x1000 0x00 0x50c22000 0x00 0x1000>;
+ eswin,syscfg = <0x17 0x3fc>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x16b>;
+ status = "disabled";
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ };
+
+ E21@0 {
+ compatible = "riscv,dev-foo-a";
+ #size-cells = <0x02>;
+ dma-ranges = <0x00 0x20000000 0x00 0xc0000000 0x00 0x40000000>;
+ iommus = <0x19 0x1c>;
+ tbus = <0xf00>;
+ status = "okay";
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ };
+
+ power-controller@51808000 {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ compatible = "eswin,win2030-pmu-controller";
+ #power-domain-cells = <0x01>;
+ reg = <0x00 0x51808000 0x00 0x8000>;
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ win2030-pmu-controller-port@0 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ id = <0x00>;
+ reg_base = <0x00>;
+ power_status = <0x02>;
+ power_delay = <0x06 0x06 0x03 0x03>;
+ clock_delay = <0x04 0x02 0x02 0x02>;
+ reset_delay = <0x02 0x04 0x02 0x02>;
+ clamp_delay = <0x03 0x03 0x02 0x02>;
+ label = "D0_PCIE";
+ tbus = <0x03>;
+ };
+
+ win2030-pmu-controller-port@40 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ id = <0x01>;
+ reg_base = <0x40>;
+ power_status = <0x02>;
+ power_delay = <0x06 0x06 0x03 0x03>;
+ clock_delay = <0x04 0x02 0x02 0x02>;
+ reset_delay = <0x02 0x04 0x02 0x02>;
+ clamp_delay = <0x03 0x03 0x02 0x02>;
+ tbus = <0x71>;
+ label = "D0_DSP1";
+ };
+
+ win2030-pmu-controller-port@80 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ id = <0x02>;
+ reg_base = <0x80>;
+ power_status = <0x02>;
+ power_delay = <0x06 0x06 0x03 0x03>;
+ clock_delay = <0x04 0x02 0x02 0x02>;
+ reset_delay = <0x02 0x04 0x02 0x02>;
+ clamp_delay = <0x03 0x03 0x02 0x02>;
+ tbus = <0x00 0x00>;
+ label = "D0_VI";
+ };
+
+ win2030-pmu-controller-port@c0 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ id = <0x03>;
+ reg_base = <0xc0>;
+ power_status = <0x02>;
+ power_delay = <0x06 0x06 0x03 0x03>;
+ clock_delay = <0x04 0x02 0x02 0x02>;
+ reset_delay = <0x02 0x04 0x02 0x02>;
+ clamp_delay = <0x03 0x03 0x02 0x02>;
+ label = "D0_VO";
+ };
+
+ win2030-pmu-controller-port@140 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ id = <0x04>;
+ reg_base = <0x140>;
+ power_status = <0x02>;
+ power_delay = <0x06 0x06 0x03 0x03>;
+ clock_delay = <0x04 0x02 0x02 0x02>;
+ reset_delay = <0x02 0x04 0x02 0x02>;
+ clamp_delay = <0x03 0x03 0x02 0x02>;
+ tbus = <0x10 0x13 0x11 0x12>;
+ label = "D0_CODEC";
+ };
+
+ win2030-pmu-controller-port@200 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ id = <0x05>;
+ reg_base = <0x200>;
+ power_status = <0x02>;
+ power_delay = <0x06 0x06 0x03 0x03>;
+ clock_delay = <0x04 0x02 0x02 0x02>;
+ reset_delay = <0x02 0x04 0x02 0x02>;
+ clamp_delay = <0x03 0x03 0x02 0x02>;
+ tbus = <0x72>;
+ label = "D0_DSP2";
+ };
+
+ win2030-pmu-controller-port@240 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ id = <0x06>;
+ reg_base = <0x240>;
+ power_status = <0x02>;
+ power_delay = <0x06 0x06 0x03 0x03>;
+ clock_delay = <0x04 0x02 0x02 0x02>;
+ reset_delay = <0x02 0x04 0x02 0x02>;
+ clamp_delay = <0x03 0x03 0x02 0x02>;
+ tbus = <0x73>;
+ label = "D0_DSP3";
+ };
+ };
+
+ dma-controller-hsp@0x50430000 {
+ compatible = "eswin,eic770x-axi-dma";
+ reg = <0x00 0x50430000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x39>;
+ #dma-cells = <0x02>;
+ clocks = <0x03 0x2b2 0x03 0x2b3>;
+ clock-names = "core-clk\0cfgr-clk";
+ resets = <0x18 0x07 0x4000 0x18 0x07 0x100000>;
+ reset-names = "arst\0prst";
+ dma-channels = <0x0c>;
+ snps,dma-masters = <0x01>;
+ snps,priority = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b>;
+ snps,data-width = <0x02>;
+ snps,block-size = <0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000>;
+ snps,axi-max-burst-len = <0x10>;
+ snps,max-msize = <0x40>;
+ iommus = <0x19 0x01>;
+ tbus = <0x02>;
+ eswin,hsp_sp_csr = <0x1a 0x104c>;
+ eswin,syscfg = <0x17 0x3004 0x370>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ };
+
+ dma-controller-aon@0x518c0000 {
+ compatible = "eswin,eic770x-axi-dma";
+ reg = <0x00 0x518c0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x121>;
+ #dma-cells = <0x02>;
+ clocks = <0x03 0x266 0x03 0x264>;
+ clock-names = "core-clk\0cfgr-clk";
+ resets = <0x18 0x27 0x01 0x18 0x27 0x02>;
+ reset-names = "arst\0prst";
+ dma-channels = <0x10>;
+ snps,dma-masters = <0x02>;
+ snps,priority = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f>;
+ snps,data-width = <0x03>;
+ snps,block-size = <0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000>;
+ snps,axi-max-burst-len = <0x20>;
+ #size-cells = <0x02>;
+ #address-cells = <0x02>;
+ dma-ranges = <0x00 0x80000000 0x00 0x80000000 0x100 0x00>;
+ iommus = <0x19 0x1a>;
+ tbus = <0x04>;
+ eswin,syscfg = <0x17 0x3004 0x370>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x3c>;
+ };
+
+ ethernet@50400000 {
+ compatible = "eswin,win2030-qos-eth";
+ reg = <0x00 0x50400000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupt-names = "macirq";
+ interrupts = <0x3d>;
+ phy-mode = "rgmii";
+ numa-node-id = <0x00>;
+ id = <0x00>;
+ status = "okay";
+ clocks = <0x03 0x226 0x03 0x227 0x03 0x228>;
+ clock-names = "app\0stmmaceth\0tx";
+ resets = <0x18 0x07 0x4000000>;
+ reset-names = "ethrst";
+ tbus = <0x02>;
+ dma-noncoherent;
+ eswin,hsp_sp_csr = <0x1a 0x1030 0x100 0x108>;
+ eswin,syscrg_csr = <0x15 0x148 0x14c>;
+ eswin,dly_hsp_reg = <0x114 0x118 0x11c>;
+ snps,axi-config = <0x1b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x1c>;
+ rst-gpios = <0x1d 0x0a 0x01>;
+ eswin,rgmiisel = <0x1e 0x290 0x03>;
+ eswin,led-cfgs = <0x6100 0xa40 0x420>;
+ dly-param-1000m = <0x23232323 0x800c8023 0xc0c0c0c>;
+ dly-param-100m = <0x50505050 0x803f8050 0x3f3f3f3f>;
+ dly-param-10m = <0x00 0x00 0x00>;
+
+ stmmac-axi-config {
+ snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
+ snps,rd_osr_lmt = <0x02>;
+ snps,wr_osr_lmt = <0x02>;
+ snps,lpi_en = <0x00>;
+ phandle = <0x1b>;
+ };
+ };
+
+ ethernet@50410000 {
+ compatible = "eswin,win2030-qos-eth";
+ reg = <0x00 0x50410000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupt-names = "macirq";
+ interrupts = <0x46>;
+ phy-mode = "rgmii";
+ numa-node-id = <0x00>;
+ id = <0x01>;
+ status = "okay";
+ clocks = <0x03 0x226 0x03 0x227 0x03 0x229>;
+ clock-names = "app\0stmmaceth\0tx";
+ resets = <0x18 0x07 0x2000000>;
+ reset-names = "ethrst";
+ tbus = <0x02>;
+ dma-noncoherent;
+ eswin,hsp_sp_csr = <0x1a 0x1034 0x200 0x208>;
+ eswin,syscrg_csr = <0x15 0x148 0x14c>;
+ eswin,dly_hsp_reg = <0x214 0x218 0x21c>;
+ snps,axi-config = <0x1f>;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x20>;
+ rst-gpios = <0x1d 0x0f 0x01>;
+ eswin,rgmiisel = <0x1e 0x294 0x03>;
+ eswin,led-cfgs = <0x6100 0xa40 0x420>;
+ dly-param-1000m = <0x25252525 0x80268025 0x26262626>;
+ dly-param-100m = <0x48484848 0x80588048 0x58585858>;
+ dly-param-10m = <0x00 0x00 0x00>;
+
+ stmmac-axi-config {
+ snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
+ snps,rd_osr_lmt = <0x02>;
+ snps,wr_osr_lmt = <0x02>;
+ snps,lpi_en = <0x00>;
+ phandle = <0x1f>;
+ };
+ };
+
+ noc {
+ compatible = "eswin,noc\0simple-bus";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ numa-node-id = <0x00>;
+
+ d0_cfg_noc {
+ compatible = "eswin,win2030-noc";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ reg = <0x00 0x52060000 0x00 0x4000>;
+ numa-node-id = <0x00>;
+ interrupts = <0x1be>;
+ interrupt-names = "error";
+ interrupt-parent = <0x10>;
+ errlogger,idx = <0x00 0x01 0x03 0x05>;
+ status = "okay";
+
+ sideband_manager@52061000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0x00 0x52061000 0x00 0x10>;
+ SenseIn0 = <0x1e 0x00 0x1f 0x01 0x20 0x02 0x21 0x03 0x22 0x04 0x23 0x05 0x24 0x06 0x25 0x07 0x26 0x08 0x27 0x09 0x28 0x0a 0x29 0x0b 0x2a 0x0c 0x2b 0x0d 0x2c 0x0e 0x2d 0x0f 0x2e 0x10 0x2f 0x11 0x30 0x12 0x31 0x13 0x32 0x14>;
+ bf-name = "SBM_CLMM\0SBM_CNOC_AON\0SBM_CNOC_DDRT0_CTRL\0SBM_CNOC_DDRT0_PHY \0SBM_CNOC_DDRT1_CTRL\0SBM_CNOC_DDRT1_PHY\0SBM_CNOC_DSPT\0SBM_CNOC_GPU\0SBM_CNOC_HSP\0SBM_CNOC_LSP_APB2\0SBM_CNOC_LSP_APB3\0SBM_CNOC_LSP_APB4\0SBM_CNOC_LSP_APB6\0SBM_CNOC_MCPUT_D2D\0SBM_CNOC_NPU\0SBM_CNOC_PCIET_P\0SBM_CNOC_PCIET_X\0SBM_CNOC_TCU\0SBM_CNOC_VC\0SBM_CNOC_VI\0SBM_CNOC_VO";
+ };
+
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x14 0x20>;
+ description = "Register 0 to log errors";
+
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x01>;
+ lut = "Not Locked\0Locked";
+ };
+
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x01 0x04>;
+ lut = "RD: data read with incrementing address\0RDW: data read with wrapping address\0RDL: allocates monitor in the Target with incrementing address\0RDX: exclusive read with incrementing address\0WR: data write with incrementing address\0WRW: data write with wrapping address\0WRC: conditional write if matching monitor in Target is found\0RSV: reserved\0PRE: preamble packet of linked sequence (locked sequence)\0URG: urgency packet used for QoS (status must be REQ)";
+ };
+
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x08 0x03>;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error\0DEC (error source: Initiator NIU): decode error\0UNS (error source: Target NIU): unsupported access type\0DISC (error source: Power Disconnect): disconnected Target or NoC domain\0SEC (error source: Initiator NIU or Firewall): security error\0HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator\0TMO (error source: Target NIU): time-out\0RSV: reserved";
+ };
+
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x10 0x0c>;
+ };
+
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x1f 0x01>;
+ lut = "NTTP v3.0 (Invalid)\0NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register\0eswin,win2030,noc,filter,routeid";
+ offset,length = <0x18 0x20>;
+ description = "Register 1 to log errors";
+
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x0f 0x01>;
+ lut = "snoc_cnoc/I/0";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x0a 0x05>;
+ lut = "clmm/T/0\0cnoc_aon/T/0\0cnoc_ddrt0_ctrl/T/0\0cnoc_ddrt0_phy/T/0\0cnoc_ddrt1_ctrl/T/0\0cnoc_ddrt1_phy/T/0\0cnoc_dspt/T/0\0cnoc_gpu/T/0\0cnoc_hsp/T/0\0cnoc_lsp_apb2/T/0\0cnoc_lsp_apb3/T/0\0cnoc_lsp_apb4/T/0\0cnoc_lsp_apb6/T/0\0cnoc_mcput_d2d/T/0\0cnoc_npu/T/0\0cnoc_pciet_p/T/0\0cnoc_pciet_x/T/0\0cnoc_service/T/0\0cnoc_tcu/T/0\0cnoc_vc/T/0\0cnoc_vi/T/0\0cnoc_vo/T/0\0RESERVED\0RESERVED\0RESERVED\0RESERVED\0RESERVED\0RESERVED\0RESERVED\0RESERVED\0RESERVED\0RESERVED";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x08 0x02>;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x08>;
+ };
+ };
+
+ ErrorLogger3 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 0x20>;
+ description = "Register 3 to log errors";
+ aperture-link = <0x01>;
+
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x08 0x08>;
+ aperture-size = <0x2e>;
+ aperture-idx,aperture-base = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x51600000 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x71600000 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x51800000 0x00 0x00 0x00 0x01 0x00 0x01 0x00 0x71800000 0x00 0x00 0x00 0x01 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x52300000 0x00 0x00 0x00 0x02 0x00 0x01 0x00 0x72300000 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x53000000 0x00 0x00 0x00 0x03 0x00 0x01 0x00 0x73000000 0x00 0x00 0x00 0x04 0x00 0x00 0x00 0x52380000 0x00 0x00 0x00 0x04 0x00 0x01 0x00 0x72380000 0x00 0x00 0x00 0x05 0x00 0x00 0x00 0x53800000 0x00 0x00 0x00 0x05 0x00 0x01 0x00 0x73800000 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x52200000 0x00 0x00 0x00 0x06 0x00 0x01 0x00 0x72200000 0x00 0x00 0x00 0x07 0x00 0x00 0x00 0x51400000 0x00 0x00 0x00 0x07 0x00 0x01 0x00 0x71400000 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0x50400000 0x00 0x00 0x00 0x08 0x00 0x01 0x00 0x70400000 0x00 0x00 0x00 0x09 0x00 0x00 0x00 0x50800000 0x00 0x00 0x00 0x09 0x00 0x01 0x00 0x70800000 0x00 0x00 0x00 0x0a 0x00 0x00 0x00 0x50900000 0x00 0x00 0x00 0x0a 0x00 0x01 0x00 0x70900000 0x00 0x00 0x00 0x0b 0x00 0x00 0x00 0x50a00000 0x00 0x00 0x00 0x0b 0x00 0x01 0x00 0x70a00000 0x00 0x00 0x00 0x0c 0x00 0x00 0x00 0x50b00000 0x00 0x00 0x00 0x0c 0x00 0x01 0x00 0x70b00000 0x00 0x00 0x00 0x0d 0x00 0x00 0x00 0x52100000 0x00 0x00 0x00 0x0d 0x00 0x01 0x00 0x72100000 0x00 0x00 0x00 0x0e 0x00 0x00 0x00 0x51c00000 0x00 0x00 0x00 0x0e 0x00 0x01 0x00 0x71c00000 0x00 0x00 0x00 0x0f 0x00 0x00 0x00 0x50000000 0x00 0x00 0x00 0x0f 0x00 0x01 0x00 0x70000000 0x00 0x00 0x00 0x10 0x00 0x00 0x00 0x54000000 0x00 0x00 0x00 0x10 0x00 0x01 0x00 0x74000000 0x00 0x00 0x00 0x11 0x00 0x00 0x00 0x52060000 0x00 0x00 0x00 0x11 0x00 0x01 0x00 0x72060000 0x00 0x00 0x00 0x12 0x00 0x00 0x00 0x50c00000 0x00 0x00 0x00 0x12 0x00 0x01 0x00 0x70c00000 0x00 0x00 0x00 0x13 0x00 0x00 0x00 0x50100000 0x00 0x00 0x00 0x13 0x00 0x01 0x00 0x70100000 0x00 0x00 0x00 0x14 0x00 0x00 0x00 0x51000000 0x00 0x00 0x00 0x14 0x00 0x01 0x00 0x71000000 0x00 0x00 0x00 0x15 0x00 0x00 0x00 0x50200000 0x00 0x00 0x00 0x15 0x00 0x01 0x00 0x70200000>;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x28 0x20>;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x07>;
+ lut = "Cache_0\0Cache_1\0Cache_2\0Cache_3\0Prot_0\0Prot_1\0Prot_2";
+ };
+ };
+ };
+
+ d0_llc_noc@52081400 {
+ compatible = "eswin,win2030-noc";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ numa-node-id = <0x00>;
+ reg = <0x00 0x52081400 0x00 0x4000>;
+ interrupts = <0x1b9>;
+ interrupt-names = "error";
+ interrupt-parent = <0x10>;
+ errlogger,idx = <0x00 0x01 0x03 0x04 0x05>;
+ status = "okay";
+ stat,0 = "TracePort:ddr0_p0_req";
+ stat,1 = "TracePort:ddr1_p0_req";
+
+ sideband_manager@52082000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0x00 0x52082000 0x00 0x10>;
+ SenseIn0 = <0x3c 0x00 0x3d 0x01 0x3e 0x02 0x3f 0x03>;
+ bf-name = "SBM_LNOC_NPU_LLC0\0SBM_LNOC_NPU_LLC1\0SBM_LNOC_DDRT0_P0\0SBM_LNOC_DDRT1_P0";
+ };
+
+ llcnoc_packet_ddr0_p0_req_probe@52080000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52080000 0x00 0x4000>;
+ clocks = <0x03 0x217>;
+ clock-names = "clk";
+ interrupts = <0x1bd>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr0_p0_req";
+ };
+
+ llcnoc_packet_ddr1_p0_req_probe@52080800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52080800 0x00 0x4000>;
+ clocks = <0x03 0x21c>;
+ clock-names = "clk";
+ interrupts = <0x1bb>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr1_p0_req";
+ };
+
+ llcnoc_trans_probe@52081000 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0x00 0x52081000 0x00 0x4000>;
+ clocks = <0x03 0x203>;
+ clock-names = "clk";
+ interrupts = <0x1b9>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x02>;
+ counter,nr = <0x08>;
+ profiler,nr = <0x01>;
+ portsel = "npu_llc0\0npu_llc1";
+
+ llcnoc_trans_npu_llc0_filter@52081480 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52081480 0x00 0x80>;
+ };
+
+ llcnoc_trans_npu_llc1_filter@52081500 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52081500 0x00 0x80>;
+ };
+
+ llcnoc_trans_profiler@52081580 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0x00 0x52081580 0x00 0x80>;
+ };
+ };
+
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x14 0x20>;
+ description = "Register 0 to log errors";
+
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x01>;
+ lut = "Not Locked\0Locked";
+ };
+
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x01 0x04>;
+ lut = "RD: data read with incrementing address\0RDW: data read with wrapping address\0RDL: allocates monitor in the Target with incrementing address\0RDX: exclusive read with incrementing address\0WR: data write with incrementing address\0WRW: data write with wrapping address\0WRC: conditional write if matching monitor in Target is found\0RSV: reserved\0PRE: preamble packet of linked sequence (locked sequence)\0URG: urgency packet used for QoS (status must be REQ)";
+ };
+
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x08 0x03>;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error\0DEC (error source: Initiator NIU): decode error\0UNS (error source: Target NIU): unsupported access type\0DISC (error source: Power Disconnect): disconnected Target or NoC domain\0SEC (error source: Initiator NIU or Firewall): security error\0HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator\0TMO (error source: Target NIU): time-out\0RSV: reserved";
+ };
+
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x10 0x0c>;
+ };
+
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x1f 0x01>;
+ lut = "NTTP v3.0 (Invalid)\0NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register\0eswin,win2030,noc,filter,routeid";
+ offset,length = <0x18 0x20>;
+ description = "Register 1 to log errors";
+
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x0e 0x02>;
+ lut = "npu_lnoc_llc0/I/0\0npu_lnoc_llc1/I/0\0snoc_lnoc/I/0\0RESERVED";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x0c 0x02>;
+ lut = "lnoc_ddrt0_p0/T/0\0lnoc_ddrt1_p0/T/0\0lnoc_service/T/0\0RESERVED";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x08 0x04>;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x08>;
+ };
+ };
+
+ ErrorLogger3 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 0x20>;
+ description = "Register 3 to log errors";
+ aperture-link = <0x01>;
+ msb-link = <0x04>;
+
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x08 0x08>;
+ aperture-size = <0x35>;
+ aperture-idx,aperture-base = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x00 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x00 0x00 0x00 0x00 0x06 0xc0 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0xe0 0x00 0x00 0x00 0x00 0x00 0x00 0x08 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x09 0x40 0x100 0x00 0x00 0x00 0x00 0x00 0x0a 0x100 0x00 0x00 0x00 0x00 0x00 0x00 0x0b 0x100 0x100 0x00 0x00 0x00 0x00 0x00 0x0c 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x00 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x00 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x00 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x00 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x00 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x00 0x00 0x01 0x00 0x06 0xc0 0x80 0x00 0x00 0x00 0x01 0x00 0x07 0xe0 0x80 0x00 0x00 0x00 0x01 0x00 0x08 0x40 0x80 0x00 0x00 0x00 0x01 0x00 0x09 0x40 0x180 0x00 0x00 0x00 0x01 0x00 0x0a 0x100 0x80 0x00 0x00 0x00 0x01 0x00 0x0b 0x100 0x180 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x01 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x01 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x01 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x01 0x00 0x00 0x00 0x06 0xc0 0x00 0x00 0x01 0x00 0x00 0x00 0x07 0xe0 0x00 0x00 0x01 0x00 0x00 0x00 0x08 0x40 0x00 0x00 0x01 0x00 0x00 0x00 0x09 0x40 0x100 0x00 0x01 0x00 0x00 0x00 0x0a 0x100 0x00 0x00 0x01 0x00 0x00 0x00 0x0b 0x100 0x100 0x00 0x01 0x00 0x00 0x00 0x0c 0x00 0x00 0x00 0x01 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x01 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x01 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x01 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x01 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x01 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x01 0x00 0x01 0x00 0x06 0xc0 0x80 0x00 0x01 0x00 0x01 0x00 0x07 0xe0 0x80 0x00 0x01 0x00 0x01 0x00 0x08 0x40 0x80 0x00 0x01 0x00 0x01 0x00 0x09 0x40 0x180 0x00 0x01 0x00 0x01 0x00 0x0a 0x100 0x80 0x00 0x01 0x00 0x01 0x00 0x0b 0x100 0x180 0x00 0x02 0x00 0x02 0x00 0x00 0x00 0x52080000 0x00 0x02 0x00 0x02 0x00 0x01 0x00 0x72080000 0x00 0x02 0x00 0x02 0x00 0x02 0x00 0x00>;
+ };
+ };
+
+ ErrorLogger4 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x24 0x20>;
+ description = "Register 4 to log errors";
+
+ addr_msb {
+ compatible = "eswin,win2030,bitfield";
+ description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+ offset,length = <0x00 0x09>;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x28 0x20>;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x10>;
+ lut = "Cache_0\0Cache_1\0Cache_2\0Cache_3\0Prot_0\0Prot_1\0Prot_2\0Qos_0\0Qos_1\0Qos_2\0Qos_3\0User_0\0User_1\0User_2\0User_3\0User_4";
+ };
+ };
+ };
+
+ d0_sys_noc@52002C00 {
+ compatible = "eswin,win2030-noc";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ numa-node-id = <0x00>;
+ reg = <0x00 0x52002c00 0x00 0x4000>;
+ interrupts = <0x1af>;
+ interrupt-names = "error";
+ interrupt-parent = <0x10>;
+ errlogger,idx = <0x00 0x01 0x03 0x04 0x05>;
+ eswin,qos-configs = "DSPT\0NPU\0SPISLV_TBU3";
+ eswin,DSPT-qos-base = <0x52002c80>;
+ eswin,DSPT-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x03 0x14 0x01 0x18 0x01>;
+ eswin,NPU-qos-base = "R\0-";
+ eswin,NPU-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x18 0x14 0x10 0x18 0x01>;
+ eswin,SPISLV_TBU3-qos-base = <0x52002d80>;
+ eswin,SPISLV_TBU3-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x18 0x14 0x10 0x18 0x01>;
+ status = "okay";
+ stat,0 = "TracePort:ddr0_p1_req";
+ stat,1 = "TracePort:ddr0_p2_req";
+ stat,2 = "TracePort:ddr1_p1_req";
+ stat,3 = "TracePort:ddr1_p2_req";
+ latency,0 = "TracePort:sysnoc_trans_probe_0\0AddrSize:0x0";
+ latency,1 = "TracePort:sysnoc_trans_probe_1\0Mode:latency\0AddrBase:0x82000000\0AddrSize:0x28\0Opcode:RdWr";
+ pending,0 = "TracePort:sysnoc_trans_probe_2\0AddrSize:0x3";
+
+ sideband_manager@52004000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0x00 0x52004000 0x00 0x10>;
+ SenseIn0 = <0x00 0x00 0x01 0x01 0x02 0x02 0x03 0x03 0x04 0x04 0x05 0x05 0x06 0x06 0x07 0x07 0x08 0x08 0x09 0x09 0x0a 0x0a 0x0b 0x0b 0x0c 0x0c 0x0d 0x0d 0x0e 0x0e 0x0f 0x0f 0x10 0x10 0x11 0x11 0x12 0x12 0x13 0x13 0x14 0x14 0x15 0x15>;
+ bf-name = "SBM_AON_SNOC_SP0\0SBM_DSPT_SNOC\0SBM_JTAG_SNOC\0SBM_MCPUT_SNOC_D2D \0SBM_MCPUT_SNOC_MP\0SBM_MCPUT_SNOC_SP0\0SBM_MCPUT_SNOC_SP1\0SBM_NPU_SNOC_SP0\0SBM_NPU_SNOC_SP1\0SBM_PCIET_SNOC_P\0SBM_SPISLV_PCIET_SNOC\0SBM_TBU4_SNOC\0SBM_TCU_SNOC\0SBM_SNOC_AON\0SBM_SNOC_DDR0_P1\0SBM_SNOC_DDR0_P2\0SBM_SNOC_DDR1_P1\0SBM_SNOC_DDR1_P2\0SBM_SNOC_DSPT\0SBM_SNOC_MCPUT_D2D\0SBM_SNOC_NPU\0SBM_SNOC_PCIET";
+ };
+
+ sysnoc_packet_ddr0_p1_req_probe@52000000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52000000 0x00 0x4000>;
+ clocks = <0x03 0x218>;
+ clock-names = "clk";
+ interrupts = <0x1b7>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr0_p1_req";
+ };
+
+ sysnoc_packet_ddr0_p2_req_probe@52000800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52000800 0x00 0x4000>;
+ clocks = <0x03 0x219>;
+ clock-names = "clk";
+ interrupts = <0x1b5>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr0_p2_req";
+ };
+
+ sysnoc_packet_ddr1_p1_req_probe@52001000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52001000 0x00 0x4000>;
+ clocks = <0x03 0x21d>;
+ clock-names = "clk";
+ interrupts = <0x1b3>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr1_p1_req";
+ };
+
+ sysnoc_packet_ddr1_p2_req_probe@52001800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52001800 0x00 0x4000>;
+ clocks = <0x03 0x21e>;
+ clock-names = "clk";
+ interrupts = <0x1b1>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr1_p2_req";
+ };
+
+ sysnoc_trans_probe_0@52002000 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0x00 0x52002000 0x00 0x4000>;
+ clocks = <0x03 0x203>;
+ clock-names = "clk";
+ interrupts = <0x1ae>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x02>;
+ counter,nr = <0x08>;
+ profiler,nr = <0x01>;
+ portsel = "dspt_snoc\0npu_sp1";
+
+ sysnoc_trans_dspt_filter@52002E00 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52002e00 0x00 0x80>;
+ };
+
+ sysnoc_trans_npu_sp1_filter@52002F80 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52002f80 0x00 0x80>;
+ };
+
+ sysnoc_trans_profiler@52003180 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0x00 0x52003180 0x00 0x80>;
+ };
+ };
+
+ sysnoc_trans_probe_1@52002400 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0x00 0x52002400 0x00 0x4000>;
+ clocks = <0x03 0x203>;
+ clock-names = "clk";
+ interrupts = <0x1ad>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x03>;
+ counter,nr = <0x0c>;
+ profiler,nr = <0x01>;
+ portsel = "mcput_mp\0mcput_sp1\0tcu";
+
+ sysnoc_trans_mcput_mp_filter@52002E80 {
+ status = "okay";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52002e80 0x00 0x80>;
+ };
+
+ sysnoc_trans_mcput_sp1_filter@52002F00 {
+ status = "okay";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52002f00 0x00 0x80>;
+ };
+
+ sysnoc_trans_tcu_filter@52003100 {
+ status = "okay";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52003100 0x00 0x80>;
+ };
+
+ sysnoc_trans_profiler@52003200 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0x00 0x52003200 0x00 0x80>;
+ };
+ };
+
+ sysnoc_trans_probe_2@52002800 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0x00 0x52002800 0x00 0x4000>;
+ clocks = <0x03 0x203>;
+ clock-names = "clk";
+ interrupts = <0x1ac>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x02>;
+ counter,nr = <0x08>;
+ profiler,nr = <0x01>;
+ portsel = "spislv_tbu3\0tbu4_snoc";
+
+ sysnoc_trans_spislv_tbu3_filter@52003000 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52003000 0x00 0x80>;
+ };
+
+ sysnoc_trans_tbu4_filter@52003080 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52003080 0x00 0x80>;
+ };
+
+ sysnoc_trans_profiler@52003280 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0x00 0x52003280 0x00 0x80>;
+ };
+ };
+
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x14 0x20>;
+ description = "Register 0 to log errors";
+
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x01>;
+ lut = "Not Locked\0Locked";
+ };
+
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x01 0x04>;
+ lut = "RD: data read with incrementing address\0RDW: data read with wrapping address\0RDL: allocates monitor in the Target with incrementing address\0RDX: exclusive read with incrementing address\0WR: data write with incrementing address\0WRW: data write with wrapping address\0WRC: conditional write if matching monitor in Target is found\0RSV: reserved\0PRE: preamble packet of linked sequence (locked sequence)\0URG: urgency packet used for QoS (status must be REQ)";
+ };
+
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x08 0x03>;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error\0DEC (error source: Initiator NIU): decode error\0UNS (error source: Target NIU): unsupported access type\0DISC (error source: Power Disconnect): disconnected Target or NoC domain\0SEC (error source: Initiator NIU or Firewall): security error\0HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator\0TMO (error source: Target NIU): time-out\0RSV: reserved";
+ };
+
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x10 0x0c>;
+ };
+
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x1f 0x01>;
+ lut = "NTTP v3.0 (Invalid)\0NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register\0eswin,win2030,noc,filter,routeid";
+ offset,length = <0x18 0x20>;
+ description = "Register 1 to log errors";
+
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x13 0x04>;
+ lut = "aon_snoc_sp0/I/0\0dspt_snoc/I/0\0jtag_snoc/I/0\0mcput_snoc_d2d/I/0\0mcput_snoc_mp/I/0\0mcput_snoc_sp0/I/0\0mcput_snoc_sp1/I/0\0mnoc_snoc/I/0\0npu_snoc_sp0/I/0\0npu_snoc_sp1/I/0\0pciet_snoc_p/I/0\0rnoc_snoc/I/0\0spislv_tbu3_snoc/I/0\0tbu4_snoc/I/0\0tcu_snoc/I/0\0RESERVED0";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x0f 0x04>;
+ lut = "snoc_aon/T/0\0snoc_cnoc/T/0\0snoc_ddrt0_p1/T/0\0snoc_ddrt0_p2/T/0\0snoc_ddrt1_p1/T/0\0snoc_ddrt1_p2/T/0\0snoc_dspt/T/0\0snoc_lnoc/T/0\0snoc_mcput_d2d/T/0\0snoc_mnoc/T/0\0snoc_npu/T/0\0snoc_pciet/T/0\0snoc_rnoc/T/0\0snoc_service/T/0\0RESERVED1\0RESERVED2";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x09 0x06>;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x09>;
+ };
+ };
+
+ ErrorLogger3 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 0x20>;
+ description = "Register 3 to log errors";
+ aperture-link = <0x01>;
+ msb-link = <0x04>;
+
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x09 0x0e>;
+ aperture-size = <0x49d>;
+ aperture-idx,aperture-base = <0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x52060000 0x00 0x00 0x00 0x01 0x00 0x01 0x00 0x72060000 0x00 0x00 0x00 0x01 0x00 0x02 0x00 0x52100000 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x52200000 0x00 0x00 0x00 0x01 0x00 0x04 0x00 0x52300000 0x00 0x00 0x00 0x01 0x00 0x05 0x00 0x72100000 0x00 0x00 0x00 0x01 0x00 0x06 0x00 0x72200000 0x00 0x00 0x00 0x01 0x00 0x07 0x00 0x72300000 0x00 0x00 0x00 0x01 0x00 0x08 0x00 0x53000000 0x00 0x00 0x00 0x01 0x00 0x09 0x00 0x73000000 0x00 0x00 0x00 0x01 0x00 0x0a 0x00 0x50000000 0x00 0x00 0x00 0x01 0x00 0x0b 0x00 0x70000000 0x00 0x00 0x00 0x01 0x00 0x0c 0x00 0x54000000 0x00 0x00 0x00 0x01 0x00 0x0d 0x00 0x74000000 0x00 0x00 0x00 0x01 0x00 0x0e 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x0f 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x10 0x00 0x00 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x520e0000 0x00 0x00 0x00 0x06 0x00 0x01 0x00 0x720e0000 0x00 0x00 0x00 0x06 0x00 0x02 0x00 0x5b000000 0x00 0x00 0x00 0x06 0x00 0x03 0x00 0x7b000000 0x00 0x00 0x00 0x07 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+ };
+ };
+
+ ErrorLogger4 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x24 0x20>;
+ description = "Register 4 to log errors";
+
+ addr_msb {
+ compatible = "eswin,win2030,bitfield";
+ description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+ offset,length = <0x00 0x09>;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x28 0x20>;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x12>;
+ lut = "Cache_0\0Cache_1\0Cache_2\0Cache_3\0Prot_0 \0Prot_1 \0Prot_2 \0User_0 \0User_1 \0User_2 \0User_3 \0User_4 \0User_5 \0User_6 \0qos0\0qos1\0qos2\0qos3";
+ };
+ };
+ };
+
+ d0_media_noc@52021400 {
+ compatible = "eswin,win2030-noc";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ numa-node-id = <0x00>;
+ reg = <0x00 0x52021400 0x00 0x4000>;
+ interrupts = <0x1c6>;
+ interrupt-names = "error";
+ interrupt-parent = <0x10>;
+ errlogger,idx = <0x00 0x01 0x03 0x04 0x05>;
+ eswin,qos-configs = "GPU\0TBU2\0VC";
+ eswin,GPU-qos-base = <0x52021480>;
+ eswin,GPU-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x1e0 0x14 0x01 0x18 0x01>;
+ eswin,TBU2-qos-base = <0x52021500>;
+ eswin,TBU2-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x18 0x14 0x10 0x18 0x01>;
+ eswin,VC-qos-base = <0x52021580>;
+ eswin,VC-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x18 0x14 0x10 0x18 0x01>;
+ status = "okay";
+ stat,0 = "TracePort:ddr0_p3_req";
+ stat,1 = "TracePort:ddr1_p3_req";
+
+ sideband_manager@52022000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0x00 0x52022000 0x00 0x10>;
+ SenseIn0 = <0x46 0x00 0x47 0x01 0x48 0x02 0x49 0x03 0x4a 0x04>;
+ bf-name = "SBM_MNOC_GPU\0SBM_MNOC_TBU2\0SBM_MNOC_VC\0SBM_MNOC_DDRT0_P3\0SBM_MNOC_DDRT1_P3";
+ };
+
+ mnoc_packet_ddr0_p3_req_probe@52020000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52020000 0x00 0x4000>;
+ clocks = <0x03 0x21a>;
+ clock-names = "clk";
+ interrupts = <0x1ca>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr0_p3_req";
+ };
+
+ mnoc_packet_ddr1_p3_req_probe@52020800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52020800 0x00 0x4000>;
+ clocks = <0x03 0x21f>;
+ clock-names = "clk";
+ interrupts = <0x1c8>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr1_p3_req";
+ };
+
+ mnoc_trans_probe@52021000 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0x00 0x52021000 0x00 0x4000>;
+ clocks = <0x03 0x203>;
+ clock-names = "clk";
+ interrupts = <0x1c5>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x03>;
+ counter,nr = <0x0c>;
+ profiler,nr = <0x01>;
+ portsel = "gpu\0tbu2\0vc";
+
+ mnoc_trans_gpu_filter@52021600 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52021600 0x00 0x80>;
+ };
+
+ mnoc_trans_tbu2_filter@52021680 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52021680 0x00 0x80>;
+ };
+
+ mnoc_trans_vc_filter@52021700 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52021700 0x00 0x80>;
+ };
+
+ mnoc_trans_profiler@52021780 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0x00 0x52021780 0x00 0x80>;
+ };
+ };
+
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x14 0x20>;
+ description = "Register 0 to log errors";
+
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x01>;
+ lut = "Not Locked\0Locked";
+ };
+
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x01 0x04>;
+ lut = "RD: data read with incrementing address\0RDW: data read with wrapping address\0RDL: allocates monitor in the Target with incrementing address\0RDX: exclusive read with incrementing address\0WR: data write with incrementing address\0WRW: data write with wrapping address\0WRC: conditional write if matching monitor in Target is found\0RSV: reserved\0PRE: preamble packet of linked sequence (locked sequence)\0URG: urgency packet used for QoS (status must be REQ)";
+ };
+
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x08 0x03>;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error\0DEC (error source: Initiator NIU): decode error\0UNS (error source: Target NIU): unsupported access type\0DISC (error source: Power Disconnect): disconnected Target or NoC domain\0SEC (error source: Initiator NIU or Firewall): security error\0HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator\0TMO (error source: Target NIU): time-out\0RSV: reserved";
+ };
+
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x10 0x0c>;
+ };
+
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x1f 0x01>;
+ lut = "NTTP v3.0 (Invalid)\0NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register\0eswin,win2030,noc,filter,routeid";
+ offset,length = <0x18 0x20>;
+ description = "Register 1 to log errors";
+
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x0e 0x02>;
+ lut = "gpu_mnoc/I/0\0snoc_mnoc/I/0\0tbu2_mnoc/I/0\0vc_mnoc/I/0";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x0c 0x02>;
+ lut = "mnoc_ddrt0_p3/T/0\0mnoc_ddrt1_p3/T/0\0mnoc_service/T/0\0mnoc_snoc/T/0";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x09 0x03>;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x09>;
+ };
+ };
+
+ ErrorLogger3 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 0x20>;
+ description = "Register 3 to log errors";
+ aperture-link = <0x01>;
+ msb-link = <0x04>;
+
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x09 0x07>;
+ aperture-size = <0x37>;
+ aperture-idx,aperture-base = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x00 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x00 0x00 0x00 0x00 0x06 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0x40 0x100 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x00 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x00 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x00 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x00 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x00 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x00 0x00 0x01 0x00 0x06 0x40 0x80 0x00 0x00 0x00 0x01 0x00 0x07 0x40 0x180 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x02 0x00 0x00 0x00 0x52020000 0x00 0x01 0x00 0x02 0x00 0x01 0x00 0x72020000 0x00 0x01 0x00 0x02 0x00 0x02 0x00 0x00 0x00 0x01 0x00 0x02 0x00 0x03 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x02 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x02 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x02 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x02 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x02 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x02 0x00 0x00 0x00 0x06 0x40 0x00 0x00 0x02 0x00 0x00 0x00 0x07 0x40 0x100 0x00 0x02 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x02 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x02 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x02 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x02 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x02 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x02 0x00 0x01 0x00 0x06 0x40 0x80 0x00 0x02 0x00 0x01 0x00 0x07 0x40 0x180 0x00 0x02 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x03 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x03 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x03 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x03 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x03 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x03 0x00 0x00 0x00 0x06 0x40 0x00 0x00 0x03 0x00 0x00 0x00 0x07 0x40 0x100 0x00 0x03 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x03 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x03 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x03 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x03 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x03 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x03 0x00 0x01 0x00 0x06 0x40 0x80 0x00 0x03 0x00 0x01 0x00 0x07 0x40 0x180 0x00 0x03 0x00 0x03 0x00 0x00 0x00 0x00>;
+ };
+ };
+
+ ErrorLogger4 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x24 0x20>;
+ description = "Register 4 to log errors";
+
+ addr_msb {
+ compatible = "eswin,win2030,bitfield";
+ description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+ offset,length = <0x00 0x09>;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x28 0x20>;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x12>;
+ lut = "Cache_0\0Cache_1\0Cache_2\0Cache_3\0Prot_0 \0Prot_1 \0Prot_2 \0User_0 \0User_1 \0User_2 \0User_3 \0User_4 \0User_5 \0User_6 \0qos0\0qos1\0qos2\0qos3";
+ };
+ };
+ };
+
+ d0_realtime_noc@52041400 {
+ compatible = "eswin,win2030-noc";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ numa-node-id = <0x00>;
+ reg = <0x00 0x52041400 0x00 0x4000>;
+ interrupts = <0x1c0>;
+ interrupt-names = "error";
+ interrupt-parent = <0x10>;
+ errlogger,idx = <0x00 0x01 0x03 0x04 0x05>;
+ eswin,qos-configs = "TBU0\0VO";
+ eswin,TBU0-qos-base = <0x52041480>;
+ eswin,TBU0-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x1e0 0x14 0x01 0x18 0x01>;
+ eswin,VO-qos-base = <0x52041500>;
+ eswin,VO-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x18 0x14 0x10 0x18 0x01>;
+ status = "okay";
+ stat,0 = "TracePort:ddr0_p4_req";
+ stat,1 = "TracePort:ddr1_p4_req";
+
+ sideband_manager@52042000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0x00 0x52042000 0x00 0x10>;
+ SenseIn0 = <0x50 0x00 0x51 0x01 0x52 0x02 0x53 0x03>;
+ bf-name = "SBM_RNOC_TBU0\0SBM_RNOC_VO\0SBM_RNOC_DDRT0_P4\0SBM_RNOC_DDRT1_P4";
+ };
+
+ rnoc_packet_ddr0_p4_req_probe@52040000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52040000 0x00 0x4000>;
+ clocks = <0x03 0x21b>;
+ clock-names = "clk";
+ interrupts = <0x1c4>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr0_p4_req";
+ };
+
+ rnoc_packet_ddr1_p4_req_probe@52040800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52040800 0x00 0x4000>;
+ clocks = <0x03 0x220>;
+ clock-names = "clk";
+ interrupts = <0x1c2>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr1_p4_req";
+ };
+
+ rnoc_trans_probe@52041000 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0x00 0x52041000 0x00 0x4000>;
+ clocks = <0x03 0x203>;
+ clock-names = "clk";
+ interrupts = <0x1bf>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x02>;
+ counter,nr = <0x08>;
+ profiler,nr = <0x01>;
+ portsel = "tbu0\0vo";
+
+ rnoc_trans_tbu0_filter@52041580 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52041580 0x00 0x80>;
+ };
+
+ rnoc_trans_vo_filter@52041600 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52041600 0x00 0x80>;
+ };
+
+ rnoc_trans_profiler@52041680 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0x00 0x52041680 0x00 0x80>;
+ };
+ };
+
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x14 0x20>;
+ description = "Register 0 to log errors";
+
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x01>;
+ lut = "Not Locked\0Locked";
+ };
+
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x01 0x04>;
+ lut = "RD: data read with incrementing address\0RDW: data read with wrapping address\0RDL: allocates monitor in the Target with incrementing address\0RDX: exclusive read with incrementing address\0WR: data write with incrementing address\0WRW: data write with wrapping address\0WRC: conditional write if matching monitor in Target is found\0RSV: reserved\0PRE: preamble packet of linked sequence (locked sequence)\0URG: urgency packet used for QoS (status must be REQ)";
+ };
+
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x08 0x03>;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error\0DEC (error source: Initiator NIU): decode error\0UNS (error source: Target NIU): unsupported access type\0DISC (error source: Power Disconnect): disconnected Target or NoC domain\0SEC (error source: Initiator NIU or Firewall): security error\0HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator\0TMO (error source: Target NIU): time-out\0RSV: reserved";
+ };
+
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x10 0x0c>;
+ };
+
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x1f 0x01>;
+ lut = "NTTP v3.0 (Invalid)\0NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register\0eswin,win2030,noc,filter,routeid";
+ offset,length = <0x18 0x20>;
+ description = "Register 1 to log errors";
+
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x0e 0x02>;
+ lut = "snoc_rnoc/I/0\0tbu0_rnoc/I/0\0vo_rnoc/I/0\0RESERVED0";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x0c 0x02>;
+ lut = "rnoc_ddrt0_p4/T/0\0rnoc_ddrt1_p4/T/0\0rnoc_service/T/0\0rnoc_snoc/T/0";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x09 0x03>;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x09>;
+ };
+ };
+
+ ErrorLogger3 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 0x20>;
+ description = "Register 3 to log errors";
+ aperture-link = <0x01>;
+ msb-link = <0x04>;
+
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x09 0x07>;
+ aperture-size = <0x28>;
+ aperture-idx,aperture-base = <0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x52040000 0x00 0x00 0x00 0x02 0x00 0x01 0x00 0x72040000 0x00 0x00 0x00 0x02 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x03 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x01 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x01 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x01 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x01 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x01 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x01 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x01 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x01 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x01 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x01 0x00 0x03 0x00 0x00 0x00 0x59000000 0x00 0x01 0x00 0x03 0x00 0x01 0x00 0x79000000 0x00 0x01 0x00 0x03 0x00 0x02 0x140 0x1000000 0x00 0x01 0x00 0x03 0x00 0x03 0x140 0x9000000 0x00 0x01 0x00 0x03 0x00 0x04 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x02 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x02 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x02 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x02 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x02 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x02 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x02 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x02 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x02 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x02 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x02 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x02 0x00 0x03 0x00 0x00 0x00 0x59000000 0x00 0x02 0x00 0x03 0x00 0x01 0x00 0x79000000 0x00 0x02 0x00 0x03 0x00 0x02 0x140 0x1000000 0x00 0x02 0x00 0x03 0x00 0x03 0x140 0x9000000 0x00 0x02 0x00 0x03 0x00 0x04 0x00 0x00 0x00 0x02 0x00 0x03 0x00 0x05 0x00 0x00>;
+ };
+ };
+
+ ErrorLogger4 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x24 0x20>;
+ description = "Register 4 to log errors";
+
+ addr_msb {
+ compatible = "eswin,win2030,bitfield";
+ description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+ offset,length = <0x00 0x09>;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x28 0x20>;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x10>;
+ lut = "Cache_0\0Cache_1\0Cache_2\0Cache_3\0Prot_0 \0Prot_1 \0Prot_2 \0User_0 \0User_1 \0User_2 \0User_3 \0User_4 \0qos0\0qos1\0qos2\0qos3";
+ };
+ };
+ };
+ };
+
+ eswin-npu@51c00000 {
+ compatible = "eswin,npu";
+ reg = <0x00 0x51c00000 0x00 0x400000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x183 0x10>;
+ #size-cells = <0x02>;
+ dma-ranges = <0x01 0x00 0x00 0xc0000000 0x1ff 0x00>;
+ iommus = <0x19 0x04>;
+ tbus = <0x05>;
+ dsp-avail-num = <0x01>;
+ spram-size = <0x400000>;
+ npu_mbox = <0x21>;
+ clocks = <0x03 0x236 0x03 0x237 0x03 0x23c 0x03 0x23d 0x03 0x26 0x03 0x0b 0x03 0x07>;
+ clock-names = "aclk\0cfg_clk\0core_clk\0e31_core_clk\0mux_u_npu_core_3mux1_gfree\0fixed_rate_clk_spll2_fout2\0fixed_rate_clk_spll1_fout1";
+ resets = <0x18 0x06 0x08>;
+ reset-names = "e31_core";
+ operating-points-v2 = <0x22>;
+ numa-node-id = <0x00>;
+ firmware-name = "eic7700_die0_e31_fw";
+ dma-noncoherent;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x00>;
+ status = "okay";
+ npu-supply = <0x23>;
+ };
+
+ llc@51c00000 {
+ compatible = "eswin,llc";
+ reg = <0x00 0x51c00000 0x00 0x400000>;
+ eswin,syscfg = <0x17 0x324>;
+ eswin,syscrg_csr = <0x15>;
+ clocks = <0x03 0x236 0x03 0x237 0x03 0x23a 0x03 0x23c 0x03 0x26 0x03 0x0b 0x03 0x07>;
+ clock-names = "aclk\0cfg_clk\0llc_clk\0core_clk\0mux_u_npu_core_3mux1_gfree\0fixed_rate_clk_spll2_fout2\0fixed_rate_clk_spll1_fout1";
+ resets = <0x18 0x06 0x01 0x18 0x06 0x02 0x18 0x06 0x04 0x18 0x06 0x40>;
+ reset-names = "axi\0cfg\0core\0llc";
+ numa-node-id = <0x00>;
+ spram-region = <0x24>;
+ npu-supply = <0x23>;
+ status = "okay";
+ };
+
+ dsp_subsys@52280400 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x52280400 0x00 0x10000 0x00 0x51810000 0x00 0x8000>;
+ ranges;
+ numa-node-id = <0x00>;
+ dma-ranges = <0x00 0x30000000 0x00 0xc0000000 0x00 0xce000000>;
+ compatible = "es-dsp-subsys\0simple-bus";
+ clocks = <0x03 0x210 0x03 0x20f>;
+ clock-names = "cfg_clk\0aclk";
+ resets = <0x18 0x02 0x01 0x18 0x02 0x02 0x18 0x02 0x04 0x18 0x02 0x10 0x18 0x02 0x20 0x18 0x02 0x40 0x18 0x02 0x80>;
+ reset-names = "axi\0cfg\0div4\0div_0\0div_1\0div_2\0div_3";
+ status = "okay";
+
+ es_dsp@0 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b000000 0x8000 0x28100000 0x00 0x5b100000 0x20000 0x28120000 0x00 0x5b120000 0x20000>;
+ clocks = <0x03 0x2a8>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x25>;
+ dsp_mbox = <0x26>;
+ device-irq = <0x0b 0x50a90000 0x20 0x50a80000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x00>;
+ iommus = <0x19 0x12>;
+ tbus = <0x70>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ es_dsp@1 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b008000 0x8000 0x28100000 0x00 0x5b140000 0x20000 0x28120000 0x00 0x5b160000 0x20000>;
+ clocks = <0x03 0x2a9>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x25>;
+ dsp_mbox = <0x27>;
+ device-irq = <0x0d 0x50ab0000 0x40 0x50aa0000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x01>;
+ iommus = <0x19 0x13>;
+ tbus = <0x71>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ es_dsp@2 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b010000 0x8000 0x28100000 0x00 0x5b180000 0x20000 0x28120000 0x00 0x5b1a0000 0x20000>;
+ clocks = <0x03 0x2aa>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x25>;
+ dsp_mbox = <0x28>;
+ device-irq = <0x0f 0x50ad0000 0x80 0x50ac0000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x02>;
+ iommus = <0x19 0x14>;
+ tbus = <0x72>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ es_dsp@3 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b018000 0x8000 0x28100000 0x00 0x5b1c0000 0x20000 0x28120000 0x00 0x5b1e0000 0x20000>;
+ clocks = <0x03 0x2ab>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x25>;
+ dsp_mbox = <0x29>;
+ device-irq = <0x11 0x50af0000 0x100 0x50ae0000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x03>;
+ iommus = <0x19 0x15>;
+ tbus = <0x73>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ sofdsp@4 {
+ #sound-dai-cells = <0x01>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "eswin,sof-dsp";
+ reg = <0x00 0x5b018000 0x00 0x8000 0x00 0x5b1c0000 0x00 0x40000>;
+ mbox-names = "dsp-mbox";
+ mboxes = <0x29 0x00>;
+ clocks = <0x03 0x2ab>;
+ clock-names = "aclk";
+ process-id = <0x03>;
+ iommus = <0x19 0x15>;
+ tbus = <0x73>;
+ dma-noncoherent;
+ mailbox-dsp-to-u84-addr = <0x50af0000>;
+ mailbox-u84-to-dsp-addr = <0x50ae0000>;
+ dsp-uart = <0x2a>;
+ device-uart-mutex = <0x51820000>;
+ numa-node-id = <0x00>;
+ };
+ };
+
+ g2d@50140000 {
+ compatible = "eswin,galcore_d0";
+ clocks = <0x03 0x254 0x03 0x255 0x03 0x25a 0x03 0x25b 0x03 0x25c 0x03 0x25d 0x03 0x2b1>;
+ clock-names = "vc_aclk\0vc_cfg\0g2d_cfg\0g2d_st2\0g2d_clk\0g2d_aclk\0mon_pclk";
+ resets = <0x18 0x16 0x02 0x18 0x16 0x01 0x18 0x16 0x04 0x18 0x1b 0x01 0x18 0x1b 0x02 0x18 0x1b 0x04>;
+ reset-names = "axi\0cfg\0moncfg\0g2d_core\0g2d_cfg\0g2d_axi";
+ reg = <0x00 0x50140000 0x00 0x40000 0x00 0x50180000 0x00 0x40000>;
+ reg-names = "core_2d\0core_2d1";
+ fe-apb-offset = <0x800>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x31 0x32>;
+ interrupt-names = "core_2d\0core_2d1";
+ enable-mmu = <0x01>;
+ contiguous-size = <0xa00000>;
+ recovery = <0x00>;
+ dma-noncoherent;
+ operating-points-v2 = <0x2b>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ };
+
+ gpu@51400000 {
+ compatible = "img,gpu";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x51400000 0x00 0xfffff>;
+ clocks = <0x03 0x20b 0x03 0x20c 0x03 0x20d>;
+ clock-names = "aclk\0gray_clk\0cfg_clk";
+ resets = <0x18 0x01 0x01 0x18 0x01 0x02 0x18 0x01 0x04 0x18 0x01 0x08 0x18 0x01 0x10>;
+ reset-names = "axi\0cfg\0gray\0jones\0spu";
+ interrupt-parent = <0x10>;
+ interrupts = <0x0f>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x00>;
+ status = "okay";
+ };
+
+ sata@0x50420000 {
+ compatible = "snps,eswin-ahci";
+ reg = <0x00 0x50420000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupt-names = "intrq\0msi\0pme";
+ interrupts = <0x3a 0x3b 0x3c>;
+ ports-implemented = <0x01>;
+ resets = <0x18 0x07 0x8000000>;
+ reset-names = "apb";
+ #size-cells = <0x02>;
+ iommus = <0x19 0x0e>;
+ tbus = <0x02>;
+ dma-ranges = <0x00 0x00 0x00 0xc0000000 0x200 0x00>;
+ eswin,hsp_sp_csr = <0x1a 0x1050>;
+ eswin,syscrg_csr = <0x15 0x41c>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <0x2c>;
+ };
+
+ pcie@0x54000000 {
+ compatible = "eswin,win2030-pcie";
+ clocks = <0x03 0x232 0x03 0x233 0x03 0x234 0x03 0x235>;
+ clock-names = "pcie_aclk\0pcie_cfg_clk\0pcie_cr_clk\0pcie_aux_clk";
+ reset-names = "pcie_cfg\0pcie_powerup\0pcie_pwren";
+ resets = <0x18 0x08 0x01 0x18 0x08 0x02 0x18 0x08 0x04>;
+ #address-cells = <0x03>;
+ #size-cells = <0x02>;
+ #interrupt-cells = <0x01>;
+ reg = <0x00 0x54000000 0x00 0x4000000 0x00 0x40000000 0x00 0x800000 0x00 0x50000000 0x00 0x100000>;
+ reg-names = "dbi\0config\0mgmt";
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0x00 0x40800000 0x00 0x40800000 0x00 0x800000 0x82000000 0x00 0x41000000 0x00 0x41000000 0x00 0xf000000 0xc3000000 0x80 0x00 0x80 0x00 0x02 0x00>;
+ num-lanes = <0x04>;
+ interrupts = <0xdc 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba>;
+ interrupt-names = "msi\0inta\0intb\0intc\0intd";
+ interrupt-parent = <0x10>;
+ interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+ interrupt-map = <0x00 0x00 0x00 0x01 0x10 0xb3 0x00 0x00 0x00 0x02 0x10 0xb4 0x00 0x00 0x00 0x03 0x10 0xb5 0x00 0x00 0x00 0x04 0x10 0xb6>;
+ iommus = <0x19 0xfe0000>;
+ iommu-map = <0x00 0x19 0xff0000 0xffffff>;
+ tbus = <0x03>;
+ status = "okay";
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ };
+
+ spi@50810000 {
+ compatible = "snps,eic770x-spi";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x50810000 0x00 0x4000>;
+ spi-max-frequency = "\0I>";
+ clocks = <0x03 0x29c>;
+ clock-names = "clk";
+ interrupt-parent = <0x10>;
+ interrupts = <0x5b>;
+ resets = <0x18 0x10 0x01>;
+ reset-names = "spi";
+ numa-node-id = <0x00>;
+ status = "disabled";
+ dma-noncoherent;
+ };
+
+ spi@50814000 {
+ compatible = "snps,eic770x-spi";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x50814000 0x00 0x4000>;
+ spi-max-frequency = "\0I>";
+ clocks = <0x03 0x29d>;
+ clock-names = "clk";
+ interrupt-parent = <0x10>;
+ interrupts = <0x5c>;
+ resets = <0x18 0x10 0x02>;
+ reset-names = "spi";
+ numa-node-id = <0x00>;
+ status = "disabled";
+ dma-noncoherent;
+ };
+
+ spi@51800000 {
+ compatible = "eswin,bootspi";
+ reg = <0x00 0x51800000 0x00 0x8000 0x00 0x51828000 0x00 0x8000 0x00 0x5c000000 0x00 0x8000>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ clocks = <0x03 0x205 0x03 0x204>;
+ clock-names = "cfg_clk\0clk";
+ resets = <0x18 0x24 0x02>;
+ reset-names = "rst";
+ spi-max-frequency = "\0I>";
+ reg-io-width = <0x04>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ num-cs = <0x01>;
+ cs-gpios = <0x1d 0x00 0x01>;
+ wp-gpios = <0x1d 0x04 0x01>;
+
+ spi-flash@0 {
+ compatible = "winbond,w25q128jw\0jedec,spi-nor";
+ reg = <0x00>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ spi-max-frequency = "\0I>";
+ rx-sample-delay-ns = <0x0a>;
+ };
+ };
+
+ mmc@50450000 {
+ compatible = "eswin,emmc-sdhci-5.1";
+ reg = <0x00 0x50450000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x4f>;
+ assigned-clocks = <0x03 0x22a>;
+ assigned-clock-rates = <0xbebc200>;
+ clocks = <0x03 0x22a 0x03 0x222>;
+ clock-names = "clk_xin\0clk_ahb";
+ clock-output-names = "emmc_cardclock";
+ #clock-cells = <0x00>;
+ resets = <0x18 0x07 0x40 0x18 0x07 0x08 0x18 0x07 0x80000 0x18 0x07 0x800000>;
+ reset-names = "txrx_rst\0phy_rst\0prstn\0arstn";
+ core-clk-reg = <0x51828160>;
+ disable-cqe-dcmd;
+ bus-width = <0x08>;
+ non-removable;
+ mmc-hs400-1_8v;
+ max-frequency = <0xbebc200>;
+ #size-cells = <0x02>;
+ iommus = <0x19 0x0f>;
+ tbus = <0x02>;
+ dma-ranges = <0x00 0x00 0x00 0xc0000000 0x01 0x00>;
+ eswin,hsp_sp_csr = <0x1a 0x1038 0x508 0x50c>;
+ eswin,syscrg_csr = <0x15 0x160 0x148 0x14c>;
+ status = "okay";
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ delay_code = <0x17>;
+ drive-impedance-ohm = <0x32>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x2d>;
+ no-sdio;
+ no-sd;
+ };
+
+ mmc@0x50460000 {
+ compatible = "eswin,sdhci-sdio";
+ reg = <0x00 0x50460000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x51>;
+ clocks = <0x03 0x22b 0x03 0x222 0x03 0x0c 0x03 0x23>;
+ clock-names = "clk_xin\0clk_ahb\0clk_spll2_fout3\0clk_mux1_1";
+ clock-output-names = "sdio0_cardclock";
+ #clock-cells = <0x00>;
+ resets = <0x18 0x07 0x80 0x18 0x07 0x10 0x18 0x07 0x40000 0x18 0x07 0x400000>;
+ reset-names = "txrx_rst\0phy_rst\0prstn\0arstn";
+ clock-frequency = <0xc65d400>;
+ max-frequency = <0xc65d400>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ dma-ranges = <0x00 0x20000000 0x00 0xc0000000 0x00 0x40000000>;
+ iommus = <0x19 0x10>;
+ tbus = <0x02>;
+ eswin,hsp_sp_csr = <0x1a 0x103c 0x608 0x60c>;
+ eswin,syscrg_csr = <0x15 0x164 0x148 0x14c>;
+ bus-width = <0x04>;
+ sdio-id = <0x00>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ dma-noncoherent;
+ delay_code = <0x55>;
+ drive-impedance-ohm = <0x21>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ no-sdio;
+ no-mmc;
+ };
+
+ mmc@0x50470000 {
+ compatible = "eswin,sdhci-sdio";
+ reg = <0x00 0x50470000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x53>;
+ clocks = <0x03 0x22c 0x03 0x222 0x03 0x0c 0x03 0x23>;
+ clock-names = "clk_xin\0clk_ahb\0clk_spll2_fout3\0clk_mux1_1";
+ clock-output-names = "sdio1_cardclock";
+ #clock-cells = <0x00>;
+ resets = <0x18 0x07 0x100 0x18 0x07 0x20 0x18 0x07 0x20000 0x18 0x07 0x200000>;
+ reset-names = "txrx_rst\0phy_rst\0prstn\0arstn";
+ clock-frequency = <0xc65d400>;
+ max-frequency = <0xc65d400>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ dma-ranges = <0x00 0x20000000 0x00 0xc0000000 0x00 0x40000000>;
+ iommus = <0x19 0x11>;
+ tbus = <0x02>;
+ eswin,hsp_sp_csr = <0x1a 0x1040 0x708 0x70c>;
+ eswin,syscrg_csr = <0x15 0x168 0x148 0x14c>;
+ bus-width = <0x04>;
+ sdio-id = <0x01>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ dma-noncoherent;
+ delay_code = <0x29>;
+ drive-impedance-ohm = <0x21>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ non-removable;
+ keep-power-in-suspend;
+ no-sd;
+ no-mmc;
+
+ wifi_aw3155@0 {
+ compatible = "aml_w1_sdio";
+ reg = <0x00>;
+ interrupt-parent = <0x2e>;
+ interrupts = <0x0f 0x08>;
+ pinctrl-names = "default\0default";
+ pinctrl-0 = <0x2f>;
+ pinctrl-1 = <0x30>;
+ irq-gpios = <0x2e 0x0f 0x00>;
+ rst-gpios = <0x16 0x0f 0x00>;
+ };
+ };
+
+ video-decoder0@50100000 {
+ compatible = "eswin,video-decoder0";
+ clocks = <0x03 0x254 0x03 0x255 0x03 0x257 0x03 0x259 0x03 0x2e 0x03 0x04 0x03 0x0a 0x03 0x2ae 0x03 0x2b0 0x03 0x2b1>;
+ clock-names = "aclk\0cfg_clk\0jd_clk\0vd_clk\0vc_mux\0spll0_fout1\0spll2_fout1\0jd_pclk\0vd_pclk\0mon_pclk";
+ resets = <0x18 0x16 0x02 0x18 0x16 0x01 0x18 0x16 0x04 0x18 0x17 0x01 0x18 0x17 0x02 0x18 0x19 0x01 0x18 0x19 0x02>;
+ reset-names = "axi\0cfg\0moncfg\0jd_cfg\0jd_axi\0vd_cfg\0vd_axi";
+ eswin,syscfg = <0x17 0x00 0x04>;
+ operating-points-v2 = <0x31>;
+ vcmd-core = <0x00 0x6c>;
+ axife-core = <0x200 0x100>;
+ vdec-core = <0x800 0xc00>;
+ interrupt-parent = <0x10>;
+ #size-cells = <0x02>;
+ dma-ranges = <0x00 0x00 0x00 0x80000000 0x200 0x00>;
+ iommus = <0x19 0x02>;
+ vccsr-reg = <0x00 0x501c0000 0x00 0x1000>;
+ numa-node-id = <0x00>;
+ tbus = <0x10 0x13>;
+ dma-noncoherent;
+ status = "okay";
+
+ vdec0@50100000 {
+ core-name = "video-dec0";
+ base-addr = <0x50100000>;
+ interrupts = <0xec>;
+ };
+
+ jdec0@50120000 {
+ core-name = "jpeg-dec0";
+ base-addr = <0x50120000>;
+ interrupts = <0xed>;
+ };
+ };
+
+ video-encoder@50110000 {
+ compatible = "eswin,video-encoder0";
+ clocks = <0x03 0x254 0x03 0x255 0x03 0x256 0x03 0x258 0x03 0x2e 0x03 0x04 0x03 0x0a 0x03 0x2ad 0x03 0x2af 0x03 0x2b1>;
+ clock-names = "aclk\0cfg_clk\0je_clk\0ve_clk\0vc_mux\0spll0_fout1\0spll2_fout1\0je_pclk\0ve_pclk\0mon_pclk";
+ resets = <0x18 0x16 0x02 0x18 0x16 0x01 0x18 0x16 0x04 0x18 0x18 0x01 0x18 0x18 0x02 0x18 0x1a 0x02 0x18 0x1a 0x01>;
+ reset-names = "axi\0cfg\0moncfg\0je_cfg\0je_axi\0ve_cfg\0ve_axi";
+ eswin,syscfg = <0x17 0x00 0x04>;
+ operating-points-v2 = <0x32>;
+ vcmd-core = <0x00 0x6c>;
+ axife-core = <0x2000 0x7d0>;
+ venc-core = <0x1000 0x87c>;
+ interrupt-parent = <0x10>;
+ #size-cells = <0x02>;
+ dma-ranges = <0x00 0x00 0x00 0x80000000 0x200 0x00>;
+ iommus = <0x19 0x03>;
+ vccsr-reg = <0x00 0x501c0000 0x00 0x1000>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+
+ venc0@50110000 {
+ core-name = "video-enc0";
+ base-addr = <0x50110000>;
+ interrupts = <0xe5>;
+ tbus = <0x11>;
+ };
+
+ jenc0@50130000 {
+ core-name = "jpeg-enc0";
+ base-addr = <0x50130000>;
+ interrupts = <0xe8>;
+ tbus = <0x12>;
+ };
+ };
+
+ mbox@50a00000 {
+ compatible = "eswin,win2030-mailbox";
+ reg = <0x00 0x50a00000 0x00 0x10000 0x00 0x50a10000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x75>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x27e 0x03 0x27f>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x18 0x0c 0x01 0x18 0x0c 0x02>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x02>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x33>;
+ };
+
+ mbox@50a20000 {
+ compatible = "eswin,win2030-mailbox";
+ reg = <0x00 0x50a20000 0x00 0x10000 0x00 0x50a30000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x77>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x280 0x03 0x281>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x18 0x0c 0x04 0x18 0x0c 0x08>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x04>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x34>;
+ };
+
+ mbox@50a40000 {
+ compatible = "eswin,npu0-mailbox";
+ reg = <0x00 0x50a40000 0x00 0x10000 0x00 0x50a50000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x79>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x282 0x03 0x283>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x18 0x0c 0x10 0x18 0x0c 0x20>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x08>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x21>;
+ };
+
+ mbox@50a60000 {
+ compatible = "eswin,win2030-mailbox";
+ reg = <0x00 0x50a60000 0x00 0x10000 0x00 0x50a70000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x7b>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x284 0x03 0x285>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x18 0x0c 0x40 0x18 0x0c 0x80>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x10>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ };
+
+ mbox@50a80000 {
+ compatible = "eswin,dsp0-mailbox";
+ reg = <0x00 0x50a80000 0x00 0x10000 0x00 0x50a90000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x7d>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x286 0x03 0x287>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x18 0x0c 0x100 0x18 0x0c 0x200>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x20>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x26>;
+ };
+
+ mbox@50aa0000 {
+ compatible = "eswin,dsp1-mailbox";
+ reg = <0x00 0x50aa0000 0x00 0x10000 0x00 0x50ab0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x7f>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x288 0x03 0x289>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x18 0x0c 0x400 0x18 0x0c 0x800>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x40>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x27>;
+ };
+
+ mbox@50ac0000 {
+ compatible = "eswin,dsp2-mailbox";
+ reg = <0x00 0x50ac0000 0x00 0x10000 0x00 0x50ad0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x81>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x28a 0x03 0x28b>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x18 0x0c 0x1000 0x18 0x0c 0x2000>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x80>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x28>;
+ };
+
+ mbox@50ae0000 {
+ compatible = "eswin,dsp3-mailbox";
+ reg = <0x00 0x50ae0000 0x00 0x10000 0x00 0x50af0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x83>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x28c 0x03 0x28d>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x18 0x0c 0x4000 0x18 0x0c 0x8000>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x100>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x29>;
+ };
+
+ ipc@0 {
+ compatible = "eswin,win2030-ipc";
+ #size-cells = <0x02>;
+ dma-ranges = <0x00 0x80000000 0x00 0xc0000000 0x00 0x80000000>;
+ iommus = <0x19 0x18 0x19 0x18>;
+ tbus = <0x04>;
+ eswin,syscfg = <0x17 0x1004 0x00 0x17 0x4004 0x00>;
+ mboxes = <0x33 0x00>;
+ mbox-names = "u84_scpu";
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ };
+
+ lpcpu@0 {
+ compatible = "eswin,win2030-lpcpu";
+ clocks = <0x03 0x209 0x03 0x20a>;
+ clock-names = "core_clk\0bus_clk";
+ reset-names = "core_rst\0bus_rst\0dbg_rst";
+ resets = <0x18 0x15 0x01 0x18 0x15 0x02 0x18 0x15 0x04>;
+ #size-cells = <0x02>;
+ dma-ranges = <0x00 0xb0000000 0x00 0xc0000000 0x00 0x50000000>;
+ iommus = <0x19 0x19>;
+ eswin,syscfg = <0x17 0x2004 0x00>;
+ tbus = <0x04>;
+ mboxes = <0x34 0x00>;
+ mbox-names = "u84_lpcpu";
+ numa-node-id = <0x00>;
+ status = "okay";
+ dma-noncoherent;
+ };
+
+ pvt@0x50b00000 {
+ compatible = "eswin,eswin-pvt-cpu";
+ clocks = <0x03 0x25f>;
+ clock-names = "pvt_clk";
+ resets = <0x18 0x0b 0x01>;
+ reset-names = "pvt_rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x50b00000 0x00 0x10000>;
+ interrupts = <0x15d>;
+ interrupt-parent = <0x10>;
+ #thermal-sensor-cells = <0x00>;
+ status = "okay";
+ label = "pvt0";
+ numa-node-id = <0x00>;
+ phandle = <0x71>;
+ };
+
+ pvt@0x52360000 {
+ compatible = "eswin,eswin-pvt-ddr";
+ clocks = <0x03 0x260>;
+ clock-names = "pvt_clk";
+ resets = <0x18 0x0b 0x02>;
+ reset-names = "pvt_rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x52360000 0x00 0x20000>;
+ interrupts = <0x15e>;
+ interrupt-parent = <0x10>;
+ status = "okay";
+ label = "pvt1";
+ numa-node-id = <0x00>;
+ };
+
+ fan_control@50b50000 {
+ compatible = "eswin-fan-control";
+ reg = <0x00 0x50b50000 0x00 0x10000>;
+ clocks = <0x03 0x2a7>;
+ clock-names = "pclk";
+ resets = <0x18 0x0a 0x01>;
+ reset-names = "fan_rst";
+ interrupt-parent = <0x10>;
+ interrupt-names = "fanirq";
+ interrupts = <0x162>;
+ pulses-per-revolution = <0x02>;
+ pwm-minimum-period = <0x3e8>;
+ pwms = <0x35 0x00 0x186a0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x36 0x37>;
+ status = "okay";
+ label = "fan_control";
+ numa-node-id = <0x00>;
+ eswin,pwm_inverted;
+ };
+
+ i2c@50950000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x28e>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x01>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x50950000 0x00 0x8000>;
+ interrupts = <0x69>;
+ interrupt-parent = <0x10>;
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ es8388-0@11 {
+ compatible = "eswin,es8388";
+ reg = <0x11>;
+ #sound-dai-cells = <0x00>;
+ eswin-plat = <0x02>;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x38 0x39>;
+ front-jack-gpios = <0x2e 0x00 0x00>;
+ back-jack-gpios = <0x2e 0x1c 0x00>;
+
+ port {
+
+ endpoint {
+ system-clock-frequency = <0xbb8000>;
+ remote-endpoint = <0x3a>;
+ phandle = <0x5a>;
+ };
+ };
+ };
+ };
+
+ i2c@50960000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x28f>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x02>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x50960000 0x00 0x10000>;
+ interrupts = <0x6a>;
+ interrupt-parent = <0x10>;
+ numa-node-id = <0x00>;
+ status = "disabled";
+ };
+
+ i2c@50970000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x290>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x04>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x50970000 0x00 0x8000>;
+ interrupts = <0x6b>;
+ interrupt-parent = <0x10>;
+ numa-node-id = <0x00>;
+ status = "disabled";
+ };
+
+ i2c@50980000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x291>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x08>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x50980000 0x00 0x8000>;
+ interrupts = <0x6c>;
+ interrupt-parent = <0x10>;
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ fusb303b@21 {
+ compatible = "fcs,fusb303b";
+ status = "okay";
+ reg = <0x21>;
+ eswin,syscfg = <0x17 0x3c0 0x0c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x3b>;
+ int-gpios = <0x2e 0x05 0x00>;
+
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "host";
+ };
+ };
+ };
+
+ i2c@50990000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x292>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x10>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x50990000 0x00 0x8000>;
+ interrupts = <0x6d>;
+ interrupt-parent = <0x10>;
+ numa-node-id = <0x00>;
+ status = "disabled";
+ };
+
+ i2c@509a0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x293>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x20>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x509a0000 0x00 0x8000>;
+ interrupts = <0x6e>;
+ interrupt-parent = <0x10>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ };
+
+ i2c@509b0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x294>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x40>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x509b0000 0x00 0x8000>;
+ interrupts = <0x6f>;
+ interrupt-parent = <0x10>;
+ numa-node-id = <0x00>;
+ status = "disabled";
+ };
+
+ i2c@509c0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x295>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x80>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x509c0000 0x00 0x8000>;
+ interrupts = <0x70>;
+ interrupt-parent = <0x10>;
+ numa-node-id = <0x00>;
+ status = "disabled";
+ };
+
+ i2c@509d0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x296>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x100>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x509d0000 0x00 0x8000>;
+ interrupts = <0x71>;
+ interrupt-parent = <0x10>;
+ numa-node-id = <0x00>;
+ status = "disabled";
+ };
+
+ i2c@509e0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x297>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x200>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x509e0000 0x00 0x8000>;
+ interrupts = <0x72>;
+ interrupt-parent = <0x10>;
+ numa-node-id = <0x00>;
+ status = "disabled";
+ };
+
+ i2c@51830000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x29f>;
+ clock-names = "pclk";
+ resets = <0x18 0x26 0x01>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x51830000 0x00 0x8000>;
+ interrupts = <0x122>;
+ interrupt-parent = <0x10>;
+ eswin,i2c_dma = <0x3c>;
+ dma-names = "rx\0tx";
+ dmas = <0x3c 0x29 0xff 0x3c 0x2a 0xff>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ eswin,syscfg = <0x17 0x3c0 0x10>;
+
+ aon_eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+ };
+
+ i2c@51838000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x2a0>;
+ clock-names = "pclk";
+ resets = <0x18 0x25 0x01>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x51838000 0x00 0x8000>;
+ interrupts = <0x123>;
+ interrupt-parent = <0x10>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ eswin,syscfg = <0x17 0x3c0 0x0f>;
+ i2c-sda-hold-time-ns = <0x40>;
+
+ pmic@10 {
+ compatible = "microchip,pac1934";
+ update_time_ms = <0x3e8>;
+ eswin,chan_label = "som vdd\0soc vdd\0cpu vdd\0ddr lpvdd";
+ label = "som_info";
+ energy_acc_count = <0x00>;
+ shunt_resistors = <0x01 0x01 0x01 0x01>;
+ reg = <0x10>;
+ };
+
+ ina226@44 {
+ compatible = "ti,ina226";
+ #io-channel-cells = <0x01>;
+ label = "sys_power";
+ reg = <0x44>;
+ shunt-resistor = <0x3e8>;
+ };
+
+ mpq8785@12 {
+ compatible = "mps,mpq8785";
+ reg = <0x12>;
+ eswin,regulator_default-microvolt = <0xf4240>;
+ eswin,regulator_label = "supply vdd1\0npu vdd1\0npu current1\0npu temperature1";
+ label = "npu_vdd";
+
+ regulators {
+
+ npu_svcc {
+ regulator-name = "NPU_SVCC";
+ regulator-min-microvolt = <0xaae60>;
+ regulator-max-microvolt = <0x10c8e0>;
+ regulator-min-microamp = <0x1312d00>;
+ regulator-max-microamp = <0x2625a00>;
+ regulator-ov-protection-microvolt = <0x10c8e0>;
+ phandle = <0x23>;
+ };
+ };
+ };
+ };
+
+ pinctrl@0x51600080 {
+ compatible = "eswin,eic7x-pinctrl\0syscon";
+ reg = <0x00 0x51600080 0x00 0x1fff80>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58>;
+ phandle = <0x1e>;
+
+ pwm0-default {
+ phandle = <0x37>;
+
+ mux {
+ groups = "pwm0_group";
+ function = "pwm0_func";
+ };
+ };
+
+ fan_tach-default {
+ phandle = <0x36>;
+
+ mux {
+ groups = "fan_tach_group";
+ function = "fan_tach_func";
+ };
+ };
+
+ sdio0-default {
+
+ mux {
+ groups = "sdio0_group";
+ function = "sdio0_func";
+ };
+ };
+
+ sdio1-default {
+
+ mux {
+ groups = "sdio1_group";
+ function = "sdio1_func";
+ };
+ };
+
+ jtag0-default {
+
+ mux {
+ groups = "jtag0_group";
+ function = "jtag0_func";
+ };
+ };
+
+ jtag1-default {
+
+ mux {
+ groups = "jtag1_group";
+ function = "jtag1_func";
+ };
+ };
+
+ jtag2-default {
+
+ mux {
+ groups = "jtag2_group";
+ function = "jtag2_func";
+ };
+ };
+
+ pcie-default {
+
+ mux {
+ groups = "pcie_group";
+ function = "pcie_func";
+ };
+ };
+
+ hdmi-default {
+
+ mux {
+ groups = "hdmi_group";
+ function = "hdmi_func";
+ };
+ };
+
+ rgmii0-default {
+
+ mux {
+ groups = "rgmii0_group";
+ function = "rgmii0_func";
+ };
+ };
+
+ rgmii1-default {
+
+ mux {
+ groups = "rgmii1_group";
+ function = "rgmii1_func";
+ };
+ };
+
+ spi0-default {
+
+ mux {
+ groups = "spi0_group";
+ function = "spi0_func";
+ };
+ };
+
+ spi1-default {
+
+ mux {
+ groups = "spi1_group";
+ function = "spi1_func";
+ };
+ };
+
+ spi3-default {
+
+ mux {
+ groups = "spi3_group";
+ function = "spi3_func";
+ };
+ };
+
+ por_time_sel0-default {
+
+ mux {
+ groups = "por_time_sel0_group";
+ function = "por_time_sel0_func";
+ };
+ };
+
+ por_time_sel1-default {
+
+ mux {
+ groups = "por_time_sel1_group";
+ function = "por_time_sel1_func";
+ };
+ };
+
+ i2s0-default {
+
+ mux {
+ groups = "i2s0_group";
+ function = "i2s0_func";
+ };
+ };
+
+ i2s1-default {
+
+ mux {
+ groups = "i2s1_group";
+ function = "i2s1_func";
+ };
+ };
+
+ i2s2-default {
+
+ mux {
+ groups = "i2s2_group";
+ function = "i2s2_func";
+ };
+ };
+
+ usb0_pwren-default {
+
+ mux {
+ groups = "usb0_pwren_group";
+ function = "usb0_pwren_func";
+ };
+ };
+
+ usb1_pwren-default {
+
+ mux {
+ groups = "usb1_pwren_group";
+ function = "usb1_pwren_func";
+ };
+ };
+
+ i2c0-default {
+
+ mux {
+ groups = "i2c0_group";
+ function = "i2c0_func";
+ };
+ };
+
+ i2c1-default {
+
+ mux {
+ groups = "i2c1_group";
+ function = "i2c1_func";
+ };
+ };
+
+ i2c2-default {
+
+ mux {
+ groups = "i2c2_group";
+ function = "i2c2_func";
+ };
+ };
+
+ i2c3-default {
+
+ mux {
+ groups = "i2c3_group";
+ function = "i2c3_func";
+ };
+ };
+
+ i2c4-default {
+
+ mux {
+ groups = "i2c4_group";
+ function = "i2c4_func";
+ };
+ };
+
+ i2c5-default {
+
+ mux {
+ groups = "i2c5_group";
+ function = "i2c5_func";
+ };
+ };
+
+ i2c8-default {
+
+ mux {
+ groups = "i2c8_group";
+ function = "i2c8_func";
+ };
+ };
+
+ i2c10-default {
+
+ mux {
+ groups = "i2c10_group";
+ function = "i2c10_func";
+ };
+ };
+
+ i2c11-default {
+
+ mux {
+ groups = "i2c11_group";
+ function = "i2c11_func";
+ };
+ };
+
+ uart0-default {
+
+ mux {
+ groups = "uart0_group";
+ function = "uart0_func";
+ };
+ };
+
+ uart1-default {
+
+ mux {
+ groups = "uart1_group";
+ function = "uart1_func";
+ };
+ };
+
+ uart2-default {
+
+ mux {
+ groups = "uart2_group";
+ function = "uart2_func";
+ };
+ };
+
+ mipi_csi0-default {
+
+ mux {
+ groups = "mipi_csi0_group";
+ function = "mipi_csi0_func";
+ };
+ };
+
+ mipi_csi1-default {
+
+ mux {
+ groups = "mipi_csi1_group";
+ function = "mipi_csi1_func";
+ };
+ };
+
+ mipi_csi2-default {
+
+ mux {
+ groups = "mipi_csi2_group";
+ function = "mipi_csi2_func";
+ };
+ };
+
+ mipi_csi3-default {
+
+ mux {
+ groups = "mipi_csi3_group";
+ function = "mipi_csi3_func";
+ };
+ };
+
+ mipi_csi4-default {
+
+ mux {
+ groups = "mipi_csi4_group";
+ function = "mipi_csi4_func";
+ };
+ };
+
+ mipi_csi5-default {
+
+ mux {
+ groups = "mipi_csi5_group";
+ function = "mipi_csi5_func";
+ };
+ };
+
+ s_mode-default {
+
+ mux {
+ groups = "s_mode_group";
+ function = "s_mode_func";
+ };
+ };
+
+ ddr_refclk_sel-default {
+
+ mux {
+ groups = "ddr_refclk_sel_group";
+ function = "ddr_refclk_sel_func";
+ };
+ };
+
+ boot_sel-default {
+
+ mux {
+ groups = "boot_sel_group";
+ function = "boot_sel_func";
+ };
+ };
+
+ lpddr_ref_clk-default {
+
+ mux {
+ groups = "lpddr_ref_clk_group";
+ function = "lpddr_ref_clk_func";
+ };
+ };
+
+ spi2-default {
+
+ mux1 {
+ groups = "spi2_clk_group";
+ function = "spi2_clk_func";
+ };
+
+ conf1 {
+ groups = "spi2_clk_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ bias-pull-down = <0x00>;
+ };
+
+ mux2 {
+ groups = "spi2_d0_group";
+ function = "spi2_d0_func";
+ };
+
+ conf2 {
+ groups = "spi2_d0_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ bias-pull-down = <0x00>;
+ };
+
+ mux3 {
+ groups = "spi2_d1_d2_d3_group";
+ function = "spi2_d1_d2_d3_func";
+ };
+
+ conf3 {
+ groups = "spi2_d1_d2_d3_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ bias-pull-down = <0x00>;
+ };
+
+ mux4 {
+ groups = "spi2_cs_group";
+ function = "spi2_cs_func";
+ };
+ };
+
+ sata_act_led-default {
+ phandle = <0x2c>;
+
+ mux {
+ groups = "sata_act_led_group";
+ function = "sata_act_led_func";
+ };
+
+ conf {
+ groups = "sata_act_led_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ emmc_led_control-default {
+ phandle = <0x2d>;
+
+ mux {
+ groups = "emmc_led_control_group";
+ function = "emmc_led_control_func";
+ };
+
+ conf {
+ groups = "emmc_led_control_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ sd0_led_control-default {
+
+ mux {
+ groups = "sd0_led_control_group";
+ function = "sd0_led_control_func";
+ };
+ };
+
+ sd1_led_control-default {
+
+ mux {
+ groups = "sd1_led_control_group";
+ function = "sd1_led_control_func";
+ };
+ };
+
+ i2c6-default {
+
+ mux {
+ groups = "i2c6_group";
+ function = "i2c6_func";
+ };
+ };
+
+ i2c7-default {
+
+ mux {
+ groups = "i2c7_group";
+ function = "i2c7_func";
+ };
+ };
+
+ i2c9-default {
+
+ mux {
+ groups = "i2c9_group";
+ function = "i2c9_func";
+ };
+ };
+
+ pwm1-default {
+
+ mux {
+ groups = "pwm1_group";
+ function = "pwm1_func";
+ };
+ };
+
+ pwm2-default {
+
+ mux {
+ groups = "pwm2_group";
+ function = "pwm2_func";
+ };
+ };
+
+ mipi_csi_xtrig-default {
+
+ mux {
+ groups = "mipi_csi_xtrig_group";
+ function = "mipi_csi_xtrig_func";
+ };
+ };
+
+ uart3-default {
+
+ mux {
+ groups = "uart3_group";
+ function = "uart3_func";
+ };
+ };
+
+ uart4-default {
+
+ mux {
+ groups = "uart4_group";
+ function = "uart4_func";
+ };
+ };
+
+ gpio0-default {
+ phandle = <0x38>;
+
+ mux {
+ groups = "gpio0_group";
+ function = "gpio0_func";
+ };
+
+ conf {
+ groups = "gpio0_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ };
+ };
+
+ gpio1-default {
+
+ mux {
+ groups = "gpio1_group";
+ function = "gpio1_func";
+ };
+ };
+
+ gpio2-default {
+
+ mux {
+ groups = "gpio2_group";
+ function = "gpio2_func";
+ };
+ };
+
+ gpio3-default {
+
+ mux {
+ groups = "gpio3_group";
+ function = "gpio3_func";
+ };
+ };
+
+ gpio4-default {
+
+ mux {
+ groups = "gpio4_group";
+ function = "gpio4_func";
+ };
+ };
+
+ gpio5-default {
+ phandle = <0x3b>;
+
+ mux {
+ groups = "gpio5_group";
+ function = "gpio5_func";
+ };
+
+ conf {
+ groups = "gpio5_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ };
+ };
+
+ gpio6-default {
+ phandle = <0x3d>;
+
+ mux {
+ groups = "gpio6_group";
+ function = "gpio6_func";
+ };
+
+ conf {
+ groups = "gpio6_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio7-default {
+ phandle = <0x3e>;
+
+ mux {
+ groups = "gpio7_group";
+ function = "gpio7_func";
+ };
+
+ conf {
+ groups = "gpio7_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio8-default {
+ phandle = <0x3f>;
+
+ mux {
+ groups = "gpio8_group";
+ function = "gpio8_func";
+ };
+
+ conf {
+ groups = "gpio8_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ };
+ };
+
+ gpio9-default {
+ phandle = <0x40>;
+
+ mux {
+ groups = "gpio9_group";
+ function = "gpio9_func";
+ };
+
+ conf {
+ groups = "gpio9_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ };
+ };
+
+ gpio10-default {
+ phandle = <0x41>;
+
+ mux {
+ groups = "gpio10_group";
+ function = "gpio10_func";
+ };
+
+ conf {
+ groups = "gpio10_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ };
+ };
+
+ gpio11-default {
+
+ mux {
+ groups = "gpio11_group";
+ function = "gpio11_func";
+ };
+
+ conf {
+ groups = "gpio11_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ };
+ };
+
+ gpio12-default {
+
+ mux {
+ groups = "gpio12_group";
+ function = "gpio12_func";
+ };
+ };
+
+ gpio13-default {
+
+ mux {
+ groups = "gpio13_group";
+ function = "gpio13_func";
+ };
+ };
+
+ gpio14-default {
+
+ mux {
+ groups = "gpio14_group";
+ function = "gpio14_func";
+ };
+ };
+
+ gpio15-default {
+ phandle = <0x2f>;
+
+ mux {
+ groups = "gpio15_group";
+ function = "gpio15_func";
+ };
+ };
+
+ gpio16-default {
+
+ mux {
+ groups = "gpio16_group";
+ function = "gpio16_func";
+ };
+
+ conf {
+ groups = "gpio16_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio17-default {
+ phandle = <0x42>;
+
+ mux {
+ groups = "gpio17_group";
+ function = "gpio17_func";
+ };
+
+ conf {
+ groups = "gpio17_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio18-default {
+
+ mux {
+ groups = "gpio18_group";
+ function = "gpio18_func";
+ };
+
+ conf {
+ groups = "gpio18_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio19-default {
+
+ mux {
+ groups = "gpio19_group";
+ function = "gpio19_func";
+ };
+
+ conf {
+ groups = "gpio19_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio20-default {
+
+ mux {
+ groups = "gpio20_group";
+ function = "gpio20_func";
+ };
+
+ conf {
+ groups = "gpio20_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio21-default {
+
+ mux {
+ groups = "gpio21_group";
+ function = "gpio21_func";
+ };
+
+ conf {
+ groups = "gpio21_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio22-default {
+
+ mux {
+ groups = "gpio22_group";
+ function = "gpio22_func";
+ };
+ };
+
+ gpio23-default {
+
+ mux {
+ groups = "gpio23_group";
+ function = "gpio23_func";
+ };
+ };
+
+ gpio24-default {
+
+ mux {
+ groups = "gpio24_group";
+ function = "gpio24_func";
+ };
+ };
+
+ gpio25-default {
+
+ mux {
+ groups = "gpio25_group";
+ function = "gpio25_func";
+ };
+ };
+
+ gpio26-default {
+
+ mux {
+ groups = "gpio26_group";
+ function = "gpio26_func";
+ };
+ };
+
+ gpio27-default {
+
+ mux {
+ groups = "gpio27_group";
+ function = "gpio27_func";
+ };
+ };
+
+ gpio28-default {
+ phandle = <0x39>;
+
+ mux {
+ groups = "gpio28_group";
+ function = "gpio28_func";
+ };
+
+ conf {
+ groups = "gpio28_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ };
+ };
+
+ gpio29-default {
+
+ mux {
+ groups = "gpio29_group";
+ function = "gpio29_func";
+ };
+ };
+
+ gpio30-default {
+
+ mux {
+ groups = "gpio30_group";
+ function = "gpio30_func";
+ };
+ };
+
+ gpio31-default {
+
+ mux {
+ groups = "gpio31_group";
+ function = "gpio31_func";
+ };
+ };
+
+ gpio32-default {
+
+ mux {
+ groups = "gpio32_group";
+ function = "gpio32_func";
+ };
+ };
+
+ gpio33-default {
+
+ mux {
+ groups = "gpio33_group";
+ function = "gpio33_func";
+ };
+ };
+
+ gpio34-default {
+
+ mux {
+ groups = "gpio34_group";
+ function = "gpio34_func";
+ };
+ };
+
+ gpio35-default {
+ phandle = <0x43>;
+
+ mux {
+ groups = "gpio35_group";
+ function = "gpio35_func";
+ };
+
+ conf {
+ groups = "gpio35_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio36-default {
+ phandle = <0x44>;
+
+ mux {
+ groups = "gpio36_group";
+ function = "gpio36_func";
+ };
+
+ conf {
+ groups = "gpio36_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio37-default {
+ phandle = <0x45>;
+
+ mux {
+ groups = "gpio37_group";
+ function = "gpio37_func";
+ };
+
+ conf {
+ groups = "gpio37_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio38-default {
+ phandle = <0x46>;
+
+ mux {
+ groups = "gpio38_group";
+ function = "gpio38_func";
+ };
+
+ conf {
+ groups = "gpio38_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio39-default {
+ phandle = <0x47>;
+
+ mux {
+ groups = "gpio39_group";
+ function = "gpio39_func";
+ };
+
+ conf {
+ groups = "gpio39_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio40-default {
+ phandle = <0x48>;
+
+ mux {
+ groups = "gpio40_group";
+ function = "gpio40_func";
+ };
+
+ conf {
+ groups = "gpio40_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio41-default {
+ phandle = <0x49>;
+
+ mux {
+ groups = "gpio41_group";
+ function = "gpio41_func";
+ };
+ };
+
+ gpio42-default {
+
+ mux {
+ groups = "gpio42_group";
+ function = "gpio42_func";
+ };
+
+ conf {
+ groups = "gpio42_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio43-default {
+ phandle = <0x69>;
+
+ mux {
+ groups = "gpio43_group";
+ function = "gpio43_func";
+ };
+ };
+
+ gpio44-default {
+
+ mux {
+ groups = "gpio44_group";
+ function = "gpio44_func";
+ };
+ };
+
+ gpio45-default {
+
+ mux {
+ groups = "gpio45_group";
+ function = "gpio45_func";
+ };
+ };
+
+ gpio46-default {
+ phandle = <0x4a>;
+
+ mux {
+ groups = "gpio46_group";
+ function = "gpio46_func";
+ };
+
+ conf {
+ groups = "gpio46_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio47-default {
+
+ mux {
+ groups = "gpio47_group";
+ function = "gpio47_func";
+ };
+
+ conf {
+ groups = "gpio47_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio48-default {
+
+ mux {
+ groups = "gpio48_group";
+ function = "gpio48_func";
+ };
+ };
+
+ gpio49-default {
+
+ mux {
+ groups = "gpio49_group";
+ function = "gpio49_func";
+ };
+ };
+
+ gpio50-default {
+
+ mux {
+ groups = "gpio50_group";
+ function = "gpio50_func";
+ };
+ };
+
+ gpio51-default {
+
+ mux {
+ groups = "gpio51_group";
+ function = "gpio51_func";
+ };
+ };
+
+ gpio52-default {
+ phandle = <0x4b>;
+
+ mux {
+ groups = "gpio52_group";
+ function = "gpio52_func";
+ };
+
+ conf {
+ groups = "gpio52_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio53-default {
+ phandle = <0x4c>;
+
+ mux {
+ groups = "gpio53_group";
+ function = "gpio53_func";
+ };
+
+ conf {
+ groups = "gpio53_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio54-default {
+
+ mux {
+ groups = "gpio54_group";
+ function = "gpio54_func";
+ };
+ };
+
+ gpio55-default {
+
+ mux {
+ groups = "gpio55_group";
+ function = "gpio55_func";
+ };
+ };
+
+ gpio56-default {
+
+ mux {
+ groups = "gpio56_group";
+ function = "gpio56_func";
+ };
+ };
+
+ gpio57-default {
+
+ mux {
+ groups = "gpio57_group";
+ function = "gpio57_func";
+ };
+ };
+
+ gpio58-default {
+
+ mux {
+ groups = "gpio58_group";
+ function = "gpio58_func";
+ };
+ };
+
+ gpio59-default {
+
+ mux {
+ groups = "gpio59_group";
+ function = "gpio59_func";
+ };
+ };
+
+ gpio60-default {
+
+ mux {
+ groups = "gpio60_group";
+ function = "gpio60_func";
+ };
+ };
+
+ gpio61-default {
+
+ mux {
+ groups = "gpio61_group";
+ function = "gpio61_func";
+ };
+ };
+
+ gpio62-default {
+
+ mux {
+ groups = "gpio62_group";
+ function = "gpio62_func";
+ };
+ };
+
+ gpio63-default {
+
+ mux {
+ groups = "gpio63_group";
+ function = "gpio63_func";
+ };
+ };
+
+ gpio64-default {
+ phandle = <0x4d>;
+
+ mux {
+ groups = "gpio64_group";
+ function = "gpio64_func";
+ };
+
+ conf {
+ groups = "gpio64_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio65-default {
+ phandle = <0x4e>;
+
+ mux {
+ groups = "gpio65_group";
+ function = "gpio65_func";
+ };
+
+ conf {
+ groups = "gpio65_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio66-default {
+ phandle = <0x4f>;
+
+ mux {
+ groups = "gpio66_group";
+ function = "gpio66_func";
+ };
+
+ conf {
+ groups = "gpio66_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio67-default {
+ phandle = <0x50>;
+
+ mux {
+ groups = "gpio67_group";
+ function = "gpio67_func";
+ };
+
+ conf {
+ groups = "gpio67_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio68-default {
+
+ mux {
+ groups = "gpio68_group";
+ function = "gpio68_func";
+ };
+ };
+
+ gpio69-default {
+
+ mux {
+ groups = "gpio69_group";
+ function = "gpio69_func";
+ };
+ };
+
+ gpio70-default {
+ phandle = <0x51>;
+
+ mux {
+ groups = "gpio70_group";
+ function = "gpio70_func";
+ };
+ };
+
+ gpio71-default {
+
+ mux {
+ groups = "gpio71_group";
+ function = "gpio71_func";
+ };
+ };
+
+ gpio72-default {
+
+ mux {
+ groups = "gpio72_group";
+ function = "gpio72_func";
+ };
+ };
+
+ gpio73-default {
+ phandle = <0x52>;
+
+ mux {
+ groups = "gpio73_group";
+ function = "gpio73_func";
+ };
+ };
+
+ gpio74-default {
+
+ mux {
+ groups = "gpio74_group";
+ function = "gpio74_func";
+ };
+ };
+
+ gpio75-default {
+
+ mux {
+ groups = "gpio75_group";
+ function = "gpio75_func";
+ };
+ };
+
+ gpio76-default {
+
+ mux {
+ groups = "gpio76_group";
+ function = "gpio76_func";
+ };
+ };
+
+ gpio77-default {
+
+ mux {
+ groups = "gpio77_group";
+ function = "gpio77_func";
+ };
+ };
+
+ gpio78-default {
+
+ mux {
+ groups = "gpio78_group";
+ function = "gpio78_func";
+ };
+ };
+
+ gpio79-default {
+ phandle = <0x30>;
+
+ mux {
+ groups = "gpio79_group";
+ function = "gpio79_func";
+ };
+ };
+
+ gpio80-default {
+
+ mux {
+ groups = "gpio80_group";
+ function = "gpio80_func";
+ };
+ };
+
+ gpio81-default {
+
+ mux {
+ groups = "gpio81_group";
+ function = "gpio81_func";
+ };
+ };
+
+ gpio82-default {
+ phandle = <0x64>;
+
+ mux {
+ groups = "gpio82_group";
+ function = "gpio82_func";
+ };
+ };
+
+ gpio83-default {
+ phandle = <0x53>;
+
+ mux {
+ groups = "gpio83_group";
+ function = "gpio83_func";
+ };
+ };
+
+ gpio84-default {
+
+ mux {
+ groups = "gpio84_group";
+ function = "gpio84_func";
+ };
+ };
+
+ gpio85-default {
+ phandle = <0x65>;
+
+ mux {
+ groups = "gpio85_group";
+ function = "gpio85_func";
+ };
+ };
+
+ gpio86-default {
+ phandle = <0x54>;
+
+ mux {
+ groups = "gpio86_group";
+ function = "gpio86_func";
+ };
+ };
+
+ gpio87-default {
+ phandle = <0x55>;
+
+ mux {
+ groups = "gpio87_group";
+ function = "gpio87_func";
+ };
+ };
+
+ gpio88-default {
+
+ mux {
+ groups = "gpio88_group";
+ function = "gpio88_func";
+ };
+ };
+
+ gpio89-default {
+
+ mux {
+ groups = "gpio89_group";
+ function = "gpio89_func";
+ };
+ };
+
+ gpio90-default {
+
+ mux {
+ groups = "gpio90_group";
+ function = "gpio90_func";
+ };
+ };
+
+ gpio91-default {
+
+ mux {
+ groups = "gpio91_group";
+ function = "gpio91_func";
+ };
+ };
+
+ gpio92-default {
+ phandle = <0x56>;
+
+ mux {
+ groups = "gpio92_group";
+ function = "gpio92_func";
+ };
+
+ conf {
+ groups = "gpio92_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio93-default {
+ phandle = <0x57>;
+
+ mux {
+ groups = "gpio93_group";
+ function = "gpio93_func";
+ };
+
+ conf {
+ groups = "gpio93_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio94-default {
+ phandle = <0x58>;
+
+ mux {
+ groups = "gpio94_group";
+ function = "gpio94_func";
+ };
+
+ conf {
+ groups = "gpio94_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio95-default {
+
+ mux {
+ groups = "gpio95_group";
+ function = "gpio95_func";
+ };
+ };
+
+ gpio96-default {
+
+ mux {
+ groups = "gpio96_group";
+ function = "gpio96_func";
+ };
+ };
+
+ gpio97-default {
+
+ mux {
+ groups = "gpio97_group";
+ function = "gpio97_func";
+ };
+ };
+
+ gpio98-default {
+
+ mux {
+ groups = "gpio98_group";
+ function = "gpio98_func";
+ };
+ };
+
+ gpio99-default {
+
+ mux {
+ groups = "gpio99_group";
+ function = "gpio99_func";
+ };
+ };
+
+ gpio100-default {
+
+ mux {
+ groups = "gpio100_group";
+ function = "gpio100_func";
+ };
+ };
+
+ gpio101-default {
+
+ mux {
+ groups = "gpio101_group";
+ function = "gpio101_func";
+ };
+ };
+
+ gpio102-default {
+
+ mux {
+ groups = "gpio102_group";
+ function = "gpio102_func";
+ };
+ };
+
+ gpio103-default {
+
+ mux {
+ groups = "gpio103_group";
+ function = "gpio103_func";
+ };
+ };
+
+ gpio104-default {
+
+ mux {
+ groups = "gpio104_group";
+ function = "gpio104_func";
+ };
+ };
+
+ gpio105-default {
+
+ mux {
+ groups = "gpio105_group";
+ function = "gpio105_func";
+ };
+ };
+
+ gpio106-default {
+ phandle = <0x1c>;
+
+ mux {
+ groups = "gpio106_group";
+ function = "gpio106_func";
+ };
+
+ conf {
+ groups = "gpio106_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio107-default {
+
+ mux {
+ groups = "gpio107_group";
+ function = "gpio107_func";
+ };
+
+ conf {
+ groups = "gpio107_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio108-default {
+
+ mux {
+ groups = "gpio108_group";
+ function = "gpio108_func";
+ };
+
+ conf {
+ groups = "gpio108_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio109-default {
+
+ mux {
+ groups = "gpio109_group";
+ function = "gpio109_func";
+ };
+
+ conf {
+ groups = "gpio109_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio110-default {
+
+ mux {
+ groups = "gpio110_group";
+ function = "gpio110_func";
+ };
+
+ conf {
+ groups = "gpio110_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio111-default {
+ phandle = <0x20>;
+
+ mux {
+ groups = "gpio111_group";
+ function = "gpio111_func";
+ };
+
+ conf {
+ groups = "gpio111_group";
+ input-enable = <0x00>;
+ bias-pull-up = <0x01>;
+ };
+ };
+
+ csi_mon_out-default {
+
+ mux {
+ groups = "csi_mon_out_group";
+ function = "csi_mon_out_func";
+ };
+ };
+
+ csi_ocla_clk-default {
+
+ mux {
+ groups = "csi_ocla_clk_group";
+ function = "csi_ocla_clk_func";
+ };
+ };
+
+ csi_mon_out_valid-default {
+
+ mux {
+ groups = "csi_mon_out_valid_group";
+ function = "csi_mon_out_valid_func";
+ };
+ };
+
+ csi_parity_error-default {
+
+ mux {
+ groups = "csi_parity_error_group";
+ function = "csi_parity_error_func";
+ };
+ };
+
+ csi_dtb_out-default {
+
+ mux {
+ groups = "csi_dtb_out_group";
+ function = "csi_dtb_out_func";
+ };
+ };
+
+ csi_phy_sel-default {
+
+ mux {
+ groups = "csi_phy_sel_group";
+ function = "csi_phy_sel_func";
+ };
+ };
+
+ vc_g2d0_debug_out-default {
+
+ mux {
+ groups = "vc_g2d0_debug_out_group";
+ function = "vc_g2d0_debug_out_func";
+ };
+ };
+
+ vc_g2d1_debug_out-default {
+
+ mux {
+ groups = "vc_g2d1_debug_out_group";
+ function = "vc_g2d1_debug_out_func";
+ };
+ };
+
+ sata_mpll_clk-default {
+
+ mux {
+ groups = "sata_mpll_clk_group";
+ function = "sata_mpll_clk_func";
+ };
+ };
+
+ sata_ref_repeat_clk_m-default {
+
+ mux {
+ groups = "sata_ref_repeat_clk_m_group";
+ function = "sata_ref_repeat_clk_m_func";
+ };
+ };
+
+ sata_ref_repeat_clk_p-default {
+
+ mux {
+ groups = "sata_ref_repeat_clk_p_group";
+ function = "sata_ref_repeat_clk_p_func";
+ };
+ };
+ };
+
+ gpio@51600000 {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x00 0x51600000 0x00 0x80>;
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ ngpios = <0x20>;
+ reg = <0x00>;
+ interrupt-parent = <0x10>;
+ interrupt-controller;
+ #interrupt-cells = <0x02>;
+ interrupts = <0x12f 0x130 0x131 0x132 0x133 0x134 0x135 0x136 0x137 0x138 0x139 0x13a 0x13b 0x13c 0x13d 0x13e 0x13f 0x140 0x141 0x142 0x143 0x144 0x145 0x146 0x147 0x148 0x149 0x14a 0x14b 0x14c 0x14d 0x14e>;
+ phandle = <0x2e>;
+ };
+
+ gpio-port@1 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ ngpios = <0x20>;
+ reg = <0x01>;
+ phandle = <0x6a>;
+ };
+
+ gpio-port@2 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ ngpios = <0x20>;
+ reg = <0x02>;
+ phandle = <0x16>;
+ };
+
+ gpio-port@3 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ ngpios = <0x10>;
+ reg = <0x03>;
+ phandle = <0x1d>;
+ };
+ };
+
+ pwm@0x50818000 {
+ compatible = "eswin,pwm-eswin";
+ #pwm-cells = <0x02>;
+ reg = <0x00 0x50818000 0x00 0x4000>;
+ clock-names = "pclk";
+ clocks = <0x03 0x2a6>;
+ clock-frequency = <0xbebc200>;
+ resets = <0x18 0x0f 0x01>;
+ reset-names = "rst";
+ status = "okay";
+ numa-node-id = <0x00>;
+ phandle = <0x35>;
+ };
+
+ watchdog@0x50800000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x00 0x50800000 0x00 0x4000>;
+ clocks = <0x03 0x298>;
+ clock-names = "pclk";
+ resets = <0x18 0x11 0x01>;
+ reset-names = "rst";
+ interrupts = <0x57>;
+ interrupt-parent = <0x10>;
+ status = "disabled";
+ numa-node-id = <0x00>;
+ };
+
+ watchdog@0x50804000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x00 0x50804000 0x00 0x4000>;
+ clocks = <0x03 0x299>;
+ clock-names = "pclk";
+ resets = <0x18 0x11 0x02>;
+ reset-names = "rst";
+ interrupts = <0x58>;
+ interrupt-parent = <0x10>;
+ status = "disabled";
+ numa-node-id = <0x00>;
+ };
+
+ watchdog@0x50808000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x00 0x50808000 0x00 0x4000>;
+ clocks = <0x03 0x29a>;
+ clock-names = "pclk";
+ resets = <0x18 0x11 0x04>;
+ reset-names = "rst";
+ interrupts = <0x59>;
+ interrupt-parent = <0x10>;
+ status = "disabled";
+ numa-node-id = <0x00>;
+ };
+
+ watchdog@0x5080c000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x00 0x5080c000 0x00 0x4000>;
+ clocks = <0x03 0x29b>;
+ clock-names = "pclk";
+ resets = <0x18 0x11 0x08>;
+ reset-names = "rst";
+ interrupts = <0x5a>;
+ interrupt-parent = <0x10>;
+ status = "disabled";
+ numa-node-id = <0x00>;
+ };
+
+ timer@0x51840000 {
+ compatible = "eswin,eswin-timer";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x51840000 0x00 0x8000>;
+ perf_count = <0x07>;
+ numa-node-id = <0x00>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x159>;
+ clock-names = "pclk\0timer_aclk";
+ clocks = <0x03 0x26c 0x03 0x268>;
+ resets = <0x18 0x30 0x01 0x18 0x30 0x02 0x18 0x30 0x04 0x18 0x30 0x08 0x18 0x30 0x10 0x18 0x30 0x20 0x18 0x30 0x40 0x18 0x30 0x80 0x18 0x30 0x100>;
+ reset-names = "trst0\0trst1\0trst2\0trst3\0trst4\0trst5\0trst6\0trst7\0prst";
+ status = "okay";
+ };
+
+ timer@0x51848000 {
+ compatible = "eswin,eswin-timer";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x51848000 0x00 0x8000>;
+ numa-node-id = <0x00>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x15a>;
+ clock-names = "pclk\0timer_aclk";
+ clocks = <0x03 0x26d 0x03 0x269>;
+ resets = <0x18 0x31 0x01 0x18 0x31 0x02 0x18 0x31 0x04 0x18 0x31 0x08 0x18 0x31 0x10 0x18 0x31 0x20 0x18 0x31 0x40 0x18 0x31 0x80 0x18 0x31 0x100>;
+ reset-names = "trst0\0trst1\0trst2\0trst3\0trst4\0trst5\0trst6\0trst7\0prst";
+ status = "okay";
+ };
+
+ timer@0x51850000 {
+ compatible = "eswin,eswin-timer";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x51850000 0x00 0x8000>;
+ numa-node-id = <0x00>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x15b>;
+ clock-names = "pclk\0timer_aclk";
+ clocks = <0x03 0x26e 0x03 0x26a>;
+ resets = <0x18 0x32 0x01 0x18 0x32 0x02 0x18 0x32 0x04 0x18 0x32 0x08 0x18 0x32 0x10 0x18 0x32 0x20 0x18 0x32 0x40 0x18 0x32 0x80 0x18 0x32 0x100>;
+ reset-names = "trst0\0trst1\0trst2\0trst3\0trst4\0trst5\0trst6\0trst7\0prst";
+ status = "okay";
+ };
+
+ timer@0x51858000 {
+ compatible = "eswin,eswin-timer";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x51858000 0x00 0x8000>;
+ numa-node-id = <0x00>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x15c>;
+ clock-names = "pclk\0timer_aclk\0timer3_clk8";
+ clocks = <0x03 0x26f 0x03 0x26b 0x03 0x270>;
+ resets = <0x18 0x33 0x01 0x18 0x33 0x02 0x18 0x33 0x04 0x18 0x33 0x08 0x18 0x33 0x10 0x18 0x33 0x20 0x18 0x33 0x40 0x18 0x33 0x80 0x18 0x33 0x100>;
+ reset-names = "trst0\0trst1\0trst2\0trst3\0trst4\0trst5\0trst6\0trst7\0prst";
+ status = "okay";
+ };
+
+ rtc@51818000 {
+ compatible = "eswin,win2030-rtc";
+ reg = <0x00 0x51818000 0x00 0x400>;
+ eswin,syscfg = <0x17 0x3c0>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x124>;
+ clocks = <0x03 0x272>;
+ clock-names = "rtcclk";
+ clock-frequency = <0x3d09>;
+ resets = <0x18 0x34 0x01>;
+ reset-names = "rtcrst";
+ status = "okay";
+ numa-node-id = <0x00>;
+ };
+
+ i2s0@50200000 {
+ compatible = "snps,i2s";
+ clocks = <0x03 0x250 0x03 0x10>;
+ clock-names = "mclk\0apll";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ #sound-dai-cells = <0x00>;
+ reg = <0x00 0x50200000 0x00 0x10000>;
+ dma-names = "rx\0tx";
+ dmas = <0x3c 0x04 0x00 0x3c 0x05 0x00>;
+ vo_mclk_sel,syscrg = <0x15 0x1bc>;
+ resets = <0x18 0x22 0x01 0x18 0x22 0x02 0x18 0x21 0x02>;
+ reset-names = "i2srst\0i2sprst\0voprst";
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ port {
+ phandle = <0x5c>;
+
+ endpoint {
+ remote-endpoint = <0x59>;
+ dai-format = "i2s";
+ phandle = <0x68>;
+ };
+ };
+ };
+
+ i2s1@50210000 {
+ compatible = "snps,i2s";
+ clocks = <0x03 0x250 0x03 0x10>;
+ clock-names = "mclk\0apll";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ #sound-dai-cells = <0x00>;
+ reg = <0x00 0x50210000 0x00 0x10000>;
+ dma-names = "rx\0tx";
+ dmas = <0x3c 0x02 0x01 0x3c 0x03 0x01>;
+ vo_mclk_sel,syscrg = <0x15 0x1bc>;
+ resets = <0x18 0x22 0x01 0x18 0x22 0x02 0x18 0x21 0x02>;
+ reset-names = "i2srst\0i2sprst\0voprst";
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ port {
+ phandle = <0x5b>;
+
+ endpoint {
+ remote-endpoint = <0x5a>;
+ dai-format = "i2s";
+ phandle = <0x3a>;
+ };
+ };
+ };
+
+ i2s2@50220000 {
+ compatible = "snps,i2s";
+ clocks = <0x03 0x250 0x03 0x10>;
+ clock-names = "mclk\0apll";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ #sound-dai-cells = <0x00>;
+ reg = <0x00 0x50220000 0x00 0x10000>;
+ dma-names = "rx\0tx";
+ dmas = <0x3c 0x00 0x02 0x3c 0x01 0x02>;
+ vo_mclk_sel,syscrg = <0x15 0x1bc>;
+ resets = <0x18 0x22 0x01 0x18 0x22 0x02 0x18 0x21 0x02>;
+ reset-names = "i2srst\0i2sprst\0voprst";
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ status = "disabled";
+ };
+
+ soundcard {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "Eswin sound card";
+ numa-node-id = <0x00>;
+ };
+
+ graphcard0 {
+ compatible = "audio-graph-card";
+ numa-node-id = <0x00>;
+ status = "okay";
+ label = "Analog Audio";
+ dais = <0x5b>;
+ };
+
+ graphcard1 {
+ compatible = "audio-graph-card";
+ numa-node-id = <0x00>;
+ status = "okay";
+ label = "HDMI Audio";
+ dais = <0x5c>;
+ };
+
+ graphcard2 {
+ compatible = "audio-graph-card";
+ numa-node-id = <0x00>;
+ status = "disabled";
+ };
+
+ display-subsystem@0 {
+ compatible = "eswin,display-subsystem";
+ ports = <0x5d>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ };
+
+ dvb-subsystem {
+ compatible = "amlogic,dvb_widgets";
+ status = "disabled";
+ numa-node-id = <0x00>;
+ };
+
+ display_control@502c0000 {
+ compatible = "eswin,dc";
+ reg = <0x00 0x502c0000 0x00 0x100 0x00 0x502c0180 0x00 0x700 0x00 0x502c1400 0x00 0x1400>;
+ interrupt-parent = <0x10>;
+ interrupts = <0xee>;
+ clocks = <0x03 0x24d 0x03 0x24f 0x03 0x24c 0x03 0x04 0x03 0x2a 0x03 0x2b 0x03 0x0b 0x03 0x0d>;
+ clock-names = "cfg_clk\0pix_clk\0axi_clk\0spll0_fout1\0vo_mux\0pix_mux\0spll2_fout2\0vpll_fout1";
+ resets = <0x18 0x23 0x01 0x18 0x23 0x02 0x18 0x23 0x04 0x18 0x23 0x08>;
+ reset-names = "vo_arst\0vo_prst\0dc_arst\0dc_prst";
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ port {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ phandle = <0x5d>;
+
+ endpoint@0 {
+ reg = <0x00>;
+ remote-endpoint = <0x5e>;
+ phandle = <0x62>;
+ };
+
+ endpoint@1 {
+ reg = <0x01>;
+ remote-endpoint = <0x5f>;
+ phandle = <0x61>;
+ };
+
+ endpoint@2 {
+ reg = <0x02>;
+ remote-endpoint = <0x60>;
+ phandle = <0x67>;
+ };
+ };
+ };
+
+ es_wb@0 {
+ compatible = "eswin,virtual_display";
+ bpp = [08];
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ port {
+
+ endpoint {
+ remote-endpoint = <0x61>;
+ phandle = <0x5f>;
+ };
+ };
+ };
+
+ dsi-output@0 {
+ compatible = "eswin,dsi-encoder";
+ numa-node-id = <0x00>;
+ status = "okay";
+ };
+
+ mipi_dsi@50270000 {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ compatible = "eswin,dsi";
+ reg = <0x00 0x50270000 0x00 0x10000>;
+ clocks = <0x03 0x201>;
+ clock-names = "pclk";
+ resets = <0x18 0x21 0x01>;
+ reset-names = "phyrstn";
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ ports {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ port@0 {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00>;
+
+ endpoint {
+ remote-endpoint = <0x62>;
+ phandle = <0x5e>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x01>;
+
+ endpoint {
+ remote-endpoint = <0x63>;
+ phandle = <0x66>;
+ };
+ };
+ };
+
+ dsi_panel@0 {
+ compatible = "eswin,generic-panel";
+ reg = <0x00>;
+ dsi,format = <0x00>;
+ dsi,lanes = <0x04>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <0x64 0x65>;
+ backlight0-gpios = <0x16 0x12 0x00>;
+ rst-gpios = <0x16 0x15 0x00>;
+
+ port {
+
+ endpoint {
+ remote-endpoint = <0x66>;
+ phandle = <0x63>;
+ };
+ };
+ };
+ };
+
+ dctest@502c0000 {
+ compatible = "eswin,dc";
+ reg = <0x00 0x502c0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0xee>;
+ numa-node-id = <0x00>;
+ status = "disabled";
+ };
+
+ hdmi@502a0000 {
+ compatible = "eswin,eswin-dw-hdmi";
+ reg = <0x00 0x502a0000 0x00 0x20000>;
+ pinctrl-names = "default";
+ interrupt-parent = <0x10>;
+ interrupts = <0x112>;
+ clocks = <0x03 0x24d 0x03 0x252 0x03 0x251>;
+ clock-names = "iahb\0cec\0isfr";
+ reg-io-width = <0x04>;
+ ddc-i2c-scl-high-time-ns = <0x1264>;
+ ddc-i2c-scl-low-time-ns = <0x1334>;
+ #sound-dai-cells = <0x00>;
+ resets = <0x18 0x21 0x08 0x18 0x21 0x10 0x18 0x21 0x20>;
+ reset-names = "prstn\0phyrstn\0rstn";
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ ports {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ port@0 {
+ reg = <0x00>;
+
+ endpoint@0 {
+ remote-endpoint = <0x67>;
+ phandle = <0x60>;
+ };
+ };
+
+ port@2 {
+ reg = <0x02>;
+
+ endpoint@1 {
+ system-clock-frequency = <0xbb8000>;
+ remote-endpoint = <0x68>;
+ phandle = <0x59>;
+ };
+ };
+ };
+ };
+
+ hdmi-hdcp2@50290000 {
+ compatible = "eswin,dw-hdmi-hdcp2";
+ reg = <0x00 0x50290000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x113>;
+ clocks = <0x03 0x24c 0x03 0x24e>;
+ clock-names = "aclk\0iesmclk";
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ status = "okay";
+ };
+
+ usb0@50480000 {
+ compatible = "eswin,win2030-dwc3";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ clocks = <0x03 0x10e 0x03 0x221 0x03 0x222>;
+ clock-names = "suspend\0aclk\0cfg_clk";
+ eswin,hsp_sp_csr = <0x1a 0x800 0x808 0x83c 0x840>;
+ resets = <0x18 0x07 0x8000>;
+ reset-names = "vaux";
+ ranges;
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ dwc3@50480000 {
+ compatible = "snps,dwc3";
+ reg = <0x00 0x50480000 0x00 0x10000>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x55>;
+ interrupt-names = "peripheral";
+ dr_mode = "host";
+ phy_type = "utmi";
+ maximum-speed = "super-speed";
+ iommus = <0x19 0x0a>;
+ eswin,hsp_sp_csr = <0x1a 0x1044>;
+ dma-ranges = <0x00 0x00 0x00 0xc0000000 0x200 0x00>;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,parkmode-disable-ss-quirk;
+ status = "okay";
+ numa-node-id = <0x00>;
+ tbus = <0x02>;
+ dma-noncoherent;
+ };
+ };
+
+ usb1@50490000 {
+ compatible = "eswin,win2030-dwc3";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ clocks = <0x03 0x10f 0x03 0x221 0x03 0x222>;
+ clock-names = "suspend\0aclk\0cfg_clk";
+ eswin,hsp_sp_csr = <0x1a 0x900 0x908 0x93c 0x940>;
+ resets = <0x18 0x07 0x10000>;
+ reset-names = "vaux";
+ ranges;
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ dwc3@50490000 {
+ compatible = "snps,dwc3";
+ reg = <0x00 0x50490000 0x00 0x10000>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x56>;
+ interrupt-names = "host";
+ dr_mode = "host";
+ phy_type = "utmi";
+ maximum-speed = "super-speed";
+ iommus = <0x19 0x0b>;
+ eswin,hsp_sp_csr = <0x1a 0x1048>;
+ dma-ranges = <0x00 0x00 0x00 0xc0000000 0x200 0x00>;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,parkmode-disable-ss-quirk;
+ status = "okay";
+ numa-node-id = <0x00>;
+ tbus = <0x02>;
+ dma-noncoherent;
+
+ usb-hub {
+ gpio-hog;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x69>;
+ gpios = <0x6a 0x0b 0x00>;
+ output-low;
+ line-name = "usb-hub-reset";
+ };
+ };
+ };
+
+ vi_common_top_csr@0x51030000 {
+ compatible = "esw,vi-common-csr\0syscon";
+ clocks = <0x03 0x23f 0x03 0x241 0x03 0x243 0x03 0x240 0x03 0x24b 0x03 0x24a 0x03 0x244 0x03 0x245 0x03 0x246 0x03 0x247 0x03 0x248 0x03 0x249 0x03 0x27 0x03 0x28 0x03 0x29 0x03 0x04 0x03 0x0d>;
+ clock-names = "aclk\0cfg_clk\0isp_aclk\0dvp_clk\0phy_cfg\0phy_escclk\0sht0\0sht1\0sht2\0sht3\0sht4\0sht5\0aclk_mux\0dvp_mux\0isp_mux\0spll0_fout1\0vpll_fout1";
+ resets = <0x18 0x1c 0x01 0x18 0x1c 0x02 0x18 0x1e 0x01 0x18 0x1f 0x01 0x18 0x1d 0x01 0x18 0x20 0x01 0x18 0x20 0x02 0x18 0x20 0x04 0x18 0x20 0x08 0x18 0x20 0x10 0x18 0x20 0x20>;
+ reset-names = "axi\0cfg\0isp0\0isp1\0dvp\0sht0\0sht1\0sht2\0sht3\0sht4\0sht5";
+ interrupt-parent = <0x10>;
+ interrupts = <0x170 0x171 0x172 0x173 0x174 0x175 0x176 0x177>;
+ id = <0x00>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x51030000 0x00 0x10000>;
+ numa-node-id = <0x00>;
+ phandle = <0x6b>;
+ };
+
+ isp@0x51000000 {
+ compatible = "esw,win2030-isp";
+ reg = <0x00 0x51000000 0x00 0x10000>;
+ interrupts = <0x15 0x13 0x14>;
+ interrupt-parent = <0x10>;
+ id = <0x00>;
+ #size-cells = <0x02>;
+ dma-ranges = <0x00 0x20000000 0x00 0x80000000 0x00 0x40000000>;
+ iommus = <0x19 0x06>;
+ tbus = <0x00>;
+ eswin,vi_top_csr = <0x6b 0x1000>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "disabled";
+ };
+
+ isp@0x51010000 {
+ compatible = "esw,win2030-isp";
+ reg = <0x00 0x51010000 0x00 0x10000>;
+ interrupts = <0x18 0x16 0x17>;
+ interrupt-parent = <0x10>;
+ id = <0x01>;
+ #size-cells = <0x02>;
+ dma-ranges = <0x00 0x20000000 0x00 0x80000000 0x00 0x40000000>;
+ iommus = <0x19 0x06>;
+ tbus = <0x00>;
+ eswin,vi_top_csr = <0x6b 0x1004>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "disabled";
+ };
+
+ dewarp@51020000 {
+ compatible = "eswin,dewarp";
+ clocks = <0x03 0x23f 0x03 0x241 0x03 0x242 0x03 0x27 0x03 0x54 0x03 0x04 0x03 0x0d>;
+ clock-names = "aclk\0cfg_clk\0dw_aclk\0aclk_mux\0dw_mux\0spll0_fout1\0vpll_fout1";
+ resets = <0x18 0x1c 0x01 0x18 0x1c 0x02 0x18 0x1c 0x04>;
+ reset-names = "axi\0cfg\0dwe";
+ operating-points-v2 = <0x6c>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x1a 0x19>;
+ #size-cells = <0x02>;
+ dma-ranges = <0x00 0x20000000 0x00 0x80000000 0x00 0x40000000>;
+ iommus = <0x19 0x08>;
+ tbus = <0x00>;
+ eswin,vi_top_csr = <0x6b 0x1008>;
+ reg = <0x00 0x51020000 0x00 0xc00 0x00 0x51020c00 0x00 0x120>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ };
+
+ dphy@510c0000 {
+ compatible = "snps,dw-dphy-rx";
+ #phy-cells = <0x01>;
+ bus-width = <0x08>;
+ snps,dphy-frequency = <0x493e0>;
+ snps,phy_type = <0x08>;
+ reg = <0x00 0x510c0000 0x00 0x20000>;
+ numa-node-id = <0x00>;
+ status = "disabled";
+ };
+
+ csidma@0x52048000 {
+ compatible = "eswin,csi-video";
+ interrupt-parent = <0x10>;
+ interrupts = <0x1d>;
+ reg = <0x00 0x52048000 0x00 0x1000>;
+ numa-node-id = <0x00>;
+ status = "disabled";
+
+ port {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ endpoint@0 {
+ reg = <0x00>;
+ bus-type = <0x04>;
+ remote-endpoint = <0x6d>;
+ phandle = <0x6f>;
+ };
+ };
+ };
+
+ csidma@0x52058000 {
+ compatible = "eswin,csi-video";
+ interrupt-parent = <0x10>;
+ interrupts = <0x1e>;
+ reg = <0x00 0x52058000 0x00 0x1000>;
+ numa-node-id = <0x00>;
+ status = "disabled";
+
+ port {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ endpoint@0 {
+ reg = <0x00>;
+ bus-type = <0x04>;
+ remote-endpoint = <0x6e>;
+ phandle = <0x70>;
+ };
+ };
+ };
+
+ csi2@51050000 {
+ compatible = "snps,dw-csi";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x1d>;
+ snps,output-type = <0x00>;
+ reg = <0x00 0x51050000 0x00 0x1000>;
+ numa-node-id = <0x00>;
+ snps,en-ppi-width = <0x00>;
+ snps,en-phy-mode = <0x00>;
+ ipi2_en = <0x00>;
+ ipi2_vcid = <0x00>;
+ ipi3_en = <0x00>;
+ ipi3_vcid = <0x00>;
+ status = "disabled";
+
+ port@2 {
+ reg = <0x02>;
+
+ endpoint {
+ bus-type = <0x04>;
+ clock-lanes = <0x00>;
+ data-lanes = <0x01 0x02>;
+ remote-endpoint = <0x6f>;
+ phandle = <0x6d>;
+ };
+ };
+ };
+
+ csi2@51060000 {
+ compatible = "snps,dw-csi";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x1e>;
+ snps,output-type = <0x00>;
+ reg = <0x00 0x51060000 0x00 0x1000>;
+ numa-node-id = <0x00>;
+ snps,en-ppi-width = <0x00>;
+ snps,en-phy-mode = <0x00>;
+ ipi2_en = <0x00>;
+ ipi2_vcid = <0x00>;
+ ipi3_en = <0x00>;
+ ipi3_vcid = <0x00>;
+ status = "disabled";
+
+ port@2 {
+ reg = <0x02>;
+
+ endpoint {
+ bus-type = <0x04>;
+ remote-endpoint = <0x70>;
+ phandle = <0x6e>;
+ };
+ };
+ };
+
+ numa_sample@0 {
+ compatible = "eswin,numa-sample\0simple-bus";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ dma-ranges = <0x00 0x80000000 0x00 0xc0000000 0x00 0x80000000>;
+ iommus = <0x19 0x18>;
+ tbus = <0xf00>;
+ numa-node-id = <0x00>;
+ status = "disabled";
+ dma-noncoherent;
+ };
+
+ ddr-controller@52300000 {
+ compatible = "eswin,ddrc-1.20a";
+ interrupt-parent = <0x10>;
+ interrupts = <0x0a>;
+ interrupt-names = "ddr-ecc";
+ reg = <0x00 0x52300000 0x00 0x40000>;
+ ctrl-id = <0x00>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ };
+
+ ddr-controller@52380000 {
+ compatible = "eswin,ddrc-1.20a";
+ interrupt-parent = <0x10>;
+ interrupts = <0x12b>;
+ interrupt-names = "ddr-ecc";
+ reg = <0x00 0x52380000 0x00 0x40000>;
+ ctrl-id = <0x01>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ };
+
+ d2d-unit@52100000 {
+ compatible = "eswin,eic7x-d2d";
+ interrupt-parent = <0x10>;
+ interrupts = <0x11f 0x120>;
+ reg = <0x00 0x52100000 0x00 0x50000>;
+ reg-names = "control";
+ numa-node-id = <0x00>;
+ status = "disabled";
+ };
+ };
+
+ thermal-zones {
+
+ thermal0 {
+ polling-delay-passive = <0x1f4>;
+ polling-delay = <0x1388>;
+ sustainable-power = <0x4b0>;
+ thermal-sensors = <0x71>;
+
+ trips {
+
+ trip-point2 {
+ temperature = <0x1adb0>;
+ hysteresis = <0x00>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ };
+ };
+ };
+
+ aliases {
+ serial0 = "/soc/serial@0x50900000";
+ ethernet0 = "/soc/ethernet@50400000";
+ ethernet1 = "/soc/ethernet@50410000";
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+
+ domain-config {
+ compatible = "opensbi,domain,config";
+ system-suspend-test;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00 0x80000000 0x04 0x00>;
+ numa-node-id = <0x00>;
+ };
+
+ memory@59000000 {
+ device_type = "memory";
+ reg = <0x00 0x59000000 0x00 0x400000>;
+ numa-node-id = <0x00>;
+ };
+
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x00 0x20000000>;
+ alignment = <0x00 0x1000>;
+ alloc-ranges = <0x00 0x80000000 0x04 0x00>;
+ linux,cma-default;
+ };
+
+ sprammemory@59000000 {
+ no-map;
+ reg = <0x00 0x59000000 0x00 0x400000>;
+ phandle = <0x24>;
+ };
+
+ g2d_4GB_boundary_reserved_4k {
+ no-map;
+ reg = <0x00 0xfffff000 0x00 0x1000>;
+ };
+
+ g2d_8GB_boundary_reserved_4k {
+ no-map;
+ reg = <0x01 0xfffff000 0x00 0x1000>;
+ };
+
+ g2d_12GB_boundary_reserved_4k {
+ no-map;
+ reg = <0x02 0xfffff000 0x00 0x1000>;
+ };
+
+ mmz_nid_0_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x03 0x00 0x01 0x80000000>;
+ no-map;
+ };
+ };
+};
diff --git a/platform/riscv64/hifive-premier-p550/image/dts/minimal.dts b/platform/riscv64/hifive-premier-p550/image/dts/minimal.dts
new file mode 100644
index 00000000..8d31e015
--- /dev/null
+++ b/platform/riscv64/hifive-premier-p550/image/dts/minimal.dts
@@ -0,0 +1,815 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "sifive,hifive-premier-p550\0eswin,eic7700";
+ model = "SiFive HiFive Premier P550";
+
+ opp-table@dsp {
+ compatible = "operating-points-v2";
+ phandle = <0x22>;
+
+ opp@520000000 {
+ opp-hz = <0x00 0x1efe9200>;
+ opp-microvolt = "\0\f5";
+ };
+
+ opp@1040000000 {
+ opp-hz = <0x00 0x3dfd2400>;
+ opp-microvolt = "\0\f5";
+ };
+ };
+
+ opp-table@npu {
+ compatible = "operating-points-v2";
+ phandle = <0x1f>;
+
+ opp@1040000000 {
+ opp-hz = <0x00 0x3dfd2400>;
+ opp-microvolt = <0xdbba0>;
+ };
+
+ opp@1500000000 {
+ opp-hz = <0x00 0x59682f00>;
+ opp-microvolt = <0x100590>;
+ };
+ };
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ timebase-frequency = <0xf4240>;
+
+ idle-states {
+
+ cpu-retentive {
+ compatible = "riscv,idle-state";
+ riscv,sbi-suspend-param = <0x00>;
+ entry-latency-us = <0x14>;
+ exit-latency-us = <0x28>;
+ min-residency-us = <0x50>;
+ phandle = <0x05>;
+ };
+ };
+
+ cpu@0 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x01>;
+ reg = <0x00>;
+ riscv,isa = "rv64imafdc";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x02>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f4>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0c>;
+ };
+ };
+
+ cpu@1 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x06>;
+ reg = <0x01>;
+ riscv,isa = "rv64imafdc";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x07>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f5>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0d>;
+ };
+ };
+
+ cpu@2 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x08>;
+ reg = <0x02>;
+ riscv,isa = "rv64imafdc";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x09>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f6>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0e>;
+ };
+ };
+
+ cpu@3 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x0a>;
+ reg = <0x03>;
+ riscv,isa = "rv64imafdc";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x0b>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f7>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0f>;
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "SiFive,FU800-soc\0fu800-soc\0sifive-soc\0simple-bus";
+ ranges;
+
+ cache-controller@2010000 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ cache-block-size = <0x40>;
+ cache-level = <0x03>;
+ cache-sets = <0x1000>;
+ cache-size = <0x400000>;
+ cache-unified;
+ compatible = "sifive,ccache1\0cache\0sifive,fu740-c000-ccache";
+ interrupt-parent = <0x10>;
+ interrupts = <0x01 0x03 0x04 0x02>;
+ reg = <0x00 0x2010000 0x00 0x4000 0x00 0x8000000 0x00 0x400000>;
+ reg-names = "control\0sideband";
+ sifive,a-mshr-count = <0x3c>;
+ sifive,bank-count = <0x04>;
+ sifive,ecc-granularity = <0x08>;
+ sifive,max-master-id = <0x0d>;
+ sifive,perfmon-counters = <0x06>;
+ numa-node-id = <0x00>;
+ ranges;
+ phandle = <0x11>;
+
+ zero-device@1a000000 {
+ compatible = "l3,zero-device";
+ reg = <0x00 0x1a000000 0x00 0x400000>;
+ };
+ };
+
+ interrupt-controller@c000000 {
+ #interrupt-cells = <0x01>;
+ compatible = "sifive,plic-1.0.0";
+ interrupt-controller;
+ interrupts-extended = <0x0c 0xffffffff 0x0c 0x09 0x0d 0xffffffff 0x0d 0x09 0x0e 0xffffffff 0x0e 0x09 0x0f 0xffffffff 0x0f 0x09>;
+ reg = <0x00 0xc000000 0x00 0x4000000>;
+ reg-names = "control";
+ riscv,max-priority = <0x07>;
+ riscv,ndev = <0x208>;
+ numa-node-id = <0x00>;
+ phandle = <0x10>;
+ };
+
+ serial@0x50900000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00 0x50900000 0x00 0x10000>;
+ clock-frequency = <0xbebc200>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x64>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ phandle = <0x27>;
+ };
+
+ scu_sys_con@0x51810000 {
+ compatible = "eswin,win2030-scu-sys-con\0syscon\0simple-mfd";
+ #syscon-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x51810000 0x00 0x8000>;
+ numa-node-id = <0x00>;
+ phandle = <0x14>;
+ };
+
+ sys-crg@51828000 {
+ compatible = "eswin,win2030-sys-crg\0syscon\0simple-mfd";
+ reg = <0x00 0x51828000 0x00 0x80000>;
+ numa-node-id = <0x00>;
+ phandle = <0x12>;
+
+ reset-controller {
+ compatible = "eswin,win2030-reset";
+ #reset-cells = <0x02>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ phandle = <0x15>;
+ };
+
+ clock-controller {
+ compatible = "eswin,win2030-clock";
+ #clock-cells = <0x01>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ cpu-voltage-gpios = <0x13 0x1e 0x00>;
+ phandle = <0x03>;
+ };
+ };
+
+ hsp_sp_top_csr@0x50440000 {
+ compatible = "eswin,win2030-hsp-sp-csr\0syscon";
+ numa-node-id = <0x00>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x50440000 0x00 0x2000>;
+ phandle = <0x17>;
+ };
+
+ iommu@50c00000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x00 0x50c00000 0x00 0x100000>;
+ eswin,syscfg = <0x14 0x3fc>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x164 0x168 0x165 0x166>;
+ interrupt-names = "eventq\0gerror\0priq\0cmdq-sync";
+ #iommu-cells = <0x01>;
+ resets = <0x15 0x05 0x01 0x15 0x05 0x02 0x15 0x05 0x10 0x15 0x05 0x20 0x15 0x05 0x40 0x15 0x05 0x80 0x15 0x05 0x100 0x15 0x05 0x200 0x15 0x05 0x400 0x15 0x05 0x800>;
+ reset-names = "axi_rst\0cfg_rst\0tbu0_rst\0tbu1_rst\0tbu2_rst\0tbu3_rst\0tbu4_rst\0tbu5_rst\0tbu6_rst\0tbu7_rst";
+ status = "okay";
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ phandle = <0x16>;
+ };
+
+ eswin-npu@51c00000 {
+ compatible = "eswin,npu";
+ reg = <0x00 0x51c00000 0x00 0x400000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x183 0x10>;
+ #size-cells = <0x02>;
+ dma-ranges = <0x01 0x00 0x00 0xc0000000 0x1ff 0x00>;
+ iommus = <0x16 0x04>;
+ tbus = <0x05>;
+ dsp-avail-num = <0x01>;
+ spram-size = <0x400000>;
+ npu_mbox = <0x1e>;
+ clocks = <0x03 0x236 0x03 0x237 0x03 0x23c 0x03 0x23a 0x03 0x23d 0x03 0x26 0x03 0x25 0x03 0x0b 0x03 0x07 0x03 0x238 0x03 0x0d>;
+ clock-names = "aclk\0cfg_clk\0core_clk\0clk_npu_llc_aclk\0e31_core_clk\0mux_u_npu_core_3mux1_gfree\0mux_u_npu_llclk_3mux1_gfree\0fixed_rate_clk_spll2_fout2\0fixed_rate_clk_spll1_fout1\0clk_clk_npu_llc_src0\0fixed_rate_clk_vpll_fout1";
+ resets = <0x15 0x06 0x08>;
+ reset-names = "e31_core";
+ operating-points-v2 = <0x1f>;
+ numa-node-id = <0x00>;
+ firmware-name = "eic7700_die0_e31_fw";
+ dma-noncoherent;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x00>;
+ status = "okay";
+ npu-supply = <0x20>;
+ };
+
+ llc@51c00000 {
+ compatible = "eswin,llc";
+ reg = <0x00 0x51c00000 0x00 0x400000>;
+ eswin,syscfg = <0x14 0x324>;
+ eswin,syscrg_csr = <0x12>;
+ clocks = <0x03 0x236 0x03 0x237 0x03 0x23a 0x03 0x23c 0x03 0x26 0x03 0x0b 0x03 0x07>;
+ clock-names = "aclk\0cfg_clk\0llc_clk\0core_clk\0mux_u_npu_core_3mux1_gfree\0fixed_rate_clk_spll2_fout2\0fixed_rate_clk_spll1_fout1";
+ resets = <0x15 0x06 0x01 0x15 0x06 0x02 0x15 0x06 0x04 0x15 0x06 0x40>;
+ reset-names = "axi\0cfg\0core\0llc";
+ numa-node-id = <0x00>;
+ spram-region = <0x21>;
+ npu-supply = <0x20>;
+ status = "okay";
+ };
+
+ dsp_subsys@52280400 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x52280400 0x00 0x10000 0x00 0x51810000 0x00 0x8000>;
+ ranges;
+ numa-node-id = <0x00>;
+ dma-ranges = <0x00 0x30000000 0x00 0xc0000000 0x00 0xce000000>;
+ compatible = "es-dsp-subsys\0simple-bus";
+ clocks = <0x03 0x210 0x03 0x20f>;
+ clock-names = "cfg_clk\0aclk";
+ resets = <0x15 0x02 0x01 0x15 0x02 0x02 0x15 0x02 0x04 0x15 0x02 0x10 0x15 0x02 0x20 0x15 0x02 0x40 0x15 0x02 0x80>;
+ reset-names = "axi\0cfg\0div4\0div_0\0div_1\0div_2\0div_3";
+ status = "okay";
+
+ es_dsp@0 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b000000 0x8000 0x28100000 0x00 0x5b100000 0x20000 0x28120000 0x00 0x5b120000 0x20000>;
+ clocks = <0x03 0x2a8>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x22>;
+ dsp_mbox = <0x23>;
+ device-irq = <0x0b 0x50a90000 0x20 0x50a80000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x00>;
+ iommus = <0x16 0x12>;
+ tbus = <0x70>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ es_dsp@1 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b008000 0x8000 0x28100000 0x00 0x5b140000 0x20000 0x28120000 0x00 0x5b160000 0x20000>;
+ clocks = <0x03 0x2a9>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x22>;
+ dsp_mbox = <0x24>;
+ device-irq = <0x0d 0x50ab0000 0x40 0x50aa0000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x01>;
+ iommus = <0x16 0x13>;
+ tbus = <0x71>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ es_dsp@2 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b010000 0x8000 0x28100000 0x00 0x5b180000 0x20000 0x28120000 0x00 0x5b1a0000 0x20000>;
+ clocks = <0x03 0x2aa>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x22>;
+ dsp_mbox = <0x25>;
+ device-irq = <0x0f 0x50ad0000 0x80 0x50ac0000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x02>;
+ iommus = <0x16 0x14>;
+ tbus = <0x72>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ es_dsp@3 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b018000 0x8000 0x28100000 0x00 0x5b1c0000 0x20000 0x28120000 0x00 0x5b1e0000 0x20000>;
+ clocks = <0x03 0x2ab>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x22>;
+ dsp_mbox = <0x26>;
+ device-irq = <0x11 0x50af0000 0x100 0x50ae0000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x03>;
+ iommus = <0x16 0x15>;
+ tbus = <0x73>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ sofdsp@4 {
+ #sound-dai-cells = <0x01>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "eswin,sof-dsp";
+ reg = <0x00 0x5b018000 0x00 0x8000 0x00 0x5b1c0000 0x00 0x40000>;
+ mbox-names = "dsp-mbox";
+ mboxes = <0x26 0x00>;
+ clocks = <0x03 0x2ab>;
+ clock-names = "aclk";
+ process-id = <0x03>;
+ iommus = <0x16 0x15>;
+ tbus = <0x73>;
+ dma-noncoherent;
+ mailbox-dsp-to-u84-addr = <0x50af0000>;
+ mailbox-u84-to-dsp-addr = <0x50ae0000>;
+ dsp-uart = <0x27>;
+ device-uart-mutex = <0x51820000>;
+ numa-node-id = <0x00>;
+ };
+ };
+
+ mmc@0x50460000 {
+ compatible = "eswin,sdhci-sdio";
+ reg = <0x00 0x50460000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x51>;
+ clocks = <0x03 0x22b 0x03 0x222 0x03 0x0c 0x03 0x23>;
+ clock-names = "clk_xin\0clk_ahb\0clk_spll2_fout3\0clk_mux1_1";
+ clock-output-names = "sdio0_cardclock";
+ #clock-cells = <0x00>;
+ resets = <0x15 0x07 0x80 0x15 0x07 0x10 0x15 0x07 0x40000 0x15 0x07 0x400000>;
+ reset-names = "txrx_rst\0phy_rst\0prstn\0arstn";
+ clock-frequency = <0xc65d400>;
+ max-frequency = <0xc65d400>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ dma-ranges = <0x00 0x20000000 0x00 0xc0000000 0x00 0x40000000>;
+ iommus = <0x16 0x10>;
+ tbus = <0x02>;
+ eswin,hsp_sp_csr = <0x17 0x103c 0x608 0x60c>;
+ eswin,syscrg_csr = <0x12 0x164 0x148 0x14c>;
+ bus-width = <0x04>;
+ sdio-id = <0x00>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ dma-noncoherent;
+ delay_code = <0x55>;
+ drive-impedance-ohm = <0x21>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ no-sdio;
+ no-mmc;
+ };
+
+ mbox@50a00000 {
+ compatible = "eswin,win2030-mailbox";
+ reg = <0x00 0x50a00000 0x00 0x10000 0x00 0x50a10000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x75>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x27e 0x03 0x27f>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x15 0x0c 0x01 0x15 0x0c 0x02>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x02>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x30>;
+ };
+
+ mbox@50a20000 {
+ compatible = "eswin,win2030-mailbox";
+ reg = <0x00 0x50a20000 0x00 0x10000 0x00 0x50a30000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x77>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x280 0x03 0x281>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x15 0x0c 0x04 0x15 0x0c 0x08>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x04>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x31>;
+ };
+
+ mbox@50a40000 {
+ compatible = "eswin,npu0-mailbox";
+ reg = <0x00 0x50a40000 0x00 0x10000 0x00 0x50a50000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x79>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x282 0x03 0x283>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x15 0x0c 0x10 0x15 0x0c 0x20>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x08>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x1e>;
+ };
+
+ mbox@50a60000 {
+ compatible = "eswin,win2030-mailbox";
+ reg = <0x00 0x50a60000 0x00 0x10000 0x00 0x50a70000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x7b>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x284 0x03 0x285>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x15 0x0c 0x40 0x15 0x0c 0x80>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x10>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ };
+
+ mbox@50a80000 {
+ compatible = "eswin,dsp0-mailbox";
+ reg = <0x00 0x50a80000 0x00 0x10000 0x00 0x50a90000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x7d>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x286 0x03 0x287>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x15 0x0c 0x100 0x15 0x0c 0x200>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x20>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x23>;
+ };
+
+ mbox@50aa0000 {
+ compatible = "eswin,dsp1-mailbox";
+ reg = <0x00 0x50aa0000 0x00 0x10000 0x00 0x50ab0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x7f>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x288 0x03 0x289>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x15 0x0c 0x400 0x15 0x0c 0x800>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x40>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x24>;
+ };
+
+ mbox@50ac0000 {
+ compatible = "eswin,dsp2-mailbox";
+ reg = <0x00 0x50ac0000 0x00 0x10000 0x00 0x50ad0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x81>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x28a 0x03 0x28b>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x15 0x0c 0x1000 0x15 0x0c 0x2000>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x80>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x25>;
+ };
+
+ mbox@50ae0000 {
+ compatible = "eswin,dsp3-mailbox";
+ reg = <0x00 0x50ae0000 0x00 0x10000 0x00 0x50af0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x83>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x28c 0x03 0x28d>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x15 0x0c 0x4000 0x15 0x0c 0x8000>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x100>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x26>;
+ };
+
+ i2c@51838000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x2a0>;
+ clock-names = "pclk";
+ resets = <0x15 0x25 0x01>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x51838000 0x00 0x8000>;
+ interrupts = <0x123>;
+ interrupt-parent = <0x10>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ eswin,syscfg = <0x14 0x3c0 0x0f>;
+ i2c-sda-hold-time-ns = <0x40>;
+
+ mpq8785@12 {
+ compatible = "mps,mpq8785";
+ reg = <0x12>;
+ eswin,regulator_default-microvolt = <0xf4240>;
+ eswin,regulator_label = "supply vdd1\0npu vdd1\0npu current1\0npu temperature1";
+ label = "npu_vdd";
+
+ regulators {
+
+ npu_svcc {
+ regulator-name = "NPU_SVCC";
+ regulator-min-microvolt = <0xaae60>;
+ regulator-max-microvolt = <0x10c8e0>;
+ regulator-min-microamp = <0x1312d00>;
+ regulator-max-microamp = <0x2625a00>;
+ regulator-ov-protection-microvolt = <0x10c8e0>;
+ phandle = <0x20>;
+ };
+ };
+ };
+ };
+ };
+
+ aliases {
+ serial0 = "/soc/serial@0x50900000";
+ };
+
+ chosen {
+ bootargs = "root=PARTUUID=b0f77ad6-36cd-4a99-a8c0-31d73649aa09 console=ttyS0,115200 root=PARTUUID=b0f77ad6-36cd-4a99-a8c0-31d73649aa09 rootfstype=ext4 rootwait rw earlycon selinux=0 LANG=en_US.UTF-8";
+ stdout-path = "serial0:115200n8";
+
+ domain-config {
+ compatible = "opensbi,domain,config";
+ system-suspend-test;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00 0x80000000 0x04 0x00>;
+ numa-node-id = <0x00>;
+ };
+
+ memory@59000000 {
+ device_type = "memory";
+ reg = <0x00 0x59000000 0x00 0x400000>;
+ numa-node-id = <0x00>;
+ };
+
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ opensbi@80000000 {
+ no-map;
+ reg = <0x00 0x80000000 0x00 0x00200000>;
+ };
+
+ sprammemory@59000000 {
+ no-map;
+ reg = <0x00 0x59000000 0x00 0x400000>;
+ phandle = <0x21>;
+ };
+
+ mmz_nid_0_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x03 0x00 0x01 0x80000000>;
+ no-map;
+ };
+ };
+};
diff --git a/platform/riscv64/hifive-premier-p550/image/dts/zone0-npu.dts b/platform/riscv64/hifive-premier-p550/image/dts/zone0-npu.dts
new file mode 100644
index 00000000..8c5b65fa
--- /dev/null
+++ b/platform/riscv64/hifive-premier-p550/image/dts/zone0-npu.dts
@@ -0,0 +1,673 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "sifive,hifive-premier-p550\0eswin,eic7700";
+ model = "SiFive HiFive Premier P550";
+
+ opp-table@dsp {
+ compatible = "operating-points-v2";
+ phandle = <0x22>;
+
+ opp@520000000 {
+ opp-hz = <0x00 0x1efe9200>;
+ opp-microvolt = "\0\f5";
+ };
+
+ opp@1040000000 {
+ opp-hz = <0x00 0x3dfd2400>;
+ opp-microvolt = "\0\f5";
+ };
+ };
+
+ opp-table@npu {
+ compatible = "operating-points-v2";
+ phandle = <0x1f>;
+
+ opp@1040000000 {
+ opp-hz = <0x00 0x3dfd2400>;
+ opp-microvolt = <0xdbba0>;
+ };
+
+ opp@1500000000 {
+ opp-hz = <0x00 0x59682f00>;
+ opp-microvolt = <0x100590>;
+ };
+ };
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ timebase-frequency = <0xf4240>;
+
+ idle-states {
+
+ cpu-retentive {
+ compatible = "riscv,idle-state";
+ riscv,sbi-suspend-param = <0x00>;
+ entry-latency-us = <0x14>;
+ exit-latency-us = <0x28>;
+ min-residency-us = <0x50>;
+ phandle = <0x05>;
+ };
+ };
+
+ cpu@0 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x01>;
+ reg = <0x00>;
+ riscv,isa = "rv64imafdc";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x02>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f4>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0c>;
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "SiFive,FU800-soc\0fu800-soc\0sifive-soc\0simple-bus";
+ ranges;
+
+ cache-controller@2010000 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ cache-block-size = <0x40>;
+ cache-level = <0x03>;
+ cache-sets = <0x1000>;
+ cache-size = <0x400000>;
+ cache-unified;
+ compatible = "sifive,ccache1\0cache\0sifive,fu740-c000-ccache";
+ interrupt-parent = <0x10>;
+ interrupts = <0x01 0x03 0x04 0x02>;
+ reg = <0x00 0x2010000 0x00 0x4000 0x00 0x8000000 0x00 0x400000>;
+ reg-names = "control\0sideband";
+ sifive,a-mshr-count = <0x3c>;
+ sifive,bank-count = <0x04>;
+ sifive,ecc-granularity = <0x08>;
+ sifive,max-master-id = <0x0d>;
+ sifive,perfmon-counters = <0x06>;
+ numa-node-id = <0x00>;
+ ranges;
+ phandle = <0x11>;
+
+ zero-device@1a000000 {
+ compatible = "l3,zero-device";
+ reg = <0x00 0x1a000000 0x00 0x400000>;
+ };
+ };
+
+ interrupt-controller@c000000 {
+ #interrupt-cells = <0x01>;
+ compatible = "sifive,plic-1.0.0";
+ interrupt-controller;
+ interrupts-extended = <0x0c 0xffffffff 0x0c 0x09>;
+ reg = <0x00 0xc000000 0x00 0x4000000>;
+ reg-names = "control";
+ riscv,max-priority = <0x07>;
+ riscv,ndev = <0x208>;
+ numa-node-id = <0x00>;
+ phandle = <0x10>;
+ };
+
+ serial@0x50900000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00 0x50900000 0x00 0x10000>;
+ clock-frequency = <0xbebc200>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x64>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ phandle = <0x27>;
+ };
+
+ scu_sys_con@0x51810000 {
+ compatible = "eswin,win2030-scu-sys-con\0syscon\0simple-mfd";
+ #syscon-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x51810000 0x00 0x8000>;
+ numa-node-id = <0x00>;
+ phandle = <0x14>;
+ };
+
+ sys-crg@51828000 {
+ compatible = "eswin,win2030-sys-crg\0syscon\0simple-mfd";
+ reg = <0x00 0x51828000 0x00 0x80000>;
+ numa-node-id = <0x00>;
+ phandle = <0x12>;
+
+ reset-controller {
+ compatible = "eswin,win2030-reset";
+ #reset-cells = <0x02>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ phandle = <0x15>;
+ };
+
+ clock-controller {
+ compatible = "eswin,win2030-clock";
+ #clock-cells = <0x01>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ cpu-voltage-gpios = <0x13 0x1e 0x00>;
+ phandle = <0x03>;
+ };
+ };
+
+ hsp_sp_top_csr@0x50440000 {
+ compatible = "eswin,win2030-hsp-sp-csr\0syscon";
+ numa-node-id = <0x00>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x50440000 0x00 0x2000>;
+ phandle = <0x17>;
+ };
+
+ iommu@50c00000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x00 0x50c00000 0x00 0x100000>;
+ eswin,syscfg = <0x14 0x3fc>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x164 0x168 0x165 0x166>;
+ interrupt-names = "eventq\0gerror\0priq\0cmdq-sync";
+ #iommu-cells = <0x01>;
+ resets = <0x15 0x05 0x01 0x15 0x05 0x02 0x15 0x05 0x10 0x15 0x05 0x20 0x15 0x05 0x40 0x15 0x05 0x80 0x15 0x05 0x100 0x15 0x05 0x200 0x15 0x05 0x400 0x15 0x05 0x800>;
+ reset-names = "axi_rst\0cfg_rst\0tbu0_rst\0tbu1_rst\0tbu2_rst\0tbu3_rst\0tbu4_rst\0tbu5_rst\0tbu6_rst\0tbu7_rst";
+ status = "okay";
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ phandle = <0x16>;
+ };
+
+ eswin-npu@51c00000 {
+ compatible = "eswin,npu";
+ reg = <0x00 0x51c00000 0x00 0x400000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x183 0x10>;
+ #size-cells = <0x02>;
+ dma-ranges = <0x01 0x00 0x00 0xc0000000 0x1ff 0x00>;
+ iommus = <0x16 0x04>;
+ tbus = <0x05>;
+ dsp-avail-num = <0x01>;
+ spram-size = <0x400000>;
+ npu_mbox = <0x1e>;
+ clocks = <0x03 0x236 0x03 0x237 0x03 0x23c 0x03 0x23a 0x03 0x23d 0x03 0x26 0x03 0x25 0x03 0x0b 0x03 0x07 0x03 0x238 0x03 0x0d>;
+ clock-names = "aclk\0cfg_clk\0core_clk\0clk_npu_llc_aclk\0e31_core_clk\0mux_u_npu_core_3mux1_gfree\0mux_u_npu_llclk_3mux1_gfree\0fixed_rate_clk_spll2_fout2\0fixed_rate_clk_spll1_fout1\0clk_clk_npu_llc_src0\0fixed_rate_clk_vpll_fout1";
+ resets = <0x15 0x06 0x08>;
+ reset-names = "e31_core";
+ operating-points-v2 = <0x1f>;
+ numa-node-id = <0x00>;
+ firmware-name = "eic7700_die0_e31_fw";
+ dma-noncoherent;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x00>;
+ status = "okay";
+ npu-supply = <0x20>;
+ };
+
+ llc@51c00000 {
+ compatible = "eswin,llc";
+ reg = <0x00 0x51c00000 0x00 0x400000>;
+ eswin,syscfg = <0x14 0x324>;
+ eswin,syscrg_csr = <0x12>;
+ clocks = <0x03 0x236 0x03 0x237 0x03 0x23a 0x03 0x23c 0x03 0x26 0x03 0x0b 0x03 0x07>;
+ clock-names = "aclk\0cfg_clk\0llc_clk\0core_clk\0mux_u_npu_core_3mux1_gfree\0fixed_rate_clk_spll2_fout2\0fixed_rate_clk_spll1_fout1";
+ resets = <0x15 0x06 0x01 0x15 0x06 0x02 0x15 0x06 0x04 0x15 0x06 0x40>;
+ reset-names = "axi\0cfg\0core\0llc";
+ numa-node-id = <0x00>;
+ spram-region = <0x21>;
+ npu-supply = <0x20>;
+ status = "okay";
+ };
+
+ dsp_subsys@52280400 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x52280400 0x00 0x10000 0x00 0x51810000 0x00 0x8000>;
+ ranges;
+ numa-node-id = <0x00>;
+ dma-ranges = <0x00 0x30000000 0x00 0xc0000000 0x00 0xce000000>;
+ compatible = "es-dsp-subsys\0simple-bus";
+ clocks = <0x03 0x210 0x03 0x20f>;
+ clock-names = "cfg_clk\0aclk";
+ resets = <0x15 0x02 0x01 0x15 0x02 0x02 0x15 0x02 0x04 0x15 0x02 0x10 0x15 0x02 0x20 0x15 0x02 0x40 0x15 0x02 0x80>;
+ reset-names = "axi\0cfg\0div4\0div_0\0div_1\0div_2\0div_3";
+ status = "okay";
+
+ es_dsp@0 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b000000 0x8000 0x28100000 0x00 0x5b100000 0x20000 0x28120000 0x00 0x5b120000 0x20000>;
+ clocks = <0x03 0x2a8>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x22>;
+ dsp_mbox = <0x23>;
+ device-irq = <0x0b 0x50a90000 0x20 0x50a80000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x00>;
+ iommus = <0x16 0x12>;
+ tbus = <0x70>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ es_dsp@1 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b008000 0x8000 0x28100000 0x00 0x5b140000 0x20000 0x28120000 0x00 0x5b160000 0x20000>;
+ clocks = <0x03 0x2a9>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x22>;
+ dsp_mbox = <0x24>;
+ device-irq = <0x0d 0x50ab0000 0x40 0x50aa0000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x01>;
+ iommus = <0x16 0x13>;
+ tbus = <0x71>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ es_dsp@2 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b010000 0x8000 0x28100000 0x00 0x5b180000 0x20000 0x28120000 0x00 0x5b1a0000 0x20000>;
+ clocks = <0x03 0x2aa>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x22>;
+ dsp_mbox = <0x25>;
+ device-irq = <0x0f 0x50ad0000 0x80 0x50ac0000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x02>;
+ iommus = <0x16 0x14>;
+ tbus = <0x72>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ es_dsp@3 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b018000 0x8000 0x28100000 0x00 0x5b1c0000 0x20000 0x28120000 0x00 0x5b1e0000 0x20000>;
+ clocks = <0x03 0x2ab>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x22>;
+ dsp_mbox = <0x26>;
+ device-irq = <0x11 0x50af0000 0x100 0x50ae0000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x03>;
+ iommus = <0x16 0x15>;
+ tbus = <0x73>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ sofdsp@4 {
+ #sound-dai-cells = <0x01>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "eswin,sof-dsp";
+ reg = <0x00 0x5b018000 0x00 0x8000 0x00 0x5b1c0000 0x00 0x40000>;
+ mbox-names = "dsp-mbox";
+ mboxes = <0x26 0x00>;
+ clocks = <0x03 0x2ab>;
+ clock-names = "aclk";
+ process-id = <0x03>;
+ iommus = <0x16 0x15>;
+ tbus = <0x73>;
+ dma-noncoherent;
+ mailbox-dsp-to-u84-addr = <0x50af0000>;
+ mailbox-u84-to-dsp-addr = <0x50ae0000>;
+ dsp-uart = <0x27>;
+ device-uart-mutex = <0x51820000>;
+ numa-node-id = <0x00>;
+ };
+ };
+
+ mmc@0x50460000 {
+ compatible = "eswin,sdhci-sdio";
+ reg = <0x00 0x50460000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x51>;
+ clocks = <0x03 0x22b 0x03 0x222 0x03 0x0c 0x03 0x23>;
+ clock-names = "clk_xin\0clk_ahb\0clk_spll2_fout3\0clk_mux1_1";
+ clock-output-names = "sdio0_cardclock";
+ #clock-cells = <0x00>;
+ resets = <0x15 0x07 0x80 0x15 0x07 0x10 0x15 0x07 0x40000 0x15 0x07 0x400000>;
+ reset-names = "txrx_rst\0phy_rst\0prstn\0arstn";
+ clock-frequency = <0xc65d400>;
+ max-frequency = <0xc65d400>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ dma-ranges = <0x00 0x20000000 0x00 0xc0000000 0x00 0x40000000>;
+ iommus = <0x16 0x10>;
+ tbus = <0x02>;
+ eswin,hsp_sp_csr = <0x17 0x103c 0x608 0x60c>;
+ eswin,syscrg_csr = <0x12 0x164 0x148 0x14c>;
+ bus-width = <0x04>;
+ sdio-id = <0x00>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ dma-noncoherent;
+ delay_code = <0x55>;
+ drive-impedance-ohm = <0x21>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ no-sdio;
+ no-mmc;
+ };
+
+ mbox@50a00000 {
+ compatible = "eswin,win2030-mailbox";
+ reg = <0x00 0x50a00000 0x00 0x10000 0x00 0x50a10000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x75>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x27e 0x03 0x27f>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x15 0x0c 0x01 0x15 0x0c 0x02>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x02>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x30>;
+ };
+
+ mbox@50a20000 {
+ compatible = "eswin,win2030-mailbox";
+ reg = <0x00 0x50a20000 0x00 0x10000 0x00 0x50a30000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x77>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x280 0x03 0x281>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x15 0x0c 0x04 0x15 0x0c 0x08>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x04>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x31>;
+ };
+
+ mbox@50a40000 {
+ compatible = "eswin,npu0-mailbox";
+ reg = <0x00 0x50a40000 0x00 0x10000 0x00 0x50a50000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x79>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x282 0x03 0x283>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x15 0x0c 0x10 0x15 0x0c 0x20>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x08>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x1e>;
+ };
+
+ mbox@50a60000 {
+ compatible = "eswin,win2030-mailbox";
+ reg = <0x00 0x50a60000 0x00 0x10000 0x00 0x50a70000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x7b>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x284 0x03 0x285>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x15 0x0c 0x40 0x15 0x0c 0x80>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x10>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ };
+
+ mbox@50a80000 {
+ compatible = "eswin,dsp0-mailbox";
+ reg = <0x00 0x50a80000 0x00 0x10000 0x00 0x50a90000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x7d>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x286 0x03 0x287>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x15 0x0c 0x100 0x15 0x0c 0x200>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x20>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x23>;
+ };
+
+ mbox@50aa0000 {
+ compatible = "eswin,dsp1-mailbox";
+ reg = <0x00 0x50aa0000 0x00 0x10000 0x00 0x50ab0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x7f>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x288 0x03 0x289>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x15 0x0c 0x400 0x15 0x0c 0x800>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x40>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x24>;
+ };
+
+ mbox@50ac0000 {
+ compatible = "eswin,dsp2-mailbox";
+ reg = <0x00 0x50ac0000 0x00 0x10000 0x00 0x50ad0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x81>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x28a 0x03 0x28b>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x15 0x0c 0x1000 0x15 0x0c 0x2000>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x80>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x25>;
+ };
+
+ mbox@50ae0000 {
+ compatible = "eswin,dsp3-mailbox";
+ reg = <0x00 0x50ae0000 0x00 0x10000 0x00 0x50af0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x83>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x28c 0x03 0x28d>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x15 0x0c 0x4000 0x15 0x0c 0x8000>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x100>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x26>;
+ };
+
+ i2c@51838000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x2a0>;
+ clock-names = "pclk";
+ resets = <0x15 0x25 0x01>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x51838000 0x00 0x8000>;
+ interrupts = <0x123>;
+ interrupt-parent = <0x10>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ eswin,syscfg = <0x14 0x3c0 0x0f>;
+ i2c-sda-hold-time-ns = <0x40>;
+
+ mpq8785@12 {
+ compatible = "mps,mpq8785";
+ reg = <0x12>;
+ eswin,regulator_default-microvolt = <0xf4240>;
+ eswin,regulator_label = "supply vdd1\0npu vdd1\0npu current1\0npu temperature1";
+ label = "npu_vdd";
+
+ regulators {
+
+ npu_svcc {
+ regulator-name = "NPU_SVCC";
+ regulator-min-microvolt = <0xaae60>;
+ regulator-max-microvolt = <0x10c8e0>;
+ regulator-min-microamp = <0x1312d00>;
+ regulator-max-microamp = <0x2625a00>;
+ regulator-ov-protection-microvolt = <0x10c8e0>;
+ phandle = <0x20>;
+ };
+ };
+ };
+ };
+ };
+
+ aliases {
+ serial0 = "/soc/serial@0x50900000";
+ };
+
+ chosen {
+ bootargs = "root=PARTUUID=b0f77ad6-36cd-4a99-a8c0-31d73649aa09 console=ttyS0,115200 root=PARTUUID=b0f77ad6-36cd-4a99-a8c0-31d73649aa09 rootfstype=ext4 rootwait rw earlycon selinux=0 LANG=en_US.UTF-8 init=/bin/bash";
+ stdout-path = "serial0:115200n8";
+
+ domain-config {
+ compatible = "opensbi,domain,config";
+ system-suspend-test;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00 0x80000000 0x04 0x00>;
+ numa-node-id = <0x00>;
+ };
+
+ memory@59000000 {
+ device_type = "memory";
+ reg = <0x00 0x59000000 0x00 0x400000>;
+ numa-node-id = <0x00>;
+ };
+
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ opensbi@80000000 {
+ no-map;
+ reg = <0x00 0x80000000 0x00 0x00200000>;
+ };
+
+ hvisor@80200000 {
+ no-map;
+ reg = <0x00 0x80200000 0x00 0x02E00000>;
+ };
+
+ sprammemory@59000000 {
+ no-map;
+ reg = <0x00 0x59000000 0x00 0x400000>;
+ phandle = <0x21>;
+ };
+
+ mmz_nid_0_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x03 0x00 0x01 0x80000000>;
+ no-map;
+ };
+ };
+};
diff --git a/platform/riscv64/hifive-premier-p550/image/dts/zone0.dts b/platform/riscv64/hifive-premier-p550/image/dts/zone0.dts
new file mode 100644
index 00000000..3a327483
--- /dev/null
+++ b/platform/riscv64/hifive-premier-p550/image/dts/zone0.dts
@@ -0,0 +1,246 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "sifive,hifive-unmatched-a00\0sifive,fu740-c000\0sifive,fu740\0eswin,eic7700";
+ model = "SiFive HiFive Premier P550";
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ timebase-frequency = <0xf4240>;
+
+ cpu@0 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x01>;
+ reg = <0x00>;
+ riscv,isa = "rv64imafdc";
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ clocks = <0x03 0x1f4>;
+ phandle = <0x4a>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0c>;
+ };
+ };
+ };
+
+ memory@80000000 {
+ compatible = "sifive,axi4-mem-port\0sifive,axi4-port\0sifive,mem-port";
+ device_type = "memory";
+ reg = <0x00 0x80000000 0x00 0x80000000>;
+ sifive,port-width-bytes = <0x20>;
+ phandle = <0x14>;
+ };
+
+ soc {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "SiFive,FU800-soc\0fu800-soc\0sifive-soc\0simple-bus";
+ ranges;
+
+ cache-controller@2010000 {
+ cache-block-size = <0x40>;
+ cache-level = <0x03>;
+ cache-sets = <0x1000>;
+ cache-size = <0x400000>;
+ cache-unified;
+ compatible = "sifive,ccache1\0cache\0sifive,fu740-c000-ccache";
+ // interrupt-parent = <0x10>;
+ // interrupts = <0x01 0x03 0x04 0x02>;
+ next-level-cache = <0x14>;
+ reg = <0x00 0x2010000 0x00 0x4000 0x00 0x8000000 0x00 0x400000>;
+ reg-names = "control\0sideband";
+ sifive,a-mshr-count = <0x3c>;
+ sifive,bank-count = <0x04>;
+ sifive,ecc-granularity = <0x08>;
+ sifive,max-master-id = <0x0d>;
+ sifive,perfmon-counters = <0x06>;
+ numa-node-id = <0x00>;
+ phandle = <0x15>;
+ };
+
+ interrupt-controller@c000000 {
+ #interrupt-cells = <0x01>;
+ compatible = "sifive,plic-1.0.0";
+ interrupt-controller;
+ interrupts-extended = <0x0c 0xffffffff 0x0c 0x09>;
+ reg = <0x00 0xc000000 0x00 0x4000000>;
+ reg-names = "control";
+ riscv,max-priority = <0x07>;
+ riscv,ndev = <0x208>;
+ phandle = <0x10>;
+ };
+
+ pl2@104000 {
+ cache-block-size = <0x40>;
+ cache-level = <0x02>;
+ cache-sets = <0x200>;
+ cache-size = <0x40000>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0\0cache";
+ next-level-cache = <0x15>;
+ reg = <0x00 0x104000 0x00 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <0x10>;
+ sifive,perfmon-counters = <0x06>;
+ phandle = <0x01>;
+ };
+
+ serial@0x50900000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00 0x50900000 0x00 0x10000>;
+ clock-frequency = <0xbebc200>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x64>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ status = "okay";
+ };
+
+ // serial@0x50920000 {
+ // compatible = "snps,dw-apb-uart";
+ // reg = <0x00 0x50920000 0x00 0x10000>;
+ // clock-frequency = <0xbebc200>;
+ // interrupt-parent = <0x10>;
+ // interrupts = <0x66>;
+ // reg-shift = <0x02>;
+ // reg-io-width = <0x04>;
+ // status = "okay";
+ // };
+
+ sys-crg@51828000 {
+ compatible = "eswin,win2030-sys-crg\0syscon\0simple-mfd";
+ reg = <0x00 0x51828000 0x00 0x80000>;
+ numa-node-id = <0x00>;
+ phandle = <0x16>;
+
+ reset-controller {
+ compatible = "eswin,win2030-reset";
+ #reset-cells = <0x02>;
+ status = "okay";
+ phandle = <0x18>;
+ };
+
+ clock-controller {
+ compatible = "eswin,win2030-clock";
+ #clock-cells = <0x01>;
+ status = "okay";
+ force-1_8ghz;
+ phandle = <0x03>;
+ };
+ };
+
+ hsp_sp_top_csr@0x50440000 {
+ compatible = "eswin,win2030-hsp-sp-csr\0syscon";
+ #size-cells = <0x02>;
+ reg = <0x00 0x50440000 0x00 0x2000>;
+ phandle = <0x1a>;
+ };
+
+ mmc@0x50460000 {
+ compatible = "eswin,sdhci-sdio";
+ reg = <0x00 0x50460000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x51>;
+ clocks = <0x03 0x22b 0x03 0x222 0x03 0x0c 0x03 0x23>;
+ clock-names = "clk_xin\0clk_ahb\0clk_spll2_fout3\0clk_mux1_1";
+ clock-output-names = "sdio0_cardclock";
+ #clock-cells = <0x00>;
+ resets = <0x18 0x07 0x80 0x18 0x07 0x10 0x18 0x07 0x40000 0x18 0x07 0x400000>;
+ reset-names = "txrx_rst\0phy_rst\0prstn\0arstn";
+ clock-frequency = <0xc65d400>;
+ max-frequency = <0xc65d400>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ eswin,hsp_sp_csr = <0x1a 0x103c 0x608 0x60c>;
+ eswin,syscrg_csr = <0x16 0x164 0x148 0x14c>;
+ bus-width = <0x04>;
+ sdio-id = <0x00>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ dma-noncoherent;
+ delay_code = <0x3b>;
+ drive-impedance-ohm = <0x21>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ no-sdio;
+ no-mmc;
+ disable-wp;
+ broken-cd;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ opensbi@80000000 {
+ no-map;
+ reg = <0x00 0x80000000 0x00 0x00200000>;
+ };
+
+ hvisor@80200000 {
+ no-map;
+ reg = <0x00 0x80200000 0x00 0x02E00000>;
+ };
+
+ nonroot@0x83000000 {
+ no-map;
+ reg = <0x00 0x83000000 0x00 0x0C000000>;
+ };
+
+ dtbfile@0x8f000000 {
+ no-map;
+ reg = <0x00 0x8f000000 0x00 0x01000000>;
+ };
+ };
+
+ hvisor_virtio_device {
+ compatible = "hvisor";
+ interrupt-parent = <0x10>;
+ interrupts = <0x20>;
+ };
+
+ aliases {
+ serial0 = "/soc/serial@0x50900000";
+ // serial2 = "/soc/serial@0x50920000";
+ };
+
+ chosen {
+ bootargs = "earlycon console=ttyS0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait init=/bin/bash";
+ stdout-path = "serial0:115200n8";
+ // bootargs = "earlycon console=ttyS2,115200 root=/dev/mmcblk0p3 rootfstype=ext4 rw rootwait init=/bin/bash";
+ // stdout-path = "serial2:115200n8";
+ };
+};
diff --git a/platform/riscv64/hifive-premier-p550/image/dts/zone1-linux-virtio.dts b/platform/riscv64/hifive-premier-p550/image/dts/zone1-linux-virtio.dts
new file mode 100644
index 00000000..d53d70e4
--- /dev/null
+++ b/platform/riscv64/hifive-premier-p550/image/dts/zone1-linux-virtio.dts
@@ -0,0 +1,105 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "sifive,hifive-unmatched-a00\0sifive,fu740-c000\0sifive,fu740\0eswin,eic7700";
+ model = "SiFive HiFive Premier P550";
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ timebase-frequency = <0xf4240>;
+
+ cpu@1 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ // hardware-exec-breakpoint-count = <0x04>;
+ // hwpf-distanceBits = <0x06>;
+ // hwpf-hitCacheThrdBits = <0x05>;
+ // hwpf-hitMSHRThrdBits = <0x04>;
+ // hwpf-l2pfPoolSize = <0x0a>;
+ // hwpf-nIssQEnt = <0x06>;
+ // hwpf-nPrefetchQueueEntries = <0x08>;
+ // hwpf-nStreams = <0x10>;
+ // hwpf-qFullnessThrdBits = <0x04>;
+ // hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ reg = <0x01>;
+ riscv,isa = "rv64imafdc";
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ clocks = <0x03 0x1f5>;
+ phandle = <0x4b>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0d>;
+ };
+ };
+ };
+
+ memory@80000000 {
+ compatible = "sifive,axi4-mem-port\0sifive,axi4-port\0sifive,mem-port";
+ device_type = "memory";
+ reg = <0x00 0x83000000 0x00 0x0C000000>;
+ sifive,port-width-bytes = <0x20>;
+ phandle = <0x14>;
+ };
+
+ soc {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "SiFive,FU800-soc\0fu800-soc\0sifive-soc\0simple-bus";
+ ranges;
+
+ interrupt-controller@c000000 {
+ #interrupt-cells = <0x01>;
+ compatible = "sifive,plic-1.0.0";
+ interrupt-controller;
+ interrupts-extended = <0x0d 0xffffffff 0x0d 0x09>;
+ reg = <0x00 0xc000000 0x00 0x4000000>;
+ reg-names = "control";
+ riscv,max-priority = <0x07>;
+ riscv,ndev = <0x208>;
+ phandle = <0x10>;
+ };
+
+ virtio_mmio@10006000 {
+ interrupts = <0x06>;
+ interrupt-parent = <0x10>;
+ reg = <0x00 0x10006000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10007000 {
+ interrupts = <0x07>;
+ interrupt-parent = <0x10>;
+ reg = <0x00 0x10007000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+ };
+
+ aliases {
+ virtio-console = "/soc/virtio_mmio@10007000";
+ };
+
+ chosen {
+ bootargs = "earlycon console=hvc0 root=/dev/vda rootfstype=ext4 rw rootwait";
+ stdout-path = "virtio-console";
+ };
+};
diff --git a/platform/riscv64/hifive-premier-p550/image/dts/zone1-linux.dts b/platform/riscv64/hifive-premier-p550/image/dts/zone1-linux.dts
new file mode 100644
index 00000000..5eabac38
--- /dev/null
+++ b/platform/riscv64/hifive-premier-p550/image/dts/zone1-linux.dts
@@ -0,0 +1,186 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "sifive,hifive-unmatched-a00\0sifive,fu740-c000\0sifive,fu740\0eswin,eic7700";
+ model = "Milk-V Megrez";
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ timebase-frequency = <0xf4240>;
+
+ cpu@1 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ // hardware-exec-breakpoint-count = <0x04>;
+ // hwpf-distanceBits = <0x06>;
+ // hwpf-hitCacheThrdBits = <0x05>;
+ // hwpf-hitMSHRThrdBits = <0x04>;
+ // hwpf-l2pfPoolSize = <0x0a>;
+ // hwpf-nIssQEnt = <0x06>;
+ // hwpf-nPrefetchQueueEntries = <0x08>;
+ // hwpf-nStreams = <0x10>;
+ // hwpf-qFullnessThrdBits = <0x04>;
+ // hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ reg = <0x01>;
+ riscv,isa = "rv64imafdc";
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ clocks = <0x03 0x1f5>;
+ phandle = <0x4b>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0d>;
+ };
+ };
+ };
+
+ memory@80000000 {
+ compatible = "sifive,axi4-mem-port\0sifive,axi4-port\0sifive,mem-port";
+ device_type = "memory";
+ reg = <0x00 0x83000000 0x00 0x0C000000>;
+ sifive,port-width-bytes = <0x20>;
+ phandle = <0x14>;
+ };
+
+ soc {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "SiFive,FU800-soc\0fu800-soc\0sifive-soc\0simple-bus";
+ ranges;
+
+ cache-controller@2010000 {
+ cache-block-size = <0x40>;
+ cache-level = <0x03>;
+ cache-sets = <0x1000>;
+ cache-size = <0x400000>;
+ cache-unified;
+ compatible = "sifive,ccache1\0cache\0sifive,fu740-c000-ccache";
+ // interrupt-parent = <0x10>;
+ // interrupts = <0x01 0x03 0x04 0x02>;
+ next-level-cache = <0x14>;
+ reg = <0x00 0x2010000 0x00 0x4000 0x00 0x8000000 0x00 0x400000>;
+ reg-names = "control\0sideband";
+ sifive,a-mshr-count = <0x3c>;
+ sifive,bank-count = <0x04>;
+ sifive,ecc-granularity = <0x08>;
+ sifive,max-master-id = <0x0d>;
+ sifive,perfmon-counters = <0x06>;
+ numa-node-id = <0x00>;
+ phandle = <0x15>;
+ };
+
+ interrupt-controller@c000000 {
+ #interrupt-cells = <0x01>;
+ compatible = "sifive,plic-1.0.0";
+ interrupt-controller;
+ interrupts-extended = <0x0d 0xffffffff 0x0d 0x09>;
+ reg = <0x00 0xc000000 0x00 0x4000000>;
+ reg-names = "control";
+ riscv,max-priority = <0x07>;
+ riscv,ndev = <0x208>;
+ phandle = <0x10>;
+ };
+
+ sys-crg@51828000 {
+ compatible = "eswin,win2030-sys-crg\0syscon\0simple-mfd";
+ reg = <0x00 0x51828000 0x00 0x80000>;
+ numa-node-id = <0x00>;
+ phandle = <0x16>;
+
+ reset-controller {
+ compatible = "eswin,win2030-reset";
+ #reset-cells = <0x02>;
+ status = "okay";
+ phandle = <0x18>;
+ };
+
+ clock-controller {
+ compatible = "eswin,win2030-clock";
+ #clock-cells = <0x01>;
+ status = "okay";
+ force-1_8ghz;
+ phandle = <0x03>;
+ };
+ };
+
+ hsp_sp_top_csr@0x50440000 {
+ compatible = "eswin,win2030-hsp-sp-csr\0syscon";
+ #size-cells = <0x02>;
+ reg = <0x00 0x50440000 0x00 0x2000>;
+ phandle = <0x1a>;
+ };
+
+ mmc@50450000 {
+ compatible = "eswin,emmc-sdhci-5.1";
+ reg = <0x00 0x50450000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x4f>;
+ assigned-clocks = <0x03 0x22a>;
+ assigned-clock-rates = <0xbebc200>;
+ clocks = <0x03 0x22a 0x03 0x222>;
+ clock-names = "clk_xin\0clk_ahb";
+ clock-output-names = "emmc_cardclock";
+ #clock-cells = <0x00>;
+ resets = <0x18 0x07 0x40 0x18 0x07 0x08 0x18 0x07 0x80000 0x18 0x07 0x800000>;
+ reset-names = "txrx_rst\0phy_rst\0prstn\0arstn";
+ core-clk-reg = <0x51828160>;
+ disable-cqe-dcmd;
+ bus-width = <0x08>;
+ non-removable;
+ mmc-hs400-1_8v;
+ max-frequency = <0xbebc200>;
+ #size-cells = <0x02>;
+ //iommus = <0x19 0x0f>;
+ //tbus = <0x02>;
+ //dma-ranges = <0x00 0x00 0x00 0xc0000000 0x01 0x00>;
+ eswin,hsp_sp_csr = <0x1a 0x1038 0x508 0x50c>;
+ eswin,syscrg_csr = <0x16 0x160 0x148 0x14c>;
+ status = "okay";
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ delay_code = <0x17>;
+ drive-impedance-ohm = <0x32>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ //pinctrl-names = "default";
+ //pinctrl-0 = <0x2b>;
+ no-sdio;
+ no-sd;
+ };
+
+ virtio_mmio@10007000 {
+ interrupts = <0x07>;
+ interrupt-parent = <0x10>;
+ reg = <0x00 0x10007000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+ };
+
+ aliases {
+ virtio-console = "/soc/virtio_mmio@10007000";
+ };
+
+ chosen {
+ bootargs = "earlycon console=hvc0 root=/dev/mmcblk0p3 rootfstype=ext4 rw rootwait init=/bin/bash";
+ stdout-path = "virtio-console";
+ };
+};
diff --git a/platform/riscv64/hifive-premier-p550/linker.ld b/platform/riscv64/hifive-premier-p550/linker.ld
new file mode 100644
index 00000000..eb62b0fe
--- /dev/null
+++ b/platform/riscv64/hifive-premier-p550/linker.ld
@@ -0,0 +1,50 @@
+ENTRY(arch_entry)
+BASE_ADDRESS = 0x80200000;
+
+
+SECTIONS
+{
+ . = BASE_ADDRESS;
+ skernel = .;
+
+ stext = .;
+ .text : {
+ *(.text.entry)
+ *(.text .text.*)
+ }
+
+ . = ALIGN(4K);
+ etext = .;
+ srodata = .;
+ .rodata : {
+ *(.rodata .rodata.*)
+ *(.srodata .srodata.*)
+ }
+
+ . = ALIGN(4K);
+ erodata = .;
+ sdata = .;
+ .data : {
+ *(.data .data.*)
+ *(.sdata .sdata.*)
+ }
+
+ . = ALIGN(4K);
+ edata = .;
+ .bss : {
+ *(.bss.stack)
+ sbss = .;
+ *(.bss .bss.*)
+ *(.sbss .sbss.*)
+ }
+
+ . = ALIGN(4K);
+ ebss = .;
+ ekernel = .;
+
+ /DISCARD/ : {
+ *(.eh_frame)
+ }
+ . = ALIGN(4K);
+ __core_end = .;
+}
\ No newline at end of file
diff --git a/platform/riscv64/hifive-premier-p550/native.txt b/platform/riscv64/hifive-premier-p550/native.txt
new file mode 100644
index 00000000..ee2ef41c
--- /dev/null
+++ b/platform/riscv64/hifive-premier-p550/native.txt
@@ -0,0 +1,7 @@
+setenv serverip 192.168.137.10;
+setenv ipaddr 192.168.137.11;
+setenv netmask 255.255.255.0;
+
+tftpboot 0x8f000000 192.168.137.10:native.dtb;
+tftpboot 0x90000000 192.168.137.10:uImage;
+bootm 0x90000000 - 0x8f000000;
\ No newline at end of file
diff --git a/platform/riscv64/hifive-premier-p550/platform.mk b/platform/riscv64/hifive-premier-p550/platform.mk
new file mode 100644
index 00000000..9e9ff31c
--- /dev/null
+++ b/platform/riscv64/hifive-premier-p550/platform.mk
@@ -0,0 +1,18 @@
+
+# HVISOR ENTRY
+HVISOR_ENTRY_PA := 0x80200000
+
+# Make hvisor.bin for hifive-premier-p550
+$(hvisor_bin): elf
+ @if ! command -v mkimage > /dev/null; then \
+ sudo apt update && sudo apt install u-boot-tools; \
+ fi && \
+ $(OBJCOPY) $(hvisor_elf) --strip-all -O binary $(hvisor_bin).tmp && \
+ mkimage -n hvisor_img -A riscv -O linux -C none -T kernel -a $(HVISOR_ENTRY_PA) \
+ -e $(HVISOR_ENTRY_PA) -d $(hvisor_bin).tmp $(hvisor_bin) && \
+ rm -rf $(hvisor_bin).tmp
+
+# Copy hvisor.bin & zone0.dtb to tftp dir, used for u-boot booting.
+wsl-cp: dtb all
+ cp $(hvisor_bin) /mnt/d/tftp/$(BOARD)/
+ cp platform/$(ARCH)/$(BOARD)/image/dts/zone0.dtb /mnt/d/tftp/$(BOARD)/
\ No newline at end of file
diff --git a/platform/riscv64/hifive-premier-p550/scripts/README.md b/platform/riscv64/hifive-premier-p550/scripts/README.md
new file mode 100644
index 00000000..8a129c43
--- /dev/null
+++ b/platform/riscv64/hifive-premier-p550/scripts/README.md
@@ -0,0 +1,28 @@
+
+Note: `boot_zone1.sh` is an example usage with `hvisor-tool`
+
+`boot_zone1.sh` will start virtio backend and boot zone1, please don't create backend repeatedly.
+
+If you want to reattch the same one virtio-console, please use `screen -r`.
+
+One example is below:
+
+```bash
+# boot zone1, in this script insmod hvisor.ko
+./boot_zone1.sh
+
+# list all zones
+./hvisor zone list
+
+# attach zone1's virtio-console, then use ctrl+a+d to return to zone0's terminal
+screen -S zone1 /dev/pts/0
+
+# shutdown zone1
+./hvisor zone shutdown -id 1
+
+# restart zone1
+./hvisor zone start zone1-linux.json
+
+# reattach to virtio-console
+screen -r zone1
+```
\ No newline at end of file
diff --git a/platform/riscv64/hifive-premier-p550/scripts/boot_zone1.sh b/platform/riscv64/hifive-premier-p550/scripts/boot_zone1.sh
new file mode 100644
index 00000000..08759372
--- /dev/null
+++ b/platform/riscv64/hifive-premier-p550/scripts/boot_zone1.sh
@@ -0,0 +1,10 @@
+insmod hvisor.ko
+mount -t proc proc /proc
+mount -t sysfs sysfs /sys
+rm nohup.out
+mkdir -p /dev/pts
+mount -t devpts devpts /dev/pts
+nohup ./hvisor virtio start zone1-linux-virtio.json &
+./hvisor zone start zone1-linux.json && \
+cat nohup.out | grep "char device" && \
+script /dev/null
\ No newline at end of file
diff --git a/platform/riscv64/megrez/board.rs b/platform/riscv64/megrez/board.rs
new file mode 100644
index 00000000..bfe9abe6
--- /dev/null
+++ b/platform/riscv64/megrez/board.rs
@@ -0,0 +1,212 @@
+// Copyright (c) 2025 Syswonder
+// hvisor is licensed under Mulan PSL v2.
+// You can use this software according to the terms and conditions of the Mulan PSL v2.
+// You may obtain a copy of Mulan PSL v2 at:
+// http://license.coscl.org.cn/MulanPSL2
+// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+// FIT FOR A PARTICULAR PURPOSE.
+// See the Mulan PSL v2 for more details.
+//
+// Syswonder Website:
+// https://www.syswonder.org
+//
+// Authors:
+//
+use crate::{arch::zone::HvArchZoneConfig, config::*};
+
+#[allow(unused)]
+pub const BOARD_NAME: &str = "milkv-megrez";
+
+pub const BOARD_NCPUS: usize = 4;
+pub const PLIC_BASE: usize = 0xc000000;
+pub const BOARD_PLIC_INTERRUPTS_NUM: usize = 1023; // except irq 0
+pub const SIFIVE_CCACHE_BASE: usize = 0x2010000; // SiFive composable cache controller
+pub const SIFIVE_CCACHE_SIZE: usize = 0x4000; // 16KB
+
+pub const ROOT_ZONE_DTB_ADDR: u64 = 0x8f000000;
+pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x90000000;
+pub const ROOT_ZONE_ENTRY: u64 = 0x90000000;
+pub const ROOT_ZONE_CPUS: u64 = (1 << 0);
+
+pub const ROOT_ZONE_NAME: &str = "root-linux";
+
+pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 10] = [
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_RAM,
+ physical_start: 0x80000000,
+ virtual_start: 0x80000000,
+ size: 0x8000_0000,
+ }, // ram
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x50900000,
+ virtual_start: 0x50900000,
+ size: 0x10000,
+ }, // serial0
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x50920000,
+ // virtual_start: 0x50920000,
+ // size: 0x10000,
+ // }, // serial2
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x50460000,
+ virtual_start: 0x50460000,
+ size: 0x10000,
+ }, // mmc
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x50440000,
+ virtual_start: 0x50440000,
+ size: 0x2000,
+ }, // hsp_sp_top_csr
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x51828000,
+ virtual_start: 0x51828000,
+ size: 0x80000,
+ }, // sys-crg (clock-controller, reset-controller) (SD card needs)
+ // Cache controller is needed, otherwise terminal will report "VFS: cannot open root device..."
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x2010000,
+ virtual_start: 0x2010000,
+ size: 0x4000,
+ }, // L3 cache-controller
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x1a000000,
+ virtual_start: 0x1a000000,
+ size: 0x400000,
+ }, // cache-controller -> zero-device@1a000000
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x8000000,
+ // virtual_start: 0x8000000,
+ // size: 0x400000,
+ // }, // L3 Loosely-Integrated Memory (L3 LIM)
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0xc0_0000_0000,
+ virtual_start: 0xc0_0000_0000,
+ // mem-port -> sys-port (here easily equal to mem size)
+ size: 0x4_0000_0000,
+ }, // Sys-port. (here related to DMA)
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x104000,
+ // virtual_start: 0x104000,
+ // size: 0x4000,
+ // }, // pL2Cache. (cpu0)
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x108000,
+ // virtual_start: 0x108000,
+ // size: 0x4000,
+ // }, // pL2Cache. (cpu1)
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x50420000,
+ // virtual_start: 0x50420000,
+ // size: 0x10000,
+ // }, // sata
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x50400000,
+ virtual_start: 0x50400000,
+ size: 0x10000,
+ }, // ethernet@50400000
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x50410000,
+ // virtual_start: 0x50410000,
+ // size: 0x10000,
+ // }, // ethernet@50410000
+ HvConfigMemoryRegion {
+ mem_type: MEM_TYPE_IO,
+ physical_start: 0x51600000,
+ virtual_start: 0x51600000,
+ size: 0x200000,
+ }, // gpio@51600000 pinctrl@0x51600080
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x51c00000,
+ // virtual_start: 0x51c00000,
+ // size: 0x400000,
+ // }, // eswin-npu@51c00000
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x50a40000,
+ // virtual_start: 0x50a40000,
+ // size: 0xc0000,
+ // }, // mbox
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x50960000,
+ // virtual_start: 0x50960000,
+ // size: 0x10000,
+ // }, // i2c@50960000
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x52280000,
+ // virtual_start: 0x52280000,
+ // size: 0x11000,
+ // }, // dsp_subsys@52280400
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x51810000,
+ // virtual_start: 0x51810000,
+ // size: 0x18000,
+ // }, // dsp_subsys@52280400 scu_sys_con@0x51810000
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x50c00000,
+ // virtual_start: 0x50c00000,
+ // size: 0x100000,
+ // }, // iommu@50c00000
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x5b100000,
+ // virtual_start: 0x5b100000,
+ // size: 0x200000,
+ // }, // dsp range
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x5a000000,
+ // virtual_start: 0x5a000000,
+ // size: 0x1000000,
+ // }, // npu need
+ // HvConfigMemoryRegion {
+ // mem_type: MEM_TYPE_IO,
+ // physical_start: 0x50450000,
+ // virtual_start: 0x50450000,
+ // size: 0x10000,
+ // }, // mmc@50450000
+];
+
+// Note: all here's irqs are hardware irqs,
+// only these irq can be transferred to the physical PLIC.
+pub const HW_IRQS: [u32; 8] = [
+ 0x51, // mmc@0x50460000
+ 0x64, // serial@0x50900000
+ 0x66, // serial@0x50920000
+ 0x3a, 0x3b, 0x3c, // sata@0x50420000
+ 0x3d, // ethernet@50400000
+ 0x46, // ethernet@50400000
+];
+
+// irqs belong to the root zone.
+pub const ROOT_ZONE_IRQS: [u32; 3] = [
+ 0x51, // mmc@0x50460000
+ 0x64, // serial@0x50900000
+ 0x3d, // ethernet@50400000
+];
+
+pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig {
+ plic_base: 0xc000000,
+ plic_size: 0x4000000,
+ aplic_base: 0xd000000,
+ aplic_size: 0x8000,
+};
diff --git a/platform/riscv64/megrez/boot.scr b/platform/riscv64/megrez/boot.scr
new file mode 100644
index 00000000..57d66ee7
Binary files /dev/null and b/platform/riscv64/megrez/boot.scr differ
diff --git a/platform/riscv64/megrez/boot.txt b/platform/riscv64/megrez/boot.txt
new file mode 100644
index 00000000..761abdc5
--- /dev/null
+++ b/platform/riscv64/megrez/boot.txt
@@ -0,0 +1,10 @@
+setenv serverip 192.168.1.150;
+setenv ipaddr 192.168.1.200;
+setenv netmask 255.255.255.0;
+setenv hvisor_addr 0x80200000;
+setenv zone0_fdt_addr 0x8f000000;
+setenv zone0_kernel_addr 0x90000000;
+tftpboot ${hvisor_addr} ${serverip}:hvisor.bin;
+tftpboot ${zone0_fdt_addr} ${serverip}:zone0.dtb;
+tftpboot ${zone0_kernel_addr} ${serverip}:Image;
+bootm ${hvisor_addr} - ${fdt_addr};
diff --git a/platform/riscv64/megrez/cargo/config.template.toml b/platform/riscv64/megrez/cargo/config.template.toml
new file mode 100644
index 00000000..f5d5b55c
--- /dev/null
+++ b/platform/riscv64/megrez/cargo/config.template.toml
@@ -0,0 +1,6 @@
+[target.riscv64gc-unknown-none-elf]
+runner = "platform/__ARCH__/__BOARD__/test/runner.sh"
+rustflags = [
+ "-Clink-arg=-Tplatform/__ARCH__/__BOARD__/linker.ld",
+ "-Cforce-frame-pointers=yes",
+]
\ No newline at end of file
diff --git a/platform/riscv64/megrez/cargo/features b/platform/riscv64/megrez/cargo/features
new file mode 100644
index 00000000..d1314d86
--- /dev/null
+++ b/platform/riscv64/megrez/cargo/features
@@ -0,0 +1,2 @@
+eic770x_soc
+plic
diff --git a/platform/riscv64/megrez/configs/zone1-linux-virtio.json b/platform/riscv64/megrez/configs/zone1-linux-virtio.json
new file mode 100644
index 00000000..1310b332
--- /dev/null
+++ b/platform/riscv64/megrez/configs/zone1-linux-virtio.json
@@ -0,0 +1,31 @@
+{
+ "zones": [
+ {
+ "id": 1,
+ "memory_region": [
+ {
+ "zone0_ipa": "0x83000000",
+ "zonex_ipa": "0x83000000",
+ "size": "0x0C000000"
+ }
+ ],
+ "devices": [
+ {
+ "type": "blk",
+ "addr": "0x10006000",
+ "len": "0x1000",
+ "irq": 6,
+ "img": "riscv_rootfs2.img",
+ "status": "enable"
+ },
+ {
+ "type": "console",
+ "addr": "0x10007000",
+ "len": "0x1000",
+ "irq": 7,
+ "status": "enable"
+ }
+ ]
+ }
+ ]
+}
\ No newline at end of file
diff --git a/platform/riscv64/megrez/configs/zone1-linux.json b/platform/riscv64/megrez/configs/zone1-linux.json
new file mode 100644
index 00000000..bf957af8
--- /dev/null
+++ b/platform/riscv64/megrez/configs/zone1-linux.json
@@ -0,0 +1,75 @@
+{
+ "arch": "riscv",
+ "name": "linux2",
+ "zone_id": 1,
+ "cpus": [1],
+ "memory_regions": [
+ {
+ "type": "ram",
+ "physical_start": "0x83000000",
+ "virtual_start": "0x83000000",
+ "size": "0x0C000000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x50920000",
+ "virtual_start": "0x50920000",
+ "size": "0x10000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x50420000",
+ "virtual_start": "0x50420000",
+ "size": "0x10000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x50440000",
+ "virtual_start": "0x50440000",
+ "size": "0x2000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x2010000",
+ "virtual_start": "0x2010000",
+ "size": "0x4000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x51828000",
+ "virtual_start": "0x51828000",
+ "size": "0x80000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0xc000000000",
+ "virtual_start": "0xc000000000",
+ "size": "0x80000000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x50410000",
+ "virtual_start": "0x50410000",
+ "size": "0x10000"
+ },
+ {
+ "type": "io",
+ "physical_start": "0x51600000",
+ "virtual_start": "0x51600000",
+ "size": "0x200000"
+ }
+ ],
+ "interrupts": [58, 59, 60, 102, 70],
+ "ivc_configs": [],
+ "kernel_filepath": "./Image",
+ "dtb_filepath": "./zone1-linux.dtb",
+ "kernel_load_paddr": "0x84000000",
+ "dtb_load_paddr": "0x83000000",
+ "entry_point": "0x84000000",
+ "arch_config": {
+ "plic_base": "0xc000000",
+ "plic_size": "0x4000000",
+ "aplic_base": "0xd000000",
+ "aplic_size": "0x8000"
+ }
+}
\ No newline at end of file
diff --git a/platform/riscv64/megrez/image/dts/Makefile b/platform/riscv64/megrez/image/dts/Makefile
new file mode 100644
index 00000000..2f795e7f
--- /dev/null
+++ b/platform/riscv64/megrez/image/dts/Makefile
@@ -0,0 +1,8 @@
+DTS_FILES := $(wildcard *.dts)
+DTB_FILES := $(DTS_FILES:.dts=.dtb)
+
+all: $(DTB_FILES)
+%.dtb: %.dts
+ dtc -I dts -O dtb $< -o $@
+clean:
+ rm -f $(DTB_FILES)
\ No newline at end of file
diff --git a/platform/riscv64/megrez/image/dts/eic7700-milkv-megrez.dts b/platform/riscv64/megrez/image/dts/eic7700-milkv-megrez.dts
new file mode 100644
index 00000000..5cada032
--- /dev/null
+++ b/platform/riscv64/megrez/image/dts/eic7700-milkv-megrez.dts
@@ -0,0 +1,5655 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "sifive,hifive-unmatched-a00\0sifive,fu740-c000\0sifive,fu740\0eswin,eic7700";
+ model = "Milk-V Megrez";
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ timebase-frequency = <0xf4240>;
+
+ idle-states {
+
+ cpu-retentive {
+ compatible = "riscv,idle-state";
+ riscv,sbi-suspend-param = <0x00>;
+ entry-latency-us = <0x14>;
+ exit-latency-us = <0x28>;
+ min-residency-us = <0x50>;
+ phandle = <0x05>;
+ };
+ };
+
+ cpu@0 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x01>;
+ reg = <0x00>;
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x02>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f4>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+ phandle = <0x4a>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0c>;
+ };
+ };
+
+ cpu@1 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x06>;
+ reg = <0x01>;
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x07>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f5>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+ phandle = <0x4b>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0d>;
+ };
+ };
+
+ cpu@2 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x08>;
+ reg = <0x02>;
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x09>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f6>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+ phandle = <0x4c>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0e>;
+ };
+ };
+
+ cpu@3 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x0a>;
+ reg = <0x03>;
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x0b>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f7>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+ phandle = <0x4d>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0f>;
+ };
+ };
+ };
+
+ memory@80000000 {
+ compatible = "sifive,axi4-mem-port\0sifive,axi4-port\0sifive,mem-port";
+ device_type = "memory";
+ reg = <0x00 0x80000000 0x04 0x00>;
+ sifive,port-width-bytes = <0x20>;
+ numa-node-id = <0x00>;
+ phandle = <0x14>;
+ };
+
+ soc {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "SiFive,FU800-soc\0fu800-soc\0sifive-soc\0simple-bus";
+ ranges;
+
+ pmu@0 {
+ riscv,raw-event-to-mhpmcounters = <0x00 0x00 0xffffffff 0xff 0x1f8 0x00 0x01 0xffffffff 0xfff800ff 0x1f8 0x00 0x02 0xffffffff 0xffffc0ff 0x1f8>;
+ riscv,event-to-mhpmcounters = <0x01 0x01 0x01 0x02 0x02 0x02 0x04 0x06 0x1f8 0x10009 0x10009 0x1f8 0x10019 0x10019 0x1f8 0x10021 0x10021 0x1f8>;
+ riscv,event-to-mhpmevent = <0x04 0x00 0x202 0x05 0x00 0x4000 0x06 0x00 0x2001 0x10009 0x00 0x102 0x10019 0x00 0x1002 0x10021 0x00 0x802>;
+ compatible = "riscv,pmu0\0riscv,pmu";
+ interrupts-extended = <0x0c 0x0d 0x0d 0x0d 0x0e 0x0d 0x0f 0x0d>;
+ };
+
+ authentication-controller {
+ compatible = "sifive,authentication0";
+ sifive,auth-types = "fuse";
+ };
+
+ axi4-sys-port@40000000 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "sifive,axi4-sys-port\0sifive,axi4-port\0sifive,sys-port\0simple-external-bus\0simple-bus";
+ ranges = <0x40000000 0x00 0x40000000 0x40000000>;
+ sifive,port-width-bytes = <0x10>;
+ };
+
+ axi4-sys-port@8000000000 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "sifive,axi4-sys-port\0sifive,axi4-port\0sifive,sys-port\0simple-external-bus\0simple-bus";
+ ranges = <0x80 0x00 0x80 0x00 0x180 0x00>;
+ sifive,port-width-bytes = <0x10>;
+ };
+
+ basic-bus-blocker@200000 {
+ compatible = "sifive,basic-bus-blocker1";
+ reg = <0x00 0x200000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ basic-bus-blocker@202000 {
+ compatible = "sifive,basic-bus-blocker1";
+ reg = <0x00 0x202000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ basic-bus-blocker@204000 {
+ compatible = "sifive,basic-bus-blocker1";
+ reg = <0x00 0x204000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ burst-bundler@10010000 {
+ compatible = "sifive,burst-bundler0";
+ reg = <0x00 0x10010000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ bus-error-unit@hart0 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <0x10>;
+ interrupts = <0x205>;
+ reg = <0x00 0x1700000 0x00 0x1000>;
+ reg-names = "control";
+ phandle = <0x02>;
+ };
+
+ bus-error-unit@hart1 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <0x10>;
+ interrupts = <0x206>;
+ reg = <0x00 0x1701000 0x00 0x1000>;
+ reg-names = "control";
+ phandle = <0x07>;
+ };
+
+ bus-error-unit@hart2 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <0x10>;
+ interrupts = <0x207>;
+ reg = <0x00 0x1702000 0x00 0x1000>;
+ reg-names = "control";
+ phandle = <0x09>;
+ };
+
+ bus-error-unit@hart3 {
+ compatible = "sifive,buserror";
+ interrupt-parent = <0x10>;
+ interrupts = <0x208>;
+ reg = <0x00 0x1703000 0x00 0x1000>;
+ reg-names = "control";
+ phandle = <0x0b>;
+ };
+
+ cache-controller@2010000 {
+ cache-block-size = <0x40>;
+ cache-level = <0x03>;
+ cache-sets = <0x1000>;
+ cache-size = <0x400000>;
+ cache-unified;
+ compatible = "sifive,ccache1\0cache\0sifive,fu740-c000-ccache";
+ interrupt-parent = <0x10>;
+ interrupts = <0x01 0x03 0x04 0x02>;
+ next-level-cache = <0x11 0x12 0x13 0x14>;
+ reg = <0x00 0x2010000 0x00 0x4000 0x00 0x8000000 0x00 0x400000>;
+ reg-names = "control\0sideband";
+ sifive,a-mshr-count = <0x3c>;
+ sifive,bank-count = <0x04>;
+ sifive,ecc-granularity = <0x08>;
+ sifive,max-master-id = <0x0d>;
+ sifive,perfmon-counters = <0x06>;
+ numa-node-id = <0x00>;
+ phandle = <0x15>;
+ };
+
+ debug-controller@0 {
+ compatible = "sifive,debug-100\0riscv,debug-100";
+ debug-attach = "jtag";
+ reg = <0x00 0x00 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ error-device@1000 {
+ compatible = "sifive,error0";
+ reg = <0x00 0x1000 0x00 0x3000 0x00 0x5000 0x00 0x13000 0x00 0x19000 0x00 0xe7000 0x00 0x114000 0x00 0xec000 0x00 0x201000 0x00 0x1000 0x00 0x203000 0x00 0x1000 0x00 0x205000 0x00 0x14fb000 0x00 0x1704000 0x00 0x8fc000 0x00 0x2014000 0x00 0x5fec000 0x00 0x8400000 0x00 0x3c00000 0x00 0x10000000 0x00 0x3000 0x00 0x10004000 0x00 0xc000 0x00 0x10011000 0x00 0x1f000 0x00 0x10034000 0x00 0x9fcc000 0x00 0x1a400000 0x00 0x5c00000>;
+ };
+
+ error-device@10003000 {
+ compatible = "sifive,error0";
+ reg = <0x00 0x10003000 0x00 0x1000>;
+ phandle = <0x11>;
+ };
+
+ interrupt-controller@c000000 {
+ #interrupt-cells = <0x01>;
+ compatible = "sifive,plic-1.0.0";
+ interrupt-controller;
+ interrupts-extended = <0x0c 0xffffffff 0x0c 0x09 0x0d 0xffffffff 0x0d 0x09 0x0e 0xffffffff 0x0e 0x09 0x0f 0xffffffff 0x0f 0x09>;
+ reg = <0x00 0xc000000 0x00 0x4000000>;
+ reg-names = "control";
+ riscv,max-priority = <0x07>;
+ riscv,ndev = <0x208>;
+ numa-node-id = <0x00>;
+ phandle = <0x10>;
+ };
+
+ order-obliterator@10030000 {
+ compatible = "sifive,order-obliterator0";
+ interrupt-parent = <0x10>;
+ interrupts = <0x204>;
+ reg = <0x00 0x10030000 0x00 0x4000>;
+ reg-names = "control";
+ };
+
+ pl2@104000 {
+ cache-block-size = <0x40>;
+ cache-level = <0x02>;
+ cache-sets = <0x200>;
+ cache-size = <0x40000>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0\0cache";
+ next-level-cache = <0x15>;
+ reg = <0x00 0x104000 0x00 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <0x10>;
+ sifive,perfmon-counters = <0x06>;
+ phandle = <0x01>;
+ };
+
+ pl2@108000 {
+ cache-block-size = <0x40>;
+ cache-level = <0x02>;
+ cache-sets = <0x200>;
+ cache-size = <0x40000>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0\0cache";
+ next-level-cache = <0x15>;
+ reg = <0x00 0x108000 0x00 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <0x10>;
+ sifive,perfmon-counters = <0x06>;
+ phandle = <0x06>;
+ };
+
+ pl2@10c000 {
+ cache-block-size = <0x40>;
+ cache-level = <0x02>;
+ cache-sets = <0x200>;
+ cache-size = <0x40000>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0\0cache";
+ next-level-cache = <0x15>;
+ reg = <0x00 0x10c000 0x00 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <0x10>;
+ sifive,perfmon-counters = <0x06>;
+ phandle = <0x08>;
+ };
+
+ pl2@110000 {
+ cache-block-size = <0x40>;
+ cache-level = <0x02>;
+ cache-sets = <0x200>;
+ cache-size = <0x40000>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0\0cache";
+ next-level-cache = <0x15>;
+ reg = <0x00 0x110000 0x00 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <0x10>;
+ sifive,perfmon-counters = <0x06>;
+ phandle = <0x0a>;
+ };
+
+ rom@1a000000 {
+ compatible = "ucbbar,cacheable-zero0";
+ reg = <0x00 0x1a000000 0x00 0x400000>;
+ phandle = <0x12>;
+ };
+
+ rom@3a000000 {
+ compatible = "ucbbar,cacheable-zero0";
+ reg = <0x00 0x3a000000 0x00 0x400000>;
+ phandle = <0x13>;
+ };
+
+ subsystem_pbus_clock {
+ #clock-cells = <0x00>;
+ clock-frequency = <0x989680>;
+ clock-output-names = "subsystem_pbus_clock";
+ compatible = "fixed-clock";
+ };
+
+ teststatus@4000 {
+ compatible = "sifive,test0";
+ reg = <0x00 0x4000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ tl-address-adjuster@20000000 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "sifive,tl-inter-sys-port\0sifive,tl-port\0simple-external-bus\0simple-bus";
+ ranges = <0x20000000 0x00 0x20000000 0x1a000000 0x3a400000 0x00 0x3a400000 0x5c00000>;
+ sifive,port-width-bytes = <0x08>;
+ };
+
+ tl-inter-mem-master-port@80000000 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "sifive,tl-inter-mem-master-port\0sifive,tl-port\0sifive,inter-mem-master-port\0simple-external-bus\0simple-bus";
+ ranges = <0x00 0x80000000 0x00 0x80000000 0x7f 0x80000000>;
+ sifive,port-width-bytes = <0x20>;
+ };
+
+ trace-encoder-0@100000 {
+ compatible = "sifive,trace0";
+ reg = <0x00 0x100000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ trace-encoder-1@101000 {
+ compatible = "sifive,trace0";
+ reg = <0x00 0x101000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ trace-encoder-2@102000 {
+ compatible = "sifive,trace0";
+ reg = <0x00 0x102000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ trace-encoder-3@103000 {
+ compatible = "sifive,trace0";
+ reg = <0x00 0x103000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ trace-funnel-0@18000 {
+ compatible = "sifive,trace0";
+ reg = <0x00 0x18000 0x00 0x1000>;
+ reg-names = "control";
+ };
+
+ serial@0x50900000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00 0x50900000 0x00 0x10000>;
+ clock-frequency = <0xbebc200>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x64>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ };
+
+ serial@0x50910000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00 0x50910000 0x00 0x10000>;
+ clock-frequency = <0xbebc200>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x65>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ };
+
+ serial@0x50920000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00 0x50920000 0x00 0x10000>;
+ clock-frequency = <0xbebc200>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x66>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ };
+
+ serial@0x50930000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00 0x50930000 0x00 0x10000>;
+ clock-frequency = <0xbebc200>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x67>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ numa-node-id = <0x00>;
+ status = "disabled";
+ };
+
+ serial@0x50940000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00 0x50940000 0x00 0x10000>;
+ clock-frequency = <0xbebc200>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x68>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ numa-node-id = <0x00>;
+ status = "disabled";
+ };
+
+ scu_sys_con@0x51810000 {
+ compatible = "eswin,win2030-scu-sys-con\0syscon\0simple-mfd";
+ #syscon-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x51810000 0x00 0x8000>;
+ numa-node-id = <0x00>;
+ phandle = <0x17>;
+
+ noc@51810324 {
+ compatible = "eswin,win2030-noc-wdt";
+ interrupt-parent = <0x10>;
+ interrupts = <0x188 0x189 0x18a 0x18b 0x18c 0x18d 0x18e 0x18f 0x190 0x191 0x192 0x193 0x194 0x195 0x196 0x197 0x198 0x199 0x19a 0x19b 0x19c 0x19d 0x19e 0x19f 0x1a0 0x1a1 0x1a2 0x1a3 0x1a4 0x1a5 0x1a6 0x1a7 0x1a8 0x1a9 0x1aa>;
+ eswin,syscrg_csr = <0x16 0x100 0xffff>;
+ status = "okay";
+ };
+ };
+
+ sys-crg@51828000 {
+ compatible = "eswin,win2030-sys-crg\0syscon\0simple-mfd";
+ reg = <0x00 0x51828000 0x00 0x80000>;
+ numa-node-id = <0x00>;
+ phandle = <0x16>;
+
+ reset-controller {
+ compatible = "eswin,win2030-reset";
+ #reset-cells = <0x02>;
+ status = "okay";
+ phandle = <0x18>;
+ };
+
+ clock-controller {
+ compatible = "eswin,win2030-clock";
+ #clock-cells = <0x01>;
+ status = "okay";
+ force-1_8ghz;
+ phandle = <0x03>;
+ };
+ };
+
+ hfclk {
+ #clock-cells = <0x00>;
+ compatible = "fixed-clock";
+ clock-frequency = <0xbebc200>;
+ clock-output-names = "hfclk";
+ };
+
+ hsp_sp_top_csr@0x50440000 {
+ compatible = "eswin,win2030-hsp-sp-csr\0syscon";
+ #size-cells = <0x02>;
+ reg = <0x00 0x50440000 0x00 0x2000>;
+ phandle = <0x1a>;
+ };
+
+ iommu@50c00000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x00 0x50c00000 0x00 0x100000>;
+ eswin,syscfg = <0x17 0x3fc>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x164 0x168 0x165 0x166>;
+ interrupt-names = "eventq\0gerror\0priq\0cmdq-sync";
+ #iommu-cells = <0x01>;
+ resets = <0x18 0x05 0x01 0x18 0x05 0x02 0x18 0x05 0x10 0x18 0x05 0x20 0x18 0x05 0x40 0x18 0x05 0x80 0x18 0x05 0x100 0x18 0x05 0x200 0x18 0x05 0x400 0x18 0x05 0x800>;
+ reset-names = "axi_rst\0cfg_rst\0tbu0_rst\0tbu1_rst\0tbu2_rst\0tbu3_rst\0tbu4_rst\0tbu5_rst\0tbu6_rst\0tbu7_rst";
+ status = "okay";
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ phandle = <0x19>;
+ };
+
+ pmu@50c02000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x00 0x50c02000 0x00 0x1000 0x00 0x50c22000 0x00 0x1000>;
+ eswin,syscfg = <0x17 0x3fc>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x16b>;
+ status = "disabled";
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ };
+
+ E21@0 {
+ compatible = "riscv,dev-foo-a";
+ #size-cells = <0x02>;
+ dma-ranges = <0x00 0x20000000 0x00 0xc0000000 0x00 0x40000000>;
+ iommus = <0x19 0x1c>;
+ tbus = <0xf00>;
+ status = "okay";
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ };
+
+ power-controller@51808000 {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ compatible = "eswin,win2030-pmu-controller";
+ #power-domain-cells = <0x01>;
+ reg = <0x00 0x51808000 0x00 0x8000>;
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ win2030-pmu-controller-port@0 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ id = <0x00>;
+ reg_base = <0x00>;
+ power_status = <0x02>;
+ power_delay = <0x06 0x06 0x03 0x03>;
+ clock_delay = <0x04 0x02 0x02 0x02>;
+ reset_delay = <0x02 0x04 0x02 0x02>;
+ clamp_delay = <0x03 0x03 0x02 0x02>;
+ label = "D0_PCIE";
+ tbus = <0x03>;
+ };
+
+ win2030-pmu-controller-port@40 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ id = <0x01>;
+ reg_base = <0x40>;
+ power_status = <0x02>;
+ power_delay = <0x06 0x06 0x03 0x03>;
+ clock_delay = <0x04 0x02 0x02 0x02>;
+ reset_delay = <0x02 0x04 0x02 0x02>;
+ clamp_delay = <0x03 0x03 0x02 0x02>;
+ tbus = <0x71>;
+ label = "D0_DSP1";
+ };
+
+ win2030-pmu-controller-port@80 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ id = <0x02>;
+ reg_base = <0x80>;
+ power_status = <0x02>;
+ power_delay = <0x06 0x06 0x03 0x03>;
+ clock_delay = <0x04 0x02 0x02 0x02>;
+ reset_delay = <0x02 0x04 0x02 0x02>;
+ clamp_delay = <0x03 0x03 0x02 0x02>;
+ tbus = <0x00 0x00>;
+ label = "D0_VI";
+ };
+
+ win2030-pmu-controller-port@c0 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ id = <0x03>;
+ reg_base = <0xc0>;
+ power_status = <0x02>;
+ power_delay = <0x06 0x06 0x03 0x03>;
+ clock_delay = <0x04 0x02 0x02 0x02>;
+ reset_delay = <0x02 0x04 0x02 0x02>;
+ clamp_delay = <0x03 0x03 0x02 0x02>;
+ label = "D0_VO";
+ };
+
+ win2030-pmu-controller-port@140 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ id = <0x04>;
+ reg_base = <0x140>;
+ power_status = <0x02>;
+ power_delay = <0x06 0x06 0x03 0x03>;
+ clock_delay = <0x04 0x02 0x02 0x02>;
+ reset_delay = <0x02 0x04 0x02 0x02>;
+ clamp_delay = <0x03 0x03 0x02 0x02>;
+ tbus = <0x10 0x13 0x11 0x12>;
+ label = "D0_CODEC";
+ };
+
+ win2030-pmu-controller-port@200 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ id = <0x05>;
+ reg_base = <0x200>;
+ power_status = <0x02>;
+ power_delay = <0x06 0x06 0x03 0x03>;
+ clock_delay = <0x04 0x02 0x02 0x02>;
+ reset_delay = <0x02 0x04 0x02 0x02>;
+ clamp_delay = <0x03 0x03 0x02 0x02>;
+ tbus = <0x72>;
+ label = "D0_DSP2";
+ };
+
+ win2030-pmu-controller-port@240 {
+ compatible = "eswin,win2030-pmu-controller-port";
+ id = <0x06>;
+ reg_base = <0x240>;
+ power_status = <0x02>;
+ power_delay = <0x06 0x06 0x03 0x03>;
+ clock_delay = <0x04 0x02 0x02 0x02>;
+ reset_delay = <0x02 0x04 0x02 0x02>;
+ clamp_delay = <0x03 0x03 0x02 0x02>;
+ tbus = <0x73>;
+ label = "D0_DSP3";
+ };
+ };
+
+ dma-controller-hsp@0x50430000 {
+ compatible = "eswin,eic770x-axi-dma";
+ reg = <0x00 0x50430000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x39>;
+ #dma-cells = <0x02>;
+ clocks = <0x03 0x2b2 0x03 0x2b3>;
+ clock-names = "core-clk\0cfgr-clk";
+ resets = <0x18 0x07 0x4000 0x18 0x07 0x100000>;
+ reset-names = "arst\0prst";
+ dma-channels = <0x0c>;
+ snps,dma-masters = <0x01>;
+ snps,priority = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b>;
+ snps,data-width = <0x02>;
+ snps,block-size = <0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000>;
+ snps,axi-max-burst-len = <0x10>;
+ snps,max-msize = <0x40>;
+ iommus = <0x19 0x01>;
+ tbus = <0x02>;
+ eswin,hsp_sp_csr = <0x1a 0x104c>;
+ eswin,syscfg = <0x17 0x3004 0x370>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ };
+
+ dma-controller-aon@0x518c0000 {
+ compatible = "eswin,eic770x-axi-dma";
+ reg = <0x00 0x518c0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x121>;
+ #dma-cells = <0x02>;
+ clocks = <0x03 0x266 0x03 0x264>;
+ clock-names = "core-clk\0cfgr-clk";
+ resets = <0x18 0x27 0x01 0x18 0x27 0x02>;
+ reset-names = "arst\0prst";
+ dma-channels = <0x10>;
+ snps,dma-masters = <0x02>;
+ snps,priority = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f>;
+ snps,data-width = <0x03>;
+ snps,block-size = <0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000>;
+ snps,axi-max-burst-len = <0x20>;
+ #size-cells = <0x02>;
+ #address-cells = <0x02>;
+ dma-ranges = <0x00 0x80000000 0x00 0x80000000 0x100 0x00>;
+ iommus = <0x19 0x1a>;
+ tbus = <0x04>;
+ eswin,syscfg = <0x17 0x3004 0x370>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x31>;
+ };
+
+ ethernet@50400000 {
+ compatible = "eswin,win2030-qos-eth";
+ reg = <0x00 0x50400000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupt-names = "macirq";
+ interrupts = <0x3d>;
+ phy-mode = "rgmii";
+ numa-node-id = <0x00>;
+ id = <0x00>;
+ status = "okay";
+ clocks = <0x03 0x226 0x03 0x227 0x03 0x228>;
+ clock-names = "app\0stmmaceth\0tx";
+ resets = <0x18 0x07 0x4000000>;
+ reset-names = "ethrst";
+ tbus = <0x02>;
+ dma-noncoherent;
+ eswin,hsp_sp_csr = <0x1a 0x1030 0x100 0x108>;
+ eswin,syscrg_csr = <0x16 0x148 0x14c>;
+ snps,axi-config = <0x1b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x1c>;
+ rst-gpios = <0x1d 0x1e 0x01>;
+ eswin,rgmiisel = <0x1e 0x290 0x03>;
+ eswin,led-cfgs = <0x6100 0xa40 0x420>;
+
+ stmmac-axi-config {
+ snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
+ snps,rd_osr_lmt = <0x02>;
+ snps,wr_osr_lmt = <0x02>;
+ snps,lpi_en = <0x00>;
+ phandle = <0x1b>;
+ };
+ };
+
+ ethernet@50410000 {
+ compatible = "eswin,win2030-qos-eth";
+ reg = <0x00 0x50410000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupt-names = "macirq";
+ interrupts = <0x46>;
+ phy-mode = "rgmii";
+ numa-node-id = <0x00>;
+ id = <0x01>;
+ status = "okay";
+ clocks = <0x03 0x226 0x03 0x227 0x03 0x229>;
+ clock-names = "app\0stmmaceth\0tx";
+ resets = <0x18 0x07 0x2000000>;
+ reset-names = "ethrst";
+ tbus = <0x02>;
+ dma-noncoherent;
+ eswin,hsp_sp_csr = <0x1a 0x1034 0x200 0x208>;
+ eswin,syscrg_csr = <0x16 0x148 0x14c>;
+ snps,axi-config = <0x1f>;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x20>;
+ rst-gpios = <0x21 0x10 0x01>;
+ eswin,rgmiisel = <0x1e 0x294 0x03>;
+ eswin,led-cfgs = <0x6100 0xa40 0x420>;
+
+ stmmac-axi-config {
+ snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
+ snps,rd_osr_lmt = <0x02>;
+ snps,wr_osr_lmt = <0x02>;
+ snps,lpi_en = <0x00>;
+ phandle = <0x1f>;
+ };
+ };
+
+ noc {
+ compatible = "eswin,noc\0simple-bus";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ d0_cfg_noc {
+ compatible = "eswin,win2030-noc";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ reg = <0x00 0x52060000 0x00 0x4000>;
+ interrupts = <0x1be>;
+ interrupt-names = "error";
+ interrupt-parent = <0x10>;
+ errlogger,idx = <0x00 0x01 0x03 0x05>;
+ status = "okay";
+
+ sideband_manager@52061000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0x00 0x52061000 0x00 0x10>;
+ SenseIn0 = <0x1e 0x00 0x1f 0x01 0x20 0x02 0x21 0x03 0x22 0x04 0x23 0x05 0x24 0x06 0x25 0x07 0x26 0x08 0x27 0x09 0x28 0x0a 0x29 0x0b 0x2a 0x0c 0x2b 0x0d 0x2c 0x0e 0x2d 0x0f 0x2e 0x10 0x2f 0x11 0x30 0x12 0x31 0x13 0x32 0x14>;
+ bf-name = "SBM_CLMM\0SBM_CNOC_AON\0SBM_CNOC_DDRT0_CTRL\0SBM_CNOC_DDRT0_PHY \0SBM_CNOC_DDRT1_CTRL\0SBM_CNOC_DDRT1_PHY\0SBM_CNOC_DSPT\0SBM_CNOC_GPU\0SBM_CNOC_HSP\0SBM_CNOC_LSP_APB2\0SBM_CNOC_LSP_APB3\0SBM_CNOC_LSP_APB4\0SBM_CNOC_LSP_APB6\0SBM_CNOC_MCPUT_D2D\0SBM_CNOC_NPU\0SBM_CNOC_PCIET_P\0SBM_CNOC_PCIET_X\0SBM_CNOC_TCU\0SBM_CNOC_VC\0SBM_CNOC_VI\0SBM_CNOC_VO";
+ };
+
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x14 0x20>;
+ description = "Register 0 to log errors";
+
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x01>;
+ lut = "Not Locked\0Locked";
+ };
+
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x01 0x04>;
+ lut = "RD: data read with incrementing address\0RDW: data read with wrapping address\0RDL: allocates monitor in the Target with incrementing address\0RDX: exclusive read with incrementing address\0WR: data write with incrementing address\0WRW: data write with wrapping address\0WRC: conditional write if matching monitor in Target is found\0RSV: reserved\0PRE: preamble packet of linked sequence (locked sequence)\0URG: urgency packet used for QoS (status must be REQ)";
+ };
+
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x08 0x03>;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error\0DEC (error source: Initiator NIU): decode error\0UNS (error source: Target NIU): unsupported access type\0DISC (error source: Power Disconnect): disconnected Target or NoC domain\0SEC (error source: Initiator NIU or Firewall): security error\0HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator\0TMO (error source: Target NIU): time-out\0RSV: reserved";
+ };
+
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x10 0x0c>;
+ };
+
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x1f 0x01>;
+ lut = "NTTP v3.0 (Invalid)\0NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register\0eswin,win2030,noc,filter,routeid";
+ offset,length = <0x18 0x20>;
+ description = "Register 1 to log errors";
+
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x0f 0x01>;
+ lut = "snoc_cnoc/I/0";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x0a 0x05>;
+ lut = "clmm/T/0\0cnoc_aon/T/0\0cnoc_ddrt0_ctrl/T/0\0cnoc_ddrt0_phy/T/0\0cnoc_ddrt1_ctrl/T/0\0cnoc_ddrt1_phy/T/0\0cnoc_dspt/T/0\0cnoc_gpu/T/0\0cnoc_hsp/T/0\0cnoc_lsp_apb2/T/0\0cnoc_lsp_apb3/T/0\0cnoc_lsp_apb4/T/0\0cnoc_lsp_apb6/T/0\0cnoc_mcput_d2d/T/0\0cnoc_npu/T/0\0cnoc_pciet_p/T/0\0cnoc_pciet_x/T/0\0cnoc_service/T/0\0cnoc_tcu/T/0\0cnoc_vc/T/0\0cnoc_vi/T/0\0cnoc_vo/T/0\0RESERVED\0RESERVED\0RESERVED\0RESERVED\0RESERVED\0RESERVED\0RESERVED\0RESERVED\0RESERVED\0RESERVED";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x08 0x02>;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x08>;
+ };
+ };
+
+ ErrorLogger3 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 0x20>;
+ description = "Register 3 to log errors";
+ aperture-link = <0x01>;
+
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x08 0x08>;
+ aperture-size = <0x2e>;
+ aperture-idx,aperture-base = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x51600000 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x71600000 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x51800000 0x00 0x00 0x00 0x01 0x00 0x01 0x00 0x71800000 0x00 0x00 0x00 0x01 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x52300000 0x00 0x00 0x00 0x02 0x00 0x01 0x00 0x72300000 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x53000000 0x00 0x00 0x00 0x03 0x00 0x01 0x00 0x73000000 0x00 0x00 0x00 0x04 0x00 0x00 0x00 0x52380000 0x00 0x00 0x00 0x04 0x00 0x01 0x00 0x72380000 0x00 0x00 0x00 0x05 0x00 0x00 0x00 0x53800000 0x00 0x00 0x00 0x05 0x00 0x01 0x00 0x73800000 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x52200000 0x00 0x00 0x00 0x06 0x00 0x01 0x00 0x72200000 0x00 0x00 0x00 0x07 0x00 0x00 0x00 0x51400000 0x00 0x00 0x00 0x07 0x00 0x01 0x00 0x71400000 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0x50400000 0x00 0x00 0x00 0x08 0x00 0x01 0x00 0x70400000 0x00 0x00 0x00 0x09 0x00 0x00 0x00 0x50800000 0x00 0x00 0x00 0x09 0x00 0x01 0x00 0x70800000 0x00 0x00 0x00 0x0a 0x00 0x00 0x00 0x50900000 0x00 0x00 0x00 0x0a 0x00 0x01 0x00 0x70900000 0x00 0x00 0x00 0x0b 0x00 0x00 0x00 0x50a00000 0x00 0x00 0x00 0x0b 0x00 0x01 0x00 0x70a00000 0x00 0x00 0x00 0x0c 0x00 0x00 0x00 0x50b00000 0x00 0x00 0x00 0x0c 0x00 0x01 0x00 0x70b00000 0x00 0x00 0x00 0x0d 0x00 0x00 0x00 0x52100000 0x00 0x00 0x00 0x0d 0x00 0x01 0x00 0x72100000 0x00 0x00 0x00 0x0e 0x00 0x00 0x00 0x51c00000 0x00 0x00 0x00 0x0e 0x00 0x01 0x00 0x71c00000 0x00 0x00 0x00 0x0f 0x00 0x00 0x00 0x50000000 0x00 0x00 0x00 0x0f 0x00 0x01 0x00 0x70000000 0x00 0x00 0x00 0x10 0x00 0x00 0x00 0x54000000 0x00 0x00 0x00 0x10 0x00 0x01 0x00 0x74000000 0x00 0x00 0x00 0x11 0x00 0x00 0x00 0x52060000 0x00 0x00 0x00 0x11 0x00 0x01 0x00 0x72060000 0x00 0x00 0x00 0x12 0x00 0x00 0x00 0x50c00000 0x00 0x00 0x00 0x12 0x00 0x01 0x00 0x70c00000 0x00 0x00 0x00 0x13 0x00 0x00 0x00 0x50100000 0x00 0x00 0x00 0x13 0x00 0x01 0x00 0x70100000 0x00 0x00 0x00 0x14 0x00 0x00 0x00 0x51000000 0x00 0x00 0x00 0x14 0x00 0x01 0x00 0x71000000 0x00 0x00 0x00 0x15 0x00 0x00 0x00 0x50200000 0x00 0x00 0x00 0x15 0x00 0x01 0x00 0x70200000>;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x28 0x20>;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x07>;
+ lut = "Cache_0\0Cache_1\0Cache_2\0Cache_3\0Prot_0\0Prot_1\0Prot_2";
+ };
+ };
+ };
+
+ d0_llc_noc@52081400 {
+ compatible = "eswin,win2030-noc";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ reg = <0x00 0x52081400 0x00 0x4000>;
+ interrupts = <0x1b9>;
+ interrupt-names = "error";
+ interrupt-parent = <0x10>;
+ errlogger,idx = <0x00 0x01 0x03 0x04 0x05>;
+ status = "okay";
+ stat,0 = "TracePort:ddr0_p0_req";
+ stat,1 = "TracePort:ddr1_p0_req";
+
+ sideband_manager@52082000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0x00 0x52082000 0x00 0x10>;
+ SenseIn0 = <0x3c 0x00 0x3d 0x01 0x3e 0x02 0x3f 0x03>;
+ bf-name = "SBM_LNOC_NPU_LLC0\0SBM_LNOC_NPU_LLC1\0SBM_LNOC_DDRT0_P0\0SBM_LNOC_DDRT1_P0";
+ };
+
+ llcnoc_packet_ddr0_p0_req_probe@52080000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52080000 0x00 0x4000>;
+ clocks = <0x03 0x217>;
+ clock-names = "clk";
+ interrupts = <0x1bd>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr0_p0_req";
+ };
+
+ llcnoc_packet_ddr1_p0_req_probe@52080800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52080800 0x00 0x4000>;
+ clocks = <0x03 0x21c>;
+ clock-names = "clk";
+ interrupts = <0x1bb>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr1_p0_req";
+ };
+
+ llcnoc_trans_probe@52081000 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0x00 0x52081000 0x00 0x4000>;
+ clocks = <0x03 0x203>;
+ clock-names = "clk";
+ interrupts = <0x1b9>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x02>;
+ counter,nr = <0x08>;
+ profiler,nr = <0x01>;
+ portsel = "npu_llc0\0npu_llc1";
+
+ llcnoc_trans_npu_llc0_filter@52081480 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52081480 0x00 0x80>;
+ };
+
+ llcnoc_trans_npu_llc1_filter@52081500 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52081500 0x00 0x80>;
+ };
+
+ llcnoc_trans_profiler@52081580 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0x00 0x52081580 0x00 0x80>;
+ };
+ };
+
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x14 0x20>;
+ description = "Register 0 to log errors";
+
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x01>;
+ lut = "Not Locked\0Locked";
+ };
+
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x01 0x04>;
+ lut = "RD: data read with incrementing address\0RDW: data read with wrapping address\0RDL: allocates monitor in the Target with incrementing address\0RDX: exclusive read with incrementing address\0WR: data write with incrementing address\0WRW: data write with wrapping address\0WRC: conditional write if matching monitor in Target is found\0RSV: reserved\0PRE: preamble packet of linked sequence (locked sequence)\0URG: urgency packet used for QoS (status must be REQ)";
+ };
+
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x08 0x03>;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error\0DEC (error source: Initiator NIU): decode error\0UNS (error source: Target NIU): unsupported access type\0DISC (error source: Power Disconnect): disconnected Target or NoC domain\0SEC (error source: Initiator NIU or Firewall): security error\0HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator\0TMO (error source: Target NIU): time-out\0RSV: reserved";
+ };
+
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x10 0x0c>;
+ };
+
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x1f 0x01>;
+ lut = "NTTP v3.0 (Invalid)\0NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register\0eswin,win2030,noc,filter,routeid";
+ offset,length = <0x18 0x20>;
+ description = "Register 1 to log errors";
+
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x0e 0x02>;
+ lut = "npu_lnoc_llc0/I/0\0npu_lnoc_llc1/I/0\0snoc_lnoc/I/0\0RESERVED";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x0c 0x02>;
+ lut = "lnoc_ddrt0_p0/T/0\0lnoc_ddrt1_p0/T/0\0lnoc_service/T/0\0RESERVED";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x08 0x04>;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x08>;
+ };
+ };
+
+ ErrorLogger3 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 0x20>;
+ description = "Register 3 to log errors";
+ aperture-link = <0x01>;
+ msb-link = <0x04>;
+
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x08 0x08>;
+ aperture-size = <0x35>;
+ aperture-idx,aperture-base = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x00 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x00 0x00 0x00 0x00 0x06 0xc0 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0xe0 0x00 0x00 0x00 0x00 0x00 0x00 0x08 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x09 0x40 0x100 0x00 0x00 0x00 0x00 0x00 0x0a 0x100 0x00 0x00 0x00 0x00 0x00 0x00 0x0b 0x100 0x100 0x00 0x00 0x00 0x00 0x00 0x0c 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x00 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x00 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x00 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x00 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x00 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x00 0x00 0x01 0x00 0x06 0xc0 0x80 0x00 0x00 0x00 0x01 0x00 0x07 0xe0 0x80 0x00 0x00 0x00 0x01 0x00 0x08 0x40 0x80 0x00 0x00 0x00 0x01 0x00 0x09 0x40 0x180 0x00 0x00 0x00 0x01 0x00 0x0a 0x100 0x80 0x00 0x00 0x00 0x01 0x00 0x0b 0x100 0x180 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x01 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x01 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x01 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x01 0x00 0x00 0x00 0x06 0xc0 0x00 0x00 0x01 0x00 0x00 0x00 0x07 0xe0 0x00 0x00 0x01 0x00 0x00 0x00 0x08 0x40 0x00 0x00 0x01 0x00 0x00 0x00 0x09 0x40 0x100 0x00 0x01 0x00 0x00 0x00 0x0a 0x100 0x00 0x00 0x01 0x00 0x00 0x00 0x0b 0x100 0x100 0x00 0x01 0x00 0x00 0x00 0x0c 0x00 0x00 0x00 0x01 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x01 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x01 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x01 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x01 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x01 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x01 0x00 0x01 0x00 0x06 0xc0 0x80 0x00 0x01 0x00 0x01 0x00 0x07 0xe0 0x80 0x00 0x01 0x00 0x01 0x00 0x08 0x40 0x80 0x00 0x01 0x00 0x01 0x00 0x09 0x40 0x180 0x00 0x01 0x00 0x01 0x00 0x0a 0x100 0x80 0x00 0x01 0x00 0x01 0x00 0x0b 0x100 0x180 0x00 0x02 0x00 0x02 0x00 0x00 0x00 0x52080000 0x00 0x02 0x00 0x02 0x00 0x01 0x00 0x72080000 0x00 0x02 0x00 0x02 0x00 0x02 0x00 0x00>;
+ };
+ };
+
+ ErrorLogger4 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x24 0x20>;
+ description = "Register 4 to log errors";
+
+ addr_msb {
+ compatible = "eswin,win2030,bitfield";
+ description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+ offset,length = <0x00 0x09>;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x28 0x20>;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x10>;
+ lut = "Cache_0\0Cache_1\0Cache_2\0Cache_3\0Prot_0\0Prot_1\0Prot_2\0Qos_0\0Qos_1\0Qos_2\0Qos_3\0User_0\0User_1\0User_2\0User_3\0User_4";
+ };
+ };
+ };
+
+ d0_sys_noc@52002C00 {
+ compatible = "eswin,win2030-noc";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ reg = <0x00 0x52002c00 0x00 0x4000>;
+ interrupts = <0x1af>;
+ interrupt-names = "error";
+ interrupt-parent = <0x10>;
+ errlogger,idx = <0x00 0x01 0x03 0x04 0x05>;
+ eswin,qos-configs = "DSPT\0NPU\0SPISLV_TBU3";
+ eswin,DSPT-qos-base = <0x52002c80>;
+ eswin,DSPT-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x03 0x14 0x01 0x18 0x01>;
+ eswin,NPU-qos-base = "R\0-";
+ eswin,NPU-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x18 0x14 0x10 0x18 0x01>;
+ eswin,SPISLV_TBU3-qos-base = <0x52002d80>;
+ eswin,SPISLV_TBU3-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x18 0x14 0x10 0x18 0x01>;
+ status = "okay";
+ stat,0 = "TracePort:ddr0_p1_req\0InitFlow:mcput_snoc_mp/I/0";
+ stat,1 = "TracePort:ddr0_p2_req\0InitFlow:dspt_snoc/I/0\0AddrBase:0x81000000\0AddrSize:0x30\0Opcode:RdWrLockUrg\0Status:ReqRsp\0Length:0x8000\0Urgency:0x0";
+ stat,2 = "TracePort:ddr1_p1_req\0Status:Req\0AddrSize:0x28";
+ stat,3 = "TracePort:ddr1_p2_req";
+ latency,0 = "TracePort:sysnoc_trans_probe_0\0AddrSize:0x0";
+ latency,1 = "TracePort:sysnoc_trans_probe_1\0Mode:latency\0AddrBase:0x82000000\0AddrSize:0x28\0Opcode:RdWr";
+ pending,0 = "TracePort:sysnoc_trans_probe_2\0AddrSize:0x3";
+
+ sideband_manager@52004000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0x00 0x52004000 0x00 0x10>;
+ SenseIn0 = <0x00 0x00 0x01 0x01 0x02 0x02 0x03 0x03 0x04 0x04 0x05 0x05 0x06 0x06 0x07 0x07 0x08 0x08 0x09 0x09 0x0a 0x0a 0x0b 0x0b 0x0c 0x0c 0x0d 0x0d 0x0e 0x0e 0x0f 0x0f 0x10 0x10 0x11 0x11 0x12 0x12 0x13 0x13 0x14 0x14 0x15 0x15>;
+ bf-name = "SBM_AON_SNOC_SP0\0SBM_DSPT_SNOC\0SBM_JTAG_SNOC\0SBM_MCPUT_SNOC_D2D \0SBM_MCPUT_SNOC_MP\0SBM_MCPUT_SNOC_SP0\0SBM_MCPUT_SNOC_SP1\0SBM_NPU_SNOC_SP0\0SBM_NPU_SNOC_SP1\0SBM_PCIET_SNOC_P\0SBM_SPISLV_PCIET_SNOC\0SBM_TBU4_SNOC\0SBM_TCU_SNOC\0SBM_SNOC_AON\0SBM_SNOC_DDR0_P1\0SBM_SNOC_DDR0_P2\0SBM_SNOC_DDR1_P1\0SBM_SNOC_DDR1_P2\0SBM_SNOC_DSPT\0SBM_SNOC_MCPUT_D2D\0SBM_SNOC_NPU\0SBM_SNOC_PCIET";
+ };
+
+ sysnoc_packet_ddr0_p1_req_probe@52000000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52000000 0x00 0x4000>;
+ clocks = <0x03 0x218>;
+ clock-names = "clk";
+ interrupts = <0x1b7>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr0_p1_req";
+ };
+
+ sysnoc_packet_ddr0_p2_req_probe@52000800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52000800 0x00 0x4000>;
+ clocks = <0x03 0x219>;
+ clock-names = "clk";
+ interrupts = <0x1b5>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr0_p2_req";
+ };
+
+ sysnoc_packet_ddr1_p1_req_probe@52001000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52001000 0x00 0x4000>;
+ clocks = <0x03 0x21d>;
+ clock-names = "clk";
+ interrupts = <0x1b3>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr1_p1_req";
+ };
+
+ sysnoc_packet_ddr1_p2_req_probe@52001800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52001800 0x00 0x4000>;
+ clocks = <0x03 0x21e>;
+ clock-names = "clk";
+ interrupts = <0x1b1>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr1_p2_req";
+ };
+
+ sysnoc_trans_probe_0@52002000 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0x00 0x52002000 0x00 0x4000>;
+ clocks = <0x03 0x203>;
+ clock-names = "clk";
+ interrupts = <0x1ae>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x02>;
+ counter,nr = <0x08>;
+ profiler,nr = <0x01>;
+ portsel = "dspt_snoc\0npu_sp1";
+
+ sysnoc_trans_dspt_filter@52002E00 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52002e00 0x00 0x80>;
+ };
+
+ sysnoc_trans_npu_sp1_filter@52002F80 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52002f80 0x00 0x80>;
+ };
+
+ sysnoc_trans_profiler@52003180 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0x00 0x52003180 0x00 0x80>;
+ };
+ };
+
+ sysnoc_trans_probe_1@52002400 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0x00 0x52002400 0x00 0x4000>;
+ clocks = <0x03 0x203>;
+ clock-names = "clk";
+ interrupts = <0x1ad>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x03>;
+ counter,nr = <0x0c>;
+ profiler,nr = <0x01>;
+ portsel = "mcput_mp\0mcput_sp1\0tcu";
+
+ sysnoc_trans_mcput_mp_filter@52002E80 {
+ status = "okay";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52002e80 0x00 0x80>;
+ };
+
+ sysnoc_trans_mcput_sp1_filter@52002F00 {
+ status = "okay";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52002f00 0x00 0x80>;
+ };
+
+ sysnoc_trans_tcu_filter@52003100 {
+ status = "okay";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52003100 0x00 0x80>;
+ };
+
+ sysnoc_trans_profiler@52003200 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0x00 0x52003200 0x00 0x80>;
+ };
+ };
+
+ sysnoc_trans_probe_2@52002800 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0x00 0x52002800 0x00 0x4000>;
+ clocks = <0x03 0x203>;
+ clock-names = "clk";
+ interrupts = <0x1ac>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x02>;
+ counter,nr = <0x08>;
+ profiler,nr = <0x01>;
+ portsel = "spislv_tbu3\0tbu4_snoc";
+
+ sysnoc_trans_spislv_tbu3_filter@52003000 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52003000 0x00 0x80>;
+ };
+
+ sysnoc_trans_tbu4_filter@52003080 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52003080 0x00 0x80>;
+ };
+
+ sysnoc_trans_profiler@52003280 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0x00 0x52003280 0x00 0x80>;
+ };
+ };
+
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x14 0x20>;
+ description = "Register 0 to log errors";
+
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x01>;
+ lut = "Not Locked\0Locked";
+ };
+
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x01 0x04>;
+ lut = "RD: data read with incrementing address\0RDW: data read with wrapping address\0RDL: allocates monitor in the Target with incrementing address\0RDX: exclusive read with incrementing address\0WR: data write with incrementing address\0WRW: data write with wrapping address\0WRC: conditional write if matching monitor in Target is found\0RSV: reserved\0PRE: preamble packet of linked sequence (locked sequence)\0URG: urgency packet used for QoS (status must be REQ)";
+ };
+
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x08 0x03>;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error\0DEC (error source: Initiator NIU): decode error\0UNS (error source: Target NIU): unsupported access type\0DISC (error source: Power Disconnect): disconnected Target or NoC domain\0SEC (error source: Initiator NIU or Firewall): security error\0HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator\0TMO (error source: Target NIU): time-out\0RSV: reserved";
+ };
+
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x10 0x0c>;
+ };
+
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x1f 0x01>;
+ lut = "NTTP v3.0 (Invalid)\0NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register\0eswin,win2030,noc,filter,routeid";
+ offset,length = <0x18 0x20>;
+ description = "Register 1 to log errors";
+
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x13 0x04>;
+ lut = "aon_snoc_sp0/I/0\0dspt_snoc/I/0\0jtag_snoc/I/0\0mcput_snoc_d2d/I/0\0mcput_snoc_mp/I/0\0mcput_snoc_sp0/I/0\0mcput_snoc_sp1/I/0\0mnoc_snoc/I/0\0npu_snoc_sp0/I/0\0npu_snoc_sp1/I/0\0pciet_snoc_p/I/0\0rnoc_snoc/I/0\0spislv_tbu3_snoc/I/0\0tbu4_snoc/I/0\0tcu_snoc/I/0\0RESERVED0";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x0f 0x04>;
+ lut = "snoc_aon/T/0\0snoc_cnoc/T/0\0snoc_ddrt0_p1/T/0\0snoc_ddrt0_p2/T/0\0snoc_ddrt1_p1/T/0\0snoc_ddrt1_p2/T/0\0snoc_dspt/T/0\0snoc_lnoc/T/0\0snoc_mcput_d2d/T/0\0snoc_mnoc/T/0\0snoc_npu/T/0\0snoc_pciet/T/0\0snoc_rnoc/T/0\0snoc_service/T/0\0RESERVED1\0RESERVED2";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x09 0x06>;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x09>;
+ };
+ };
+
+ ErrorLogger3 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 0x20>;
+ description = "Register 3 to log errors";
+ aperture-link = <0x01>;
+ msb-link = <0x04>;
+
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x09 0x0e>;
+ aperture-size = <0x49d>;
+ aperture-idx,aperture-base = <0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x52060000 0x00 0x00 0x00 0x01 0x00 0x01 0x00 0x72060000 0x00 0x00 0x00 0x01 0x00 0x02 0x00 0x52100000 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x52200000 0x00 0x00 0x00 0x01 0x00 0x04 0x00 0x52300000 0x00 0x00 0x00 0x01 0x00 0x05 0x00 0x72100000 0x00 0x00 0x00 0x01 0x00 0x06 0x00 0x72200000 0x00 0x00 0x00 0x01 0x00 0x07 0x00 0x72300000 0x00 0x00 0x00 0x01 0x00 0x08 0x00 0x53000000 0x00 0x00 0x00 0x01 0x00 0x09 0x00 0x73000000 0x00 0x00 0x00 0x01 0x00 0x0a 0x00 0x50000000 0x00 0x00 0x00 0x01 0x00 0x0b 0x00 0x70000000 0x00 0x00 0x00 0x01 0x00 0x0c 0x00 0x54000000 0x00 0x00 0x00 0x01 0x00 0x0d 0x00 0x74000000 0x00 0x00 0x00 0x01 0x00 0x0e 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x0f 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x10 0x00 0x00 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x520e0000 0x00 0x00 0x00 0x06 0x00 0x01 0x00 0x720e0000 0x00 0x00 0x00 0x06 0x00 0x02 0x00 0x5b000000 0x00 0x00 0x00 0x06 0x00 0x03 0x00 0x7b000000 0x00 0x00 0x00 0x07 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0x00 0x11 0x140 0x9000000 0x00 0x0e 0x00 0x08 0x00 0x12 0x140 0xa000000 0x00 0x0e 0x00 0x08 0x00 0x13 0x140 0xb000000 0x00 0x0e 0x00 0x08 0x00 0x14 0x00 0x50000000 0x00 0x0e 0x00 0x08 0x00 0x15 0x00 0x70000000 0x00 0x0e 0x00 0x08 0x00 0x16 0x00 0x40000000 0x00 0x0e 0x00 0x08 0x00 0x17 0x00 0x60000000 0x00 0x0e 0x00 0x08 0x00 0x18 0x00 0x80000000 0x00 0x0e 0x00 0x08 0x00 0x19 0x01 0x00 0x00 0x0e 0x00 0x08 0x00 0x1a 0x02 0x00 0x00 0x0e 0x00 0x08 0x00 0x1b 0x04 0x00 0x00 0x0e 0x00 0x08 0x00 0x1c 0x08 0x00 0x00 0x0e 0x00 0x08 0x00 0x1d 0x18 0x00 0x00 0x0e 0x00 0x08 0x00 0x1e 0x38 0x00 0x00 0x0e 0x00 0x08 0x00 0x1f 0xd8 0x00 0x00 0x0e 0x00 0x08 0x00 0x20 0xf8 0x00 0x00 0x0e 0x00 0x08 0x00 0x21 0x20 0x00 0x00 0x0e 0x00 0x08 0x00 0x22 0x70 0x00 0x00 0x0e 0x00 0x08 0x00 0x23 0x70 0x100 0x00 0x0e 0x00 0x08 0x00 0x24 0xc0 0x00 0x00 0x0e 0x00 0x08 0x00 0x25 0xe0 0x00 0x00 0x0e 0x00 0x08 0x00 0x26 0x130 0x00 0x00 0x0e 0x00 0x08 0x00 0x27 0x130 0x100 0x00 0x0e 0x00 0x08 0x00 0x28 0x40 0x00 0x00 0x0e 0x00 0x08 0x00 0x29 0x40 0x100 0x00 0x0e 0x00 0x08 0x00 0x2a 0x80 0x00 0x00 0x0e 0x00 0x08 0x00 0x2b 0xa0 0x00 0x00 0x0e 0x00 0x08 0x00 0x2c 0x100 0x00 0x00 0x0e 0x00 0x08 0x00 0x2d 0x100 0x100 0x00 0x0e 0x00 0x0a 0x00 0x00 0x00 0x52080000 0x00 0x0e 0x00 0x0a 0x00 0x01 0x00 0x72080000 0x00 0x0e 0x00 0x0a 0x00 0x02 0x00 0x59000000 0x00 0x0e 0x00 0x0a 0x00 0x03 0x00 0x5a000000 0x00 0x0e 0x00 0x0a 0x00 0x04 0x00 0x79000000 0x00 0x0e 0x00 0x0a 0x00 0x05 0x00 0x7a000000 0x00 0x0e 0x00 0x0a 0x00 0x06 0x140 0x1000000 0x00 0x0e 0x00 0x0a 0x00 0x07 0x140 0x2000000 0x00 0x0e 0x00 0x0a 0x00 0x08 0x140 0x9000000 0x00 0x0e 0x00 0x0a 0x00 0x09 0x140 0xa000000 0x00 0x0e 0x00 0x0a 0x00 0x0a 0x18 0x00 0x00 0x0e 0x00 0x0a 0x00 0x0b 0x38 0x00 0x00 0x0e 0x00 0x0a 0x00 0x0c 0xd8 0x00 0x00 0x0e 0x00 0x0a 0x00 0x0d 0xf8 0x00 0x00 0x0e 0x00 0x0a 0x00 0x0e 0x70 0x00 0x00 0x0e 0x00 0x0a 0x00 0x0f 0x70 0x100 0x00 0x0e 0x00 0x0a 0x00 0x10 0x130 0x00 0x00 0x0e 0x00 0x0a 0x00 0x11 0x130 0x100 0x00 0x0e 0x00 0x0a 0x00 0x12 0x00 0x00 0x00 0x0e 0x00 0x0a 0x00 0x13 0x00 0x00>;
+ };
+ };
+
+ ErrorLogger4 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x24 0x20>;
+ description = "Register 4 to log errors";
+
+ addr_msb {
+ compatible = "eswin,win2030,bitfield";
+ description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+ offset,length = <0x00 0x09>;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x28 0x20>;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x12>;
+ lut = "Cache_0\0Cache_1\0Cache_2\0Cache_3\0Prot_0 \0Prot_1 \0Prot_2 \0User_0 \0User_1 \0User_2 \0User_3 \0User_4 \0User_5 \0User_6 \0qos0\0qos1\0qos2\0qos3";
+ };
+ };
+ };
+
+ d0_media_noc@52021400 {
+ compatible = "eswin,win2030-noc";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ reg = <0x00 0x52021400 0x00 0x4000>;
+ interrupts = <0x1c6>;
+ interrupt-names = "error";
+ interrupt-parent = <0x10>;
+ errlogger,idx = <0x00 0x01 0x03 0x04 0x05>;
+ eswin,qos-configs = "GPU\0TBU2\0VC";
+ eswin,GPU-qos-base = <0x52021480>;
+ eswin,GPU-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x1e0 0x14 0x01 0x18 0x01>;
+ eswin,TBU2-qos-base = <0x52021500>;
+ eswin,TBU2-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x18 0x14 0x10 0x18 0x01>;
+ eswin,VC-qos-base = <0x52021580>;
+ eswin,VC-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x18 0x14 0x10 0x18 0x01>;
+ status = "okay";
+ stat,0 = "TracePort:ddr0_p3_req";
+ stat,1 = "TracePort:ddr1_p3_req";
+
+ sideband_manager@52022000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0x00 0x52022000 0x00 0x10>;
+ SenseIn0 = <0x46 0x00 0x47 0x01 0x48 0x02 0x49 0x03 0x4a 0x04>;
+ bf-name = "SBM_MNOC_GPU\0SBM_MNOC_TBU2\0SBM_MNOC_VC\0SBM_MNOC_DDRT0_P3\0SBM_MNOC_DDRT1_P3";
+ };
+
+ mnoc_packet_ddr0_p3_req_probe@52020000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52020000 0x00 0x4000>;
+ clocks = <0x03 0x21a>;
+ clock-names = "clk";
+ interrupts = <0x1ca>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr0_p3_req";
+ };
+
+ mnoc_packet_ddr1_p3_req_probe@52020800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52020800 0x00 0x4000>;
+ clocks = <0x03 0x21f>;
+ clock-names = "clk";
+ interrupts = <0x1c8>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr1_p3_req";
+ };
+
+ mnoc_trans_probe@52021000 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0x00 0x52021000 0x00 0x4000>;
+ clocks = <0x03 0x203>;
+ clock-names = "clk";
+ interrupts = <0x1c5>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x03>;
+ counter,nr = <0x0c>;
+ profiler,nr = <0x01>;
+ portsel = "gpu\0tbu2\0vc";
+
+ mnoc_trans_gpu_filter@52021600 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52021600 0x00 0x80>;
+ };
+
+ mnoc_trans_tbu2_filter@52021680 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52021680 0x00 0x80>;
+ };
+
+ mnoc_trans_vc_filter@52021700 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52021700 0x00 0x80>;
+ };
+
+ mnoc_trans_profiler@52021780 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0x00 0x52021780 0x00 0x80>;
+ };
+ };
+
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x14 0x20>;
+ description = "Register 0 to log errors";
+
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x01>;
+ lut = "Not Locked\0Locked";
+ };
+
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x01 0x04>;
+ lut = "RD: data read with incrementing address\0RDW: data read with wrapping address\0RDL: allocates monitor in the Target with incrementing address\0RDX: exclusive read with incrementing address\0WR: data write with incrementing address\0WRW: data write with wrapping address\0WRC: conditional write if matching monitor in Target is found\0RSV: reserved\0PRE: preamble packet of linked sequence (locked sequence)\0URG: urgency packet used for QoS (status must be REQ)";
+ };
+
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x08 0x03>;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error\0DEC (error source: Initiator NIU): decode error\0UNS (error source: Target NIU): unsupported access type\0DISC (error source: Power Disconnect): disconnected Target or NoC domain\0SEC (error source: Initiator NIU or Firewall): security error\0HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator\0TMO (error source: Target NIU): time-out\0RSV: reserved";
+ };
+
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x10 0x0c>;
+ };
+
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x1f 0x01>;
+ lut = "NTTP v3.0 (Invalid)\0NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register\0eswin,win2030,noc,filter,routeid";
+ offset,length = <0x18 0x20>;
+ description = "Register 1 to log errors";
+
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x0e 0x02>;
+ lut = "gpu_mnoc/I/0\0snoc_mnoc/I/0\0tbu2_mnoc/I/0\0vc_mnoc/I/0";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x0c 0x02>;
+ lut = "mnoc_ddrt0_p3/T/0\0mnoc_ddrt1_p3/T/0\0mnoc_service/T/0\0mnoc_snoc/T/0";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x09 0x03>;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x09>;
+ };
+ };
+
+ ErrorLogger3 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 0x20>;
+ description = "Register 3 to log errors";
+ aperture-link = <0x01>;
+ msb-link = <0x04>;
+
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x09 0x07>;
+ aperture-size = <0x37>;
+ aperture-idx,aperture-base = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x00 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x00 0x00 0x00 0x00 0x06 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0x40 0x100 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x00 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x00 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x00 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x00 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x00 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x00 0x00 0x01 0x00 0x06 0x40 0x80 0x00 0x00 0x00 0x01 0x00 0x07 0x40 0x180 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x02 0x00 0x00 0x00 0x52020000 0x00 0x01 0x00 0x02 0x00 0x01 0x00 0x72020000 0x00 0x01 0x00 0x02 0x00 0x02 0x00 0x00 0x00 0x01 0x00 0x02 0x00 0x03 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x02 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x02 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x02 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x02 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x02 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x02 0x00 0x00 0x00 0x06 0x40 0x00 0x00 0x02 0x00 0x00 0x00 0x07 0x40 0x100 0x00 0x02 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x02 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x02 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x02 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x02 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x02 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x02 0x00 0x01 0x00 0x06 0x40 0x80 0x00 0x02 0x00 0x01 0x00 0x07 0x40 0x180 0x00 0x02 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x03 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x03 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x03 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x03 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x03 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x03 0x00 0x00 0x00 0x06 0x40 0x00 0x00 0x03 0x00 0x00 0x00 0x07 0x40 0x100 0x00 0x03 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x03 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x03 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x03 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x03 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x03 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x03 0x00 0x01 0x00 0x06 0x40 0x80 0x00 0x03 0x00 0x01 0x00 0x07 0x40 0x180 0x00 0x03 0x00 0x03 0x00 0x00 0x00 0x00>;
+ };
+ };
+
+ ErrorLogger4 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x24 0x20>;
+ description = "Register 4 to log errors";
+
+ addr_msb {
+ compatible = "eswin,win2030,bitfield";
+ description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+ offset,length = <0x00 0x09>;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x28 0x20>;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x12>;
+ lut = "Cache_0\0Cache_1\0Cache_2\0Cache_3\0Prot_0 \0Prot_1 \0Prot_2 \0User_0 \0User_1 \0User_2 \0User_3 \0User_4 \0User_5 \0User_6 \0qos0\0qos1\0qos2\0qos3";
+ };
+ };
+ };
+
+ d0_realtime_noc@52041400 {
+ compatible = "eswin,win2030-noc";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ reg = <0x00 0x52041400 0x00 0x4000>;
+ interrupts = <0x1c0>;
+ interrupt-names = "error";
+ interrupt-parent = <0x10>;
+ errlogger,idx = <0x00 0x01 0x03 0x04 0x05>;
+ eswin,qos-configs = "TBU0\0VO";
+ eswin,TBU0-qos-base = <0x52041480>;
+ eswin,TBU0-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x1e0 0x14 0x01 0x18 0x01>;
+ eswin,VO-qos-base = <0x52041500>;
+ eswin,VO-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x18 0x14 0x10 0x18 0x01>;
+ status = "okay";
+ stat,0 = "TracePort:ddr0_p4_req";
+ stat,1 = "TracePort:ddr1_p4_req";
+
+ sideband_manager@52042000 {
+ compatible = "eswin,win2xxx-noc-sideband-manager";
+ reg = <0x00 0x52042000 0x00 0x10>;
+ SenseIn0 = <0x50 0x00 0x51 0x01 0x52 0x02 0x53 0x03>;
+ bf-name = "SBM_RNOC_TBU0\0SBM_RNOC_VO\0SBM_RNOC_DDRT0_P4\0SBM_RNOC_DDRT1_P4";
+ };
+
+ rnoc_packet_ddr0_p4_req_probe@52040000 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52040000 0x00 0x4000>;
+ clocks = <0x03 0x21b>;
+ clock-names = "clk";
+ interrupts = <0x1c4>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr0_p4_req";
+ };
+
+ rnoc_packet_ddr1_p4_req_probe@52040800 {
+ compatible = "eswin,win2xxx-noc-packet-probe";
+ reg = <0x00 0x52040800 0x00 0x4000>;
+ clocks = <0x03 0x220>;
+ clock-names = "clk";
+ interrupts = <0x1c2>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x01>;
+ counter,nr = <0x02>;
+ portsel = "ddr1_p4_req";
+ };
+
+ rnoc_trans_probe@52041000 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ compatible = "eswin,win2xxx-noc-trans-probe";
+ reg = <0x00 0x52041000 0x00 0x4000>;
+ clocks = <0x03 0x203>;
+ clock-names = "clk";
+ interrupts = <0x1bf>;
+ interrupt-names = "stat";
+ interrupt-parent = <0x10>;
+ filter,nr = <0x02>;
+ counter,nr = <0x08>;
+ profiler,nr = <0x01>;
+ portsel = "tbu0\0vo";
+
+ rnoc_trans_tbu0_filter@52041580 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52041580 0x00 0x80>;
+ };
+
+ rnoc_trans_vo_filter@52041600 {
+ status = "disabled";
+ compatible = "eswin,win2xxx-noc-trans-filter";
+ reg = <0x00 0x52041600 0x00 0x80>;
+ };
+
+ rnoc_trans_profiler@52041680 {
+ compatible = "eswin,win2xxx-noc-trans-profiler";
+ reg = <0x00 0x52041680 0x00 0x80>;
+ };
+ };
+
+ ErrorLogger0 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x14 0x20>;
+ description = "Register 0 to log errors";
+
+ lock {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x01>;
+ lut = "Not Locked\0Locked";
+ };
+
+ OpCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x01 0x04>;
+ lut = "RD: data read with incrementing address\0RDW: data read with wrapping address\0RDL: allocates monitor in the Target with incrementing address\0RDX: exclusive read with incrementing address\0WR: data write with incrementing address\0WRW: data write with wrapping address\0WRC: conditional write if matching monitor in Target is found\0RSV: reserved\0PRE: preamble packet of linked sequence (locked sequence)\0URG: urgency packet used for QoS (status must be REQ)";
+ };
+
+ ErrCode {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x08 0x03>;
+ lut = "SLV (error source: Target): error detected by the Slave without any information or no Error\0DEC (error source: Initiator NIU): decode error\0UNS (error source: Target NIU): unsupported access type\0DISC (error source: Power Disconnect): disconnected Target or NoC domain\0SEC (error source: Initiator NIU or Firewall): security error\0HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator\0TMO (error source: Target NIU): time-out\0RSV: reserved";
+ };
+
+ Len1 {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x10 0x0c>;
+ };
+
+ Format {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x1f 0x01>;
+ lut = "NTTP v3.0 (Invalid)\0NTTP v3.5 (Ok)";
+ };
+ };
+
+ ErrorLogger1 {
+ compatible = "eswin,win2030,register\0eswin,win2030,noc,filter,routeid";
+ offset,length = <0x18 0x20>;
+ description = "Register 1 to log errors";
+
+ InitFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x0e 0x02>;
+ lut = "snoc_rnoc/I/0\0tbu0_rnoc/I/0\0vo_rnoc/I/0\0RESERVED0";
+ };
+
+ TargetFlow {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x0c 0x02>;
+ lut = "rnoc_ddrt0_p4/T/0\0rnoc_ddrt1_p4/T/0\0rnoc_service/T/0\0rnoc_snoc/T/0";
+ };
+
+ TargetSubRange {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x09 0x03>;
+ };
+
+ SeqId {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x09>;
+ };
+ };
+
+ ErrorLogger3 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x20 0x20>;
+ description = "Register 3 to log errors";
+ aperture-link = <0x01>;
+ msb-link = <0x04>;
+
+ AbsoluteAddress {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x09 0x07>;
+ aperture-size = <0x28>;
+ aperture-idx,aperture-base = <0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x52040000 0x00 0x00 0x00 0x02 0x00 0x01 0x00 0x72040000 0x00 0x00 0x00 0x02 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x03 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x01 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x01 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x01 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x01 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x01 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x01 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x01 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x01 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x01 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x01 0x00 0x03 0x00 0x00 0x00 0x59000000 0x00 0x01 0x00 0x03 0x00 0x01 0x00 0x79000000 0x00 0x01 0x00 0x03 0x00 0x02 0x140 0x1000000 0x00 0x01 0x00 0x03 0x00 0x03 0x140 0x9000000 0x00 0x01 0x00 0x03 0x00 0x04 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x02 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x02 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x02 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x02 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x02 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x02 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x02 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x02 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x02 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x02 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x02 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x02 0x00 0x03 0x00 0x00 0x00 0x59000000 0x00 0x02 0x00 0x03 0x00 0x01 0x00 0x79000000 0x00 0x02 0x00 0x03 0x00 0x02 0x140 0x1000000 0x00 0x02 0x00 0x03 0x00 0x03 0x140 0x9000000 0x00 0x02 0x00 0x03 0x00 0x04 0x00 0x00 0x00 0x02 0x00 0x03 0x00 0x05 0x00 0x00>;
+ };
+ };
+
+ ErrorLogger4 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x24 0x20>;
+ description = "Register 4 to log errors";
+
+ addr_msb {
+ compatible = "eswin,win2030,bitfield";
+ description = "Stores NTTP packet header field Addr (MSBs) of the logged error";
+ offset,length = <0x00 0x09>;
+ };
+ };
+
+ ErrorLogger5 {
+ compatible = "eswin,win2030,register";
+ offset,length = <0x28 0x20>;
+ description = "Register 5 to log errors";
+
+ User_flag {
+ compatible = "eswin,win2030,bitfield";
+ offset,length = <0x00 0x10>;
+ lut = "Cache_0\0Cache_1\0Cache_2\0Cache_3\0Prot_0 \0Prot_1 \0Prot_2 \0User_0 \0User_1 \0User_2 \0User_3 \0User_4 \0qos0\0qos1\0qos2\0qos3";
+ };
+ };
+ };
+ };
+
+ eswin-npu@51c00000 {
+ compatible = "eswin,npu";
+ reg = <0x00 0x51c00000 0x00 0x400000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x183 0x10>;
+ #size-cells = <0x02>;
+ dma-ranges = <0x01 0x00 0x00 0xc0000000 0x1ff 0x00>;
+ iommus = <0x19 0x04>;
+ tbus = <0x05>;
+ dsp-avail-num = <0x01>;
+ spram-size = <0x400000>;
+ npu_mbox = <0x22>;
+ clocks = <0x03 0x236 0x03 0x237 0x03 0x23c 0x03 0x23d>;
+ clock-names = "aclk\0cfg_clk\0core_clk\0e31_core_clk";
+ resets = <0x18 0x06 0x08>;
+ reset-names = "e31_core";
+ numa-node-id = <0x00>;
+ firmware-name = "eic7700_die0_e31_fw";
+ dma-noncoherent;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x00>;
+ status = "okay";
+ phandle = <0x4e>;
+ };
+
+ llc@51c00000 {
+ compatible = "eswin,llc";
+ reg = <0x00 0x51c00000 0x00 0x400000>;
+ eswin,syscfg = <0x17 0x324>;
+ eswin,syscrg_csr = <0x16>;
+ clocks = <0x03 0x236 0x03 0x237 0x03 0x23a 0x03 0x23c 0x03 0x26 0x03 0x0b 0x03 0x07>;
+ clock-names = "aclk\0cfg_clk\0llc_clk\0core_clk\0mux_u_npu_core_3mux1_gfree\0fixed_rate_clk_spll2_fout2\0fixed_rate_clk_spll1_fout1";
+ resets = <0x18 0x06 0x01 0x18 0x06 0x02 0x18 0x06 0x04 0x18 0x06 0x40>;
+ reset-names = "axi\0cfg\0core\0llc";
+ numa-node-id = <0x00>;
+ spram-region = <0x23>;
+ apply_npu_high_freq;
+ };
+
+ dsp_subsys@52280400 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x52280400 0x00 0x10000 0x00 0x51810000 0x00 0x8000>;
+ ranges;
+ dma-ranges = <0x00 0x30000000 0x00 0xc0000000 0x00 0xce000000>;
+ compatible = "es-dsp-subsys\0simple-bus";
+ clocks = <0x03 0x210 0x03 0x20f>;
+ clock-names = "cfg_clk\0aclk";
+ resets = <0x18 0x02 0x01 0x18 0x02 0x02 0x18 0x02 0x04 0x18 0x02 0x10 0x18 0x02 0x20 0x18 0x02 0x40 0x18 0x02 0x80>;
+ reset-names = "axi\0cfg\0div4\0div_0\0div_1\0div_2\0div_3";
+ status = "okay";
+
+ es_dsp@0 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b000000 0x8000 0x28100000 0x00 0x5b100000 0x20000 0x28120000 0x00 0x5b120000 0x20000>;
+ clocks = <0x03 0x2a8>;
+ clock-names = "aclk";
+ dsp_mbox = <0x24>;
+ device-irq = <0x0b 0x50a90000 0x20 0x50a80000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x00>;
+ iommus = <0x19 0x12>;
+ tbus = <0x70>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ es_dsp@1 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b008000 0x8000 0x28100000 0x00 0x5b140000 0x20000 0x28120000 0x00 0x5b160000 0x20000>;
+ clocks = <0x03 0x2a9>;
+ clock-names = "aclk";
+ dsp_mbox = <0x25>;
+ device-irq = <0x0d 0x50ab0000 0x40 0x50aa0000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x01>;
+ iommus = <0x19 0x13>;
+ tbus = <0x71>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ es_dsp@2 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b010000 0x8000 0x28100000 0x00 0x5b180000 0x20000 0x28120000 0x00 0x5b1a0000 0x20000>;
+ clocks = <0x03 0x2aa>;
+ clock-names = "aclk";
+ dsp_mbox = <0x26>;
+ device-irq = <0x0f 0x50ad0000 0x80 0x50ac0000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x02>;
+ iommus = <0x19 0x14>;
+ tbus = <0x72>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ es_dsp@3 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b018000 0x8000 0x28100000 0x00 0x5b1c0000 0x20000 0x28120000 0x00 0x5b1e0000 0x20000>;
+ clocks = <0x03 0x2ab>;
+ clock-names = "aclk";
+ dsp_mbox = <0x27>;
+ device-irq = <0x11 0x50af0000 0x100 0x50ae0000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x03>;
+ iommus = <0x19 0x15>;
+ tbus = <0x73>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+ };
+
+ g2d@50140000 {
+ compatible = "eswin,galcore_d0";
+ clocks = <0x03 0x254 0x03 0x255 0x03 0x25a 0x03 0x25b 0x03 0x25c 0x03 0x25d 0x03 0x2b1>;
+ clock-names = "vc_aclk\0vc_cfg\0g2d_cfg\0g2d_st2\0g2d_clk\0g2d_aclk\0mon_pclk";
+ resets = <0x18 0x16 0x02 0x18 0x16 0x01 0x18 0x16 0x04 0x18 0x1b 0x01 0x18 0x1b 0x02 0x18 0x1b 0x04>;
+ reset-names = "axi\0cfg\0moncfg\0g2d_core\0g2d_cfg\0g2d_axi";
+ reg = <0x00 0x50140000 0x00 0x40000 0x00 0x50180000 0x00 0x40000>;
+ reg-names = "core_2d\0core_2d1";
+ fe-apb-offset = <0x800>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x31 0x32>;
+ interrupt-names = "core_2d\0core_2d1";
+ enable-mmu = <0x01>;
+ contiguous-size = <0xa00000>;
+ recovery = <0x00>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ status = "okay";
+ };
+
+ gpu@51400000 {
+ compatible = "img,gpu";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x51400000 0x00 0xfffff>;
+ clocks = <0x03 0x20b 0x03 0x20c 0x03 0x20d>;
+ clock-names = "aclk\0gray_clk\0cfg_clk";
+ resets = <0x18 0x01 0x01 0x18 0x01 0x02 0x18 0x01 0x04 0x18 0x01 0x08 0x18 0x01 0x10>;
+ reset-names = "axi\0cfg\0gray\0jones\0spu";
+ interrupt-parent = <0x10>;
+ interrupts = <0x0f>;
+ dma-noncoherent;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x00>;
+ status = "okay";
+ phandle = <0x4f>;
+ };
+
+ sata@0x50420000 {
+ compatible = "snps,eswin-ahci";
+ reg = <0x00 0x50420000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupt-names = "intrq\0msi\0pme";
+ interrupts = <0x3a 0x3b 0x3c>;
+ ports-implemented = <0x01>;
+ resets = <0x18 0x07 0x8000000>;
+ reset-names = "apb";
+ #size-cells = <0x02>;
+ iommus = <0x19 0x0e>;
+ tbus = <0x02>;
+ dma-ranges = <0x00 0x00 0x00 0xc0000000 0x200 0x00>;
+ eswin,hsp_sp_csr = <0x1a 0x1050>;
+ eswin,syscrg_csr = <0x16 0x41c>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <0x28>;
+ };
+
+ pcie@0x54000000 {
+ compatible = "eswin,win2030-pcie";
+ clocks = <0x03 0x232 0x03 0x233 0x03 0x234 0x03 0x235>;
+ clock-names = "pcie_aclk\0pcie_cfg_clk\0pcie_cr_clk\0pcie_aux_clk";
+ reset-names = "pcie_cfg\0pcie_powerup\0pcie_pwren";
+ resets = <0x18 0x08 0x01 0x18 0x08 0x02 0x18 0x08 0x04>;
+ #address-cells = <0x03>;
+ #size-cells = <0x02>;
+ #interrupt-cells = <0x01>;
+ reg = <0x00 0x54000000 0x00 0x4000000 0x00 0x40000000 0x00 0x800000 0x00 0x50000000 0x00 0x100000>;
+ reg-names = "dbi\0config\0mgmt";
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0x00 0x40800000 0x00 0x40800000 0x00 0x800000 0x82000000 0x00 0x41000000 0x00 0x41000000 0x00 0xf000000 0xc3000000 0x80 0x00 0x80 0x00 0x02 0x00>;
+ num-lanes = <0x04>;
+ interrupts = <0xdc 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba>;
+ interrupt-names = "msi\0inta\0intb\0intc\0intd";
+ interrupt-parent = <0x10>;
+ interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+ interrupt-map = <0x00 0x00 0x00 0x01 0x10 0xb3 0x00 0x00 0x00 0x02 0x10 0xb4 0x00 0x00 0x00 0x03 0x10 0xb5 0x00 0x00 0x00 0x04 0x10 0xb6>;
+ iommus = <0x19 0xfe0000>;
+ iommu-map = <0x00 0x19 0xff0000 0xffffff>;
+ tbus = <0x03>;
+ status = "okay";
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ };
+
+ spi@50810000 {
+ compatible = "snps,eic770x-spi";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x50810000 0x00 0x4000>;
+ spi-max-frequency = "\0I>";
+ clocks = <0x03 0x29c>;
+ clock-names = "clk";
+ interrupt-parent = <0x10>;
+ interrupts = <0x5b>;
+ resets = <0x18 0x10 0x01>;
+ reset-names = "spi";
+ numa-node-id = <0x00>;
+ status = "okay";
+ dma-noncoherent;
+ num-cs = <0x02>;
+
+ spi-flash@0 {
+ compatible = "winbond,w25q128fw\0jedec,spi-nor";
+ reg = <0x00>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ spi-max-frequency = "\0I>";
+ rx-sample-delay-ns = <0x0a>;
+ };
+
+ spi-flash@1 {
+ compatible = "winbond,w25q128fw\0jedec,spi-nor";
+ reg = <0x01>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ spi-max-frequency = "\0I>";
+ rx-sample-delay-ns = <0x0a>;
+ };
+ };
+
+ spi@50814000 {
+ compatible = "snps,eic770x-spi";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x50814000 0x00 0x4000>;
+ spi-max-frequency = "\0I>";
+ clocks = <0x03 0x29d>;
+ clock-names = "clk";
+ interrupt-parent = <0x10>;
+ interrupts = <0x5c>;
+ resets = <0x18 0x10 0x02>;
+ reset-names = "spi";
+ numa-node-id = <0x00>;
+ status = "disabled";
+ dma-noncoherent;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x29>;
+ num-cs = <0x02>;
+
+ spi-flash@0 {
+ compatible = "winbond,w25q128fw\0jedec,spi-nor";
+ reg = <0x00>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ spi-max-frequency = "\0I>";
+ rx-sample-delay-ns = <0x0a>;
+ };
+
+ spi-flash@1 {
+ compatible = "winbond,w25q128fw\0jedec,spi-nor";
+ reg = <0x01>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ spi-max-frequency = "\0I>";
+ rx-sample-delay-ns = <0x0a>;
+ };
+ };
+
+ spi@51800000 {
+ compatible = "eswin,bootspi";
+ reg = <0x00 0x51800000 0x00 0x8000 0x00 0x51828000 0x00 0x8000 0x00 0x5c000000 0x00 0x8000>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ clocks = <0x03 0x205 0x03 0x204>;
+ clock-names = "cfg_clk\0clk";
+ resets = <0x18 0x24 0x02>;
+ reset-names = "rst";
+ spi-max-frequency = "\0I>";
+ reg-io-width = <0x04>;
+ status = "okay";
+ num-cs = <0x01>;
+ cs-gpios = <0x2a 0x00 0x01>;
+ wp-gpios = <0x2a 0x04 0x01>;
+
+ spi-flash@0 {
+ compatible = "winbond,w25q128jw\0jedec,spi-nor";
+ reg = <0x00>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ spi-max-frequency = "\0I>";
+ rx-sample-delay-ns = <0x0a>;
+ };
+ };
+
+ mmc@50450000 {
+ compatible = "eswin,emmc-sdhci-5.1";
+ reg = <0x00 0x50450000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x4f>;
+ assigned-clocks = <0x03 0x22a>;
+ assigned-clock-rates = <0xbebc200>;
+ clocks = <0x03 0x22a 0x03 0x222>;
+ clock-names = "clk_xin\0clk_ahb";
+ clock-output-names = "emmc_cardclock";
+ #clock-cells = <0x00>;
+ resets = <0x18 0x07 0x40 0x18 0x07 0x08 0x18 0x07 0x80000 0x18 0x07 0x800000>;
+ reset-names = "txrx_rst\0phy_rst\0prstn\0arstn";
+ core-clk-reg = <0x51828160>;
+ disable-cqe-dcmd;
+ bus-width = <0x08>;
+ non-removable;
+ mmc-hs400-1_8v;
+ max-frequency = <0xbebc200>;
+ #size-cells = <0x02>;
+ iommus = <0x19 0x0f>;
+ tbus = <0x02>;
+ dma-ranges = <0x00 0x00 0x00 0xc0000000 0x01 0x00>;
+ eswin,hsp_sp_csr = <0x1a 0x1038 0x508 0x50c>;
+ eswin,syscrg_csr = <0x16 0x160 0x148 0x14c>;
+ status = "okay";
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ delay_code = <0x17>;
+ drive-impedance-ohm = <0x32>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x2b>;
+ no-sdio;
+ no-sd;
+ };
+
+ mmc@0x50460000 {
+ compatible = "eswin,sdhci-sdio";
+ reg = <0x00 0x50460000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x51>;
+ clocks = <0x03 0x22b 0x03 0x222 0x03 0x0c 0x03 0x23>;
+ clock-names = "clk_xin\0clk_ahb\0clk_spll2_fout3\0clk_mux1_1";
+ clock-output-names = "sdio0_cardclock";
+ #clock-cells = <0x00>;
+ resets = <0x18 0x07 0x80 0x18 0x07 0x10 0x18 0x07 0x40000 0x18 0x07 0x400000>;
+ reset-names = "txrx_rst\0phy_rst\0prstn\0arstn";
+ clock-frequency = <0xc65d400>;
+ max-frequency = <0xc65d400>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ dma-ranges = <0x00 0x20000000 0x00 0xc0000000 0x00 0x40000000>;
+ iommus = <0x19 0x10>;
+ tbus = <0x02>;
+ eswin,hsp_sp_csr = <0x1a 0x103c 0x608 0x60c>;
+ eswin,syscrg_csr = <0x16 0x164 0x148 0x14c>;
+ bus-width = <0x04>;
+ sdio-id = <0x00>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ dma-noncoherent;
+ delay_code = <0x3b>;
+ drive-impedance-ohm = <0x21>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ no-sdio;
+ no-mmc;
+ disable-wp;
+ broken-cd;
+ };
+
+ mmc@0x50470000 {
+ compatible = "eswin,sdhci-sdio";
+ reg = <0x00 0x50470000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x53>;
+ clocks = <0x03 0x22c 0x03 0x222 0x03 0x0c 0x03 0x23>;
+ clock-names = "clk_xin\0clk_ahb\0clk_spll2_fout3\0clk_mux1_1";
+ clock-output-names = "sdio1_cardclock";
+ #clock-cells = <0x00>;
+ resets = <0x18 0x07 0x100 0x18 0x07 0x20 0x18 0x07 0x20000 0x18 0x07 0x200000>;
+ reset-names = "txrx_rst\0phy_rst\0prstn\0arstn";
+ clock-frequency = <0xc65d400>;
+ max-frequency = <0xc65d400>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ dma-ranges = <0x00 0x20000000 0x00 0xc0000000 0x00 0x40000000>;
+ iommus = <0x19 0x11>;
+ tbus = <0x02>;
+ eswin,hsp_sp_csr = <0x1a 0x1040 0x708 0x70c>;
+ eswin,syscrg_csr = <0x16 0x168 0x148 0x14c>;
+ bus-width = <0x04>;
+ sdio-id = <0x01>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ dma-noncoherent;
+ delay_code = <0x29>;
+ drive-impedance-ohm = <0x21>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ keep-power-in-suspend;
+ non-removable;
+ no-sd;
+ no-mmc;
+ };
+
+ video-decoder0@50100000 {
+ compatible = "eswin,video-decoder0";
+ clocks = <0x03 0x254 0x03 0x255 0x03 0x257 0x03 0x259 0x03 0x2e 0x03 0x04 0x03 0x0a 0x03 0x2ae 0x03 0x2b0 0x03 0x2b1>;
+ clock-names = "aclk\0cfg_clk\0jd_clk\0vd_clk\0vc_mux\0spll0_fout1\0spll2_fout1\0jd_pclk\0vd_pclk\0mon_pclk";
+ resets = <0x18 0x16 0x02 0x18 0x16 0x01 0x18 0x16 0x04 0x18 0x17 0x01 0x18 0x17 0x02 0x18 0x19 0x01 0x18 0x19 0x02>;
+ reset-names = "axi\0cfg\0moncfg\0jd_cfg\0jd_axi\0vd_cfg\0vd_axi";
+ eswin,syscfg = <0x17 0x00 0x04>;
+ vcmd-core = <0x00 0x6c>;
+ axife-core = <0x200 0x100>;
+ vdec-core = <0x800 0xc00>;
+ interrupt-parent = <0x10>;
+ #size-cells = <0x02>;
+ dma-ranges = <0x00 0x00 0x00 0x80000000 0x200 0x00>;
+ iommus = <0x19 0x02>;
+ vccsr-reg = <0x00 0x501c0000 0x00 0x1000>;
+ numa-node-id = <0x00>;
+ tbus = <0x10 0x13>;
+ dma-noncoherent;
+ status = "okay";
+
+ vdec0@50100000 {
+ core-name = "video-dec0";
+ base-addr = <0x50100000>;
+ interrupts = <0xec>;
+ };
+
+ jdec0@50120000 {
+ core-name = "jpeg-dec0";
+ base-addr = <0x50120000>;
+ interrupts = <0xed>;
+ };
+ };
+
+ video-encoder@50110000 {
+ compatible = "eswin,video-encoder0";
+ clocks = <0x03 0x254 0x03 0x255 0x03 0x256 0x03 0x258 0x03 0x2e 0x03 0x04 0x03 0x0a 0x03 0x2ad 0x03 0x2af 0x03 0x2b1>;
+ clock-names = "aclk\0cfg_clk\0je_clk\0ve_clk\0vc_mux\0spll0_fout1\0spll2_fout1\0je_pclk\0ve_pclk\0mon_pclk";
+ resets = <0x18 0x16 0x02 0x18 0x16 0x01 0x18 0x16 0x04 0x18 0x18 0x01 0x18 0x18 0x02 0x18 0x1a 0x02 0x18 0x1a 0x01>;
+ reset-names = "axi\0cfg\0moncfg\0je_cfg\0je_axi\0ve_cfg\0ve_axi";
+ eswin,syscfg = <0x17 0x00 0x04>;
+ vcmd-core = <0x00 0x6c>;
+ axife-core = <0x2000 0x7d0>;
+ venc-core = <0x1000 0x87c>;
+ interrupt-parent = <0x10>;
+ #size-cells = <0x02>;
+ dma-ranges = <0x00 0x00 0x00 0x80000000 0x200 0x00>;
+ iommus = <0x19 0x03>;
+ vccsr-reg = <0x00 0x501c0000 0x00 0x1000>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+
+ venc0@50110000 {
+ core-name = "video-enc0";
+ base-addr = <0x50110000>;
+ interrupts = <0xe5>;
+ tbus = <0x11>;
+ };
+
+ jenc0@50130000 {
+ core-name = "jpeg-enc0";
+ base-addr = <0x50130000>;
+ interrupts = <0xe8>;
+ tbus = <0x12>;
+ };
+ };
+
+ mbox@50a00000 {
+ compatible = "eswin,win2030-mailbox";
+ reg = <0x00 0x50a00000 0x00 0x10000 0x00 0x50a10000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x75>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x27e 0x03 0x27f>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x18 0x0c 0x01 0x18 0x0c 0x02>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x02>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x2c>;
+ };
+
+ mbox@50a20000 {
+ compatible = "eswin,win2030-mailbox";
+ reg = <0x00 0x50a20000 0x00 0x10000 0x00 0x50a30000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x77>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x280 0x03 0x281>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x18 0x0c 0x04 0x18 0x0c 0x08>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x04>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x2d>;
+ };
+
+ mbox@50a40000 {
+ compatible = "eswin,npu0-mailbox";
+ reg = <0x00 0x50a40000 0x00 0x10000 0x00 0x50a50000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x79>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x282 0x03 0x283>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x18 0x0c 0x10 0x18 0x0c 0x20>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x08>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x22>;
+ };
+
+ mbox@50a60000 {
+ compatible = "eswin,win2030-mailbox";
+ reg = <0x00 0x50a60000 0x00 0x10000 0x00 0x50a70000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x7b>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x284 0x03 0x285>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x18 0x0c 0x40 0x18 0x0c 0x80>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x10>;
+ dma-noncoherent;
+ status = "okay";
+ };
+
+ mbox@50a80000 {
+ compatible = "eswin,dsp0-mailbox";
+ reg = <0x00 0x50a80000 0x00 0x10000 0x00 0x50a90000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x7d>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x286 0x03 0x287>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x18 0x0c 0x100 0x18 0x0c 0x200>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x20>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x24>;
+ };
+
+ mbox@50aa0000 {
+ compatible = "eswin,dsp1-mailbox";
+ reg = <0x00 0x50aa0000 0x00 0x10000 0x00 0x50ab0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x7f>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x288 0x03 0x289>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x18 0x0c 0x400 0x18 0x0c 0x800>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x40>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x25>;
+ };
+
+ mbox@50ac0000 {
+ compatible = "eswin,dsp2-mailbox";
+ reg = <0x00 0x50ac0000 0x00 0x10000 0x00 0x50ad0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x81>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x28a 0x03 0x28b>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x18 0x0c 0x1000 0x18 0x0c 0x2000>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x80>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x26>;
+ };
+
+ mbox@50ae0000 {
+ compatible = "eswin,dsp3-mailbox";
+ reg = <0x00 0x50ae0000 0x00 0x10000 0x00 0x50af0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x83>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x28c 0x03 0x28d>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x18 0x0c 0x4000 0x18 0x0c 0x8000>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x100>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x27>;
+ };
+
+ ipc@0 {
+ compatible = "eswin,win2030-ipc";
+ #size-cells = <0x02>;
+ dma-ranges = <0x00 0x80000000 0x00 0xc0000000 0x00 0x80000000>;
+ iommus = <0x19 0x18 0x19 0x18>;
+ tbus = <0x04>;
+ eswin,syscfg = <0x17 0x1004 0x00 0x17 0x4004 0x00>;
+ mboxes = <0x2c 0x00>;
+ mbox-names = "u84_scpu";
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ };
+
+ lpcpu@0 {
+ compatible = "eswin,win2030-lpcpu";
+ clocks = <0x03 0x209 0x03 0x20a>;
+ clock-names = "core_clk\0bus_clk";
+ reset-names = "core_rst\0bus_rst\0dbg_rst";
+ resets = <0x18 0x15 0x01 0x18 0x15 0x02 0x18 0x15 0x04>;
+ #size-cells = <0x02>;
+ dma-ranges = <0x00 0xb0000000 0x00 0xc0000000 0x00 0x50000000>;
+ iommus = <0x19 0x19>;
+ eswin,syscfg = <0x17 0x2004 0x00>;
+ tbus = <0x04>;
+ mboxes = <0x2d 0x00>;
+ mbox-names = "u84_lpcpu";
+ numa-node-id = <0x00>;
+ status = "okay";
+ dma-noncoherent;
+ };
+
+ pvt@0x50b00000 {
+ compatible = "eswin,eswin-pvt-cpu";
+ clocks = <0x03 0x25f>;
+ clock-names = "pvt_clk";
+ resets = <0x18 0x0b 0x01>;
+ reset-names = "pvt_rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x50b00000 0x00 0x10000>;
+ interrupts = <0x15d>;
+ interrupt-parent = <0x10>;
+ #thermal-sensor-cells = <0x00>;
+ status = "okay";
+ label = "pvt0";
+ phandle = <0x48>;
+ };
+
+ pvt@0x52360000 {
+ compatible = "eswin,eswin-pvt-ddr";
+ clocks = <0x03 0x260>;
+ clock-names = "pvt_clk";
+ resets = <0x18 0x0b 0x02>;
+ reset-names = "pvt_rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x52360000 0x00 0x20000>;
+ interrupts = <0x15e>;
+ interrupt-parent = <0x10>;
+ status = "okay";
+ label = "pvt1";
+ };
+
+ fan_control@50b50000 {
+ compatible = "eswin-fan-control";
+ reg = <0x00 0x50b50000 0x00 0x10000>;
+ clocks = <0x03 0x2a7>;
+ clock-names = "pclk";
+ resets = <0x18 0x0a 0x01>;
+ reset-names = "fan_rst";
+ interrupt-parent = <0x10>;
+ interrupt-names = "fanirq";
+ interrupts = <0x162>;
+ pulses-per-revolution = <0x02>;
+ pwm-minimum-period = <0x3e8>;
+ pwms = <0x2e 0x00 0x186a0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x2f>;
+ status = "okay";
+ label = "fan_control";
+ eswin,pwm_inverted;
+ };
+
+ i2c@50950000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x28e>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x01>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x50950000 0x00 0x8000>;
+ interrupts = <0x69>;
+ interrupt-parent = <0x10>;
+ status = "okay";
+
+ es8388-0@10 {
+ compatible = "eswin,es8388";
+ reg = <0x10>;
+ #sound-dai-cells = <0x00>;
+
+ port {
+
+ endpoint {
+ system-clock-frequency = <0xbb8000>;
+ remote-endpoint = <0x30>;
+ phandle = <0x34>;
+ };
+ };
+ };
+ };
+
+ i2c@50960000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x28f>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x02>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x50960000 0x00 0x10000>;
+ interrupts = <0x6a>;
+ interrupt-parent = <0x10>;
+ status = "okay";
+
+ es5430@f {
+ compatible = "einno,es5340";
+ reg = <0x0f>;
+ eswin,regulator_default-microvolt = <0xf4240>;
+ eswin,regulator_label = "supply vdd1\0npu vdd1\0npu current1\0npu temperature1";
+ label = "npu_vdd";
+
+ regulators {
+
+ npu_svcc {
+ regulator-name = "NPU_SVCC";
+ regulator-min-microvolt = <0xaae60>;
+ regulator-max-microvolt = <0x10c8e0>;
+ regulator-min-microamp = <0x1312d00>;
+ regulator-max-microamp = <0x2625a00>;
+ regulator-ov-protection-microvolt = <0x10c8e0>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+
+ i2c@50970000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x290>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x04>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x50970000 0x00 0x8000>;
+ interrupts = <0x6b>;
+ interrupt-parent = <0x10>;
+ status = "disabled";
+ };
+
+ i2c@50980000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x291>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x08>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x50980000 0x00 0x8000>;
+ interrupts = <0x6c>;
+ interrupt-parent = <0x10>;
+ status = "okay";
+ };
+
+ i2c@50990000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x292>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x10>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x50990000 0x00 0x8000>;
+ interrupts = <0x6d>;
+ interrupt-parent = <0x10>;
+ status = "disabled";
+ };
+
+ i2c@509a0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x293>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x20>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x509a0000 0x00 0x8000>;
+ interrupts = <0x6e>;
+ interrupt-parent = <0x10>;
+ status = "disabled";
+ };
+
+ i2c@509b0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x294>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x40>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x509b0000 0x00 0x8000>;
+ interrupts = <0x6f>;
+ interrupt-parent = <0x10>;
+ status = "disabled";
+ };
+
+ i2c@509c0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x295>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x80>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x509c0000 0x00 0x8000>;
+ interrupts = <0x70>;
+ interrupt-parent = <0x10>;
+ status = "disabled";
+ };
+
+ i2c@509d0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x296>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x100>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x509d0000 0x00 0x8000>;
+ interrupts = <0x71>;
+ interrupt-parent = <0x10>;
+ status = "okay";
+
+ gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ gpio-line-names = "MIPI_CSI0_PWDN\0MIPI_CSI0_RESET\0MIPI_CSI1_FBC\0MIPI_CSI1_ENB\0MIPI_CSI1_RESET\0MIPI_CSI1_PWDN\0FREX_GP0\0\0MIPI_CSI0_ENB\0MIPI_CSI0_FBC\0FREX_GP2\0MIPI_CSI2_FBC\0MIPI_CSI2_ENB\0FREX_GP1\0MIPI_CSI2_RESET\0MIPI_CSI2_PWDN";
+ };
+
+ gpio@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ gpio-line-names = "MIPI_CSI3_PWDN\0MIPI_CSI3_RESET\0MIPI_CSI3_ENB\0MIPI_CSI3_FBC\0MIPI_CSI4_PWDN\0MIPI_CSI4_RESET\0MIPI_CSI4_ENB\0MIPI_CSI4_FBC\0MIPI_CSI5_FBC\0MIPI_CSI5_ENB\0MIPI_CSI5_RESET\0MIPI_CSI5_PWDN\0\0\0\0";
+ };
+ };
+
+ i2c@509e0000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x297>;
+ clock-names = "pclk";
+ resets = <0x18 0x09 0x200>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x509e0000 0x00 0x8000>;
+ interrupts = <0x72>;
+ interrupt-parent = <0x10>;
+ status = "disabled";
+ };
+
+ i2c@51830000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x29f>;
+ clock-names = "pclk";
+ resets = <0x18 0x26 0x01>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x51830000 0x00 0x8000>;
+ interrupts = <0x122>;
+ interrupt-parent = <0x10>;
+ eswin,i2c_dma = <0x31>;
+ dma-names = "rx\0tx";
+ dmas = <0x31 0x29 0xff 0x31 0x2a 0xff>;
+ status = "okay";
+ eswin,syscfg = <0x17 0x3c0 0x10>;
+
+ rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+
+ m41t11@68 {
+ compatible = "st,m41t11";
+ reg = <0x68>;
+ };
+ };
+
+ i2c@51838000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x2a0>;
+ clock-names = "pclk";
+ resets = <0x18 0x25 0x01>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x51838000 0x00 0x8000>;
+ interrupts = <0x123>;
+ interrupt-parent = <0x10>;
+ status = "okay";
+ i2c-sda-hold-time-ns = <0x40>;
+
+ ina226@45 {
+ compatible = "ti,ina226";
+ #io-channel-cells = <0x01>;
+ label = "cpu_vdd";
+ reg = <0x45>;
+ shunt-resistor = <0x3e8>;
+ };
+
+ ina226@44 {
+ compatible = "ti,ina226";
+ #io-channel-cells = <0x01>;
+ label = "soc_vdd";
+ reg = <0x44>;
+ shunt-resistor = <0x3e8>;
+ };
+
+ ina226@41 {
+ compatible = "ti,ina226";
+ #io-channel-cells = <0x01>;
+ label = "lpddr_vdd";
+ reg = <0x41>;
+ shunt-resistor = <0x3e8>;
+ };
+
+ ina226@48 {
+ compatible = "ti,ina226";
+ #io-channel-cells = <0x01>;
+ label = "dc_vdd";
+ reg = <0x48>;
+ shunt-resistor = <0x3e8>;
+ };
+ };
+
+ pinctrl@0x51600080 {
+ compatible = "eswin,eic7x-pinctrl\0syscon";
+ reg = <0x00 0x51600080 0x00 0x1fff80>;
+ status = "okay";
+ phandle = <0x1e>;
+
+ pwm0-default {
+ phandle = <0x32>;
+
+ mux {
+ groups = "pwm0_group";
+ function = "pwm0_func";
+ };
+ };
+
+ fan_tach-default {
+ phandle = <0x2f>;
+
+ mux {
+ groups = "fan_tach_group";
+ function = "fan_tach_func";
+ };
+ };
+
+ sdio0-default {
+
+ mux {
+ groups = "sdio0_group";
+ function = "sdio0_func";
+ };
+ };
+
+ sdio1-default {
+
+ mux {
+ groups = "sdio1_group";
+ function = "sdio1_func";
+ };
+ };
+
+ jtag0-default {
+
+ mux {
+ groups = "jtag0_group";
+ function = "jtag0_func";
+ };
+ };
+
+ jtag1-default {
+
+ mux {
+ groups = "jtag1_group";
+ function = "jtag1_func";
+ };
+ };
+
+ jtag2-default {
+
+ mux {
+ groups = "jtag2_group";
+ function = "jtag2_func";
+ };
+ };
+
+ pcie-default {
+
+ mux {
+ groups = "pcie_group";
+ function = "pcie_func";
+ };
+ };
+
+ hdmi-default {
+
+ mux {
+ groups = "hdmi_group";
+ function = "hdmi_func";
+ };
+ };
+
+ rgmii0-default {
+
+ mux {
+ groups = "rgmii0_group";
+ function = "rgmii0_func";
+ };
+ };
+
+ rgmii1-default {
+
+ mux {
+ groups = "rgmii1_group";
+ function = "rgmii1_func";
+ };
+ };
+
+ spi0-default {
+
+ mux {
+ groups = "spi0_group";
+ function = "spi0_func";
+ };
+ };
+
+ spi1-default {
+
+ mux {
+ groups = "spi1_group";
+ function = "spi1_func";
+ };
+ };
+
+ spi3-default {
+
+ mux {
+ groups = "spi3_group";
+ function = "spi3_func";
+ };
+ };
+
+ por_time_sel0-default {
+
+ mux {
+ groups = "por_time_sel0_group";
+ function = "por_time_sel0_func";
+ };
+ };
+
+ por_time_sel1-default {
+
+ mux {
+ groups = "por_time_sel1_group";
+ function = "por_time_sel1_func";
+ };
+ };
+
+ i2s0-default {
+
+ mux {
+ groups = "i2s0_group";
+ function = "i2s0_func";
+ };
+ };
+
+ i2s1-default {
+
+ mux {
+ groups = "i2s1_group";
+ function = "i2s1_func";
+ };
+ };
+
+ i2s2-default {
+
+ mux {
+ groups = "i2s2_group";
+ function = "i2s2_func";
+ };
+ };
+
+ usb0_pwren-default {
+
+ mux {
+ groups = "usb0_pwren_group";
+ function = "usb0_pwren_func";
+ };
+ };
+
+ usb1_pwren-default {
+
+ mux {
+ groups = "usb1_pwren_group";
+ function = "usb1_pwren_func";
+ };
+ };
+
+ i2c0-default {
+
+ mux {
+ groups = "i2c0_group";
+ function = "i2c0_func";
+ };
+ };
+
+ i2c1-default {
+
+ mux {
+ groups = "i2c1_group";
+ function = "i2c1_func";
+ };
+ };
+
+ i2c2-default {
+
+ mux {
+ groups = "i2c2_group";
+ function = "i2c2_func";
+ };
+ };
+
+ i2c3-default {
+
+ mux {
+ groups = "i2c3_group";
+ function = "i2c3_func";
+ };
+ };
+
+ i2c4-default {
+
+ mux {
+ groups = "i2c4_group";
+ function = "i2c4_func";
+ };
+ };
+
+ i2c5-default {
+
+ mux {
+ groups = "i2c5_group";
+ function = "i2c5_func";
+ };
+ };
+
+ i2c8-default {
+
+ mux {
+ groups = "i2c8_group";
+ function = "i2c8_func";
+ };
+ };
+
+ i2c10-default {
+
+ mux {
+ groups = "i2c10_group";
+ function = "i2c10_func";
+ };
+ };
+
+ i2c11-default {
+
+ mux {
+ groups = "i2c11_group";
+ function = "i2c11_func";
+ };
+ };
+
+ uart0-default {
+
+ mux {
+ groups = "uart0_group";
+ function = "uart0_func";
+ };
+ };
+
+ uart1-default {
+
+ mux {
+ groups = "uart1_group";
+ function = "uart1_func";
+ };
+ };
+
+ uart2-default {
+
+ mux {
+ groups = "uart2_group";
+ function = "uart2_func";
+ };
+ };
+
+ mipi_csi0-default {
+
+ mux {
+ groups = "mipi_csi0_group";
+ function = "mipi_csi0_func";
+ };
+ };
+
+ mipi_csi1-default {
+
+ mux {
+ groups = "mipi_csi1_group";
+ function = "mipi_csi1_func";
+ };
+ };
+
+ mipi_csi2-default {
+
+ mux {
+ groups = "mipi_csi2_group";
+ function = "mipi_csi2_func";
+ };
+ };
+
+ mipi_csi3-default {
+
+ mux {
+ groups = "mipi_csi3_group";
+ function = "mipi_csi3_func";
+ };
+ };
+
+ mipi_csi4-default {
+
+ mux {
+ groups = "mipi_csi4_group";
+ function = "mipi_csi4_func";
+ };
+ };
+
+ mipi_csi5-default {
+
+ mux {
+ groups = "mipi_csi5_group";
+ function = "mipi_csi5_func";
+ };
+ };
+
+ s_mode-default {
+
+ mux {
+ groups = "s_mode_group";
+ function = "s_mode_func";
+ };
+ };
+
+ ddr_refclk_sel-default {
+
+ mux {
+ groups = "ddr_refclk_sel_group";
+ function = "ddr_refclk_sel_func";
+ };
+ };
+
+ boot_sel-default {
+
+ mux {
+ groups = "boot_sel_group";
+ function = "boot_sel_func";
+ };
+ };
+
+ lpddr_ref_clk-default {
+
+ mux {
+ groups = "lpddr_ref_clk_group";
+ function = "lpddr_ref_clk_func";
+ };
+ };
+
+ spi2-default {
+ phandle = <0x29>;
+
+ mux1 {
+ groups = "spi2_clk_group";
+ function = "spi2_clk_func";
+ };
+
+ conf1 {
+ groups = "spi2_clk_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ bias-pull-down = <0x00>;
+ };
+
+ mux2 {
+ groups = "spi2_d0_group";
+ function = "spi2_d0_func";
+ };
+
+ conf2 {
+ groups = "spi2_d0_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ bias-pull-down = <0x00>;
+ };
+
+ mux3 {
+ groups = "spi2_d1_d2_d3_group";
+ function = "spi2_d1_d2_d3_func";
+ };
+
+ conf3 {
+ groups = "spi2_d1_d2_d3_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ bias-pull-down = <0x00>;
+ };
+
+ mux4 {
+ groups = "spi2_cs_group";
+ function = "spi2_cs_func";
+ };
+ };
+
+ sata_act_led-default {
+ phandle = <0x28>;
+
+ mux {
+ groups = "sata_act_led_group";
+ function = "sata_act_led_func";
+ };
+
+ conf {
+ groups = "sata_act_led_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ emmc_led_control-default {
+ phandle = <0x2b>;
+
+ mux {
+ groups = "emmc_led_control_group";
+ function = "emmc_led_control_func";
+ };
+
+ conf {
+ groups = "emmc_led_control_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ sd0_led_control-default {
+
+ mux {
+ groups = "sd0_led_control_group";
+ function = "sd0_led_control_func";
+ };
+ };
+
+ sd1_led_control-default {
+
+ mux {
+ groups = "sd1_led_control_group";
+ function = "sd1_led_control_func";
+ };
+ };
+
+ i2c6-default {
+
+ mux {
+ groups = "i2c6_group";
+ function = "i2c6_func";
+ };
+ };
+
+ i2c7-default {
+
+ mux {
+ groups = "i2c7_group";
+ function = "i2c7_func";
+ };
+ };
+
+ i2c9-default {
+
+ mux {
+ groups = "i2c9_group";
+ function = "i2c9_func";
+ };
+ };
+
+ pwm1-default {
+
+ mux {
+ groups = "pwm1_group";
+ function = "pwm1_func";
+ };
+ };
+
+ pwm2-default {
+
+ mux {
+ groups = "pwm2_group";
+ function = "pwm2_func";
+ };
+ };
+
+ mipi_csi_xtrig-default {
+
+ mux {
+ groups = "mipi_csi_xtrig_group";
+ function = "mipi_csi_xtrig_func";
+ };
+ };
+
+ uart3-default {
+
+ mux {
+ groups = "uart3_group";
+ function = "uart3_func";
+ };
+ };
+
+ uart4-default {
+
+ mux {
+ groups = "uart4_group";
+ function = "uart4_func";
+ };
+ };
+
+ gpio0-default {
+
+ mux {
+ groups = "gpio0_group";
+ function = "gpio0_func";
+ };
+
+ conf {
+ groups = "gpio0_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ };
+ };
+
+ gpio1-default {
+
+ mux {
+ groups = "gpio1_group";
+ function = "gpio1_func";
+ };
+ };
+
+ gpio2-default {
+
+ mux {
+ groups = "gpio2_group";
+ function = "gpio2_func";
+ };
+ };
+
+ gpio3-default {
+
+ mux {
+ groups = "gpio3_group";
+ function = "gpio3_func";
+ };
+ };
+
+ gpio4-default {
+
+ mux {
+ groups = "gpio4_group";
+ function = "gpio4_func";
+ };
+ };
+
+ gpio5-default {
+ phandle = <0x3e>;
+
+ mux {
+ groups = "gpio5_group";
+ function = "gpio5_func";
+ };
+
+ conf {
+ groups = "gpio5_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ };
+ };
+
+ gpio6-default {
+ phandle = <0x53>;
+
+ mux {
+ groups = "gpio6_group";
+ function = "gpio6_func";
+ };
+
+ conf {
+ groups = "gpio6_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio7-default {
+
+ mux {
+ groups = "gpio7_group";
+ function = "gpio7_func";
+ };
+
+ conf {
+ groups = "gpio7_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio8-default {
+
+ mux {
+ groups = "gpio8_group";
+ function = "gpio8_func";
+ };
+
+ conf {
+ groups = "gpio8_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ };
+ };
+
+ gpio9-default {
+
+ mux {
+ groups = "gpio9_group";
+ function = "gpio9_func";
+ };
+
+ conf {
+ groups = "gpio9_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ };
+ };
+
+ gpio10-default {
+
+ mux {
+ groups = "gpio10_group";
+ function = "gpio10_func";
+ };
+
+ conf {
+ groups = "gpio10_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ };
+ };
+
+ gpio11-default {
+
+ mux {
+ groups = "gpio11_group";
+ function = "gpio11_func";
+ };
+
+ conf {
+ groups = "gpio11_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ };
+ };
+
+ gpio12-default {
+
+ mux {
+ groups = "gpio12_group";
+ function = "gpio12_func";
+ };
+ };
+
+ gpio13-default {
+
+ mux {
+ groups = "gpio13_group";
+ function = "gpio13_func";
+ };
+ };
+
+ gpio14-default {
+
+ mux {
+ groups = "gpio14_group";
+ function = "gpio14_func";
+ };
+ };
+
+ gpio15-default {
+
+ mux {
+ groups = "gpio15_group";
+ function = "gpio15_func";
+ };
+ };
+
+ gpio16-default {
+ phandle = <0x20>;
+
+ mux {
+ groups = "gpio16_group";
+ function = "gpio16_func";
+ };
+
+ conf {
+ groups = "gpio16_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio17-default {
+
+ mux {
+ groups = "gpio17_group";
+ function = "gpio17_func";
+ };
+
+ conf {
+ groups = "gpio17_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio18-default {
+
+ mux {
+ groups = "gpio18_group";
+ function = "gpio18_func";
+ };
+
+ conf {
+ groups = "gpio18_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio19-default {
+
+ mux {
+ groups = "gpio19_group";
+ function = "gpio19_func";
+ };
+
+ conf {
+ groups = "gpio19_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio20-default {
+
+ mux {
+ groups = "gpio20_group";
+ function = "gpio20_func";
+ };
+
+ conf {
+ groups = "gpio20_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio21-default {
+
+ mux {
+ groups = "gpio21_group";
+ function = "gpio21_func";
+ };
+
+ conf {
+ groups = "gpio21_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio22-default {
+
+ mux {
+ groups = "gpio22_group";
+ function = "gpio22_func";
+ };
+ };
+
+ gpio23-default {
+
+ mux {
+ groups = "gpio23_group";
+ function = "gpio23_func";
+ };
+ };
+
+ gpio24-default {
+
+ mux {
+ groups = "gpio24_group";
+ function = "gpio24_func";
+ };
+ };
+
+ gpio25-default {
+
+ mux {
+ groups = "gpio25_group";
+ function = "gpio25_func";
+ };
+ };
+
+ gpio26-default {
+
+ mux {
+ groups = "gpio26_group";
+ function = "gpio26_func";
+ };
+ };
+
+ gpio27-default {
+
+ mux {
+ groups = "gpio27_group";
+ function = "gpio27_func";
+ };
+ };
+
+ gpio28-default {
+
+ mux {
+ groups = "gpio28_group";
+ function = "gpio28_func";
+ };
+
+ conf {
+ groups = "gpio28_group";
+ input-enable = <0x01>;
+ bias-pull-up = <0x01>;
+ };
+ };
+
+ gpio29-default {
+
+ mux {
+ groups = "gpio29_group";
+ function = "gpio29_func";
+ };
+ };
+
+ gpio30-default {
+
+ mux {
+ groups = "gpio30_group";
+ function = "gpio30_func";
+ };
+ };
+
+ gpio31-default {
+
+ mux {
+ groups = "gpio31_group";
+ function = "gpio31_func";
+ };
+ };
+
+ gpio32-default {
+
+ mux {
+ groups = "gpio32_group";
+ function = "gpio32_func";
+ };
+ };
+
+ gpio33-default {
+
+ mux {
+ groups = "gpio33_group";
+ function = "gpio33_func";
+ };
+ };
+
+ gpio34-default {
+
+ mux {
+ groups = "gpio34_group";
+ function = "gpio34_func";
+ };
+ };
+
+ gpio35-default {
+
+ mux {
+ groups = "gpio35_group";
+ function = "gpio35_func";
+ };
+
+ conf {
+ groups = "gpio35_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio36-default {
+
+ mux {
+ groups = "gpio36_group";
+ function = "gpio36_func";
+ };
+
+ conf {
+ groups = "gpio36_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio37-default {
+
+ mux {
+ groups = "gpio37_group";
+ function = "gpio37_func";
+ };
+
+ conf {
+ groups = "gpio37_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio38-default {
+
+ mux {
+ groups = "gpio38_group";
+ function = "gpio38_func";
+ };
+
+ conf {
+ groups = "gpio38_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio39-default {
+
+ mux {
+ groups = "gpio39_group";
+ function = "gpio39_func";
+ };
+
+ conf {
+ groups = "gpio39_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio40-default {
+
+ mux {
+ groups = "gpio40_group";
+ function = "gpio40_func";
+ };
+
+ conf {
+ groups = "gpio40_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio41-default {
+
+ mux {
+ groups = "gpio41_group";
+ function = "gpio41_func";
+ };
+ };
+
+ gpio42-default {
+
+ mux {
+ groups = "gpio42_group";
+ function = "gpio42_func";
+ };
+
+ conf {
+ groups = "gpio42_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio43-default {
+
+ mux {
+ groups = "gpio43_group";
+ function = "gpio43_func";
+ };
+ };
+
+ gpio44-default {
+
+ mux {
+ groups = "gpio44_group";
+ function = "gpio44_func";
+ };
+ };
+
+ gpio45-default {
+
+ mux {
+ groups = "gpio45_group";
+ function = "gpio45_func";
+ };
+ };
+
+ gpio46-default {
+
+ mux {
+ groups = "gpio46_group";
+ function = "gpio46_func";
+ };
+
+ conf {
+ groups = "gpio46_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio47-default {
+
+ mux {
+ groups = "gpio47_group";
+ function = "gpio47_func";
+ };
+
+ conf {
+ groups = "gpio47_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio48-default {
+
+ mux {
+ groups = "gpio48_group";
+ function = "gpio48_func";
+ };
+ };
+
+ gpio49-default {
+
+ mux {
+ groups = "gpio49_group";
+ function = "gpio49_func";
+ };
+ };
+
+ gpio50-default {
+
+ mux {
+ groups = "gpio50_group";
+ function = "gpio50_func";
+ };
+ };
+
+ gpio51-default {
+
+ mux {
+ groups = "gpio51_group";
+ function = "gpio51_func";
+ };
+ };
+
+ gpio52-default {
+
+ mux {
+ groups = "gpio52_group";
+ function = "gpio52_func";
+ };
+
+ conf {
+ groups = "gpio52_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio53-default {
+
+ mux {
+ groups = "gpio53_group";
+ function = "gpio53_func";
+ };
+
+ conf {
+ groups = "gpio53_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio54-default {
+
+ mux {
+ groups = "gpio54_group";
+ function = "gpio54_func";
+ };
+ };
+
+ gpio55-default {
+
+ mux {
+ groups = "gpio55_group";
+ function = "gpio55_func";
+ };
+ };
+
+ gpio56-default {
+
+ mux {
+ groups = "gpio56_group";
+ function = "gpio56_func";
+ };
+ };
+
+ gpio57-default {
+
+ mux {
+ groups = "gpio57_group";
+ function = "gpio57_func";
+ };
+ };
+
+ gpio58-default {
+
+ mux {
+ groups = "gpio58_group";
+ function = "gpio58_func";
+ };
+ };
+
+ gpio59-default {
+
+ mux {
+ groups = "gpio59_group";
+ function = "gpio59_func";
+ };
+ };
+
+ gpio60-default {
+
+ mux {
+ groups = "gpio60_group";
+ function = "gpio60_func";
+ };
+ };
+
+ gpio61-default {
+
+ mux {
+ groups = "gpio61_group";
+ function = "gpio61_func";
+ };
+ };
+
+ gpio62-default {
+
+ mux {
+ groups = "gpio62_group";
+ function = "gpio62_func";
+ };
+ };
+
+ gpio63-default {
+
+ mux {
+ groups = "gpio63_group";
+ function = "gpio63_func";
+ };
+ };
+
+ gpio64-default {
+
+ mux {
+ groups = "gpio64_group";
+ function = "gpio64_func";
+ };
+
+ conf {
+ groups = "gpio64_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio65-default {
+
+ mux {
+ groups = "gpio65_group";
+ function = "gpio65_func";
+ };
+
+ conf {
+ groups = "gpio65_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio66-default {
+
+ mux {
+ groups = "gpio66_group";
+ function = "gpio66_func";
+ };
+
+ conf {
+ groups = "gpio66_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio67-default {
+
+ mux {
+ groups = "gpio67_group";
+ function = "gpio67_func";
+ };
+
+ conf {
+ groups = "gpio67_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio68-default {
+
+ mux {
+ groups = "gpio68_group";
+ function = "gpio68_func";
+ };
+ };
+
+ gpio69-default {
+
+ mux {
+ groups = "gpio69_group";
+ function = "gpio69_func";
+ };
+ };
+
+ gpio70-default {
+
+ mux {
+ groups = "gpio70_group";
+ function = "gpio70_func";
+ };
+ };
+
+ gpio71-default {
+
+ mux {
+ groups = "gpio71_group";
+ function = "gpio71_func";
+ };
+ };
+
+ gpio72-default {
+
+ mux {
+ groups = "gpio72_group";
+ function = "gpio72_func";
+ };
+ };
+
+ gpio73-default {
+
+ mux {
+ groups = "gpio73_group";
+ function = "gpio73_func";
+ };
+ };
+
+ gpio74-default {
+
+ mux {
+ groups = "gpio74_group";
+ function = "gpio74_func";
+ };
+ };
+
+ gpio75-default {
+
+ mux {
+ groups = "gpio75_group";
+ function = "gpio75_func";
+ };
+ };
+
+ gpio76-default {
+
+ mux {
+ groups = "gpio76_group";
+ function = "gpio76_func";
+ };
+ };
+
+ gpio77-default {
+
+ mux {
+ groups = "gpio77_group";
+ function = "gpio77_func";
+ };
+ };
+
+ gpio78-default {
+
+ mux {
+ groups = "gpio78_group";
+ function = "gpio78_func";
+ };
+ };
+
+ gpio79-default {
+
+ mux {
+ groups = "gpio79_group";
+ function = "gpio79_func";
+ };
+ };
+
+ gpio80-default {
+
+ mux {
+ groups = "gpio80_group";
+ function = "gpio80_func";
+ };
+ };
+
+ gpio81-default {
+
+ mux {
+ groups = "gpio81_group";
+ function = "gpio81_func";
+ };
+ };
+
+ gpio82-default {
+
+ mux {
+ groups = "gpio82_group";
+ function = "gpio82_func";
+ };
+ };
+
+ gpio83-default {
+
+ mux {
+ groups = "gpio83_group";
+ function = "gpio83_func";
+ };
+ };
+
+ gpio84-default {
+
+ mux {
+ groups = "gpio84_group";
+ function = "gpio84_func";
+ };
+ };
+
+ gpio85-default {
+
+ mux {
+ groups = "gpio85_group";
+ function = "gpio85_func";
+ };
+ };
+
+ gpio86-default {
+
+ mux {
+ groups = "gpio86_group";
+ function = "gpio86_func";
+ };
+ };
+
+ gpio87-default {
+
+ mux {
+ groups = "gpio87_group";
+ function = "gpio87_func";
+ };
+ };
+
+ gpio88-default {
+
+ mux {
+ groups = "gpio88_group";
+ function = "gpio88_func";
+ };
+ };
+
+ gpio89-default {
+
+ mux {
+ groups = "gpio89_group";
+ function = "gpio89_func";
+ };
+ };
+
+ gpio90-default {
+
+ mux {
+ groups = "gpio90_group";
+ function = "gpio90_func";
+ };
+ };
+
+ gpio91-default {
+
+ mux {
+ groups = "gpio91_group";
+ function = "gpio91_func";
+ };
+ };
+
+ gpio92-default {
+
+ mux {
+ groups = "gpio92_group";
+ function = "gpio92_func";
+ };
+
+ conf {
+ groups = "gpio92_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio93-default {
+
+ mux {
+ groups = "gpio93_group";
+ function = "gpio93_func";
+ };
+
+ conf {
+ groups = "gpio93_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio94-default {
+ phandle = <0x1c>;
+
+ mux {
+ groups = "gpio94_group";
+ function = "gpio94_func";
+ };
+
+ conf {
+ groups = "gpio94_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio95-default {
+
+ mux {
+ groups = "gpio95_group";
+ function = "gpio95_func";
+ };
+ };
+
+ gpio96-default {
+
+ mux {
+ groups = "gpio96_group";
+ function = "gpio96_func";
+ };
+ };
+
+ gpio97-default {
+
+ mux {
+ groups = "gpio97_group";
+ function = "gpio97_func";
+ };
+ };
+
+ gpio98-default {
+
+ mux {
+ groups = "gpio98_group";
+ function = "gpio98_func";
+ };
+ };
+
+ gpio99-default {
+
+ mux {
+ groups = "gpio99_group";
+ function = "gpio99_func";
+ };
+ };
+
+ gpio100-default {
+
+ mux {
+ groups = "gpio100_group";
+ function = "gpio100_func";
+ };
+ };
+
+ gpio101-default {
+
+ mux {
+ groups = "gpio101_group";
+ function = "gpio101_func";
+ };
+ };
+
+ gpio102-default {
+
+ mux {
+ groups = "gpio102_group";
+ function = "gpio102_func";
+ };
+ };
+
+ gpio103-default {
+
+ mux {
+ groups = "gpio103_group";
+ function = "gpio103_func";
+ };
+ };
+
+ gpio104-default {
+
+ mux {
+ groups = "gpio104_group";
+ function = "gpio104_func";
+ };
+ };
+
+ gpio105-default {
+
+ mux {
+ groups = "gpio105_group";
+ function = "gpio105_func";
+ };
+ };
+
+ gpio106-default {
+
+ mux {
+ groups = "gpio106_group";
+ function = "gpio106_func";
+ };
+
+ conf {
+ groups = "gpio106_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio107-default {
+ phandle = <0x50>;
+
+ mux {
+ groups = "gpio107_group";
+ function = "gpio107_func";
+ };
+
+ conf {
+ groups = "gpio107_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio108-default {
+ phandle = <0x51>;
+
+ mux {
+ groups = "gpio108_group";
+ function = "gpio108_func";
+ };
+
+ conf {
+ groups = "gpio108_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio109-default {
+ phandle = <0x52>;
+
+ mux {
+ groups = "gpio109_group";
+ function = "gpio109_func";
+ };
+
+ conf {
+ groups = "gpio109_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio110-default {
+
+ mux {
+ groups = "gpio110_group";
+ function = "gpio110_func";
+ };
+
+ conf {
+ groups = "gpio110_group";
+ input-enable = <0x01>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio111-default {
+ phandle = <0x3f>;
+
+ mux {
+ groups = "gpio111_group";
+ function = "gpio111_func";
+ };
+
+ conf {
+ groups = "gpio111_group";
+ input-enable = <0x00>;
+ bias-pull-up = <0x01>;
+ };
+ };
+
+ csi_mon_out-default {
+
+ mux {
+ groups = "csi_mon_out_group";
+ function = "csi_mon_out_func";
+ };
+ };
+
+ csi_ocla_clk-default {
+
+ mux {
+ groups = "csi_ocla_clk_group";
+ function = "csi_ocla_clk_func";
+ };
+ };
+
+ csi_mon_out_valid-default {
+
+ mux {
+ groups = "csi_mon_out_valid_group";
+ function = "csi_mon_out_valid_func";
+ };
+ };
+
+ csi_parity_error-default {
+
+ mux {
+ groups = "csi_parity_error_group";
+ function = "csi_parity_error_func";
+ };
+ };
+
+ csi_dtb_out-default {
+
+ mux {
+ groups = "csi_dtb_out_group";
+ function = "csi_dtb_out_func";
+ };
+ };
+
+ csi_phy_sel-default {
+
+ mux {
+ groups = "csi_phy_sel_group";
+ function = "csi_phy_sel_func";
+ };
+ };
+
+ vc_g2d0_debug_out-default {
+
+ mux {
+ groups = "vc_g2d0_debug_out_group";
+ function = "vc_g2d0_debug_out_func";
+ };
+ };
+
+ vc_g2d1_debug_out-default {
+
+ mux {
+ groups = "vc_g2d1_debug_out_group";
+ function = "vc_g2d1_debug_out_func";
+ };
+ };
+
+ sata_mpll_clk-default {
+
+ mux {
+ groups = "sata_mpll_clk_group";
+ function = "sata_mpll_clk_func";
+ };
+ };
+
+ sata_ref_repeat_clk_m-default {
+
+ mux {
+ groups = "sata_ref_repeat_clk_m_group";
+ function = "sata_ref_repeat_clk_m_func";
+ };
+ };
+
+ sata_ref_repeat_clk_p-default {
+
+ mux {
+ groups = "sata_ref_repeat_clk_p_group";
+ function = "sata_ref_repeat_clk_p_func";
+ };
+ };
+ };
+
+ gpio@51600000 {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x00 0x51600000 0x00 0x80>;
+ status = "okay";
+
+ gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ ngpios = <0x20>;
+ reg = <0x00>;
+ interrupt-parent = <0x10>;
+ interrupt-controller;
+ #interrupt-cells = <0x02>;
+ interrupts = <0x12f 0x130 0x131 0x132 0x133 0x134 0x135 0x136 0x137 0x138 0x139 0x13a 0x13b 0x13c 0x13d 0x13e 0x13f 0x140 0x141 0x142 0x143 0x144 0x145 0x146 0x147 0x148 0x149 0x14a 0x14b 0x14c 0x14d 0x14e>;
+ phandle = <0x21>;
+ };
+
+ gpio-port@1 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ ngpios = <0x20>;
+ reg = <0x01>;
+ };
+
+ gpio-port@2 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ ngpios = <0x20>;
+ reg = <0x02>;
+ phandle = <0x1d>;
+ };
+
+ gpio-port@3 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ ngpios = <0x10>;
+ reg = <0x03>;
+ phandle = <0x2a>;
+ };
+ };
+
+ pwm@0x50818000 {
+ compatible = "eswin,pwm-eswin";
+ #pwm-cells = <0x02>;
+ reg = <0x00 0x50818000 0x00 0x4000>;
+ clock-names = "pclk";
+ clocks = <0x03 0x2a6>;
+ clock-frequency = <0xbebc200>;
+ resets = <0x18 0x0f 0x01>;
+ reset-names = "rst";
+ pinctrl-names = "default";
+ pinctrl-0 = <0x32>;
+ status = "okay";
+ phandle = <0x2e>;
+ };
+
+ watchdog@0x50800000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x00 0x50800000 0x00 0x4000>;
+ clocks = <0x03 0x298>;
+ clock-names = "pclk";
+ resets = <0x18 0x11 0x01>;
+ reset-names = "rst";
+ interrupts = <0x57>;
+ interrupt-parent = <0x10>;
+ status = "disabled";
+ };
+
+ watchdog@0x50804000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x00 0x50804000 0x00 0x4000>;
+ clocks = <0x03 0x299>;
+ clock-names = "pclk";
+ resets = <0x18 0x11 0x02>;
+ reset-names = "rst";
+ interrupts = <0x58>;
+ interrupt-parent = <0x10>;
+ status = "disabled";
+ };
+
+ watchdog@0x50808000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x00 0x50808000 0x00 0x4000>;
+ clocks = <0x03 0x29a>;
+ clock-names = "pclk";
+ resets = <0x18 0x11 0x04>;
+ reset-names = "rst";
+ interrupts = <0x59>;
+ interrupt-parent = <0x10>;
+ status = "disabled";
+ };
+
+ watchdog@0x5080c000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x00 0x5080c000 0x00 0x4000>;
+ clocks = <0x03 0x29b>;
+ clock-names = "pclk";
+ resets = <0x18 0x11 0x08>;
+ reset-names = "rst";
+ interrupts = <0x5a>;
+ interrupt-parent = <0x10>;
+ status = "disabled";
+ };
+
+ timer@0x51840000 {
+ compatible = "eswin,eswin-timer";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x51840000 0x00 0x8000>;
+ perf_count = <0x07>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x159>;
+ clock-names = "pclk\0timer_aclk";
+ clocks = <0x03 0x26c 0x03 0x268>;
+ resets = <0x18 0x30 0x01 0x18 0x30 0x02 0x18 0x30 0x04 0x18 0x30 0x08 0x18 0x30 0x10 0x18 0x30 0x20 0x18 0x30 0x40 0x18 0x30 0x80 0x18 0x30 0x100>;
+ reset-names = "trst0\0trst1\0trst2\0trst3\0trst4\0trst5\0trst6\0trst7\0prst";
+ status = "okay";
+ };
+
+ timer@0x51848000 {
+ compatible = "eswin,eswin-timer";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x51848000 0x00 0x8000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x15a>;
+ clock-names = "pclk\0timer_aclk";
+ clocks = <0x03 0x26d 0x03 0x269>;
+ resets = <0x18 0x31 0x01 0x18 0x31 0x02 0x18 0x31 0x04 0x18 0x31 0x08 0x18 0x31 0x10 0x18 0x31 0x20 0x18 0x31 0x40 0x18 0x31 0x80 0x18 0x31 0x100>;
+ reset-names = "trst0\0trst1\0trst2\0trst3\0trst4\0trst5\0trst6\0trst7\0prst";
+ status = "okay";
+ };
+
+ timer@0x51850000 {
+ compatible = "eswin,eswin-timer";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x51850000 0x00 0x8000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x15b>;
+ clock-names = "pclk\0timer_aclk";
+ clocks = <0x03 0x26e 0x03 0x26a>;
+ resets = <0x18 0x32 0x01 0x18 0x32 0x02 0x18 0x32 0x04 0x18 0x32 0x08 0x18 0x32 0x10 0x18 0x32 0x20 0x18 0x32 0x40 0x18 0x32 0x80 0x18 0x32 0x100>;
+ reset-names = "trst0\0trst1\0trst2\0trst3\0trst4\0trst5\0trst6\0trst7\0prst";
+ status = "okay";
+ };
+
+ timer@0x51858000 {
+ compatible = "eswin,eswin-timer";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x51858000 0x00 0x8000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x15c>;
+ clock-names = "pclk\0timer_aclk\0timer3_clk8";
+ clocks = <0x03 0x26f 0x03 0x26b 0x03 0x270>;
+ resets = <0x18 0x33 0x01 0x18 0x33 0x02 0x18 0x33 0x04 0x18 0x33 0x08 0x18 0x33 0x10 0x18 0x33 0x20 0x18 0x33 0x40 0x18 0x33 0x80 0x18 0x33 0x100>;
+ reset-names = "trst0\0trst1\0trst2\0trst3\0trst4\0trst5\0trst6\0trst7\0prst";
+ status = "okay";
+ };
+
+ rtc@51818000 {
+ compatible = "eswin,win2030-rtc";
+ reg = <0x00 0x51818000 0x00 0x400>;
+ eswin,syscfg = <0x17 0x3c0>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x124>;
+ clocks = <0x03 0x272>;
+ clock-names = "rtcclk";
+ clock-frequency = <0x3d09>;
+ resets = <0x18 0x34 0x01>;
+ reset-names = "rtcrst";
+ status = "okay";
+ };
+
+ i2s0@50200000 {
+ compatible = "snps,i2s";
+ clocks = <0x03 0x250>;
+ clock-names = "mclk";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ #sound-dai-cells = <0x00>;
+ reg = <0x00 0x50200000 0x00 0x10000>;
+ dma-names = "rx\0tx";
+ dmas = <0x31 0x04 0x00 0x31 0x05 0x00>;
+ vo_mclk_sel,syscrg = <0x16 0x1bc>;
+ resets = <0x18 0x22 0x01 0x18 0x22 0x02 0x18 0x21 0x02>;
+ reset-names = "i2srst\0i2sprst\0voprst";
+ dma-noncoherent;
+ status = "okay";
+
+ port {
+ phandle = <0x36>;
+
+ endpoint {
+ remote-endpoint = <0x33>;
+ dai-format = "i2s";
+ phandle = <0x42>;
+ };
+ };
+ };
+
+ i2s1@50210000 {
+ compatible = "snps,i2s";
+ clocks = <0x03 0x250>;
+ clock-names = "mclk";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ #sound-dai-cells = <0x00>;
+ reg = <0x00 0x50210000 0x00 0x10000>;
+ dma-names = "rx\0tx";
+ dmas = <0x31 0x02 0x01 0x31 0x03 0x01>;
+ vo_mclk_sel,syscrg = <0x16 0x1bc>;
+ resets = <0x18 0x22 0x01 0x18 0x22 0x02 0x18 0x21 0x02>;
+ reset-names = "i2srst\0i2sprst\0voprst";
+ dma-noncoherent;
+ status = "okay";
+
+ port {
+ phandle = <0x35>;
+
+ endpoint {
+ remote-endpoint = <0x34>;
+ dai-format = "i2s";
+ phandle = <0x30>;
+ };
+ };
+ };
+
+ i2s2@50220000 {
+ compatible = "snps,i2s";
+ clocks = <0x03 0x250>;
+ clock-names = "mclk";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ #sound-dai-cells = <0x00>;
+ reg = <0x00 0x50220000 0x00 0x10000>;
+ dma-names = "rx\0tx";
+ dmas = <0x31 0x00 0x02 0x31 0x01 0x02>;
+ vo_mclk_sel,syscrg = <0x16 0x1bc>;
+ resets = <0x18 0x22 0x01 0x18 0x22 0x02 0x18 0x21 0x02>;
+ reset-names = "i2srst\0i2sprst\0voprst";
+ dma-noncoherent;
+ status = "disabled";
+ };
+
+ graphcard0 {
+ compatible = "audio-graph-card";
+ status = "okay";
+ label = "Analog Audio-0";
+ dais = <0x35>;
+ };
+
+ graphcard1 {
+ compatible = "audio-graph-card";
+ status = "okay";
+ label = "HDMI Audio";
+ dais = <0x36>;
+ };
+
+ graphcard2 {
+ compatible = "audio-graph-card";
+ status = "disabled";
+ };
+
+ display-subsystem@0 {
+ compatible = "eswin,display-subsystem";
+ ports = <0x37>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ };
+
+ dvb-subsystem {
+ compatible = "amlogic,dvb_widgets";
+ status = "disabled";
+ };
+
+ display_control@502c0000 {
+ compatible = "eswin,dc";
+ reg = <0x00 0x502c0000 0x00 0x100 0x00 0x502c0180 0x00 0x700 0x00 0x502c1400 0x00 0x1400>;
+ interrupt-parent = <0x10>;
+ interrupts = <0xee>;
+ clocks = <0x03 0x24d 0x03 0x24f 0x03 0x24c 0x03 0x04 0x03 0x2a>;
+ clock-names = "cfg_clk\0pix_clk\0axi_clk\0spll0_fout1\0vo_mux";
+ resets = <0x18 0x23 0x01 0x18 0x23 0x02 0x18 0x23 0x04 0x18 0x23 0x08>;
+ reset-names = "vo_arst\0vo_prst\0dc_arst\0dc_prst";
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ port {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ phandle = <0x37>;
+
+ endpoint@0 {
+ reg = <0x00>;
+ remote-endpoint = <0x38>;
+ phandle = <0x3c>;
+ };
+
+ endpoint@1 {
+ reg = <0x01>;
+ remote-endpoint = <0x39>;
+ phandle = <0x3b>;
+ };
+
+ endpoint@2 {
+ reg = <0x02>;
+ remote-endpoint = <0x3a>;
+ phandle = <0x41>;
+ };
+ };
+ };
+
+ es_wb@0 {
+ compatible = "eswin,virtual_display";
+ bpp = [08];
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ port {
+
+ endpoint {
+ remote-endpoint = <0x3b>;
+ phandle = <0x39>;
+ };
+ };
+ };
+
+ dsi-output@0 {
+ compatible = "eswin,dsi-encoder";
+ numa-node-id = <0x00>;
+ status = "okay";
+ };
+
+ mipi_dsi@50270000 {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ compatible = "eswin,dsi";
+ reg = <0x00 0x50270000 0x00 0x10000>;
+ clocks = <0x03 0x201>;
+ clock-names = "pclk";
+ resets = <0x18 0x21 0x01>;
+ reset-names = "phyrstn";
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ ports {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ port@0 {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00>;
+
+ endpoint {
+ remote-endpoint = <0x3c>;
+ phandle = <0x38>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x01>;
+
+ endpoint {
+ remote-endpoint = <0x3d>;
+ phandle = <0x40>;
+ };
+ };
+ };
+
+ dsi_panel@0 {
+ compatible = "eswin,generic-panel";
+ reg = <0x00>;
+ dsi,format = <0x00>;
+ dsi,lanes = <0x04>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <0x3e 0x3f>;
+ backlight0-gpios = <0x21 0x05 0x00>;
+ rst-gpios = <0x2a 0x0f 0x00>;
+
+ port {
+
+ endpoint {
+ remote-endpoint = <0x40>;
+ phandle = <0x3d>;
+ };
+ };
+ };
+ };
+
+ dctest@502c0000 {
+ compatible = "eswin,dc";
+ reg = <0x00 0x502c0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0xee>;
+ status = "disabled";
+ };
+
+ hdmi@502a0000 {
+ compatible = "eswin,eswin-dw-hdmi";
+ reg = <0x00 0x502a0000 0x00 0x20000>;
+ pinctrl-names = "default";
+ interrupt-parent = <0x10>;
+ interrupts = <0x112>;
+ clocks = <0x03 0x24d 0x03 0x252 0x03 0x251>;
+ clock-names = "iahb\0cec\0isfr";
+ reg-io-width = <0x04>;
+ ddc-i2c-scl-high-time-ns = <0x1264>;
+ ddc-i2c-scl-low-time-ns = <0x1334>;
+ #sound-dai-cells = <0x00>;
+ resets = <0x18 0x21 0x08 0x18 0x21 0x10 0x18 0x21 0x20>;
+ reset-names = "prstn\0phyrstn\0rstn";
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ ports {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ port@0 {
+ reg = <0x00>;
+
+ endpoint@0 {
+ remote-endpoint = <0x41>;
+ phandle = <0x3a>;
+ };
+ };
+
+ port@2 {
+ reg = <0x02>;
+
+ endpoint@1 {
+ system-clock-frequency = <0xbb8000>;
+ remote-endpoint = <0x42>;
+ phandle = <0x33>;
+ };
+ };
+ };
+ };
+
+ hdmi-hdcp2@50290000 {
+ compatible = "eswin,dw-hdmi-hdcp2";
+ reg = <0x00 0x50290000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x113>;
+ clocks = <0x03 0x24c 0x03 0x24e>;
+ clock-names = "aclk\0iesmclk";
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ status = "okay";
+ };
+
+ usb0@50480000 {
+ compatible = "eswin,win2030-dwc3";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ clocks = <0x03 0x10e 0x03 0x221 0x03 0x222>;
+ clock-names = "suspend\0aclk\0cfg_clk";
+ eswin,hsp_sp_csr = <0x1a 0x800 0x808 0x83c 0x840>;
+ resets = <0x18 0x07 0x8000>;
+ reset-names = "vaux";
+ ranges;
+ status = "okay";
+
+ dwc3@50480000 {
+ compatible = "snps,dwc3";
+ reg = <0x00 0x50480000 0x00 0x10000>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x55>;
+ interrupt-names = "peripheral";
+ dr_mode = "host";
+ phy_type = "utmi";
+ maximum-speed = "super-speed";
+ iommus = <0x19 0x0a>;
+ eswin,hsp_sp_csr = <0x1a 0x1044>;
+ dma-ranges = <0x00 0x00 0x00 0xc0000000 0x200 0x00>;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,parkmode-disable-ss-quirk;
+ status = "okay";
+ numa-node-id = <0x00>;
+ tbus = <0x02>;
+ dma-noncoherent;
+ };
+ };
+
+ usb1@50490000 {
+ compatible = "eswin,win2030-dwc3";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ clocks = <0x03 0x10f 0x03 0x221 0x03 0x222>;
+ clock-names = "suspend\0aclk\0cfg_clk";
+ eswin,hsp_sp_csr = <0x1a 0x900 0x908 0x93c 0x940>;
+ resets = <0x18 0x07 0x10000>;
+ reset-names = "vaux";
+ ranges;
+ status = "okay";
+
+ dwc3@50490000 {
+ compatible = "snps,dwc3";
+ reg = <0x00 0x50490000 0x00 0x10000>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x56>;
+ interrupt-names = "host";
+ dr_mode = "host";
+ phy_type = "utmi";
+ maximum-speed = "super-speed";
+ iommus = <0x19 0x0b>;
+ eswin,hsp_sp_csr = <0x1a 0x1048>;
+ dma-ranges = <0x00 0x00 0x00 0xc0000000 0x200 0x00>;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,parkmode-disable-ss-quirk;
+ status = "okay";
+ numa-node-id = <0x00>;
+ tbus = <0x02>;
+ dma-noncoherent;
+ };
+ };
+
+ vi_common_top_csr@0x51030000 {
+ compatible = "esw,vi-common-csr\0syscon";
+ clocks = <0x03 0x23f 0x03 0x241 0x03 0x243 0x03 0x240 0x03 0x24b 0x03 0x24a 0x03 0x244 0x03 0x245 0x03 0x246 0x03 0x247 0x03 0x248 0x03 0x249 0x03 0x27 0x03 0x28 0x03 0x29 0x03 0x04 0x03 0x0d>;
+ clock-names = "aclk\0cfg_clk\0isp_aclk\0dvp_clk\0phy_cfg\0phy_escclk\0sht0\0sht1\0sht2\0sht3\0sht4\0sht5\0aclk_mux\0dvp_mux\0isp_mux\0spll0_fout1\0vpll_fout1";
+ resets = <0x18 0x1c 0x01 0x18 0x1c 0x02 0x18 0x1e 0x01 0x18 0x1f 0x01 0x18 0x1d 0x01 0x18 0x20 0x01 0x18 0x20 0x02 0x18 0x20 0x04 0x18 0x20 0x08 0x18 0x20 0x10 0x18 0x20 0x20>;
+ reset-names = "axi\0cfg\0isp0\0isp1\0dvp\0sht0\0sht1\0sht2\0sht3\0sht4\0sht5";
+ interrupt-parent = <0x10>;
+ interrupts = <0x170 0x171 0x172 0x173 0x174 0x175 0x176 0x177>;
+ id = <0x00>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x51030000 0x00 0x10000>;
+ phandle = <0x43>;
+ };
+
+ isp@0x51000000 {
+ compatible = "esw,win2030-isp";
+ reg = <0x00 0x51000000 0x00 0x10000>;
+ interrupts = <0x15 0x13 0x14>;
+ interrupt-parent = <0x10>;
+ id = <0x00>;
+ #size-cells = <0x02>;
+ dma-ranges = <0x00 0x20000000 0x00 0x80000000 0x00 0x40000000>;
+ iommus = <0x19 0x06>;
+ tbus = <0x00>;
+ eswin,vi_top_csr = <0x43 0x1000>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ };
+
+ isp@0x51010000 {
+ compatible = "esw,win2030-isp";
+ reg = <0x00 0x51010000 0x00 0x10000>;
+ interrupts = <0x18 0x16 0x17>;
+ interrupt-parent = <0x10>;
+ id = <0x01>;
+ #size-cells = <0x02>;
+ dma-ranges = <0x00 0x20000000 0x00 0x80000000 0x00 0x40000000>;
+ iommus = <0x19 0x06>;
+ tbus = <0x00>;
+ eswin,vi_top_csr = <0x43 0x1004>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ };
+
+ dewarp@51020000 {
+ compatible = "eswin,dewarp";
+ clocks = <0x03 0x23f 0x03 0x241 0x03 0x242 0x03 0x27 0x03 0x54 0x03 0x04 0x03 0x0d>;
+ clock-names = "aclk\0cfg_clk\0dw_aclk\0aclk_mux\0dw_mux\0spll0_fout1\0vpll_fout1";
+ resets = <0x18 0x1c 0x01 0x18 0x1c 0x02 0x18 0x1c 0x04>;
+ reset-names = "axi\0cfg\0dwe";
+ interrupt-parent = <0x10>;
+ interrupts = <0x1a 0x19>;
+ #size-cells = <0x02>;
+ dma-ranges = <0x00 0x20000000 0x00 0x80000000 0x00 0x40000000>;
+ iommus = <0x19 0x08>;
+ tbus = <0x00>;
+ eswin,vi_top_csr = <0x43 0x1008>;
+ reg = <0x00 0x51020000 0x00 0xc00 0x00 0x51020c00 0x00 0x120>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ };
+
+ dphy@510c0000 {
+ compatible = "snps,dw-dphy-rx";
+ #phy-cells = <0x01>;
+ bus-width = <0x08>;
+ snps,dphy-frequency = <0x493e0>;
+ snps,phy_type = <0x08>;
+ reg = <0x00 0x510c0000 0x00 0x20000>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ };
+
+ csidma@0x52048000 {
+ compatible = "eswin,csi-video";
+ interrupt-parent = <0x10>;
+ interrupts = <0x1d>;
+ reg = <0x00 0x52048000 0x00 0x1000>;
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ port {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ endpoint@0 {
+ reg = <0x00>;
+ bus-type = <0x04>;
+ remote-endpoint = <0x44>;
+ phandle = <0x46>;
+ };
+ };
+ };
+
+ csidma@0x52058000 {
+ compatible = "eswin,csi-video";
+ interrupt-parent = <0x10>;
+ interrupts = <0x1e>;
+ reg = <0x00 0x52058000 0x00 0x1000>;
+ numa-node-id = <0x00>;
+ status = "disabled";
+
+ port {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ endpoint@0 {
+ reg = <0x00>;
+ bus-type = <0x04>;
+ remote-endpoint = <0x45>;
+ phandle = <0x47>;
+ };
+ };
+ };
+
+ csi2@51050000 {
+ compatible = "snps,dw-csi";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x1d>;
+ snps,output-type = <0x00>;
+ reg = <0x00 0x51050000 0x00 0x1000>;
+ numa-node-id = <0x00>;
+ snps,en-ppi-width = <0x00>;
+ snps,en-phy-mode = <0x00>;
+ ipi2_en = <0x00>;
+ ipi2_vcid = <0x00>;
+ ipi3_en = <0x00>;
+ ipi3_vcid = <0x00>;
+ status = "okay";
+
+ port@2 {
+ reg = <0x02>;
+
+ endpoint {
+ bus-type = <0x04>;
+ clock-lanes = <0x00>;
+ data-lanes = <0x01 0x02>;
+ remote-endpoint = <0x46>;
+ phandle = <0x44>;
+ };
+ };
+ };
+
+ csi2@51060000 {
+ compatible = "snps,dw-csi";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x1e>;
+ snps,output-type = <0x00>;
+ reg = <0x00 0x51060000 0x00 0x1000>;
+ numa-node-id = <0x00>;
+ snps,en-ppi-width = <0x00>;
+ snps,en-phy-mode = <0x00>;
+ ipi2_en = <0x00>;
+ ipi2_vcid = <0x00>;
+ ipi3_en = <0x00>;
+ ipi3_vcid = <0x00>;
+ status = "disabled";
+
+ port@2 {
+ reg = <0x02>;
+
+ endpoint {
+ bus-type = <0x04>;
+ remote-endpoint = <0x47>;
+ phandle = <0x45>;
+ };
+ };
+ };
+
+ numa_sample@0 {
+ compatible = "eswin,numa-sample\0simple-bus";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+ dma-ranges = <0x00 0x80000000 0x00 0xc0000000 0x00 0x80000000>;
+ iommus = <0x19 0x18>;
+ tbus = <0xf00>;
+ numa-node-id = <0x00>;
+ status = "disabled";
+ dma-noncoherent;
+ };
+
+ ddr-controller@52300000 {
+ compatible = "eswin,ddrc-1.20a";
+ interrupt-parent = <0x10>;
+ interrupts = <0x0a>;
+ interrupt-names = "ddr-ecc";
+ reg = <0x00 0x52300000 0x00 0x40000>;
+ ctrl-id = <0x00>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ };
+
+ ddr-controller@52380000 {
+ compatible = "eswin,ddrc-1.20a";
+ interrupt-parent = <0x10>;
+ interrupts = <0x12b>;
+ interrupt-names = "ddr-ecc";
+ reg = <0x00 0x52380000 0x00 0x40000>;
+ ctrl-id = <0x01>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ };
+
+ d2d-unit@52100000 {
+ compatible = "eswin,eic7x-d2d";
+ interrupt-parent = <0x10>;
+ interrupts = <0x11f 0x120>;
+ reg = <0x00 0x52100000 0x00 0x50000>;
+ reg-names = "control";
+ numa-node-id = <0x00>;
+ status = "disabled";
+ };
+ };
+
+ opp-table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ phandle = <0x04>;
+
+ opp-24000000 {
+ opp-hz = <0x00 0x16e3600>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-100000000 {
+ opp-hz = <0x00 0x5f5e100>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-200000000 {
+ opp-hz = <0x00 0xbebc200>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-400000000 {
+ opp-hz = <0x00 0x17d78400>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-500000000 {
+ opp-hz = <0x00 0x1dcd6500>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-600000000 {
+ opp-hz = <0x00 0x23c34600>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-700000000 {
+ opp-hz = <0x00 0x29b92700>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-800000000 {
+ opp-hz = <0x00 0x2faf0800>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-900000000 {
+ opp-hz = <0x00 0x35a4e900>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-1000000000 {
+ opp-hz = <0x00 0x3b9aca00>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-1200000000 {
+ opp-hz = <0x00 0x47868c00>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-1300000000 {
+ opp-hz = <0x00 0x4d7c6d00>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-1400000000 {
+ opp-hz = <0x00 0x53724e00>;
+ opp-microvolt = "\0\f5";
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-1500000000 {
+ opp-hz = <0x00 0x59682f00>;
+ opp-microvolt = <0xdbba0>;
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-1600000000 {
+ opp-hz = <0x00 0x5f5e1000>;
+ opp-microvolt = <0xdbba0>;
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-1700000000 {
+ opp-hz = <0x00 0x6553f100>;
+ opp-microvolt = <0xdbba0>;
+ clock-latency-ns = <0x11170>;
+ };
+
+ opp-1800000000 {
+ opp-hz = <0x00 0x6b49d200>;
+ opp-microvolt = <0xdbba0>;
+ clock-latency-ns = <0x11170>;
+ };
+ };
+
+ thermal-zones {
+
+ thermal0 {
+ polling-delay-passive = <0x1f4>;
+ polling-delay = <0x1388>;
+ sustainable-power = <0x4b0>;
+ thermal-sensors = <0x48>;
+
+ trips {
+
+ trip-point0 {
+ temperature = <0xea60>;
+ hysteresis = <0x3e8>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <0x11170>;
+ hysteresis = <0x3e8>;
+ type = "passive";
+ phandle = <0x49>;
+ };
+
+ trip-point2 {
+ temperature = <0x1adb0>;
+ hysteresis = <0x00>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+
+ map0 {
+ trip = <0x49>;
+ contribution = <0x400>;
+ cooling-device = <0x4a 0xffffffff 0xffffffff 0x4b 0xffffffff 0xffffffff 0x4c 0xffffffff 0xffffffff 0x4d 0xffffffff 0xffffffff>;
+ };
+
+ map1 {
+ trip = <0x49>;
+ contribution = <0x400>;
+ cooling-device = <0x4e 0xffffffff 0xffffffff>;
+ };
+
+ map2 {
+ trip = <0x49>;
+ contribution = <0x400>;
+ cooling-device = <0x4f 0xffffffff 0xffffffff>;
+ };
+ };
+ };
+ };
+
+ aliases {
+ serial0 = "/soc/serial@0x50900000";
+ ethernet0 = "/soc/ethernet@50400000";
+ ethernet1 = "/soc/ethernet@50410000";
+ rtc0 = "/soc/rtc@51818000";
+ rtc1 = "/soc/i2c@51830000/rtc@51";
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+
+ domain-config {
+ compatible = "opensbi,domain,config";
+ system-suspend-test;
+ };
+ };
+
+ memory@59000000 {
+ device_type = "memory";
+ reg = <0x00 0x59000000 0x00 0x400000>;
+ numa-node-id = <0x00>;
+ };
+
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x00 0x20000000>;
+ alignment = <0x00 0x1000>;
+ alloc-ranges = <0x00 0x80000000 0x04 0x00>;
+ linux,cma-default;
+ };
+
+ sprammemory@59000000 {
+ no-map;
+ reg = <0x00 0x59000000 0x00 0x400000>;
+ phandle = <0x23>;
+ };
+
+ g2d_4GB_boundary_reserved_4k {
+ no-map;
+ reg = <0x00 0xfffff000 0x00 0x1000>;
+ };
+
+ g2d_8GB_boundary_reserved_4k {
+ no-map;
+ reg = <0x01 0xfffff000 0x00 0x1000>;
+ };
+
+ g2d_12GB_boundary_reserved_4k {
+ no-map;
+ reg = <0x02 0xfffff000 0x00 0x1000>;
+ };
+
+ mmz_nid_0_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x03 0x00 0x01 0x1000>;
+ no-map;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <0x50 0x51 0x52>;
+
+ gpio-107 {
+ gpios = <0x2a 0x0b 0x00>;
+ label = "power";
+ linux,default-trigger = "default-on";
+ };
+
+ gpio-108 {
+ gpios = <0x2a 0x0c 0x01>;
+ label = "heartbeat";
+ linux,default-trigger = "heartbeat";
+ };
+
+ gpio-109 {
+ gpios = <0x2a 0x0d 0x00>;
+ label = "gpio-109";
+ linux,default-trigger = "default-off";
+ };
+
+ gpio-110 {
+ gpios = <0x2a 0x0e 0x00>;
+ label = "gpio-109";
+ linux,default-trigger = "default-off";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ ok_key {
+ label = "OK";
+ linux,code = <0x160>;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x53>;
+ gpios = <0x21 0x06 0x01>;
+ };
+ };
+};
diff --git a/platform/riscv64/megrez/image/dts/minimal.dts b/platform/riscv64/megrez/image/dts/minimal.dts
new file mode 100644
index 00000000..d2581fc6
--- /dev/null
+++ b/platform/riscv64/megrez/image/dts/minimal.dts
@@ -0,0 +1,1006 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "sifive,hifive-unmatched-a00\0sifive,fu740-c000\0sifive,fu740\0eswin,eic7700";
+ model = "Milk-V Megrez";
+
+ opp-table@dsp {
+ compatible = "operating-points-v2";
+ phandle = <0x22>;
+
+ opp@520000000 {
+ opp-hz = <0x00 0x1efe9200>;
+ opp-microvolt = "\0\f5";
+ };
+
+ opp@1040000000 {
+ opp-hz = <0x00 0x3dfd2400>;
+ opp-microvolt = "\0\f5";
+ };
+ };
+
+ opp-table@npu {
+ compatible = "operating-points-v2";
+ phandle = <0x1f>;
+
+ opp@1040000000 {
+ opp-hz = <0x00 0x3dfd2400>;
+ opp-microvolt = <0xdbba0>;
+ };
+
+ opp@1500000000 {
+ opp-hz = <0x00 0x59682f00>;
+ opp-microvolt = <0x100590>;
+ };
+ };
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ timebase-frequency = <0xf4240>;
+
+ idle-states {
+
+ cpu-retentive {
+ compatible = "riscv,idle-state";
+ riscv,sbi-suspend-param = <0x00>;
+ entry-latency-us = <0x14>;
+ exit-latency-us = <0x28>;
+ min-residency-us = <0x50>;
+ phandle = <0x05>;
+ };
+ };
+
+ cpu@0 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x01>;
+ reg = <0x00>;
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x02>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f4>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0c>;
+ };
+ };
+
+ cpu@1 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x06>;
+ reg = <0x01>;
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x07>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f5>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0d>;
+ };
+ };
+
+ cpu@2 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x08>;
+ reg = <0x02>;
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x09>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f6>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0e>;
+ };
+ };
+
+ cpu@3 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x0a>;
+ reg = <0x03>;
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x0b>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f7>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0f>;
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "SiFive,FU800-soc\0fu800-soc\0sifive-soc\0simple-bus";
+ ranges;
+
+ cache-controller@2010000 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ cache-block-size = <0x40>;
+ cache-level = <0x03>;
+ cache-sets = <0x1000>;
+ cache-size = <0x400000>;
+ cache-unified;
+ compatible = "sifive,ccache1\0cache\0sifive,fu740-c000-ccache";
+ interrupt-parent = <0x10>;
+ interrupts = <0x01 0x03 0x04 0x02>;
+ reg = <0x00 0x2010000 0x00 0x4000 0x00 0x8000000 0x00 0x400000>;
+ reg-names = "control\0sideband";
+ sifive,a-mshr-count = <0x3c>;
+ sifive,bank-count = <0x04>;
+ sifive,ecc-granularity = <0x08>;
+ sifive,max-master-id = <0x0d>;
+ sifive,perfmon-counters = <0x06>;
+ numa-node-id = <0x00>;
+ ranges;
+ phandle = <0x11>;
+
+ zero-device@1a000000 {
+ compatible = "l3,zero-device";
+ reg = <0x00 0x1a000000 0x00 0x400000>;
+ };
+ };
+
+ interrupt-controller@c000000 {
+ #interrupt-cells = <0x01>;
+ compatible = "sifive,plic-1.0.0";
+ interrupt-controller;
+ interrupts-extended = <0x0c 0xffffffff 0x0c 0x09 0x0d 0xffffffff 0x0d 0x09 0x0e 0xffffffff 0x0e 0x09 0x0f 0xffffffff 0x0f 0x09>;
+ reg = <0x00 0xc000000 0x00 0x4000000>;
+ reg-names = "control";
+ riscv,max-priority = <0x07>;
+ riscv,ndev = <0x208>;
+ numa-node-id = <0x00>;
+ phandle = <0x10>;
+ };
+
+
+ serial@0x50900000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00 0x50900000 0x00 0x10000>;
+ clock-frequency = <0xbebc200>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x64>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ phandle = <0x27>;
+ };
+
+
+ scu_sys_con@0x51810000 {
+ compatible = "eswin,win2030-scu-sys-con\0syscon\0simple-mfd";
+ #syscon-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x51810000 0x00 0x8000>;
+ numa-node-id = <0x00>;
+ phandle = <0x13>;
+
+ noc@51810324 {
+ compatible = "eswin,win2030-noc-wdt";
+ interrupt-parent = <0x10>;
+ interrupts = <0x188 0x189 0x18a 0x18b 0x18c 0x18d 0x18e 0x18f 0x190 0x191 0x192 0x193 0x194 0x195 0x196 0x197 0x198 0x199 0x19a 0x19b 0x19c 0x19d 0x19e 0x19f 0x1a0 0x1a1 0x1a2 0x1a3 0x1a4 0x1a5 0x1a6 0x1a7 0x1a8 0x1a9 0x1aa>;
+ eswin,syscrg_csr = <0x12 0x100 0xffff>;
+ status = "okay";
+ };
+ };
+
+ sys-crg@51828000 {
+ compatible = "eswin,win2030-sys-crg\0syscon\0simple-mfd";
+ reg = <0x00 0x51828000 0x00 0x80000>;
+ numa-node-id = <0x00>;
+ phandle = <0x12>;
+
+ reset-controller {
+ compatible = "eswin,win2030-reset";
+ #reset-cells = <0x02>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ phandle = <0x14>;
+ };
+
+ clock-controller {
+ compatible = "eswin,win2030-clock";
+ #clock-cells = <0x01>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ force-1_8ghz;
+ phandle = <0x03>;
+ };
+ };
+
+
+ hsp_sp_top_csr@0x50440000 {
+ compatible = "eswin,win2030-hsp-sp-csr\0syscon";
+ numa-node-id = <0x00>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x50440000 0x00 0x2000>;
+ phandle = <0x16>;
+ };
+
+ iommu@50c00000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x00 0x50c00000 0x00 0x100000>;
+ eswin,syscfg = <0x13 0x3fc>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x164 0x168 0x165 0x166>;
+ interrupt-names = "eventq\0gerror\0priq\0cmdq-sync";
+ #iommu-cells = <0x01>;
+ resets = <0x14 0x05 0x01 0x14 0x05 0x02 0x14 0x05 0x10 0x14 0x05 0x20 0x14 0x05 0x40 0x14 0x05 0x80 0x14 0x05 0x100 0x14 0x05 0x200 0x14 0x05 0x400 0x14 0x05 0x800>;
+ reset-names = "axi_rst\0cfg_rst\0tbu0_rst\0tbu1_rst\0tbu2_rst\0tbu3_rst\0tbu4_rst\0tbu5_rst\0tbu6_rst\0tbu7_rst";
+ status = "okay";
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ phandle = <0x15>;
+ };
+
+ ethernet@50400000 {
+ compatible = "eswin,win2030-qos-eth";
+ reg = <0x00 0x50400000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupt-names = "macirq";
+ interrupts = <0x3d>;
+ phy-mode = "rgmii";
+ numa-node-id = <0x00>;
+ id = <0x00>;
+ status = "okay";
+ clocks = <0x03 0x226 0x03 0x227 0x03 0x228>;
+ clock-names = "app\0stmmaceth\0tx";
+ resets = <0x14 0x07 0x4000000>;
+ reset-names = "ethrst";
+ tbus = <0x02>;
+ dma-noncoherent;
+ eswin,hsp_sp_csr = <0x16 0x1030 0x100 0x108>;
+ eswin,syscrg_csr = <0x12 0x148 0x14c>;
+ eswin,dly_hsp_reg = <0x114 0x118 0x11c>;
+ snps,axi-config = <0x17>;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x18>;
+ rst-gpios = <0x19 0x1e 0x01>;
+ eswin,rgmiisel = <0x1a 0x290 0x03>;
+ eswin,led-cfgs = <0x6100 0xa40 0x420>;
+ dly-param-1000m = <0x23232323 0x800c8023 0xc0c0c0c>;
+ dly-param-100m = <0x50505050 0x803f8050 0x3f3f3f3f>;
+ dly-param-10m = <0x00 0x00 0x00>;
+
+ stmmac-axi-config {
+ snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
+ snps,rd_osr_lmt = <0x02>;
+ snps,wr_osr_lmt = <0x02>;
+ snps,lpi_en = <0x00>;
+ phandle = <0x17>;
+ };
+ };
+
+ ethernet@50410000 {
+ compatible = "eswin,win2030-qos-eth";
+ reg = <0x00 0x50410000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupt-names = "macirq";
+ interrupts = <0x46>;
+ phy-mode = "rgmii";
+ numa-node-id = <0x00>;
+ id = <0x01>;
+ status = "okay";
+ clocks = <0x03 0x226 0x03 0x227 0x03 0x229>;
+ clock-names = "app\0stmmaceth\0tx";
+ resets = <0x14 0x07 0x2000000>;
+ reset-names = "ethrst";
+ tbus = <0x02>;
+ dma-noncoherent;
+ eswin,hsp_sp_csr = <0x16 0x1034 0x200 0x208>;
+ eswin,syscrg_csr = <0x12 0x148 0x14c>;
+ eswin,dly_hsp_reg = <0x214 0x218 0x21c>;
+ snps,axi-config = <0x1b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x1c>;
+ rst-gpios = <0x1d 0x10 0x01>;
+ eswin,rgmiisel = <0x1a 0x294 0x03>;
+ eswin,led-cfgs = <0x6100 0xa40 0x420>;
+ dly-param-1000m = <0x25252525 0x80268025 0x26262626>;
+ dly-param-100m = <0x48484848 0x80588048 0x58585858>;
+ dly-param-10m = <0x00 0x00 0x00>;
+
+ stmmac-axi-config {
+ snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
+ snps,rd_osr_lmt = <0x02>;
+ snps,wr_osr_lmt = <0x02>;
+ snps,lpi_en = <0x00>;
+ phandle = <0x1b>;
+ };
+ };
+
+
+ eswin-npu@51c00000 {
+ compatible = "eswin,npu";
+ reg = <0x00 0x51c00000 0x00 0x400000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x183 0x10>;
+ #size-cells = <0x02>;
+ dma-ranges = <0x01 0x00 0x00 0xc0000000 0x1ff 0x00>;
+ iommus = <0x15 0x04>;
+ tbus = <0x05>;
+ dsp-avail-num = <0x01>;
+ spram-size = <0x400000>;
+ npu_mbox = <0x1e>;
+ clocks = <0x03 0x236 0x03 0x237 0x03 0x23c 0x03 0x23a 0x03 0x23d 0x03 0x26 0x03 0x25 0x03 0x0b 0x03 0x07 0x03 0x238 0x03 0x0d>;
+ clock-names = "aclk\0cfg_clk\0core_clk\0clk_npu_llc_aclk\0e31_core_clk\0mux_u_npu_core_3mux1_gfree\0mux_u_npu_llclk_3mux1_gfree\0fixed_rate_clk_spll2_fout2\0fixed_rate_clk_spll1_fout1\0clk_clk_npu_llc_src0\0fixed_rate_clk_vpll_fout1";
+ resets = <0x14 0x06 0x08>;
+ reset-names = "e31_core";
+ operating-points-v2 = <0x1f>;
+ numa-node-id = <0x00>;
+ firmware-name = "eic7700_die0_e31_fw";
+ dma-noncoherent;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x00>;
+ status = "okay";
+ npu-supply = <0x20>;
+ apply_npu_1G_freq;
+ };
+
+ llc@51c00000 {
+ compatible = "eswin,llc";
+ reg = <0x00 0x51c00000 0x00 0x400000>;
+ eswin,syscfg = <0x13 0x324>;
+ eswin,syscrg_csr = <0x12>;
+ clocks = <0x03 0x236 0x03 0x237 0x03 0x23a 0x03 0x23c 0x03 0x26 0x03 0x0b 0x03 0x07>;
+ clock-names = "aclk\0cfg_clk\0llc_clk\0core_clk\0mux_u_npu_core_3mux1_gfree\0fixed_rate_clk_spll2_fout2\0fixed_rate_clk_spll1_fout1";
+ resets = <0x14 0x06 0x01 0x14 0x06 0x02 0x14 0x06 0x04 0x14 0x06 0x40>;
+ reset-names = "axi\0cfg\0core\0llc";
+ numa-node-id = <0x00>;
+ spram-region = <0x21>;
+ npu-supply = <0x20>;
+ apply_npu_high_freq;
+ };
+
+ dsp_subsys@52280400 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x52280400 0x00 0x10000 0x00 0x51810000 0x00 0x8000>;
+ ranges;
+ numa-node-id = <0x00>;
+ dma-ranges = <0x00 0x30000000 0x00 0xc0000000 0x00 0xce000000>;
+ compatible = "es-dsp-subsys\0simple-bus";
+ clocks = <0x03 0x210 0x03 0x20f>;
+ clock-names = "cfg_clk\0aclk";
+ resets = <0x14 0x02 0x01 0x14 0x02 0x02 0x14 0x02 0x04 0x14 0x02 0x10 0x14 0x02 0x20 0x14 0x02 0x40 0x14 0x02 0x80>;
+ reset-names = "axi\0cfg\0div4\0div_0\0div_1\0div_2\0div_3";
+ status = "okay";
+
+ es_dsp@0 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b000000 0x8000 0x28100000 0x00 0x5b100000 0x20000 0x28120000 0x00 0x5b120000 0x20000>;
+ clocks = <0x03 0x2a8>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x22>;
+ dsp_mbox = <0x23>;
+ device-irq = <0x0b 0x50a90000 0x20 0x50a80000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x00>;
+ iommus = <0x15 0x12>;
+ tbus = <0x70>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ es_dsp@1 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b008000 0x8000 0x28100000 0x00 0x5b140000 0x20000 0x28120000 0x00 0x5b160000 0x20000>;
+ clocks = <0x03 0x2a9>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x22>;
+ dsp_mbox = <0x24>;
+ device-irq = <0x0d 0x50ab0000 0x40 0x50aa0000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x01>;
+ iommus = <0x15 0x13>;
+ tbus = <0x71>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ es_dsp@2 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b010000 0x8000 0x28100000 0x00 0x5b180000 0x20000 0x28120000 0x00 0x5b1a0000 0x20000>;
+ clocks = <0x03 0x2aa>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x22>;
+ dsp_mbox = <0x25>;
+ device-irq = <0x0f 0x50ad0000 0x80 0x50ac0000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x02>;
+ iommus = <0x15 0x14>;
+ tbus = <0x72>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ es_dsp@3 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b018000 0x8000 0x28100000 0x00 0x5b1c0000 0x20000 0x28120000 0x00 0x5b1e0000 0x20000>;
+ clocks = <0x03 0x2ab>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x22>;
+ dsp_mbox = <0x26>;
+ device-irq = <0x11 0x50af0000 0x100 0x50ae0000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x03>;
+ iommus = <0x15 0x15>;
+ tbus = <0x73>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ sofdsp@4 {
+ #sound-dai-cells = <0x01>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "eswin,sof-dsp";
+ reg = <0x00 0x5b018000 0x00 0x8000 0x00 0x5b1c0000 0x00 0x40000>;
+ mbox-names = "dsp-mbox";
+ mboxes = <0x26 0x00>;
+ clocks = <0x03 0x2ab>;
+ clock-names = "aclk";
+ process-id = <0x03>;
+ iommus = <0x15 0x15>;
+ tbus = <0x73>;
+ dma-noncoherent;
+ mailbox-dsp-to-u84-addr = <0x50af0000>;
+ mailbox-u84-to-dsp-addr = <0x50ae0000>;
+ dsp-uart = <0x27>;
+ device-uart-mutex = <0x51820000>;
+ numa-node-id = <0x00>;
+ };
+ };
+
+ mmc@50450000 {
+ compatible = "eswin,emmc-sdhci-5.1";
+ reg = <0x00 0x50450000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x4f>;
+ assigned-clocks = <0x03 0x22a>;
+ assigned-clock-rates = <0xbebc200>;
+ clocks = <0x03 0x22a 0x03 0x222>;
+ clock-names = "clk_xin\0clk_ahb";
+ clock-output-names = "emmc_cardclock";
+ #clock-cells = <0x00>;
+ resets = <0x14 0x07 0x40 0x14 0x07 0x08 0x14 0x07 0x80000 0x14 0x07 0x800000>;
+ reset-names = "txrx_rst\0phy_rst\0prstn\0arstn";
+ core-clk-reg = <0x51828160>;
+ disable-cqe-dcmd;
+ bus-width = <0x08>;
+ non-removable;
+ mmc-hs400-1_8v;
+ max-frequency = <0xbebc200>;
+ #size-cells = <0x02>;
+ iommus = <0x15 0x0f>;
+ tbus = <0x02>;
+ dma-ranges = <0x00 0x00 0x00 0xc0000000 0x01 0x00>;
+ eswin,hsp_sp_csr = <0x16 0x1038 0x508 0x50c>;
+ eswin,syscrg_csr = <0x12 0x160 0x148 0x14c>;
+ status = "okay";
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ delay_code = <0x17>;
+ drive-impedance-ohm = <0x32>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x2c>;
+ no-sdio;
+ no-sd;
+ };
+
+ mmc@0x50460000 {
+ compatible = "eswin,sdhci-sdio";
+ reg = <0x00 0x50460000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x51>;
+ clocks = <0x03 0x22b 0x03 0x222 0x03 0x0c 0x03 0x23>;
+ clock-names = "clk_xin\0clk_ahb\0clk_spll2_fout3\0clk_mux1_1";
+ clock-output-names = "sdio0_cardclock";
+ #clock-cells = <0x00>;
+ resets = <0x14 0x07 0x80 0x14 0x07 0x10 0x14 0x07 0x40000 0x14 0x07 0x400000>;
+ reset-names = "txrx_rst\0phy_rst\0prstn\0arstn";
+ clock-frequency = <0xc65d400>;
+ max-frequency = <0xc65d400>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ dma-ranges = <0x00 0x20000000 0x00 0xc0000000 0x00 0x40000000>;
+ iommus = <0x15 0x10>;
+ tbus = <0x02>;
+ eswin,hsp_sp_csr = <0x16 0x103c 0x608 0x60c>;
+ eswin,syscrg_csr = <0x12 0x164 0x148 0x14c>;
+ bus-width = <0x04>;
+ sdio-id = <0x00>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ dma-noncoherent;
+ delay_code = <0x3b>;
+ drive-impedance-ohm = <0x21>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ no-sdio;
+ no-mmc;
+ disable-wp;
+ broken-cd;
+ };
+
+ // mmc@0x50470000 {
+ // compatible = "eswin,sdhci-sdio";
+ // reg = <0x00 0x50470000 0x00 0x10000>;
+ // interrupt-parent = <0x10>;
+ // interrupts = <0x53>;
+ // clocks = <0x03 0x22c 0x03 0x222 0x03 0x0c 0x03 0x23>;
+ // clock-names = "clk_xin\0clk_ahb\0clk_spll2_fout3\0clk_mux1_1";
+ // clock-output-names = "sdio1_cardclock";
+ // #clock-cells = <0x00>;
+ // resets = <0x14 0x07 0x100 0x14 0x07 0x20 0x14 0x07 0x20000 0x14 0x07 0x200000>;
+ // reset-names = "txrx_rst\0phy_rst\0prstn\0arstn";
+ // clock-frequency = <0xc65d400>;
+ // max-frequency = <0xc65d400>;
+ // #address-cells = <0x01>;
+ // #size-cells = <0x00>;
+ // dma-ranges = <0x00 0x20000000 0x00 0xc0000000 0x00 0x40000000>;
+ // iommus = <0x15 0x11>;
+ // tbus = <0x02>;
+ // eswin,hsp_sp_csr = <0x16 0x1040 0x708 0x70c>;
+ // eswin,syscrg_csr = <0x12 0x168 0x148 0x14c>;
+ // bus-width = <0x04>;
+ // sdio-id = <0x01>;
+ // numa-node-id = <0x00>;
+ // status = "okay";
+ // dma-noncoherent;
+ // delay_code = <0x29>;
+ // drive-impedance-ohm = <0x21>;
+ // enable-cmd-pullup;
+ // enable-data-pullup;
+ // keep-power-in-suspend;
+ // non-removable;
+ // no-sd;
+ // no-mmc;
+ // };
+
+ mbox@50a40000 {
+ compatible = "eswin,npu0-mailbox";
+ reg = <0x00 0x50a40000 0x00 0x10000 0x00 0x50a50000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x79>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x282 0x03 0x283>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x14 0x0c 0x10 0x14 0x0c 0x20>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x08>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x1e>;
+ };
+
+ mbox@50a80000 {
+ compatible = "eswin,dsp0-mailbox";
+ reg = <0x00 0x50a80000 0x00 0x10000 0x00 0x50a90000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x7d>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x286 0x03 0x287>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x14 0x0c 0x100 0x14 0x0c 0x200>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x20>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x23>;
+ };
+
+ mbox@50aa0000 {
+ compatible = "eswin,dsp1-mailbox";
+ reg = <0x00 0x50aa0000 0x00 0x10000 0x00 0x50ab0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x7f>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x288 0x03 0x289>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x14 0x0c 0x400 0x14 0x0c 0x800>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x40>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x24>;
+ };
+
+ mbox@50ac0000 {
+ compatible = "eswin,dsp2-mailbox";
+ reg = <0x00 0x50ac0000 0x00 0x10000 0x00 0x50ad0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x81>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x28a 0x03 0x28b>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x14 0x0c 0x1000 0x14 0x0c 0x2000>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x80>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x25>;
+ };
+
+ mbox@50ae0000 {
+ compatible = "eswin,dsp3-mailbox";
+ reg = <0x00 0x50ae0000 0x00 0x10000 0x00 0x50af0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x83>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x28c 0x03 0x28d>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x14 0x0c 0x4000 0x14 0x0c 0x8000>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x100>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x26>;
+ };
+
+ i2c@50960000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x28f>;
+ clock-names = "pclk";
+ resets = <0x14 0x09 0x02>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x50960000 0x00 0x10000>;
+ interrupts = <0x6a>;
+ interrupt-parent = <0x10>;
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ es5430@f {
+ compatible = "einno,es5340";
+ reg = <0x0f>;
+ eswin,regulator_default-microvolt = <0xf4240>;
+ eswin,regulator_label = "supply vdd1\0npu vdd1\0npu current1\0npu temperature1";
+ label = "npu_vdd";
+
+ regulators {
+
+ npu_svcc {
+ regulator-name = "NPU_SVCC";
+ regulator-min-microvolt = <0xaae60>;
+ regulator-max-microvolt = <0x10c8e0>;
+ regulator-min-microamp = <0x1312d00>;
+ regulator-max-microamp = <0x2625a00>;
+ regulator-ov-protection-microvolt = <0x10c8e0>;
+ regulator-always-on;
+ phandle = <0x20>;
+ };
+ };
+ };
+ };
+
+ pinctrl@0x51600080 {
+ compatible = "eswin,eic7x-pinctrl\0syscon";
+ reg = <0x00 0x51600080 0x00 0x1fff80>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ phandle = <0x1a>;
+
+ emmc_led_control-default {
+ phandle = <0x2c>;
+
+ mux {
+ groups = "emmc_led_control_group";
+ function = "emmc_led_control_func";
+ };
+
+ conf {
+ groups = "emmc_led_control_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio16-default {
+ phandle = <0x1c>;
+
+ mux {
+ groups = "gpio16_group";
+ function = "gpio16_func";
+ };
+
+ conf {
+ groups = "gpio16_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio94-default {
+ phandle = <0x18>;
+
+ mux {
+ groups = "gpio94_group";
+ function = "gpio94_func";
+ };
+
+ conf {
+ groups = "gpio94_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+ };
+
+ gpio@51600000 {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x00 0x51600000 0x00 0x80>;
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ ngpios = <0x20>;
+ reg = <0x00>;
+ interrupt-parent = <0x10>;
+ interrupt-controller;
+ #interrupt-cells = <0x02>;
+ interrupts = <0x12f 0x130 0x131 0x132 0x133 0x134 0x135 0x136 0x137 0x138 0x139 0x13a 0x13b 0x13c 0x13d 0x13e 0x13f 0x140 0x141 0x142 0x143 0x144 0x145 0x146 0x147 0x148 0x149 0x14a 0x14b 0x14c 0x14d 0x14e>;
+ phandle = <0x1d>;
+ };
+
+
+ gpio-port@2 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ ngpios = <0x20>;
+ reg = <0x02>;
+ phandle = <0x19>;
+ };
+ };
+ };
+
+ aliases {
+ serial0 = "/soc/serial@0x50900000";
+ ethernet0 = "/soc/ethernet@50400000";
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "console=ttyS0,115200 earlycon=ttyS0,115200 root=PARTUUID=b0f77ad6-36cd-4a99-a8c0-31d73649aa09 rootfstype=ext4 rw rootwait";
+
+ domain-config {
+ compatible = "opensbi,domain,config";
+ system-suspend-test;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00 0x80000000 0x04 0x00>;
+ numa-node-id = <0x00>;
+ };
+
+ memory@59000000 {
+ device_type = "memory";
+ reg = <0x00 0x59000000 0x00 0x400000>;
+ numa-node-id = <0x00>;
+ };
+
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ sprammemory@59000000 {
+ no-map;
+ reg = <0x00 0x59000000 0x00 0x400000>;
+ phandle = <0x21>;
+ };
+
+ mmz_nid_0_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x03 0x00 0x01 0x80000000>;
+ no-map;
+ };
+ };
+};
\ No newline at end of file
diff --git a/platform/riscv64/megrez/image/dts/zone0-npu.dts b/platform/riscv64/megrez/image/dts/zone0-npu.dts
new file mode 100644
index 00000000..2ba9bda1
--- /dev/null
+++ b/platform/riscv64/megrez/image/dts/zone0-npu.dts
@@ -0,0 +1,876 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "sifive,hifive-unmatched-a00\0sifive,fu740-c000\0sifive,fu740\0eswin,eic7700";
+ model = "Milk-V Megrez";
+
+ opp-table@dsp {
+ compatible = "operating-points-v2";
+ phandle = <0x22>;
+
+ opp@520000000 {
+ opp-hz = <0x00 0x1efe9200>;
+ opp-microvolt = "\0\f5";
+ };
+
+ opp@1040000000 {
+ opp-hz = <0x00 0x3dfd2400>;
+ opp-microvolt = "\0\f5";
+ };
+ };
+
+ opp-table@npu {
+ compatible = "operating-points-v2";
+ phandle = <0x1f>;
+
+ opp@1040000000 {
+ opp-hz = <0x00 0x3dfd2400>;
+ opp-microvolt = <0xdbba0>;
+ };
+
+ opp@1500000000 {
+ opp-hz = <0x00 0x59682f00>;
+ opp-microvolt = <0x100590>;
+ };
+ };
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ timebase-frequency = <0xf4240>;
+
+ idle-states {
+
+ cpu-retentive {
+ compatible = "riscv,idle-state";
+ riscv,sbi-suspend-param = <0x00>;
+ entry-latency-us = <0x14>;
+ exit-latency-us = <0x28>;
+ min-residency-us = <0x50>;
+ phandle = <0x05>;
+ };
+ };
+
+ cpu@0 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x01>;
+ reg = <0x00>;
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x02>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f4>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0c>;
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "SiFive,FU800-soc\0fu800-soc\0sifive-soc\0simple-bus";
+ ranges;
+
+ cache-controller@2010000 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ cache-block-size = <0x40>;
+ cache-level = <0x03>;
+ cache-sets = <0x1000>;
+ cache-size = <0x400000>;
+ cache-unified;
+ compatible = "sifive,ccache1\0cache\0sifive,fu740-c000-ccache";
+ interrupt-parent = <0x10>;
+ interrupts = <0x01 0x03 0x04 0x02>;
+ reg = <0x00 0x2010000 0x00 0x4000 0x00 0x8000000 0x00 0x400000>;
+ reg-names = "control\0sideband";
+ sifive,a-mshr-count = <0x3c>;
+ sifive,bank-count = <0x04>;
+ sifive,ecc-granularity = <0x08>;
+ sifive,max-master-id = <0x0d>;
+ sifive,perfmon-counters = <0x06>;
+ numa-node-id = <0x00>;
+ ranges;
+ phandle = <0x11>;
+
+ zero-device@1a000000 {
+ compatible = "l3,zero-device";
+ reg = <0x00 0x1a000000 0x00 0x400000>;
+ };
+ };
+
+ interrupt-controller@c000000 {
+ #interrupt-cells = <0x01>;
+ compatible = "sifive,plic-1.0.0";
+ interrupt-controller;
+ interrupts-extended = <0x0c 0xffffffff 0x0c 0x09 0x0d 0xffffffff 0x0d 0x09 0x0e 0xffffffff 0x0e 0x09 0x0f 0xffffffff 0x0f 0x09>;
+ reg = <0x00 0xc000000 0x00 0x4000000>;
+ reg-names = "control";
+ riscv,max-priority = <0x07>;
+ riscv,ndev = <0x208>;
+ numa-node-id = <0x00>;
+ phandle = <0x10>;
+ };
+
+ serial@0x50900000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00 0x50900000 0x00 0x10000>;
+ clock-frequency = <0xbebc200>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x64>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ phandle = <0x27>;
+ };
+
+ scu_sys_con@0x51810000 {
+ compatible = "eswin,win2030-scu-sys-con\0syscon\0simple-mfd";
+ #syscon-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x51810000 0x00 0x8000>;
+ numa-node-id = <0x00>;
+ phandle = <0x13>;
+
+ noc@51810324 {
+ compatible = "eswin,win2030-noc-wdt";
+ interrupt-parent = <0x10>;
+ interrupts = <0x188 0x189 0x18a 0x18b 0x18c 0x18d 0x18e 0x18f 0x190 0x191 0x192 0x193 0x194 0x195 0x196 0x197 0x198 0x199 0x19a 0x19b 0x19c 0x19d 0x19e 0x19f 0x1a0 0x1a1 0x1a2 0x1a3 0x1a4 0x1a5 0x1a6 0x1a7 0x1a8 0x1a9 0x1aa>;
+ eswin,syscrg_csr = <0x12 0x100 0xffff>;
+ status = "okay";
+ };
+ };
+
+ sys-crg@51828000 {
+ compatible = "eswin,win2030-sys-crg\0syscon\0simple-mfd";
+ reg = <0x00 0x51828000 0x00 0x80000>;
+ numa-node-id = <0x00>;
+ phandle = <0x12>;
+
+ reset-controller {
+ compatible = "eswin,win2030-reset";
+ #reset-cells = <0x02>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ phandle = <0x14>;
+ };
+
+ clock-controller {
+ compatible = "eswin,win2030-clock";
+ #clock-cells = <0x01>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ force-1_8ghz;
+ phandle = <0x03>;
+ };
+ };
+
+ hsp_sp_top_csr@0x50440000 {
+ compatible = "eswin,win2030-hsp-sp-csr\0syscon";
+ numa-node-id = <0x00>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x50440000 0x00 0x2000>;
+ phandle = <0x16>;
+ };
+
+ iommu@50c00000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x00 0x50c00000 0x00 0x100000>;
+ eswin,syscfg = <0x13 0x3fc>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x164 0x168 0x165 0x166>;
+ interrupt-names = "eventq\0gerror\0priq\0cmdq-sync";
+ #iommu-cells = <0x01>;
+ resets = <0x14 0x05 0x01 0x14 0x05 0x02 0x14 0x05 0x10 0x14 0x05 0x20 0x14 0x05 0x40 0x14 0x05 0x80 0x14 0x05 0x100 0x14 0x05 0x200 0x14 0x05 0x400 0x14 0x05 0x800>;
+ reset-names = "axi_rst\0cfg_rst\0tbu0_rst\0tbu1_rst\0tbu2_rst\0tbu3_rst\0tbu4_rst\0tbu5_rst\0tbu6_rst\0tbu7_rst";
+ status = "okay";
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ phandle = <0x15>;
+ };
+
+ ethernet@50400000 {
+ compatible = "eswin,win2030-qos-eth";
+ reg = <0x00 0x50400000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupt-names = "macirq";
+ interrupts = <0x3d>;
+ phy-mode = "rgmii";
+ numa-node-id = <0x00>;
+ id = <0x00>;
+ status = "okay";
+ clocks = <0x03 0x226 0x03 0x227 0x03 0x228>;
+ clock-names = "app\0stmmaceth\0tx";
+ resets = <0x14 0x07 0x4000000>;
+ reset-names = "ethrst";
+ tbus = <0x02>;
+ dma-noncoherent;
+ eswin,hsp_sp_csr = <0x16 0x1030 0x100 0x108>;
+ eswin,syscrg_csr = <0x12 0x148 0x14c>;
+ eswin,dly_hsp_reg = <0x114 0x118 0x11c>;
+ snps,axi-config = <0x17>;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x18>;
+ rst-gpios = <0x19 0x1e 0x01>;
+ eswin,rgmiisel = <0x1a 0x290 0x03>;
+ eswin,led-cfgs = <0x6100 0xa40 0x420>;
+ dly-param-1000m = <0x23232323 0x800c8023 0xc0c0c0c>;
+ dly-param-100m = <0x50505050 0x803f8050 0x3f3f3f3f>;
+ dly-param-10m = <0x00 0x00 0x00>;
+
+ stmmac-axi-config {
+ snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
+ snps,rd_osr_lmt = <0x02>;
+ snps,wr_osr_lmt = <0x02>;
+ snps,lpi_en = <0x00>;
+ phandle = <0x17>;
+ };
+ };
+
+ // ethernet@50410000 {
+ // compatible = "eswin,win2030-qos-eth";
+ // reg = <0x00 0x50410000 0x00 0x10000>;
+ // interrupt-parent = <0x10>;
+ // interrupt-names = "macirq";
+ // interrupts = <0x46>;
+ // phy-mode = "rgmii";
+ // numa-node-id = <0x00>;
+ // id = <0x01>;
+ // status = "okay";
+ // clocks = <0x03 0x226 0x03 0x227 0x03 0x229>;
+ // clock-names = "app\0stmmaceth\0tx";
+ // resets = <0x14 0x07 0x2000000>;
+ // reset-names = "ethrst";
+ // tbus = <0x02>;
+ // dma-noncoherent;
+ // eswin,hsp_sp_csr = <0x16 0x1034 0x200 0x208>;
+ // eswin,syscrg_csr = <0x12 0x148 0x14c>;
+ // eswin,dly_hsp_reg = <0x214 0x218 0x21c>;
+ // snps,axi-config = <0x1b>;
+ // pinctrl-names = "default";
+ // pinctrl-0 = <0x1c>;
+ // rst-gpios = <0x1d 0x10 0x01>;
+ // eswin,rgmiisel = <0x1a 0x294 0x03>;
+ // eswin,led-cfgs = <0x6100 0xa40 0x420>;
+ // dly-param-1000m = <0x25252525 0x80268025 0x26262626>;
+ // dly-param-100m = <0x48484848 0x80588048 0x58585858>;
+ // dly-param-10m = <0x00 0x00 0x00>;
+
+ // stmmac-axi-config {
+ // snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
+ // snps,rd_osr_lmt = <0x02>;
+ // snps,wr_osr_lmt = <0x02>;
+ // snps,lpi_en = <0x00>;
+ // phandle = <0x1b>;
+ // };
+ // };
+
+ eswin-npu@51c00000 {
+ compatible = "eswin,npu";
+ reg = <0x00 0x51c00000 0x00 0x400000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x183 0x10>;
+ #size-cells = <0x02>;
+ dma-ranges = <0x01 0x00 0x00 0xc0000000 0x1ff 0x00>;
+ iommus = <0x15 0x04>;
+ tbus = <0x05>;
+ dsp-avail-num = <0x01>;
+ spram-size = <0x400000>;
+ npu_mbox = <0x1e>;
+ clocks = <0x03 0x236 0x03 0x237 0x03 0x23c 0x03 0x23a 0x03 0x23d 0x03 0x26 0x03 0x25 0x03 0x0b 0x03 0x07 0x03 0x238 0x03 0x0d>;
+ clock-names = "aclk\0cfg_clk\0core_clk\0clk_npu_llc_aclk\0e31_core_clk\0mux_u_npu_core_3mux1_gfree\0mux_u_npu_llclk_3mux1_gfree\0fixed_rate_clk_spll2_fout2\0fixed_rate_clk_spll1_fout1\0clk_clk_npu_llc_src0\0fixed_rate_clk_vpll_fout1";
+ resets = <0x14 0x06 0x08>;
+ reset-names = "e31_core";
+ operating-points-v2 = <0x1f>;
+ numa-node-id = <0x00>;
+ firmware-name = "eic7700_die0_e31_fw";
+ dma-noncoherent;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x00>;
+ status = "okay";
+ npu-supply = <0x20>;
+ apply_npu_1G_freq;
+ };
+
+ llc@51c00000 {
+ compatible = "eswin,llc";
+ reg = <0x00 0x51c00000 0x00 0x400000>;
+ eswin,syscfg = <0x13 0x324>;
+ eswin,syscrg_csr = <0x12>;
+ clocks = <0x03 0x236 0x03 0x237 0x03 0x23a 0x03 0x23c 0x03 0x26 0x03 0x0b 0x03 0x07>;
+ clock-names = "aclk\0cfg_clk\0llc_clk\0core_clk\0mux_u_npu_core_3mux1_gfree\0fixed_rate_clk_spll2_fout2\0fixed_rate_clk_spll1_fout1";
+ resets = <0x14 0x06 0x01 0x14 0x06 0x02 0x14 0x06 0x04 0x14 0x06 0x40>;
+ reset-names = "axi\0cfg\0core\0llc";
+ numa-node-id = <0x00>;
+ spram-region = <0x21>;
+ npu-supply = <0x20>;
+ apply_npu_high_freq;
+ };
+
+ dsp_subsys@52280400 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x52280400 0x00 0x10000 0x00 0x51810000 0x00 0x8000>;
+ ranges;
+ numa-node-id = <0x00>;
+ dma-ranges = <0x00 0x30000000 0x00 0xc0000000 0x00 0xce000000>;
+ compatible = "es-dsp-subsys\0simple-bus";
+ clocks = <0x03 0x210 0x03 0x20f>;
+ clock-names = "cfg_clk\0aclk";
+ resets = <0x14 0x02 0x01 0x14 0x02 0x02 0x14 0x02 0x04 0x14 0x02 0x10 0x14 0x02 0x20 0x14 0x02 0x40 0x14 0x02 0x80>;
+ reset-names = "axi\0cfg\0div4\0div_0\0div_1\0div_2\0div_3";
+ status = "okay";
+
+ es_dsp@0 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b000000 0x8000 0x28100000 0x00 0x5b100000 0x20000 0x28120000 0x00 0x5b120000 0x20000>;
+ clocks = <0x03 0x2a8>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x22>;
+ dsp_mbox = <0x23>;
+ device-irq = <0x0b 0x50a90000 0x20 0x50a80000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x00>;
+ iommus = <0x15 0x12>;
+ tbus = <0x70>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ es_dsp@1 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b008000 0x8000 0x28100000 0x00 0x5b140000 0x20000 0x28120000 0x00 0x5b160000 0x20000>;
+ clocks = <0x03 0x2a9>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x22>;
+ dsp_mbox = <0x24>;
+ device-irq = <0x0d 0x50ab0000 0x40 0x50aa0000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x01>;
+ iommus = <0x15 0x13>;
+ tbus = <0x71>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ es_dsp@2 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b010000 0x8000 0x28100000 0x00 0x5b180000 0x20000 0x28120000 0x00 0x5b1a0000 0x20000>;
+ clocks = <0x03 0x2aa>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x22>;
+ dsp_mbox = <0x25>;
+ device-irq = <0x0f 0x50ad0000 0x80 0x50ac0000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x02>;
+ iommus = <0x15 0x14>;
+ tbus = <0x72>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ es_dsp@3 {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "eswin-dsp\0cdns,xrp-hw-eswin";
+ ranges = <0x28000000 0x00 0x5b018000 0x8000 0x28100000 0x00 0x5b1c0000 0x20000 0x28120000 0x00 0x5b1e0000 0x20000>;
+ clocks = <0x03 0x2ab>;
+ clock-names = "aclk";
+ operating-points-v2 = <0x22>;
+ dsp_mbox = <0x26>;
+ device-irq = <0x11 0x50af0000 0x100 0x50ae0000 0x01 0x50a40000>;
+ device-uart = <0x50900000>;
+ device-irq-mode = <0x01>;
+ host-irq-mode = <0x01>;
+ firmware-name = "eic7700_dsp_fw";
+ process-id = <0x03>;
+ iommus = <0x15 0x15>;
+ tbus = <0x73>;
+ dma-noncoherent;
+ numa-node-id = <0x00>;
+ aux-e31-dtim = <0x5a110000>;
+ status = "okay";
+
+ dsp@0 {
+ };
+ };
+
+ sofdsp@4 {
+ #sound-dai-cells = <0x01>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "eswin,sof-dsp";
+ reg = <0x00 0x5b018000 0x00 0x8000 0x00 0x5b1c0000 0x00 0x40000>;
+ mbox-names = "dsp-mbox";
+ mboxes = <0x26 0x00>;
+ clocks = <0x03 0x2ab>;
+ clock-names = "aclk";
+ process-id = <0x03>;
+ iommus = <0x15 0x15>;
+ tbus = <0x73>;
+ dma-noncoherent;
+ mailbox-dsp-to-u84-addr = <0x50af0000>;
+ mailbox-u84-to-dsp-addr = <0x50ae0000>;
+ dsp-uart = <0x27>;
+ device-uart-mutex = <0x51820000>;
+ numa-node-id = <0x00>;
+ };
+ };
+
+ mmc@50450000 {
+ compatible = "eswin,emmc-sdhci-5.1";
+ reg = <0x00 0x50450000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x4f>;
+ assigned-clocks = <0x03 0x22a>;
+ assigned-clock-rates = <0xbebc200>;
+ clocks = <0x03 0x22a 0x03 0x222>;
+ clock-names = "clk_xin\0clk_ahb";
+ clock-output-names = "emmc_cardclock";
+ #clock-cells = <0x00>;
+ resets = <0x14 0x07 0x40 0x14 0x07 0x08 0x14 0x07 0x80000 0x14 0x07 0x800000>;
+ reset-names = "txrx_rst\0phy_rst\0prstn\0arstn";
+ core-clk-reg = <0x51828160>;
+ disable-cqe-dcmd;
+ bus-width = <0x08>;
+ non-removable;
+ mmc-hs400-1_8v;
+ max-frequency = <0xbebc200>;
+ #size-cells = <0x02>;
+ iommus = <0x15 0x0f>;
+ tbus = <0x02>;
+ dma-ranges = <0x00 0x00 0x00 0xc0000000 0x01 0x00>;
+ eswin,hsp_sp_csr = <0x16 0x1038 0x508 0x50c>;
+ eswin,syscrg_csr = <0x12 0x160 0x148 0x14c>;
+ status = "okay";
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ delay_code = <0x17>;
+ drive-impedance-ohm = <0x32>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x2c>;
+ no-sdio;
+ no-sd;
+ };
+
+ mmc@0x50460000 {
+ compatible = "eswin,sdhci-sdio";
+ reg = <0x00 0x50460000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x51>;
+ clocks = <0x03 0x22b 0x03 0x222 0x03 0x0c 0x03 0x23>;
+ clock-names = "clk_xin\0clk_ahb\0clk_spll2_fout3\0clk_mux1_1";
+ clock-output-names = "sdio0_cardclock";
+ #clock-cells = <0x00>;
+ resets = <0x14 0x07 0x80 0x14 0x07 0x10 0x14 0x07 0x40000 0x14 0x07 0x400000>;
+ reset-names = "txrx_rst\0phy_rst\0prstn\0arstn";
+ clock-frequency = <0xc65d400>;
+ max-frequency = <0xc65d400>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ dma-ranges = <0x00 0x20000000 0x00 0xc0000000 0x00 0x40000000>;
+ iommus = <0x15 0x10>;
+ tbus = <0x02>;
+ eswin,hsp_sp_csr = <0x16 0x103c 0x608 0x60c>;
+ eswin,syscrg_csr = <0x12 0x164 0x148 0x14c>;
+ bus-width = <0x04>;
+ sdio-id = <0x00>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ dma-noncoherent;
+ delay_code = <0x3b>;
+ drive-impedance-ohm = <0x21>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ no-sdio;
+ no-mmc;
+ disable-wp;
+ broken-cd;
+ };
+
+ // mmc@0x50470000 {
+ // compatible = "eswin,sdhci-sdio";
+ // reg = <0x00 0x50470000 0x00 0x10000>;
+ // interrupt-parent = <0x10>;
+ // interrupts = <0x53>;
+ // clocks = <0x03 0x22c 0x03 0x222 0x03 0x0c 0x03 0x23>;
+ // clock-names = "clk_xin\0clk_ahb\0clk_spll2_fout3\0clk_mux1_1";
+ // clock-output-names = "sdio1_cardclock";
+ // #clock-cells = <0x00>;
+ // resets = <0x14 0x07 0x100 0x14 0x07 0x20 0x14 0x07 0x20000 0x14 0x07 0x200000>;
+ // reset-names = "txrx_rst\0phy_rst\0prstn\0arstn";
+ // clock-frequency = <0xc65d400>;
+ // max-frequency = <0xc65d400>;
+ // #address-cells = <0x01>;
+ // #size-cells = <0x00>;
+ // dma-ranges = <0x00 0x20000000 0x00 0xc0000000 0x00 0x40000000>;
+ // iommus = <0x15 0x11>;
+ // tbus = <0x02>;
+ // eswin,hsp_sp_csr = <0x16 0x1040 0x708 0x70c>;
+ // eswin,syscrg_csr = <0x12 0x168 0x148 0x14c>;
+ // bus-width = <0x04>;
+ // sdio-id = <0x01>;
+ // numa-node-id = <0x00>;
+ // status = "okay";
+ // dma-noncoherent;
+ // delay_code = <0x29>;
+ // drive-impedance-ohm = <0x21>;
+ // enable-cmd-pullup;
+ // enable-data-pullup;
+ // keep-power-in-suspend;
+ // non-removable;
+ // no-sd;
+ // no-mmc;
+ // };
+
+ mbox@50a40000 {
+ compatible = "eswin,npu0-mailbox";
+ reg = <0x00 0x50a40000 0x00 0x10000 0x00 0x50a50000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x79>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x282 0x03 0x283>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x14 0x0c 0x10 0x14 0x0c 0x20>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x08>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x1e>;
+ };
+
+ mbox@50a80000 {
+ compatible = "eswin,dsp0-mailbox";
+ reg = <0x00 0x50a80000 0x00 0x10000 0x00 0x50a90000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x7d>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x286 0x03 0x287>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x14 0x0c 0x100 0x14 0x0c 0x200>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x20>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x23>;
+ };
+
+ mbox@50aa0000 {
+ compatible = "eswin,dsp1-mailbox";
+ reg = <0x00 0x50aa0000 0x00 0x10000 0x00 0x50ab0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x7f>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x288 0x03 0x289>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x14 0x0c 0x400 0x14 0x0c 0x800>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x40>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x24>;
+ };
+
+ mbox@50ac0000 {
+ compatible = "eswin,dsp2-mailbox";
+ reg = <0x00 0x50ac0000 0x00 0x10000 0x00 0x50ad0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x81>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x28a 0x03 0x28b>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x14 0x0c 0x1000 0x14 0x0c 0x2000>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x80>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x25>;
+ };
+
+ mbox@50ae0000 {
+ compatible = "eswin,dsp3-mailbox";
+ reg = <0x00 0x50ae0000 0x00 0x10000 0x00 0x50af0000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x83>;
+ #mbox-cells = <0x01>;
+ clocks = <0x03 0x28c 0x03 0x28d>;
+ clock-names = "pclk_mailbox_host\0pclk_mailbox_device";
+ resets = <0x14 0x0c 0x4000 0x14 0x0c 0x8000>;
+ reset-names = "rst\0rst_device";
+ lock-bit = <0x01>;
+ irq-bit = <0x100>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ phandle = <0x26>;
+ };
+
+ i2c@50960000 {
+ compatible = "snps,designware-i2c";
+ clock-frequency = <0x186a0>;
+ clocks = <0x03 0x28f>;
+ clock-names = "pclk";
+ resets = <0x14 0x09 0x02>;
+ reset-names = "rst";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x50960000 0x00 0x10000>;
+ interrupts = <0x6a>;
+ interrupt-parent = <0x10>;
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ es5430@f {
+ compatible = "einno,es5340";
+ reg = <0x0f>;
+ eswin,regulator_default-microvolt = <0xf4240>;
+ eswin,regulator_label = "supply vdd1\0npu vdd1\0npu current1\0npu temperature1";
+ label = "npu_vdd";
+
+ regulators {
+
+ npu_svcc {
+ regulator-name = "NPU_SVCC";
+ regulator-min-microvolt = <0xaae60>;
+ regulator-max-microvolt = <0x10c8e0>;
+ regulator-min-microamp = <0x1312d00>;
+ regulator-max-microamp = <0x2625a00>;
+ regulator-ov-protection-microvolt = <0x10c8e0>;
+ regulator-always-on;
+ phandle = <0x20>;
+ };
+ };
+ };
+ };
+
+ pinctrl@0x51600080 {
+ compatible = "eswin,eic7x-pinctrl\0syscon";
+ reg = <0x00 0x51600080 0x00 0x1fff80>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ phandle = <0x1a>;
+
+ emmc_led_control-default {
+ phandle = <0x2c>;
+
+ mux {
+ groups = "emmc_led_control_group";
+ function = "emmc_led_control_func";
+ };
+
+ conf {
+ groups = "emmc_led_control_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio16-default {
+ phandle = <0x1c>;
+
+ mux {
+ groups = "gpio16_group";
+ function = "gpio16_func";
+ };
+
+ conf {
+ groups = "gpio16_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio94-default {
+ phandle = <0x18>;
+
+ mux {
+ groups = "gpio94_group";
+ function = "gpio94_func";
+ };
+
+ conf {
+ groups = "gpio94_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+ };
+
+ gpio@51600000 {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x00 0x51600000 0x00 0x80>;
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ ngpios = <0x20>;
+ reg = <0x00>;
+ interrupt-parent = <0x10>;
+ interrupt-controller;
+ #interrupt-cells = <0x02>;
+ interrupts = <0x12f 0x130 0x131 0x132 0x133 0x134 0x135 0x136 0x137 0x138 0x139 0x13a 0x13b 0x13c 0x13d 0x13e 0x13f 0x140 0x141 0x142 0x143 0x144 0x145 0x146 0x147 0x148 0x149 0x14a 0x14b 0x14c 0x14d 0x14e>;
+ phandle = <0x1d>;
+ };
+
+
+ gpio-port@2 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ ngpios = <0x20>;
+ reg = <0x02>;
+ phandle = <0x19>;
+ };
+ };
+ };
+
+ aliases {
+ serial0 = "/soc/serial@0x50900000";
+ ethernet0 = "/soc/ethernet@50400000";
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "console=ttyS0,115200 earlycon=ttyS0,115200 root=PARTUUID=b0f77ad6-36cd-4a99-a8c0-31d73649aa09 rootfstype=ext4 rw rootwait init=/bin/bash";
+
+ domain-config {
+ compatible = "opensbi,domain,config";
+ system-suspend-test;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00 0x80000000 0x04 0x00>;
+ numa-node-id = <0x00>;
+ };
+
+ memory@59000000 {
+ device_type = "memory";
+ reg = <0x00 0x59000000 0x00 0x400000>;
+ numa-node-id = <0x00>;
+ };
+
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ opensbi@80000000 {
+ no-map;
+ reg = <0x00 0x80000000 0x00 0x00200000>;
+ };
+
+ sprammemory@59000000 {
+ no-map;
+ reg = <0x00 0x59000000 0x00 0x400000>;
+ phandle = <0x21>;
+ };
+
+ mmz_nid_0_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x03 0x00 0x01 0x80000000>;
+ no-map;
+ };
+
+ hvisor@80200000 {
+ no-map;
+ reg = <0x00 0x80200000 0x00 0x02E00000>;
+ };
+
+ nonroot@0x83000000 {
+ no-map;
+ reg = <0x00 0x83000000 0x00 0x0C000000>;
+ };
+
+ dtbfile@0x8f000000 {
+ no-map;
+ reg = <0x00 0x8f000000 0x00 0x01000000>;
+ };
+ };
+
+};
diff --git a/platform/riscv64/megrez/image/dts/zone0.dts b/platform/riscv64/megrez/image/dts/zone0.dts
new file mode 100644
index 00000000..da904289
--- /dev/null
+++ b/platform/riscv64/megrez/image/dts/zone0.dts
@@ -0,0 +1,507 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "sifive,hifive-unmatched-a00\0sifive,fu740-c000\0sifive,fu740\0eswin,eic7700";
+ model = "Milk-V Megrez";
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ timebase-frequency = <0xf4240>;
+
+ idle-states {
+
+ cpu-retentive {
+ compatible = "riscv,idle-state";
+ riscv,sbi-suspend-param = <0x00>;
+ entry-latency-us = <0x14>;
+ exit-latency-us = <0x28>;
+ min-residency-us = <0x50>;
+ phandle = <0x05>;
+ };
+ };
+
+ cpu@0 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x01>;
+ reg = <0x00>;
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x02>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f4>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0c>;
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "SiFive,FU800-soc\0fu800-soc\0sifive-soc\0simple-bus";
+ ranges;
+
+ cache-controller@2010000 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ cache-block-size = <0x40>;
+ cache-level = <0x03>;
+ cache-sets = <0x1000>;
+ cache-size = <0x400000>;
+ cache-unified;
+ compatible = "sifive,ccache1\0cache\0sifive,fu740-c000-ccache";
+ // interrupt-parent = <0x10>;
+ // interrupts = <0x01 0x03 0x04 0x02>;
+ reg = <0x00 0x2010000 0x00 0x4000 0x00 0x8000000 0x00 0x400000>;
+ reg-names = "control\0sideband";
+ sifive,a-mshr-count = <0x3c>;
+ sifive,bank-count = <0x04>;
+ sifive,ecc-granularity = <0x08>;
+ sifive,max-master-id = <0x0d>;
+ sifive,perfmon-counters = <0x06>;
+ numa-node-id = <0x00>;
+ ranges;
+ phandle = <0x11>;
+
+ zero-device@1a000000 {
+ compatible = "l3,zero-device";
+ reg = <0x00 0x1a000000 0x00 0x400000>;
+ };
+ };
+
+ interrupt-controller@c000000 {
+ #interrupt-cells = <0x01>;
+ compatible = "sifive,plic-1.0.0";
+ interrupt-controller;
+ interrupts-extended = <0x0c 0xffffffff 0x0c 0x09>;
+ reg = <0x00 0xc000000 0x00 0x4000000>;
+ reg-names = "control";
+ riscv,max-priority = <0x07>;
+ riscv,ndev = <0x208>;
+ numa-node-id = <0x00>;
+ phandle = <0x10>;
+ };
+
+ pl2@104000 {
+ cache-block-size = <0x40>;
+ cache-level = <0x02>;
+ cache-sets = <0x200>;
+ cache-size = <0x40000>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0\0cache";
+ next-level-cache = <0x11>;
+ reg = <0x00 0x104000 0x00 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <0x10>;
+ sifive,perfmon-counters = <0x06>;
+ numa-node-id = <0x00>;
+ phandle = <0x01>;
+ };
+
+ serial@0x50900000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00 0x50900000 0x00 0x10000>;
+ clock-frequency = <0xbebc200>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x64>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ phandle = <0x27>;
+ };
+
+ // serial@0x50920000 {
+ // compatible = "snps,dw-apb-uart";
+ // reg = <0x00 0x50920000 0x00 0x10000>;
+ // clock-frequency = <0xbebc200>;
+ // interrupt-parent = <0x10>;
+ // interrupts = <0x66>;
+ // reg-shift = <0x02>;
+ // reg-io-width = <0x04>;
+ // numa-node-id = <0x00>;
+ // status = "okay";
+ // };
+
+ sys-crg@51828000 {
+ compatible = "eswin,win2030-sys-crg\0syscon\0simple-mfd";
+ reg = <0x00 0x51828000 0x00 0x80000>;
+ numa-node-id = <0x00>;
+ phandle = <0x12>;
+
+ reset-controller {
+ compatible = "eswin,win2030-reset";
+ #reset-cells = <0x02>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ phandle = <0x14>;
+ };
+
+ clock-controller {
+ compatible = "eswin,win2030-clock";
+ #clock-cells = <0x01>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ force-1_8ghz;
+ phandle = <0x03>;
+ };
+ };
+
+ hsp_sp_top_csr@0x50440000 {
+ compatible = "eswin,win2030-hsp-sp-csr\0syscon";
+ numa-node-id = <0x00>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x50440000 0x00 0x2000>;
+ phandle = <0x16>;
+ };
+
+ ethernet@50400000 {
+ compatible = "eswin,win2030-qos-eth";
+ reg = <0x00 0x50400000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupt-names = "macirq";
+ interrupts = <0x3d>;
+ phy-mode = "rgmii";
+ numa-node-id = <0x00>;
+ id = <0x00>;
+ status = "okay";
+ clocks = <0x03 0x226 0x03 0x227 0x03 0x228>;
+ clock-names = "app\0stmmaceth\0tx";
+ resets = <0x14 0x07 0x4000000>;
+ reset-names = "ethrst";
+ // tbus = <0x02>;
+ dma-noncoherent;
+ eswin,hsp_sp_csr = <0x16 0x1030 0x100 0x108>;
+ eswin,syscrg_csr = <0x12 0x148 0x14c>;
+ eswin,dly_hsp_reg = <0x114 0x118 0x11c>;
+ snps,axi-config = <0x17>;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x18>;
+ rst-gpios = <0x19 0x1e 0x01>;
+ eswin,rgmiisel = <0x1a 0x290 0x03>;
+ eswin,led-cfgs = <0x6100 0xa40 0x420>;
+ dly-param-1000m = <0x23232323 0x800c8023 0xc0c0c0c>;
+ dly-param-100m = <0x50505050 0x803f8050 0x3f3f3f3f>;
+ dly-param-10m = <0x00 0x00 0x00>;
+
+ stmmac-axi-config {
+ snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
+ snps,rd_osr_lmt = <0x02>;
+ snps,wr_osr_lmt = <0x02>;
+ snps,lpi_en = <0x00>;
+ phandle = <0x17>;
+ };
+ };
+
+ // ethernet@50410000 {
+ // compatible = "eswin,win2030-qos-eth";
+ // reg = <0x00 0x50410000 0x00 0x10000>;
+ // interrupt-parent = <0x10>;
+ // interrupt-names = "macirq";
+ // interrupts = <0x46>;
+ // phy-mode = "rgmii";
+ // numa-node-id = <0x00>;
+ // id = <0x01>;
+ // status = "okay";
+ // clocks = <0x03 0x226 0x03 0x227 0x03 0x229>;
+ // clock-names = "app\0stmmaceth\0tx";
+ // resets = <0x14 0x07 0x2000000>;
+ // reset-names = "ethrst";
+ // tbus = <0x02>;
+ // dma-noncoherent;
+ // eswin,hsp_sp_csr = <0x16 0x1034 0x200 0x208>;
+ // eswin,syscrg_csr = <0x12 0x148 0x14c>;
+ // eswin,dly_hsp_reg = <0x214 0x218 0x21c>;
+ // snps,axi-config = <0x1b>;
+ // pinctrl-names = "default";
+ // pinctrl-0 = <0x1c>;
+ // rst-gpios = <0x1d 0x10 0x01>;
+ // eswin,rgmiisel = <0x1a 0x294 0x03>;
+ // eswin,led-cfgs = <0x6100 0xa40 0x420>;
+ // dly-param-1000m = <0x25252525 0x80268025 0x26262626>;
+ // dly-param-100m = <0x48484848 0x80588048 0x58585858>;
+ // dly-param-10m = <0x00 0x00 0x00>;
+
+ // stmmac-axi-config {
+ // snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
+ // snps,rd_osr_lmt = <0x02>;
+ // snps,wr_osr_lmt = <0x02>;
+ // snps,lpi_en = <0x00>;
+ // phandle = <0x1b>;
+ // };
+ // };
+
+ // sata@0x50420000 {
+ // compatible = "snps,eswin-ahci";
+ // reg = <0x00 0x50420000 0x00 0x10000>;
+ // interrupt-parent = <0x10>;
+ // interrupt-names = "intrq\0msi\0pme";
+ // interrupts = <0x3a 0x3b 0x3c>;
+ // ports-implemented = <0x01>;
+ // resets = <0x14 0x07 0x8000000>;
+ // reset-names = "apb";
+ // #size-cells = <0x02>;
+ // iommus = <0x15 0x0e>;
+ // tbus = <0x02>;
+ // dma-ranges = <0x00 0x00 0x00 0xc0000000 0x200 0x00>;
+ // eswin,hsp_sp_csr = <0x16 0x1050>;
+ // eswin,syscrg_csr = <0x12 0x41c>;
+ // numa-node-id = <0x00>;
+ // dma-noncoherent;
+ // status = "okay";
+ // pinctrl-names = "default";
+ // pinctrl-0 = <0x29>;
+ // };
+
+ // mmc@50450000 {
+ // compatible = "eswin,emmc-sdhci-5.1";
+ // reg = <0x00 0x50450000 0x00 0x10000>;
+ // interrupt-parent = <0x10>;
+ // interrupts = <0x4f>;
+ // assigned-clocks = <0x03 0x22a>;
+ // assigned-clock-rates = <0xbebc200>;
+ // clocks = <0x03 0x22a 0x03 0x222>;
+ // clock-names = "clk_xin\0clk_ahb";
+ // clock-output-names = "emmc_cardclock";
+ // #clock-cells = <0x00>;
+ // resets = <0x14 0x07 0x40 0x14 0x07 0x08 0x14 0x07 0x80000 0x14 0x07 0x800000>;
+ // reset-names = "txrx_rst\0phy_rst\0prstn\0arstn";
+ // core-clk-reg = <0x51828160>;
+ // disable-cqe-dcmd;
+ // bus-width = <0x08>;
+ // non-removable;
+ // mmc-hs400-1_8v;
+ // max-frequency = <0xbebc200>;
+ // #size-cells = <0x02>;
+ // iommus = <0x15 0x0f>;
+ // tbus = <0x02>;
+ // dma-ranges = <0x00 0x00 0x00 0xc0000000 0x01 0x00>;
+ // eswin,hsp_sp_csr = <0x16 0x1038 0x508 0x50c>;
+ // eswin,syscrg_csr = <0x12 0x160 0x148 0x14c>;
+ // status = "okay";
+ // numa-node-id = <0x00>;
+ // dma-noncoherent;
+ // delay_code = <0x17>;
+ // drive-impedance-ohm = <0x32>;
+ // enable-cmd-pullup;
+ // enable-data-pullup;
+ // pinctrl-names = "default";
+ // pinctrl-0 = <0x2c>;
+ // no-sdio;
+ // no-sd;
+ // };
+
+ mmc@0x50460000 {
+ compatible = "eswin,sdhci-sdio";
+ reg = <0x00 0x50460000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x51>;
+ clocks = <0x03 0x22b 0x03 0x222 0x03 0x0c 0x03 0x23>;
+ clock-names = "clk_xin\0clk_ahb\0clk_spll2_fout3\0clk_mux1_1";
+ clock-output-names = "sdio0_cardclock";
+ #clock-cells = <0x00>;
+ resets = <0x14 0x07 0x80 0x14 0x07 0x10 0x14 0x07 0x40000 0x14 0x07 0x400000>;
+ reset-names = "txrx_rst\0phy_rst\0prstn\0arstn";
+ clock-frequency = <0xc65d400>;
+ max-frequency = <0xc65d400>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ dma-ranges = <0x00 0x20000000 0x00 0xc0000000 0x00 0x40000000>;
+ // iommus = <0x15 0x10>;
+ // tbus = <0x02>;
+ eswin,hsp_sp_csr = <0x16 0x103c 0x608 0x60c>;
+ eswin,syscrg_csr = <0x12 0x164 0x148 0x14c>;
+ bus-width = <0x04>;
+ sdio-id = <0x00>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ dma-noncoherent;
+ delay_code = <0x3b>;
+ drive-impedance-ohm = <0x21>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ no-sdio;
+ no-mmc;
+ disable-wp;
+ broken-cd;
+ };
+
+
+ pinctrl@0x51600080 {
+ compatible = "eswin,eic7x-pinctrl\0syscon";
+ reg = <0x00 0x51600080 0x00 0x1fff80>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ phandle = <0x1a>;
+
+ emmc_led_control-default {
+ phandle = <0x2c>;
+
+ mux {
+ groups = "emmc_led_control_group";
+ function = "emmc_led_control_func";
+ };
+
+ conf {
+ groups = "emmc_led_control_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio16-default {
+ phandle = <0x1c>;
+
+ mux {
+ groups = "gpio16_group";
+ function = "gpio16_func";
+ };
+
+ conf {
+ groups = "gpio16_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+
+ gpio94-default {
+ phandle = <0x18>;
+
+ mux {
+ groups = "gpio94_group";
+ function = "gpio94_func";
+ };
+
+ conf {
+ groups = "gpio94_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+ };
+
+ gpio@51600000 {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x00 0x51600000 0x00 0x80>;
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ ngpios = <0x20>;
+ reg = <0x00>;
+ interrupt-parent = <0x10>;
+ interrupt-controller;
+ #interrupt-cells = <0x02>;
+ interrupts = <0x12f 0x130 0x131 0x132 0x133 0x134 0x135 0x136 0x137 0x138 0x139 0x13a 0x13b 0x13c 0x13d 0x13e 0x13f 0x140 0x141 0x142 0x143 0x144 0x145 0x146 0x147 0x148 0x149 0x14a 0x14b 0x14c 0x14d 0x14e>;
+ phandle = <0x1d>;
+ };
+
+ gpio-port@2 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ ngpios = <0x20>;
+ reg = <0x02>;
+ phandle = <0x19>;
+ };
+ };
+
+ };
+
+
+ hvisor_virtio_device {
+ compatible = "hvisor";
+ interrupt-parent = <0x10>;
+ interrupts = <0x20>;
+ };
+
+ aliases {
+ serial0 = "/soc/serial@0x50900000";
+ // serial2 = "/soc/serial@0x50920000";
+ ethernet0 = "/soc/ethernet@50400000";
+ // ethernet1 = "/soc/ethernet@50410000";
+ };
+
+ chosen {
+ bootargs = "earlycon console=ttyS0,115200 root=/dev/mmcblk0p3 rootfstype=ext4 rw rootwait init=/bin/bash";
+ stdout-path = "serial0:115200n8";
+ // bootargs = "earlycon console=ttyS2,115200 root=/dev/mmcblk0p3 rootfstype=ext4 rw rootwait init=/bin/bash";
+ // stdout-path = "serial2:115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00 0x80000000 0x00 0x80000000>;
+ numa-node-id = <0x00>;
+ };
+
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ opensbi@80000000 {
+ no-map;
+ reg = <0x00 0x80000000 0x00 0x00200000>;
+ };
+
+ hvisor@80200000 {
+ no-map;
+ reg = <0x00 0x80200000 0x00 0x02E00000>;
+ };
+
+ nonroot@0x83000000 {
+ no-map;
+ reg = <0x00 0x83000000 0x00 0x0C000000>;
+ };
+
+ dtbfile@0x8f000000 {
+ no-map;
+ reg = <0x00 0x8f000000 0x00 0x01000000>;
+ };
+ };
+
+};
diff --git a/platform/riscv64/megrez/image/dts/zone1-linux.dts b/platform/riscv64/megrez/image/dts/zone1-linux.dts
new file mode 100644
index 00000000..73407084
--- /dev/null
+++ b/platform/riscv64/megrez/image/dts/zone1-linux.dts
@@ -0,0 +1,324 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "sifive,hifive-unmatched-a00\0sifive,fu740-c000\0sifive,fu740\0eswin,eic7700";
+ model = "Milk-V Megrez";
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ timebase-frequency = <0xf4240>;
+
+ idle-states {
+
+ cpu-retentive {
+ compatible = "riscv,idle-state";
+ riscv,sbi-suspend-param = <0x00>;
+ entry-latency-us = <0x14>;
+ exit-latency-us = <0x28>;
+ min-residency-us = <0x50>;
+ phandle = <0x05>;
+ };
+ };
+
+ cpu@1 {
+ clock-frequency = <0x00>;
+ compatible = "eswin,eic770x\0riscv";
+ d-cache-block-size = <0x40>;
+ d-cache-sets = <0x80>;
+ d-cache-size = <0x8000>;
+ d-tlb-sets = <0x01>;
+ d-tlb-size = <0x20>;
+ device_type = "cpu";
+ hardware-exec-breakpoint-count = <0x04>;
+ hwpf-distanceBits = <0x06>;
+ hwpf-hitCacheThrdBits = <0x05>;
+ hwpf-hitMSHRThrdBits = <0x04>;
+ hwpf-l2pfPoolSize = <0x0a>;
+ hwpf-nIssQEnt = <0x06>;
+ hwpf-nPrefetchQueueEntries = <0x08>;
+ hwpf-nStreams = <0x10>;
+ hwpf-qFullnessThrdBits = <0x04>;
+ hwpf-windowBits = <0x06>;
+ i-cache-block-size = <0x40>;
+ i-cache-sets = <0x80>;
+ i-cache-size = <0x8000>;
+ i-tlb-sets = <0x01>;
+ i-tlb-size = <0x20>;
+ mmu-type = "riscv,sv48";
+ next-level-cache = <0x06>;
+ reg = <0x01>;
+ riscv,isa = "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf";
+ riscv,pmpgranularity = <0x1000>;
+ riscv,pmpregions = <0x08>;
+ sifive,buserror = <0x07>;
+ status = "okay";
+ timebase-frequency = <0xf4240>;
+ tlb-split;
+ numa-node-id = <0x00>;
+ clocks = <0x03 0x1f5>;
+ operating-points-v2 = <0x04>;
+ #cooling-cells = <0x02>;
+ dynamic-power-coefficient = <0x144>;
+ cpu-idle-states = <0x05>;
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ phandle = <0x0d>;
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "SiFive,FU800-soc\0fu800-soc\0sifive-soc\0simple-bus";
+ ranges;
+
+ cache-controller@2010000 {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ cache-block-size = <0x40>;
+ cache-level = <0x03>;
+ cache-sets = <0x1000>;
+ cache-size = <0x400000>;
+ cache-unified;
+ compatible = "sifive,ccache1\0cache\0sifive,fu740-c000-ccache";
+ // interrupt-parent = <0x10>;
+ // interrupts = <0x01 0x03 0x04 0x02>;
+ reg = <0x00 0x2010000 0x00 0x4000 0x00 0x8000000 0x00 0x400000>;
+ reg-names = "control\0sideband";
+ sifive,a-mshr-count = <0x3c>;
+ sifive,bank-count = <0x04>;
+ sifive,ecc-granularity = <0x08>;
+ sifive,max-master-id = <0x0d>;
+ sifive,perfmon-counters = <0x06>;
+ numa-node-id = <0x00>;
+ ranges;
+ phandle = <0x11>;
+
+ zero-device@1a000000 {
+ compatible = "l3,zero-device";
+ reg = <0x00 0x1a000000 0x00 0x400000>;
+ };
+ };
+
+ interrupt-controller@c000000 {
+ #interrupt-cells = <0x01>;
+ compatible = "sifive,plic-1.0.0";
+ interrupt-controller;
+ interrupts-extended = <0x0d 0xffffffff 0x0d 0x09>;
+ reg = <0x00 0xc000000 0x00 0x4000000>;
+ reg-names = "control";
+ riscv,max-priority = <0x07>;
+ riscv,ndev = <0x208>;
+ numa-node-id = <0x00>;
+ phandle = <0x10>;
+ };
+
+ pl2@108000 {
+ cache-block-size = <0x40>;
+ cache-level = <0x02>;
+ cache-sets = <0x200>;
+ cache-size = <0x40000>;
+ cache-unified;
+ compatible = "sifive,pL2Cache0\0cache";
+ next-level-cache = <0x11>;
+ reg = <0x00 0x108000 0x00 0x4000>;
+ reg-names = "control";
+ sifive,ecc-granularity = <0x10>;
+ sifive,perfmon-counters = <0x06>;
+ numa-node-id = <0x00>;
+ phandle = <0x06>;
+ };
+
+ serial@0x50920000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00 0x50920000 0x00 0x10000>;
+ clock-frequency = <0xbebc200>;
+ interrupt-parent = <0x10>;
+ interrupts = <0x66>;
+ reg-shift = <0x02>;
+ reg-io-width = <0x04>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ };
+
+ sys-crg@51828000 {
+ compatible = "eswin,win2030-sys-crg\0syscon\0simple-mfd";
+ reg = <0x00 0x51828000 0x00 0x80000>;
+ numa-node-id = <0x00>;
+ phandle = <0x12>;
+
+ reset-controller {
+ compatible = "eswin,win2030-reset";
+ #reset-cells = <0x02>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ phandle = <0x14>;
+ };
+
+ clock-controller {
+ compatible = "eswin,win2030-clock";
+ #clock-cells = <0x01>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ force-1_8ghz;
+ phandle = <0x03>;
+ };
+ };
+
+ hsp_sp_top_csr@0x50440000 {
+ compatible = "eswin,win2030-hsp-sp-csr\0syscon";
+ numa-node-id = <0x00>;
+ #size-cells = <0x02>;
+ reg = <0x00 0x50440000 0x00 0x2000>;
+ phandle = <0x16>;
+ };
+
+
+ ethernet@50410000 {
+ compatible = "eswin,win2030-qos-eth";
+ reg = <0x00 0x50410000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupt-names = "macirq";
+ interrupts = <0x46>;
+ phy-mode = "rgmii";
+ numa-node-id = <0x00>;
+ id = <0x01>;
+ status = "okay";
+ clocks = <0x03 0x226 0x03 0x227 0x03 0x229>;
+ clock-names = "app\0stmmaceth\0tx";
+ resets = <0x14 0x07 0x2000000>;
+ reset-names = "ethrst";
+ // tbus = <0x02>;
+ dma-noncoherent;
+ eswin,hsp_sp_csr = <0x16 0x1034 0x200 0x208>;
+ eswin,syscrg_csr = <0x12 0x148 0x14c>;
+ eswin,dly_hsp_reg = <0x214 0x218 0x21c>;
+ snps,axi-config = <0x1b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x1c>;
+ rst-gpios = <0x1d 0x10 0x01>;
+ eswin,rgmiisel = <0x1a 0x294 0x03>;
+ eswin,led-cfgs = <0x6100 0xa40 0x420>;
+ dly-param-1000m = <0x25252525 0x80268025 0x26262626>;
+ dly-param-100m = <0x48484848 0x80588048 0x58585858>;
+ dly-param-10m = <0x00 0x00 0x00>;
+
+ stmmac-axi-config {
+ snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
+ snps,rd_osr_lmt = <0x02>;
+ snps,wr_osr_lmt = <0x02>;
+ snps,lpi_en = <0x00>;
+ phandle = <0x1b>;
+ };
+ };
+
+ sata@0x50420000 {
+ compatible = "snps,eswin-ahci";
+ reg = <0x00 0x50420000 0x00 0x10000>;
+ interrupt-parent = <0x10>;
+ interrupt-names = "intrq\0msi\0pme";
+ interrupts = <0x3a 0x3b 0x3c>;
+ ports-implemented = <0x01>;
+ resets = <0x14 0x07 0x8000000>;
+ reset-names = "apb";
+ #size-cells = <0x02>;
+ // iommus = <0x15 0x0e>;
+ // tbus = <0x02>;
+ // dma-ranges = <0x00 0x00 0x00 0xc0000000 0x200 0x00>;
+ eswin,hsp_sp_csr = <0x16 0x1050>;
+ eswin,syscrg_csr = <0x12 0x41c>;
+ numa-node-id = <0x00>;
+ dma-noncoherent;
+ status = "okay";
+ // pinctrl-names = "default";
+ // pinctrl-0 = <0x29>;
+ };
+
+ // virtio_mmio@10006000 {
+ // interrupts = <0x06>;
+ // interrupt-parent = <0x10>;
+ // reg = <0x00 0x10006000 0x00 0x1000>;
+ // compatible = "virtio,mmio";
+ // };
+
+ // virtio_mmio@10007000 {
+ // interrupts = <0x07>;
+ // interrupt-parent = <0x10>;
+ // reg = <0x00 0x10007000 0x00 0x1000>;
+ // compatible = "virtio,mmio";
+ // };
+
+ pinctrl@0x51600080 {
+ compatible = "eswin,eic7x-pinctrl\0syscon";
+ reg = <0x00 0x51600080 0x00 0x1fff80>;
+ numa-node-id = <0x00>;
+ status = "okay";
+ phandle = <0x1a>;
+
+ gpio16-default {
+ phandle = <0x1c>;
+
+ mux {
+ groups = "gpio16_group";
+ function = "gpio16_func";
+ };
+
+ conf {
+ groups = "gpio16_group";
+ input-enable = <0x00>;
+ bias-pull-down = <0x01>;
+ };
+ };
+ };
+
+ gpio@51600000 {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x00 0x51600000 0x00 0x80>;
+ numa-node-id = <0x00>;
+ status = "okay";
+
+ gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ ngpios = <0x20>;
+ reg = <0x00>;
+ interrupt-parent = <0x10>;
+ interrupt-controller;
+ #interrupt-cells = <0x02>;
+ interrupts = <0x12f 0x130 0x131 0x132 0x133 0x134 0x135 0x136 0x137 0x138 0x139 0x13a 0x13b 0x13c 0x13d 0x13e 0x13f 0x140 0x141 0x142 0x143 0x144 0x145 0x146 0x147 0x148 0x149 0x14a 0x14b 0x14c 0x14d 0x14e>;
+ phandle = <0x1d>;
+ };
+ };
+
+ };
+
+ aliases {
+ // serial0 = "/soc/serial@0x50900000";
+ serial2 = "/soc/serial@0x50920000";
+ // virtio-console = "/soc/virtio_mmio@10007000";
+ ethernet1 = "/soc/ethernet@50410000";
+ };
+
+ chosen {
+ // bootargs = "earlycon console=hvc0 root=/dev/vda rootfstype=ext4 rw rootwait";
+ // stdout-path = "virtio-console";
+ bootargs = "earlycon console=ttyS2,115200 root=/dev/sda3 rootfstype=ext4 rw rootwait init=/bin/bash";
+ stdout-path = "serial2:115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00 0x83000000 0x00 0x0C000000>;
+ numa-node-id = <0x00>;
+ };
+};
diff --git a/platform/riscv64/megrez/linker.ld b/platform/riscv64/megrez/linker.ld
new file mode 100644
index 00000000..eb62b0fe
--- /dev/null
+++ b/platform/riscv64/megrez/linker.ld
@@ -0,0 +1,50 @@
+ENTRY(arch_entry)
+BASE_ADDRESS = 0x80200000;
+
+
+SECTIONS
+{
+ . = BASE_ADDRESS;
+ skernel = .;
+
+ stext = .;
+ .text : {
+ *(.text.entry)
+ *(.text .text.*)
+ }
+
+ . = ALIGN(4K);
+ etext = .;
+ srodata = .;
+ .rodata : {
+ *(.rodata .rodata.*)
+ *(.srodata .srodata.*)
+ }
+
+ . = ALIGN(4K);
+ erodata = .;
+ sdata = .;
+ .data : {
+ *(.data .data.*)
+ *(.sdata .sdata.*)
+ }
+
+ . = ALIGN(4K);
+ edata = .;
+ .bss : {
+ *(.bss.stack)
+ sbss = .;
+ *(.bss .bss.*)
+ *(.sbss .sbss.*)
+ }
+
+ . = ALIGN(4K);
+ ebss = .;
+ ekernel = .;
+
+ /DISCARD/ : {
+ *(.eh_frame)
+ }
+ . = ALIGN(4K);
+ __core_end = .;
+}
\ No newline at end of file
diff --git a/platform/riscv64/megrez/native.txt b/platform/riscv64/megrez/native.txt
new file mode 100644
index 00000000..c3a0d426
--- /dev/null
+++ b/platform/riscv64/megrez/native.txt
@@ -0,0 +1,9 @@
+setenv serverip 192.168.1.150;
+setenv ipaddr 192.168.1.200;
+setenv netmask 255.255.255.0;
+setenv fdt_addr 0x8f000000;
+setenv ker_addr 0x90000000;
+tftpboot ${fdt_addr} ${serverip}:minimal.dtb;
+tftpboot ${ker_addr} ${serverip}:uImage;
+bootm ${ker_addr} - ${fdt_addr};
+
diff --git a/platform/riscv64/megrez/platform.mk b/platform/riscv64/megrez/platform.mk
new file mode 100644
index 00000000..ae62a65e
--- /dev/null
+++ b/platform/riscv64/megrez/platform.mk
@@ -0,0 +1,17 @@
+
+# HVISOR ENTRY
+HVISOR_ENTRY_PA := 0x80200000
+BOOT_PATH := $(image_dir)/../
+
+
+$(hvisor_bin): elf
+ @if ! command -v mkimage > /dev/null; then \
+ sudo apt update && sudo apt install u-boot-tools; \
+ fi && \
+ $(OBJCOPY) $(hvisor_elf) --strip-all -O binary $(hvisor_bin).tmp && \
+ mkimage -n hvisor_img -A riscv -O linux -C none -T kernel -a $(HVISOR_ENTRY_PA) \
+ -e $(HVISOR_ENTRY_PA) -d $(hvisor_bin).tmp $(hvisor_bin) && \
+ rm -rf $(hvisor_bin).tmp
+
+mkscr:
+ mkimage -A arm -T script -C none -n "Boot Script" -d $(BOOT_PATH)boot.txt $(BOOT_PATH)boot.scr
\ No newline at end of file
diff --git a/platform/riscv64/megrez/scirpts/boot_zone1.sh b/platform/riscv64/megrez/scirpts/boot_zone1.sh
new file mode 100755
index 00000000..8202c0b5
--- /dev/null
+++ b/platform/riscv64/megrez/scirpts/boot_zone1.sh
@@ -0,0 +1,4 @@
+insmod hvisor.ko
+mount -t proc /proc /proc
+mount -t sysfs /sys /sys
+./hvisor zone start zone1-linux.json
diff --git a/platform/riscv64/megrez/scirpts/screen_zone1.sh b/platform/riscv64/megrez/scirpts/screen_zone1.sh
new file mode 100755
index 00000000..4388535f
--- /dev/null
+++ b/platform/riscv64/megrez/scirpts/screen_zone1.sh
@@ -0,0 +1,5 @@
+screen_output=$(cat nohup.out | grep "char device")
+echo "$screen_output"
+device=$(echo "$screen_output" | awk '{print $NF}')
+echo "$device"
+screen -S screen_linux2 $device
diff --git a/platform/riscv64/qemu-aia/board.rs b/platform/riscv64/qemu-aia/board.rs
index bca3b8ff..61dcce29 100644
--- a/platform/riscv64/qemu-aia/board.rs
+++ b/platform/riscv64/qemu-aia/board.rs
@@ -24,15 +24,12 @@ pub const ACLINT_SSWI_BASE: usize = 0x2F00000;
// This device is used for qemu-quit.
pub const SIFIVE_TEST_BASE: u64 = 0x100000;
-pub const PLIC_BASE: usize = 0xc000000;
pub const APLIC_BASE: usize = 0xc000000;
-pub const PLIC_MAX_IRQ: usize = 1024;
-pub const PLIC_GLOBAL_SIZE: usize = 0x200000;
-pub const PLIC_TOTAL_SIZE: usize = 0x400000;
-pub const PLIC_MAX_CONTEXT: usize = 64;
-pub const PLIC_PRIORITY_BASE: usize = 0x0000;
-pub const PLIC_PENDING_BASE: usize = 0x1000;
-pub const PLIC_ENABLE_BASE: usize = 0x2000;
+pub const BOARD_APLIC_INTERRUPTS_NUM: usize = 1023;
+pub const IMSIC_S_BASE: usize = 0x2800_0000;
+pub const IMSIC_GUEST_NUM: usize = 1; // hvisor only supports 1 guest now.
+pub const IMSIC_GUEST_INDEX: usize = 1;
+pub const IMSIC_NUM_IDS: usize = 0xFF;
pub const ROOT_ZONE_DTB_ADDR: u64 = 0x8f000000;
pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x90000000;
@@ -98,6 +95,7 @@ pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 9] = [
}, // virtio
];
+pub const HW_IRQS: [u32; 11] = [1, 2, 3, 4, 5, 8, 10, 33, 34, 35, 36];
pub const ROOT_ZONE_IRQS: [u32; 11] = [1, 2, 3, 4, 5, 8, 10, 33, 34, 35, 36]; // ARCH= riscv .It doesn't matter temporarily.
pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig {
diff --git a/platform/riscv64/qemu-aia/image/dts/virt.dts b/platform/riscv64/qemu-aia/image/dts/virt.dts
new file mode 100644
index 00000000..6197376b
--- /dev/null
+++ b/platform/riscv64/qemu-aia/image/dts/virt.dts
@@ -0,0 +1,327 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "riscv-virtio";
+ model = "riscv-virtio,qemu";
+
+ poweroff {
+ value = <0x5555>;
+ offset = <0x00>;
+ regmap = <0x0d>;
+ compatible = "syscon-poweroff";
+ };
+
+ reboot {
+ value = <0x7777>;
+ offset = <0x00>;
+ regmap = <0x0d>;
+ compatible = "syscon-reboot";
+ };
+
+ platform-bus@4000000 {
+ interrupt-parent = <0x0c>;
+ ranges = <0x00 0x00 0x4000000 0x2000000>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "qemu,platform\0simple-bus";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00 0x80000000 0x00 0x80000000>;
+ };
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ timebase-frequency = <0x989680>;
+
+ cpu@0 {
+ phandle = <0x07>;
+ device_type = "cpu";
+ reg = <0x00>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,cbop-block-size = <0x40>;
+ riscv,cboz-block-size = <0x40>;
+ riscv,cbom-block-size = <0x40>;
+ riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihintntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd\0zba\0zbb\0zbc\0zbs\0smaia\0ssaia\0ssccptr\0sscounterenw\0sstc\0sstvala\0sstvecd\0svadu\0svvptc";
+ riscv,isa-base = "rv64i";
+ riscv,isa = "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_smaia_ssaia_ssccptr_sscounterenw_sstc_sstvala_sstvecd_svadu_svvptc";
+ mmu-type = "riscv,sv57";
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ phandle = <0x08>;
+ };
+ };
+
+ cpu@1 {
+ phandle = <0x05>;
+ device_type = "cpu";
+ reg = <0x01>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,cbop-block-size = <0x40>;
+ riscv,cboz-block-size = <0x40>;
+ riscv,cbom-block-size = <0x40>;
+ riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihintntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd\0zba\0zbb\0zbc\0zbs\0smaia\0ssaia\0ssccptr\0sscounterenw\0sstc\0sstvala\0sstvecd\0svadu\0svvptc";
+ riscv,isa-base = "rv64i";
+ riscv,isa = "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_smaia_ssaia_ssccptr_sscounterenw_sstc_sstvala_sstvecd_svadu_svvptc";
+ mmu-type = "riscv,sv57";
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ phandle = <0x06>;
+ };
+ };
+
+ cpu@2 {
+ phandle = <0x03>;
+ device_type = "cpu";
+ reg = <0x02>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,cbop-block-size = <0x40>;
+ riscv,cboz-block-size = <0x40>;
+ riscv,cbom-block-size = <0x40>;
+ riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihintntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd\0zba\0zbb\0zbc\0zbs\0smaia\0ssaia\0ssccptr\0sscounterenw\0sstc\0sstvala\0sstvecd\0svadu\0svvptc";
+ riscv,isa-base = "rv64i";
+ riscv,isa = "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_smaia_ssaia_ssccptr_sscounterenw_sstc_sstvala_sstvecd_svadu_svvptc";
+ mmu-type = "riscv,sv57";
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ phandle = <0x04>;
+ };
+ };
+
+ cpu@3 {
+ phandle = <0x01>;
+ device_type = "cpu";
+ reg = <0x03>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,cbop-block-size = <0x40>;
+ riscv,cboz-block-size = <0x40>;
+ riscv,cbom-block-size = <0x40>;
+ riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihintntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd\0zba\0zbb\0zbc\0zbs\0smaia\0ssaia\0ssccptr\0sscounterenw\0sstc\0sstvala\0sstvecd\0svadu\0svvptc";
+ riscv,isa-base = "rv64i";
+ riscv,isa = "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_smaia_ssaia_ssccptr_sscounterenw_sstc_sstvala_sstvecd_svadu_svvptc";
+ mmu-type = "riscv,sv57";
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ phandle = <0x02>;
+ };
+ };
+
+ cpu-map {
+
+ cluster0 {
+
+ core0 {
+ cpu = <0x07>;
+ };
+
+ core1 {
+ cpu = <0x05>;
+ };
+
+ core2 {
+ cpu = <0x03>;
+ };
+
+ core3 {
+ cpu = <0x01>;
+ };
+ };
+ };
+ };
+
+ pmu {
+ riscv,event-to-mhpmcounters = <0x01 0x01 0x7fff9 0x02 0x02 0x7fffc 0x10019 0x10019 0x7fff8 0x1001b 0x1001b 0x7fff8 0x10021 0x10021 0x7fff8>;
+ compatible = "riscv,pmu";
+ };
+
+ fw-cfg@10100000 {
+ dma-coherent;
+ reg = <0x00 0x10100000 0x00 0x18>;
+ compatible = "qemu,fw-cfg-mmio";
+ };
+
+ flash@20000000 {
+ bank-width = <0x04>;
+ reg = <0x00 0x20000000 0x00 0x2000000 0x00 0x22000000 0x00 0x2000000>;
+ compatible = "cfi-flash";
+ };
+
+ chosen {
+ stdout-path = "/soc/serial@10000000";
+ rng-seed = <0xbc910764 0xbb4865ed 0x33a78ccd 0xeeeb809c 0xf3a8c22c 0xb1993bfb 0xcae1b78a 0x709d4b21>;
+ };
+
+ soc {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "simple-bus";
+ ranges;
+
+ rtc@101000 {
+ interrupts = <0x0b 0x04>;
+ interrupt-parent = <0x0c>;
+ reg = <0x00 0x101000 0x00 0x1000>;
+ compatible = "google,goldfish-rtc";
+ };
+
+ serial@10000000 {
+ interrupts = <0x0a 0x04>;
+ interrupt-parent = <0x0c>;
+ clock-frequency = "\08@";
+ reg = <0x00 0x10000000 0x00 0x100>;
+ compatible = "ns16550a";
+ };
+
+ test@100000 {
+ phandle = <0x0d>;
+ reg = <0x00 0x100000 0x00 0x1000>;
+ compatible = "sifive,test1\0sifive,test0\0syscon";
+ };
+
+ virtio_mmio@10008000 {
+ interrupts = <0x08 0x04>;
+ interrupt-parent = <0x0c>;
+ reg = <0x00 0x10008000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10007000 {
+ interrupts = <0x07 0x04>;
+ interrupt-parent = <0x0c>;
+ reg = <0x00 0x10007000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10006000 {
+ interrupts = <0x06 0x04>;
+ interrupt-parent = <0x0c>;
+ reg = <0x00 0x10006000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10005000 {
+ interrupts = <0x05 0x04>;
+ interrupt-parent = <0x0c>;
+ reg = <0x00 0x10005000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10004000 {
+ interrupts = <0x04 0x04>;
+ interrupt-parent = <0x0c>;
+ reg = <0x00 0x10004000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10003000 {
+ interrupts = <0x03 0x04>;
+ interrupt-parent = <0x0c>;
+ reg = <0x00 0x10003000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10002000 {
+ interrupts = <0x02 0x04>;
+ interrupt-parent = <0x0c>;
+ reg = <0x00 0x10002000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10001000 {
+ interrupts = <0x01 0x04>;
+ interrupt-parent = <0x0c>;
+ reg = <0x00 0x10001000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ interrupt-controller@d000000 {
+ phandle = <0x0c>;
+ riscv,num-sources = <0x60>;
+ reg = <0x00 0xd000000 0x00 0x8000>;
+ msi-parent = <0x0a>;
+ interrupt-controller;
+ #interrupt-cells = <0x02>;
+ #address-cells = <0x00>;
+ compatible = "qemu,aplic\0riscv,aplic";
+ };
+
+ interrupt-controller@c000000 {
+ phandle = <0x0b>;
+ riscv,delegate = <0x0c 0x01 0x60>;
+ riscv,delegation = <0x0c 0x01 0x60>;
+ riscv,children = <0x0c>;
+ riscv,num-sources = <0x60>;
+ reg = <0x00 0xc000000 0x00 0x8000>;
+ msi-parent = <0x09>;
+ interrupt-controller;
+ #interrupt-cells = <0x02>;
+ #address-cells = <0x00>;
+ compatible = "qemu,aplic\0riscv,aplic";
+ };
+
+ interrupt-controller@28000000 {
+ phandle = <0x0a>;
+ riscv,guest-index-bits = <0x01>;
+ riscv,num-ids = <0xff>;
+ reg = <0x00 0x28000000 0x00 0x8000>;
+ interrupts-extended = <0x08 0x09 0x06 0x09 0x04 0x09 0x02 0x09>;
+ msi-controller;
+ interrupt-controller;
+ #interrupt-cells = <0x00>;
+ compatible = "qemu,imsics\0riscv,imsics";
+ };
+
+ interrupt-controller@24000000 {
+ phandle = <0x09>;
+ riscv,num-ids = <0xff>;
+ reg = <0x00 0x24000000 0x00 0x4000>;
+ interrupts-extended = <0x08 0x0b 0x06 0x0b 0x04 0x0b 0x02 0x0b>;
+ msi-controller;
+ interrupt-controller;
+ #interrupt-cells = <0x00>;
+ compatible = "qemu,imsics\0riscv,imsics";
+ };
+
+ mtimer@2000000 {
+ interrupts-extended = <0x08 0x07 0x06 0x07 0x04 0x07 0x02 0x07>;
+ reg = <0x00 0x2007ff8 0x00 0x08 0x00 0x2000000 0x00 0x7ff8>;
+ compatible = "riscv,aclint-mtimer";
+ };
+
+ pci@30000000 {
+ interrupt-map-mask = <0x1800 0x00 0x00 0x07>;
+ interrupt-map = <0x00 0x00 0x00 0x01 0x0c 0x20 0x04 0x00 0x00 0x00 0x02 0x0c 0x21 0x04 0x00 0x00 0x00 0x03 0x0c 0x22 0x04 0x00 0x00 0x00 0x04 0x0c 0x23 0x04 0x800 0x00 0x00 0x01 0x0c 0x21 0x04 0x800 0x00 0x00 0x02 0x0c 0x22 0x04 0x800 0x00 0x00 0x03 0x0c 0x23 0x04 0x800 0x00 0x00 0x04 0x0c 0x20 0x04 0x1000 0x00 0x00 0x01 0x0c 0x22 0x04 0x1000 0x00 0x00 0x02 0x0c 0x23 0x04 0x1000 0x00 0x00 0x03 0x0c 0x20 0x04 0x1000 0x00 0x00 0x04 0x0c 0x21 0x04 0x1800 0x00 0x00 0x01 0x0c 0x23 0x04 0x1800 0x00 0x00 0x02 0x0c 0x20 0x04 0x1800 0x00 0x00 0x03 0x0c 0x21 0x04 0x1800 0x00 0x00 0x04 0x0c 0x22 0x04>;
+ ranges = <0x1000000 0x00 0x00 0x00 0x3000000 0x00 0x10000 0x2000000 0x00 0x40000000 0x00 0x40000000 0x00 0x40000000 0x3000000 0x04 0x00 0x04 0x00 0x04 0x00>;
+ reg = <0x00 0x30000000 0x00 0x10000000>;
+ msi-parent = <0x0a>;
+ dma-coherent;
+ bus-range = <0x00 0xff>;
+ linux,pci-domain = <0x00>;
+ device_type = "pci";
+ compatible = "pci-host-ecam-generic";
+ #size-cells = <0x02>;
+ #interrupt-cells = <0x01>;
+ #address-cells = <0x03>;
+ };
+ };
+};
diff --git a/src/arch/aarch64/consts.rs b/src/arch/aarch64/consts.rs
new file mode 100644
index 00000000..5bfd0825
--- /dev/null
+++ b/src/arch/aarch64/consts.rs
@@ -0,0 +1,20 @@
+// Copyright (c) 2025 Syswonder
+// hvisor is licensed under Mulan PSL v2.
+// You can use this software according to the terms and conditions of the Mulan PSL v2.
+// You may obtain a copy of Mulan PSL v2 at:
+// http://license.coscl.org.cn/MulanPSL2
+// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+// FIT FOR A PARTICULAR PURPOSE.
+// See the Mulan PSL v2 for more details.
+//
+// Syswonder Website:
+// https://www.syswonder.org
+//
+// Authors:
+// ForeverYolo <2572131118@qq.com>
+
+// PCI constants
+pub const HV_ADDR_PREFIX: u64 = 0;
+pub const LOONG_HT_PREFIX: u64 = 0;
+pub const BDF_SHIFT: usize = 12;
diff --git a/src/arch/aarch64/cpu.rs b/src/arch/aarch64/cpu.rs
index 6e2b98e2..f7498c7a 100644
--- a/src/arch/aarch64/cpu.rs
+++ b/src/arch/aarch64/cpu.rs
@@ -15,12 +15,13 @@
//
use crate::{
arch::{mm::new_s2_memory_set, sysreg::write_sysreg},
- consts::{PAGE_SIZE, PER_CPU_ARRAY_PTR, PER_CPU_SIZE},
+ consts::{MAX_CPU_NUM, PAGE_SIZE, PER_CPU_ARRAY_PTR, PER_CPU_SIZE},
memory::{
addr::PHYS_VIRT_OFFSET, mm::PARKING_MEMORY_SET, GuestPhysAddr, HostPhysAddr, MemFlags,
MemoryRegion, VirtAddr, PARKING_INST_PAGE,
},
percpu::this_cpu_data,
+ platform::BOARD_MPIDR_MAPPINGS,
};
use aarch64_cpu::registers::{
Readable, Writeable, ELR_EL2, HCR_EL2, MPIDR_EL1, SCTLR_EL1, SPSR_EL2, VTCR_EL2,
@@ -32,8 +33,16 @@ use super::{
trap::vmreturn,
};
+pub const MPIDR_MASK: u64 = 0xff00ffffff;
+
pub fn cpu_start(cpuid: usize, start_addr: usize, opaque: usize) {
- psci::cpu_on(cpuid as u64 | 0x80000000, start_addr as _, opaque as _).unwrap_or_else(|err| {
+ let new_cpuid = {
+ if cpuid >= MAX_CPU_NUM {
+ panic!("Invalid cpuid: {}", cpuid);
+ }
+ BOARD_MPIDR_MAPPINGS[cpuid]
+ };
+ psci::cpu_on(new_cpuid, start_addr as _, opaque as _).unwrap_or_else(|err| {
if let psci::error::Error::AlreadyOn = err {
} else {
panic!("can't wake up cpu {}", cpuid);
@@ -59,6 +68,7 @@ impl GeneralRegisters {
#[derive(Debug)]
pub struct ArchCpu {
pub cpuid: usize,
+ pub is_aarch32: bool,
pub power_on: bool,
}
@@ -66,6 +76,7 @@ impl ArchCpu {
pub fn new(cpuid: usize) -> Self {
Self {
cpuid,
+ is_aarch32: false,
power_on: false,
}
}
@@ -76,7 +87,14 @@ impl ArchCpu {
self.cpuid, entry, dtb
);
ELR_EL2.set(entry as _);
- SPSR_EL2.set(0x3c5);
+ SPSR_EL2.write(
+ SPSR_EL2::D::SET
+ + SPSR_EL2::A::SET
+ + SPSR_EL2::I::SET
+ + SPSR_EL2::F::SET
+ + SPSR_EL2::M::EL1h,
+ );
+
let regs = self.guest_reg();
regs.clear();
regs.usr[0] = dtb as _; // dtb addr
@@ -157,9 +175,8 @@ impl ArchCpu {
write_sysreg!(CNTV_CTL_EL0, 0);
write_sysreg!(CNTV_CVAL_EL0, 0);
write_sysreg!(CNTV_TVAL_EL0, 0);
- // //disable stage 1
- // write_sysreg!(SCTLR_EL1, 0);
+ // Disable EL1 MMU and all caches.
SCTLR_EL1.set((1 << 11) | (1 << 20) | (3 << 22) | (3 << 28));
}
@@ -167,6 +184,19 @@ impl ArchCpu {
assert!(this_cpu_id() == self.cpuid);
this_cpu_data().activate_gpm();
self.reset(this_cpu_data().cpu_on_entry, this_cpu_data().dtb_ipa);
+ if self.is_aarch32 {
+ info!("cpu {} is aarch32", self.cpuid);
+ // if guest runs at aarch32, set these registers to aarch32 mode
+ HCR_EL2.write(
+ HCR_EL2::RW::AllLowerELsAreAarch32
+ + HCR_EL2::TSC::EnableTrapEl1SmcToEl2
+ + HCR_EL2::VM::SET
+ + HCR_EL2::IMO::SET
+ + HCR_EL2::FMO::SET,
+ );
+ // Return to AArch32 Supervisor (SVC) mode, disable IRQ, FIQ, ABT
+ SPSR_EL2.set(0x1D3);
+ }
self.power_on = true;
info!(
"cpu {} started at {:#x?}",
@@ -215,13 +245,26 @@ impl ArchCpu {
}
pub fn mpidr_to_cpuid(mpidr: u64) -> u64 {
- if cfg!(feature = "mpidr_rockchip") {
- (mpidr >> 8) & 0xff
- } else {
- mpidr & 0xff00ffffff
- }
+ let mpidr = mpidr & MPIDR_MASK;
+ (0..MAX_CPU_NUM)
+ .find(|&i| BOARD_MPIDR_MAPPINGS[i] == mpidr)
+ .unwrap() as u64
+}
+
+pub fn cpuid_to_mpidr_affinity(cpuid: u64) -> (u64, u64, u64, u64) {
+ let mpidr = BOARD_MPIDR_MAPPINGS[cpuid as usize];
+ let aff3 = (mpidr >> 32) & 0xff;
+ let aff2 = (mpidr >> 16) & 0xff;
+ let aff1 = (mpidr >> 8) & 0xff;
+ let aff0 = mpidr & 0xff;
+ (aff3, aff2, aff1, aff0)
}
pub fn this_cpu_id() -> usize {
mpidr_to_cpuid(MPIDR_EL1.get()) as _
}
+
+pub fn store_cpu_pointer_to_reg(pointer: usize) {
+ // println!("aarch64 doesn't support store cpu pointer to reg, pointer: {:#x}", pointer);
+ return;
+}
diff --git a/src/arch/aarch64/entry.rs b/src/arch/aarch64/entry.rs
index e5ebcdfd..45c443e4 100644
--- a/src/arch/aarch64/entry.rs
+++ b/src/arch/aarch64/entry.rs
@@ -14,12 +14,14 @@
// Authors:
//
use crate::consts::PER_CPU_SIZE;
+use crate::platform::BOARD_MPIDR_MAPPINGS;
+
+const INVALID_CPUID: usize = (-1) as _;
-//global_asm!(include_str!("boot_pt.S"));
#[naked]
#[no_mangle]
#[link_section = ".text.entry"]
-pub unsafe extern "C" fn arch_entry() -> i32 {
+pub unsafe extern "C" fn arch_entry() -> ! {
unsafe {
core::arch::asm!(
"
@@ -34,11 +36,11 @@ pub unsafe extern "C" fn arch_entry() -> i32 {
nop
nop
- bl {boot_cpuid_get}
+ bl {boot_cpuid_get} // x17 = cpuid
- adrp x2, __core_end // x2 = &__core_end
- mov x3, {per_cpu_size} // x3 = per_cpu_size
- madd x4, x17, x3, x3 // x4 = cpuid * per_cpu_size
+ adrp x2, __core_end // x2 = &__core_end
+ mov x3, {per_cpu_size} // x3 = per_cpu_size
+ madd x4, x17, x3, x3 // x4 = cpuid * per_cpu_size
add x5, x2, x4
mov sp, x5 // sp = &__core_end + (cpuid + 1) * per_cpu_size
@@ -63,24 +65,14 @@ pub unsafe extern "C" fn arch_entry() -> i32 {
// ic iallu
bl {clear_bss}
-
- //bl boot_pt_init
- adrp x0, {BOOT_PT_L0}
- adrp x1, {BOOT_PT_L1}
bl {boot_pt_init}
1:
- adrp x0, {BOOT_PT_L0}
- bl {mmu_init}
bl {mmu_enable}
- tlbi alle2
- dsb nsh
- isb
-
mov x1, x18
mov x0, x17
- mov x18, 0
- mov x17, 0
+ mov x18, #0
+ mov x17, #0
bl {rust_main} // x0 = cpuid, x1 = dtbaddr
",
options(noreturn),
@@ -89,40 +81,47 @@ pub unsafe extern "C" fn arch_entry() -> i32 {
per_cpu_size = const PER_CPU_SIZE,
rust_main = sym crate::rust_main,
clear_bss = sym crate::clear_bss,
- BOOT_PT_L0 = sym super::mmu::BOOT_PT_L0,
- BOOT_PT_L1 = sym super::mmu::BOOT_PT_L1,
boot_pt_init = sym super::mmu::boot_pt_init,
- mmu_init = sym super::mmu::mmu_init,
mmu_enable = sym super::mmu::mmu_enable,
);
}
}
-#[cfg(feature = "mpidr_rockchip")]
#[naked]
#[no_mangle]
pub unsafe extern "C" fn boot_cpuid_get() {
- core::arch::asm!(
- "
- mrs x17, mpidr_el1
- lsr x17, x17, #0x8
- and x17, x17, #0xff
- ret
- ",
- options(noreturn)
- )
-}
+ use crate::arch::cpu;
-#[cfg(not(feature = "mpidr_rockchip"))]
-#[naked]
-#[no_mangle]
-pub unsafe extern "C" fn boot_cpuid_get() {
core::arch::asm!(
"
mrs x17, mpidr_el1
- and x17, x17, #0xff
+ ldr x2, ={mpidr_mask}
+ and x17, x17, x2
+ adr x2, {mpidr_mappings}
+ mov x4, #0
+ 1:
+ // search for the mpidr_el1 mapping in BOARD_MPIDR_MAPPINGS.
+ ldr x3, [x2]
+ cmp x17, x3
+ b.eq 3f
+ add x2, x2, #8
+ add x4, x4, #1
+ cmp x4, {ncpus}
+ b.ne 1b
+ 2:
+ // failed to get cpuid, return an invalid id, and spin in an infinite loop.
+ mov x17, {inv_id}
+ wfi
+ b 2b
+ 3:
+ // found cpuid, return it.
+ mov x17, x4
ret
",
+ mpidr_mask = const cpu::MPIDR_MASK,
+ mpidr_mappings = sym BOARD_MPIDR_MAPPINGS,
+ ncpus = const crate::consts::MAX_CPU_NUM,
+ inv_id = const INVALID_CPUID,
options(noreturn)
)
}
diff --git a/src/arch/aarch64/hypercall.rs b/src/arch/aarch64/hypercall.rs
new file mode 100644
index 00000000..68eb755f
--- /dev/null
+++ b/src/arch/aarch64/hypercall.rs
@@ -0,0 +1,82 @@
+// Copyright (c) 2025 Syswonder
+// hvisor is licensed under Mulan PSL v2.
+// You can use this software according to the terms and conditions of the Mulan PSL v2.
+// You may obtain a copy of Mulan PSL v2 at:
+// http://license.coscl.org.cn/MulanPSL2
+// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+// FIT FOR A PARTICULAR PURPOSE.
+// See the Mulan PSL v2 for more details.
+//
+// Syswonder Website:
+// https://www.syswonder.org
+//
+// Authors:
+// ForeverYolo <2572131118@qq.com>
+
+use crate::arch::cpu::this_cpu_id;
+use crate::arch::ivc::{IvcInfo, IVC_INFOS};
+use crate::config::{HvZoneConfig, CONFIG_MAGIC_VERSION};
+use crate::device::virtio_trampoline::MAX_DEVS;
+use crate::hypercall::HyperCall;
+use crate::hypercall::HyperCallResult;
+use crate::percpu::this_zone;
+use crate::zone::this_zone_id;
+
+impl<'a> HyperCall<'a> {
+ pub fn hv_ivc_info(&mut self, ivc_info_ipa: u64) -> HyperCallResult {
+ let zone_id = this_zone_id();
+ let zone = this_zone();
+ // ipa->hpa->hva
+ let hpa = unsafe {
+ zone.read()
+ .gpm
+ .page_table_query(ivc_info_ipa as _)
+ .unwrap()
+ .0
+ };
+ // hva == hpa
+ let ivc_info = unsafe { &mut *(hpa as *mut IvcInfo) };
+ let ivc_infos = IVC_INFOS.lock();
+ let zone_ivc_info = ivc_infos.get(&(zone_id as _));
+ match zone_ivc_info {
+ Some(zone_ivc_info) => *ivc_info = *zone_ivc_info,
+ None => return hv_result_err!(ENODEV, "Zone {zone_id} has no ivc config!"),
+ }
+ HyperCallResult::Ok(0)
+ }
+
+ pub fn translate_ipa_to_hva(&mut self, ipa: u64) -> u64 {
+ return ipa;
+ }
+
+ pub fn wait_for_interrupt(&mut self, irq_list: &mut [u64; MAX_DEVS + 1]) {
+ trace!("wait_for_interrupt is not need for AArch64");
+ }
+
+ pub fn hv_zone_config_check(&self, magic_version: *mut u64) -> HyperCallResult {
+ unsafe {
+ *magic_version = CONFIG_MAGIC_VERSION as _;
+ }
+ debug!(
+ "hv_zone_config_check: finished writing current magic version ({:#x})",
+ CONFIG_MAGIC_VERSION
+ );
+ HyperCallResult::Ok(0)
+ }
+
+ pub fn hv_get_real_pa(&mut self, config_addr: u64) -> u64 {
+ // AArch64 does not have a specific prefix for cached memory, so we return the address as is.
+ return config_addr;
+ }
+
+ pub fn hv_get_real_list_pa(&mut self, list_addr: u64) -> u64 {
+ // RISC-V does not have a specific prefix for cached memory, so we return the address as is.
+ return list_addr;
+ }
+
+ pub fn check_cpu_id(&self) {
+ let cpuid = this_cpu_id();
+ trace!("CPU ID: {} Start Zone", cpuid);
+ }
+}
diff --git a/src/arch/aarch64/iommu.rs b/src/arch/aarch64/iommu.rs
index 50b22e81..6773d2f7 100644
--- a/src/arch/aarch64/iommu.rs
+++ b/src/arch/aarch64/iommu.rs
@@ -582,8 +582,13 @@ static SMMUV3: spin::Once> = spin::Once::new();
/// smmuv3 init
pub fn iommu_init() {
- info!("Smmuv3 init...");
- SMMUV3.call_once(|| Mutex::new(Smmuv3::new()));
+ #[cfg(feature = "iommu")]
+ {
+ info!("Smmuv3 init...");
+ SMMUV3.call_once(|| Mutex::new(Smmuv3::new()));
+ }
+ #[cfg(not(feature = "iommu"))]
+ info!("Smmuv3 init: do nothing now");
}
/// smmuv3_base
@@ -600,6 +605,14 @@ pub fn smmuv3_size() -> usize {
/// write ste
pub fn iommu_add_device(vmid: usize, sid: usize) {
- let mut smmu = SMMUV3.get().unwrap().lock();
- smmu.write_ste(sid as _, vmid as _);
+ #[cfg(feature = "iommu")]
+ {
+ let mut smmu = SMMUV3.get().unwrap().lock();
+ smmu.write_ste(sid as _, vmid as _);
+ }
+ #[cfg(not(feature = "iommu"))]
+ info!(
+ "aarch64: iommu_add_device: do nothing now, vmid: {}, sid: {}",
+ vmid, sid
+ );
}
diff --git a/src/arch/aarch64/ipi.rs b/src/arch/aarch64/ipi.rs
index a8ef2e46..a0aa0ab8 100644
--- a/src/arch/aarch64/ipi.rs
+++ b/src/arch/aarch64/ipi.rs
@@ -14,43 +14,22 @@
// Authors:
//
-#[cfg(feature = "gicv3")]
-use crate::arch::sysreg::write_sysreg;
-#[cfg(feature = "gicv2")]
-use crate::device::irqchip::set_sgi_irq;
+use crate::device::irqchip::gic_send_event;
pub fn arch_send_event(cpu_id: u64, sgi_num: u64) {
- #[cfg(feature = "gicv3")]
- {
- /*Actually, the value passed to ICC_SGI1R_EL1 should be derived from
- the MPIDR of the target CPU. However, since we cannot access this
- register on the sender side, we have reverse-engineered a value
- here using the cpu_id.
- Due to differences in how some CPU implementations (e.g., RK3568 and RK3588)
- encode affinity values in MPIDR, we use conditional compilation to handle
- platform-specific mappings between cpu_id and interrupt target affinity.
- */
- let aff3: u64 = 0 << 48;
- let aff2: u64 = 0 << 32;
- let aff1: u64;
- let target_list: u64;
+ gic_send_event(cpu_id, sgi_num);
+}
- if cfg!(feature = "mpidr_rockchip") {
- aff1 = cpu_id << 16;
- target_list = 1 << 0;
- } else {
- aff1 = 0 << 16;
- target_list = 1 << cpu_id;
+pub fn arch_check_events(event: Option) {
+ match event {
+ _ => {
+ info!(
+ "aarch64: arch_check_events: event={:#x?} do nothing now",
+ event
+ );
}
- let irm: u64 = 0 << 40;
- let sgi_id: u64 = sgi_num << 24;
- let val: u64 = aff1 | aff2 | aff3 | irm | sgi_id | target_list;
- write_sysreg!(icc_sgi1r_el1, val);
- debug!("write sgi sys value = {:#x}", val);
- }
- #[cfg(feature = "gicv2")]
- {
- let sgi_id: u64 = sgi_num;
- let target_list: u64 = 1 << cpu_id;
- set_sgi_irq(sgi_id as usize, target_list as usize, 0);
}
}
+
+pub fn arch_prepare_send_event(cpu_id: usize, ipi_int_id: usize, event_id: usize) {
+ debug!("aarch64 arch_prepare_send_event: do nothing now.")
+}
diff --git a/src/ivc.rs b/src/arch/aarch64/ivc.rs
similarity index 100%
rename from src/ivc.rs
rename to src/arch/aarch64/ivc.rs
diff --git a/src/arch/aarch64/mm.rs b/src/arch/aarch64/mm.rs
index 6ea1a335..9acdae18 100644
--- a/src/arch/aarch64/mm.rs
+++ b/src/arch/aarch64/mm.rs
@@ -25,7 +25,7 @@ const PARANGE_TABLE: [usize; 6] = [32, 36, 40, 42, 44, 48];
static MIN_PARANGE: RwLock = RwLock::new(0x7);
static PARANGE_OK_CPUS: AtomicU32 = AtomicU32::new(0);
-pub fn setup_parange() {
+pub fn arch_setup_parange() {
let temp_parange = read_sysreg!(id_aa64mmfr0_el1) & 0xf;
let mut p = MIN_PARANGE.write();
*p = p.min(temp_parange);
diff --git a/src/arch/aarch64/mmu.rs b/src/arch/aarch64/mmu.rs
index 614aa462..199d2e56 100644
--- a/src/arch/aarch64/mmu.rs
+++ b/src/arch/aarch64/mmu.rs
@@ -15,13 +15,22 @@
//
#![allow(unused)]
+use core::ptr::addr_of;
+use core::{mem, panic};
+
+use aarch64_cpu::registers::CSSELR_EL1::Level::L1;
+use aarch64_cpu::registers::PAR_EL1::PA;
use cfg_if::cfg_if;
use cortex_a::registers::SCTLR_EL2;
use tock_registers::interfaces::*;
use tock_registers::*;
+use crate::arch::mmu::S1PageAndBlockDescriptor::VALID;
+use crate::memory::addr::is_aligned;
+use crate::memory::AlignedPage;
+
register_bitfields! {u64,
- pub S1PageAndBlockDescriptor [
+ S1PageAndBlockDescriptor [
RES OFFSET(55) NUMBITS(4) [],
UXN OFFSET(54) NUMBITS(1) [
False = 0,
@@ -71,7 +80,8 @@ const PAGE_SHIFT: usize = 12;
const WORD_SIZE: usize = 8;
const ENTRY_PER_PAGE: usize = PAGE_SIZE / WORD_SIZE;
-enum MemoryType {
+#[derive(PartialEq, Clone, Copy)]
+pub enum MemoryType {
Normal,
Device,
Null,
@@ -125,92 +135,123 @@ impl PTEDescriptor {
}
}
+const MAX_PT_L1_PAGES: usize = 16;
+
#[repr(C)]
#[repr(align(4096))]
-pub struct PageTables {
+struct BootPTPagePool([u8; MAX_PT_L1_PAGES * PAGE_SIZE]);
+
+static mut BOOT_PT_L1_PAGE_POOL: BootPTPagePool = BootPTPagePool([0; MAX_PT_L1_PAGES * PAGE_SIZE]);
+static mut BOOT_PT_INDEX: usize = 0;
+
+const L1_SHIFT: u64 = 21;
+const L0_SHIFT: u64 = 30;
+
+const L1_SZ: u64 = 1 << L1_SHIFT;
+const L0_SZ: u64 = 1 << L0_SHIFT;
+
+#[repr(C)]
+#[repr(align(4096))]
+struct PageTables {
entry: [PTEDescriptor; ENTRY_PER_PAGE],
}
-// l1 page table
-pub static BOOT_PT_L0: PageTables = PageTables {
+static mut BOOT_PT_L0: PageTables = PageTables {
entry: [PTEDescriptor(0); ENTRY_PER_PAGE],
};
-// l2 page table
-pub static BOOT_PT_L1: PageTables = PageTables {
- entry: [PTEDescriptor(0); ENTRY_PER_PAGE],
-};
+fn check_list(list: &[(u64, u64, MemoryType)]) {
+ unsafe { assert!(is_aligned(addr_of!(BOOT_PT_L1_PAGE_POOL.0) as _)) };
+ assert!(MAX_PT_L1_PAGES > 0);
-//TODO: use memset from crate
-pub unsafe fn memset(s: *mut u8, c: i32, n: usize) {
- if (s as usize) < 0x1000 {
- panic!("illegal addr for memset s {:x}", s as usize);
+ for i in 0..list.len() {
+ // each addr should align to 2M
+ if list[i].0 % L1_SZ != 0 || list[i].1 % L1_SZ != 0 {
+ panic!("memory list addr not align to 2M at index {}", i);
+ }
+ if i < list.len() - 1 && list[i].1 > list[i + 1].0 {
+ panic!("memory list addr not sorted at index {}", i);
+ }
}
- core::ptr::write_bytes(s, c as u8, n);
}
-// #[link_section = ".text.boot"]
-pub extern "C" fn boot_pt_init(l0_pt: &mut PageTables, l1_pt: &mut PageTables) {
- let l0_pt_entry: usize = l0_pt as *const _ as usize;
- let l1_pt_entry: usize = l1_pt as *const _ as usize;
+unsafe fn map_l1_page(addr: usize, l0_index: usize, l1_index: usize, mem_type: MemoryType) {
+ let l0_entry = &mut BOOT_PT_L0.entry[l0_index];
+ let l1_pt_addr = if (l0_entry.0 & 0x1 == 0) {
+ // l1 page table not exist, create it
+ if BOOT_PT_INDEX >= MAX_PT_L1_PAGES {
+ panic!("boot pt page pool is full");
+ }
+ let l1_pt_addr = BOOT_PT_L1_PAGE_POOL
+ .0
+ .as_ptr()
+ .add(BOOT_PT_INDEX * PAGE_SIZE) as u64;
+ BOOT_PT_INDEX += 1;
+ *l0_entry = PTEDescriptor::new(l1_pt_addr as _, MemoryType::Null, PTEType::Page);
+ l1_pt_addr
+ } else {
+ l0_entry.0 & !(PAGE_SIZE as u64 - 1)
+ };
+ assert!(is_aligned(l1_pt_addr as _));
+ (*(l1_pt_addr as *mut PageTables)).entry[l1_index] =
+ PTEDescriptor::new(addr, mem_type, PTEType::Block);
+}
- unsafe {
- memset(l0_pt_entry as *mut u8, 0, PAGE_SIZE);
- memset(l1_pt_entry as *mut u8, 0, PAGE_SIZE);
- }
- cfg_if! {
- if #[cfg(feature = "pt_layout_qemu")] {
- l0_pt.entry[0] = PTEDescriptor::new(0x0, MemoryType::Device, PTEType::Block);
- for i in 1..ENTRY_PER_PAGE {
- l0_pt.entry[i] = PTEDescriptor::new(0x40000000*i, MemoryType::Normal, PTEType::Block);
- }
- } else if #[cfg(any(feature = "pt_layout_rk3568",
- feature = "pt_layout_rk3588",
- feature = "pt_layout_zcu102"))] {
- // EMMC fe310000 0xfe200000-0xfe400000
- // GIC fd400000 0xfd400000-0xfd600000
- // UART fe660000 0xfe600000-0xfe800000
- const L2_SHIFT: usize = 21;
- l0_pt.entry[0] = PTEDescriptor::new(0x0, MemoryType::Normal, PTEType::Block);
- l0_pt.entry[1] = PTEDescriptor::new(0x40000000, MemoryType::Normal, PTEType::Block);
- l0_pt.entry[2] = PTEDescriptor::new(0x80000000, MemoryType::Normal, PTEType::Block);
- l0_pt.entry[3] = PTEDescriptor::new(l1_pt_entry, MemoryType::Null, PTEType::Page);
- // 0xc0000000 ~ 0xf0000000
- const DEVICE_BOUND: usize = (0xf0000000 - 0xc0000000) / (1 << L2_SHIFT);
- for i in 0..DEVICE_BOUND {
- l1_pt.entry[i] = PTEDescriptor::new(
- 0x0c0000000 + (i << L2_SHIFT),
- MemoryType::Normal,
- PTEType::Block,
- );
- }
- // 0xf0000000 ~ 0x10000_0000
- for i in DEVICE_BOUND..ENTRY_PER_PAGE {
- l1_pt.entry[i] = PTEDescriptor::new(
- 0x0c0000000 + (i << L2_SHIFT),
- MemoryType::Device,
- PTEType::Block,
- );
- }
- for i in 4..ENTRY_PER_PAGE {
- l0_pt.entry[i] = PTEDescriptor::new(0x40000000*i, MemoryType::Normal, PTEType::Block);
+unsafe fn map_l0_page(addr: usize, l0_index: usize, mem_type: MemoryType) {
+ assert!(addr as u64 % L0_SZ == 0);
+ let l0_entry = &mut BOOT_PT_L0.entry[l0_index];
+ *l0_entry = PTEDescriptor::new(addr, mem_type, PTEType::Block);
+}
+
+fn map_range(mut start: u64, end: u64, mem_type: MemoryType) {
+ assert!(start <= end, "Start address is greater than end address");
+ assert!(start % L1_SZ == 0, "Start address is not align to 2M");
+ assert!(end % L1_SZ == 0, "End address is not align to 2M");
+
+ while (start < end) {
+ let l0_index = start >> L0_SHIFT;
+ let l1_index = (start >> L1_SHIFT) & (ENTRY_PER_PAGE as u64 - 1);
+ if (l0_index >= ENTRY_PER_PAGE as _) || (l1_index >= ENTRY_PER_PAGE as _) {
+ panic!("l0_index or l1_index out of range");
+ }
+
+ if (l1_index == 0 && start + L0_SZ <= end) {
+ // we can directly map l0 page table here
+ unsafe {
+ map_l0_page(start as _, l0_index as _, mem_type);
}
+ start += L0_SZ;
} else {
- l0_pt.entry[0] = PTEDescriptor::new(0x0, MemoryType::Device, PTEType::Block);
- for i in 1..7 {
- l0_pt.entry[i] = PTEDescriptor::new(0x40000000*i, MemoryType::Normal, PTEType::Block);
- }
- for i in 8..ENTRY_PER_PAGE {
- l0_pt.entry[i] = PTEDescriptor::invalid();
+ unsafe {
+ map_l1_page(start as _, l0_index as _, l1_index as _, mem_type);
}
+ start += L1_SZ;
+ }
+ }
+}
+
+fn map_list(list: &[(u64, u64, MemoryType)]) {
+ let mut i = 0;
+
+ while i < list.len() {
+ let (start, mut end, mem_type) = list[i];
+ while i + 1 < list.len() && list[i + 1].0 == end && list[i + 1].2 == mem_type {
+ end = list[i].1;
+ i += 1;
}
+ // map from start to end with mem_type
+ map_range(start, end, mem_type);
+ i += 1;
}
}
-// init mmu
-// #[link_section = ".text.boot"]
-#[no_mangle]
-pub extern "C" fn mmu_init(pt: &PageTables) {
+pub extern "C" fn boot_pt_init() {
+ let phys_memlist = &crate::platform::BOARD_PHYSMEM_LIST;
+ check_list(phys_memlist);
+ map_list(phys_memlist);
+}
+
+pub extern "C" fn mmu_enable() {
use cortex_a::registers::*;
MAIR_EL2.write(
MAIR_EL2::Attr0_Device::nonGathering_nonReordering_noEarlyWriteAck
@@ -219,7 +260,8 @@ pub extern "C" fn mmu_init(pt: &PageTables) {
+ MAIR_EL2::Attr2_Normal_Outer::NonCacheable
+ MAIR_EL2::Attr2_Normal_Inner::NonCacheable,
);
- TTBR0_EL2.set(&pt.entry as *const _ as u64);
+
+ TTBR0_EL2.set(unsafe { &BOOT_PT_L0.entry } as *const _ as u64);
TCR_EL2.write(
TCR_EL2::PS::Bits_48
@@ -229,9 +271,11 @@ pub extern "C" fn mmu_init(pt: &PageTables) {
+ TCR_EL2::IRGN0::WriteBack_ReadAlloc_WriteAlloc_Cacheable
+ TCR_EL2::T0SZ.val(64 - 39),
);
-}
-
-// #[link_section = ".text.boot"]
-pub extern "C" fn mmu_enable() {
SCTLR_EL2.modify(SCTLR_EL2::M::Enable + SCTLR_EL2::C::Cacheable + SCTLR_EL2::I::Cacheable);
+
+ unsafe {
+ core::arch::asm!("tlbi alle2");
+ core::arch::asm!("dsb nsh");
+ core::arch::asm!("isb");
+ }
}
diff --git a/src/arch/aarch64/mod.rs b/src/arch/aarch64/mod.rs
index 70bdf070..85bd3d21 100644
--- a/src/arch/aarch64/mod.rs
+++ b/src/arch/aarch64/mod.rs
@@ -13,10 +13,13 @@
//
// Authors:
//
+pub mod consts;
pub mod cpu;
pub mod entry;
+pub mod hypercall;
pub mod iommu;
pub mod ipi;
+pub mod ivc;
pub mod mm;
pub mod mmu;
pub mod paging;
@@ -25,4 +28,5 @@ pub mod sysreg;
pub mod trap;
pub mod zone;
+pub use s2pt::stage2_mode_detect;
pub use s2pt::Stage2PageTable;
diff --git a/src/arch/aarch64/s2pt.rs b/src/arch/aarch64/s2pt.rs
index 02bf8569..9e947a11 100644
--- a/src/arch/aarch64/s2pt.rs
+++ b/src/arch/aarch64/s2pt.rs
@@ -228,3 +228,7 @@ impl PagingInstr for S2PTInstr {
}
pub type Stage2PageTable = HvPageTable;
+
+pub fn stage2_mode_detect() {
+ info!("Dynamical detection of stage-2 paging mode is not supported yet.");
+}
diff --git a/src/arch/aarch64/trap.S b/src/arch/aarch64/trap.S
index 60ee0e87..7e6abb29 100644
--- a/src/arch/aarch64/trap.S
+++ b/src/arch/aarch64/trap.S
@@ -52,6 +52,8 @@ EXIT_REASON_EL2_ABORT =0x0
EXIT_REASON_EL2_IRQ =0x1
EXIT_REASON_EL1_ABORT =0x2
EXIT_REASON_EL1_IRQ =0x3
+EXIT_REASON_EL1_AARCH32_ABORT =0x4
+EXIT_REASON_EL1_AARCH32_IRQ =0x5
.global _hyp_trap_vector
.align 11
@@ -71,7 +73,7 @@ _hyp_trap_vector:
ventry .
ventry .
- ventry .
- ventry .
+ handle_vmexit EXIT_REASON_EL1_AARCH32_ABORT
+ handle_vmexit EXIT_REASON_EL1_AARCH32_IRQ
ventry .
ventry .
\ No newline at end of file
diff --git a/src/arch/aarch64/trap.rs b/src/arch/aarch64/trap.rs
index 74280e91..e49146e0 100644
--- a/src/arch/aarch64/trap.rs
+++ b/src/arch/aarch64/trap.rs
@@ -45,6 +45,8 @@ pub mod ExceptionType {
pub const EXIT_REASON_EL2_IRQ: u64 = 0x1;
pub const EXIT_REASON_EL1_ABORT: u64 = 0x2;
pub const EXIT_REASON_EL1_IRQ: u64 = 0x3;
+ pub const EXIT_REASON_EL1_AARCH32_ABORT: u64 = 0x4;
+ pub const EXIT_REASON_EL1_AARCH32_IRQ: u64 = 0x5;
}
const SMC_TYPE_MASK: u64 = 0x3F000000;
#[allow(non_snake_case)]
@@ -109,8 +111,12 @@ pub fn arch_handle_exit(regs: &mut GeneralRegisters) -> ! {
let _cpu_id = mpidr_to_cpuid(mpidr);
trace!("cpu exit, exit_reson:{:#x?}", regs.exit_reason);
match regs.exit_reason as u64 {
- ExceptionType::EXIT_REASON_EL1_IRQ => irqchip_handle_irq1(),
- ExceptionType::EXIT_REASON_EL1_ABORT => arch_handle_trap_el1(regs),
+ ExceptionType::EXIT_REASON_EL1_IRQ | ExceptionType::EXIT_REASON_EL1_AARCH32_IRQ => {
+ irqchip_handle_irq1()
+ }
+ ExceptionType::EXIT_REASON_EL1_ABORT | ExceptionType::EXIT_REASON_EL1_AARCH32_ABORT => {
+ arch_handle_trap_el1(regs)
+ }
ExceptionType::EXIT_REASON_EL2_ABORT => arch_handle_trap_el2(regs),
ExceptionType::EXIT_REASON_EL2_IRQ => irqchip_handle_irq2(),
_ => arch_dump_exit(regs.exit_reason),
@@ -222,10 +228,10 @@ fn handle_dabt(regs: &mut GeneralRegisters) {
address: address as _,
size,
is_write,
- value: if srt == 31 {
- 0
- } else {
+ value: if is_write && srt != 31 {
regs.usr[srt as usize] as _
+ } else {
+ 0
},
};
diff --git a/src/arch/aarch64/zone.rs b/src/arch/aarch64/zone.rs
index 037750e4..b7e8e90b 100644
--- a/src/arch/aarch64/zone.rs
+++ b/src/arch/aarch64/zone.rs
@@ -59,22 +59,48 @@ impl Zone {
info!("VM stage 2 memory set: {:#x?}", self.gpm);
Ok(())
}
+
+ pub fn arch_zone_configuration(&mut self, config: &HvZoneConfig) -> HvResult {
+ self.ivc_init(config.ivc_config());
+ Ok(())
+ }
}
#[repr(C)]
#[derive(Debug, Clone)]
pub struct HvArchZoneConfig {
+ pub is_aarch32: u8,
+ pub gic_config: GicConfig,
+}
+
+#[repr(C, usize)]
+#[derive(Debug, Clone)]
+pub enum GicConfig {
+ Gicv2(Gicv2Config),
+ Gicv3(Gicv3Config),
+}
+
+#[repr(C)]
+#[derive(Debug, Clone)]
+pub struct Gicv2Config {
pub gicd_base: usize,
pub gicd_size: usize,
- pub gicr_base: usize,
- pub gicr_size: usize,
- pub gits_base: usize,
- pub gits_size: usize,
pub gicc_base: usize,
- pub gicc_offset: usize,
pub gicc_size: usize,
+ pub gicc_offset: usize,
pub gich_base: usize,
pub gich_size: usize,
pub gicv_base: usize,
pub gicv_size: usize,
}
+
+#[repr(C)]
+#[derive(Debug, Clone)]
+pub struct Gicv3Config {
+ pub gicd_base: usize,
+ pub gicd_size: usize,
+ pub gicr_base: usize,
+ pub gicr_size: usize,
+ pub gits_base: usize,
+ pub gits_size: usize,
+}
diff --git a/src/arch/loongarch64/clock.rs b/src/arch/loongarch64/clock.rs
new file mode 100644
index 00000000..3496e5ca
--- /dev/null
+++ b/src/arch/loongarch64/clock.rs
@@ -0,0 +1,72 @@
+// Copyright (c) 2025 Syswonder
+// hvisor is licensed under Mulan PSL v2.
+// You can use this software according to the terms and conditions of the Mulan PSL v2.
+// You may obtain a copy of Mulan PSL v2 at:
+// http://license.coscl.org.cn/MulanPSL2
+// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+// FIT FOR A PARTICULAR PURPOSE.
+// See the Mulan PSL v2 for more details.
+//
+// Syswonder Website:
+// https://www.syswonder.org
+//
+// Authors:
+// Yulong Han
+//
+use loongArch64::cpu::CPUCFG;
+use loongArch64::time::*;
+use spin::Mutex;
+
+use crate::arch::cpu::this_cpu_id;
+
+pub fn get_cpucfg_cc_freq() -> usize {
+ let cpucfg = CPUCFG::read(0x4);
+ cpucfg.get_bits(0, 31)
+}
+
+pub fn get_cpucfg_cc_mul() -> usize {
+ let cpucfg = CPUCFG::read(0x5);
+ cpucfg.get_bits(0, 15)
+}
+
+pub fn get_cpucfg_cc_div() -> usize {
+ let cpucfg = CPUCFG::read(0x5);
+ cpucfg.get_bits(16, 31)
+}
+
+pub fn read_stable_counter() -> usize {
+ loongArch64::time::Time::read()
+}
+
+pub fn timer_test_tick() {
+ if this_cpu_id() != 0 {
+ return; // we only test on primary core
+ }
+ let freq = get_timer_freq();
+ let start_time = read_stable_counter();
+ info!(
+ "loongarch64: clock: timer_test_tick: freq: {}, start_time: {}",
+ freq, start_time
+ );
+ let mut last_log_time = start_time;
+ loop {
+ // after we passes 1 sec, we output a log, stop after 6 sec
+ let current_time = read_stable_counter();
+ if current_time - last_log_time > freq {
+ info!(
+ "loongarch64: clock: timer_test_tick: freq: {}, current_time: {}, calculated seconds: {}",
+ freq, current_time, (current_time - start_time) / freq
+ );
+ last_log_time = current_time;
+ }
+ if current_time - start_time > 10 * freq {
+ break;
+ }
+ }
+ info!(
+ "loongarch64: clock: timer_test_tick: freq: {}, end_time: {}",
+ freq,
+ read_stable_counter()
+ );
+}
diff --git a/src/arch/loongarch64/consts.rs b/src/arch/loongarch64/consts.rs
new file mode 100644
index 00000000..96340a3f
--- /dev/null
+++ b/src/arch/loongarch64/consts.rs
@@ -0,0 +1,21 @@
+// Copyright (c) 2025 Syswonder
+// hvisor is licensed under Mulan PSL v2.
+// You can use this software according to the terms and conditions of the Mulan PSL v2.
+// You may obtain a copy of Mulan PSL v2 at:
+// http://license.coscl.org.cn/MulanPSL2
+// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+// FIT FOR A PARTICULAR PURPOSE.
+// See the Mulan PSL v2 for more details.
+//
+// Syswonder Website:
+// https://www.syswonder.org
+//
+// Authors:
+// ForeverYolo <2572131118@qq.com>
+
+// PCI constants
+/* turn to virtual address and add 0xe prefix for HT accessing */
+pub const HV_ADDR_PREFIX: u64 = 0x8000_0000_0000_0000;
+pub const LOONG_HT_PREFIX: u64 = 0xe00_0000_0000;
+pub const BDF_SHIFT: usize = 8;
diff --git a/src/arch/loongarch64/cpu.rs b/src/arch/loongarch64/cpu.rs
index 3e4aca42..4e811c4c 100644
--- a/src/arch/loongarch64/cpu.rs
+++ b/src/arch/loongarch64/cpu.rs
@@ -78,11 +78,11 @@ impl ArchCpu {
// - wheatfox 2025.5.20
self.ctx.gcsr_cpuid = 0;
info!(
- "loongarch64: CPU{} run@{:#x}",
+ "[[CPU virtualization]] CPU{} run@{:#x}",
self.get_cpuid(),
self.ctx.sepc
);
- debug!("loongarch64: @{:#x?}", self);
+ info!("loongarch64: @{:#x?}", self);
// step 1: enable guest mode
// step 2: set guest entry to era
// step 3: run ertn and enter guest mode
@@ -158,3 +158,8 @@ pub fn cpu_start(cpuid: usize, start_addr: usize, opaque: usize) {
mail_send(entry_addr, cpuid, 0);
ipi_write_action(cpuid, SMP_BOOT_CPU);
}
+
+pub fn store_cpu_pointer_to_reg(pointer: usize) {
+ // println!("loongarch64 doesn't support store cpu pointer to reg, pointer: {:#x}", pointer);
+ return;
+}
diff --git a/src/arch/loongarch64/hypercall.rs b/src/arch/loongarch64/hypercall.rs
new file mode 100644
index 00000000..0253397a
--- /dev/null
+++ b/src/arch/loongarch64/hypercall.rs
@@ -0,0 +1,69 @@
+// Copyright (c) 2025 Syswonder
+// hvisor is licensed under Mulan PSL v2.
+// You can use this software according to the terms and conditions of the Mulan PSL v2.
+// You may obtain a copy of Mulan PSL v2 at:
+// http://license.coscl.org.cn/MulanPSL2
+// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+// FIT FOR A PARTICULAR PURPOSE.
+// See the Mulan PSL v2 for more details.
+//
+// Syswonder Website:
+// https://www.syswonder.org
+//
+// Authors:
+// ForeverYolo <2572131118@qq.com>
+
+use crate::arch::cpu::this_cpu_id;
+use crate::config::HvZoneConfig;
+use crate::config::CONFIG_MAGIC_VERSION;
+use crate::device::virtio_trampoline::MAX_DEVS;
+use crate::hypercall::HyperCall;
+use crate::hypercall::HyperCallResult;
+impl<'a> HyperCall<'a> {
+ pub fn hv_ivc_info(&mut self, ivc_info_ipa: u64) -> HyperCallResult {
+ warn!("hv_ivc_info is not implemented for LoongArch64");
+ HyperCallResult::Ok(0)
+ }
+
+ pub fn translate_ipa_to_hva(&mut self, ipa: u64) -> u64 {
+ return ipa | crate::arch::mm::LOONGARCH64_CACHED_DMW_PREFIX;
+ }
+
+ pub fn wait_for_interrupt(&mut self, irq_list: &mut [u64; MAX_DEVS + 1]) {
+ use crate::device::irqchip::ls7a2000::*;
+ let status = GLOBAL_IRQ_INJECT_STATUS.lock();
+ drop(status);
+ irq_list[0] = 0; // CAUTION: this is a workaround for loongarch64
+ }
+
+ pub fn hv_zone_config_check(&self, magic_version: *mut u64) -> HyperCallResult {
+ let magic_version_raw = magic_version as u64;
+ let magic_version_hva = magic_version_raw | crate::arch::mm::LOONGARCH64_CACHED_DMW_PREFIX;
+ let magic_version_hva = magic_version_hva as *mut u64;
+ debug!(
+ "hv_zone_config_check: magic_version target addr to write = {:#x?}",
+ magic_version_hva
+ );
+ unsafe {
+ core::ptr::write(magic_version_hva, CONFIG_MAGIC_VERSION as _);
+ }
+ HyperCallResult::Ok(0)
+ }
+
+ pub fn hv_get_real_pa(&mut self, config_addr: u64) -> u64 {
+ // LoongArch64 uses a specific prefix for cached memory addresses.
+ let config_addr = config_addr as u64 | crate::arch::mm::LOONGARCH64_CACHED_DMW_PREFIX;
+ return config_addr;
+ }
+
+ pub fn hv_get_real_list_pa(&mut self, list_addr: u64) -> u64 {
+ // RISC-V does not have a specific prefix for cached memory, so we return the address as is.
+ return list_addr;
+ }
+
+ pub fn check_cpu_id(&self) {
+ let cpuid = this_cpu_id();
+ assert_eq!(cpuid, 0);
+ }
+}
diff --git a/src/arch/loongarch64/iommu.rs b/src/arch/loongarch64/iommu.rs
index f633b640..6a37d541 100644
--- a/src/arch/loongarch64/iommu.rs
+++ b/src/arch/loongarch64/iommu.rs
@@ -18,3 +18,10 @@
pub fn iommu_init() {
info!("loongarch64: iommu_init: do nothing now");
}
+
+pub fn iommu_add_device(vmid: usize, sid: usize) {
+ info!(
+ "loongarch64: iommu_add_device: do nothing now, vmid: {}, sid: {}",
+ vmid, sid
+ );
+}
diff --git a/src/arch/loongarch64/ipi.rs b/src/arch/loongarch64/ipi.rs
index 24f91c2f..1e1f0cfd 100644
--- a/src/arch/loongarch64/ipi.rs
+++ b/src/arch/loongarch64/ipi.rs
@@ -15,6 +15,7 @@
// Yulong Han
//
use crate::arch::cpu::this_cpu_id;
+use crate::consts::IPI_EVENT_CLEAR_INJECT_IRQ;
use crate::device::common::MMIODerefWrapper;
use core::arch::asm;
use core::ptr::write_volatile;
@@ -342,3 +343,25 @@ pub fn dump_ipi_registers() {
ipi.mailbox3.read(Mailbox3::MAILBOX3)
);
}
+
+pub fn arch_check_events(event: Option) {
+ match event {
+ Some(IPI_EVENT_CLEAR_INJECT_IRQ) => {
+ // clear the injected IPI interrupt
+ use crate::device::irqchip::ls7a2000::clear_hwi_injected_irq;
+ clear_hwi_injected_irq();
+ }
+ _ => {
+ panic!("arch_check_events: unhandled event: {:?}", event);
+ }
+ }
+}
+
+pub fn arch_prepare_send_event(cpu_id: usize, ipi_int_id: usize, event_id: usize) {
+ use crate::event::fetch_event;
+ while !fetch_event(cpu_id).is_none() {}
+ debug!(
+ "loongarch64:: send_event: cpu_id: {}, ipi_int_id: {}, event_id: {}",
+ cpu_id, ipi_int_id, event_id
+ );
+}
diff --git a/src/arch/loongarch64/mm.rs b/src/arch/loongarch64/mm.rs
index 68a63113..075e96b1 100644
--- a/src/arch/loongarch64/mm.rs
+++ b/src/arch/loongarch64/mm.rs
@@ -29,7 +29,7 @@ use spin::*;
pub const LOONGARCH64_CACHED_DMW_PREFIX: u64 = 0x9000_0000_0000_0000;
pub const LOONGARCH64_UNCACHED_DMW_PREFIX: u64 = 0x8000_0000_0000_0000;
-pub fn init_hv_page_table(fdt: &fdt::Fdt) -> HvResult {
+pub fn init_hv_page_table() -> HvResult {
todo!();
// let mut hv_pt: MemorySet = MemorySet::new(4);
// // let mem_region = fdt.memory().regions().next().unwrap();
@@ -63,3 +63,9 @@ pub fn init_hv_page_table(fdt: &fdt::Fdt) -> HvResult {
pub fn new_s2_memory_set() -> MemorySet {
MemorySet::new(4)
}
+
+pub fn arch_setup_parange() {
+ // LoongArch64 does not have a parange setup like AArch64.
+ // This function can be used to set up any architecture-specific parameters if needed.
+ // Currently, it does nothing.
+}
diff --git a/src/arch/loongarch64/mod.rs b/src/arch/loongarch64/mod.rs
index e9deaf2e..e0ef90aa 100644
--- a/src/arch/loongarch64/mod.rs
+++ b/src/arch/loongarch64/mod.rs
@@ -16,8 +16,11 @@
//
#![allow(unused)]
+pub mod clock;
+pub mod consts;
pub mod cpu;
pub mod entry;
+pub mod hypercall;
pub mod iommu;
pub mod ipi;
pub mod mm;
@@ -29,4 +32,5 @@ pub mod trap;
pub mod zone;
pub use s1pt::Stage1PageTable;
+pub use s2pt::stage2_mode_detect;
pub use s2pt::Stage2PageTable;
diff --git a/src/arch/loongarch64/s2pt.rs b/src/arch/loongarch64/s2pt.rs
index 197a20ac..4ac95c45 100644
--- a/src/arch/loongarch64/s2pt.rs
+++ b/src/arch/loongarch64/s2pt.rs
@@ -165,7 +165,10 @@ pub struct S2PTInstr;
impl PagingInstr for S2PTInstr {
unsafe fn activate(root_pa: HostPhysAddr) {
- info!("loongarch64: S2PTInstr::activate: root_pa: {:#x?}", root_pa);
+ info!(
+ "[[memory virtualization]] activating stage-2 pagetable: root_pa: {:#x?}",
+ root_pa
+ );
super::paging::set_pwcl_pwch_stlbps();
extern "C" {
fn tlb_refill_handler();
@@ -178,13 +181,20 @@ impl PagingInstr for S2PTInstr {
tlbrentry::set_tlbrentry(tlb_refill_handler as usize);
}
info!(
- "loongarch64: S2PTInstr::activate: set tlbrentry to {:#x?} done!",
+ "[[memory virtualization]] activating stage 2 pagetable: set tlbrentry to {:#x?} done!",
tlbrentry::read().addr()
);
}
fn flush(vaddr: Option) {
- warn!("loongarch64: S2PTInstr::flush: vaddr: {:#x?}", vaddr);
+ warn!(
+ "[[memory virtualization]] flushing stage2 page table: vaddr: {:#x?}",
+ vaddr
+ );
}
}
pub type Stage2PageTable = Level4PageTable;
+
+pub fn stage2_mode_detect() {
+ info!("Dynamical detection of stage-2 paging mode is not supported yet.");
+}
diff --git a/src/arch/loongarch64/trap.rs b/src/arch/loongarch64/trap.rs
index da1761f8..d16e1c81 100644
--- a/src/arch/loongarch64/trap.rs
+++ b/src/arch/loongarch64/trap.rs
@@ -19,7 +19,7 @@ use super::register::*;
use super::zone::ZoneContext;
use crate::arch::cpu::this_cpu_id;
use crate::arch::ipi::*;
-use crate::consts::MAX_CPU_NUM;
+use crate::consts::{IPI_EVENT_CLEAR_INJECT_IRQ, MAX_CPU_NUM};
use crate::device::irqchip::inject_irq;
use crate::device::irqchip::ls7a2000::chip::*;
use crate::event::{check_events, dump_cpu_events, dump_events};
@@ -105,24 +105,29 @@ pub fn install_trap_vector() {
}
/// enable CRMD.IE
+#[inline(always)]
pub fn enable_global_interrupt() {
crmd::set_ie(true);
}
/// disable CRMD.IE
+#[inline(always)]
pub fn disable_global_interrupt() {
crmd::set_ie(false);
}
+#[inline(always)]
pub fn get_ms_counter(ms: usize) -> usize {
ms * (time::get_timer_freq() / 1000)
}
+#[inline(always)]
pub fn get_us_counter(us: usize) -> usize {
us * (time::get_timer_freq() / 1000_000)
}
-/// read the current stable counter value
+/// read the current stable counter value, not ns!
+#[inline(always)]
pub fn ktime_get() -> usize {
let mut current_counter_time;
unsafe {
@@ -215,10 +220,20 @@ fn handle_page_modify_fault() {
#[no_mangle]
pub fn trap_handler(mut ctx: &mut ZoneContext) {
- let cur = ktime_get();
- // print ctx addr
trace!("loongarch64: trap_handler: ctx addr = {:p}", &ctx);
+ // save timer
+ let delta;
+ let ticks = ctx.gcsr_tval;
+ let cfg = ctx.gcsr_tcfg;
+ if ticks < cfg {
+ delta = ticks;
+ } else {
+ delta = 0;
+ }
+ let expire = ktime_get() + delta;
+
+ // dump trap csr regs
let estat_ = estat::read();
let ecode = estat_.ecode();
let esubcode = estat_.esubcode();
@@ -247,10 +262,15 @@ pub fn trap_handler(mut ctx: &mut ZoneContext) {
let mut is_idle = false;
if ecode == ECODE_GSPR && badi_.inst() == 0b0000_0110_0100_1000_1000_0000_0000_0000 {
is_idle = true;
+ ctx.sepc += 4;
+ // just return to guest
+ unsafe {
+ let _ctx_ptr = ctx as *mut ZoneContext;
+ _vcpu_return(_ctx_ptr as usize);
+ }
}
- if !is_idle {
- debug!(
+ debug!(
"loongarch64: trap_handler: {} ecode={:#x} esubcode={:#x} is={:#x} badv={:#x} badi={:#x} era={:#x}",
ecode2str(ecode, esubcode),
ecode,
@@ -260,8 +280,6 @@ pub fn trap_handler(mut ctx: &mut ZoneContext) {
badi_.inst(),
era_.raw(),
);
- print!("\0");
- }
handle_exception(
ecode,
@@ -275,38 +293,46 @@ pub fn trap_handler(mut ctx: &mut ZoneContext) {
// restore timer
let cfg = ctx.gcsr_tcfg;
- write_gcsr_tcfg(0);
+
+ ctx.gcsr_tcfg = 0;
+
// restore GCSR_ESTAT and GCSR_TCFG
- write_gcsr_estat(ctx.gcsr_estat);
- write_gcsr_tcfg(ctx.gcsr_tcfg);
- if cfg & (1 << 0) == 0 {
+ ctx.gcsr_estat = 0;
+ ctx.gcsr_tcfg = 0;
+
+ debug!("loongarch64: trap_handler: restore timer, cfg={:#x}", cfg);
+
+ if cfg & 1 == 0 {
// guest has disabled timer, we just restore the tval
- write_gcsr_tval(ctx.gcsr_tval);
+ ctx.gcsr_tval = 0;
} else {
- // guest has enabled timer
let ticks = ctx.gcsr_tval;
let estat = ctx.gcsr_estat;
+
if !((cfg & 2) != 0 && (ticks > cfg)) {
- write_gcsr_tval(0); // inject timer irq
- if estat & 0x800 != 0 {
- // set GCSR.TICLR[0] to 1
- write_gcsr_ticlr(1);
+ ctx.gcsr_tval = 0; // inject irq
+ let cpu_timer = 1usize << 11;
+ if estat & cpu_timer == 0 {
+ ctx.gcsr_ticlr = 1; // clear timer interrupt
+ }
+ } else {
+ let now = ktime_get();
+ let mut __delta = 0;
+ if now < expire {
+ __delta = expire - now;
+ } else if (cfg & 2) != 0 {
+ // tcfg[63:2] || 00 is tval
+ let period = cfg & (0xffff_ffff_ffff_fffc);
+ __delta = now - expire;
+ __delta = period - (__delta % period);
+ // kvm queued guest timer irq injection here but we do nothing here
}
+
+ ctx.gcsr_tval = __delta;
}
}
- let cur1 = ktime_get();
- // calculate the time spent in trap_handler
- let time_spent = cur1 - cur;
- // set guest timer compensation
- let gcntc = gcntc::read();
- let gcntc_com = gcntc.compensation();
- gcntc::set_compensation(gcntc_com.wrapping_sub(time_spent));
-
- if !is_idle {
- debug!("loongarch64: trap_handler: return");
- print!("\0");
- }
+ debug!("loongarch64: trap_handler: return");
unsafe {
let _ctx_ptr = ctx as *mut ZoneContext;
@@ -1391,16 +1417,6 @@ fn emulate_idle(ins: usize, ctx: &mut ZoneContext) {
// idle level 0000011001 0010001 level[14:0]
let level = extract_field(ins, 0, 15);
trace!("guest request an idle at level {:#x}", level);
- // // wait until GCSR.ESTAT.IS != 0
- // loop {
- // let estat = read_gcsr_estat();
- // // ESTAT[12:0] = IS
- // if estat & 0x1fff != 0 {
- // let is = estat & 0x1fff;
- // debug!("idle waited, interrupt status is {:#x}", is);
- // break;
- // }
- // }
}
fn ty2str(ty: usize) -> &'static str {
@@ -1475,31 +1491,6 @@ fn emulate_iocsr(ins: usize, ctx: &mut ZoneContext) {
// iocsrwr.w
mmio_access.size = 4;
mmio_access.is_write = true;
-
- // TODO: move these to mmio handler in arch/loongarch64/zone.rs
- //
- // Special handling for IPI
- // if mmio_access.address == 0x1014 {
- // // IPI send issued from guest is tricky ...
- // // IPI_send is 32 bit, we ignore the upper 32 bits
- // // bit [31]: wait for completion
- // // bit [25:16] target cpu id
- // // bit [4:0] ipi id (IPI_status, 32 bit) indicates the IPI type (0-31)
- // let ipi_send = mmio_access.value as u32;
- // let ipi_id = ipi_send & 0x1f;
- // let target_cpu_id = (ipi_send >> 16) & 0x3ff;
- // let wait_for_completion = (ipi_send >> 31) & 0x1;
- // warn!("IPI send issued from guest, ipi_id = {:#x}, target_cpu_id = {:#x}, wait_for_completion = {:#x}", ipi_id, target_cpu_id, wait_for_completion);
- // if target_cpu_id == this_cpu_id() as u32 {
- // warn!("send IPI to itself, injecting IPI to GCSR_ESTAT");
- // inject_irq(INT_IPI, false);
- // ctx.sepc += 4;
- // return;
- // } else {
- // // TODO
- // panic!("send IPI from guest to other cpu is not supported yet!");
- // }
- // }
}
7 => {
// iocsrwr.d
@@ -1689,10 +1680,6 @@ fn emulate_ld_b(ins: usize, ctx: &mut ZoneContext) {
let vaddr = ctx.x[rj] as isize + imm12toi64(si12);
info!("vaddr = 0x{:x}", vaddr as usize);
let offset = (vaddr - UART0_BASE as isize) as usize; // minus the UART0 base address
- // let mut uart0 = UART_EMU.lock();
- // let byte = uart0.read(offset);
- // info!("byte = 0x{:x}", byte as usize);
- // ctx.x[rd] = byte as usize;
}
fn emulate_st_b(ins: usize, ctx: &mut ZoneContext) {
@@ -1710,15 +1697,6 @@ fn emulate_st_b(ins: usize, ctx: &mut ZoneContext) {
let vaddr = ctx.x[rj] as isize + imm12toi64(si12);
// info!("vaddr = 0x{:x}", vaddr as usize);
let offset = (vaddr - UART0_BASE as isize) as usize; // minus the UART0 base address
- // for VGA
- // let mut uart0 = UART_EMU.lock();
- // let byte = ctx.x[rd] as u8;
- // info!("byte = 0x{:x}", byte as usize);
- // let cur_zone = current_vcpu().unwrap().get_zone().unwrap();
- // let cur_zone_id = cur_zone.get_zone_id();
- // uart0.write(offset, byte, false, (cur_zone_id - 1) as i32);
- // drop(uart0); // !!!! very important
- // cur_zone.inner.lock().uart_emu.write(offset, byte, true, 0);
}
fn emulate_ld_bu(ins: usize, ctx: &mut ZoneContext) {
@@ -1729,19 +1707,13 @@ fn emulate_ld_bu(ins: usize, ctx: &mut ZoneContext) {
let rd = extract_field(ins, 0, 5);
let rj = extract_field(ins, 5, 5);
let si12 = extract_field(ins, 10, 12);
-
// info!("ld.bu emulation, rd = {}, rj = {}, si12 = {}", rd, rj, si12);
// vaddr = GR[rj] + SignExt(si12, GRLEN(64))
// paddr = translate(vaddr)
// byte = load (paddr, BYTE)
// GR[rd] = byte
let vaddr = ctx.x[rj] as isize + imm12toi64(si12);
- // info!("vaddr = 0x{:x}", vaddr as usize);
let offset = (vaddr - UART0_BASE as isize) as usize; // minus the UART0 base address
- // let mut uart0 = UART_EMU.lock();
- // let byte = uart0.read(offset);
- // info!("byte = 0x{:x}", byte as usize);
- // ctx.x[rd] = byte as usize;
}
fn check_op_type(inst: usize, opcode: usize, opcode_length: usize) -> bool {
@@ -1822,7 +1794,7 @@ fn emulate_instruction(era: usize, ins: usize, ctx: &mut ZoneContext) {
}
}
- panic!("Unexpected opcode encountered, ins = {:#x}", ins);
+ panic!("unexpected opcode encountered, ins = {:#x}", ins);
}
/* TLB REFILL HANDLER */
diff --git a/src/arch/loongarch64/zone.rs b/src/arch/loongarch64/zone.rs
index 2e12d3ed..419b29ef 100644
--- a/src/arch/loongarch64/zone.rs
+++ b/src/arch/loongarch64/zone.rs
@@ -94,7 +94,7 @@ impl Zone {
info!("loongarch64: pt_init: add mmio handler for 0x1fe0_xxxx mmio region");
self.mmio_region_register(0x1fe0_0000, 0x3000, loongarch_generic_mmio_handler, 0x1234);
- debug!("zone stage-2 memory set: {:#x?}", self.gpm);
+ info!("zone stage-2 memory set: {:#x?}", self.gpm);
unsafe {
// test the page table by querying the first page
if mem_regions.len() > 0 {
@@ -116,9 +116,6 @@ impl Zone {
}
Ok(())
}
- pub fn isa_init(&mut self, fdt: &fdt::Fdt) {
- warn!("loongarch64: mm: isa_init do nothing");
- }
pub fn irq_bitmap_init(&mut self, irqs: &[u32]) {}
}
@@ -447,8 +444,8 @@ impl MMIOAccessTracker {
static MMIO_ACCESS_STATS: Lazy> =
Lazy::new(|| Mutex::new(MMIOAccessTracker::new()));
-const COMPRESSION_THRESHOLD: u64 = 50;
-const LOG_INTERVAL: u64 = 50;
+const COMPRESSION_THRESHOLD: u64 = 40;
+const LOG_INTERVAL: u64 = 100000;
const BASE_ADDR: usize = PHY_TO_DMW_UNCACHED!(0x1fe0_0000);
const UART0_BASE: usize = PHY_TO_DMW_UNCACHED!(0x1fe0_01e0);
@@ -567,8 +564,8 @@ fn handle_extioi_mapping_mmio(mmio: &mut MMIOAccess, base_addr: usize, size: usi
new_data |= (1 << target_cpu_id);
let target_write_phyaddr = base_addr + target_ioi_number as usize;
let target_write_value = new_data as u8;
- debug!(
- "extioi[{}], node_selection={:#x}, irq_target={:#x}, changed cpu routing to {}, value={:#x}",
+ info!(
+ "[[interrupt virtualization]] extioi[{}], node_selection={:#x}, irq_target={:#x}, changed irq routing to cpu {}, value={:#x}",
target_ioi_number, target_ioi_node_selection, target_ioi_irq_target, target_cpu_id, target_write_value
);
unsafe {
@@ -646,21 +643,21 @@ pub fn loongarch_generic_mmio_handler(mmio: &mut MMIOAccess, arg: usize) -> HvRe
ret = handle_extioi_status_mmio(mmio, EXTIOI_SR_CORE_BASE, EXTIOI_SR_CORE_SIZE);
} else if is_in_mmio_range!(mmio.address, EXTIOI_ENABLE_BASE, EXTIOI_ENABLE_SIZE) {
if this_cpu_id() != 0 && mmio.is_write {
- info!("nonroot's write to enable regs, ignored");
+ info!("nonroot's write to extioi enable regs, ignored");
return Ok(());
} else {
ret = handle_generic_mmio(mmio, BASE_ADDR);
}
} else if is_in_mmio_range!(mmio.address, EXTIOI_BOUNCE_BASE, EXTIOI_BOUNCE_SIZE) {
if this_cpu_id() != 0 && mmio.is_write {
- info!("nonroot's write to bounce regs, ignored");
+ info!("nonroot's write to extioi bounce regs, ignored");
return Ok(());
} else {
ret = handle_generic_mmio(mmio, BASE_ADDR);
}
} else if is_in_mmio_range!(mmio.address, EXTIOI_NODE_SEL_BASE, EXTIOI_NODE_SEL_SIZE) {
if this_cpu_id() != 0 && mmio.is_write {
- info!("nonroot's write to node sel regs, ignored");
+ info!("nonroot's write to extioi node sel regs, ignored");
return Ok(());
} else {
ret = handle_generic_mmio(mmio, BASE_ADDR);
@@ -685,4 +682,16 @@ impl Zone {
))?;
self.gpm.delete(vaddr as GuestPhysAddr)
}
+
+ pub fn arch_zone_configuration(&mut self, config: &HvZoneConfig) -> HvResult {
+ let vaddr = config.pci_config.ecam_base;
+ let size = config.pci_config.ecam_size;
+ self.gpm.insert(MemoryRegion::new_with_offset_mapper(
+ vaddr as GuestPhysAddr,
+ vaddr as HostPhysAddr,
+ size as _,
+ MemFlags::READ | MemFlags::WRITE | MemFlags::IO,
+ ))?;
+ self.gpm.delete(vaddr as GuestPhysAddr)
+ }
}
diff --git a/src/arch/riscv64/consts.rs b/src/arch/riscv64/consts.rs
new file mode 100644
index 00000000..5bfd0825
--- /dev/null
+++ b/src/arch/riscv64/consts.rs
@@ -0,0 +1,20 @@
+// Copyright (c) 2025 Syswonder
+// hvisor is licensed under Mulan PSL v2.
+// You can use this software according to the terms and conditions of the Mulan PSL v2.
+// You may obtain a copy of Mulan PSL v2 at:
+// http://license.coscl.org.cn/MulanPSL2
+// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+// FIT FOR A PARTICULAR PURPOSE.
+// See the Mulan PSL v2 for more details.
+//
+// Syswonder Website:
+// https://www.syswonder.org
+//
+// Authors:
+// ForeverYolo <2572131118@qq.com>
+
+// PCI constants
+pub const HV_ADDR_PREFIX: u64 = 0;
+pub const LOONG_HT_PREFIX: u64 = 0;
+pub const BDF_SHIFT: usize = 12;
diff --git a/src/arch/riscv64/cpu.rs b/src/arch/riscv64/cpu.rs
index 002229b4..cb735efa 100644
--- a/src/arch/riscv64/cpu.rs
+++ b/src/arch/riscv64/cpu.rs
@@ -41,6 +41,8 @@ pub struct ArchCpu {
pub sstc: bool,
}
+const PARKING_INST_GPA: usize = 0x0; // wfi instruction address (gpa)
+
impl ArchCpu {
pub fn new(cpuid: usize) -> Self {
let ret = ArchCpu {
@@ -85,6 +87,8 @@ impl ArchCpu {
set_csr!(CSR_HENVCFG, 1 << 63);
set_csr!(CSR_VSTIMECMP, usize::MAX);
} else {
+ // In megrez board, this instruction is not supported. (illegal instruction)
+ #[cfg(not(feature = "eic770x_soc"))]
set_csr!(CSR_HENVCFG, 0);
}
set_csr!(CSR_HCOUNTEREN, 1 << 1); // HCOUNTEREN_TM
@@ -103,7 +107,9 @@ impl ArchCpu {
pub fn init_interrupt(&self) {
// Used before enter into VM.
set_csr!(CSR_HIDELEG, 1 << 2 | 1 << 6 | 1 << 10); // HIDELEG_VSSI | HIDELEG_VSTI | HIDELEG_VSEI
- set_csr!(CSR_HEDELEG, 1 << 8 | 1 << 12 | 1 << 13 | 1 << 15); // HEDELEG_ECU | HEDELEG_IPF | HEDELEG_LPF | HEDELEG_SPF
+ // Note: Breakpoint exception is temporarily needed.
+ // TODO: This is need to be checked in the future.
+ set_csr!(CSR_HEDELEG, 1 << 3 | 1 << 8 | 1 << 12 | 1 << 13 | 1 << 15); // HEDELEG_ECU | HEDELEG_IPF | HEDELEG_LPF | HEDELEG_SPF
set_csr!(CSR_SIE, 1 << 9 | 1 << 5 | 1 << 1); // Enable all interrupts (SEIE STIE SSIE).
}
@@ -151,14 +157,14 @@ impl ArchCpu {
self.power_on = false;
PARKING_MEMORY_SET.call_once(|| {
- let parking_code: [u8; 4] = [0x73, 0x00, 0x50, 0x10]; // 1: wfi; b 1b
+ let parking_code: [u8; 8] = [0x73, 0x00, 0x50, 0x10, 0x6F, 0xF0, 0xDF, 0xFF]; // 1: wfi; b 1b
unsafe {
- PARKING_INST_PAGE[..4].copy_from_slice(&parking_code);
+ PARKING_INST_PAGE[..8].copy_from_slice(&parking_code);
}
let mut gpm = new_s2_memory_set();
gpm.insert(MemoryRegion::new_with_offset_mapper(
- 0 as GuestPhysAddr,
+ PARKING_INST_GPA as GuestPhysAddr,
unsafe { &PARKING_INST_PAGE as *const _ as HostPhysAddr - PHYS_VIRT_OFFSET },
PAGE_SIZE,
MemFlags::READ | MemFlags::WRITE | MemFlags::EXECUTE,
@@ -168,7 +174,12 @@ impl ArchCpu {
});
// reset current cpu -> pc = 0x0 (wfi)
- self.reset_regs(0, this_cpu_data().id, this_cpu_data().dtb_ipa);
+ // Note: in park_inst_page
+ self.reset_regs(
+ PARKING_INST_GPA, // entry_addr
+ this_cpu_data().id, // a0
+ this_cpu_data().dtb_ipa, // a1
+ );
self.reset_interrupt();
unsafe {
PARKING_MEMORY_SET.get().unwrap().activate();
@@ -211,3 +222,10 @@ pub fn cpu_start(cpuid: usize, start_addr: usize, opaque: usize) {
panic!("cpu_start error: {:#x?}", e);
}
}
+
+pub fn store_cpu_pointer_to_reg(pointer: usize) {
+ /// Store the pointer to the current CPU's ArchCpu structure in CSR_SSCRATCH
+ write_csr!(CSR_SSCRATCH, pointer);
+ // println!("Stored CPU pointer to CSR_SSCRATCH: {:#x}", pointer);
+ return;
+}
diff --git a/src/arch/riscv64/entry.rs b/src/arch/riscv64/entry.rs
index 2ec2bbf7..653ab9f0 100644
--- a/src/arch/riscv64/entry.rs
+++ b/src/arch/riscv64/entry.rs
@@ -13,7 +13,15 @@
//
// Authors:
//
+use crate::clear_bss;
use crate::consts::PER_CPU_SIZE;
+#[no_mangle]
+#[link_section = ".data"]
+pub static mut CPU_BSS_LOCK: u32 = 1;
+
+#[no_mangle]
+#[link_section = ".data"]
+pub static mut ENTER_CPU: u32 = u32::MAX; // the first entered cpuid will be written.
#[naked]
#[no_mangle]
@@ -22,12 +30,41 @@ pub unsafe extern "C" fn arch_entry() -> i32 {
//a0=cpuid,a1=dtb addr
core::arch::asm!(
"
- la t0, __core_end // t0 = core_end
- li t1, {per_cpu_size} // t1 = per_cpu_size
- mul t2, a0, t1 // t2 = cpuid * per_cpu_size
- add t2, t1, t2 // t2 = cpuid * per_cpu_size+per_cpu_size
- add sp, t0, t2 // sp = core_end + cpuid * per_cpu_size + per_cpu_size
- call {rust_main}
+ la t0, __core_end // t0 = core_end
+ li t1, {per_cpu_size} // t1 = per_cpu_size
+ mul t2, a0, t1 // t2 = cpuid * per_cpu_size
+ add t2, t1, t2 // t2 = cpuid * per_cpu_size+per_cpu_size
+ add sp, t0, t2 // sp = core_end + cpuid * per_cpu_size + per_cpu_size
+
+ # The first entered CPU will be stored in ENTER_CPU.
+ # And the first CPU will clear the bss.
+
+ la t0, ENTER_CPU # t0 = &ENTER_CPU
+ la t3, CPU_BSS_LOCK
+ li t1, -1 # t1 = initial expected value (-1)
+ amoswap.w.aq t2, a0, (t0) # t2 = old value; swap a0(cpuid) into ENTER_CPU
+ bne t2, t1, 2f # if old != -1, someone else already wrote
+
+ 0:
+ la a3, sbss // a3 = bss's start addr
+ la a4, ebss // a4 = bss's end addr
+ 1:
+ blt a4, a3, 2f // first entered cpu clear bss
+ sb zero, 0(a3)
+ addi a3, a3, 1
+ j 1b
+ 2:
+ fence w, w
+ sw zero, 0(t3) // clear bss done
+ j 4f
+ 3:
+ lw t4, 0(t3) // wait for ENTER_CPU to clear bss
+ bnez t4, 3b
+ fence r, rw
+
+ 4:
+ # All CPUs could see the bss cleared.
+ call {rust_main} // a0, a1, sp are certain values
",
rust_main = sym crate::rust_main,
per_cpu_size=const PER_CPU_SIZE,
diff --git a/src/arch/riscv64/hypercall.rs b/src/arch/riscv64/hypercall.rs
new file mode 100644
index 00000000..195fdfaa
--- /dev/null
+++ b/src/arch/riscv64/hypercall.rs
@@ -0,0 +1,62 @@
+// Copyright (c) 2025 Syswonder
+// hvisor is licensed under Mulan PSL v2.
+// You can use this software according to the terms and conditions of the Mulan PSL v2.
+// You may obtain a copy of Mulan PSL v2 at:
+// http://license.coscl.org.cn/MulanPSL2
+// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+// FIT FOR A PARTICULAR PURPOSE.
+// See the Mulan PSL v2 for more details.
+//
+// Syswonder Website:
+// https://www.syswonder.org
+//
+// Authors:
+// ForeverYolo <2572131118@qq.com>
+
+use crate::arch::cpu::this_cpu_id;
+use crate::config::{HvZoneConfig, CONFIG_MAGIC_VERSION};
+use crate::device::virtio_trampoline::MAX_DEVS;
+use crate::hypercall::HyperCall;
+use crate::hypercall::HyperCallResult;
+
+impl<'a> HyperCall<'a> {
+ pub fn hv_ivc_info(&mut self, ivc_info_ipa: u64) -> HyperCallResult {
+ warn!("hv_ivc_info is not implemented for Risc-V");
+ HyperCallResult::Ok(0)
+ }
+
+ pub fn translate_ipa_to_hva(&mut self, ipa: u64) -> u64 {
+ return ipa;
+ }
+
+ pub fn wait_for_interrupt(&mut self, irq_list: &mut [u64; MAX_DEVS + 1]) {
+ trace!("wait_for_interrupt is not need for RISC-V");
+ }
+
+ pub fn hv_zone_config_check(&self, magic_version: *mut u64) -> HyperCallResult {
+ unsafe {
+ *magic_version = CONFIG_MAGIC_VERSION as _;
+ }
+ debug!(
+ "hv_zone_config_check: finished writing current magic version ({:#x})",
+ CONFIG_MAGIC_VERSION
+ );
+ HyperCallResult::Ok(0)
+ }
+
+ pub fn hv_get_real_pa(&mut self, config_addr: u64) -> u64 {
+ // RISC-V does not have a specific prefix for cached memory, so we return the address as is.
+ return config_addr;
+ }
+
+ pub fn hv_get_real_list_pa(&mut self, list_addr: u64) -> u64 {
+ // RISC-V does not have a specific prefix for cached memory, so we return the address as is.
+ return list_addr;
+ }
+
+ pub fn check_cpu_id(&self) {
+ let cpuid = this_cpu_id();
+ trace!("CPU ID: {} Start Zone", cpuid);
+ }
+}
diff --git a/src/arch/riscv64/iommu.rs b/src/arch/riscv64/iommu.rs
new file mode 100644
index 00000000..fd0d60bd
--- /dev/null
+++ b/src/arch/riscv64/iommu.rs
@@ -0,0 +1,26 @@
+// Copyright (c) 2025 Syswonder
+// hvisor is licensed under Mulan PSL v2.
+// You can use this software according to the terms and conditions of the Mulan PSL v2.
+// You may obtain a copy of Mulan PSL v2 at:
+// http://license.coscl.org.cn/MulanPSL2
+// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+// FIT FOR A PARTICULAR PURPOSE.
+// See the Mulan PSL v2 for more details.
+//
+// Syswonder Website:
+// https://www.syswonder.org
+//
+// Authors:
+// ForeverYolo <2572131118@qq.com>
+
+pub fn iommu_init() {
+ info!("riscv: iommu_init: do nothing now");
+}
+
+pub fn iommu_add_device(vmid: usize, sid: usize) {
+ info!(
+ "riscv: iommu_add_device: do nothing now, vmid: {}, sid: {}",
+ vmid, sid
+ );
+}
diff --git a/src/arch/riscv64/ipi.rs b/src/arch/riscv64/ipi.rs
index 4f837263..97a59791 100644
--- a/src/arch/riscv64/ipi.rs
+++ b/src/arch/riscv64/ipi.rs
@@ -13,7 +13,9 @@
//
// Authors:
//
+use crate::consts::{IPI_EVENT_SEND_IPI, IPI_EVENT_UPDATE_HART_LINE};
use sbi_rt::HartMask;
+use sbi_rt::SbiRet;
// arch_send_event
pub fn arch_send_event(cpu_id: u64, _sgi_num: u64) {
@@ -21,7 +23,12 @@ pub fn arch_send_event(cpu_id: u64, _sgi_num: u64) {
#[cfg(feature = "aclint")]
crate::device::irqchip::aclint::aclint_send_ipi(cpu_id as usize);
#[cfg(not(feature = "aclint"))]
- sbi_rt::send_ipi(HartMask::from_mask_base(1 << cpu_id, 0));
+ {
+ let sbi_ret: SbiRet = sbi_rt::send_ipi(HartMask::from_mask_base(1 << cpu_id, 0));
+ if sbi_ret.is_err() {
+ error!("arch_send_event: send_ipi failed: {:?}", sbi_ret);
+ }
+ }
}
/// Handle send_ipi event.
@@ -30,3 +37,24 @@ pub fn arch_ipi_handler() {
riscv_h::register::hvip::set_vssip();
}
}
+
+pub fn arch_check_events(event: Option) {
+ match event {
+ #[cfg(feature = "plic")]
+ Some(IPI_EVENT_UPDATE_HART_LINE) => {
+ use crate::device::irqchip::plic::update_hart_line;
+ update_hart_line();
+ }
+ Some(IPI_EVENT_SEND_IPI) => {
+ use crate::arch::riscv64::ipi::arch_ipi_handler;
+ arch_ipi_handler();
+ }
+ _ => {
+ panic!("arch_check_events: unhandled event: {:?}", event);
+ }
+ }
+}
+
+pub fn arch_prepare_send_event(cpu_id: usize, ipi_int_id: usize, event_id: usize) {
+ debug!("risc-v arch_prepare_send_event: do nothing now.")
+}
diff --git a/src/arch/riscv64/mm.rs b/src/arch/riscv64/mm.rs
index effd2762..7b860ff5 100644
--- a/src/arch/riscv64/mm.rs
+++ b/src/arch/riscv64/mm.rs
@@ -136,5 +136,12 @@ pub fn init_hv_page_table() -> HvResult {
}
pub fn new_s2_memory_set() -> MemorySet {
- MemorySet::new(3)
+ // Create a new memory set for stage 2 page table, pt_level is dynamically detected before here.
+ unsafe { MemorySet::new(crate::arch::s2pt::GSTAGE_PT_LEVEL) }
+}
+
+pub fn arch_setup_parange() {
+ // RISC-V does not have a parange setup like AArch64.
+ // The parange is determined by the memory regions defined in the device tree.
+ // So we do not need to do anything here.
}
diff --git a/src/arch/riscv64/mod.rs b/src/arch/riscv64/mod.rs
index afd74244..a4143b61 100644
--- a/src/arch/riscv64/mod.rs
+++ b/src/arch/riscv64/mod.rs
@@ -13,9 +13,12 @@
//
// Authors:
//
+pub mod consts;
pub mod cpu;
pub mod csr;
pub mod entry;
+pub mod hypercall;
+pub mod iommu;
pub mod ipi;
pub mod mm;
pub mod paging;
@@ -26,4 +29,5 @@ pub mod trap;
pub mod zone;
pub use s1pt::Stage1PageTable;
+pub use s2pt::stage2_mode_detect;
pub use s2pt::Stage2PageTable;
diff --git a/src/arch/riscv64/paging.rs b/src/arch/riscv64/paging.rs
index 9f78a1c9..99928f05 100644
--- a/src/arch/riscv64/paging.rs
+++ b/src/arch/riscv64/paging.rs
@@ -41,12 +41,15 @@ impl From for HvError {
}
}
+// Note: 1G huge-page is enough for hvisor.
#[repr(usize)]
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
pub enum PageSize {
- Size4K = 0x1000,
- Size2M = 0x20_0000,
- Size1G = 0x4000_0000,
+ Size4K = 0x1000, // 12 bits
+ Size2M = 0x20_0000, // 21 bits
+ Size1G = 0x4000_0000, // 30 bits
+ // Size512G = 0x80_0000_0000, // 39 bits
+ // Size256TB = 0x1_0000_0000_0000,// 48 bits
}
#[derive(Debug, Copy, Clone)]
@@ -67,9 +70,9 @@ impl PageSize {
pub const fn page_offset(self, addr: usize) -> usize {
addr & (self as usize - 1)
}
- #[allow(unused)]
+
pub const fn is_huge(self) -> bool {
- matches!(self, Self::Size1G | Self::Size2M)
+ !matches!(self, Self::Size4K)
}
}
@@ -101,7 +104,7 @@ pub trait GenericPTE: Debug + Clone {
fn clear(&mut self);
}
-const ENTRY_COUNT: usize = 512;
+const ENTRY_COUNT: usize = 512; // For RV64, each page table has 512 entries.
pub trait PagingInstr {
unsafe fn activate(root_paddr: PhysAddr);
@@ -112,14 +115,15 @@ pub trait PagingInstr {
pub trait GenericPageTableImmut: Sized {
type VA: From + Into + Copy;
- unsafe fn from_root(root_paddr: PhysAddr) -> Self;
+ fn level(&self) -> usize;
+ unsafe fn from_root(root_paddr: PhysAddr, pt_level: usize) -> Self;
fn root_paddr(&self) -> PhysAddr;
fn query(&self, vaddr: Self::VA) -> PagingResult<(PhysAddr, MemFlags, PageSize)>;
}
/// A extended mutable page table can change mappings.
pub trait GenericPageTable: GenericPageTableImmut {
- fn new() -> Self;
+ fn new(pt_level: usize) -> Self;
fn map(&mut self, region: &MemoryRegion) -> HvResult;
fn unmap(&mut self, region: &MemoryRegion) -> HvResult;
@@ -137,28 +141,50 @@ pub trait GenericPageTable: GenericPageTableImmut {
}
/// A immutable level-3 page table implements `GenericPageTableImmut`.
-pub struct Level3PageTableImmut {
+pub struct HvPageTableImmut {
/// Root table frame.
root: Frame,
+ /// Page table level.
+ pt_level: usize,
/// Phantom data.
_phantom: PhantomData<(VA, PTE)>,
}
-impl Level3PageTableImmut
+impl HvPageTableImmut
where
VA: From + Into + Copy,
PTE: GenericPTE,
{
- fn new() -> Self {
+ fn new(pt_level: usize) -> Self {
+ assert!(pt_level >= 3 && pt_level <= 5, "pt_level must be 3, 4 or 5");
+ // Note: riscv spec requires G-stage's root page table addr to be 16KB aligned.
Self {
root: Frame::new_16().expect("failed to allocate root frame for host page table"),
+ pt_level: pt_level,
_phantom: PhantomData,
}
}
fn get_entry_mut(&self, vaddr: VA) -> PagingResult<(&mut PTE, PageSize)> {
let vaddr = vaddr.into();
- let p3 = table_of_mut::(self.root_paddr());
+ let p3 = if self.pt_level == 5 {
+ // Get the root page table (related to root_paddr).
+ let p5 = table_of_mut::(self.root_paddr());
+ // Use index to get the related PTE.
+ let p5e = &mut p5[p5_index(vaddr)];
+ let p4 = next_table_mut(p5e)?;
+ let p4e = &mut p4[p4_index(vaddr)];
+ next_table_mut(p4e)?
+ } else if self.pt_level == 4 {
+ // Get the root page table (related to root_paddr).
+ let p4 = table_of_mut::(self.root_paddr());
+ let p4e = &mut p4[p4_index(vaddr)];
+ next_table_mut(p4e)?
+ } else {
+ // Get the root page table (related to root_paddr).
+ table_of_mut::(self.root_paddr())
+ };
+
let p3e = &mut p3[p3_index(vaddr)];
if p3e.is_huge() {
return Ok((p3e, PageSize::Size1G));
@@ -185,10 +211,11 @@ where
) {
let mut n = 0;
for (i, entry) in table.iter().enumerate() {
- let vaddr = start_vaddr + (i << (12 + (3 - level) * 9));
+ // start_vaddr is the base virtual address of the current page table.
+ let vaddr = start_vaddr + (i << (12 + (self.pt_level - 1 - level) * 9));
if entry.is_present() {
func(level, i, vaddr, entry);
- if level < 2 {
+ if level < self.pt_level - 1 {
match next_table_mut(entry) {
Ok(entry) => self.walk(entry, level + 1, vaddr, limit, func),
Err(PagingError::MappedToHugePage) => {}
@@ -230,16 +257,17 @@ where
}
}
-impl GenericPageTableImmut for Level3PageTableImmut
+impl GenericPageTableImmut for HvPageTableImmut
where
VA: From + Into + Copy,
PTE: GenericPTE,
{
type VA = VA;
- unsafe fn from_root(root_paddr: PhysAddr) -> Self {
+ unsafe fn from_root(root_paddr: PhysAddr, pt_level: usize) -> Self {
Self {
root: Frame::from_paddr(root_paddr),
+ pt_level,
_phantom: PhantomData,
}
}
@@ -249,6 +277,7 @@ where
}
fn query(&self, vaddr: VA) -> PagingResult<(PhysAddr, MemFlags, PageSize)> {
+ // info!("query: {:#x?}", vaddr.into());
let (entry, size) = self.get_entry_mut(vaddr)?;
if entry.is_unused() {
return Err(PagingError::NotMapped);
@@ -256,35 +285,39 @@ where
let off = size.page_offset(vaddr.into());
Ok((entry.addr() + off, entry.flags(), size))
}
+
+ fn level(&self) -> usize {
+ self.pt_level
+ }
}
/// A extended level-3 page table that can change its mapping. It also tracks all intermediate
/// level tables. Locks need to be used if change the same page table concurrently.
-struct Level3PageTableUnlocked {
- inner: Level3PageTableImmut,
+struct HvPageTableUnlocked {
+ inner: HvPageTableImmut,
/// Intermediate level table frames.
intrm_tables: Vec,
/// Phantom data.
_phantom: PhantomData<(VA, PTE, I)>,
}
-impl Level3PageTableUnlocked
+impl HvPageTableUnlocked
where
VA: From + Into + Copy,
PTE: GenericPTE,
I: PagingInstr,
{
- fn new() -> Self {
+ fn new(pt_level: usize) -> Self {
Self {
- inner: Level3PageTableImmut::new(),
+ inner: HvPageTableImmut::new(pt_level),
intrm_tables: Vec::new(),
_phantom: PhantomData,
}
}
- unsafe fn from_root(root_paddr: PhysAddr) -> Self {
+ unsafe fn from_root(root_paddr: PhysAddr, pt_level: usize) -> Self {
Self {
- inner: Level3PageTableImmut::from_root(root_paddr),
+ inner: HvPageTableImmut::from_root(root_paddr, pt_level),
intrm_tables: Vec::new(),
_phantom: PhantomData,
}
@@ -305,17 +338,33 @@ where
flags: &mut MemFlags,
) -> PagingResult<&mut PTE> {
let vaddr: usize = page.vaddr.into();
- let p3 = table_of_mut::(self.inner.root_paddr());
+ // Current hvisor don't support huge page which > 1G.
+ let p3 = if self.inner.pt_level == 5 {
+ // Get the root page table (related to root_paddr).
+ let p5 = table_of_mut::(self.inner.root_paddr());
+ // Use index to get the related PTE.
+ let p5e = &mut p5[p5_index(vaddr)];
+ let p4 = next_table_mut_or_create(p5e, || self.alloc_intrm_table())?;
+ let p4e = &mut p4[p4_index(vaddr)];
+ next_table_mut_or_create(p4e, || self.alloc_intrm_table())?
+ } else if self.inner.pt_level == 4 {
+ // Get the root page table (related to root_paddr).
+ let p4 = table_of_mut::(self.inner.root_paddr());
+ let p4e = &mut p4[p4_index(vaddr)];
+ next_table_mut_or_create(p4e, || self.alloc_intrm_table())?
+ } else {
+ // Get the root page table (related to root_paddr).
+ table_of_mut::(self.inner.root_paddr())
+ };
+
let p3e = &mut p3[p3_index(vaddr)];
if page.size == PageSize::Size1G {
- flags.remove(MemFlags::NO_HUGEPAGES);
return Ok(p3e);
}
let p2 = next_table_mut_or_create(p3e, || self.alloc_intrm_table())?;
let p2e = &mut p2[p2_index(vaddr)];
if page.size == PageSize::Size2M {
- flags.remove(MemFlags::NO_HUGEPAGES);
return Ok(p2e);
}
@@ -359,13 +408,13 @@ where
/// A extended level-4 page table implements `GenericPageTable`. It use locks to avoid data
/// racing between it and its clonees.
-pub struct Level3PageTable {
- inner: Level3PageTableUnlocked,
+pub struct HvPageTable {
+ inner: HvPageTableUnlocked,
/// Make sure all accesses to the page table and its clonees is exclusive.
clonee_lock: Arc>,
}
-impl Level3PageTable
+impl HvPageTable
where
VA: From + Into + Copy,
PTE: GenericPTE,
@@ -380,7 +429,7 @@ where
pub fn clone_from(src: &impl GenericPageTableImmut) -> Self {
// XXX: The clonee won't track intermediate tables, must ensure it lives shorter than the
// original page table.
- let pt = Self::new();
+ let pt = Self::new(src.level());
let dst_p3_table = unsafe {
slice::from_raw_parts_mut(phys_to_virt(pt.root_paddr()) as *mut PTE, ENTRY_COUNT)
};
@@ -392,7 +441,7 @@ where
}
}
-impl GenericPageTableImmut for Level3PageTable
+impl GenericPageTableImmut for HvPageTable
where
VA: From + Into + Copy,
PTE: GenericPTE,
@@ -400,9 +449,9 @@ where
{
type VA = VA;
- unsafe fn from_root(root_paddr: PhysAddr) -> Self {
+ unsafe fn from_root(root_paddr: PhysAddr, pt_level: usize) -> Self {
Self {
- inner: Level3PageTableUnlocked::from_root(root_paddr),
+ inner: HvPageTableUnlocked::from_root(root_paddr, pt_level),
clonee_lock: Arc::new(Mutex::new(())),
}
}
@@ -415,17 +464,21 @@ where
let _lock = self.clonee_lock.lock();
self.inner.inner.query(vaddr)
}
+
+ fn level(&self) -> usize {
+ self.inner.inner.level()
+ }
}
-impl GenericPageTable for Level3PageTable
+impl GenericPageTable for HvPageTable
where
VA: From + Into + Copy,
PTE: GenericPTE,
I: PagingInstr,
{
- fn new() -> Self {
+ fn new(pt_level: usize) -> Self {
Self {
- inner: Level3PageTableUnlocked::new(),
+ inner: HvPageTableUnlocked::new(pt_level),
clonee_lock: Arc::new(Mutex::new(())),
}
}
@@ -446,22 +499,26 @@ where
let mut vaddr = region.start.into();
let mut size = region.size;
while size > 0 {
+ // Hvisor don't support huge page which > 1G.
let paddr = region.mapper.map_fn(vaddr);
- let page_size = if PageSize::Size1G.is_aligned(vaddr)
- && PageSize::Size1G.is_aligned(paddr)
+ let page_size = if PageSize::Size1G.is_aligned(vaddr) // vadddr is aligned to 1G
+ && PageSize::Size1G.is_aligned(paddr) // vaddr is aligned to 1G
&& size >= PageSize::Size1G as usize
&& !region.flags.contains(MemFlags::NO_HUGEPAGES)
+ // current hvisor this condition always be true
{
PageSize::Size1G
- } else if PageSize::Size2M.is_aligned(vaddr)
- && PageSize::Size2M.is_aligned(paddr)
+ } else if PageSize::Size2M.is_aligned(vaddr) // vadddr is aligned to 2M
+ && PageSize::Size2M.is_aligned(paddr) // paddr is aligned to 2M
&& size >= PageSize::Size2M as usize
&& !region.flags.contains(MemFlags::NO_HUGEPAGES)
+ // current hvisor this condition always be true
{
PageSize::Size2M
} else {
PageSize::Size4K
};
+ // debug!("page_size: {:#x?}", page_size);
let page = Page::new_aligned(vaddr.into(), page_size);
self.inner
.map_page(page, paddr, region.flags)
@@ -525,9 +582,13 @@ where
}
}
-// const fn p4_index(vaddr: usize) -> usize {
-// (vaddr >> (12 + 27)) & (ENTRY_COUNT - 1)
-// }
+const fn p5_index(vaddr: usize) -> usize {
+ (vaddr >> (12 + 36)) & (ENTRY_COUNT - 1)
+}
+
+const fn p4_index(vaddr: usize) -> usize {
+ (vaddr >> (12 + 27)) & (ENTRY_COUNT - 1)
+}
const fn p3_index(vaddr: usize) -> usize {
(vaddr >> (12 + 18)) & (ENTRY_COUNT - 1)
@@ -573,11 +634,3 @@ fn next_table_mut_or_create<'a, E: GenericPTE>(
next_table_mut(entry)
}
}
-#[allow(unused)]
-pub fn npages(sz: usize) -> usize {
- if sz & 0xfff == 0 {
- sz >> 12
- } else {
- (sz >> 12) + 1
- }
-}
diff --git a/src/arch/riscv64/s1pt.rs b/src/arch/riscv64/s1pt.rs
index c418badd..ac1131c3 100644
--- a/src/arch/riscv64/s1pt.rs
+++ b/src/arch/riscv64/s1pt.rs
@@ -25,7 +25,7 @@ use crate::memory::{
MemFlags,
};
-use super::paging::{GenericPTE, Level3PageTable, PagingInstr};
+use super::paging::{GenericPTE, HvPageTable, PagingInstr};
// |Reserved| PPN |RSW |Attr|
// | 63-54 | 53-10 |9-8 |7-0 |
@@ -178,4 +178,4 @@ impl PagingInstr for S1PTInstr {
}
}
-pub type Stage1PageTable = Level3PageTable;
+pub type Stage1PageTable = HvPageTable;
diff --git a/src/arch/riscv64/s2pt.rs b/src/arch/riscv64/s2pt.rs
index 0e267467..64dc962a 100644
--- a/src/arch/riscv64/s2pt.rs
+++ b/src/arch/riscv64/s2pt.rs
@@ -15,8 +15,8 @@
//
#![allow(unused)]
use super::{
- csr::{write_csr, CSR_HGATP},
- paging::{GenericPTE, Level3PageTable, PagingInstr},
+ csr::{read_csr, write_csr, CSR_HGATP},
+ paging::{GenericPTE, HvPageTable, PagingInstr},
};
use bit_field::BitField;
use core::fmt;
@@ -24,18 +24,58 @@ use numeric_enum_macro::numeric_enum;
use tock_registers::interfaces::Writeable;
use crate::memory::{
- addr::{HostPhysAddr, PhysAddr},
+ addr::{GuestPhysAddr, HostPhysAddr, PhysAddr},
MemFlags,
};
// |Reserved| PPN |RSW |Attr|
// | 63-54 | 53-10 |9-8 |7-0 |
+pub const HGATP_MODE_SHIFT: usize = 60;
+pub const HGATP_MODE_SV57X4: usize = 10;
+pub const HGATP_MODE_SV48X4: usize = 9;
+pub const HGATP_MODE_SV39X4: usize = 8;
+
+// Default G-stage mode is Sv39x4.
+static mut GSTAGE_MODE: usize = HGATP_MODE_SV39X4;
+pub static mut GSTAGE_PT_LEVEL: usize = 3;
+
+pub fn stage2_mode_detect() {
+ info!("Detecting stage-2 paging mode...");
+ unsafe {
+ // Attempt to set the HGATP.mode to Sv57x4 first.
+ let mode_sv57x4 = HGATP_MODE_SV57X4 << HGATP_MODE_SHIFT;
+ write_csr!(CSR_HGATP, mode_sv57x4);
+ if (read_csr!(CSR_HGATP) >> HGATP_MODE_SHIFT) == HGATP_MODE_SV57X4 {
+ GSTAGE_MODE = HGATP_MODE_SV57X4;
+ GSTAGE_PT_LEVEL = 5;
+ info!("Sv57x4 is supported.");
+ write_csr!(CSR_HGATP, 0);
+ hfence_gvma_all();
+ return;
+ }
+ // Attemp to set the HGATP.mode to Sv48x4.
+ let mode_sv48x4 = HGATP_MODE_SV48X4 << HGATP_MODE_SHIFT;
+ write_csr!(CSR_HGATP, mode_sv48x4);
+ if (read_csr!(CSR_HGATP) >> HGATP_MODE_SHIFT) == HGATP_MODE_SV48X4 {
+ GSTAGE_MODE = HGATP_MODE_SV48X4;
+ GSTAGE_PT_LEVEL = 4;
+ info!("Sv48x4 is supported.");
+ }
+ info!("Default stage-2 paging mode is Sv39x4.");
+ write_csr!(CSR_HGATP, 0);
+ hfence_gvma_all();
+ }
+}
+
+#[inline(always)]
+unsafe fn hfence_gvma_all() {
+ core::arch::asm!("hfence.gvma");
+}
+
bitflags::bitflags! {
- /// Memory attribute fields in the Sv39 translation table format descriptors.
#[derive(Clone, Copy, Debug)]
pub struct DescriptorAttr: u64 {
- // Attribute fields in stage 1 Sv39 Block and Page descriptors:
-
+ // In risc-v, bits[0..=7] is base attribute bits in PTE.
const VALID = 1 << 0;
// WHEN R|W|X is 0, this PTE is pointer to next level page table,else Block descriptor
const READABLE = 1 << 1;
@@ -45,12 +85,26 @@ bitflags::bitflags! {
const GLOBAL = 1 << 5;
const ACCESSED = 1 << 6;
const DIRTY = 1 << 7;
- // RSW fields is bit[8..9]:Reserved for Software
-
+ // RSW fields is bit[8..=9]:Reserved for Software
+ const RSW = 0b11 << 8;
+ // Reserved bits[54..=60]
+ const RESERVED = 0b111_1111 << 54;
+ // Svpbmt extension defines PBMT bitfields (Page-Based Memory Types) bits[61..=62]
+ const NOCACHE = 1 << 61; // Non-cacheable, idempotent, weakly-ordered (RVWMO), main memory
+ const IO = 1 << 62; // Non-cacheable, non-idempotent, strongly-ordered (I/O ordering), I/O
+ // Svnapot extension defines NAPOT bitfield (Naturally Aligned Power Of Two) bits[63]
+ const NAPOT = 1 << 63;
+ // Combined flags for PTE_HV_FLAGS (Accessed, Dirty, Global)
+ const PTE_HV_FLAGS = Self::ACCESSED.bits() | Self::DIRTY.bits() | Self::GLOBAL.bits();
+ // Combined flags for PTE_VM_FLAGS (Accessed, Dirty, User)
+ const PTE_VM_FLAGS = Self::ACCESSED.bits() | Self::DIRTY.bits() | Self::USER.bits();
+ // Combined flags for leaf descriptor (Read, Write, Execute)
+ const PTE_LEAF_FLAGS = Self::READABLE.bits() | Self::WRITABLE.bits() | Self::EXECUTABLE.bits();
}
}
impl From for MemFlags {
+ // Convert DescriptorAttr(arch-related) to MemFlags(abstract)
fn from(attr: DescriptorAttr) -> Self {
let mut flags = Self::empty();
if !attr.contains(DescriptorAttr::VALID) {
@@ -73,9 +127,10 @@ impl From for MemFlags {
}
impl From for DescriptorAttr {
+ // Convert MemFlags(abstract) to DescriptorAttr(arch-related)
fn from(flags: MemFlags) -> Self {
let mut attr = Self::empty();
- attr |= Self::VALID | Self::USER; //stage 2 page table must user
+ attr |= Self::VALID | Self::PTE_VM_FLAGS; // Set the valid bit and PTE_VM_FLAGS
if flags.contains(MemFlags::READ) {
attr |= Self::READABLE;
}
@@ -85,9 +140,6 @@ impl From for DescriptorAttr {
if flags.contains(MemFlags::EXECUTE) {
attr |= Self::EXECUTABLE;
}
- if flags.contains(MemFlags::USER) {
- attr |= Self::USER;
- }
attr
}
}
@@ -96,18 +148,24 @@ impl From for DescriptorAttr {
#[repr(transparent)]
pub struct PageTableEntry(pub u64);
const PTE_PPN_MASK: u64 = 0x3F_FFFF_FFFF_FC00; //[10..53]ppn
-const PPN_MASK: u64 = 0xFF_FFFF_FFFF_F000; //[12..55]ppn
+const PA_PPN_MASK: u64 = 0xFF_FFFF_FFFF_F000; //[12..55]ppn
impl PageTableEntry {
pub const fn empty() -> Self {
Self(0)
}
+ // Get the page table entry flags as MemFlags
+ fn pt_flags(&self) -> MemFlags {
+ DescriptorAttr::from_bits_truncate(self.0).into()
+ }
}
impl GenericPTE for PageTableEntry {
+ // Get physical address embedded in the page table entry.
fn addr(&self) -> HostPhysAddr {
PhysAddr::from(((self.0 & PTE_PPN_MASK) << 2) as usize) //[10:53] ppn
}
+ // Get the page table entry flags as MemFlags
fn flags(&self) -> MemFlags {
DescriptorAttr::from_bits_truncate(self.0).into()
}
@@ -121,25 +179,28 @@ impl GenericPTE for PageTableEntry {
}
fn is_huge(&self) -> bool {
- DescriptorAttr::from_bits_truncate(self.0).contains(DescriptorAttr::READABLE)
- | DescriptorAttr::from_bits_truncate(self.0).contains(DescriptorAttr::WRITABLE)
- | DescriptorAttr::from_bits_truncate(self.0).contains(DescriptorAttr::EXECUTABLE)
+ // Note: It is not possible to determine huge pages only by flags.
+ // But one huge page entry must be a leaf node.
+ DescriptorAttr::from_bits_truncate(self.0).intersects(DescriptorAttr::PTE_LEAF_FLAGS)
}
+ // Set the physical address embedded in the page table entry.
fn set_addr(&mut self, paddr: HostPhysAddr) {
- self.0 = (self.0.get_bits(0..7)) | ((paddr as u64 & PPN_MASK) >> 2);
+ // In RISC-V PTE, the physical address is stored in bits [10:53] of the entry.
+ self.0 = (self.0 & !PTE_PPN_MASK) | ((paddr as u64 & PA_PPN_MASK) >> 2);
}
+ // Set the flags embedded in the page table entry.
fn set_flags(&mut self, flags: MemFlags) {
let mut attr: DescriptorAttr = flags.into();
-
- self.0 = (attr.bits() & !PTE_PPN_MASK as u64) | (self.0 as u64 & PTE_PPN_MASK as u64);
+ self.0 = (attr.bits() & !PTE_PPN_MASK) | (self.0 & PTE_PPN_MASK);
}
+ // Set the page table entry as a table entry.
fn set_table(&mut self, paddr: HostPhysAddr) {
self.set_addr(paddr);
let attr = DescriptorAttr::VALID;
- self.0 = (attr.bits() & !PTE_PPN_MASK as u64) | (self.0 as u64 & PTE_PPN_MASK as u64);
+ self.0 = (attr.bits() & !PTE_PPN_MASK) | (self.0 & PTE_PPN_MASK);
}
fn clear(&mut self) {
@@ -147,15 +208,9 @@ impl GenericPTE for PageTableEntry {
}
}
-impl PageTableEntry {
- fn pt_flags(&self) -> MemFlags {
- DescriptorAttr::from_bits_truncate(self.0).into()
- }
-}
-
impl fmt::Debug for PageTableEntry {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
- f.debug_struct("Stage1PageTableEntry")
+ f.debug_struct("Stage2PageTableEntry")
.field("raw", &self.0)
.field("paddr", &self.addr())
.field("attr", &DescriptorAttr::from_bits_truncate(self.0))
@@ -168,23 +223,39 @@ pub struct S2PTInstr;
impl PagingInstr for S2PTInstr {
unsafe fn activate(root_paddr: HostPhysAddr) {
- println!("guest stage2 PT activate");
+ info!("guest stage2 PT activate, gstage_mode: {:#x?}", GSTAGE_MODE);
+ match GSTAGE_MODE {
+ HGATP_MODE_SV57X4 => {
+ info!("Using Sv57x4 mode.");
+ }
+ HGATP_MODE_SV48X4 => {
+ info!("Using Sv48x4 mode.");
+ }
+ _ => {
+ info!("Using default Sv39x4 mode.");
+ }
+ }
unsafe {
- let mut bits = 0usize;
- let mode: usize = 8; //Mode::Sv39x4
- let vmid: usize = 0;
- bits.set_bits(60..64, mode as usize);
- bits.set_bits(44..58, vmid);
- bits.set_bits(0..44, root_paddr >> 12);
- println!("HGATP: {:#x?}", bits);
+ let mut bits: usize = 0;
+ let mode: usize = GSTAGE_MODE; // GSTAGE_MODE is dynamically detected.
+ let vmid: usize = 0; // Default VMID is 0, in hvisor one CPU only supports one VMID.
+ bits.set_bits(60..64, mode as usize); // Set the HGATP mode.
+ bits.set_bits(44..58, vmid); // Set the VMID.
+ bits.set_bits(0..44, root_paddr >> 12); // Set the root page table's PPN.
write_csr!(CSR_HGATP, bits);
- //core::arch::asm!("hsfence.vvma");//not supported in rust
+ // info!("flush TLB: hfence.gvma, hfence.vvma");
+ let hgatp: usize = read_csr!(CSR_HGATP);
+ info!("HGATP after activation: {:#x?}", hgatp);
+ // hfence_gvma_all();
+ riscv_h::asm::hfence_gvma(0, 0); // Flush all stage-2 TLB entries.
}
}
fn flush(_vaddr: Option) {
- // do nothing
+ warn!("S2PTInstr::flush is not implemented.");
}
}
-pub type Stage2PageTable = Level3PageTable;
+// Here HvPageTable means Hvisor's Abstract Page Table, which is used for stage-2 paging & stage-1 paging.
+// Stage2PageTable is a specific type used for GPA->HPA.
+pub type Stage2PageTable = HvPageTable;
diff --git a/src/arch/riscv64/sbi.rs b/src/arch/riscv64/sbi.rs
index d3084750..4086f49d 100644
--- a/src/arch/riscv64/sbi.rs
+++ b/src/arch/riscv64/sbi.rs
@@ -17,7 +17,8 @@
use super::cpu::ArchCpu;
use crate::arch::csr::*;
-use crate::event::{send_event, IPI_EVENT_SEND_IPI, IPI_EVENT_WAKEUP};
+use crate::consts::IPI_EVENT_SEND_IPI;
+use crate::event::{send_event, IPI_EVENT_WAKEUP};
use crate::hypercall::HyperCall;
use crate::percpu::{get_cpu_data, this_cpu_data};
use core::sync::atomic::{self, Ordering};
@@ -27,7 +28,7 @@ use sbi_rt::{HartMask, SbiRet};
use sbi_spec::binary::{
RET_ERR_ALREADY_AVAILABLE, RET_ERR_FAILED, RET_ERR_NOT_SUPPORTED, RET_SUCCESS,
};
-use sbi_spec::{base, hsm, rfnc, spi, time};
+use sbi_spec::{base, hsm, legacy, rfnc, spi, time};
// Reserved for hvisor-tool.
pub const EID_HVISOR: usize = 0x114514;
@@ -90,6 +91,19 @@ pub fn sbi_vs_handler(current_cpu: &mut ArchCpu) {
EID_HVISOR => {
sbi_ret = sbi_hvisor_handler(current_cpu);
}
+ // Legacy::Console putchar (usually used), temporily don't support other legacy extensions.
+ legacy::LEGACY_CONSOLE_PUTCHAR => {
+ sbi_ret = SbiRet {
+ error: sbi_rt::legacy::console_putchar(current_cpu.x[10] as _),
+ value: 0,
+ };
+ }
+ legacy::LEGACY_CONSOLE_GETCHAR => {
+ sbi_ret = SbiRet {
+ error: sbi_rt::legacy::console_getchar(),
+ value: 0,
+ };
+ }
_ => {
// Pass through SBI call
warn!("Unsupported SBI extension {:#x} function {:#x}", eid, fid);
@@ -213,7 +227,7 @@ pub fn sbi_hsm_handler(fid: usize, current_cpu: &mut ArchCpu) -> SbiRet {
hsm::HART_SUSPEND => {
// Todo: support hart suspend.
sbi_ret.error = RET_ERR_NOT_SUPPORTED;
- warn!("SBI: unsupported sbi_hsm_hart_suspend");
+ // warn!("SBI: unsupported sbi_hsm_hart_suspend");
}
_ => {
sbi_ret.error = RET_ERR_NOT_SUPPORTED;
diff --git a/src/arch/riscv64/trap.rs b/src/arch/riscv64/trap.rs
index 35a4b23b..f1563fdc 100644
--- a/src/arch/riscv64/trap.rs
+++ b/src/arch/riscv64/trap.rs
@@ -17,10 +17,7 @@ use super::cpu::ArchCpu;
use crate::arch::csr::read_csr;
use crate::arch::csr::*;
use crate::arch::sbi::sbi_vs_handler;
-#[cfg(feature = "aia")]
-use crate::device::irqchip::aia::aplic::{host_aplic, vaplic_emul_handler};
-#[cfg(feature = "plic")]
-use crate::device::irqchip::plic::*;
+use crate::consts::{IPI_EVENT_SEND_IPI, IPI_EVENT_UPDATE_HART_LINE};
use crate::event::check_events;
use crate::memory::{mmio_handle_access, MMIOAccess};
use crate::memory::{GuestPhysAddr, HostPhysAddr};
@@ -93,8 +90,10 @@ pub const OPCODE_STORE: usize = 0x23;
pub const INS_C_FUNCT3_MASK: usize = 0xe000;
// compressed ins[1:0]
pub const INS_C_OPCODE_MASK: usize = 0x0003;
-pub const INS_C_LW: usize = 0x4000;
-pub const INS_C_SW: usize = 0xc000;
+pub const INS_C_LW: usize = 0x4000; // [15:13] = 0b010, [1:0] = 0b00
+pub const INS_C_SW: usize = 0xc000; // [15:13] = 0b110, [1:0] = 0b00
+pub const INS_C_LD: usize = 0x6000; // [15:13] = 0b011, [1:0] = 0b00
+pub const INS_C_SD: usize = 0xe000; // [15:13] = 0b111, [1:0] = 0b00
pub const INS_RS1_MASK: usize = 0x000f8000;
pub const INS_RS2_MASK: usize = 0x01f00000;
@@ -118,6 +117,7 @@ pub fn sync_exception_handler(current_cpu: &mut ArchCpu) {
trace!("CSR_SCAUSE: {}", trap_code);
if !riscv_h::register::hstatus::read().spv() {
+ warn!("Trap Cause: {}", CAUSE_STRINGS[trap_code]);
// Hvisor don't handle sync exception which occurs in hvisor self (HS-mode).
// If sync exception occurs, hvisor will panic!
panic!("exception from HS mode");
@@ -145,14 +145,16 @@ pub fn sync_exception_handler(current_cpu: &mut ArchCpu) {
guest_page_fault_handler(current_cpu);
}
_ => {
- let raw_inst = read_inst(trap_pc);
- let inst = riscv_decode::decode(raw_inst);
warn!(
"CPU {} sync exception, sepc: {:#x}",
current_cpu.cpuid, current_cpu.sepc
);
- warn!("Trap cause code: {}", trap_code);
+ warn!("Trap Cause: {}", CAUSE_STRINGS[trap_code]);
warn!("htval: {:#x}, htinst: {:#x}", trap_value, trap_ins);
+ // Some exceptions occur, read_inst may cause load guest-page fault.
+ // Because read_inst use hlvxhu to read instruction from guest memory.
+ let raw_inst = read_inst(trap_pc);
+ let inst = riscv_decode::decode(raw_inst);
warn!("trap instruction: {:?}", inst);
panic!("Unhandled sync exception");
}
@@ -183,13 +185,23 @@ pub fn ins_ldst_decode(ins: usize) -> (usize, bool, bool, usize) {
// Here, for compressed instruction, only C.LW and C.SW are supported.
let ins_is_clw = ins & (INS_C_OPCODE_MASK | INS_C_FUNCT3_MASK) == INS_C_LW;
let ins_is_csw = ins & (INS_C_OPCODE_MASK | INS_C_FUNCT3_MASK) == INS_C_SW;
- if (ins_is_clw == false) && (ins_is_csw == false) {
- panic!("trap instruction is not C.LW or C.SW, inst 0x{:04x}.", ins);
+ let ins_is_cld = ins & (INS_C_OPCODE_MASK | INS_C_FUNCT3_MASK) == INS_C_LD;
+ let ins_is_csd = ins & (INS_C_OPCODE_MASK | INS_C_FUNCT3_MASK) == INS_C_SD;
+ if (ins_is_clw == false)
+ && (ins_is_csw == false)
+ && (ins_is_cld == false)
+ && (ins_is_csd == false)
+ {
+ panic!(
+ "trap instruction is not C.LW, C.SW, C.LD or C.SD, inst 0x{:04x}.",
+ ins
+ );
}
- let is_write = ins_is_csw;
+ let size = if (ins_is_cld || ins_is_csd) { 8 } else { 4 };
+ let is_write = ins_is_csw || ins_is_csd;
// Decode register number.
let reg = ((ins >> 2) & 0x7) + 8;
- (4, is_write, true, reg)
+ (size, is_write, true, reg)
} else {
let ins_is_load = ins & INS_OPCODE_MASK == OPCODE_LOAD;
let ins_is_store = ins & INS_OPCODE_MASK == OPCODE_STORE;
@@ -226,231 +238,93 @@ pub fn ins_ldst_decode(ins: usize) -> (usize, bool, bool, usize) {
/// Handle guest page fault sync exception.
pub fn guest_page_fault_handler(current_cpu: &mut ArchCpu) {
- #[cfg(feature = "plic")]
- {
- use riscv_h::register::{htinst, htval, stval};
- // htval: Hypervisor bad guest physical address.
- let addr: usize = (htval::read() << 2) | (stval::read() & 0x3);
- // htinst: Hypervisor trap instruction (transformed).
- let mut trap_ins = htinst::read();
- // Default instruction size is 4 bytes.
- let mut ins_size = 4;
-
+ use riscv_h::register::{htinst, htval, stval};
+ // htval: Hypervisor bad guest physical address.
+ let addr: usize = (htval::read() << 2) | (stval::read() & 0x3);
+ // htinst: Hypervisor trap instruction (transformed).
+ let mut trap_ins = htinst::read();
+ // Default instruction size is 4 bytes.
+ let mut ins_size = 4;
+ /*
+ * According riscv spec, htinst is one of the following:
+ * 1. zero;
+ * 2. a transformation of the trapping instruction;
+ * 3. a custom value;
+ * 4. a special pseudoinstruction.
+ */
+ if trap_ins == 0 {
/*
- * According riscv spec, htinst is one of the following:
- * 1. zero;
- * 2. a transformation of the trapping instruction;
- * 3. a custom value;
- * 4. a special pseudoinstruction.
+ * An implementation may at any time reduce its effort by substituting zero in place of the transformed instruction.
+ * Handling this case is important to be more compatible with different hardware.
*/
-
- if trap_ins == 0 {
- /*
- * An implementation may at any time reduce its effort by substituting zero in place of the transformed instruction.
- * Handling this case is important to be more compatible with different hardware.
- */
- // Get trap instruction from memory.
- trap_ins = read_inst(current_cpu.sepc) as _;
- if ins_is_compressed(trap_ins as _) {
- ins_size = 2;
- } else {
- ins_size = 4;
- }
- } else if ins_is_preudo(trap_ins) {
- /*
- * If the instruction is a pseudo instruction, it will be transformed to a standard instruction.
- * The pseudo instruction will be replaced with a standard instruction.
- */
- panic!("No support for htinst pseudo instruction.");
+ // Get trap instruction from memory.
+ trap_ins = read_inst(current_cpu.sepc) as _;
+ if ins_is_compressed(trap_ins as _) {
+ ins_size = 2;
} else {
- /*
- * For a standard compressed instruction (16-bit size), the transformed instruction is found as follows:
- * 1. Expand the compressed instruction to its 32-bit equivalent.
- * 2. Transform the 32-bit equivalent instruction.
- * 3. Replace bit 1 with a 0.
- *
- * RISCV Spec: Bits[1:0] of a transformed standard instruction will be binary 01
- * if the trapping instruction is compressed and 11 if not.
- */
- ins_size = match trap_ins & 0x3 {
- 0x1 => 2,
- 0x3 => 4,
- _ => panic!("Invalid instruction size."),
- };
- /*
- * Bit[0] == 1, and replacing bit 1 with 1 makes the value
- * into a valid encoding of a standard instruction.
- */
- trap_ins = trap_ins | 0x2;
+ ins_size = 4;
}
-
- // Decode instruction to get size, is_write, sign_ext and register number.
- // For load, reg is rd, and for store, reg is rs2.
- let (size, is_write, sign_ext, reg) = ins_ldst_decode(trap_ins);
-
- // create mmio access struct.
- let mut mmio_access = MMIOAccess {
- address: addr as _,
- size: size as _,
- is_write: is_write as _,
- value: if is_write { current_cpu.x[reg] as _ } else { 0 },
+ } else if ins_is_preudo(trap_ins) {
+ /*
+ * If the instruction is a pseudo instruction, it will be transformed to a standard instruction.
+ * The pseudo instruction will be replaced with a standard instruction.
+ */
+ panic!("No support for htinst pseudo instruction.");
+ } else {
+ /*
+ * For a standard compressed instruction (16-bit size), the transformed instruction is found as follows:
+ * 1. Expand the compressed instruction to its 32-bit equivalent.
+ * 2. Transform the 32-bit equivalent instruction.
+ * 3. Replace bit 1 with a 0.
+ *
+ * RISCV Spec: Bits[1:0] of a transformed standard instruction will be binary 01
+ * if the trapping instruction is compressed and 11 if not.
+ */
+ ins_size = match trap_ins & 0x3 {
+ 0x1 => 2,
+ 0x3 => 4,
+ _ => panic!("Invalid instruction size."),
};
-
- match mmio_handle_access(&mut mmio_access) {
- Ok(_) => {
- if !is_write {
- current_cpu.x[reg] = if reg == 0 {
- 0
- } else {
- // for load instruction, x[rd] will be written.
- if sign_ext {
- // note: this is used for 64bit system.
- (((mmio_access.value << (64 - 8 * size)) as i64) >> (64 - 8 * size))
- as usize
- } else {
- mmio_access.value
- }
- };
- }
- }
- Err(e) => {
- panic!("mmio_handle_access: {:#x?}", e);
- }
- }
- debug!("guest page fault at {:#x}, trap_ins: {:08x}, size: {}, is_write: {}, sign_ext: {}, reg: {}", addr, trap_ins, size, is_write, sign_ext, reg);
- // Add inst size.
- current_cpu.sepc += ins_size;
+ /*
+ * Bit[0] == 1, and replacing bit 1 with 1 makes the value
+ * into a valid encoding of a standard instruction.
+ */
+ trap_ins = trap_ins | 0x2;
}
- #[cfg(feature = "aia")]
- {
- let addr: HostPhysAddr = read_csr!(CSR_HTVAL) << 2;
- trace!("guest page fault at {:#x}", addr);
-
- let host_aplic_base = host_aplic().read().base;
- let host_aplic_size = host_aplic().read().size;
-
- if addr >= host_aplic_base && addr < host_aplic_base + host_aplic_size {
- trace!("APLIC access");
- let mut inst: u32 = read_csr!(CSR_HTINST) as u32;
- let mut ins_size: usize = 0;
- if inst == 0 {
- let inst_addr: GuestPhysAddr = current_cpu.sepc;
- inst = read_inst(inst_addr);
- ins_size = if inst & 0x3 == 3 { 4 } else { 2 };
- } else if inst == 0x3020 || inst == 0x3000 {
- error!("fault on 1st stage page table walk");
- } else {
- ins_size = if (inst) & 0x2 == 0 { 2 } else { 4 };
- inst = inst | 0b10;
- // error!("unhandled guest page fault at {:#x}", addr);
- }
- // let (len, inst) = decode_inst(inst);
- let (_, inst) = decode_inst(inst);
-
- if let Some(inst) = inst {
- vaplic_emul_handler(current_cpu, addr, inst);
- current_cpu.sepc += ins_size;
- } else {
- error!("Invalid instruction at {:#x}", current_cpu.sepc);
- }
- } else {
- // warn!("guest page fault at {:#x}", addr);
- use riscv_h::register::{htinst, htval, stval};
- // htval: Hypervisor bad guest physical address.
- let addr: usize = (htval::read() << 2) | (stval::read() & 0x3);
- // htinst: Hypervisor trap instruction (transformed).
- let mut trap_ins = htinst::read();
- // Default instruction size is 4 bytes.
- let mut ins_size = 4;
-
- /*
- * According riscv spec, htinst is one of the following:
- * 1. zero;
- * 2. a transformation of the trapping instruction;
- * 3. a custom value;
- * 4. a special pseudoinstruction.
- */
-
- if trap_ins == 0 {
- /*
- * An implementation may at any time reduce its effort by substituting zero in place of the transformed instruction.
- * Handling this case is important to be more compatible with different hardware.
- */
- // Get trap instruction from memory.
- trap_ins = read_inst(current_cpu.sepc) as _;
- if ins_is_compressed(trap_ins as _) {
- ins_size = 2;
+ // Decode instruction to get size, is_write, sign_ext and register number.
+ // For load, reg is rd, and for store, reg is rs2.
+ let (size, is_write, sign_ext, reg) = ins_ldst_decode(trap_ins);
+ // create mmio access struct.
+ let mut mmio_access = MMIOAccess {
+ address: addr as _,
+ size: size as _,
+ is_write: is_write as _,
+ value: if is_write { current_cpu.x[reg] as _ } else { 0 },
+ };
+ match mmio_handle_access(&mut mmio_access) {
+ Ok(_) => {
+ if !is_write {
+ current_cpu.x[reg] = if reg == 0 {
+ 0
} else {
- ins_size = 4;
- }
- } else if ins_is_preudo(trap_ins) {
- /*
- * If the instruction is a pseudo instruction, it will be transformed to a standard instruction.
- * The pseudo instruction will be replaced with a standard instruction.
- */
- panic!("No support for htinst pseudo instruction.");
- } else {
- /*
- * For a standard compressed instruction (16-bit size), the transformed instruction is found as follows:
- * 1. Expand the compressed instruction to its 32-bit equivalent.
- * 2. Transform the 32-bit equivalent instruction.
- * 3. Replace bit 1 with a 0.
- *
- * RISCV Spec: Bits[1:0] of a transformed standard instruction will be binary 01
- * if the trapping instruction is compressed and 11 if not.
- */
- ins_size = match trap_ins & 0x3 {
- 0x1 => 2,
- 0x3 => 4,
- _ => panic!("Invalid instruction size."),
- };
- /*
- * Bit[0] == 1, and replacing bit 1 with 1 makes the value
- * into a valid encoding of a standard instruction.
- */
- trap_ins = trap_ins | 0x2;
- }
-
- // Decode instruction to get size, is_write, sign_ext and register number.
- // For load, reg is rd, and for store, reg is rs2.
- let (size, is_write, sign_ext, reg) = ins_ldst_decode(trap_ins);
- // warn!("size: {}, is_write: {}, sign_ext: {}, reg: {}", size, is_write, sign_ext, reg);
-
- // create mmio access struct.
- let mut mmio_access = MMIOAccess {
- address: addr as _,
- size: size as _,
- is_write: is_write as _,
- value: if is_write { current_cpu.x[reg] as _ } else { 0 },
- };
-
- match mmio_handle_access(&mut mmio_access) {
- Ok(_) => {
- if !is_write {
- current_cpu.x[reg] = if reg == 0 {
- 0
- } else {
- // for load instruction, x[rd] will be written.
- if sign_ext {
- // note: this is used for 64bit system.
- // warn!("value: 0x{:x}",(((mmio_access.value << (64 - 8 * size)) as i64) >> (64 - 8 * size)));
- (((mmio_access.value << (64 - 8 * size)) as i64) >> (64 - 8 * size))
- as usize
- } else {
- mmio_access.value
- }
- };
- // warn!("current_cpu.x[{}]: 0x{:x}", reg, current_cpu.x[reg]);
+ // for load instruction, x[rd] will be written.
+ if sign_ext {
+ // note: this is used for 64bit system.
+ (((mmio_access.value << (64 - 8 * size)) as i64) >> (64 - 8 * size))
+ as usize
+ } else {
+ mmio_access.value
}
- }
- Err(e) => {
- panic!("CPU {} unmaped memmory at {:#x}", current_cpu.cpuid, addr);
- }
+ };
}
- current_cpu.sepc += ins_size;
- // panic!("CPU {} unmaped memmory at {:#x}", current_cpu.cpuid, addr);
+ }
+ Err(e) => {
+ panic!("mmio_handle_access: {:#x?}", e);
}
}
+ debug!("guest page fault at {:#x}, trap_ins: {:08x}, size: {}, is_write: {}, sign_ext: {}, reg: {}", addr, trap_ins, size, is_write, sign_ext, reg);
+ // Add inst size.
+ current_cpu.sepc += ins_size;
}
/// Read instruction from guest memory.
@@ -506,6 +380,7 @@ pub fn interrupts_arch_handle(current_cpu: &mut ArchCpu) {
handle_timer_interrupt(current_cpu);
}
InterruptType::SSI => {
+ // warn!("IPI receive: {}", current_cpu.cpuid);
// Get event to handle and clear software interrupt pending bit.
handle_software_interrupt(current_cpu);
}
@@ -547,7 +422,7 @@ pub fn handle_external_interrupt(current_cpu: &mut ArchCpu) {
// Note: in hvisor, all external interrupts are assigned to VS.
// 1. claim hw irq.
let context_id = 2 * this_cpu_data().id + 1;
- let irq_id = host_plic().claim(context_id);
+ let irq_id = crate::device::irqchip::plic::host_plic().claim(context_id);
// If this irq has been claimed, it will be 0.
if irq_id == 0 {
@@ -555,10 +430,11 @@ pub fn handle_external_interrupt(current_cpu: &mut ArchCpu) {
}
// 2. inject hw irq to zone.
- inject_irq(irq_id as usize, true);
+ crate::device::irqchip::plic::inject_irq(irq_id as usize, true);
}
#[cfg(feature = "aia")]
{
+ // Note: no irq belongs to hvisor, so hvisor won't handle external interrupt.
panic!("HS extensional interrupt")
}
}
diff --git a/src/arch/riscv64/zone.rs b/src/arch/riscv64/zone.rs
index ed944805..32c9952a 100644
--- a/src/arch/riscv64/zone.rs
+++ b/src/arch/riscv64/zone.rs
@@ -24,9 +24,11 @@ use crate::{
impl Zone {
pub fn pt_init(&mut self, mem_regions: &[HvConfigMemoryRegion]) -> HvResult {
for mem_region in mem_regions.iter() {
- let mut flags = MemFlags::READ | MemFlags::WRITE | MemFlags::EXECUTE;
- if mem_region.mem_type == MEM_TYPE_IO {
- flags |= MemFlags::IO;
+ let mut flags = MemFlags::READ | MemFlags::WRITE;
+ // Note: in riscv, base flags are D/A/G/U/W/X, some mem attributes are embedded in the PMA.
+ // Svpbmt extension is not supported in current hvisor(G-Stage).
+ if mem_region.mem_type == MEM_TYPE_RAM {
+ flags |= MemFlags::EXECUTE;
}
match mem_region.mem_type {
MEM_TYPE_RAM | MEM_TYPE_IO => {
@@ -50,65 +52,14 @@ impl Zone {
}
}
}
- #[cfg(feature = "aia")]
- {
- use crate::memory::PAGE_SIZE;
- let paddr = 0x2800_0000 as HostPhysAddr;
- let size = PAGE_SIZE;
- self.gpm.insert(MemoryRegion::new_with_offset_mapper(
- paddr as GuestPhysAddr,
- paddr + PAGE_SIZE * 1,
- size,
- MemFlags::READ | MemFlags::WRITE,
- ))?;
-
- let paddr = 0x2800_1000 as HostPhysAddr;
- let size = PAGE_SIZE;
- self.gpm.insert(MemoryRegion::new_with_offset_mapper(
- paddr as GuestPhysAddr,
- paddr + PAGE_SIZE * 2,
- size,
- MemFlags::READ | MemFlags::WRITE,
- ))?;
-
- let paddr = 0x2800_2000 as HostPhysAddr;
- let size = PAGE_SIZE;
- self.gpm.insert(MemoryRegion::new_with_offset_mapper(
- paddr as GuestPhysAddr,
- paddr + PAGE_SIZE * 3,
- size,
- MemFlags::READ | MemFlags::WRITE,
- ))?;
-
- let paddr = 0x2800_3000 as HostPhysAddr;
- let size = PAGE_SIZE;
- self.gpm.insert(MemoryRegion::new_with_offset_mapper(
- paddr as GuestPhysAddr,
- paddr + PAGE_SIZE * 4,
- size,
- MemFlags::READ | MemFlags::WRITE,
- ))?;
- }
info!("VM stage 2 memory set: {:#x?}", self.gpm);
Ok(())
}
- pub fn isa_init(&mut self, fdt: &fdt::Fdt) {
- let cpu_set = self.cpu_set;
- cpu_set.iter().for_each(|cpuid| {
- let cpu_data = get_cpu_data(cpuid);
- let cpu_isa = fdt
- .cpus()
- .find(|cpu| cpu.ids().all().next().unwrap() == cpuid)
- .unwrap()
- .properties()
- .find(|p| p.name == "riscv,isa")
- .unwrap();
- if cpu_isa.as_str().unwrap().contains("sstc") {
- println!("cpu{} support sstc", cpuid);
- cpu_data.arch_cpu.sstc = true;
- }
- })
+ pub fn arch_zone_configuration(&mut self, config: &HvZoneConfig) -> HvResult {
+ // We do not have any specific architecture configuration for RISC-V.
+ // If needed, this function can be extended in the future.
+ Ok(())
}
}
diff --git a/src/config.rs b/src/config.rs
index ebb323f1..7d72f45d 100644
--- a/src/config.rs
+++ b/src/config.rs
@@ -22,7 +22,7 @@ pub const MEM_TYPE_RAM: u32 = 0;
pub const MEM_TYPE_IO: u32 = 1;
pub const MEM_TYPE_VIRTIO: u32 = 2;
-pub const CONFIG_MAGIC_VERSION: usize = 0x1;
+pub const CONFIG_MAGIC_VERSION: usize = 0x3;
pub const CONFIG_MAX_MEMORY_REGIONS: usize = 64;
pub const CONFIG_MAX_INTERRUPTS: usize = 32;
pub const CONFIG_NAME_MAXLEN: usize = 32;
diff --git a/src/consts.rs b/src/consts.rs
index cc97b80e..c78adbe8 100644
--- a/src/consts.rs
+++ b/src/consts.rs
@@ -30,7 +30,7 @@ pub const INVALID_ADDRESS: usize = usize::MAX;
pub const MAX_CPU_NUM: usize = BOARD_NCPUS;
-pub const MAX_ZONE_NUM: usize = 3;
+pub const MAX_ZONE_NUM: usize = 4;
pub const MAX_WAIT_TIMES: usize = 10000000;
@@ -46,6 +46,11 @@ pub fn hv_end() -> VirtAddr {
mem_pool_start() + HV_MEM_POOL_SIZE
}
+/// arch specific constants
+pub const IPI_EVENT_CLEAR_INJECT_IRQ: usize = 4;
+pub const IPI_EVENT_UPDATE_HART_LINE: usize = 5;
+pub const IPI_EVENT_SEND_IPI: usize = 6;
+
extern "C" {
fn __core_end();
}
diff --git a/src/device/eic7700_syscrg.rs b/src/device/eic7700_syscrg.rs
new file mode 100644
index 00000000..d6049309
--- /dev/null
+++ b/src/device/eic7700_syscrg.rs
@@ -0,0 +1,113 @@
+// Copyright (c) 2025 Syswonder
+// hvisor is licensed under Mulan PSL v2.
+// You can use this software according to the terms and conditions of the Mulan PSL v2.
+// You may obtain a copy of Mulan PSL v2 at:
+// http://license.coscl.org.cn/MulanPSL2
+// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+// FIT FOR A PARTICULAR PURPOSE.
+// See the Mulan PSL v2 for more details.
+//
+// Syswonder Website:
+// https://www.syswonder.org
+//
+// Authors: Jingyu Liu
+//
+
+// ESWIN Eic7700x SysCrg Emulation
+
+pub const EIC7700_SYSCRG_BASE: usize = 0x51828000;
+pub const EIC7700_SYSCRG_SIZE: usize = 0x80000;
+pub const EIC7700_HSP_SP_TOP_CSR_BASE: usize = 0x50440000;
+pub const EIC7700_HSP_SP_TOP_CSR_SIZE: usize = 0x2000;
+
+use crate::arch::zone::HvArchZoneConfig;
+use crate::error::{self, HvResult};
+use crate::memory::mmio::MMIOAccess;
+use crate::zone::Zone;
+
+pub fn virtual_syscrg_handler(mmio: &mut MMIOAccess, _arg: usize) -> HvResult {
+ let addr = mmio.address + EIC7700_SYSCRG_BASE;
+ use core::ptr::{read_volatile, write_volatile};
+ unsafe {
+ if mmio.is_write {
+ info!(
+ "Syscrg MMIO write: addr=0x{:x}, value=0x{:x}, size={}",
+ mmio.address, mmio.value, mmio.size
+ );
+ match mmio.size {
+ 1 => write_volatile(addr as *mut u8, mmio.value as u8),
+ 2 => write_volatile(addr as *mut u16, mmio.value as u16),
+ 4 => write_volatile(addr as *mut u32, mmio.value as u32),
+ 8 => write_volatile(addr as *mut u64, mmio.value as u64),
+ _ => panic!("Unsupported MMIO write size: {}", mmio.size),
+ }
+ } else {
+ mmio.value = match mmio.size {
+ 1 => read_volatile(addr as *const u8) as _,
+ 2 => read_volatile(addr as *const u16) as _,
+ 4 => read_volatile(addr as *const u32) as _,
+ 8 => read_volatile(addr as *const u64) as _,
+ _ => panic!("Unsupported MMIO read size: {}", mmio.size),
+ };
+ debug!(
+ "Syscrg MMIO read: addr=0x{:x}, value=0x{:x}, size={}",
+ mmio.address, mmio.value, mmio.size
+ );
+ }
+ }
+
+ Ok(())
+}
+
+pub fn virtual_hsp_sp_top_csr_handler(mmio: &mut MMIOAccess, _arg: usize) -> HvResult {
+ let addr = mmio.address + EIC7700_HSP_SP_TOP_CSR_BASE;
+ use core::ptr::{read_volatile, write_volatile};
+ unsafe {
+ if mmio.is_write {
+ info!(
+ "Hsp_sp_top_csr MMIO write: addr=0x{:x}, value=0x{:x}, size={}",
+ mmio.address, mmio.value, mmio.size
+ );
+ match mmio.size {
+ 1 => write_volatile(addr as *mut u8, mmio.value as u8),
+ 2 => write_volatile(addr as *mut u16, mmio.value as u16),
+ 4 => write_volatile(addr as *mut u32, mmio.value as u32),
+ 8 => write_volatile(addr as *mut u64, mmio.value as u64),
+ _ => panic!("Unsupported MMIO write size: {}", mmio.size),
+ }
+ } else {
+ mmio.value = match mmio.size {
+ 1 => read_volatile(addr as *const u8) as _,
+ 2 => read_volatile(addr as *const u16) as _,
+ 4 => read_volatile(addr as *const u32) as _,
+ 8 => read_volatile(addr as *const u64) as _,
+ _ => panic!("Unsupported MMIO read size: {}", mmio.size),
+ };
+ debug!(
+ "Hsp_sp_top_csr MMIO read: addr=0x{:x}, value=0x{:x}, size={}",
+ mmio.address, mmio.value, mmio.size
+ );
+ }
+ }
+
+ Ok(())
+}
+
+impl Zone {
+ /// Initialize syscon MMIO region.
+ pub fn virtual_syscon_mmio_init(&mut self) {
+ self.mmio_region_register(
+ EIC7700_SYSCRG_BASE,
+ EIC7700_SYSCRG_SIZE,
+ virtual_syscrg_handler,
+ 0,
+ );
+ self.mmio_region_register(
+ EIC7700_HSP_SP_TOP_CSR_BASE,
+ EIC7700_HSP_SP_TOP_CSR_SIZE,
+ virtual_hsp_sp_top_csr_handler,
+ 0,
+ );
+ }
+}
diff --git a/src/device/irqchip/aia/aplic.rs b/src/device/irqchip/aia/aplic.rs
index 6851ad81..b92556a3 100644
--- a/src/device/irqchip/aia/aplic.rs
+++ b/src/device/irqchip/aia/aplic.rs
@@ -11,7 +11,7 @@
// Syswonder Website:
// https://www.syswonder.org
//
-// Authors:
+// Authors: Jingyu Liu
//
use crate::config::root_zone_config;
@@ -21,28 +21,80 @@ use crate::{arch::cpu::ArchCpu, memory::GuestPhysAddr, percpu::this_cpu_data};
use riscv_decode::Instruction;
use spin::Once;
use spin::RwLock;
-// S-mode interrupt delivery controller
-const APLIC_S_IDC: usize = 0xd00_4000;
+
+/*
+ APLIC Memory Map:
+
+ base + 0x0000 4 bytes domaincfg
+ base + 0x0004 4 bytes sourcecfg[1]
+ base + 0x0008 4 bytes sourcecfg[2]
+ ...
+ base + 0x0FFC 4 bytes sourcecfg[1023]
+ base + 0x1BC0 4 bytes mmsiaddrcfg (machine-level interrupt domains only)
+ base + 0x1BC4 4 bytes mmsiaddrcfgh ”
+ base + 0x1BC8 4 bytes smsiaddrcfg ”
+ base + 0x1BCC 4 bytes smsiaddrcfgh ”
+ base + 0x1C00 4 bytes setip[0]
+ base + 0x1C04 4 bytes setip[1]
+ ...
+ base + 0x1C7C 4 bytes setip[31]
+ base + 0x1CDC 4 bytes setipnum
+ base + 0x1D00 4 bytes in clrip[0]
+ base + 0x1D04 4 bytes in clrip[1]
+ ..
+ base + 0x1D7C 4 bytes in clrip[31]
+ base + 0x1DDC 4 bytes clripnum
+ base + 0x1E00 4 bytes setie[0]
+ base + 0x1E04 4 bytes setie[1]
+ ...
+ base + 0x1E7C 4 bytes setie[31]
+ base + 0x1EDC 4 bytes setienum
+ base + 0x1F00 4 bytes clrie[0]
+ base + 0x1F04 4 bytes clrie[1]
+ ..
+ base + 0x1F7C 4 bytes clrie[31]
+ base + 0x1FDC 4 bytes clrienum
+ base + 0x2000 4 bytes setipnum le
+ base + 0x2004 4 bytes setipnum be
+ base + 0x3000 4 bytes genmsi
+ base + 0x3004 4 bytes target[1]
+ base + 0x3008 4 bytes target[2]
+ ...
+ base + 0x3FFC 4 bytes target[1023]
+*/
+
+// S-mode Interrupt Domain
pub const APLIC_DOMAINCFG_BASE: usize = 0x0000;
-pub const APLIC_SOURCECFG_BASE: usize = 0x0004;
+pub const APLIC_SOURCECFG_BASE: usize = 0x0004; // [APLIC_SOURCECFG_BASE, APLIC_SOURCECFG_TOP)
pub const APLIC_SOURCECFG_TOP: usize = 0x1000;
-pub const APLIC_MSIADDR_BASE: usize = 0x1BC8;
-pub const APLIC_PENDING_BASE: usize = 0x1C00;
-pub const APLIC_PENDING_TOP: usize = 0x1C7C;
-pub const APLIC_IPNUM_BASE: usize = 0x1CDC;
-pub const APLIC_CLRIP_BASE: usize = 0x1D00;
-pub const APLIC_ENABLE_BASE: usize = 0x1E00;
-pub const APLIC_ENABLE_TOP: usize = 0x1E7C;
-pub const APLIC_ENABLE_NUM: usize = 0x1EDC;
-pub const APLIC_CLRIE_BASE: usize = 0x1F00;
-pub const APLIC_CLRIE_NUM_BASE: usize = 0x1FDC;
-pub const APLIC_IPNUM_LE_BASE: usize = 0x2000;
-pub const APLIC_TARGET_BASE: usize = 0x3004;
-pub const APLIC_IDC_BASE: usize = 0x4000;
-
-#[repr(u32)]
+pub const APLIC_MSIADDR_BASE: usize = 0x1BC8; // smsiaddrcfg
+pub const APLIC_SETIP_BASE: usize = 0x1C00; // [APLIC_SETIP_BASE, APLIC_SETIP_TOP)
+pub const APLIC_SETIP_TOP: usize = 0x1C80;
+pub const APLIC_SETIPNUM_BASE: usize = 0x1CDC;
+pub const APLIC_CLRIP_BASE: usize = 0x1D00; // [APLIC_CLRIP_BASE, APLIC_CLRIP_TOP)
+pub const APLIC_CLRIP_TOP: usize = 0x1D80;
+pub const APLIC_CLRIPNUM_BASE: usize = 0x1DDC;
+pub const APLIC_SETIE_BASE: usize = 0x1E00; // [APLIC_SETIE_BASE, APLIC_SETIE_TOP)
+pub const APLIC_SETIE_TOP: usize = 0x1E80;
+pub const APLIC_SETIENUM_BASE: usize = 0x1EDC;
+pub const APLIC_CLRIE_BASE: usize = 0x1F00; // [APLIC_CLRIE_BASE, APLIC_CLRIE_TOP)
+pub const APLIC_CLRIE_TOP: usize = 0x1F80;
+pub const APLIC_CLRIENUM_BASE: usize = 0x1FDC;
+pub const APLIC_SETIPNUM_LE_BASE: usize = 0x2000;
+pub const APLIC_SETIPNUM_BE_BASE: usize = 0x2004;
+pub const APLIC_GENMSI_BASE: usize = 0x3000;
+pub const APLIC_TARGET_BASE: usize = 0x3004; // [APLIC_TARGET_BASE, APLIC_TARGET_TOP)
+pub const APLIC_TARGET_TOP: usize = 0x4000;
+
+#[allow(dead_code)]
+pub enum DeliveryMode {
+ Direct = 0,
+ MSI = 1,
+}
+
#[allow(dead_code)]
-pub enum SourceModes {
+#[derive(PartialEq)]
+pub enum SourceMode {
Inactive = 0,
Detached = 1,
RisingEdge = 4,
@@ -51,100 +103,73 @@ pub enum SourceModes {
LevelLow = 7,
}
-// offset size register name
-// 0x0000 4 bytes domaincfg
-// 0x0004 4 bytes sourcecfg[1]
-// 0x0008 4 bytes sourcecfg[2]
-// . . . . . .
-// 0x0FFC 4 bytes sourcecfg[1023]
-// 0x1BC0 4 bytes mmsiaddrcfg (machine-level interrupt domains only)
-// 0x1BC4 4 bytes mmsiaddrcfgh ”
-// 0x1BC8 4 bytes smsiaddrcfg ”
-// 0x1BCC 4 bytes smsiaddrcfgh ”
-// 0x1C00 4 bytes setip[0]
-// 0x1C04 4 bytes setip[1]
-// . . . . . .
-// 0x1C7C 4 bytes setip[31]
-// 0x1CDC 4 bytes setipnum
-// 0x1D00 4 bytes in clrip[0]
-// 0x1D04 4 bytes in clrip[1]
-// . . . . . .
-// 0x1D7C 4 bytes in clrip[31]
-// 0x1DDC 4 bytes clripnum
-// 0x1E00 4 bytes setie[0]
-// 0x1E04 4 bytes setie[1]
-// . . . . . .
-// 0x1E7C 4 bytes setie[31]
-// 0x1EDC 4 bytes setienum
-// 0x1F00 4 bytes clrie[0]
-// 0x1F04 4 bytes clrie[1]
-// . . . . . .
-// 0x1F7C 4 bytes clrie[31]
-// 0x1FDC 4 bytes clrienum
-// 0x2000 4 bytes setipnum le
-// 0x2004 4 bytes setipnum be
-// 0x3000 4 bytes genmsi
-// 0x3004 4 bytes target[1]
-// 0x3008 4 bytes target[2]
-// . . . . . .
-// 0x3FFC 4 bytes target[1023]
-
-pub fn primary_init_early() {
- let root_config = root_zone_config();
- init_aplic(
- root_config.arch_config.aplic_base as usize,
- root_config.arch_config.aplic_size as usize,
- );
-}
-pub fn primary_init_late() {
- //nothing to do
-}
-pub fn percpu_init() {
- //nothing to do
-}
-pub fn inject_irq(_irq: usize, is_hardware: bool) {
- // info!("inject_irq _irq: {} is_hardware {}", _irq, is_hardware);
- let host_aplic = host_aplic();
- let (hart, guest, eiid) = host_aplic.read().get_target_info(_irq as u32);
- imsic_trigger(hart, guest, eiid);
-}
-pub static APLIC: Once> = Once::new();
-pub fn host_aplic<'a>() -> &'a RwLock {
- APLIC.get().expect("Uninitialized hypervisor aplic!")
-}
-
#[repr(C)]
pub struct Aplic {
pub base: usize,
- pub size: usize,
}
#[allow(dead_code)]
impl Aplic {
- pub fn new(base: usize, size: usize) -> Self {
- Self { base, size }
+ pub fn new(base: usize) -> Self {
+ Self { base }
}
+
+ /// Aplic init
+ pub fn init_global(&self, hart_id: usize, max_interrupts: usize) {
+ // Note: for riscv-aia, hvisor supports msi-mode, but doesn't support direct-mode
+ self.set_domaincfg(false, false, false);
+
+ // Clear all pending and enabled bits
+ for i in 0..((max_interrupts + 31) / 32) {
+ self.set_setip(i, 0);
+ self.set_setie(i, 0);
+ }
+
+ // Sets the default value of target and sourcecfg
+ for i in 1..=max_interrupts {
+ // [1, 1023]
+ // Set irq inactive
+ self.set_sourcecfg(i as u32, SourceMode::Inactive);
+ // Set target to current hart
+ self.set_target_msi(i as u32, hart_id as u32, 0, i as u32);
+ }
+
+ // Set little endian, msi-mode, global irq enabled
+ self.set_domaincfg(false, true, true);
+ }
+
+ /// Set domain configuration
pub fn set_domaincfg(&self, bigendian: bool, msimode: bool, enabled: bool) {
let enabled = u32::from(enabled);
let msimode = u32::from(msimode);
let bigendian = u32::from(bigendian);
let addr = self.base + APLIC_DOMAINCFG_BASE;
- let bigendian = 0;
let src = (enabled << 8) | (msimode << 2) | bigendian;
unsafe {
core::ptr::write_volatile(addr as *mut u32, src);
}
}
+
+ /// Get domain configuration
pub fn get_domaincfg(&self) -> u32 {
let addr = self.base + APLIC_DOMAINCFG_BASE;
unsafe { core::ptr::read_volatile(addr as *const u32) }
}
+
+ /// Get bigendian from domain configuration
+ pub fn get_bigendian(&self) -> bool {
+ let addr = self.base + APLIC_DOMAINCFG_BASE;
+ unsafe { core::ptr::read_volatile(addr as *const u32) & 0b1 != 0 }
+ }
+
+ /// Get MSI_Mode from domain configuration
pub fn get_msimode(&self) -> bool {
let addr = self.base + APLIC_DOMAINCFG_BASE;
- let value = unsafe { core::ptr::read_volatile(addr as *const u32) };
- ((value >> 2) & 0b11) != 0
+ unsafe { core::ptr::read_volatile(addr as *const u32) & 0b100 != 0 }
}
- pub fn set_sourcecfg(&self, irq: u32, mode: SourceModes) {
+
+ /// Set sourcecfg, interrupt source type
+ pub fn set_sourcecfg(&self, irq: u32, mode: SourceMode) {
assert!(irq > 0 && irq < 1024);
let addr = self.base + APLIC_SOURCECFG_BASE + (irq as usize - 1) * 4;
let src = mode as u32;
@@ -152,6 +177,8 @@ impl Aplic {
core::ptr::write_volatile(addr as *mut u32, src);
}
}
+
+ /// Set sourcecfg, delegate
pub fn set_sourcecfg_delegate(&self, irq: u32, child: u32) {
assert!(irq > 0 && irq < 1024);
let addr = self.base + APLIC_SOURCECFG_BASE + (irq as usize - 1) * 4;
@@ -160,324 +187,175 @@ impl Aplic {
core::ptr::write_volatile(addr as *mut u32, src);
}
}
+
+ /// Get sourcecfg
pub fn get_sourcecfg(&self, irq: u32) -> u32 {
assert!(irq > 0 && irq < 1024);
let addr = self.base + APLIC_SOURCECFG_BASE + (irq as usize - 1) * 4;
unsafe { core::ptr::read_volatile(addr as *const u32) }
}
+
+ /// Set msiaddr, smsiaddrcfg & smsiaddrcfgh
pub fn set_msiaddr(&self, address: usize) {
let addr = self.base + APLIC_MSIADDR_BASE;
- let src = (address >> 12) as u32;
+ let src_lo = (address >> 12) as u32;
+ let src_hi = (address >> 44) as u32;
unsafe {
- core::ptr::write_volatile(addr as *mut u32, src);
- core::ptr::write_volatile((addr + 4) as *mut u32, 0);
+ core::ptr::write_volatile(addr as *mut u32, src_lo);
+ core::ptr::write_volatile((addr + 4) as *mut u32, src_hi);
}
}
- pub fn get_ip(&self, irqidx: usize) -> u32 {
- assert!(irqidx < 32);
- let addr = self.base + APLIC_PENDING_BASE + irqidx * 4;
- unsafe { core::ptr::read_volatile(addr as *const u32) }
+
+ /// Get msiaddr, smsiaddrcfg & smsiaddrcfgh
+ pub fn get_msiaddr(&self) -> usize {
+ let addr = self.base + APLIC_MSIADDR_BASE;
+ let src_lo = unsafe { core::ptr::read_volatile(addr as *const u32) } as usize;
+ let src_hi = unsafe { core::ptr::read_volatile((addr + 4) as *const u32) } as usize;
+ (src_hi << 44) | (src_lo << 12)
}
- pub fn get_clrip(&self, irqidx: usize) -> u32 {
+
+ /// Get setip register
+ pub fn get_setip(&self, irqidx: usize) -> u32 {
assert!(irqidx < 32);
- let addr = self.base + APLIC_CLRIP_BASE + irqidx * 4;
+ let addr = self.base + APLIC_SETIP_BASE + irqidx * 4;
unsafe { core::ptr::read_volatile(addr as *const u32) }
}
- pub fn set_ip(&self, irqidx: usize, src: u32, pending: bool) {
+
+ /// Set setip register
+ pub fn set_setip(&self, irqidx: usize, src: u32) {
assert!(irqidx < 32);
- let addr = self.base + APLIC_PENDING_BASE + irqidx * 4;
- let clr_addr = self.base + APLIC_CLRIP_BASE + irqidx * 4;
- if pending {
- unsafe {
- core::ptr::write_volatile(addr as *mut u32, src);
- }
- } else {
- unsafe {
- core::ptr::write_volatile(clr_addr as *mut u32, src);
- }
+ let addr = self.base + APLIC_SETIP_BASE + irqidx * 4;
+ unsafe {
+ core::ptr::write_volatile(addr as *mut u32, src);
}
}
- pub fn set_ipnum(&self, value: u32) {
- let addr = self.base + APLIC_IPNUM_BASE;
+
+ /// Set setipnum register
+ pub fn set_setipnum(&self, value: u32) {
+ assert!(value > 0 && value < 1024);
+ let addr = self.base + APLIC_SETIPNUM_BASE;
unsafe {
core::ptr::write_volatile(addr as *mut u32, value);
}
}
+
+ /// Set setipnum register
+ pub fn set_setipnum_le(&self, value: u32) {
+ assert!(value > 0 && value < 1024);
+ let addr = self.base + APLIC_SETIPNUM_LE_BASE;
+ unsafe {
+ core::ptr::write_volatile(addr as *mut u32, value);
+ }
+ }
+
+ /// Get in_clrip register
pub fn get_in_clrip(&self, irqidx: usize) -> u32 {
assert!(irqidx < 32);
let addr = self.base + APLIC_CLRIP_BASE + irqidx * 4;
unsafe { core::ptr::read_volatile(addr as *const u32) }
}
- pub fn get_ie(&self, irqidx: usize) -> u32 {
+
+ /// Set in_clrip register
+ pub fn set_in_clrip(&self, irqidx: usize, src: u32) {
+ assert!(irqidx < 32);
+ let addr = self.base + APLIC_CLRIP_BASE + irqidx * 4;
+ unsafe {
+ core::ptr::write_volatile(addr as *mut u32, src);
+ }
+ }
+
+ /// Set clripnum register
+ pub fn set_clripnum(&self, value: u32) {
+ assert!(value > 0 && value < 1024);
+ let addr = self.base + APLIC_CLRIPNUM_BASE;
+ unsafe {
+ core::ptr::write_volatile(addr as *mut u32, value);
+ }
+ }
+
+ /// Get setie register
+ pub fn get_setie(&self, irqidx: usize) -> u32 {
assert!(irqidx < 32);
- let addr = self.base + APLIC_ENABLE_BASE + irqidx * 4;
+ let addr = self.base + APLIC_SETIE_BASE + irqidx * 4;
unsafe { core::ptr::read_volatile(addr as *const u32) }
}
+
+ /// Set setie register
+ pub fn set_setie(&self, irqidx: usize, value: u32) {
+ assert!(irqidx < 32);
+ let addr = self.base + APLIC_SETIE_BASE + irqidx * 4;
+ unsafe {
+ core::ptr::write_volatile(addr as *mut u32, value);
+ }
+ }
+
+ /// Set setienum register
+ pub fn set_setienum(&self, value: u32) {
+ assert!(value > 0 && value < 1024);
+ let addr = self.base + APLIC_SETIENUM_BASE;
+ unsafe {
+ core::ptr::write_volatile(addr as *mut u32, value);
+ }
+ }
+
+ /// Get clrie register
pub fn get_clrie(&self, irqidx: usize) -> u32 {
assert!(irqidx < 32);
let addr = self.base + APLIC_CLRIE_BASE + irqidx * 4;
unsafe { core::ptr::read_volatile(addr as *const u32) }
}
- pub fn setie(&self, irqidx: usize, value: u32, enabled: bool) {
+
+ /// Set clrie register
+ pub fn set_clrie(&self, irqidx: usize, value: u32) {
assert!(irqidx < 32);
- let addr = self.base + APLIC_ENABLE_BASE + irqidx * 4;
- let clr_addr = self.base + APLIC_CLRIE_BASE + irqidx * 4;
- if enabled {
- unsafe {
- core::ptr::write_volatile(addr as *mut u32, value);
- }
- } else {
- unsafe {
- core::ptr::write_volatile(clr_addr as *mut u32, value);
- }
- }
- }
- pub fn setienum(&self, value: u32) {
- let addr = self.base + APLIC_ENABLE_NUM;
+ let addr = self.base + APLIC_CLRIE_BASE + irqidx * 4;
unsafe {
core::ptr::write_volatile(addr as *mut u32, value);
}
}
- pub fn clrienum(&self, value: u32) {
- let addr = self.base + APLIC_CLRIE_NUM_BASE;
+
+ /// Set clrienum register
+ pub fn set_clrienum(&self, value: u32) {
+ assert!(value > 0 && value < 1024);
+ let addr = self.base + APLIC_CLRIENUM_BASE;
unsafe {
core::ptr::write_volatile(addr as *mut u32, value);
}
}
+
+ /// Set setipnum_le register
pub fn setipnum_le(&self, value: u32) {
- let addr = self.base + APLIC_IPNUM_LE_BASE;
+ assert!(value > 0 && value < 1024);
+ let addr = self.base + APLIC_SETIPNUM_LE_BASE;
unsafe {
core::ptr::write_volatile(addr as *mut u32, value);
}
}
+
+ /// Set target, msi-mode
pub fn set_target_msi(&self, irq: u32, hart: u32, guest: u32, eiid: u32) {
+ assert!(irq > 0 && irq < 1024);
let addr = self.base + APLIC_TARGET_BASE + (irq as usize - 1) * 4;
- let src = (hart << 18) | (guest << 12) | eiid;
+ let src = ((hart & 0x3FFF) << 18) | ((guest & 0x3F) << 12) | (eiid & 0x3FF);
unsafe {
core::ptr::write_volatile(addr as *mut u32, src);
}
}
+
+ /// Set target, direct-mode
pub fn set_target_direct(&self, irq: u32, hart: u32, prio: u32) {
+ assert!(irq > 0 && irq < 1024);
let addr = self.base + APLIC_TARGET_BASE + (irq as usize - 1) * 4;
- let src = (hart << 18) | (prio & 0xFF);
+ let src = ((hart & 0x3FFF) << 18) | (prio & 0xFF);
unsafe {
core::ptr::write_volatile(addr as *mut u32, src);
}
}
- pub fn get_target_info(&self, irq: u32) -> (u32, u32, u32) {
+
+ /// Get target register
+ pub fn get_target(&self, irq: u32) -> u32 {
+ assert!(irq > 0 && irq < 1024);
let addr = self.base + APLIC_TARGET_BASE + (irq as usize - 1) * 4;
- unsafe {
- let src = core::ptr::read_volatile(addr as *const u32);
- let hart = (src >> 18) & 0x3F;
- let guest = (src >> 12) & 0x3F;
- let eiid = src & 0xFFF;
- (hart, guest, eiid)
- }
- }
-}
-pub fn vaplic_emul_handler(current_cpu: &mut ArchCpu, addr: GuestPhysAddr, inst: Instruction) {
- let host_aplic = host_aplic();
- let offset = addr.wrapping_sub(host_aplic.read().base);
- if offset >= APLIC_DOMAINCFG_BASE && offset < APLIC_SOURCECFG_BASE {
- match inst {
- Instruction::Sw(i) => {
- let value = current_cpu.x[i.rs2() as usize] as u32; // 要写入的 value
- let enabled = ((value >> 8) & 0x1) != 0; // IE
- let msimode = ((value >> 2) & 0b1) != 0; // DM / MSI
- let bigendian = (value & 0b1) != 0; // 大小端
- if this_cpu_data().id != 3 {
- host_aplic
- .write()
- .set_domaincfg(bigendian, msimode, enabled);
- debug!(
- "APLIC set domaincfg write addr@{:#x} bigendian {} msimode {} enabled {}",
- addr, bigendian, msimode, enabled
- );
- }
- }
- Instruction::Lw(i) => {
- let value = host_aplic.read().get_domaincfg();
- current_cpu.x[i.rd() as usize] = value as usize;
- }
- _ => panic!("Unexpected instruction {:?}", inst),
- }
- } else if offset >= APLIC_SOURCECFG_BASE && offset < APLIC_SOURCECFG_TOP {
- //sourcecfg
- match inst {
- Instruction::Sw(i) => {
- let value = current_cpu.x[i.rs2() as usize] as u32;
- let irq = ((offset - APLIC_SOURCECFG_BASE) / 4) + 1;
- if (value >> 10) & 0b1 == 1 {
- //delegate
- let child = value & 0x3ff;
- host_aplic.write().set_sourcecfg_delegate(irq as u32, child);
- debug!(
- "APLIC set sourcecfg_delegate write addr@{:#x} irq {} child {}",
- addr, irq, child
- );
- } else {
- let mode = match value {
- 0 => SourceModes::Inactive,
- 1 => SourceModes::Detached,
- 4 => SourceModes::RisingEdge,
- 5 => SourceModes::FallingEdge,
- 6 => SourceModes::LevelHigh,
- 7 => SourceModes::LevelLow,
- _ => panic!("Unknown sourcecfg mode"),
- };
- if this_cpu_data().id != 3 || this_cpu_data().id == 3 && (irq == 6 || irq == 7)
- {
- host_aplic.write().set_sourcecfg(irq as u32, mode);
- debug!(
- "APLIC set sourcecfg write addr@{:#x} irq {} mode {}",
- addr, irq, value
- );
- }
- }
- }
- _ => panic!("Unexpected instruction {:?}", inst),
- }
- } else if offset >= APLIC_MSIADDR_BASE && offset <= 0x1BCC {
- // msia
- match inst {
- Instruction::Sw(i) => {
- let value = current_cpu.x[i.rs2() as usize] as u32;
- let address = (value as usize) << 12;
- host_aplic.write().set_msiaddr(address);
- debug!(
- "APLIC set msiaddr write addr@{:#x} address {}",
- addr, address
- );
- }
- _ => panic!("Unexpected instruction {:?}", inst),
- }
- } else if offset >= APLIC_PENDING_BASE && offset < APLIC_PENDING_TOP {
- // pending
- panic!("setip Unexpected instruction {:?}", inst);
- }
- // setipnum 区域 0x1CDC - 0x1CE0
- else if offset >= 0x1CDC && offset < 0x1CE0 {
- panic!("setipnum Unexpected instruction {:?}", inst)
- } else if offset >= APLIC_CLRIP_BASE && offset < 0x1D80 {
- // panic!("addr@{:#x} in_clrip Unexpected instruction {:?}", offset ,inst);
- match inst {
- Instruction::Lw(i) => {
- let irqidx = (offset - APLIC_CLRIP_BASE) / 4;
- let value = host_aplic.read().get_in_clrip(irqidx);
- current_cpu.x[i.rd() as usize] = value as usize;
- debug!(
- "APLIC read in clrip addr@{:#x} irqidx {} value {}",
- addr, irqidx, value
- );
- }
- _ => panic!("Unexpected instruction {:?}", inst),
- }
- }
- // clripnum 区域
- else if offset >= 0x1DDC && offset < 0x1DE0 {
- panic!("clripnum Unexpected instruction {:?}", inst)
- }
- // setie
- else if offset >= APLIC_ENABLE_BASE && offset < 0x1E80 {
- panic!("setie Unexpected instruction {:?}", inst);
- } else if offset >= APLIC_ENABLE_NUM && offset < 0x1EE0 {
- // setienum
- match inst {
- Instruction::Sw(i) => {
- let value = current_cpu.x[i.rs2() as usize] as u32;
- host_aplic.write().setienum(value);
- debug!("APLIC setienum write addr@{:#x} value {}", addr, value);
- }
- _ => panic!("Unexpected instruction {:?}", inst),
- }
- } else if offset >= APLIC_CLRIE_BASE && offset < 0x1FDC {
- // clrie
- match inst {
- Instruction::Sw(i) => {
- let value = current_cpu.x[i.rs2() as usize] as u32;
- let irqidx = (offset - APLIC_CLRIE_BASE) / 4;
- if this_cpu_data().id != 3 {
- host_aplic.write().setie(irqidx, value, false);
- }
- debug!(
- "APLIC set clrie write addr@{:#x} irqidx {} value@{:#x}",
- addr, irqidx, value
- );
- }
- _ => panic!("Unexpected instruction {:?}", inst),
- }
- }
- // clrienum
- else if offset >= 0x1FDC && offset < 0x1FE0 {
- match inst {
- Instruction::Sw(i) => {
- let value = current_cpu.x[i.rs2() as usize] as u32;
- host_aplic.write().clrienum(value);
- debug!("APLIC set clrienum write addr@{:#x} value{}", offset, value);
- }
- _ => panic!("Unexpected instruction {:?}", inst),
- }
- }
- // setipnum_le
- else if offset >= 0x2000 && offset < 0x2004 {
- match inst {
- Instruction::Sw(i) => {
- let value = current_cpu.x[i.rs2() as usize] as u32;
- host_aplic.write().setipnum_le(value);
- // debug!("APLIC setipnum le write addr@{:#x} value@{:#x}",offset, value);
- }
- _ => panic!("Unexpected instruction {:?}", inst),
- }
- }
- // setipnum_be
- else if offset >= 0x2004 && offset < 0x2008 {
- panic!("setipnum_be Unexpected instruction {:?}", inst)
- }
- // genmsi
- else if offset >= 0x3000 && offset < 0x3004 {
- panic!("genmsi Unexpected instruction {:?}", inst)
- } else if offset >= APLIC_TARGET_BASE && offset < APLIC_IDC_BASE {
- // target
- match inst {
- Instruction::Sw(i) => {
- let first_cpu = this_cpu_data()
- .zone
- .as_ref()
- .unwrap()
- .read()
- .cpu_set
- .first_cpu()
- .unwrap();
- let value = current_cpu.x[i.rs2() as usize] as u32;
- let irq = ((offset - APLIC_TARGET_BASE) / 4) as u32 + 1;
- let hart = ((value >> 18) & 0x3F) + first_cpu as u32;
- if host_aplic.read().get_msimode() {
- let guest = ((value >> 12) & 0x3F) + 1;
- let eiid = value & 0xFFF;
- if this_cpu_data().id != 3 || this_cpu_data().id == 3 && (irq == 6 || irq == 7)
- {
- host_aplic.write().set_target_msi(irq, hart, guest, eiid);
- debug!(
- "APLIC set msi target write addr@{:#x} irq {} hart {} guest {} eiid {}",
- addr, irq, hart, guest, eiid
- );
- }
- } else {
- let prio = value & 0xFF;
- host_aplic.write().set_target_direct(irq, hart, prio);
- debug!(
- "APLIC set direct target write addr@{:#x} irq {} hart {} prio {}",
- addr, irq, hart, prio
- );
- }
- }
- _ => panic!("Unexpected instruction {:?}", inst),
- }
- } else {
- panic!("Invalid address: {:#x}", addr);
+ unsafe { core::ptr::read_volatile(addr as *const u32) }
}
}
-pub fn init_aplic(aplic_base: usize, aplic_size: usize) {
- let aplic = Aplic::new(aplic_base, aplic_size);
- APLIC.call_once(|| RwLock::new(aplic));
-}
diff --git a/src/device/irqchip/aia/imsic.rs b/src/device/irqchip/aia/imsic.rs
index eb754308..00d250ba 100644
--- a/src/device/irqchip/aia/imsic.rs
+++ b/src/device/irqchip/aia/imsic.rs
@@ -13,58 +13,56 @@
//
// Authors:
//
+use super::vimsic::*;
use crate::arch::csr::{read_csr, write_csr};
-/* AIA Extension */
-pub const CSR_VSISELECT: usize = 0x250;
-pub const CSR_VSIREG: usize = 0x251;
-pub const CSR_VSTOPI: usize = 0xEB0;
-pub const CSR_VSTOPEI: usize = 0x25C;
+use crate::platform::__board::{IMSIC_GUEST_INDEX, IMSIC_NUM_IDS};
-pub const IMSIC_VS: usize = 0x2800_1000;
-const IMSIC_VS_HART_STRIDE: usize = 0x2000;
+pub const CSR_SISELECT: usize = 0x150;
+pub const CSR_SIREG: usize = 0x151;
+pub const CSR_STOPEI: usize = 0x15c;
+// pub const CSR_VSISELECT: usize = 0x250;
+// pub const CSR_VSIREG: usize = 0x251;
+// pub const CSR_VSTOPEI: usize = 0x25C;
-const XLEN: usize = usize::BITS as usize;
-const XLEN_STRIDE: usize = XLEN / 32;
+pub const IMSIC_EIDELIVERY: usize = 0x70;
+pub const IMSIC_EITHRESHOLD: usize = 0x72;
+pub const IMSIC_EIP: usize = 0x80; // 0x80..=0xBF
+pub const IMSIC_EIE: usize = 0xC0; // 0xC0..=0xFF
-const EIP: usize = 0x80;
+/// Init imsic per hart
+pub fn imsic_init() {
+ // Disable interrupt delivery
+ write_csr!(CSR_SISELECT, IMSIC_EIDELIVERY);
+ write_csr!(CSR_SIREG, 0);
-pub const fn imsic_vs(hart: usize) -> usize {
- IMSIC_VS + IMSIC_VS_HART_STRIDE * hart
-}
-fn imsic_write(reg: usize, val: usize) {
- unsafe {
- match reg {
- CSR_VSISELECT => write_csr!(CSR_VSISELECT, val),
- CSR_VSIREG => write_csr!(CSR_VSIREG, val),
- CSR_VSTOPI => write_csr!(CSR_VSTOPI, val),
- CSR_VSTOPEI => write_csr!(CSR_VSTOPEI, val),
- _ => panic!("Unknown CSR {}", reg),
- }
+ // For qemu, num_ids = 0xff
+ let num_ids = (IMSIC_NUM_IDS + 63) / 64;
+
+ // For 64bit system, eip1, eip3.. eip63 don't exist.
+ for i in (0..num_ids) {
+ // Disable all interrupts
+ write_csr!(CSR_SISELECT, IMSIC_EIE + i * 2);
+ write_csr!(CSR_SIREG, 0);
+ // Remove all pending interrupts
+ write_csr!(CSR_SISELECT, IMSIC_EIP + i * 2);
+ write_csr!(CSR_SIREG, 0);
}
-}
-// Read from an IMSIC CSR
+ // Every interrupt is triggerable
+ write_csr!(CSR_SISELECT, IMSIC_EITHRESHOLD);
+ write_csr!(CSR_SIREG, 0);
-fn imsic_read(reg: usize) -> usize {
- let ret: usize;
- unsafe {
- ret = match reg {
- CSR_VSISELECT => read_csr!(CSR_VSISELECT),
- CSR_VSIREG => read_csr!(CSR_VSIREG),
- CSR_VSTOPI => read_csr!(CSR_VSTOPI),
- CSR_VSTOPEI => read_csr!(CSR_VSTOPEI),
- _ => panic!("Unknown CSR {}", reg),
- }
- }
- ret
+ // Enable interrupt delivery
+ write_csr!(CSR_SISELECT, IMSIC_EIDELIVERY);
+ write_csr!(CSR_SIREG, 1);
}
-// VS-Mode IMSIC CSRs
+/// Write to imsic interrupt file.
pub fn imsic_trigger(hart: u32, guest: u32, eiid: u32) {
- // info!("hart: {} guest {} eiid {}", hart, guest, eiid);
- if guest == 1 {
+ if guest as usize == IMSIC_GUEST_INDEX {
+ let addr = imsic_vs_file_addr(hart as usize);
unsafe {
- core::ptr::write_volatile(imsic_vs(hart as usize) as *mut u32, eiid);
+ core::ptr::write_volatile(addr as *mut u32, eiid);
}
} else {
panic!(
diff --git a/src/device/irqchip/aia/mod.rs b/src/device/irqchip/aia/mod.rs
index 1a60944f..fd1b89a4 100644
--- a/src/device/irqchip/aia/mod.rs
+++ b/src/device/irqchip/aia/mod.rs
@@ -13,16 +13,203 @@
//
// Authors:
//
+
+// Note: hvisor's AIA supports MSI-mode, doesn't support Direct-mode.
+
pub mod aplic;
pub mod imsic;
+pub mod vaplic;
+pub mod vimsic;
+use crate::arch::cpu::this_cpu_id;
+use crate::arch::zone::HvArchZoneConfig;
+use crate::config::HvZoneConfig;
+use crate::consts::{MAX_CPU_NUM, MAX_ZONE_NUM};
+use crate::error::HvResult;
+use crate::memory::GuestPhysAddr;
+use crate::memory::HostPhysAddr;
+use crate::memory::MMIOAccess;
+use crate::memory::MemFlags;
+use crate::memory::MemoryRegion;
+use crate::percpu::this_cpu_data;
+use crate::platform::HW_IRQS;
+use crate::platform::{
+ BOARD_APLIC_INTERRUPTS_NUM, IMSIC_GUEST_INDEX, IMSIC_GUEST_NUM, IMSIC_S_BASE,
+};
+use crate::root_zone_config;
use crate::zone::Zone;
+pub use aplic::*;
+use heapless::FnvIndexMap;
+pub use imsic::*;
+use spin::Once;
+pub use vaplic::*;
+pub use vimsic::*;
+
+// Physical APLIC
+pub static APLIC: Once = Once::new();
+// The MAX_ZONE_NUM should be the power of 2.
+static mut VAPLIC_MAP: Option> = None;
+
+pub fn init_aplic(aplic_base: usize) {
+ APLIC.call_once(|| Aplic::new(aplic_base));
+}
+
+pub fn host_aplic<'a>() -> &'a Aplic {
+ APLIC.get().expect("Uninitialized hypervisor aplic!")
+}
+
+pub fn primary_init_early() {
+ // Init the physical APLIC global part
+ let root_config = root_zone_config();
+ init_aplic(root_config.arch_config.aplic_base as usize);
+ host_aplic().init_global(this_cpu_id(), BOARD_APLIC_INTERRUPTS_NUM);
+
+ unsafe {
+ VAPLIC_MAP = Some(FnvIndexMap::new());
+ }
+}
+
+pub fn primary_init_late() {
+ info!("APLIC do nothing in primary_init_late");
+}
+
+pub fn percpu_init() {
+ // Each hart init its own imisc.
+ imsic_init();
+}
+
+/// handle Zone's aplic mmio access.
+pub fn vaplic_handler(mmio: &mut MMIOAccess, _arg: usize) -> HvResult {
+ let value = this_cpu_data()
+ .zone
+ .as_ref()
+ .unwrap()
+ .read()
+ .get_vaplic()
+ .vaplic_emul_access(mmio.address, mmio.size, mmio.value, mmio.is_write);
+ if !mmio.is_write {
+ // read from vplic
+ mmio.value = value as usize;
+ }
+ Ok(())
+}
+
+pub fn inject_irq(irq: usize, is_hardware: bool) {
+ // Due to hvisor doesn't handle external interrupt, inject_irq related interrupt is generated by software.
+ if is_hardware {
+ error!("For hvisor's riscv-aia, hardware interrupt should be transferred to IMSIC's interrupt file.");
+ return;
+ }
+ // For hvisor on qemu-aia, only software interrupt will be injected.
+ // Hardware interrupt will be transferred to IMSIC's interrupt file directly.
+ let target = this_cpu_data()
+ .zone
+ .as_ref()
+ .unwrap()
+ .read()
+ .get_vaplic()
+ .vaplic_get_target(irq);
+ let mut hart = (target >> 18) & 0x3FFF;
+ // let guest = (target >> 12) & 0x3F;
+ let eiid = target & 0x3FF;
+ // Transfer vhart_id to phart_id.
+ hart = hart
+ + this_cpu_data()
+ .zone
+ .as_ref()
+ .unwrap()
+ .read()
+ .cpu_set
+ .first_cpu()
+ .unwrap() as u32;
+ imsic_trigger(hart, IMSIC_GUEST_INDEX as u32, eiid);
+}
+
+/// Print all keys in the VAPLIC_MAP for debugging purposes.
+fn print_keys() {
+ info!("VAPLIC_MAP keys:");
+ unsafe {
+ if let Some(map) = &VAPLIC_MAP {
+ for (&key, _) in map.iter() {
+ info!("\tZone {}'s vaplic in VAPLIC_MAP", key);
+ }
+ }
+ }
+}
impl Zone {
+ /// Initial the virtual APLIC related to thiz Zone.
+ pub fn vaplic_init(&mut self, config: &HvZoneConfig) {
+ // Create a new VirtualAPLIC for this Zone.
+ unsafe {
+ if let Some(map) = &mut VAPLIC_MAP {
+ if map.contains_key(&self.id) {
+ panic!("VirtualAPLIC for Zone {} already exists!", self.id);
+ }
+ let vaplic = vaplic::VirtualAPLIC::new(
+ config.arch_config.aplic_base,
+ BOARD_APLIC_INTERRUPTS_NUM,
+ );
+ // Insert into Map
+ let _ = map.insert(self.id, vaplic);
+ } else {
+ panic!("VAPLIC_MAP is not initialized!");
+ }
+ }
+ info!("VirtualAPLIC for Zone {} initialized successfully", self.id);
+ print_keys();
+ }
+
+ /// Initial the virtual IMSIC related to thiz Zone.
+ pub fn vimsic_init(&mut self, config: &HvZoneConfig) {
+ info!("Zone {} vIMSIC init", self.id);
+ vimsic::vimsic_init(self, IMSIC_S_BASE, IMSIC_GUEST_NUM);
+ }
+
+ pub fn get_vaplic(&self) -> &VirtualAPLIC {
+ unsafe {
+ VAPLIC_MAP
+ .as_ref()
+ .expect("VAPLIC_MAP is not initialized!")
+ .get(&self.id)
+ .expect("VirtualAPLIC for this Zone does not exist!")
+ }
+ }
+
pub fn arch_irqchip_reset(&self) {
- /*
- Reset priority, threshold, enable, and so on related to this zone.
- */
- todo!();
+ // We should make sure only one cpu to do this.
+ // This func will only be called by one root zone's cpu.
+ let host_aplic = host_aplic();
+ let vaplic = self.get_vaplic();
+ for (index, &word) in self.irq_bitmap.iter().enumerate() {
+ for bit_position in 0..32 {
+ if word & (1 << bit_position) != 0 {
+ let irq_id = index * 32 + bit_position;
+ // Skip the irq_id which is not in HW_IRQS
+ if !HW_IRQS.iter().any(|&x| x == irq_id as _) {
+ continue;
+ }
+ info!("Reset irq_id {} in VirtualAPLIC", irq_id);
+ host_aplic.set_clrienum(irq_id as u32);
+ host_aplic.set_sourcecfg(irq_id as u32, SourceMode::Inactive);
+ host_aplic.set_clripnum(irq_id as u32);
+ }
+ }
+ }
+
+ self.cpu_set.iter().for_each(|cpuid| {
+ // Clear the events related to this cpu.
+ info!("Clear events related to cpu {}", cpuid);
+ crate::event::clear_events(cpuid);
+ });
+
+ unsafe {
+ if let Some(map) = &mut VAPLIC_MAP {
+ map.remove(&self.id);
+ } else {
+ panic!("VAPLIC_MAP is not initialized!");
+ }
+ }
+ print_keys();
}
fn insert_irq_to_bitmap(&mut self, irq: u32) {
@@ -37,6 +224,10 @@ impl Zone {
for irq in irqs {
let irq_id = *irq;
// They are hardware interrupts.
+ if HW_IRQS.iter().any(|&x| x == irq_id) {
+ self.get_vaplic().vaplic_set_hw(irq_id as usize, true);
+ info!("Set irq {} to hardware interrupt", irq_id);
+ }
self.insert_irq_to_bitmap(irq_id);
}
// print irq_bitmap
@@ -52,4 +243,11 @@ impl Zone {
}
}
}
+
+ pub fn vaplic_mmio_init(&mut self, arch: &HvArchZoneConfig) {
+ if arch.aplic_base == 0 {
+ panic!("vplic_mmio_init: plic_base is null");
+ }
+ self.mmio_region_register(arch.aplic_base, arch.aplic_size, vaplic_handler, 0);
+ }
}
diff --git a/src/device/irqchip/aia/vaplic.rs b/src/device/irqchip/aia/vaplic.rs
new file mode 100644
index 00000000..fdd50405
--- /dev/null
+++ b/src/device/irqchip/aia/vaplic.rs
@@ -0,0 +1,415 @@
+// Copyright (c) 2025 Syswonder
+// hvisor is licensed under Mulan PSL v2.
+// You can use this software according to the terms and conditions of the Mulan PSL v2.
+// You may obtain a copy of Mulan PSL v2 at:
+// http://license.coscl.org.cn/MulanPSL2
+// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+// FIT FOR A PARTICULAR PURPOSE.
+// See the Mulan PSL v2 for more details.
+//
+// Syswonder Website:
+// https://www.syswonder.org
+//
+// Authors: Jingyu Liu
+//
+
+use super::*;
+use crate::percpu::this_cpu_data;
+use alloc::sync::Arc;
+use alloc::vec::Vec;
+use bitvec::prelude::*;
+use spin::Mutex;
+
+// Note: one hart execute one VM!
+pub const GUEST_INDEX: usize = 1; // MSI-mode: forward irq to VS
+
+/// Virtual Advanced Platform-Level Interrupt Controller (vAPLIC)
+#[allow(unused)]
+pub struct VirtualAPLIC {
+ /// Base address of the vAPLIC in guest physical memory
+ base_addr: usize,
+ /// Maximum number of interrupts
+ max_interrupts: usize,
+ /// Inner state of the vAPLIC (thread-safe)
+ inner: Arc>,
+}
+
+/// Inner state of the vAPLIC, only supports MSI-mode
+struct VirtualAPLICInner {
+ /// Hardware interrupt bitmap
+ hw: BitVec,
+ /// Active interrupt bitmap
+ active: BitVec,
+ /// Pending interrupt bitmap
+ pending: BitVec,
+ /// Interrupt enable bitmap
+ enable: BitVec,
+ /// Domain configuration
+ domaincfg: u32,
+ /// Source configuration for each interrupt
+ srccfg: Vec,
+ /// Interrupt targets
+ target: Vec,
+}
+
+impl VirtualAPLIC {
+ /// Create a new vAPLIC instance
+ pub fn new(base_addr: usize, max_interrupts: usize) -> Self {
+ VirtualAPLIC {
+ base_addr,
+ max_interrupts,
+ inner: Arc::new(Mutex::new(VirtualAPLICInner {
+ hw: bitvec![0; max_interrupts + 1],
+ active: bitvec![0; max_interrupts + 1],
+ pending: bitvec![0; max_interrupts + 1],
+ enable: bitvec![0; max_interrupts + 1],
+ domaincfg: 0,
+ srccfg: vec![0; max_interrupts + 1],
+ target: vec![0; max_interrupts + 1],
+ })),
+ }
+ }
+
+ /// Set one interrupt as hardware interrupt.
+ pub fn vaplic_set_hw(&self, intr_id: usize, hw: bool) {
+ let mut inner = self.inner.lock();
+ inner.vaplic_set_hw(intr_id, hw);
+ }
+
+ /// Get one interrupt as hardware interrupt.
+ pub fn vaplic_get_hw(&self, intr_id: usize) -> bool {
+ let inner = self.inner.lock();
+ inner.vaplic_get_hw(intr_id)
+ }
+
+ /// Get one interrupt as hardware interrupt.
+ pub fn vaplic_get_target(&self, intr_id: usize) -> u32 {
+ let inner = self.inner.lock();
+ inner.vaplic_get_target(intr_id)
+ }
+
+ /// vAPLIC emul access.
+ pub fn vaplic_emul_access(
+ &self,
+ offset: usize,
+ size: usize,
+ value: usize,
+ is_write: bool,
+ ) -> u32 {
+ if size != 4 || offset & 0x3 != 0 {
+ panic!("vaplic_emul_access: only allowed word accesses");
+ return 0;
+ }
+
+ match offset {
+ // Domain configuration
+ 0x0000 => {
+ let mut inner = self.inner.lock();
+ if is_write {
+ // Write domain config
+ let msi_mode = (value as u32 & 0b100 != 0);
+ // let phys_msi_mode = host_aplic().get_msimode();
+ // if (msi_mode != phys_msi_mode) {
+ // error!(
+ // "vAPLIC msi_mode {} is different from host APLIC msi_mode {}",
+ // msi_mode, phys_msi_mode
+ // );
+ // return 0;
+ // }
+ let bigendian = (value as u32 & 0b1 != 0);
+ // let phys_bigendian = host_aplic().get_bigendian();
+ // if (bigendian != phys_bigendian) {
+ // error!(
+ // "vAPLIC bigendian {} is different from host APLIC bigendian {}",
+ // bigendian, phys_bigendian
+ // );
+ // return 0;
+ // }
+ info!(
+ "Set vAPLIC domaincfg to {:#x}, msi_mode {}, bigendian {}",
+ value, msi_mode, bigendian
+ );
+ let new_value = value & 0b1_0000_0101; // 3bits: IE, MSI-mode, Bigendian
+ inner.vaplic_set_domaincfg(new_value as u32);
+ } else {
+ // Read domain config
+ return inner.vaplic_get_domaincfg() as _;
+ }
+ }
+ // Source configuration
+ 0x0004..=0x0FFC => {
+ let irq_id = (offset - 0x0004) / 4 + 1; // Begin from irq_id 1.
+ let mut inner = self.inner.lock();
+ if is_write {
+ if ((value >> 10) & 0x1 == 0x1) {
+ error!("vAPLIC sourcecfg delegate isn't supported!");
+ return 0;
+ } else {
+ let mode = match value {
+ 0 => SourceMode::Inactive,
+ 1 => SourceMode::Detached,
+ 4 => SourceMode::RisingEdge,
+ 5 => SourceMode::FallingEdge,
+ 6 => SourceMode::LevelHigh,
+ 7 => SourceMode::LevelLow,
+ _ => {
+ error!("Unknown sourcecfg mode");
+ return 0;
+ }
+ };
+ if inner.hw[irq_id] {
+ host_aplic().set_sourcecfg(irq_id as u32, mode);
+ inner.vaplic_set_sourcecfg(irq_id, value as u32);
+ } else {
+ // if mode != SourceMode::Inactive {
+ // error!(
+ // "Want to set sourcecfg active for IRQ {} with no hw flag.",
+ // irq_id
+ // );
+ // return 0;
+ // }
+ inner.vaplic_set_sourcecfg(irq_id, value as u32);
+ }
+ }
+ } else {
+ info!("Read vAPLIC sourcecfg for IRQ {}", irq_id);
+ return inner.vaplic_get_sourcecfg((offset - 0x0004) / 4) as _;
+ }
+ }
+ // msiaddrcfg
+ 0x1BC8..=0x1BCC => {
+ if is_write {
+ let host_msiaddr = host_aplic().get_msiaddr();
+ if host_msiaddr != value {
+ error!(
+ "vAPLIC msiaddrcfg {:x} is different from host APLIC msiaddrcfg {:x}",
+ value, host_msiaddr
+ );
+ return 0;
+ }
+ } else {
+ error!("Want to read APLIC msiaddrcfg");
+ }
+ }
+ // Setip
+ 0x1C00..=0x1C7C => {
+ error!("Want to read/write APLIC setip, not supported yet.");
+ }
+ // Setipnum
+ 0x1CDC => {
+ error!("Want to read/write APLIC setipnum, not supported yet.");
+ }
+ // In_clrip
+ 0x1D00..=0x1D7C => {
+ error!("Want to read/write APLIC in clrip, not supported yet.");
+ }
+ // Clripnum
+ 0x1DDC => {
+ error!("Want to read/write APLIC clripnum, not supported yet.");
+ }
+ // Setie
+ 0x1E00..=0x1E7C => {
+ error!("Want to read/write APLIC setie, not supported yet.");
+ }
+ // Setienum
+ 0x1EDC => {
+ let irq_id = value as u32;
+ let mut inner = self.inner.lock();
+ if is_write {
+ if inner.hw[irq_id as usize] {
+ host_aplic().set_setienum(irq_id);
+ debug!("vAPLIC setienum for IRQ {} --> host APLIC", irq_id);
+ inner.vaplic_set_enable(irq_id as usize, true);
+ } else {
+ inner.vaplic_set_enable(irq_id as usize, true);
+ }
+ } else {
+ warn!("Want to read APLIC setienum.");
+ }
+ }
+ // Clrie
+ 0x1F00..=0x1F7C => {
+ let irq_idx = (offset - 0x1F00) / 4;
+ let mut inner = self.inner.lock();
+ if is_write {
+ for irq_id in irq_idx * 32..(irq_idx + 1) * 32 {
+ if irq_id > self.max_interrupts {
+ break;
+ }
+ if (value & (1 << (irq_id - irq_idx * 32))) != 0 {
+ if inner.hw[irq_id] {
+ host_aplic().set_clrienum(irq_id as u32);
+ debug!("vAPLIC clrienum for IRQ {} --> host APLIC", irq_id);
+ inner.vaplic_set_enable(irq_id, false);
+ } else {
+ inner.vaplic_set_enable(irq_id, false);
+ }
+ }
+ }
+ } else {
+ error!("Want to read APLIC clrie, not supported yet.");
+ }
+ }
+ // Clrienum
+ 0x1FDC => {
+ let irq_id = value as u32;
+ let mut inner = self.inner.lock();
+ if is_write {
+ if inner.hw[irq_id as usize] {
+ host_aplic().set_clrienum(irq_id);
+ debug!("vAPLIC clrienum for IRQ {} --> host APLIC", irq_id);
+ inner.vaplic_set_enable(irq_id as usize, false);
+ } else {
+ inner.vaplic_set_enable(irq_id as usize, false);
+ }
+ } else {
+ warn!("Want to read APLIC clrienum.");
+ }
+ }
+ // Setipnum_le
+ 0x2000 => {
+ let irq_id = value as u32;
+ let mut inner = self.inner.lock();
+ if is_write {
+ if inner.hw[irq_id as usize] {
+ host_aplic().set_setipnum_le(irq_id);
+ inner.vaplic_set_pending(irq_id as usize, true);
+ } else {
+ inner.vaplic_set_pending(irq_id as usize, true);
+ }
+ } else {
+ warn!("Want to read APLIC setipnum_le.");
+ }
+ }
+ // Setipnum_be
+ 0x2004 => {
+ error!("Want to read/write APLIC setipnum_be, not supported yet.");
+ }
+ // Genmsi
+ 0x3000 => {
+ error!("Want to read/write APLIC genmsi, not supported yet.");
+ }
+ // Target configuration
+ 0x3004..=0x3FFC => {
+ let irq_id = (offset - 0x3004) / 4 + 1;
+ let mut inner = self.inner.lock();
+ if is_write {
+ let hart_id = (value >> 18) & 0x3fff;
+ let phys_hart_id = hart_id
+ + this_cpu_data()
+ .zone
+ .as_ref()
+ .unwrap()
+ .read()
+ .cpu_set
+ .first_cpu()
+ .unwrap();
+ let guest_id = (value >> 12) & 0x3f;
+ let eiid = value & 0x7ff;
+ if inner.hw[irq_id] {
+ if !host_aplic().get_msimode() {
+ error!("hvisor's vAPLIC only supports MSI-mode");
+ return 0;
+ }
+ host_aplic().set_target_msi(
+ irq_id as u32,
+ phys_hart_id as u32,
+ GUEST_INDEX as u32,
+ eiid as u32,
+ );
+ info!(
+ "vAPLIC set target for IRQ {} to guest {}, hart {}, eiid {} -> host APLIC Guest {}",
+ irq_id, guest_id, hart_id, eiid, GUEST_INDEX
+ );
+ inner.vaplic_set_target(irq_id, value as u32);
+ } else {
+ debug!("Want to set target with no hw flag, irq: {}", irq_id);
+ inner.vaplic_set_target(irq_id, value as u32);
+ }
+ } else {
+ info!("Read vAPLIC target for IRQ {}", irq_id);
+ return inner.vaplic_get_target(irq_id) as _;
+ }
+ }
+ _ => panic!(
+ "Invalid vAPLIC access at offset: {:#x}, size: {:#x}",
+ offset, size
+ ),
+ }
+ return 0;
+ }
+}
+
+#[allow(unused)]
+impl VirtualAPLICInner {
+ /// vAPLIC get hardware interrupt.
+ fn vaplic_get_hw(&self, intr_id: usize) -> bool {
+ self.hw[intr_id]
+ }
+
+ /// vAPLIC set hardware interrupt.
+ fn vaplic_set_hw(&mut self, intr_id: usize, hw: bool) {
+ self.hw.set(intr_id, hw);
+ }
+
+ /// vAPLIC get active interrupt.
+ fn vaplic_get_active(&self, intr_id: usize) -> bool {
+ self.active[intr_id]
+ }
+
+ /// vAPLIC set active interrupt.
+ fn vaplic_set_active(&mut self, intr_id: usize, active: bool) {
+ self.active.set(intr_id, active);
+ }
+
+ /// vAPLIC get interrupt pending bit.
+ fn vaplic_get_pending(&self, intr_id: usize) -> bool {
+ self.pending[intr_id]
+ }
+
+ /// vAPLIC set interrupt pending bit.
+ fn vaplic_set_pending(&mut self, intr_id: usize, pend: bool) {
+ self.pending.set(intr_id, pend);
+ }
+
+ /// vAPLIC get enable bit.
+ fn vaplic_get_enable(&self, intr_id: usize) -> bool {
+ self.enable[intr_id]
+ }
+
+ /// vAPLIC set enable bit.
+ fn vaplic_set_enable(&mut self, intr_id: usize, enable: bool) {
+ self.enable.set(intr_id, enable);
+ }
+
+ /// vAPLIC get domain configuration.
+ fn vaplic_get_domaincfg(&self) -> u32 {
+ self.domaincfg
+ }
+
+ /// vAPLIC set domain configuration.
+ fn vaplic_set_domaincfg(&mut self, domaincfg: u32) {
+ self.domaincfg = domaincfg;
+ }
+
+ /// vAPLIC get source configuration.
+ fn vaplic_get_sourcecfg(&self, intr_id: usize) -> u32 {
+ self.srccfg[intr_id]
+ }
+
+ /// vAPLIC set source configuration.
+ fn vaplic_set_sourcecfg(&mut self, intr_id: usize, srccfg: u32) {
+ self.srccfg[intr_id] = srccfg;
+ }
+
+ /// vAPLIC get target.
+ fn vaplic_get_target(&self, intr_id: usize) -> u32 {
+ self.target[intr_id]
+ }
+
+ /// vAPLIC set target.
+ fn vaplic_set_target(&mut self, intr_id: usize, target: u32) {
+ self.target[intr_id] = target;
+ }
+}
diff --git a/src/device/irqchip/aia/vimsic.rs b/src/device/irqchip/aia/vimsic.rs
new file mode 100644
index 00000000..0e065f4a
--- /dev/null
+++ b/src/device/irqchip/aia/vimsic.rs
@@ -0,0 +1,58 @@
+// Copyright (c) 2025 Syswonder
+// hvisor is licensed under Mulan PSL v2.
+// You can use this software according to the terms and conditions of the Mulan PSL v2.
+// You may obtain a copy of Mulan PSL v2 at:
+// http://license.coscl.org.cn/MulanPSL2
+// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+// FIT FOR A PARTICULAR PURPOSE.
+// See the Mulan PSL v2 for more details.
+//
+// Syswonder Website:
+// https://www.syswonder.org
+//
+// Authors: Jingyu Liu
+//
+
+use crate::consts::PAGE_SIZE;
+use crate::memory::GuestPhysAddr;
+use crate::memory::HostPhysAddr;
+use crate::memory::MemFlags;
+use crate::memory::MemoryRegion;
+use crate::platform::__board::{IMSIC_GUEST_INDEX, IMSIC_GUEST_NUM, IMSIC_S_BASE};
+use crate::zone::Zone;
+
+/**
+ * For imsic's guest_num = 1
+ * its interrupt files:
+ * S-file CPU0 base + 0x0000
+ * VS-file CPU0 base + 0x1000
+ * S-file CPU1 base + 0x2000
+ * VS-file CPU1 base + 0x3000
+ * ...
+ */
+
+pub fn vimsic_init(zone: &mut Zone, imsic_base: usize, guest_num: usize) {
+ let paddr = imsic_base as HostPhysAddr;
+ let size = crate::memory::PAGE_SIZE;
+ zone.cpu_set.iter().for_each(|cpu_id| {
+ let vcpu_id = cpu_id; // In hvisor, vcpu_id == cpu_id.
+ let imsic_hpa = imsic_base + PAGE_SIZE * ((1 + guest_num) * cpu_id + IMSIC_GUEST_INDEX);
+ // For VM, it couldn't see VS-files.
+ let imsic_gpa = imsic_base + PAGE_SIZE * vcpu_id; // In hvisor, vcpu_id == cpu_id.
+ info!(
+ "Zone {} vIMSIC map hart {} imsic hpa {:#x} gpa {:#x}",
+ zone.id, cpu_id, imsic_hpa, imsic_gpa
+ );
+ zone.gpm.insert(MemoryRegion::new_with_offset_mapper(
+ imsic_gpa as GuestPhysAddr,
+ imsic_hpa,
+ size,
+ MemFlags::READ | MemFlags::WRITE,
+ ));
+ });
+}
+
+pub fn imsic_vs_file_addr(hart_id: usize) -> usize {
+ IMSIC_S_BASE + PAGE_SIZE * ((1 + IMSIC_GUEST_NUM) * hart_id + IMSIC_GUEST_INDEX)
+}
diff --git a/src/device/irqchip/gicv2/gic.rs b/src/device/irqchip/gicv2/gic.rs
index 50356341..9322b582 100644
--- a/src/device/irqchip/gicv2/gic.rs
+++ b/src/device/irqchip/gicv2/gic.rs
@@ -12,9 +12,8 @@
// https://www.syswonder.org
//
// Authors:
-//
+// Hangqi Ren <2572131118@qq.com>
use crate::arch::cpu::this_cpu_id;
-use crate::consts;
use crate::device::irqchip::gicv2::gicc::GICC;
use crate::device::irqchip::gicv2::gicd::GICV2_SGIS_NUM;
use crate::device::irqchip::gicv2::gich::{
@@ -31,7 +30,8 @@ use alloc::collections::VecDeque;
use alloc::vec::Vec;
use spin::{Mutex, Once};
-pub const MAX_CPU_NUM: usize = consts::MAX_CPU_NUM;
+// gicv2 support max 8 cpus
+pub(crate) const MAX_CPU_NUM: usize = 8;
pub const MAINTENACE_INTERRUPT: u64 = 25;
pub fn gicv2_handle_irq() {
@@ -57,7 +57,7 @@ pub fn gicv2_handle_irq() {
}
pub fn get_pending_irq() -> Option {
- let iar = GICC.get_iar() as usize;
+ let iar = GICC.get().unwrap().get_iar() as usize;
let irq = iar & 0x3ff;
if irq >= 1023 {
None
@@ -68,22 +68,22 @@ pub fn get_pending_irq() -> Option {
// deactivate irq: GIC doesn't care CPU ID.
pub fn deactivate_irq(irq_id: usize) {
- GICC.set_eoir(irq_id as u32);
+ GICC.get().unwrap().set_eoir(irq_id as u32);
if irq_id < GICV2_SGIS_NUM {
- GICC.set_dir(irq_id as u32);
+ GICC.get().unwrap().set_dir(irq_id as u32);
}
}
pub fn change_underflow_maintenance(is_enable: bool) {
trace!("enable_maintenace_interrupt, is_enable is {}", is_enable);
- let mut hcr = GICH.get_hcr();
+ let mut hcr = GICH.get().unwrap().get_hcr();
trace!("hcr is {}", hcr);
if is_enable {
hcr |= GICV2_GICH_HCR_UIE;
} else {
hcr &= !GICV2_GICH_HCR_UIE;
}
- GICH.set_hcr(hcr);
+ GICH.get().unwrap().set_hcr(hcr);
}
fn handle_maintenace_interrupt() {
@@ -103,8 +103,9 @@ fn handle_maintenace_interrupt() {
}
pub fn inject_irq(irq_id: usize, is_sgi: bool) -> bool {
- let elrsr: u64 = (GICH.get_elrsr(1) as u64) << 32 | GICH.get_elrsr(0) as u64;
- let lr_num: isize = GICH.get_lr_num() as isize;
+ let elrsr: u64 =
+ (GICH.get().unwrap().get_elrsr(1) as u64) << 32 | GICH.get().unwrap().get_elrsr(0) as u64;
+ let lr_num: isize = GICH.get().unwrap().get_lr_num() as isize;
let lr_pint_mask: usize = 0x3ff << 10;
let mut free_lr: isize = -1;
for i in 0..lr_num {
@@ -112,7 +113,7 @@ pub fn inject_irq(irq_id: usize, is_sgi: bool) -> bool {
free_lr = i;
continue;
}
- let lr = GICH.get_lr(i as usize) as usize;
+ let lr = GICH.get().unwrap().get_lr(i as usize) as usize;
let pint = (lr & lr_pint_mask) >> 10;
if pint == irq_id {
trace!("virtual irq {} enables again", irq_id);
@@ -122,7 +123,7 @@ pub fn inject_irq(irq_id: usize, is_sgi: bool) -> bool {
if free_lr == -1 {
warn!("no free lr");
for i in 0..lr_num {
- let lr = GICH.get_lr(i as usize) as usize;
+ let lr = GICH.get().unwrap().get_lr(i as usize) as usize;
warn!("lr[{}]: {:#x}", i, lr);
}
PENDING_VIRQS
@@ -147,7 +148,7 @@ pub fn inject_irq(irq_id: usize, is_sgi: bool) -> bool {
// config hw bit 31
val = val | GICV2_GICH_LR_HW;
}
- GICH.set_lr(free_lr as usize, val as u32);
+ GICH.get().unwrap().set_lr(free_lr as usize, val as u32);
true
}
}
diff --git a/src/device/irqchip/gicv2/gic_ref.rs b/src/device/irqchip/gicv2/gic_ref.rs
index b86f2f92..833d7e48 100644
--- a/src/device/irqchip/gicv2/gic_ref.rs
+++ b/src/device/irqchip/gicv2/gic_ref.rs
@@ -12,12 +12,8 @@
// https://www.syswonder.org
//
// Authors:
-//
+// Hangqi Ren <2572131118@qq.com>
use core::marker::PhantomData;
-/// A struct definition that wraps around a bare pointer
-/// author: ForeverYolo
-/// references:
-/// rust_shyper: https://gitee.com/openeuler/rust_shyper
use core::ops::Deref;
use core::ptr::NonNull;
diff --git a/src/device/irqchip/gicv2/gicc.rs b/src/device/irqchip/gicv2/gicc.rs
index 41a9f0c7..a5f14df3 100644
--- a/src/device/irqchip/gicv2/gicc.rs
+++ b/src/device/irqchip/gicv2/gicc.rs
@@ -12,9 +12,10 @@
// https://www.syswonder.org
//
// Authors:
-//
+// Hangqi Ren <2572131118@qq.com>
#![allow(unused_variables)]
#![allow(dead_code)]
+
use crate::device::irqchip::gicv2::gic_ref::GicRef;
use crate::device::irqchip::gicv2::gicd::GICD;
use crate::device::irqchip::gicv2::gich::{
@@ -22,6 +23,7 @@ use crate::device::irqchip::gicv2::gich::{
GICV2_GICH_VMCR_VMGRP0EN,
};
use crate::device::irqchip::gicv2::GICV2;
+use spin::Once;
/// gicc layout definition and functions for gicc operations.
/// author : ForeverYolo
/// reference:
@@ -83,14 +85,19 @@ register_structs! {
unsafe impl Sync for GicCpuInterface {}
// Each CPU holds one GICC.
-pub static GICC: GicRef =
- unsafe { GicRef::new(GICV2.gicc_base as *const GicCpuInterface) };
+pub static GICC: Once> = Once::new();
+
+pub fn gicc_init(gicc_base: usize) {
+ unsafe {
+ GICC.call_once(|| GicRef::new(gicc_base as *const GicCpuInterface));
+ }
+}
impl GicCpuInterface {
// init GICC for each CPU.
pub fn init(&self) {
// Ensure all SGIs disabled.
- GICD.set_icenabler(0, 0x0000FFFF);
+ GICD.get().unwrap().set_icenabler(0, 0x0000FFFF);
// get ctrl and pmr value
let gicc_ctrl = self.CTLR.get();
let gicc_pmr = self.PMR.get();
@@ -108,18 +115,18 @@ impl GicCpuInterface {
if gicc_ctrl & GICV2_GICC_CTRL_EOIMODES != 0 {
vmcr |= GICV2_GICH_VMCR_VEM;
}
- GICH.set_vmcr(vmcr);
+ GICH.get().unwrap().set_vmcr(vmcr);
// Enable virtual CPU interface operation.
- GICH.set_hcr(GICV2_GICH_HCR_EN);
+ GICH.get().unwrap().set_hcr(GICV2_GICH_HCR_EN);
// Clear all lr registers in GICH.
- GICH.clear_all_lr();
+ GICH.get().unwrap().clear_all_lr();
// Deactivate all active and pending SGIS
- let gicd_isactive = GICD.get_isactiver(0);
- let gicd_ispend = GICD.get_spendsgir(0);
- GICD.set_icactiver(0, gicd_isactive & 0xffff);
- GICD.set_cpendsgir(0, gicd_ispend & 0xffff);
+ let gicd_isactive = GICD.get().unwrap().get_isactiver(0);
+ let gicd_ispend = GICD.get().unwrap().get_spendsgir(0);
+ GICD.get().unwrap().set_icactiver(0, gicd_isactive & 0xffff);
+ GICD.get().unwrap().set_cpendsgir(0, gicd_ispend & 0xffff);
// re-enable all SGIs
- GICD.set_isenabler(0, 0x0000FFFF);
+ GICD.get().unwrap().set_isenabler(0, 0x0000FFFF);
info!("GICV2: GICC init done.");
}
diff --git a/src/device/irqchip/gicv2/gicd.rs b/src/device/irqchip/gicv2/gicd.rs
index bc8fab22..dd9f3283 100644
--- a/src/device/irqchip/gicv2/gicd.rs
+++ b/src/device/irqchip/gicv2/gicd.rs
@@ -12,7 +12,7 @@
// https://www.syswonder.org
//
// Authors:
-//
+// Hangqi Ren <2572131118@qq.com>
#![allow(unused_variables)]
#![allow(dead_code)]
use crate::device::irqchip::gicv2::gic_ref::GicRef;
@@ -21,7 +21,7 @@ use crate::device::irqchip::gicv2::GICV2;
/// author : ForeverYolo
/// reference:
/// 1. gicv2 spec : https://www.cl.cam.ac.uk/research/srg/han/ACS-P35/zynq/arm_gic_architecture_specification.pdf
-use spin::Mutex;
+use spin::{Mutex, Once};
use tock_registers::interfaces::{Readable, Writeable};
use tock_registers::register_structs;
use tock_registers::registers::{ReadOnly, ReadWrite};
@@ -100,10 +100,13 @@ register_structs! {
unsafe impl Sync for GicDistributer {}
// GICD is globally unique.
-pub static GICD: GicRef =
- unsafe { GicRef::new(GICV2.gicd_base as *const GicDistributer) };
+pub static GICD: Once> = Once::new();
pub static GICD_LOCK: Mutex<()> = Mutex::new(());
+pub fn gicd_init(gicd_base: usize) {
+ GICD.call_once(|| unsafe { GicRef::new(gicd_base as *const GicDistributer) });
+}
+
impl GicDistributer {
// init GICD globally and enable it.
pub fn global_init(&self) {
@@ -187,7 +190,7 @@ impl GicDistributer {
// Get the maximum number of interrupt IDs that the GIC supports.
pub fn get_max_int_num() -> usize {
- let value = (GICD.TYPER.get() & 0b11111) as usize;
+ let value = (GICD.get().unwrap().TYPER.get() & 0b11111) as usize;
(value + 1) * 32
}
@@ -198,9 +201,9 @@ pub fn is_spi(irqn: usize) -> bool {
// Get the base address of GICD.
pub fn host_gicd_base() -> usize {
- GICV2.gicd_base
+ GICV2.get().unwrap().gicd_base
}
pub fn set_ispender(index: usize, value: u32) {
- GICD.set_ispender(index, value);
+ GICD.get().unwrap().set_ispender(index, value);
}
diff --git a/src/device/irqchip/gicv2/gich.rs b/src/device/irqchip/gicv2/gich.rs
index e1dc2bae..982ff7ad 100644
--- a/src/device/irqchip/gicv2/gich.rs
+++ b/src/device/irqchip/gicv2/gich.rs
@@ -12,11 +12,12 @@
// https://www.syswonder.org
//
// Authors:
-//
+// Hangqi Ren <2572131118@qq.com>
#![allow(unused_variables)]
#![allow(dead_code)]
use crate::device::irqchip::gicv2::gic_ref::GicRef;
use crate::device::irqchip::gicv2::GICV2;
+use spin::Once;
/// gich layout definition and functions for gich operations.
/// author : ForeverYolo
use tock_registers::interfaces::{Readable, Writeable};
@@ -67,8 +68,13 @@ register_structs! {
}
unsafe impl Sync for GicHypervisorInterface {}
// Each CPU holds one GICH.
-pub static GICH: GicRef =
- unsafe { GicRef::new(GICV2.gich_base as *const GicHypervisorInterface) };
+pub static GICH: Once> = Once::new();
+
+pub fn gich_init(gich_base: usize) {
+ unsafe {
+ GICH.call_once(|| GicRef::new(gich_base as *const GicHypervisorInterface));
+ }
+}
impl GicHypervisorInterface {
// init GICH for each CPU.
diff --git a/src/device/irqchip/gicv2/gicv.rs b/src/device/irqchip/gicv2/gicv.rs
index 6f408f5e..c523dc62 100644
--- a/src/device/irqchip/gicv2/gicv.rs
+++ b/src/device/irqchip/gicv2/gicv.rs
@@ -12,18 +12,22 @@
// https://www.syswonder.org
//
// Authors:
-//
+// Hangqi Ren <2572131118@qq.com>
#![allow(unused_variables)]
#![allow(dead_code)]
/// gicv layout definition and functions for gicv operations.
-/// author : ForeverYolo
/// reference:
/// 1. gicv2 spec : https://www.cl.cam.ac.uk/research/srg/han/ACS-P35/zynq/arm_gic_architecture_specification.pdf
/// note: We don't actually use it. This is to ensure the integrity of GICV2.
use crate::device::irqchip::gicv2::gic_ref::GicRef;
use crate::device::irqchip::gicv2::gicc::GicCpuInterface;
use crate::device::irqchip::gicv2::GICV2;
-
+use spin::Once;
// Each CPU holds one GICV, and it has the same register layout as GICC.
-pub static GICV: GicRef =
- unsafe { GicRef::new(GICV2.gicv_base as *const GicCpuInterface) };
+pub static GICV: Once> = Once::new();
+
+pub fn gicv_init(gicv_base: usize) {
+ unsafe {
+ GICV.call_once(|| GicRef::new(gicv_base as *const GicCpuInterface));
+ }
+}
diff --git a/src/device/irqchip/gicv2/mod.rs b/src/device/irqchip/gicv2/mod.rs
index ea1760f8..b50f1e6a 100644
--- a/src/device/irqchip/gicv2/mod.rs
+++ b/src/device/irqchip/gicv2/mod.rs
@@ -12,16 +12,22 @@
// https://www.syswonder.org
//
// Authors:
-//
+// Hangqi Ren <2572131118@qq.com>
+use crate::arch::zone::{GicConfig, Gicv2Config, HvArchZoneConfig};
use crate::device::irqchip::gicv2::gic::MAX_CPU_NUM;
+use crate::device::irqchip::gicv2::gicc::gicc_init;
/// The outer layer is defined using gicv2.
/// author: ForeverYolo
/// reference:
/// 1. gicv2 spec : https://www.cl.cam.ac.uk/research/srg/han/ACS-P35/zynq/arm_gic_architecture_specification.pdf
use crate::device::irqchip::gicv2::gicc::GICC;
+use crate::device::irqchip::gicv2::gicd::gicd_init;
use crate::device::irqchip::gicv2::gicd::GICD;
+use crate::device::irqchip::gicv2::gich::gich_init;
+use crate::device::irqchip::gicv2::gicv::gicv_init;
use crate::platform::ROOT_ARCH_ZONE_CONFIG;
use crate::zone::Zone;
+use spin::Once;
// GIC Distributor Definition.
pub mod gicd;
@@ -51,35 +57,66 @@ pub struct Gicv2 {
gicv_base: usize,
}
-pub static GICV2: Gicv2 = Gicv2 {
- gicd_base: ROOT_ARCH_ZONE_CONFIG.gicd_base,
- /*
- * Some boards have the GIC CPU interface registers alias, which will overlap DIR register, so we need to add an offset to
- * find the last gic cpu alias region.
- * ref: https://github.com/Xilinx/qemu-devicetrees/commit/09d4c3200538dc90082fbda9289e2af9794b9a28
- */
- gicc_base: ROOT_ARCH_ZONE_CONFIG.gicc_base + ROOT_ARCH_ZONE_CONFIG.gicc_offset,
- gich_base: ROOT_ARCH_ZONE_CONFIG.gich_base,
- gicv_base: ROOT_ARCH_ZONE_CONFIG.gicv_base,
-};
+pub static GICV2: Once = Once::new();
// get base address of GIC and initialize GIC Structs.
pub fn primary_init_early() {
- info!("GicDistributer = {:#x?}", GICV2.gicd_base);
- info!("GicCpuInterface = {:#x?}", GICV2.gicc_base);
- info!("GicHypervisorInterface = {:#x?}", GICV2.gich_base);
- info!("GicVCpuInterface = {:#x?}", GICV2.gicv_base);
+ match ROOT_ARCH_ZONE_CONFIG.gic_config {
+ GicConfig::Gicv3(_) => {
+ panic!("GICv3 is not supported in this version of hvisor");
+ }
+ GicConfig::Gicv2(ref gicv2_config) => {
+ info!("GICv2 detected");
+ GICV2.call_once(|| {
+ Gicv2 {
+ gicd_base: gicv2_config.gicd_base,
+ /*
+ * Some boards have the GIC CPU interface registers alias, which will overlap DIR register, so we need to add an offset to
+ * find the last gic cpu alias region.
+ * ref: https://github.com/Xilinx/qemu-devicetrees/commit/09d4c3200538dc90082fbda9289e2af9794b9a28
+ */
+ gicc_base: gicv2_config.gicc_base + gicv2_config.gicc_offset,
+ gich_base: gicv2_config.gich_base,
+ gicv_base: gicv2_config.gicv_base,
+ }
+ });
+ gicd_init(gicv2_config.gicd_base);
+ gicc_init(gicv2_config.gicc_base + gicv2_config.gicc_offset);
+ gich_init(gicv2_config.gich_base);
+ gicv_init(gicv2_config.gicv_base);
+ info!(
+ "GIC Distributor base: {:#x}, size: {:#x}",
+ GICV2.get().unwrap().gicd_base,
+ gicv2_config.gicd_size
+ );
+ info!(
+ "GIC CPU Interface base: {:#x}, size: {:#x}",
+ GICV2.get().unwrap().gicc_base,
+ gicv2_config.gicc_size
+ );
+ info!("GIC CPU Interface offset: {:#x}", gicv2_config.gicc_offset);
+ info!(
+ "GIC Hypervisor Interface base: {:#x}, size: {:#x}",
+ GICV2.get().unwrap().gich_base,
+ gicv2_config.gich_size
+ );
+ info!(
+ "GIC Virtual CPU Interface base: {:#x}, size: {:#x}",
+ GICV2.get().unwrap().gicv_base,
+ gicv2_config.gicv_size
+ );
+ }
+ };
gic::PENDING_VIRQS.call_once(|| gic::PendingIrqs::new(MAX_CPU_NUM));
}
pub fn percpu_init() {
- GICC.init();
+ GICC.get().unwrap().init();
}
pub fn primary_init_late() {
- GICD.global_init();
+ GICD.get().unwrap().global_init();
}
-
impl Zone {
pub fn arch_irqchip_reset(&self) {
// todo
diff --git a/src/device/irqchip/gicv2/vgic.rs b/src/device/irqchip/gicv2/vgic.rs
index eddfcb90..a3af2309 100644
--- a/src/device/irqchip/gicv2/vgic.rs
+++ b/src/device/irqchip/gicv2/vgic.rs
@@ -12,8 +12,8 @@
// https://www.syswonder.org
//
// Authors:
-//
-use crate::arch::zone::HvArchZoneConfig;
+// Hangqi Ren <2572131118@qq.com>
+use crate::arch::zone::{GicConfig, Gicv2Config, HvArchZoneConfig};
use crate::device::irqchip::gicv2::gicd::{
get_max_int_num, GICD, GICD_CTRL_REG_OFFSET, GICD_ICACTIVER_REG_OFFSET,
GICD_ICENABLER_REG_OFFSET, GICD_ICFGR_REG_OFFSET, GICD_ICPENDR_REG_OFFSET,
@@ -39,30 +39,57 @@ const GICV2_REG_WIDTH: usize = 4;
impl Zone {
// trap all Guest OS accesses to the GIC Distributor registers.
pub fn vgicv2_mmio_init(&mut self, arch: &HvArchZoneConfig) {
- if arch.gicd_base == 0 {
- panic!("vgicv2_mmio_init: gicd_base is null");
+ match arch.gic_config {
+ GicConfig::Gicv3(_) => {
+ panic!("GICv3 is not supported in this version of hvisor");
+ }
+ GicConfig::Gicv2(ref gicv2_config) => {
+ if gicv2_config.gicd_base == 0 {
+ panic!("vgicv2_mmio_init: gicd_base is null");
+ }
+ info!("Initializing GICv2 MMIO regions for zone {}", self.id);
+ self.mmio_region_register(
+ gicv2_config.gicd_base,
+ gicv2_config.gicd_size,
+ vgicv2_dist_handler,
+ 0,
+ );
+ }
}
- self.mmio_region_register(arch.gicd_base, arch.gicd_size, vgicv2_dist_handler, 0);
}
// remap the GIC CPU interface register address space to point to the GIC virtual CPU interface registers.
pub fn vgicv2_remap_init(&mut self, arch: &HvArchZoneConfig) {
- if arch.gicc_base == 0 || arch.gicv_base == 0 || arch.gicc_size == 0 || arch.gicv_size == 0
- {
- panic!("vgicv2_remap_init: gic related address is null");
- }
- if arch.gicv_size != arch.gicc_size {
- panic!("vgicv2_remap_init: gicv_size not equal to gicc_size");
+ match arch.gic_config {
+ GicConfig::Gicv3(_) => {
+ panic!("GICv3 is not supported in this version of hvisor");
+ }
+ GicConfig::Gicv2(ref gicv2_config) => {
+ if gicv2_config.gicc_base == 0
+ || gicv2_config.gicv_base == 0
+ || gicv2_config.gicc_size == 0
+ || gicv2_config.gicv_size == 0
+ {
+ panic!("vgicv2_remap_init: gic related address is null");
+ }
+ if gicv2_config.gicv_size != gicv2_config.gicc_size {
+ panic!("vgicv2_remap_init: gicv_size not equal to gicc_size");
+ }
+ info!(
+ "Remaping GICv2 GICV MMIO regions to GICC MMIO regions for zone {}",
+ self.id
+ );
+ // map gicv memory region to gicc memory region.
+ self.gpm
+ .insert(MemoryRegion::new_with_offset_mapper(
+ gicv2_config.gicc_base,
+ gicv2_config.gicv_base,
+ gicv2_config.gicc_size,
+ MemFlags::READ | MemFlags::WRITE,
+ ))
+ .unwrap();
+ }
}
- // map gicv memory region to gicc memory region.
- self.gpm
- .insert(MemoryRegion::new_with_offset_mapper(
- arch.gicc_base,
- arch.gicv_base,
- arch.gicc_size,
- MemFlags::READ | MemFlags::WRITE,
- ))
- .unwrap();
}
// store the interrupt number in the irq_bitmap.
@@ -229,13 +256,13 @@ pub fn set_sgi_irq(irq_id: usize, target_list: usize, routing_mode: usize) {
target_list,
routing_mode
);
- trace!("ISENABLER: {:#x}", GICD.get_isenabler(0));
- GICD.set_sgir(val as u32);
+ trace!("ISENABLER: {:#x}", GICD.get().unwrap().get_isenabler(0));
+ GICD.get().unwrap().set_sgir(val as u32);
}
// Handle GIC Distributor register accesses.
pub fn vgicv2_dist_handler(mmio: &mut MMIOAccess, _arg: usize) -> HvResult {
- let gicd_base = GICV2.gicd_base;
+ let gicd_base = GICV2.get().unwrap().gicd_base;
let reg = mmio.address;
match reg {
diff --git a/src/device/irqchip/gicv3/gicd.rs b/src/device/irqchip/gicv3/gicd.rs
index 87d4b7ed..2729b8c2 100644
--- a/src/device/irqchip/gicv3/gicd.rs
+++ b/src/device/irqchip/gicv3/gicd.rs
@@ -31,6 +31,7 @@ pub const GICD_TYPER: usize = 0x0004;
pub const GICD_IIDR: usize = 0x0008;
pub const GICD_TYPER2: usize = 0x000c;
pub const GICD_IGROUPR: usize = 0x0080;
+pub const GICD_IGRPMODR: usize = 0x0d00;
pub const GICD_ISENABLER: usize = 0x0100;
pub const GICD_ICENABLER: usize = 0x0180;
pub const GICD_ISPENDR: usize = 0x0200;
diff --git a/src/device/irqchip/gicv3/gits.rs b/src/device/irqchip/gicv3/gits.rs
index efc0d0e0..b43c2849 100644
--- a/src/device/irqchip/gicv3/gits.rs
+++ b/src/device/irqchip/gicv3/gits.rs
@@ -131,7 +131,7 @@ pub struct Cmdq {
impl Cmdq {
fn new() -> Self {
let f = Frame::new_contiguous_with_base(CMDQ_PAGES_NUM, 16).unwrap();
- info!("its cmdq base: 0x{:x}", f.start_paddr());
+ info!("ITS cmdq base: 0x{:x}", f.start_paddr());
let r = Self {
phy_addr: f.start_paddr(),
readr: 0,
diff --git a/src/device/irqchip/gicv3/mod.rs b/src/device/irqchip/gicv3/mod.rs
index 3d0969a4..60a22cad 100644
--- a/src/device/irqchip/gicv3/mod.rs
+++ b/src/device/irqchip/gicv3/mod.rs
@@ -28,12 +28,13 @@ use alloc::collections::vec_deque::VecDeque;
use alloc::vec::Vec;
use gicr::init_lpi_prop;
use gits::gits_init;
-use spin::{Mutex, Once};
+use spin::{Lazy, Mutex, Once};
use self::gicd::{enable_gic_are_ns, GICD_ICACTIVER, GICD_ICENABLER};
use self::gicr::enable_ipi;
use crate::arch::aarch64::sysreg::{read_sysreg, smc_arg1, write_sysreg};
-use crate::arch::cpu::this_cpu_id;
+use crate::arch::cpu::{cpuid_to_mpidr_affinity, this_cpu_id};
+use crate::arch::zone::GicConfig;
use crate::config::root_zone_config;
use crate::consts::{self, MAX_CPU_NUM};
@@ -59,7 +60,7 @@ pub fn gicc_init() {
gicv3_clear_pending_irqs();
let _vtr = read_sysreg!(ich_vtr_el2);
- let vmcr = ((pmr & 0xff) << 24) | (1 << 1) | (1 << 9); //VPMR|VENG1|VEOIM
+ let vmcr = ((pmr & 0xff) << 24) | (1 << 1); //VPMR|VENG1
write_sysreg!(ich_vmcr_el2, vmcr);
write_sysreg!(ich_hcr_el2, 0x1); //enable virt cpu interface
@@ -331,6 +332,10 @@ pub fn inject_irq(irq_id: usize, is_hardware: bool) -> bool {
pub static GIC: Once = Once::new();
pub const PER_GICR_SIZE: usize = 0x20000;
+// GICR register offsets and fields
+const GICR_TYPER_AFFINITY_VALUE_SHIFT: usize = 32;
+const GICR_TYPER_AFFINITY_VALUE_MASK: u64 = 0xFFFFFFFF << GICR_TYPER_AFFINITY_VALUE_SHIFT;
+
#[derive(Debug)]
pub struct Gic {
pub gicd_base: usize,
@@ -345,9 +350,45 @@ pub fn host_gicd_base() -> usize {
GIC.get().unwrap().gicd_base
}
+static CPU_GICR_BASE: Lazy> = Lazy::new(|| {
+ let mut bases = vec![0; MAX_CPU_NUM];
+ let gic = GIC.get().unwrap();
+ let base = gic.gicr_base;
+ let mut found_cpus = 0;
+
+ // Scan through all GICR frames once
+ let mut curr_base = base;
+
+ for _ in 0..MAX_CPU_NUM {
+ let typer =
+ unsafe { core::ptr::read_volatile((curr_base + gicr::GICR_TYPER) as *const u64) };
+ let affinity = (typer & GICR_TYPER_AFFINITY_VALUE_MASK) >> GICR_TYPER_AFFINITY_VALUE_SHIFT;
+
+ // Find which CPU this GICR belongs to
+ if let Some(cpu_id) = (0..MAX_CPU_NUM).position(|cpu_id| {
+ let (aff3, aff2, aff1, aff0) = cpuid_to_mpidr_affinity(cpu_id as u64);
+ let aff = (aff3 << 24) | (aff2 << 16) | (aff1 << 8) | aff0;
+ aff == affinity
+ }) {
+ bases[cpu_id] = curr_base;
+ found_cpus += 1;
+ }
+ curr_base += PER_GICR_SIZE;
+ }
+
+ if found_cpus != MAX_CPU_NUM {
+ panic!(
+ "Could not find GICR for all CPUs, only found {}",
+ found_cpus
+ );
+ }
+ info!("GICR bases: {:#x?}", bases);
+ bases
+});
+
pub fn host_gicr_base(id: usize) -> usize {
assert!(id < consts::MAX_CPU_NUM);
- GIC.get().unwrap().gicr_base + id * PER_GICR_SIZE
+ CPU_GICR_BASE[id]
}
pub fn host_gits_base() -> usize {
@@ -384,16 +425,37 @@ pub fn disable_irqs() {
pub fn primary_init_early() {
let root_config = root_zone_config();
-
- GIC.call_once(|| Gic {
- gicd_base: root_config.arch_config.gicd_base,
- gicr_base: root_config.arch_config.gicr_base,
- gicd_size: root_config.arch_config.gicd_size,
- gicr_size: root_config.arch_config.gicr_size,
- gits_base: root_config.arch_config.gits_base,
- gits_size: root_config.arch_config.gits_size,
- });
-
+ match root_config.arch_config.gic_config {
+ GicConfig::Gicv2(_) => {
+ panic!("GICv2 is not supported in this version of hvisor");
+ }
+ GicConfig::Gicv3(ref gicv3_config) => {
+ info!("GICv3 detected");
+ GIC.call_once(|| Gic {
+ gicd_base: gicv3_config.gicd_base,
+ gicr_base: gicv3_config.gicr_base,
+ gicd_size: gicv3_config.gicd_size,
+ gicr_size: gicv3_config.gicr_size,
+ gits_base: gicv3_config.gits_base,
+ gits_size: gicv3_config.gits_size,
+ });
+ info!(
+ "GIC Distributor base: {:#x}, size: {:#x}",
+ GIC.get().unwrap().gicd_base,
+ GIC.get().unwrap().gicd_size
+ );
+ info!(
+ "GIC Redistributor base: {:#x}, size: {:#x}",
+ GIC.get().unwrap().gicr_base,
+ GIC.get().unwrap().gicr_size
+ );
+ info!(
+ "GIC ITS base: {:#x}, size: {:#x}",
+ GIC.get().unwrap().gits_base,
+ GIC.get().unwrap().gits_size
+ );
+ }
+ }
init_lpi_prop();
if host_gits_base() != 0 && host_gits_size() != 0 {
diff --git a/src/device/irqchip/gicv3/vgic.rs b/src/device/irqchip/gicv3/vgic.rs
index e4e812fc..b5662b4d 100644
--- a/src/device/irqchip/gicv3/vgic.rs
+++ b/src/device/irqchip/gicv3/vgic.rs
@@ -16,8 +16,9 @@
use alloc::sync::Arc;
use super::{gicd::GICD_LOCK, is_spi};
+use crate::platform::BOARD_MPIDR_MAPPINGS;
use crate::{
- arch::zone::HvArchZoneConfig,
+ arch::zone::{GicConfig, Gicv2Config, Gicv3Config, HvArchZoneConfig},
consts::MAX_CPU_NUM,
device::irqchip::gicv3::{
gicd::*, gicr::*, gits::*, host_gicd_base, host_gicr_base, host_gits_base,
@@ -29,24 +30,45 @@ use crate::{
percpu::{get_cpu_data, this_zone},
zone::{this_zone_id, Zone},
};
-
pub fn reg_range(base: usize, n: usize, size: usize) -> core::ops::Range {
base..(base + n * size)
}
impl Zone {
pub fn vgicv3_mmio_init(&mut self, arch: &HvArchZoneConfig) {
- if arch.gicd_base == 0 || arch.gicr_base == 0 {
- panic!("vgicv3_mmio_init: gicd_base or gicr_base is null");
- }
+ match arch.gic_config {
+ GicConfig::Gicv2(_) => {
+ panic!("vgicv3_mmio_init: GICv2 is not supported in this function");
+ }
+ GicConfig::Gicv3(ref gicv3_config) => {
+ // GICv3 specific initialization
+ info!("Initializing GICv3 MMIO regions for zone {}", self.id);
+ if gicv3_config.gicd_base == 0 || gicv3_config.gicr_base == 0 {
+ panic!("vgicv3_mmio_init: gicd_base or gicr_base is null");
+ }
- self.mmio_region_register(arch.gicd_base, arch.gicd_size, vgicv3_dist_handler, 0);
- self.mmio_region_register(arch.gits_base, arch.gits_size, vgicv3_its_handler, 0);
+ self.mmio_region_register(
+ gicv3_config.gicd_base,
+ gicv3_config.gicd_size,
+ vgicv3_dist_handler,
+ 0,
+ );
+ self.mmio_region_register(
+ gicv3_config.gits_base,
+ gicv3_config.gits_size,
+ vgicv3_its_handler,
+ 0,
+ );
- for cpu in 0..MAX_CPU_NUM {
- let gicr_base = arch.gicr_base + cpu * PER_GICR_SIZE;
- debug!("registering gicr {} at {:#x?}", cpu, gicr_base);
- self.mmio_region_register(gicr_base, PER_GICR_SIZE, vgicv3_redist_handler, cpu);
+ for cpu in 0..MAX_CPU_NUM {
+ let gicr_base = host_gicr_base(cpu);
+ info!(
+ "Registering GIC Redistributor region for CPU {} at {:#x?}",
+ cpu, gicr_base
+ );
+ self.mmio_region_register(gicr_base, PER_GICR_SIZE, vgicv3_redist_handler, cpu);
+ }
+ }
}
}
@@ -151,9 +173,13 @@ pub fn vgicv3_redist_handler(mmio: &mut MMIOAccess, cpu: usize) -> HvResult {
}
}
}
- GICR_TYPER => {
+ reg if reg == GICR_TYPER || reg == GICR_TYPER + 0x4 => {
+ // For aarch32 guest, the access to GICR_TYPER will be split into two parts.
+ // Many GIC supports 32-bit access to GICR_TYPER twice.
mmio_perform_access(gicr_base, mmio);
- if cpu == MAX_CPU_NUM - 1 {
+ let max_mpidr = BOARD_MPIDR_MAPPINGS.iter().max().copied().unwrap_or(0);
+ let current_mpidr = BOARD_MPIDR_MAPPINGS[cpu];
+ if current_mpidr == max_mpidr && reg == GICR_TYPER {
mmio.value |= GICR_TYPER_LAST;
}
}
@@ -292,6 +318,14 @@ pub fn vgicv3_dist_handler(mmio: &mut MMIOAccess, _arg: usize) -> HvResult {
reg if reg_range(GICD_IPRIORITYR, 255, 4).contains(®) => {
restrict_bitmask_access(mmio, (reg & 0x3ff) / 4, 8, false, gicd_base)
}
+ reg if reg_range(GICD_IGRPMODR, 32, 4).contains(®) => {
+ // GICD_IGRPMODR is not supported in hvisor because it is used for secure state.
+ warn!(
+ "GICD_IGRPMODR is not supported in hvisor, reg = {:#x?}",
+ reg
+ );
+ Ok(())
+ }
_ => vgicv3_dist_misc_access(mmio, gicd_base),
}
}
diff --git a/src/device/irqchip/ls7a2000/mod.rs b/src/device/irqchip/ls7a2000/mod.rs
index aeebc16c..b34a766c 100644
--- a/src/device/irqchip/ls7a2000/mod.rs
+++ b/src/device/irqchip/ls7a2000/mod.rs
@@ -18,6 +18,7 @@
use crate::{
arch::{
+ clock::*,
cpu::this_cpu_id,
ipi::*,
register::{read_gcsr_estat, write_gcsr_estat},
@@ -67,12 +68,32 @@ pub fn primary_init_late() {
info!("loongarch64: irqchip: primary_init_late finished");
}
+
+// actually these configures are from cpucfg, not irqchip, but we put all
+// configuartion stuff here for convenience
+pub fn clock_cpucfg_dump() {
+ info!(
+ "loongarch64: irqchip: clock_cpucfg_dump: cc_freq: {}",
+ get_cpucfg_cc_freq()
+ );
+ info!(
+ "loongarch64: irqchip: clock_cpucfg_dump: cc_mul: {}",
+ get_cpucfg_cc_mul()
+ );
+ info!(
+ "loongarch64: irqchip: clock_cpucfg_dump: cc_div: {}",
+ get_cpucfg_cc_div()
+ );
+}
+
pub fn percpu_init() {
info!("loongarch64: irqchip: percpu_init: running percpu_init");
clear_all_ipi(this_cpu_id());
enable_ipi(this_cpu_id());
ecfg_ipi_enable();
+ clock_cpucfg_dump();
+ // timer_test_tick();
}
const INT_SWI0: usize = 0;
diff --git a/src/device/irqchip/mod.rs b/src/device/irqchip/mod.rs
index 4e76929d..13a2e76f 100644
--- a/src/device/irqchip/mod.rs
+++ b/src/device/irqchip/mod.rs
@@ -14,6 +14,7 @@
// Authors:
//
use crate::arch::zone::HvArchZoneConfig;
+use crate::config::HvZoneConfig;
use crate::zone::Zone;
#[cfg(all(feature = "gicv2", target_arch = "aarch64"))]
@@ -31,35 +32,58 @@ pub use gicv3::{
gicd::set_ispender, inject_irq, percpu_init, primary_init_early, primary_init_late,
};
-#[cfg(all(feature = "aclint", target_arch = "riscv64"))]
-pub mod aclint;
-
-#[cfg(all(feature = "plic", target_arch = "riscv64"))]
-pub mod plic;
-
-#[cfg(all(feature = "aia", target_arch = "riscv64"))]
-pub mod aia;
-
-#[cfg(target_arch = "riscv64")]
-pub fn primary_init_early() {
- // aclint is local interrupt controller
- // plic & aia is global interrupt controller
- #[cfg(feature = "plic")]
- plic::primary_init_early();
- #[cfg(feature = "aia")]
- aia::aplic::primary_init_early();
- #[cfg(feature = "aclint")]
- aclint::aclint_init(crate::platform::ACLINT_SSWI_BASE);
-}
-
+#[cfg(target_arch = "aarch64")]
pub fn gic_handle_irq() {
- #[cfg(all(feature = "gicv2", target_arch = "aarch64"))]
+ #[cfg(feature = "gicv2")]
gicv2::gic::gicv2_handle_irq();
- #[cfg(all(feature = "gicv3", target_arch = "aarch64"))]
+ #[cfg(feature = "gicv3")]
gicv3::gicv3_handle_irq_el1();
}
+#[cfg(target_arch = "aarch64")]
+pub fn gic_send_event(cpu_id: u64, sgi_num: u64) {
+ #[cfg(feature = "gicv3")]
+ {
+ /*Actually, the value passed to ICC_SGI1R_EL1 should be derived from
+ the MPIDR of the target CPU. However, since we cannot access this
+ register on the sender side, we have reverse-engineered a value
+ here using the cpu_id.
+ Due to differences in how some CPU implementations (e.g., RK3568 and RK3588)
+ encode affinity values in MPIDR, we use conditional compilation to handle
+ platform-specific mappings between cpu_id and interrupt target affinity.
+ */
+
+ use crate::arch::cpu::cpuid_to_mpidr_affinity;
+ use crate::arch::sysreg::write_sysreg;
+ let (aff3, aff2, aff1, aff0) = cpuid_to_mpidr_affinity(cpu_id);
+ let target_list = 1 << aff0;
+ let irm: u64 = 0 << 40;
+ let sgi_id: u64 = sgi_num << 24;
+ let val: u64 = (aff1 << 16) | (aff2 << 32) | (aff3 << 48) | irm | sgi_id | target_list;
+ write_sysreg!(icc_sgi1r_el1, val);
+ debug!("write sgi sys value = {:#x}", val);
+ }
+ #[cfg(feature = "gicv2")]
+ {
+ let sgi_id: u64 = sgi_num;
+ let target_list: u64 = 1 << cpu_id;
+ set_sgi_irq(sgi_id as usize, target_list as usize, 0);
+ }
+}
+
impl Zone {
+ pub fn virqc_init(&mut self, config: &HvZoneConfig) {
+ #[cfg(all(feature = "plic", target_arch = "riscv64"))]
+ {
+ self.vplic_init(config);
+ }
+ #[cfg(all(feature = "aia", target_arch = "riscv64"))]
+ {
+ self.vaplic_init(config);
+ self.vimsic_init(config);
+ }
+ }
+
pub fn mmio_init(&mut self, hv_config: &HvArchZoneConfig) {
#[cfg(all(feature = "gicv2", target_arch = "aarch64"))]
{
@@ -74,14 +98,46 @@ impl Zone {
{
self.vplic_mmio_init(hv_config);
}
+ #[cfg(all(feature = "aia", target_arch = "riscv64"))]
+ {
+ self.vaplic_mmio_init(hv_config);
+ }
+ #[cfg(all(feature = "eic770x_soc", target_arch = "riscv64"))]
+ {
+ #[cfg(feature = "sifive_ccache")]
+ self.virtual_sifive_ccache_mmio_init();
+ #[cfg(feature = "eic7700_sysreg")]
+ self.virtual_syscon_mmio_init();
+ }
}
}
+#[cfg(all(feature = "aclint", target_arch = "riscv64"))]
+pub mod aclint;
+
+#[cfg(all(feature = "plic", target_arch = "riscv64"))]
+pub mod plic;
+
#[cfg(all(feature = "plic", target_arch = "riscv64"))]
pub use plic::{host_plic, inject_irq, percpu_init, primary_init_late};
#[cfg(all(feature = "aia", target_arch = "riscv64"))]
-pub use aia::aplic::{host_aplic, inject_irq, percpu_init, primary_init_late, vaplic_emul_handler};
+pub mod aia;
+
+#[cfg(all(feature = "aia", target_arch = "riscv64"))]
+pub use aia::{host_aplic, inject_irq, percpu_init, primary_init_late};
+
+#[cfg(target_arch = "riscv64")]
+pub fn primary_init_early() {
+ // aclint is local interrupt controller
+ // plic & aia is global interrupt controller
+ #[cfg(feature = "plic")]
+ plic::primary_init_early();
+ #[cfg(feature = "aia")]
+ aia::primary_init_early();
+ #[cfg(feature = "aclint")]
+ aclint::aclint_init(crate::platform::ACLINT_SSWI_BASE);
+}
#[cfg(target_arch = "loongarch64")]
pub mod ls7a2000;
diff --git a/src/device/irqchip/plic/mod.rs b/src/device/irqchip/plic/mod.rs
index 68162508..64a9163c 100644
--- a/src/device/irqchip/plic/mod.rs
+++ b/src/device/irqchip/plic/mod.rs
@@ -11,7 +11,7 @@
// Syswonder Website:
// https://www.syswonder.org
//
-// Authors:
+// Authors: Jingyu Liu
//
pub mod plic;
@@ -21,15 +21,18 @@ pub use self::plic::*;
use self::vplic::*;
use crate::arch::zone::HvArchZoneConfig;
use crate::config::root_zone_config;
-use crate::consts::MAX_CPU_NUM;
+use crate::config::HvZoneConfig;
+use crate::consts::{MAX_CPU_NUM, MAX_ZONE_NUM};
use crate::error::HvResult;
use crate::memory::mmio::MMIOAccess;
use crate::memory::GuestPhysAddr;
use crate::percpu::this_zone;
use crate::platform::__board::*;
+use crate::platform::BOARD_PLIC_INTERRUPTS_NUM;
use crate::zone::Zone;
use crate::{arch::cpu::ArchCpu, percpu::this_cpu_data};
use alloc::vec::Vec;
+use heapless::FnvIndexMap;
use riscv_decode::Instruction;
use riscv_h::register::hvip;
use spin::Once;
@@ -41,7 +44,10 @@ use spin::Once;
For physical plic, we don't add lock for it.
*/
+// Physical PLIC
pub static PLIC: Once = Once::new();
+// The MAX_ZONE_NUM should be the power of 2.
+static mut VPLIC_MAP: Option> = None;
pub fn init_plic(plic_base: usize) {
PLIC.call_once(|| Plic::new(plic_base));
@@ -56,6 +62,10 @@ pub fn primary_init_early() {
let root_config = root_zone_config();
init_plic(root_config.arch_config.plic_base as usize);
host_plic().init_global(BOARD_PLIC_INTERRUPTS_NUM, MAX_CPU_NUM * 2);
+
+ unsafe {
+ VPLIC_MAP = Some(FnvIndexMap::new());
+ }
}
pub fn primary_init_late() {
@@ -74,9 +84,7 @@ pub fn inject_irq(irq: usize, is_hardware: bool) {
.as_ref()
.unwrap()
.read()
- .vplic
- .as_ref()
- .unwrap()
+ .get_vplic()
.inject_irq(vcontext_id, irq, is_hardware);
}
@@ -125,9 +133,7 @@ pub fn vplic_handler(mmio: &mut MMIOAccess, _arg: usize) -> HvResult {
.as_ref()
.unwrap()
.read()
- .vplic
- .as_ref()
- .unwrap()
+ .get_vplic()
.vplic_emul_access(mmio.address, mmio.size, mmio.value, mmio.is_write);
if !mmio.is_write {
// read from vplic
@@ -145,18 +151,61 @@ pub fn update_hart_line() {
.as_ref()
.unwrap()
.read()
- .vplic
- .as_ref()
- .unwrap()
+ .get_vplic()
.update_hart_line(vcontext_id);
}
+/// Print all keys in the VPLIC_MAP for debugging purposes.
+fn print_keys() {
+ info!("VPLIC_MAP keys:");
+ unsafe {
+ if let Some(map) = &VPLIC_MAP {
+ for (&key, _) in map.iter() {
+ info!("Zone {} in VPLIC_MAP", key);
+ }
+ }
+ }
+}
+
impl Zone {
+ /// Initial the virtual PLIC related to thiz Zone.
+ pub fn vplic_init(&mut self, config: &HvZoneConfig) {
+ // Create a new VirtualPLIC for this Zone.
+ unsafe {
+ if let Some(map) = &mut VPLIC_MAP {
+ if map.contains_key(&self.id) {
+ panic!("VirtualPLIC for Zone {} already exists!", self.id);
+ }
+ let vplic = vplic::VirtualPLIC::new(
+ config.arch_config.plic_base,
+ BOARD_PLIC_INTERRUPTS_NUM,
+ self.cpu_num * 2,
+ );
+ // Insert into Map
+ let _ = map.insert(self.id, vplic);
+ } else {
+ panic!("VPLIC_MAP is not initialized!");
+ }
+ }
+ info!("VirtualPLIC for Zone {} initialized successfully", self.id);
+ print_keys();
+ }
+
+ pub fn get_vplic(&self) -> &VirtualPLIC {
+ unsafe {
+ VPLIC_MAP
+ .as_ref()
+ .expect("VPLIC_MAP is not initialized!")
+ .get(&self.id)
+ .expect("VirtualPLIC for this Zone does not exist!")
+ }
+ }
+
pub fn arch_irqchip_reset(&self) {
// We should make sure only one cpu to do this.
// This func will only be called by one root zone's cpu.
let host_plic = host_plic();
- let vplic = self.vplic.as_ref().unwrap();
+ let vplic = self.get_vplic();
for (index, &word) in self.irq_bitmap.iter().enumerate() {
for bit_position in 0..32 {
if word & (1 << bit_position) != 0 {
@@ -189,6 +238,15 @@ impl Zone {
info!("Clear events related to cpu {}", cpuid);
crate::event::clear_events(cpuid);
});
+
+ unsafe {
+ if let Some(map) = &mut VPLIC_MAP {
+ map.remove(&self.id);
+ } else {
+ panic!("VPLIC_MAP is not initialized!");
+ }
+ }
+ print_keys();
}
fn insert_irq_to_bitmap(&mut self, irq: u32) {
@@ -204,10 +262,7 @@ impl Zone {
let irq_id = *irq;
// They are hardware interrupts.
if HW_IRQS.iter().any(|&x| x == irq_id) {
- self.vplic
- .as_ref()
- .unwrap()
- .vplic_set_hw(irq_id as usize, true);
+ self.get_vplic().vplic_set_hw(irq_id as usize, true);
info!("Set irq {} to hardware interrupt", irq_id);
}
self.insert_irq_to_bitmap(irq_id);
diff --git a/src/device/irqchip/plic/plic.rs b/src/device/irqchip/plic/plic.rs
index 663679d9..821d678e 100644
--- a/src/device/irqchip/plic/plic.rs
+++ b/src/device/irqchip/plic/plic.rs
@@ -11,7 +11,7 @@
// Syswonder Website:
// https://www.syswonder.org
//
-// Authors:
+// Authors: Jingyu Liu
//
/*
diff --git a/src/device/irqchip/plic/vplic.rs b/src/device/irqchip/plic/vplic.rs
index 9bd020e8..91d057a7 100644
--- a/src/device/irqchip/plic/vplic.rs
+++ b/src/device/irqchip/plic/vplic.rs
@@ -132,13 +132,18 @@ impl VirtualPLIC {
error!("vplic_emul_access: only allowed word accesses");
return 0;
}
- if value > u32::MAX as usize {
- error!(
- "vplic_emul_access: value {:#x} is out of range 0xffffffff",
- value
- );
- return 0;
- }
+ // Reason for annotation: When four consecutive interrupts are enabled,
+ // their corresponding enable bits are bits 28, 29, 30, and 31 of the same context.
+ // According to the kernel's enable logic, the written mask bits accumulate to 0xF0000000.
+ // After writing this value to a 64-bit register, sign extension occurs,
+ // converting the value to 0xFFFFFFFFF0000000, which leads to the following error.
+ // if value > u32::MAX as usize {
+ // error!(
+ // "vplic_emul_access: value {:#x} is out of range 0xffffffff",
+ // value
+ // );
+ // return 0;
+ // }
/*
* In VirtualPLICInner, we don't check, so in this function, we must check operations.
@@ -414,7 +419,8 @@ impl VirtualPLICInner {
}
}
} else {
- use crate::event::{send_event, IPI_EVENT_UPDATE_HART_LINE};
+ use crate::consts::IPI_EVENT_UPDATE_HART_LINE;
+ use crate::event::send_event;
let cpu_id = pcontext_id / 2;
info!("vplic_update_hart_line to cpu {}", cpu_id);
// the second arg don't need.
diff --git a/src/device/mod.rs b/src/device/mod.rs
index 888671aa..fdca7686 100644
--- a/src/device/mod.rs
+++ b/src/device/mod.rs
@@ -17,3 +17,9 @@ pub mod common;
pub mod irqchip;
pub mod uart;
pub mod virtio_trampoline;
+
+#[cfg(feature = "eic7700_sysreg")]
+pub mod eic7700_syscrg;
+
+#[cfg(feature = "sifive_ccache")]
+pub mod sifive_ccache;
diff --git a/src/device/sifive_ccache/ccache.rs b/src/device/sifive_ccache/ccache.rs
new file mode 100644
index 00000000..888f7fbe
--- /dev/null
+++ b/src/device/sifive_ccache/ccache.rs
@@ -0,0 +1,83 @@
+// Copyright (c) 2025 Syswonder
+// hvisor is licensed under Mulan PSL v2.
+// You can use this software according to the terms and conditions of the Mulan PSL v2.
+// You may obtain a copy of Mulan PSL v2 at:
+// http://license.coscl.org.cn/MulanPSL2
+// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+// FIT FOR A PARTICULAR PURPOSE.
+// See the Mulan PSL v2 for more details.
+//
+// Syswonder Website:
+// https://www.syswonder.org
+//
+// Authors: Jingyu Liu
+//
+
+pub const SIFIVE_CCACHE_CONFIG: usize = 0x00;
+pub const SIFIVE_CCACHE_CONFIG_BANK_MASK: u32 = 0xFF; // config[7:0]
+pub const SIFIVE_CCACHE_CONFIG_WAYS_MASK: u32 = 0xFF << 8; // config[15:8]
+pub const SIFIVE_CCACHE_CONFIG_SETS_MASK: u32 = 0xFF << 16; // config[23:16]
+pub const SIFIVE_CCACHE_CONFIG_BLKS_MASK: u32 = 0xFF << 24; // config[31:24]
+
+pub const SIFIVE_CCACHE_WAYENABLE: usize = 0x08;
+pub const SIFIVE_CCACHE_FLUSH64: usize = 0x200;
+pub const SIFIVE_CCACHE_FLUSH64_LINE_LEN: usize = 64;
+
+/// SifiveCcache struct
+pub struct SifiveCcache {
+ base: usize,
+}
+
+#[allow(unused)]
+impl SifiveCcache {
+ /// Create a new SifiveCcache instance according to the base address
+ pub fn new(base: usize) -> Self {
+ Self { base }
+ }
+
+ /// Enable all cache ways
+ pub fn init(&self) {
+ let cfg: u32 =
+ unsafe { core::ptr::read_volatile((self.base + SIFIVE_CCACHE_CONFIG) as *const u32) };
+ // Note: once all L3 cache ways are enabled, L3 cache can't be transferred to L3 LIM except restart
+ // Enable whole L3 cache ways
+ unsafe {
+ let val = cfg & SIFIVE_CCACHE_CONFIG_WAYS_MASK >> 8;
+ core::ptr::write_volatile((self.base + SIFIVE_CCACHE_WAYENABLE) as *mut u32, val - 1);
+ }
+ // Get configuration
+ info!(
+ "banks = {}, ways = {}, sets/bank = {}, bytes/block = {}",
+ cfg & SIFIVE_CCACHE_CONFIG_BANK_MASK,
+ (cfg & SIFIVE_CCACHE_CONFIG_WAYS_MASK) >> 8,
+ 1u64 << ((cfg & SIFIVE_CCACHE_CONFIG_SETS_MASK) >> 16),
+ 1u64 << ((cfg & SIFIVE_CCACHE_CONFIG_BLKS_MASK) >> 24)
+ );
+ // Get largest way enabled
+ let cfg = unsafe {
+ core::ptr::read_volatile((self.base + SIFIVE_CCACHE_WAYENABLE) as *const u32)
+ };
+ info!("Node 0, index of the largest way enabled: {}", cfg);
+ }
+
+ pub fn get_config(&self) -> u32 {
+ unsafe { core::ptr::read_volatile((self.base + SIFIVE_CCACHE_CONFIG) as *const u32) }
+ }
+
+ pub fn get_wayenable(&self) -> u32 {
+ unsafe { core::ptr::read_volatile((self.base + SIFIVE_CCACHE_WAYENABLE) as *const u32) }
+ }
+
+ /// Flush the related cache line to Memory
+ pub fn flush_range(&self, paddr: u64) {
+ // Handle page-fault for flush.
+ unsafe {
+ core::ptr::write_volatile(
+ (self.base + SIFIVE_CCACHE_FLUSH64) as *mut usize,
+ paddr as _,
+ );
+ core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
+ }
+ }
+}
diff --git a/src/device/sifive_ccache/mod.rs b/src/device/sifive_ccache/mod.rs
new file mode 100644
index 00000000..a4d2a604
--- /dev/null
+++ b/src/device/sifive_ccache/mod.rs
@@ -0,0 +1,96 @@
+// Copyright (c) 2025 Syswonder
+// hvisor is licensed under Mulan PSL v2.
+// You can use this software according to the terms and conditions of the Mulan PSL v2.
+// You may obtain a copy of Mulan PSL v2 at:
+// http://license.coscl.org.cn/MulanPSL2
+// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+// FIT FOR A PARTICULAR PURPOSE.
+// See the Mulan PSL v2 for more details.
+//
+// Syswonder Website:
+// https://www.syswonder.org
+//
+// Authors: Jingyu Liu
+//
+
+// SiFive composable cache controller Driver
+
+// Note: this driver doesn't leverage full capability of hardware.
+// This is needed for eic7700x soc(1 die), which has dma-noncoherent device, such as mmc, sata.
+// In hvisor, L3 cache can't be used as Loosely-Integrated Memory(LIM).
+
+// Reference:
+// Linux - drivers/soc/sifive/sifive_ccache.c
+
+pub mod ccache;
+
+use crate::arch::zone::HvArchZoneConfig;
+use crate::error::{self, HvResult};
+use crate::memory::mmio::MMIOAccess;
+use crate::platform::__board::{SIFIVE_CCACHE_BASE, SIFIVE_CCACHE_SIZE};
+use crate::zone::Zone;
+use ccache::*;
+use spin::Once;
+
+pub static SIFIVE_CCACHE: Once = Once::new();
+
+pub fn init_sifive_ccache() {
+ SIFIVE_CCACHE.call_once(|| SifiveCcache::new(SIFIVE_CCACHE_BASE));
+ // info!("Sifive composable cache controller initialized at 0x{:x}", SIFIVE_CCACHE_BASE);
+ host_sifive_ccache().init();
+}
+
+pub fn host_sifive_ccache<'a>() -> &'a SifiveCcache {
+ SIFIVE_CCACHE.get().expect("Uninitialized sifive ccache!")
+}
+
+/// Handle Zone's sifive composable cache controller mmio access.
+pub fn virtual_sifive_ccache_handler(mmio: &mut MMIOAccess, _arg: usize) -> HvResult {
+ match mmio.address {
+ SIFIVE_CCACHE_CONFIG => {
+ if mmio.size != 4 || mmio.is_write {
+ error!("virtual_sifive_ccache_handler: Invalid access to SIFIVE_CCACHE_CONFIG");
+ return hv_result_err!(EINVAL);
+ }
+ // Return config to guest
+ mmio.value = host_sifive_ccache().get_config() as _;
+ }
+ SIFIVE_CCACHE_WAYENABLE => {
+ if mmio.is_write {
+ info!("Hvisor doesn't support guest to configure ccache wayenable");
+ info!("Hvisor defaultly configs L3 cache ways enable.");
+ } else {
+ info!("virtual_sifive_ccache_handler: Reading SIFIVE_CCACHE_WAYENABLE");
+ mmio.value = host_sifive_ccache().get_wayenable() as _;
+ }
+ }
+ SIFIVE_CCACHE_FLUSH64 => {
+ if mmio.is_write {
+ host_sifive_ccache().flush_range(mmio.value as _);
+ } else {
+ return hv_result_err!(EPERM, "Guest wants to read SIFIVE_CCACHE_FLUSH64.");
+ }
+ }
+ _ => {
+ error!(
+ "virtual_sifive_ccache_handler: Unknown address 0x{:x}",
+ mmio.address
+ );
+ return hv_result_err!(EFAULT);
+ }
+ };
+ Ok(())
+}
+
+impl Zone {
+ /// Initialize cache controller MMIO region.
+ pub fn virtual_sifive_ccache_mmio_init(&mut self) {
+ self.mmio_region_register(
+ SIFIVE_CCACHE_BASE,
+ SIFIVE_CCACHE_SIZE,
+ virtual_sifive_ccache_handler,
+ 0,
+ );
+ }
+}
diff --git a/src/device/uart/imx_uart.rs b/src/device/uart/imx_uart.rs
index e8d2b623..ed3c8fe0 100644
--- a/src/device/uart/imx_uart.rs
+++ b/src/device/uart/imx_uart.rs
@@ -18,10 +18,7 @@
use core::ptr;
use crate::memory::addr::{PhysAddr, VirtAddr};
-// use spin::Mutex;
-
-pub const UART_BASE_PHYS: PhysAddr = 0x30890000;
-// pub const UART_BASE_VIRT: VirtAddr = 0xffffc0090000;
+use crate::platform::BOARD_UART_BASE;
const UTS: usize = 0xb4;
const UTXD: usize = 0x40;
@@ -29,7 +26,7 @@ const UTS_TXEMPTY: u32 = 1 << 6;
// lazy_static! {
static mut UART: ImxUart = {
- ImxUart::new(UART_BASE_PHYS)
+ ImxUart::new(BOARD_UART_BASE as _)
// Mutex::new(uart)
};
// }
diff --git a/src/device/uart/pl011.rs b/src/device/uart/pl011.rs
index 2b8a58a3..255a656e 100644
--- a/src/device/uart/pl011.rs
+++ b/src/device/uart/pl011.rs
@@ -19,13 +19,12 @@ use tock_registers::register_structs;
use tock_registers::registers::{ReadOnly, ReadWrite, WriteOnly};
use crate::memory::addr::{PhysAddr, VirtAddr};
+use crate::platform::BOARD_UART_BASE;
use spin::Mutex;
-pub const UART_BASE_VIRT: VirtAddr = 0x09000000;
-
lazy_static! {
static ref UART: Mutex = {
- let mut uart = Pl011Uart::new(UART_BASE_VIRT);
+ let mut uart = Pl011Uart::new(BOARD_UART_BASE as _);
uart.init();
Mutex::new(uart)
};
diff --git a/src/device/uart/uart_16550.rs b/src/device/uart/uart_16550.rs
index 1cae26ae..343d7c0b 100644
--- a/src/device/uart/uart_16550.rs
+++ b/src/device/uart/uart_16550.rs
@@ -16,6 +16,7 @@
//
use crate::memory::addr::{PhysAddr, VirtAddr};
+use crate::platform::BOARD_UART_BASE;
use core::ptr;
use spin::Mutex;
use tock_registers::interfaces::*;
@@ -23,15 +24,6 @@ use tock_registers::register_bitfields;
use tock_registers::register_structs;
use tock_registers::registers::*;
-#[cfg(feature = "uart_base_rk3568")]
-pub const UART_BASE: PhysAddr = 0xfe660000;
-
-#[cfg(feature = "uart_base_rk3588")]
-pub const UART_BASE: PhysAddr = 0xfeb50000;
-
-#[cfg(feature = "uart_base_ok6254")]
-pub const UART_BASE: PhysAddr = 0x2800000;
-
/// Register struct representing the UART registers.
register_structs! {
/// Representation of the UART registers.
@@ -87,7 +79,7 @@ impl Uart16550 {
}
}
-static mut UART: Uart16550 = Uart16550::new(UART_BASE);
+static mut UART: Uart16550 = Uart16550::new(BOARD_UART_BASE as _);
#[inline]
pub fn console_putchar(c: u8) {
diff --git a/src/device/uart/xuartps.rs b/src/device/uart/xuartps.rs
index e01e00ea..2f6370b7 100644
--- a/src/device/uart/xuartps.rs
+++ b/src/device/uart/xuartps.rs
@@ -24,6 +24,7 @@
/// 2. https://github.com/Xilinx/linux-xlnx :: drivers/tty/serial/xilinx_uartps.c
/// 3. https://github.com/torvalds/linux/blob/master/drivers/tty/serial/xilinx_uartps.c
use crate::memory::addr::{PhysAddr, VirtAddr};
+use crate::platform::BOARD_UART_BASE;
use spin::Mutex;
use tock_registers::{
interfaces::{ReadWriteable, Readable, Writeable},
@@ -31,8 +32,8 @@ use tock_registers::{
registers::{ReadOnly, ReadWrite, WriteOnly},
};
-pub const UART0_BASE: PhysAddr = 0xff000000;
-pub const UART1_BASE: PhysAddr = 0xff010000;
+// pub const UART0_BASE: PhysAddr = 0xff000000;
+// pub const UART1_BASE: PhysAddr = 0xff010000;
pub const UART_FIFO_SIZE: usize = 64;
pub const UART_REGS_REGION_SIZE: usize = 0x1000;
@@ -44,17 +45,17 @@ pub const UART_BAUDRATE_BDIV: u32 = 6;
lazy_static! {
static ref UART0: Mutex = {
- let mut uart = ZynqUart::new(UART0_BASE);
+ let mut uart = ZynqUart::new(BOARD_UART_BASE as _);
Mutex::new(uart)
};
}
-lazy_static! {
- static ref UART1: Mutex = {
- let mut uart = ZynqUart::new(UART1_BASE);
- Mutex::new(uart)
- };
-}
+// lazy_static! {
+// static ref UART1: Mutex = {
+// let mut uart = ZynqUart::new(UART1_BASE);
+// Mutex::new(uart)
+// };
+// }
register_structs! {
ZynqUartRegs {
diff --git a/src/event.rs b/src/event.rs
index 9838fe2f..c7c2243e 100644
--- a/src/event.rs
+++ b/src/event.rs
@@ -15,8 +15,10 @@
//
#![allow(unused)]
use crate::{
- arch::ipi::arch_send_event,
- consts::MAX_CPU_NUM,
+ arch::ipi::{arch_check_events, arch_prepare_send_event, arch_send_event},
+ consts::{
+ IPI_EVENT_CLEAR_INJECT_IRQ, IPI_EVENT_SEND_IPI, IPI_EVENT_UPDATE_HART_LINE, MAX_CPU_NUM,
+ },
device::{
irqchip::inject_irq,
virtio_trampoline::{handle_virtio_irq, IRQ_WAKEUP_VIRTIO_DEVICE},
@@ -30,9 +32,6 @@ pub const IPI_EVENT_WAKEUP: usize = 0;
pub const IPI_EVENT_SHUTDOWN: usize = 1;
pub const IPI_EVENT_VIRTIO_INJECT_IRQ: usize = 2;
pub const IPI_EVENT_WAKEUP_VIRTIO_DEVICE: usize = 3;
-pub const IPI_EVENT_CLEAR_INJECT_IRQ: usize = 4;
-pub const IPI_EVENT_UPDATE_HART_LINE: usize = 5;
-pub const IPI_EVENT_SEND_IPI: usize = 6;
static EVENT_MANAGER: Once = Once::new();
@@ -95,7 +94,7 @@ fn add_event(cpu: usize, event_id: usize) -> Option<()> {
EVENT_MANAGER.get().unwrap().add_event(cpu, event_id)
}
-fn fetch_event(cpu: usize) -> Option {
+pub fn fetch_event(cpu: usize) -> Option {
EVENT_MANAGER.get().unwrap().fetch_event(cpu)
}
@@ -118,7 +117,8 @@ pub fn clear_events(cpu: usize) {
pub fn check_events() -> bool {
trace!("check_events");
let cpu_data = this_cpu_data();
- match fetch_event(cpu_data.id) {
+ let event = fetch_event(cpu_data.id);
+ match event {
Some(IPI_EVENT_WAKEUP) => {
info!("cpu {} wakeup", cpu_data.id);
cpu_data.arch_cpu.run();
@@ -134,42 +134,51 @@ pub fn check_events() -> bool {
inject_irq(IRQ_WAKEUP_VIRTIO_DEVICE, false);
true
}
- #[cfg(target_arch = "loongarch64")]
- Some(IPI_EVENT_CLEAR_INJECT_IRQ) => {
- use crate::device::irqchip;
- irqchip::ls7a2000::clear_hwi_injected_irq();
- true
- }
- #[cfg(all(target_arch = "riscv64", feature = "plic"))]
- Some(IPI_EVENT_UPDATE_HART_LINE) => {
- use crate::device::irqchip;
- info!("cpu {} update hart line", cpu_data.id);
- irqchip::plic::update_hart_line();
- true
- }
- #[cfg(target_arch = "riscv64")]
- Some(IPI_EVENT_SEND_IPI) => {
- // This event is different from events above, it is used to inject software interrupt.
- // While events above will inject external interrupt.
- use crate::arch::ipi::arch_ipi_handler;
- arch_ipi_handler();
+ Some(IPI_EVENT_CLEAR_INJECT_IRQ)
+ | Some(IPI_EVENT_UPDATE_HART_LINE)
+ | Some(IPI_EVENT_SEND_IPI) => {
+ arch_check_events(event);
true
}
+ // #[cfg(target_arch = "loongarch64")]
+ // Some(IPI_EVENT_CLEAR_INJECT_IRQ) => {
+ // use crate::device::irqchip;
+ // irqchip::ls7a2000::clear_hwi_injected_irq();
+ // true
+ // }
+ // #[cfg(all(target_arch = "riscv64", feature = "plic"))]
+ // Some(IPI_EVENT_UPDATE_HART_LINE) => {
+ // use crate::device::irqchip;
+ // info!("cpu {} update hart line", cpu_data.id);
+ // irqchip::plic::update_hart_line();
+ // true
+ // }
+ // #[cfg(target_arch = "riscv64")]
+ // Some(IPI_EVENT_SEND_IPI) => {
+ // // This event is different from events above, it is used to inject software interrupt.
+ // // While events above will inject external interrupt.
+ // use crate::arch::ipi::arch_ipi_handler;
+ // arch_ipi_handler();
+ // true
+ // }
_ => false,
}
}
pub fn send_event(cpu_id: usize, ipi_int_id: usize, event_id: usize) {
- #[cfg(target_arch = "loongarch64")]
- {
- // block until the previous event is processed, which means
- // the target queue is empty
- while !fetch_event(cpu_id).is_none() {}
- debug!(
- "loongarch64:: send_event: cpu_id: {}, ipi_int_id: {}, event_id: {}",
- cpu_id, ipi_int_id, event_id
- );
- }
+ // #[cfg(target_arch = "loongarch64")]
+ // {
+ // // block until the previous event is processed, which means
+ // // the target queue is empty
+ // while !fetch_event(cpu_id).is_none() {}
+ // debug!(
+ // "loongarch64:: send_event: cpu_id: {}, ipi_int_id: {}, event_id: {}",
+ // cpu_id, ipi_int_id, event_id
+ // );
+ // }
+ /// Some arch need do something before send event.
+ /// Currently, we are not passing parameters, and we will modify the function signature later as needed.
+ arch_prepare_send_event(cpu_id, ipi_int_id, event_id);
add_event(cpu_id, event_id);
arch_send_event(cpu_id as _, ipi_int_id as _);
}
diff --git a/src/hypercall/mod.rs b/src/hypercall/mod.rs
index 2c80d521..b8407f4e 100644
--- a/src/hypercall/mod.rs
+++ b/src/hypercall/mod.rs
@@ -29,10 +29,6 @@ use crate::zone::{
use crate::event::{send_event, IPI_EVENT_SHUTDOWN, IPI_EVENT_VIRTIO_INJECT_IRQ, IPI_EVENT_WAKEUP};
use core::convert::TryFrom;
use core::sync::atomic::{fence, Ordering};
-
-#[cfg(target_arch = "aarch64")]
-use crate::ivc::{IvcInfo, IVC_INFOS};
-
use numeric_enum_macro::numeric_enum;
numeric_enum! {
@@ -84,7 +80,7 @@ impl<'a> HyperCall<'a> {
HyperCallCode::HvZoneShutdown => self.hv_zone_shutdown(arg0),
HyperCallCode::HvZoneList => self.hv_zone_list(&mut *(arg0 as *mut ZoneInfo), arg1),
HyperCallCode::HvClearInjectIrq => {
- use crate::event::IPI_EVENT_CLEAR_INJECT_IRQ;
+ use crate::consts::IPI_EVENT_CLEAR_INJECT_IRQ;
for i in 1..MAX_CPU_NUM {
// if target cpu status is not running, we skip it
if !get_cpu_data(i).arch_cpu.power_on {
@@ -94,7 +90,6 @@ impl<'a> HyperCall<'a> {
}
HyperCallResult::Ok(0)
}
- #[cfg(target_arch = "aarch64")]
HyperCallCode::HvIvcInfo => self.hv_ivc_info(arg0),
HyperCallCode::HvConfigCheck => self.hv_zone_config_check(arg0 as *mut u64),
_ => {
@@ -105,29 +100,6 @@ impl<'a> HyperCall<'a> {
}
}
- #[cfg(target_arch = "aarch64")]
- fn hv_ivc_info(&mut self, ivc_info_ipa: u64) -> HyperCallResult {
- let zone_id = this_zone_id();
- let zone = this_zone();
- // ipa->hpa->hva
- let hpa = unsafe {
- zone.read()
- .gpm
- .page_table_query(ivc_info_ipa as _)
- .unwrap()
- .0
- };
- // hva == hpa
- let ivc_info = unsafe { &mut *(hpa as *mut IvcInfo) };
- let ivc_infos = IVC_INFOS.lock();
- let zone_ivc_info = ivc_infos.get(&(zone_id as _));
- match zone_ivc_info {
- Some(zone_ivc_info) => *ivc_info = *zone_ivc_info,
- None => return hv_result_err!(ENODEV, "Zone {zone_id} has no ivc config!"),
- }
- HyperCallResult::Ok(0)
- }
-
// only root zone calls the function and set virtio shared region between el1 and el2.
fn hv_virtio_init(&mut self, shared_region_addr: u64) -> HyperCallResult {
info!(
@@ -138,10 +110,7 @@ impl<'a> HyperCall<'a> {
return hv_result_err!(EPERM, "Init virtio over non-root zones: unsupported!");
}
- let shared_region_addr_pa = shared_region_addr as usize;
- #[cfg(target_arch = "loongarch64")]
- let shared_region_addr_pa =
- shared_region_addr_pa | crate::arch::mm::LOONGARCH64_CACHED_DMW_PREFIX as usize;
+ let shared_region_addr_pa = self.translate_ipa_to_hva(shared_region_addr) as usize;
assert!(shared_region_addr_pa % PAGE_SIZE == 0);
// let offset = shared_region_addr_pa & (PAGE_SIZE - 1);
@@ -162,7 +131,7 @@ impl<'a> HyperCall<'a> {
}
// Inject virtio device's irq to non root when a virtio device finishes one IO request. Only root zone calls.
- fn hv_virtio_inject_irq(&self) -> HyperCallResult {
+ fn hv_virtio_inject_irq(&mut self) -> HyperCallResult {
trace!("hv_virtio_inject_irq: hypercall for trigger target cpu to inject irq");
if !is_this_root_zone() {
return hv_result_err!(
@@ -189,17 +158,8 @@ impl<'a> HyperCall<'a> {
};
let irq_list = map_irq.entry(target_cpu).or_insert([0; MAX_DEVS + 1]);
- #[cfg(target_arch = "loongarch64")]
- {
- use crate::device::irqchip::ls7a2000::*;
- let status = GLOBAL_IRQ_INJECT_STATUS.lock();
- debug!(
- "hv_virtio_inject_irq: cpu {} status: {:?}",
- target_cpu, status.cpu_status[target_cpu].status
- );
- drop(status);
- irq_list[0] = 0; // CAUTION: this is a workaround for loongarch64
- }
+
+ self.wait_for_interrupt(irq_list);
if !irq_list[1..=irq_list[0] as usize].contains(&irq_id) {
let len = irq_list[0] as usize;
assert!(len + 1 < MAX_DEVS);
@@ -220,41 +180,10 @@ impl<'a> HyperCall<'a> {
HyperCallResult::Ok(0)
}
- pub fn hv_zone_config_check(&self, magic_version: *mut u64) -> HyperCallResult {
- #[cfg(target_arch = "loongarch64")]
- {
- let magic_version_raw = magic_version as u64;
- let magic_version_hva =
- magic_version_raw | crate::arch::mm::LOONGARCH64_CACHED_DMW_PREFIX;
- let magic_version_hva = magic_version_hva as *mut u64;
- debug!(
- "hv_zone_config_check: magic_version target addr to write = {:#x?}",
- magic_version_hva
- );
- unsafe {
- core::ptr::write(magic_version_hva, CONFIG_MAGIC_VERSION as _);
- }
- }
- #[cfg(not(target_arch = "loongarch64"))]
- {
- unsafe {
- *magic_version = CONFIG_MAGIC_VERSION as _;
- }
- }
- debug!(
- "hv_zone_config_check: finished writing current magic version ({:#x})",
- CONFIG_MAGIC_VERSION
- );
- HyperCallResult::Ok(0)
- }
-
pub fn hv_zone_start(&mut self, config: &HvZoneConfig, config_size: u64) -> HyperCallResult {
- #[cfg(target_arch = "loongarch64")]
- let config = unsafe {
- &*((config as *const HvZoneConfig as u64
- | crate::arch::mm::LOONGARCH64_CACHED_DMW_PREFIX)
- as *const HvZoneConfig)
- };
+ let config_ipa = config as *const HvZoneConfig as u64;
+ let config_pa = self.hv_get_real_pa(config_ipa);
+ let config = unsafe { &*(config_pa as *const HvZoneConfig) };
debug!("hv_zone_start: config: {:#x?}", config);
if !is_this_root_zone() {
@@ -280,18 +209,13 @@ impl<'a> HyperCall<'a> {
let _lock = target_data.ctrl_lock.lock();
if !target_data.arch_cpu.power_on {
+ info!("boot_cpu: {}", boot_cpu);
send_event(boot_cpu, SGI_IPI_ID as _, IPI_EVENT_WAKEUP);
} else {
error!("hv_zone_start: cpu {} already on", boot_cpu);
return hv_result_err!(EBUSY);
};
- #[cfg(target_arch = "loongarch64")]
- {
- use crate::arch::cpu::this_cpu_id;
- // assert this is cpu 0
- let cpuid = this_cpu_id();
- assert_eq!(cpuid, 0);
- }
+ self.check_cpu_id();
add_zone(zone);
drop(_lock);
HyperCallResult::Ok(0)
@@ -361,20 +285,23 @@ impl<'a> HyperCall<'a> {
HyperCallResult::Ok(0)
}
- fn hv_zone_list(&self, zones: *mut ZoneInfo, cnt: u64) -> HyperCallResult {
+ fn hv_zone_list(&mut self, zones: *mut ZoneInfo, cnt: u64) -> HyperCallResult {
if zones.is_null() {
return hv_result_err!(EINVAL, "hv_zone_list: zones is null");
}
let zones_info = all_zones_info();
+ let zones_ipa = zones as u64;
+ let zones_pa = self.hv_get_real_pa(zones_ipa);
+ let zones = zones_pa as *mut ZoneInfo;
let slice = unsafe { core::slice::from_raw_parts_mut(zones, cnt as usize) };
- #[cfg(target_arch = "loongarch64")]
- let slice = unsafe {
- core::slice::from_raw_parts_mut(
- (zones as u64 | crate::arch::mm::LOONGARCH64_CACHED_DMW_PREFIX) as *mut ZoneInfo,
- cnt as usize,
- )
- };
+ // #[cfg(target_arch = "loongarch64")]
+ // let slice = unsafe {
+ // core::slice::from_raw_parts_mut(
+ // (zones as u64 | crate::arch::mm::LOONGARCH64_CACHED_DMW_PREFIX) as *mut ZoneInfo,
+ // cnt as usize,
+ // )
+ // };
for (i, zone_info) in slice.iter_mut().enumerate() {
if i < zones_info.len() {
@@ -383,6 +310,7 @@ impl<'a> HyperCall<'a> {
break;
}
}
+
HyperCallResult::Ok(core::cmp::min(cnt as _, zones_info.len()))
}
}
diff --git a/src/main.rs b/src/main.rs
index fa6aec9c..10f9ae27 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -46,8 +46,6 @@ extern crate log;
#[macro_use]
extern crate lazy_static;
-extern crate fdt_rs;
-
#[macro_use]
mod logging;
mod arch;
@@ -62,26 +60,20 @@ mod percpu;
mod platform;
mod zone;
-#[cfg(target_arch = "aarch64")]
-mod ivc;
-
mod pci;
#[cfg(test)]
mod tests;
-#[cfg(target_arch = "aarch64")]
-use crate::arch::mm::setup_parange;
-use crate::consts::MAX_CPU_NUM;
+use crate::arch::iommu::iommu_init;
+use crate::arch::mm::arch_setup_parange;
+use crate::consts::{hv_end, mem_pool_start, MAX_CPU_NUM};
use arch::{cpu::cpu_start, entry::arch_entry};
use config::root_zone_config;
use core::sync::atomic::{AtomicI32, AtomicU32, Ordering};
use percpu::PerCpu;
use zone::{add_zone, zone_create};
-#[cfg(all(feature = "iommu"))]
-use crate::arch::iommu::iommu_init;
-
static INITED_CPUS: AtomicU32 = AtomicU32::new(0);
static ENTERED_CPUS: AtomicU32 = AtomicU32::new(0);
static INIT_EARLY_OK: AtomicU32 = AtomicU32::new(0);
@@ -119,6 +111,8 @@ fn primary_init_early() {
logging::init();
info!("Logging is enabled.");
info!("__core_end = {:#x?}", __core_end as usize);
+ info!("mem_pool_start = {:#x?}", mem_pool_start() as usize);
+ info!("hv_end = {:#x?}", hv_end() as usize);
// let system_config = HvSystemConfig::get();
// let revision = system_config.revision;
info!("Hypervisor initialization in progress...");
@@ -133,9 +127,10 @@ fn primary_init_early() {
memory::frame::test();
event::init();
+ arch::stage2_mode_detect();
+
device::irqchip::primary_init_early();
- #[cfg(all(feature = "iommu", target_arch = "aarch64"))]
iommu_init();
#[cfg(not(test))]
@@ -155,9 +150,8 @@ fn primary_init_late() {
fn per_cpu_init(cpu: &mut PerCpu) {
if cpu.zone.is_none() {
- warn!("zone is not created for cpu {}", cpu.id);
+ warn!("CPU {} is not bound to zone0 (root zone)", cpu.id);
}
- info!("CPU {} hv_pt_install OK.", cpu.id);
}
fn wakeup_secondary_cpus(this_id: usize, host_dtb: usize) {
@@ -180,8 +174,6 @@ fn rust_main(cpuid: usize, host_dtb: usize) {
if MASTER_CPU.load(Ordering::Acquire) == -1 {
MASTER_CPU.store(cpuid as i32, Ordering::Release);
is_primary = true;
- #[cfg(target_arch = "riscv64")]
- clear_bss();
memory::heap::init();
memory::heap::test();
}
@@ -207,8 +199,9 @@ fn rust_main(cpuid: usize, host_dtb: usize) {
cpu.id
);
- #[cfg(target_arch = "aarch64")]
- setup_parange();
+ arch_setup_parange();
+ // #[cfg(target_arch = "aarch64")]
+ // setup_parange();
if is_primary {
primary_init_early(); // create root zone here
diff --git a/src/memory/frame.rs b/src/memory/frame.rs
index eb49a10b..030b3e55 100644
--- a/src/memory/frame.rs
+++ b/src/memory/frame.rs
@@ -150,10 +150,10 @@ impl Frame {
loop {
if let Ok(frame) = Frame::new_contiguous(frame_count, 0) {
if frame.start_paddr() & align_mask == 0 {
- info!(
- "new contiguous success!!! start_paddr:0x{:x}",
- frame.start_paddr()
- );
+ // info!(
+ // "new contiguous success!!! start_paddr:0x{:x}",
+ // frame.start_paddr()
+ // );
return Ok(frame);
} else {
let start_paddr = frame.start_paddr();
@@ -162,10 +162,10 @@ impl Frame {
drop(frame);
attempted_frames.push(Frame::new_contiguous(temp_frame_count, 0));
if let Ok(frame) = Frame::new_contiguous(frame_count, 0) {
- info!(
- "new contiguous success!!! start_paddr:0x{:x}",
- frame.start_paddr()
- );
+ // info!(
+ // "new contiguous success!!! start_paddr:0x{:x}",
+ // frame.start_paddr()
+ // );
return Ok(frame);
}
}
diff --git a/src/memory/mm.rs b/src/memory/mm.rs
index 164a0d61..10196366 100644
--- a/src/memory/mm.rs
+++ b/src/memory/mm.rs
@@ -73,10 +73,8 @@ where
pub fn new(pt_level: usize) -> Self {
Self {
regions: BTreeMap::new(),
- #[cfg(target_arch = "aarch64")]
+ #[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))]
pt: PT::new(pt_level),
- #[cfg(target_arch = "riscv64")]
- pt: PT::new(),
#[cfg(target_arch = "loongarch64")]
pt: PT::new(),
}
diff --git a/src/pci/pci.rs b/src/pci/pci.rs
index 52cc61d0..ac0d5ec7 100644
--- a/src/pci/pci.rs
+++ b/src/pci/pci.rs
@@ -38,10 +38,8 @@ use super::{
cfg_base, extract_reg_addr, get_bdf_shift, CFG_EXT_CAP_PTR_OFF, NUM_BAR_REGS_TYPE0,
NUM_BAR_REGS_TYPE1,
};
-
-#[cfg(all(feature = "iommu", target_arch = "aarch64"))]
+use crate::arch::consts::{BDF_SHIFT, HV_ADDR_PREFIX, LOONG_HT_PREFIX};
use crate::arch::iommu::iommu_add_device;
-
#[derive(Debug)]
pub struct PciRoot {
endpoints: Vec,
@@ -157,24 +155,20 @@ impl Zone {
num_pci_devs: usize,
alloc_pci_devs: &[u64; CONFIG_MAX_PCI_DEV],
) {
- if num_pci_devs == 0 {
+ #[cfg(not(feature = "pci"))]
+ {
+ info!("PCIe feature is not enabled, skipping PCIe initialization.");
return;
}
+ if num_pci_devs == 0 {
+ return;
+ }
info!("PCIe init!");
- let mut hv_addr_prefix: u64 = 0;
- let mut loong_ht_prefix: u64 = 0;
- let mut bdf_shift: usize = 12;
-
- #[cfg(all(target_arch = "loongarch64"))]
- {
- info!("change bdf shift to 8 for loongson");
- bdf_shift = 8;
- /* turn to virtual address and add 0xe prefix for HT accessing */
- hv_addr_prefix = 0x8000_0000_0000_0000;
- loong_ht_prefix = 0xe00_0000_0000
- }
+ let hv_addr_prefix: u64 = HV_ADDR_PREFIX;
+ let loong_ht_prefix: u64 = LOONG_HT_PREFIX;
+ let bdf_shift: usize = BDF_SHIFT;
init_bdf_shift(bdf_shift);
@@ -191,7 +185,6 @@ impl Zone {
alloc_pci_devs[idx] & 0b111
);
self.pciroot.alloc_devs.push(alloc_pci_devs[idx] as _);
- #[cfg(all(feature = "iommu", target_arch = "aarch64"))]
if alloc_pci_devs[idx] != 0 {
iommu_add_device(self.id, alloc_pci_devs[idx] as _);
}
diff --git a/src/percpu.rs b/src/percpu.rs
index 2e7c9069..b9e460af 100644
--- a/src/percpu.rs
+++ b/src/percpu.rs
@@ -16,7 +16,7 @@
use alloc::sync::Arc;
use spin::{Mutex, RwLock};
-use crate::arch::cpu::{this_cpu_id, ArchCpu};
+use crate::arch::cpu::{store_cpu_pointer_to_reg, this_cpu_id, ArchCpu};
use crate::consts::{INVALID_ADDRESS, PER_CPU_ARRAY_PTR, PER_CPU_SIZE};
use crate::memory::addr::VirtAddr;
use crate::zone::Zone;
@@ -53,14 +53,18 @@ impl PerCpu {
boot_cpu: false,
})
};
- #[cfg(target_arch = "riscv64")]
- {
- use crate::arch::csr::{write_csr, CSR_SSCRATCH};
- write_csr!(
- CSR_SSCRATCH,
- &ret.as_mut().unwrap().arch_cpu as *const _ as usize
- ); //arch cpu pointer
+ unsafe {
+ let pointer = &ret.as_mut().unwrap().arch_cpu as *const _ as usize;
+ store_cpu_pointer_to_reg(pointer);
}
+ // #[cfg(target_arch = "riscv64")]
+ // {
+ // use crate::arch::csr::{write_csr, CSR_SSCRATCH};
+ // write_csr!(
+ // CSR_SSCRATCH,
+ // &ret.as_mut().unwrap().arch_cpu as *const _ as usize
+ // ); //arch cpu pointer
+ // }
unsafe { ret.as_mut().unwrap() }
}
diff --git a/src/zone.rs b/src/zone.rs
index 0177b220..5e6483e1 100644
--- a/src/zone.rs
+++ b/src/zone.rs
@@ -24,26 +24,21 @@ use crate::arch::mm::new_s2_memory_set;
use crate::arch::s2pt::Stage2PageTable;
use crate::config::{HvZoneConfig, CONFIG_NAME_MAXLEN};
-#[cfg(all(target_arch = "riscv64", feature = "plic"))]
-use crate::device::irqchip::plic::vplic;
use crate::error::HvResult;
use crate::memory::addr::GuestPhysAddr;
use crate::memory::{MMIOConfig, MMIOHandler, MMIORegion, MemorySet};
use crate::percpu::{get_cpu_data, this_zone, CpuSet};
-#[cfg(all(feature = "plic", target_arch = "riscv64"))]
-use crate::platform::BOARD_PLIC_INTERRUPTS_NUM;
use core::panic;
pub struct Zone {
pub name: [u8; CONFIG_NAME_MAXLEN],
pub id: usize,
pub mmio: Vec,
+ pub cpu_num: usize,
pub cpu_set: CpuSet,
pub irq_bitmap: [u32; 1024 / 32],
pub gpm: MemorySet,
pub pciroot: PciRoot,
- #[cfg(all(target_arch = "riscv64", feature = "plic"))]
- pub vplic: Option,
pub is_err: bool,
}
@@ -53,13 +48,12 @@ impl Zone {
name: name.try_into().unwrap(),
id: zoneid,
gpm: new_s2_memory_set(),
+ cpu_num: 0,
cpu_set: CpuSet::new(MAX_CPU_NUM as usize, 0),
mmio: Vec::new(),
irq_bitmap: [0; 1024 / 32],
pciroot: PciRoot::new(),
is_err: false,
- #[cfg(all(target_arch = "riscv64", feature = "plic"))]
- vplic: None,
}
}
@@ -209,25 +203,26 @@ pub fn zone_create(config: &HvZoneConfig) -> HvResult>> {
let mut zone = Zone::new(zone_id, &config.name);
zone.pt_init(config.memory_regions()).unwrap();
zone.mmio_init(&config.arch_config);
- #[cfg(target_arch = "aarch64")]
- zone.ivc_init(config.ivc_config());
+
+ zone.arch_zone_configuration(config)?;
+ // #[cfg(target_arch = "aarch64")]
+ // zone.ivc_init(config.ivc_config());
/* loongarch page table emergency */
/* Kai: Maybe unnecessary but i can't boot vms on my 3A6000 PC without this function. */
- #[cfg(target_arch = "loongarch64")]
- zone.page_table_emergency(
- config.pci_config.ecam_base as _,
- config.pci_config.ecam_size as _,
- )?;
+ // #[cfg(target_arch = "loongarch64")]
+ // zone.page_table_emergency(
+ // config.pci_config.ecam_base as _,
+ // config.pci_config.ecam_size as _,
+ // )?;
- #[cfg(all(feature = "pci"))]
zone.pci_init(
&config.pci_config,
config.num_pci_devs as _,
&config.alloc_pci_devs,
);
- let mut _cpu_num = 0;
+ let mut cpu_num = 0;
for cpu_id in config.cpus().iter() {
if let Some(zone) = get_cpu_data(*cpu_id as _).zone.clone() {
@@ -241,17 +236,12 @@ pub fn zone_create(config: &HvZoneConfig) -> HvResult>> {
);
}
zone.cpu_set.set_bit(*cpu_id as _);
- _cpu_num += 1;
+ cpu_num += 1;
}
- #[cfg(feature = "plic")]
- {
- zone.vplic = Some(vplic::VirtualPLIC::new(
- config.arch_config.plic_base,
- BOARD_PLIC_INTERRUPTS_NUM,
- _cpu_num * 2,
- ));
- }
+ zone.cpu_num = cpu_num;
+ // Initialize the virtual interrupt controller, it needs zone.cpu_num
+ zone.virqc_init(config);
zone.irq_bitmap_init(config.interrupts());
@@ -278,6 +268,10 @@ pub fn zone_create(config: &HvZoneConfig) -> HvResult>> {
}
cpu_data.cpu_on_entry = config.entry_point as _;
cpu_data.dtb_ipa = dtb_ipa as _;
+ #[cfg(target_arch = "aarch64")]
+ {
+ cpu_data.arch_cpu.is_aarch32 = config.arch_config.is_aarch32 != 0;
+ }
});
}
diff --git a/vendor/fdt/.cargo-checksum.json b/vendor/fdt/.cargo-checksum.json
deleted file mode 100644
index f3c54c0d..00000000
--- a/vendor/fdt/.cargo-checksum.json
+++ /dev/null
@@ -1 +0,0 @@
-{"files":{"Cargo.lock":"22b60c6dde7117e68fa52c490094a93541a3a97ef2817ec719b14d97856b109b","Cargo.toml":"7bec39af6b4f7c8aa20e1c6e255521b27364c915b6801d6c7e7a05554289ab25","LICENSE":"633595578dcd218cd0c5e7b8d17b42480fbc830e60ef4e4506ddc6a99578693b","README.md":"befea38f057024652fb8afb650b06a183a09a9052d9c2dfb579dfd69492be732","dtb/issue-3.dtb":"009af2ed275ba2e33e8474e0697749f570aabc25512b5cf01b0c795980889c5e","dtb/sifive.dtb":"620397140fcb78ab50fa88ea9039b1dbd8359d1b4fae56e16309161d938af88c","dtb/test.dtb":"a345dc38b73355e3f2e6e3fbb0abf70f01f96b83442dcf15afd8cbb7a99aac54","dts/issue-3.dts":"23ae50d11986e1bbe4f1b60ba062db33805c48887502dec148119fcda7753190","dts/sifive.dts":"ed72adb3f198a7d394923a8658ec895e02a897f18a379703b3dcb235c5209876","dts/test.dts":"6d147709a1d9bf8dbb03ba5a49e5bf02d9131bf29a5bc6e4333bbf60d84d6b3e","examples/basic_info.rs":"9494ab25f13a1f1994d47e74fe2137b39edaa8c6db45ce7895061b6cebb79dd5","examples/tree_print.rs":"99d0051215de538b993e56ad3fadfbeb1e0db5b801aa08116d092b9745e62f7a","rustfmt.toml":"f74204a6f92aa7422a16ecb2ffe2d5bae0f123b778d08b5db1a398a3c9ca4306","src/lib.rs":"244937d5c88eb04c883d27e141846890fab72f8a4bf581af00379021c2134b61","src/node.rs":"45fe1ff721cfeadd11da517eb2a4f38013bca831ce56328c8bffa5856f908738","src/parsing.rs":"d7de682e2d29210917beb016bb672a48bb9377f3b0bd6a002cdbe5081b78dde6","src/pretty_print.rs":"46e70d0f5780a5daa0961f1f09ee6f3e1be89ddb1fb48013ce910f0e8b143e3e","src/standard_nodes.rs":"57c7f40bd2710fa42fd2583403776e5c7414ba3295e024bc2e9f5b5b62225b78","src/tests.rs":"c086298302660b93e9591c804d4eaa47cc113114a301e0766abb615d1dab167b"},"package":"784a4df722dc6267a04af36895398f59d21d07dce47232adf31ec0ff2fa45e67"}
\ No newline at end of file
diff --git a/vendor/fdt/Cargo.lock b/vendor/fdt/Cargo.lock
deleted file mode 100644
index 5314bc65..00000000
--- a/vendor/fdt/Cargo.lock
+++ /dev/null
@@ -1,7 +0,0 @@
-# This file is automatically @generated by Cargo.
-# It is not intended for manual editing.
-version = 3
-
-[[package]]
-name = "fdt"
-version = "0.1.5"
diff --git a/vendor/fdt/Cargo.toml b/vendor/fdt/Cargo.toml
deleted file mode 100644
index b57f46a5..00000000
--- a/vendor/fdt/Cargo.toml
+++ /dev/null
@@ -1,34 +0,0 @@
-# THIS FILE IS AUTOMATICALLY GENERATED BY CARGO
-#
-# When uploading crates to the registry Cargo will automatically
-# "normalize" Cargo.toml files for maximal compatibility
-# with all versions of Cargo and also rewrite `path` dependencies
-# to registry (e.g., crates.io) dependencies.
-#
-# If you are reading this file be aware that the original Cargo.toml
-# will likely look very different (and much more reasonable).
-# See Cargo.toml.orig for the original contents.
-
-[package]
-edition = "2018"
-name = "fdt"
-version = "0.1.5"
-authors = ["Wesley Norris "]
-description = "A pure-Rust `#![no_std]` crate for parsing Flattened Devicetrees"
-readme = "README.md"
-keywords = [
- "devicetree",
- "fdt",
- "dt",
-]
-categories = [
- "embedded",
- "no-std",
-]
-license = "MPL-2.0"
-repository = "https://github.com/repnop/fdt"
-
-[dependencies]
-
-[features]
-pretty-printing = []
diff --git a/vendor/fdt/LICENSE b/vendor/fdt/LICENSE
deleted file mode 100644
index f6dda5a0..00000000
--- a/vendor/fdt/LICENSE
+++ /dev/null
@@ -1,343 +0,0 @@
-Mozilla Public License Version 2.0
-
-1. Definitions
-
-1.1. “Contributor”
-
- means each individual or legal entity that creates, contributes to the
- creation of, or owns Covered Software.
-
-1.2. “Contributor Version”
-
- means the combination of the Contributions of others (if any) used by a
- Contributor and that particular Contributor’s Contribution.
-
-1.3. “Contribution”
-
- means Covered Software of a particular Contributor.
-
-1.4. “Covered Software”
-
- means Source Code Form to which the initial Contributor has attached the
- notice in Exhibit A, the Executable Form of such Source Code Form, and
- Modifications of such Source Code Form, in each case including portions
- thereof.
-
-1.5. “Incompatible With Secondary Licenses”
-
- means that the initial Contributor has attached the notice described in
- Exhibit B to the Covered Software; or
-
- that the Covered Software was made available under the terms of version 1.1
- or earlier of the License, but not also under the terms of a Secondary
- License.
-
-1.6. “Executable Form”
-
- means any form of the work other than Source Code Form.
-
-1.7. “Larger Work”
-
- means a work that combines Covered Software with other material, in a
- separate file or files, that is not Covered Software.
-
-1.8. “License”
-
- means this document.
-
-1.9. “Licensable”
-
- means having the right to grant, to the maximum extent possible, whether at
- the time of the initial grant or subsequently, any and all of the rights
- conveyed by this License.
-
-1.10. “Modifications”
-
- means any of the following:
-
- any file in Source Code Form that results from an addition to, deletion
- from, or modification of the contents of Covered Software; or
-
- any new file in Source Code Form that contains any Covered Software.
-
-1.11. “Patent Claims” of a Contributor
-
- means any patent claim(s), including without limitation, method, process,
- and apparatus claims, in any patent Licensable by such Contributor that
- would be infringed, but for the grant of the License, by the making, using,
- selling, offering for sale, having made, import, or transfer of either its
- Contributions or its Contributor Version.
-
-1.12. “Secondary License”
-
- means either the GNU General Public License, Version 2.0, the GNU Lesser
- General Public License, Version 2.1, the GNU Affero General Public License,
- Version 3.0, or any later versions of those licenses.
-
-1.13. “Source Code Form”
-
- means the form of the work preferred for making modifications.
-
-1.14. “You” (or “Your”)
-
- means an individual or a legal entity exercising rights under this License.
- For legal entities, “You” includes any entity that controls, is controlled
- by, or is under common control with You. For purposes of this definition,
- “control” means (a) the power, direct or indirect, to cause the direction or
- management of such entity, whether by contract or otherwise, or (b)
- ownership of more than fifty percent (50%) of the outstanding shares or
- beneficial ownership of such entity.
-
-2. License Grants and Conditions
-
- 2.1. Grants
-
- Each Contributor hereby grants You a world-wide, royalty-free, non-exclusive
- license:
-
- under intellectual property rights (other than patent or trademark)
- Licensable by such Contributor to use, reproduce, make available, modify,
- display, perform, distribute, and otherwise exploit its Contributions,
- either on an unmodified basis, with Modifications, or as part of a Larger
- Work; and
-
- under Patent Claims of such Contributor to make, use, sell, offer for sale,
- have made, import, and otherwise transfer either its Contributions or its
- Contributor Version.
-
- 2.2. Effective Date
-
- The licenses granted in Section 2.1 with respect to any Contribution become
- effective for each Contribution on the date the Contributor first distributes
- such Contribution.
-
- 2.3. Limitations on Grant Scope
-
- The licenses granted in this Section 2 are the only rights granted under this
- License. No additional rights or licenses will be implied from the distribution
- or licensing of Covered Software under this License. Notwithstanding Section
- 2.1(b) above, no patent license is granted by a Contributor:
-
- for any code that a Contributor has removed from Covered Software; or
-
- for infringements caused by: (i) Your and any other third party’s
- modifications of Covered Software, or (ii) the combination of its
- Contributions with other software (except as part of its Contributor
- Version); or
-
- under Patent Claims infringed by Covered Software in the absence of its
- Contributions.
-
- This License does not grant any rights in the trademarks, service marks, or
- logos of any Contributor (except as may be necessary to comply with the notice
- requirements in Section 3.4).
-
- 2.4. Subsequent Licenses
-
- No Contributor makes additional grants as a result of Your choice to distribute
- the Covered Software under a subsequent version of this License (see Section
- 10.2) or under the terms of a Secondary License (if permitted under the terms of
- Section 3.3).
-
- 2.5. Representation
-
- Each Contributor represents that the Contributor believes its Contributions are
- its original creation(s) or it has sufficient rights to grant the rights to its
- Contributions conveyed by this License.
-
- 2.6. Fair Use
-
- This License is not intended to limit any rights You have under applicable
- copyright doctrines of fair use, fair dealing, or other equivalents.
-
- 2.7. Conditions
-
- Sections 3.1, 3.2, 3.3, and 3.4 are conditions of the licenses granted in
- Section 2.1.
-
-3. Responsibilities
-
- 3.1. Distribution of Source Form
-
- All distribution of Covered Software in Source Code Form, including any
- Modifications that You create or to which You contribute, must be under the
- terms of this License. You must inform recipients that the Source Code Form of
- the Covered Software is governed by the terms of this License, and how they can
- obtain a copy of this License. You may not attempt to alter or restrict the
- recipients’ rights in the Source Code Form.
-
- 3.2. Distribution of Executable Form
-
- If You distribute Covered Software in Executable Form then:
-
- such Covered Software must also be made available in Source Code Form, as
- described in Section 3.1, and You must inform recipients of the Executable
- Form how they can obtain a copy of such Source Code Form by reasonable means
- in a timely manner, at a charge no more than the cost of distribution to the
- recipient; and
-
- You may distribute such Executable Form under the terms of this License, or
- sublicense it under different terms, provided that the license for the
- Executable Form does not attempt to limit or alter the recipients’ rights in
- the Source Code Form under this License.
-
- 3.3. Distribution of a Larger Work
-
- You may create and distribute a Larger Work under terms of Your choice, provided
- that You also comply with the requirements of this License for the Covered
- Software. If the Larger Work is a combination of Covered Software with a work
- governed by one or more Secondary Licenses, and the Covered Software is not
- Incompatible With Secondary Licenses, this License permits You to additionally
- distribute such Covered Software under the terms of such Secondary License(s),
- so that the recipient of the Larger Work may, at their option, further
- distribute the Covered Software under the terms of either this License or such
- Secondary License(s).
-
- 3.4. Notices
-
- You may not remove or alter the substance of any license notices (including
- copyright notices, patent notices, disclaimers of warranty, or limitations of
- liability) contained within the Source Code Form of the Covered Software, except
- that You may alter any license notices to the extent required to remedy known
- factual inaccuracies.
-
- 3.5. Application of Additional Terms
-
- You may choose to offer, and to charge a fee for, warranty, support, indemnity
- or liability obligations to one or more recipients of Covered Software. However,
- You may do so only on Your own behalf, and not on behalf of any Contributor. You
- must make it absolutely clear that any such warranty, support, indemnity, or
- liability obligation is offered by You alone, and You hereby agree to indemnify
- every Contributor for any liability incurred by such Contributor as a result of
- warranty, support, indemnity or liability terms You offer. You may include
- additional disclaimers of warranty and limitations of liability specific to any
- jurisdiction.
-
-4. Inability to Comply Due to Statute or Regulation
-
- If it is impossible for You to comply with any of the terms of this License with
- respect to some or all of the Covered Software due to statute, judicial order,
- or regulation then You must: (a) comply with the terms of this License to the
- maximum extent possible; and (b) describe the limitations and the code they
- affect. Such description must be placed in a text file included with all
- distributions of the Covered Software under this License. Except to the extent
- prohibited by statute or regulation, such description must be sufficiently
- detailed for a recipient of ordinary skill to be able to understand it.
-
-5. Termination
-
- 5.1. The rights granted under this License will terminate automatically if You
- fail to comply with any of its terms. However, if You become compliant, then the
- rights granted under this License from a particular Contributor are reinstated
- (a) provisionally, unless and until such Contributor explicitly and finally
- terminates Your grants, and (b) on an ongoing basis, if such Contributor fails
- to notify You of the non-compliance by some reasonable means prior to 60 days
- after You have come back into compliance. Moreover, Your grants from a
- particular Contributor are reinstated on an ongoing basis if such Contributor
- notifies You of the non-compliance by some reasonable means, this is the first
- time You have received notice of non-compliance with this License from such
- Contributor, and You become compliant prior to 30 days after Your receipt of the
- notice.
-
- 5.2. If You initiate litigation against any entity by asserting a patent
- infringement claim (excluding declaratory judgment actions, counter-claims, and
- cross-claims) alleging that a Contributor Version directly or indirectly
- infringes any patent, then the rights granted to You by any and all Contributors
- for the Covered Software under Section 2.1 of this License shall terminate.
-
- 5.3. In the event of termination under Sections 5.1 or 5.2 above, all end user
- license agreements (excluding distributors and resellers) which have been
- validly granted by You or Your distributors under this License prior to
- termination shall survive termination.
-
-6. Disclaimer of Warranty
-
- Covered Software is provided under this License on an “as is” basis, without
- warranty of any kind, either expressed, implied, or statutory, including,
- without limitation, warranties that the Covered Software is free of defects,
- merchantable, fit for a particular purpose or non-infringing. The entire risk as
- to the quality and performance of the Covered Software is with You. Should any
- Covered Software prove defective in any respect, You (not any Contributor)
- assume the cost of any necessary servicing, repair, or correction. This
- disclaimer of warranty constitutes an essential part of this License. No use of
- any Covered Software is authorized under this License except under this
- disclaimer.
-
-7. Limitation of Liability
-
- Under no circumstances and under no legal theory, whether tort (including
- negligence), contract, or otherwise, shall any Contributor, or anyone who
- distributes Covered Software as permitted above, be liable to You for any
- direct, indirect, special, incidental, or consequential damages of any character
- including, without limitation, damages for lost profits, loss of goodwill, work
- stoppage, computer failure or malfunction, or any and all other commercial
- damages or losses, even if such party shall have been informed of the
- possibility of such damages. This limitation of liability shall not apply to
- liability for death or personal injury resulting from such party’s negligence to
- the extent applicable law prohibits such limitation. Some jurisdictions do not
- allow the exclusion or limitation of incidental or consequential damages, so
- this exclusion and limitation may not apply to You.
-
-8. Litigation
-
- Any litigation relating to this License may be brought only in the courts of a
- jurisdiction where the defendant maintains its principal place of business and
- such litigation shall be governed by laws of that jurisdiction, without
- reference to its conflict-of-law provisions. Nothing in this Section shall
- prevent a party’s ability to bring cross-claims or counter-claims.
-
-9. Miscellaneous
-
- This License represents the complete agreement concerning the subject matter
- hereof. If any provision of this License is held to be unenforceable, such
- provision shall be reformed only to the extent necessary to make it enforceable.
- Any law or regulation which provides that the language of a contract shall be
- construed against the drafter shall not be used to construe this License against
- a Contributor.
-
-10. Versions of the License
-
- 10.1. New Versions
-
- Mozilla Foundation is the license steward. Except as provided in Section 10.3,
- no one other than the license steward has the right to modify or publish new
- versions of this License. Each version will be given a distinguishing version
- number.
-
- 10.2. Effect of New Versions
-
- You may distribute the Covered Software under the terms of the version of the
- License under which You originally received the Covered Software, or under the
- terms of any subsequent version published by the license steward.
-
- 10.3. Modified Versions
-
- If you create software not governed by this License, and you want to create a
- new license for such software, you may create and use a modified version of this
- License if you rename the license and remove any references to the name of the
- license steward (except to note that such modified license differs from this
- License).
-
- 10.4. Distributing Source Code Form that is Incompatible With Secondary Licenses
-
- If You choose to distribute Source Code Form that is Incompatible With Secondary
- Licenses under the terms of this version of the License, the notice described in
- Exhibit B of this License must be attached.
-
- Exhibit A - Source Code Form License Notice
-
- This Source Code Form is subject to the terms of the Mozilla Public License,
- v. 2.0. If a copy of the MPL was not distributed with this file, You can
- obtain one at https://mozilla.org/MPL/2.0/.
-
- If it is not possible or desirable to put the notice in a particular file, then
- You may include the notice in a location (such as a LICENSE file in a relevant
- directory) where a recipient would be likely to look for such a notice.
-
- You may add additional accurate notices of copyright ownership.
-
- Exhibit B - “Incompatible With Secondary Licenses” Notice
-
- This Source Code Form is “Incompatible With Secondary Licenses”, as defined
- by the Mozilla Public License, v. 2.0.
-
diff --git a/vendor/fdt/README.md b/vendor/fdt/README.md
deleted file mode 100644
index 23991103..00000000
--- a/vendor/fdt/README.md
+++ /dev/null
@@ -1,46 +0,0 @@
-# `fdt`
-
-A pure-Rust `#![no_std]` crate for parsing Flattened Devicetrees, with the goal of having a
-very ergonomic and idiomatic API.
-
-[](https://crates.io/crates/fdt) [](https://docs.rs/fdt) 
-
-## License
-
-This crate is licensed under the Mozilla Public License 2.0 (see the LICENSE file).
-
-## Example
-
-```rust
-static MY_FDT: &[u8] = include_bytes!("../dtb/test.dtb");
-
-fn main() {
- let fdt = fdt::Fdt::new(MY_FDT).unwrap();
-
- println!("This is a devicetree representation of a {}", fdt.root().model());
- println!("...which is compatible with at least: {}", fdt.root().compatible().first());
- println!("...and has {} CPU(s)", fdt.cpus().count());
- println!(
- "...and has at least one memory location at: {:#X}\n",
- fdt.memory().regions().next().unwrap().starting_address as usize
- );
-
- let chosen = fdt.chosen();
- if let Some(bootargs) = chosen.bootargs() {
- println!("The bootargs are: {:?}", bootargs);
- }
-
- if let Some(stdout) = chosen.stdout() {
- println!("It would write stdout to: {}", stdout.name);
- }
-
- let soc = fdt.find_node("/soc");
- println!("Does it have a `/soc` node? {}", if soc.is_some() { "yes" } else { "no" });
- if let Some(soc) = soc {
- println!("...and it has the following children:");
- for child in soc.children() {
- println!(" {}", child.name);
- }
- }
-}
-```
\ No newline at end of file
diff --git a/vendor/fdt/dts/issue-3.dts b/vendor/fdt/dts/issue-3.dts
deleted file mode 100644
index cd8343cc..00000000
--- a/vendor/fdt/dts/issue-3.dts
+++ /dev/null
@@ -1,250 +0,0 @@
-/dts-v1/;
-
-/ {
- #address-cells = <0x02>;
- #size-cells = <0x02>;
- compatible = "riscv-virtio";
- model = "riscv-virtio,qemu";
-
- chosen {
- bootargs = [00];
- stdout-path = "/soc/uart@10000000";
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x00 0x80000000 0x00 0x8000000>;
- };
-
- cpus {
- #address-cells = <0x01>;
- #size-cells = <0x00>;
- timebase-frequency = <0x989680>;
-
- cpu@0 {
- phandle = <0x07>;
- device_type = "cpu";
- reg = <0x00>;
- status = "okay";
- compatible = "riscv";
- riscv,isa = "rv64imafdcsu";
- mmu-type = "riscv,sv48";
-
- interrupt-controller {
- #interrupt-cells = <0x01>;
- interrupt-controller;
- compatible = "riscv,cpu-intc";
- phandle = <0x08>;
- };
- };
-
- cpu@1 {
- phandle = <0x05>;
- device_type = "cpu";
- reg = <0x01>;
- status = "okay";
- compatible = "riscv";
- riscv,isa = "rv64imafdcsu";
- mmu-type = "riscv,sv48";
-
- interrupt-controller {
- #interrupt-cells = <0x01>;
- interrupt-controller;
- compatible = "riscv,cpu-intc";
- phandle = <0x06>;
- };
- };
-
- cpu@2 {
- phandle = <0x03>;
- device_type = "cpu";
- reg = <0x02>;
- status = "okay";
- compatible = "riscv";
- riscv,isa = "rv64imafdcsu";
- mmu-type = "riscv,sv48";
-
- interrupt-controller {
- #interrupt-cells = <0x01>;
- interrupt-controller;
- compatible = "riscv,cpu-intc";
- phandle = <0x04>;
- };
- };
-
- cpu@3 {
- phandle = <0x01>;
- device_type = "cpu";
- reg = <0x03>;
- status = "okay";
- compatible = "riscv";
- riscv,isa = "rv64imafdcsu";
- mmu-type = "riscv,sv48";
-
- interrupt-controller {
- #interrupt-cells = <0x01>;
- interrupt-controller;
- compatible = "riscv,cpu-intc";
- phandle = <0x02>;
- };
- };
-
- cpu-map {
-
- cluster0 {
-
- core0 {
- cpu = <0x07>;
- };
-
- core1 {
- cpu = <0x05>;
- };
-
- core2 {
- cpu = <0x03>;
- };
-
- core3 {
- cpu = <0x01>;
- };
- };
- };
- };
-
- soc {
- #address-cells = <0x02>;
- #size-cells = <0x02>;
- compatible = "simple-bus";
- ranges;
-
- flash@20000000 {
- bank-width = <0x04>;
- reg = <0x00 0x20000000 0x00 0x2000000 0x00 0x22000000 0x00 0x2000000>;
- compatible = "cfi-flash";
- };
-
- rtc@101000 {
- interrupts = <0x0b>;
- interrupt-parent = <0x09>;
- reg = <0x00 0x101000 0x00 0x1000>;
- compatible = "google,goldfish-rtc";
- };
-
- uart@10000000 {
- interrupts = <0x0a>;
- interrupt-parent = <0x09>;
- clock-frequency = <0x384000>;
- reg = <0x00 0x10000000 0x00 0x100>;
- compatible = "ns16550a";
- };
-
- poweroff {
- value = <0x5555>;
- offset = <0x00>;
- regmap = <0x0a>;
- compatible = "syscon-poweroff";
- };
-
- reboot {
- value = <0x7777>;
- offset = <0x00>;
- regmap = <0x0a>;
- compatible = "syscon-reboot";
- };
-
- test@100000 {
- phandle = <0x0a>;
- reg = <0x00 0x100000 0x00 0x1000>;
- compatible = "sifive,test1\0sifive,test0\0syscon";
- };
-
- pci@30000000 {
- interrupt-map-mask = <0x1800 0x00 0x00 0x07>;
- interrupt-map = <0x00 0x00 0x00 0x01 0x09 0x20 0x00 0x00 0x00 0x02 0x09 0x21 0x00 0x00 0x00 0x03 0x09 0x22 0x00 0x00 0x00 0x04 0x09 0x23 0x800 0x00 0x00 0x01 0x09 0x21 0x800 0x00 0x00 0x02 0x09 0x22 0x800 0x00 0x00 0x03 0x09 0x23 0x800 0x00 0x00 0x04 0x09 0x20 0x1000 0x00 0x00 0x01 0x09 0x22 0x1000 0x00 0x00 0x02 0x09 0x23 0x1000 0x00 0x00 0x03 0x09 0x20 0x1000 0x00 0x00 0x04 0x09 0x21 0x1800 0x00 0x00 0x01 0x09 0x23 0x1800 0x00 0x00 0x02 0x09 0x20 0x1800 0x00 0x00 0x03 0x09 0x21 0x1800 0x00 0x00 0x04 0x09 0x22>;
- ranges = <0x1000000 0x00 0x00 0x00 0x3000000 0x00 0x10000 0x2000000 0x00 0x40000000 0x00 0x40000000 0x00 0x40000000>;
- reg = <0x00 0x30000000 0x00 0x10000000>;
- dma-coherent;
- bus-range = <0x00 0xff>;
- linux,pci-domain = <0x00>;
- device_type = "pci";
- compatible = "pci-host-ecam-generic";
- #size-cells = <0x02>;
- #interrupt-cells = <0x01>;
- #address-cells = <0x03>;
- };
-
- virtio_mmio@10008000 {
- interrupts = <0x08>;
- interrupt-parent = <0x09>;
- reg = <0x00 0x10008000 0x00 0x1000>;
- compatible = "virtio,mmio";
- };
-
- virtio_mmio@10007000 {
- interrupts = <0x07>;
- interrupt-parent = <0x09>;
- reg = <0x00 0x10007000 0x00 0x1000>;
- compatible = "virtio,mmio";
- };
-
- virtio_mmio@10006000 {
- interrupts = <0x06>;
- interrupt-parent = <0x09>;
- reg = <0x00 0x10006000 0x00 0x1000>;
- compatible = "virtio,mmio";
- };
-
- virtio_mmio@10005000 {
- interrupts = <0x05>;
- interrupt-parent = <0x09>;
- reg = <0x00 0x10005000 0x00 0x1000>;
- compatible = "virtio,mmio";
- };
-
- virtio_mmio@10004000 {
- interrupts = <0x04>;
- interrupt-parent = <0x09>;
- reg = <0x00 0x10004000 0x00 0x1000>;
- compatible = "virtio,mmio";
- };
-
- virtio_mmio@10003000 {
- interrupts = <0x03>;
- interrupt-parent = <0x09>;
- reg = <0x00 0x10003000 0x00 0x1000>;
- compatible = "virtio,mmio";
- };
-
- virtio_mmio@10002000 {
- interrupts = <0x02>;
- interrupt-parent = <0x09>;
- reg = <0x00 0x10002000 0x00 0x1000>;
- compatible = "virtio,mmio";
- };
-
- virtio_mmio@10001000 {
- interrupts = <0x01>;
- interrupt-parent = <0x09>;
- reg = <0x00 0x10001000 0x00 0x1000>;
- compatible = "virtio,mmio";
- };
-
- plic@c000000 {
- phandle = <0x09>;
- riscv,ndev = <0x35>;
- reg = <0x00 0xc000000 0x00 0x210000>;
- interrupts-extended = <0x08 0x0b 0x08 0x09 0x06 0x0b 0x06 0x09 0x04 0x0b 0x04 0x09 0x02 0x0b 0x02 0x09>;
- interrupt-controller;
- compatible = "riscv,plic0";
- #interrupt-cells = <0x01>;
- #address-cells = <0x00>;
- };
-
- clint@2000000 {
- interrupts-extended = <0x08 0x03 0x08 0x07 0x06 0x03 0x06 0x07 0x04 0x03 0x04 0x07 0x02 0x03 0x02 0x07>;
- reg = <0x00 0x2000000 0x00 0x10000>;
- compatible = "riscv,clint0";
- };
- };
-};
\ No newline at end of file
diff --git a/vendor/fdt/dts/sifive.dts b/vendor/fdt/dts/sifive.dts
deleted file mode 100644
index e24fcfc8..00000000
--- a/vendor/fdt/dts/sifive.dts
+++ /dev/null
@@ -1,207 +0,0 @@
-/dts-v1/;
-
-/ {
- #address-cells = <0x02>;
- #size-cells = <0x02>;
- compatible = "sifive,hifive-unleashed-a00";
- model = "SiFive HiFive Unleashed A00";
-
- chosen {
- bootargs = [00];
- stdout-path = "/soc/serial@10010000";
- };
-
- aliases {
- serial0 = "/soc/serial@10010000";
- ethernet0 = "/soc/ethernet@10090000";
- };
-
- gpio-restart {
- compatible = "gpio-restart";
- gpios = <0x0a 0x0a 0x01>;
- };
-
- cpus {
- #address-cells = <0x01>;
- #size-cells = <0x00>;
- timebase-frequency = <0x989680>;
-
- cpu@0 {
- device_type = "cpu";
- reg = <0x00>;
- status = "okay";
- compatible = "riscv";
- riscv,isa = "rv64imacu";
-
- interrupt-controller {
- #interrupt-cells = <0x01>;
- interrupt-controller;
- compatible = "riscv,cpu-intc";
- phandle = <0x07>;
- };
- };
-
- cpu@1 {
- device_type = "cpu";
- reg = <0x01>;
- status = "okay";
- compatible = "riscv";
- riscv,isa = "rv64imafdcsu";
- mmu-type = "riscv,sv48";
-
- interrupt-controller {
- #interrupt-cells = <0x01>;
- interrupt-controller;
- compatible = "riscv,cpu-intc";
- phandle = <0x06>;
- };
- };
-
- cpu@2 {
- device_type = "cpu";
- reg = <0x02>;
- status = "okay";
- compatible = "riscv";
- riscv,isa = "rv64imafdcsu";
- mmu-type = "riscv,sv48";
-
- interrupt-controller {
- #interrupt-cells = <0x01>;
- interrupt-controller;
- compatible = "riscv,cpu-intc";
- phandle = <0x05>;
- };
- };
-
- cpu@3 {
- device_type = "cpu";
- reg = <0x03>;
- status = "okay";
- compatible = "riscv";
- riscv,isa = "rv64imafdcsu";
- mmu-type = "riscv,sv48";
-
- interrupt-controller {
- #interrupt-cells = <0x01>;
- interrupt-controller;
- compatible = "riscv,cpu-intc";
- phandle = <0x04>;
- };
- };
-
- cpu@4 {
- device_type = "cpu";
- reg = <0x04>;
- status = "okay";
- compatible = "riscv";
- riscv,isa = "rv64imafdcsu";
- mmu-type = "riscv,sv48";
-
- interrupt-controller {
- #interrupt-cells = <0x01>;
- interrupt-controller;
- compatible = "riscv,cpu-intc";
- phandle = <0x03>;
- };
- };
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x00 0x80000000 0x00 0x20000000>;
- };
-
- rtcclk {
- #clock-cells = <0x00>;
- compatible = "fixed-clock";
- clock-frequency = <0xf4240>;
- clock-output-names = "rtcclk";
- phandle = <0x02>;
- };
-
- hfclk {
- #clock-cells = <0x00>;
- compatible = "fixed-clock";
- clock-frequency = <0x1fca055>;
- clock-output-names = "hfclk";
- phandle = <0x01>;
- };
-
- soc {
- #address-cells = <0x02>;
- #size-cells = <0x02>;
- compatible = "simple-bus";
- ranges;
-
- serial@10010000 {
- interrupts = <0x04>;
- interrupt-parent = <0x09>;
- clocks = <0x08 0x03>;
- reg = <0x00 0x10010000 0x00 0x1000>;
- compatible = "sifive,uart0";
- };
-
- ethernet@10090000 {
- #size-cells = <0x00>;
- #address-cells = <0x01>;
- local-mac-address = [52 54 00 12 34 56];
- clock-names = "pclk\0hclk";
- clocks = <0x08 0x02 0x08 0x02>;
- interrupts = <0x35>;
- interrupt-parent = <0x09>;
- phy-handle = <0x0b>;
- phy-mode = "gmii";
- reg-names = "control";
- reg = <0x00 0x10090000 0x00 0x2000 0x00 0x100a0000 0x00 0x1000>;
- compatible = "sifive,fu540-c000-gem";
-
- ethernet-phy@0 {
- reg = <0x00>;
- phandle = <0x0b>;
- };
- };
-
- gpio@10060000 {
- compatible = "sifive,gpio0";
- interrupt-parent = <0x09>;
- interrupts = <0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16>;
- reg = <0x00 0x10060000 0x00 0x1000>;
- gpio-controller;
- #gpio-cells = <0x02>;
- interrupt-controller;
- #interrupt-cells = <0x02>;
- clocks = <0x08 0x03>;
- phandle = <0x0a>;
- };
-
- interrupt-controller@c000000 {
- phandle = <0x09>;
- riscv,ndev = <0x35>;
- reg = <0x00 0xc000000 0x00 0x4000000>;
- interrupts-extended = <0x07 0x0b 0x06 0x0b 0x06 0x09 0x05 0x0b 0x05 0x09 0x04 0x0b 0x04 0x09 0x03 0x0b 0x03 0x09>;
- interrupt-controller;
- compatible = "riscv,plic0";
- #interrupt-cells = <0x01>;
- };
-
- clock-controller@10000000 {
- compatible = "sifive,fu540-c000-prci";
- reg = <0x00 0x10000000 0x00 0x1000>;
- clocks = <0x01 0x02>;
- #clock-cells = <0x01>;
- phandle = <0x08>;
- };
-
- otp@10070000 {
- compatible = "sifive,fu540-c000-otp";
- reg = <0x00 0x10070000 0x00 0x1000>;
- fuse-count = <0x1000>;
- };
-
- clint@2000000 {
- interrupts-extended = <0x07 0x03 0x07 0x07 0x06 0x03 0x06 0x07 0x05 0x03 0x05 0x07 0x04 0x03 0x04 0x07 0x03 0x03 0x03 0x07>;
- reg = <0x00 0x2000000 0x00 0x10000>;
- compatible = "riscv,clint0";
- };
- };
-};
diff --git a/vendor/fdt/dts/test.dts b/vendor/fdt/dts/test.dts
deleted file mode 100644
index 46d25ba5..00000000
--- a/vendor/fdt/dts/test.dts
+++ /dev/null
@@ -1,191 +0,0 @@
-/dts-v1/;
-
-/ {
- #address-cells = <0x02>;
- #size-cells = <0x02>;
- compatible = "riscv-virtio";
- model = "riscv-virtio,qemu";
-
- chosen {
- bootargs = [00];
- stdout-path = "/soc/uart@10000000";
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x00 0x80000000 0x00 0x20000000>;
- };
-
- cpus {
- #address-cells = <0x01>;
- #size-cells = <0x00>;
- timebase-frequency = <0x989680>;
-
- cpu@0 {
- phandle = <0x01>;
- device_type = "cpu";
- reg = <0x00>;
- status = "okay";
- compatible = "riscv";
- riscv,isa = "rv64imafdcsu";
- mmu-type = "riscv,sv48";
-
- interrupt-controller {
- #interrupt-cells = <0x01>;
- interrupt-controller;
- compatible = "riscv,cpu-intc";
- phandle = <0x02>;
- };
- };
-
- cpu-map {
-
- cluster0 {
-
- core0 {
- cpu = <0x01>;
- };
- };
- };
- };
-
- emptyproptest {
-
- };
-
- soc {
- #address-cells = <0x02>;
- #size-cells = <0x02>;
- compatible = "simple-bus";
- ranges;
-
- flash@20000000 {
- bank-width = <0x04>;
- reg = <0x00 0x20000000 0x00 0x2000000 0x00 0x22000000 0x00 0x2000000>;
- compatible = "cfi-flash";
- };
-
- rtc@101000 {
- interrupts = <0x0b>;
- interrupt-parent = <0x03>;
- reg = <0x00 0x101000 0x00 0x1000>;
- compatible = "google,goldfish-rtc";
- };
-
- uart@10000000 {
- interrupts = <0x0a>;
- interrupt-parent = <0x03>;
- clock-frequency = <0x384000>;
- reg = <0x00 0x10000000 0x00 0x100>;
- compatible = "ns16550a";
- };
-
- poweroff {
- value = <0x5555>;
- offset = <0x00>;
- regmap = <0x04>;
- compatible = "syscon-poweroff";
- };
-
- reboot {
- value = <0x7777>;
- offset = <0x00>;
- regmap = <0x04>;
- compatible = "syscon-reboot";
- };
-
- test@100000 {
- phandle = <0x04>;
- reg = <0x00 0x100000 0x00 0x1000>;
- compatible = "sifive,test1\0sifive,test0\0syscon";
- };
-
- pci@30000000 {
- interrupt-map-mask = <0x1800 0x00 0x00 0x07>;
- interrupt-map = <0x00 0x00 0x00 0x01 0x03 0x20 0x00 0x00 0x00 0x02 0x03 0x21 0x00 0x00 0x00 0x03 0x03 0x22 0x00 0x00 0x00 0x04 0x03 0x23 0x800 0x00 0x00 0x01 0x03 0x21 0x800 0x00 0x00 0x02 0x03 0x22 0x800 0x00 0x00 0x03 0x03 0x23 0x800 0x00 0x00 0x04 0x03 0x20 0x1000 0x00 0x00 0x01 0x03 0x22 0x1000 0x00 0x00 0x02 0x03 0x23 0x1000 0x00 0x00 0x03 0x03 0x20 0x1000 0x00 0x00 0x04 0x03 0x21 0x1800 0x00 0x00 0x01 0x03 0x23 0x1800 0x00 0x00 0x02 0x03 0x20 0x1800 0x00 0x00 0x03 0x03 0x21 0x1800 0x00 0x00 0x04 0x03 0x22>;
- ranges = <0x1000000 0x00 0x00 0x00 0x3000000 0x00 0x10000 0x2000000 0x00 0x40000000 0x00 0x40000000 0x00 0x40000000>;
- reg = <0x00 0x30000000 0x00 0x10000000>;
- dma-coherent;
- bus-range = <0x00 0xff>;
- linux,pci-domain = <0x00>;
- device_type = "pci";
- compatible = "pci-host-ecam-generic";
- #size-cells = <0x02>;
- #interrupt-cells = <0x01>;
- #address-cells = <0x03>;
- };
-
- virtio_mmio@10008000 {
- interrupts = <0x08>;
- interrupt-parent = <0x03>;
- reg = <0x00 0x10008000 0x00 0x1000>;
- compatible = "virtio,mmio";
- };
-
- virtio_mmio@10007000 {
- interrupts = <0x07>;
- interrupt-parent = <0x03>;
- reg = <0x00 0x10007000 0x00 0x1000>;
- compatible = "virtio,mmio";
- };
-
- virtio_mmio@10006000 {
- interrupts = <0x06>;
- interrupt-parent = <0x03>;
- reg = <0x00 0x10006000 0x00 0x1000>;
- compatible = "virtio,mmio";
- };
-
- virtio_mmio@10005000 {
- interrupts = <0x05>;
- interrupt-parent = <0x03>;
- reg = <0x00 0x10005000 0x00 0x1000>;
- compatible = "virtio,mmio";
- };
-
- virtio_mmio@10004000 {
- interrupts = <0x04>;
- interrupt-parent = <0x03>;
- reg = <0x00 0x10004000 0x00 0x1000>;
- compatible = "virtio,mmio";
- };
-
- virtio_mmio@10003000 {
- interrupts = <0x03>;
- interrupt-parent = <0x03>;
- reg = <0x00 0x10003000 0x00 0x1000>;
- compatible = "virtio,mmio";
- };
-
- virtio_mmio@10002000 {
- interrupts = <0x02>;
- interrupt-parent = <0x03>;
- reg = <0x00 0x10002000 0x00 0x1000>;
- compatible = "virtio,mmio";
- };
-
- virtio_mmio@10001000 {
- interrupts = <0x01>;
- interrupt-parent = <0x03>;
- reg = <0x00 0x10001000 0x00 0x1000>;
- compatible = "virtio,mmio";
- };
-
- plic@c000000 {
- phandle = <0x03>;
- riscv,ndev = <0x35>;
- reg = <0x00 0xc000000 0x00 0x210000>;
- interrupts-extended = <0x02 0x0b 0x02 0x09>;
- interrupt-controller;
- compatible = "riscv,plic0";
- #interrupt-cells = <0x01>;
- #address-cells = <0x00>;
- };
-
- clint@2000000 {
- interrupts-extended = <0x02 0x03 0x02 0x07>;
- reg = <0x00 0x2000000 0x00 0x10000>;
- compatible = "riscv,clint0";
- };
- };
-};
diff --git a/vendor/fdt/examples/basic_info.rs b/vendor/fdt/examples/basic_info.rs
deleted file mode 100644
index bb91570a..00000000
--- a/vendor/fdt/examples/basic_info.rs
+++ /dev/null
@@ -1,31 +0,0 @@
-static MY_FDT: &[u8] = include_bytes!("../dtb/test.dtb");
-
-fn main() {
- let fdt = fdt::Fdt::new(MY_FDT).unwrap();
-
- println!("This is a devicetree representation of a {}", fdt.root().model());
- println!("...which is compatible with at least: {}", fdt.root().compatible().first());
- println!("...and has {} CPU(s)", fdt.cpus().count());
- println!(
- "...and has at least one memory location at: {:#X}\n",
- fdt.memory().regions().next().unwrap().starting_address as usize
- );
-
- let chosen = fdt.chosen();
- if let Some(bootargs) = chosen.bootargs() {
- println!("The bootargs are: {:?}", bootargs);
- }
-
- if let Some(stdout) = chosen.stdout() {
- println!("It would write stdout to: {}", stdout.name);
- }
-
- let soc = fdt.find_node("/soc");
- println!("Does it have a `/soc` node? {}", if soc.is_some() { "yes" } else { "no" });
- if let Some(soc) = soc {
- println!("...and it has the following children:");
- for child in soc.children() {
- println!(" {}", child.name);
- }
- }
-}
diff --git a/vendor/fdt/examples/tree_print.rs b/vendor/fdt/examples/tree_print.rs
deleted file mode 100644
index 194562c5..00000000
--- a/vendor/fdt/examples/tree_print.rs
+++ /dev/null
@@ -1,18 +0,0 @@
-use fdt::node::FdtNode;
-
-static MY_FDT: &[u8] = include_bytes!("../dtb/test.dtb");
-
-fn main() {
- let fdt = fdt::Fdt::new(MY_FDT).unwrap();
-
- print_node(fdt.find_node("/").unwrap(), 0);
-}
-
-fn print_node(node: FdtNode<'_, '_>, n_spaces: usize) {
- (0..n_spaces).for_each(|_| print!(" "));
- println!("{}/", node.name);
-
- for child in node.children() {
- print_node(child, n_spaces + 4);
- }
-}
diff --git a/vendor/fdt/rustfmt.toml b/vendor/fdt/rustfmt.toml
deleted file mode 100644
index 2a35f023..00000000
--- a/vendor/fdt/rustfmt.toml
+++ /dev/null
@@ -1 +0,0 @@
-use_small_heuristics = "Max"
diff --git a/vendor/fdt/src/lib.rs b/vendor/fdt/src/lib.rs
deleted file mode 100644
index 0bcfe88c..00000000
--- a/vendor/fdt/src/lib.rs
+++ /dev/null
@@ -1,415 +0,0 @@
-// This Source Code Form is subject to the terms of the Mozilla Public License,
-// v. 2.0. If a copy of the MPL was not distributed with this file, You can
-// obtain one at https://mozilla.org/MPL/2.0/.
-
-//! # `fdt`
-//!
-//! A pure-Rust `#![no_std]` crate for parsing Flattened Devicetrees, with the goal of having a
-//! very ergonomic and idiomatic API.
-//!
-//! [](https://crates.io/crates/fdt) [](https://docs.rs/fdt) 
-//!
-//! ## License
-//!
-//! This crate is licensed under the Mozilla Public License 2.0 (see the LICENSE file).
-//!
-//! ## Example
-//!
-//! ```rust,no_run
-//! static MY_FDT: &[u8] = include_bytes!("../dtb/test.dtb");
-//!
-//! fn main() {
-//! let fdt = fdt::Fdt::new(MY_FDT).unwrap();
-//!
-//! println!("This is a devicetree representation of a {}", fdt.root().model());
-//! println!("...which is compatible with at least: {}", fdt.root().compatible().first());
-//! println!("...and has {} CPU(s)", fdt.cpus().count());
-//! println!(
-//! "...and has at least one memory location at: {:#X}\n",
-//! fdt.memory().regions().next().unwrap().starting_address as usize
-//! );
-//!
-//! let chosen = fdt.chosen();
-//! if let Some(bootargs) = chosen.bootargs() {
-//! println!("The bootargs are: {:?}", bootargs);
-//! }
-//!
-//! if let Some(stdout) = chosen.stdout() {
-//! println!("It would write stdout to: {}", stdout.name);
-//! }
-//!
-//! let soc = fdt.find_node("/soc");
-//! println!("Does it have a `/soc` node? {}", if soc.is_some() { "yes" } else { "no" });
-//! if let Some(soc) = soc {
-//! println!("...and it has the following children:");
-//! for child in soc.children() {
-//! println!(" {}", child.name);
-//! }
-//! }
-//! }
-//! ```
-
-#![no_std]
-
-#[cfg(test)]
-mod tests;
-
-pub mod node;
-mod parsing;
-pub mod standard_nodes;
-
-#[cfg(feature = "pretty-printing")]
-mod pretty_print;
-
-use node::MemoryReservation;
-use parsing::{BigEndianU32, CStr, FdtData};
-use standard_nodes::{Aliases, Chosen, Cpu, Memory, MemoryRegion, Root};
-
-/// Possible errors when attempting to create an `Fdt`
-#[derive(Debug, Clone, Copy, PartialEq)]
-pub enum FdtError {
- /// The FDT had an invalid magic value
- BadMagic,
- /// The given pointer was null
- BadPtr,
- /// The slice passed in was too small to fit the given total size of the FDT
- /// structure
- BufferTooSmall,
-}
-
-impl core::fmt::Display for FdtError {
- fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
- match self {
- FdtError::BadMagic => write!(f, "bad FDT magic value"),
- FdtError::BadPtr => write!(f, "an invalid pointer was passed"),
- FdtError::BufferTooSmall => {
- write!(f, "the given buffer was too small to contain a FDT header")
- }
- }
- }
-}
-
-/// A flattened devicetree located somewhere in memory
-///
-/// Note on `Debug` impl: by default the `Debug` impl of this struct will not
-/// print any useful information, if you would like a best-effort tree print
-/// which looks similar to `dtc`'s output, enable the `pretty-printing` feature
-#[derive(Clone, Copy)]
-pub struct Fdt<'a> {
- data: &'a [u8],
- header: FdtHeader,
-}
-
-impl core::fmt::Debug for Fdt<'_> {
- fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
- #[cfg(feature = "pretty-printing")]
- pretty_print::print_node(f, self.root().node, 0)?;
-
- #[cfg(not(feature = "pretty-printing"))]
- f.debug_struct("Fdt").finish_non_exhaustive()?;
-
- Ok(())
- }
-}
-
-#[derive(Debug, Clone, Copy)]
-#[repr(C)]
-struct FdtHeader {
- /// FDT header magic
- magic: BigEndianU32,
- /// Total size in bytes of the FDT structure
- totalsize: BigEndianU32,
- /// Offset in bytes from the start of the header to the structure block
- off_dt_struct: BigEndianU32,
- /// Offset in bytes from the start of the header to the strings block
- off_dt_strings: BigEndianU32,
- /// Offset in bytes from the start of the header to the memory reservation
- /// block
- off_mem_rsvmap: BigEndianU32,
- /// FDT version
- version: BigEndianU32,
- /// Last compatible FDT version
- last_comp_version: BigEndianU32,
- /// System boot CPU ID
- boot_cpuid_phys: BigEndianU32,
- /// Length in bytes of the strings block
- size_dt_strings: BigEndianU32,
- /// Length in bytes of the struct block
- size_dt_struct: BigEndianU32,
-}
-
-impl FdtHeader {
- fn valid_magic(&self) -> bool {
- self.magic.get() == 0xd00dfeed
- }
-
- fn struct_range(&self) -> core::ops::Range {
- let start = self.off_dt_struct.get() as usize;
- let end = start + self.size_dt_struct.get() as usize;
-
- start..end
- }
-
- fn strings_range(&self) -> core::ops::Range {
- let start = self.off_dt_strings.get() as usize;
- let end = start + self.size_dt_strings.get() as usize;
-
- start..end
- }
-
- fn from_bytes(bytes: &mut FdtData<'_>) -> Option {
- Some(Self {
- magic: bytes.u32()?,
- totalsize: bytes.u32()?,
- off_dt_struct: bytes.u32()?,
- off_dt_strings: bytes.u32()?,
- off_mem_rsvmap: bytes.u32()?,
- version: bytes.u32()?,
- last_comp_version: bytes.u32()?,
- boot_cpuid_phys: bytes.u32()?,
- size_dt_strings: bytes.u32()?,
- size_dt_struct: bytes.u32()?,
- })
- }
-}
-
-impl<'a> Fdt<'a> {
- /// Construct a new `Fdt` from a byte buffer
- ///
- /// Note: this function does ***not*** require that the data be 4-byte
- /// aligned
- pub fn new(data: &'a [u8]) -> Result {
- let mut stream = FdtData::new(data);
- let header = FdtHeader::from_bytes(&mut stream).ok_or(FdtError::BufferTooSmall)?;
-
- if !header.valid_magic() {
- return Err(FdtError::BadMagic);
- } else if data.len() < header.totalsize.get() as usize {
- return Err(FdtError::BufferTooSmall);
- }
-
- Ok(Self { data, header })
- }
-
- /// # Safety
- /// This function performs a read to verify the magic value. If the pointer
- /// is invalid this can result in undefined behavior.
- ///
- /// Note: this function does ***not*** require that the data be 4-byte
- /// aligned
- pub unsafe fn from_ptr(ptr: *const u8) -> Result {
- if ptr.is_null() {
- return Err(FdtError::BadPtr);
- }
-
- let tmp_header = core::slice::from_raw_parts(ptr, core::mem::size_of::());
- let real_size =
- FdtHeader::from_bytes(&mut FdtData::new(tmp_header)).unwrap().totalsize.get() as usize;
-
- Self::new(core::slice::from_raw_parts(ptr, real_size))
- }
-
- /// Return the `/aliases` node, if one exists
- pub fn aliases(&self) -> Option> {
- Some(Aliases {
- node: node::find_node(&mut FdtData::new(self.structs_block()), "/aliases", self, None)?,
- header: self,
- })
- }
-
- /// Searches for the `/chosen` node, which is always available
- pub fn chosen(&self) -> Chosen<'_, 'a> {
- node::find_node(&mut FdtData::new(self.structs_block()), "/chosen", self, None)
- .map(|node| Chosen { node })
- .expect("/chosen is required")
- }
-
- /// Return the `/cpus` node, which is always available
- pub fn cpus(&self) -> impl Iterator- > {
- let parent = self.find_node("/cpus").expect("/cpus is a required node");
-
- parent
- .children()
- .filter(|c| c.name.split('@').next().unwrap() == "cpu")
- .map(move |cpu| Cpu { parent, node: cpu })
- }
-
- /// Returns the memory node, which is always available
- pub fn memory(&self) -> Memory<'_, 'a> {
- Memory { node: self.find_node("/memory").expect("requires memory node") }
- }
-
- /// Returns an iterator over the memory reservations
- pub fn memory_reservations(&self) -> impl Iterator
- + 'a {
- let mut stream = FdtData::new(&self.data[self.header.off_mem_rsvmap.get() as usize..]);
- let mut done = false;
-
- core::iter::from_fn(move || {
- if stream.is_empty() || done {
- return None;
- }
-
- let res = MemoryReservation::from_bytes(&mut stream)?;
-
- if res.address() as usize == 0 && res.size() == 0 {
- done = true;
- return None;
- }
-
- Some(res)
- })
- }
-
- /// Return the root (`/`) node, which is always available
- pub fn root(&self) -> Root<'_, 'a> {
- Root { node: self.find_node("/").expect("/ is a required node") }
- }
-
- /// Returns the first node that matches the node path, if you want all that
- /// match the path, use `find_all_nodes`. This will automatically attempt to
- /// resolve aliases if `path` is not found.
- ///
- /// Node paths must begin with a leading `/` and are ASCII only. Passing in
- /// an invalid node path or non-ASCII node name in the path will return
- /// `None`, as they will not be found within the devicetree structure.
- ///
- /// Note: if the address of a node name is left out, the search will find
- /// the first node that has a matching name, ignoring the address portion if
- /// it exists.
- pub fn find_node(&self, path: &str) -> Option> {
- let node = node::find_node(&mut FdtData::new(self.structs_block()), path, self, None);
- node.or_else(|| self.aliases()?.resolve_node(path))
- }
-
- /// Searches for a node which contains a `compatible` property and contains
- /// one of the strings inside of `with`
- pub fn find_compatible(&self, with: &[&str]) -> Option> {
- self.all_nodes().find(|n| {
- n.compatible().and_then(|compats| compats.all().find(|c| with.contains(c))).is_some()
- })
- }
-
- /// Searches for the given `phandle`
- pub fn find_phandle(&self, phandle: u32) -> Option> {
- self.all_nodes().find(|n| {
- n.properties()
- .find(|p| p.name == "phandle")
- .and_then(|p| Some(BigEndianU32::from_bytes(p.value)?.get() == phandle))
- .unwrap_or(false)
- })
- }
-
- /// Returns an iterator over all of the available nodes with the given path.
- /// This does **not** attempt to find any node with the same name as the
- /// provided path, if you're looking to do that, [`Fdt::all_nodes`] will
- /// allow you to iterate over each node's name and filter for the desired
- /// node(s).
- ///
- /// For example:
- /// ```rust
- /// static MY_FDT: &[u8] = include_bytes!("../dtb/test.dtb");
- ///
- /// let fdt = fdt::Fdt::new(MY_FDT).unwrap();
- ///
- /// for node in fdt.find_all_nodes("/soc/virtio_mmio") {
- /// println!("{}", node.name);
- /// }
- /// ```
- /// prints:
- /// ```notrust
- /// virtio_mmio@10008000
- /// virtio_mmio@10007000
- /// virtio_mmio@10006000
- /// virtio_mmio@10005000
- /// virtio_mmio@10004000
- /// virtio_mmio@10003000
- /// virtio_mmio@10002000
- /// virtio_mmio@10001000
- /// ```
- pub fn find_all_nodes(&self, path: &'a str) -> impl Iterator
- > {
- let mut done = false;
- let only_root = path == "/";
- let valid_path = path.chars().fold(0, |acc, c| acc + if c == '/' { 1 } else { 0 }) >= 1;
-
- let mut path_split = path.rsplitn(2, '/');
- let child_name = path_split.next().unwrap();
- let parent = match path_split.next() {
- Some("") => Some(self.root().node),
- Some(s) => node::find_node(&mut FdtData::new(self.structs_block()), s, self, None),
- None => None,
- };
-
- let (parent, bad_parent) = match parent {
- Some(parent) => (parent, false),
- None => (self.find_node("/").unwrap(), true),
- };
-
- let mut child_iter = parent.children();
-
- core::iter::from_fn(move || {
- if done || !valid_path || bad_parent {
- return None;
- }
-
- if only_root {
- done = true;
- return self.find_node("/");
- }
-
- let mut ret = None;
-
- #[allow(clippy::while_let_on_iterator)]
- while let Some(child) = child_iter.next() {
- if child.name.split('@').next()? == child_name {
- ret = Some(child);
- break;
- }
- }
-
- ret
- })
- }
-
- /// Returns an iterator over all of the nodes in the devicetree, depth-first
- pub fn all_nodes(&self) -> impl Iterator
- > {
- node::all_nodes(self)
- }
-
- /// Returns an iterator over all of the strings inside of the strings block
- pub fn strings(&self) -> impl Iterator
- {
- let mut block = self.strings_block();
-
- core::iter::from_fn(move || {
- if block.is_empty() {
- return None;
- }
-
- let cstr = CStr::new(block)?;
-
- block = &block[cstr.len() + 1..];
-
- cstr.as_str()
- })
- }
-
- /// Total size of the devicetree in bytes
- pub fn total_size(&self) -> usize {
- self.header.totalsize.get() as usize
- }
-
- fn cstr_at_offset(&self, offset: usize) -> CStr<'a> {
- CStr::new(&self.strings_block()[offset..]).expect("no null terminating string on C str?")
- }
-
- fn str_at_offset(&self, offset: usize) -> &'a str {
- self.cstr_at_offset(offset).as_str().expect("not utf-8 cstr")
- }
-
- fn strings_block(&self) -> &'a [u8] {
- &self.data[self.header.strings_range()]
- }
-
- fn structs_block(&self) -> &'a [u8] {
- &self.data[self.header.struct_range()]
- }
-}
diff --git a/vendor/fdt/src/node.rs b/vendor/fdt/src/node.rs
deleted file mode 100644
index e71a42f0..00000000
--- a/vendor/fdt/src/node.rs
+++ /dev/null
@@ -1,549 +0,0 @@
-// This Source Code Form is subject to the terms of the Mozilla Public License,
-// v. 2.0. If a copy of the MPL was not distributed with this file, You can
-// obtain one at https://mozilla.org/MPL/2.0/.
-
-use crate::{
- parsing::{BigEndianU32, BigEndianU64, CStr, FdtData},
- standard_nodes::{Compatible, MemoryRegion},
- Fdt,
-};
-
-const FDT_BEGIN_NODE: u32 = 1;
-const FDT_END_NODE: u32 = 2;
-const FDT_PROP: u32 = 3;
-pub(crate) const FDT_NOP: u32 = 4;
-const FDT_END: u32 = 5;
-
-#[derive(Debug, Clone, Copy)]
-#[repr(C)]
-struct FdtProperty {
- len: BigEndianU32,
- name_offset: BigEndianU32,
-}
-
-impl FdtProperty {
- fn from_bytes(bytes: &mut FdtData<'_>) -> Option {
- let len = bytes.u32()?;
- let name_offset = bytes.u32()?;
-
- Some(Self { len, name_offset })
- }
-}
-
-/// A devicetree node
-#[derive(Debug, Clone, Copy)]
-pub struct FdtNode<'b, 'a: 'b> {
- pub name: &'a str,
- pub(crate) header: &'b Fdt<'a>,
- props: &'a [u8],
- parent_props: Option<&'a [u8]>,
-}
-
-impl<'b, 'a: 'b> FdtNode<'b, 'a> {
- fn new(
- name: &'a str,
- header: &'b Fdt<'a>,
- props: &'a [u8],
- parent_props: Option<&'a [u8]>,
- ) -> Self {
- Self { name, header, props, parent_props }
- }
-
- /// Returns an iterator over the available properties of the node
- pub fn properties(self) -> impl Iterator
- > + 'b {
- let mut stream = FdtData::new(self.props);
- let mut done = false;
-
- core::iter::from_fn(move || {
- if stream.is_empty() || done {
- return None;
- }
-
- while stream.peek_u32()?.get() == FDT_NOP {
- stream.skip(4);
- }
-
- if stream.peek_u32().unwrap().get() == FDT_PROP {
- Some(NodeProperty::parse(&mut stream, self.header))
- } else {
- done = true;
- None
- }
- })
- }
-
- /// Attempts to find the a property by its name
- pub fn property(self, name: &str) -> Option> {
- self.properties().find(|p| p.name == name)
- }
-
- /// Returns an iterator over the children of the current node
- pub fn children(self) -> impl Iterator
- > {
- let mut stream = FdtData::new(self.props);
-
- while stream.peek_u32().unwrap().get() == FDT_NOP {
- stream.skip(4);
- }
-
- while stream.peek_u32().unwrap().get() == FDT_PROP {
- NodeProperty::parse(&mut stream, self.header);
- }
-
- let mut done = false;
-
- core::iter::from_fn(move || {
- if stream.is_empty() || done {
- return None;
- }
-
- while stream.peek_u32()?.get() == FDT_NOP {
- stream.skip(4);
- }
-
- if stream.peek_u32()?.get() == FDT_BEGIN_NODE {
- let origin = stream.remaining();
- let ret = {
- stream.skip(4);
- let unit_name = CStr::new(stream.remaining()).expect("unit name").as_str()?;
- let full_name_len = unit_name.len() + 1;
- stream.skip(full_name_len);
-
- if full_name_len % 4 != 0 {
- stream.skip(4 - (full_name_len % 4));
- }
-
- Some(Self::new(unit_name, self.header, stream.remaining(), Some(self.props)))
- };
-
- stream = FdtData::new(origin);
-
- skip_current_node(&mut stream, self.header);
-
- ret
- } else {
- done = true;
- None
- }
- })
- }
-
- /// `reg` property
- ///
- /// Important: this method assumes that the value(s) inside the `reg`
- /// property represent CPU-addressable addresses that are able to fit within
- /// the platform's pointer size (e.g. `#address-cells` and `#size-cells` are
- /// less than or equal to 2 for a 64-bit platform). If this is not the case
- /// or you're unsure of whether this applies to the node, it is recommended
- /// to use the [`FdtNode::property`] method to extract the raw value slice
- /// or use the provided [`FdtNode::raw_reg`] helper method to give you an
- /// iterator over the address and size slices. One example of where this
- /// would return `None` for a node is a `pci` child node which contains the
- /// PCI address information in the `reg` property, of which the address has
- /// an `#address-cells` value of 3.
- pub fn reg(self) -> Option + 'a> {
- let sizes = self.parent_cell_sizes();
- if sizes.address_cells > 2 || sizes.size_cells > 2 {
- return None;
- }
-
- let mut reg = None;
- for prop in self.properties() {
- if prop.name == "reg" {
- let mut stream = FdtData::new(prop.value);
- reg = Some(core::iter::from_fn(move || {
- let starting_address = match sizes.address_cells {
- 1 => stream.u32()?.get() as usize,
- 2 => stream.u64()?.get() as usize,
- _ => return None,
- } as *const u8;
-
- let size = match sizes.size_cells {
- 0 => None,
- 1 => Some(stream.u32()?.get() as usize),
- 2 => Some(stream.u64()?.get() as usize),
- _ => return None,
- };
-
- Some(MemoryRegion { starting_address, size })
- }));
- break;
- }
- }
-
- reg
- }
-
- /// Convenience method that provides an iterator over the raw bytes for the
- /// address and size values inside of the `reg` property
- pub fn raw_reg(self) -> Option> + 'a> {
- let sizes = self.parent_cell_sizes();
-
- if let Some(prop) = self.property("reg") {
- let mut stream = FdtData::new(prop.value);
- return Some(core::iter::from_fn(move || {
- Some(RawReg {
- address: stream.take(sizes.address_cells * 4)?,
- size: stream.take(sizes.size_cells * 4)?,
- })
- }));
- }
-
- None
- }
-
- /// `compatible` property
- pub fn compatible(self) -> Option> {
- let mut s = None;
- for prop in self.properties() {
- if prop.name == "compatible" {
- s = Some(Compatible { data: prop.value });
- }
- }
-
- s
- }
-
- /// Cell sizes for child nodes
- pub fn cell_sizes(self) -> CellSizes {
- let mut cell_sizes = CellSizes::default();
-
- for property in self.properties() {
- match property.name {
- "#address-cells" => {
- cell_sizes.address_cells = BigEndianU32::from_bytes(property.value)
- .expect("not enough bytes for #address-cells value")
- .get() as usize;
- }
- "#size-cells" => {
- cell_sizes.size_cells = BigEndianU32::from_bytes(property.value)
- .expect("not enough bytes for #size-cells value")
- .get() as usize;
- }
- _ => {}
- }
- }
-
- cell_sizes
- }
-
- /// Searches for the interrupt parent, if the node contains one
- pub fn interrupt_parent(self) -> Option> {
- self.properties()
- .find(|p| p.name == "interrupt-parent")
- .and_then(|p| self.header.find_phandle(BigEndianU32::from_bytes(p.value)?.get()))
- }
-
- /// `#interrupt-cells` property
- pub fn interrupt_cells(self) -> Option {
- let mut interrupt_cells = None;
-
- if let Some(prop) = self.property("#interrupt-cells") {
- interrupt_cells = BigEndianU32::from_bytes(prop.value).map(|n| n.get() as usize)
- }
-
- interrupt_cells
- }
-
- /// `interrupts` property
- pub fn interrupts(self) -> Option + 'a> {
- let sizes = self.parent_interrupt_cells()?;
-
- let mut interrupt = None;
- for prop in self.properties() {
- if prop.name == "interrupts" {
- let mut stream = FdtData::new(prop.value);
- interrupt = Some(core::iter::from_fn(move || {
- let interrupt = match sizes {
- 1 => stream.u32()?.get() as usize,
- 2 => stream.u64()?.get() as usize,
- 3 => {
- let ret = stream.u64()?.get() as usize;
- stream.skip(4);
- ret
- }
- _ => return None,
- };
-
- Some(interrupt)
- }));
- break;
- }
- }
- interrupt
- }
-
- pub(crate) fn parent_cell_sizes(self) -> CellSizes {
- let mut cell_sizes = CellSizes::default();
-
- if let Some(parent) = self.parent_props {
- let parent =
- FdtNode { name: "", props: parent, header: self.header, parent_props: None };
- cell_sizes = parent.cell_sizes();
- }
-
- cell_sizes
- }
-
- pub(crate) fn parent_interrupt_cells(self) -> Option {
- let mut interrupt_cells = None;
- let parent = self
- .property("interrupt-parent")
- .and_then(|p| self.header.find_phandle(BigEndianU32::from_bytes(p.value)?.get()))
- .or_else(|| {
- Some(FdtNode {
- name: "",
- props: self.parent_props?,
- header: self.header,
- parent_props: None,
- })
- });
-
- if let Some(size) = parent.and_then(|parent| parent.interrupt_cells()) {
- interrupt_cells = Some(size);
- }
-
- interrupt_cells
- }
-}
-
-/// The number of cells (big endian u32s) that addresses and sizes take
-#[derive(Debug, Clone, Copy)]
-pub struct CellSizes {
- /// Size of values representing an address
- pub address_cells: usize,
- /// Size of values representing a size
- pub size_cells: usize,
-}
-
-impl Default for CellSizes {
- fn default() -> Self {
- CellSizes { address_cells: 2, size_cells: 1 }
- }
-}
-
-/// A raw `reg` property value set
-#[derive(Debug, Clone, Copy, PartialEq)]
-pub struct RawReg<'a> {
- /// Big-endian encoded bytes making up the address portion of the property.
- /// Length will always be a multiple of 4 bytes.
- pub address: &'a [u8],
- /// Big-endian encoded bytes making up the size portion of the property.
- /// Length will always be a multiple of 4 bytes.
- pub size: &'a [u8],
-}
-
-pub(crate) fn find_node<'b, 'a: 'b>(
- stream: &mut FdtData<'a>,
- name: &str,
- header: &'b Fdt<'a>,
- parent_props: Option<&'a [u8]>,
-) -> Option> {
- let mut parts = name.splitn(2, '/');
- let looking_for = parts.next()?;
-
- stream.skip_nops();
-
- let curr_data = stream.remaining();
-
- match stream.u32()?.get() {
- FDT_BEGIN_NODE => {}
- _ => return None,
- }
-
- let unit_name = CStr::new(stream.remaining()).expect("unit name C str").as_str()?;
-
- let full_name_len = unit_name.len() + 1;
- skip_4_aligned(stream, full_name_len);
-
- let looking_contains_addr = looking_for.contains('@');
- let addr_name_same = unit_name == looking_for;
- let base_name_same = unit_name.split('@').next()? == looking_for;
-
- if (looking_contains_addr && !addr_name_same) || (!looking_contains_addr && !base_name_same) {
- *stream = FdtData::new(curr_data);
- skip_current_node(stream, header);
-
- return None;
- }
-
- let next_part = match parts.next() {
- None | Some("") => {
- return Some(FdtNode::new(unit_name, header, stream.remaining(), parent_props))
- }
- Some(part) => part,
- };
-
- stream.skip_nops();
-
- let parent_props = Some(stream.remaining());
-
- while stream.peek_u32()?.get() == FDT_PROP {
- let _ = NodeProperty::parse(stream, header);
- }
-
- while stream.peek_u32()?.get() == FDT_BEGIN_NODE {
- if let Some(p) = find_node(stream, next_part, header, parent_props) {
- return Some(p);
- }
- }
-
- stream.skip_nops();
-
- if stream.u32()?.get() != FDT_END_NODE {
- return None;
- }
-
- None
-}
-
-// FIXME: this probably needs refactored
-pub(crate) fn all_nodes<'b, 'a: 'b>(header: &'b Fdt<'a>) -> impl Iterator
- > {
- let mut stream = FdtData::new(header.structs_block());
- let mut done = false;
- let mut parents: [&[u8]; 64] = [&[]; 64];
- let mut parent_index = 0;
-
- core::iter::from_fn(move || {
- if stream.is_empty() || done {
- return None;
- }
-
- while stream.peek_u32()?.get() == FDT_END_NODE {
- parent_index -= 1;
- stream.skip(4);
- }
-
- if stream.peek_u32()?.get() == FDT_END {
- done = true;
- return None;
- }
-
- while stream.peek_u32()?.get() == FDT_NOP {
- stream.skip(4);
- }
-
- match stream.u32()?.get() {
- FDT_BEGIN_NODE => {}
- _ => return None,
- }
-
- let unit_name = CStr::new(stream.remaining()).expect("unit name C str").as_str().unwrap();
- let full_name_len = unit_name.len() + 1;
- skip_4_aligned(&mut stream, full_name_len);
-
- let curr_node = stream.remaining();
-
- parent_index += 1;
- parents[parent_index] = curr_node;
-
- while stream.peek_u32()?.get() == FDT_NOP {
- stream.skip(4);
- }
-
- while stream.peek_u32()?.get() == FDT_PROP {
- NodeProperty::parse(&mut stream, header);
- }
-
- Some(FdtNode {
- name: if unit_name.is_empty() { "/" } else { unit_name },
- header,
- parent_props: match parent_index {
- 1 => None,
- _ => Some(parents[parent_index - 1]),
- },
- props: curr_node,
- })
- })
-}
-
-pub(crate) fn skip_current_node<'a>(stream: &mut FdtData<'a>, header: &Fdt<'a>) {
- assert_eq!(stream.u32().unwrap().get(), FDT_BEGIN_NODE, "bad node");
-
- let unit_name = CStr::new(stream.remaining()).expect("unit_name C str").as_str().unwrap();
- let full_name_len = unit_name.len() + 1;
- skip_4_aligned(stream, full_name_len);
-
- while stream.peek_u32().unwrap().get() == FDT_PROP {
- NodeProperty::parse(stream, header);
- }
-
- while stream.peek_u32().unwrap().get() == FDT_BEGIN_NODE {
- skip_current_node(stream, header);
- }
-
- stream.skip_nops();
-
- assert_eq!(stream.u32().unwrap().get(), FDT_END_NODE, "bad node");
-}
-
-/// A node property
-#[derive(Debug, Clone, Copy)]
-pub struct NodeProperty<'a> {
- /// Property name
- pub name: &'a str,
- /// Property value
- pub value: &'a [u8],
-}
-
-impl<'a> NodeProperty<'a> {
- /// Attempt to parse the property value as a `usize`
- pub fn as_usize(self) -> Option {
- match self.value.len() {
- 4 => BigEndianU32::from_bytes(self.value).map(|i| i.get() as usize),
- 8 => BigEndianU64::from_bytes(self.value).map(|i| i.get() as usize),
- _ => None,
- }
- }
-
- /// Attempt to parse the property value as a `&str`
- pub fn as_str(self) -> Option<&'a str> {
- core::str::from_utf8(self.value).map(|s| s.trim_end_matches('\0')).ok()
- }
-
- fn parse(stream: &mut FdtData<'a>, header: &Fdt<'a>) -> Self {
- match stream.u32().unwrap().get() {
- FDT_PROP => {}
- other => panic!("bad prop, tag: {}", other),
- }
-
- let prop = FdtProperty::from_bytes(stream).expect("FDT property");
- let data_len = prop.len.get() as usize;
-
- let data = &stream.remaining()[..data_len];
-
- skip_4_aligned(stream, data_len);
-
- NodeProperty { name: header.str_at_offset(prop.name_offset.get() as usize), value: data }
- }
-}
-
-/// A memory reservation
-#[derive(Debug)]
-#[repr(C)]
-pub struct MemoryReservation {
- pub(crate) address: BigEndianU64,
- pub(crate) size: BigEndianU64,
-}
-
-impl MemoryReservation {
- /// Pointer representing the memory reservation address
- pub fn address(&self) -> *const u8 {
- self.address.get() as usize as *const u8
- }
-
- /// Size of the memory reservation
- pub fn size(&self) -> usize {
- self.size.get() as usize
- }
-
- pub(crate) fn from_bytes(bytes: &mut FdtData<'_>) -> Option {
- let address = bytes.u64()?;
- let size = bytes.u64()?;
-
- Some(Self { address, size })
- }
-}
-
-fn skip_4_aligned(stream: &mut FdtData<'_>, len: usize) {
- stream.skip((len + 3) & !0x3);
-}
diff --git a/vendor/fdt/src/parsing.rs b/vendor/fdt/src/parsing.rs
deleted file mode 100644
index 9d9e5604..00000000
--- a/vendor/fdt/src/parsing.rs
+++ /dev/null
@@ -1,108 +0,0 @@
-// This Source Code Form is subject to the terms of the Mozilla Public License,
-// v. 2.0. If a copy of the MPL was not distributed with this file, You can
-// obtain one at https://mozilla.org/MPL/2.0/.
-
-use core::convert::TryInto;
-pub struct CStr<'a>(&'a [u8]);
-
-impl<'a> CStr<'a> {
- pub fn new(data: &'a [u8]) -> Option {
- let end = data.iter().position(|&b| b == 0)?;
- Some(Self(&data[..end]))
- }
-
- /// Does not include the null terminating byte
- pub fn len(&self) -> usize {
- self.0.len()
- }
-
- pub fn as_str(&self) -> Option<&'a str> {
- core::str::from_utf8(self.0).ok()
- }
-}
-
-#[derive(Debug, Clone, Copy)]
-#[repr(transparent)]
-pub struct BigEndianU32(u32);
-
-impl BigEndianU32 {
- pub fn get(self) -> u32 {
- self.0
- }
-
- pub(crate) fn from_bytes(bytes: &[u8]) -> Option {
- Some(BigEndianU32(u32::from_be_bytes(bytes.get(..4)?.try_into().unwrap())))
- }
-}
-
-#[derive(Debug, Clone, Copy)]
-#[repr(transparent)]
-pub struct BigEndianU64(u64);
-
-impl BigEndianU64 {
- pub fn get(&self) -> u64 {
- self.0
- }
-
- pub(crate) fn from_bytes(bytes: &[u8]) -> Option {
- Some(BigEndianU64(u64::from_be_bytes(bytes.get(..8)?.try_into().unwrap())))
- }
-}
-
-#[derive(Debug, Clone, Copy)]
-pub struct FdtData<'a> {
- bytes: &'a [u8],
-}
-
-impl<'a> FdtData<'a> {
- pub fn new(bytes: &'a [u8]) -> Self {
- Self { bytes }
- }
-
- pub fn u32(&mut self) -> Option {
- let ret = BigEndianU32::from_bytes(self.bytes)?;
- self.skip(4);
-
- Some(ret)
- }
-
- pub fn u64(&mut self) -> Option {
- let ret = BigEndianU64::from_bytes(self.bytes)?;
- self.skip(8);
-
- Some(ret)
- }
-
- pub fn skip(&mut self, n_bytes: usize) {
- self.bytes = self.bytes.get(n_bytes..).unwrap_or_default()
- }
-
- pub fn remaining(&self) -> &'a [u8] {
- self.bytes
- }
-
- pub fn peek_u32(&self) -> Option {
- Self::new(self.remaining()).u32()
- }
-
- pub fn is_empty(&self) -> bool {
- self.remaining().is_empty()
- }
-
- pub fn skip_nops(&mut self) {
- while let Some(crate::node::FDT_NOP) = self.peek_u32().map(|n| n.get()) {
- let _ = self.u32();
- }
- }
-
- pub fn take(&mut self, bytes: usize) -> Option<&'a [u8]> {
- if self.bytes.len() >= bytes {
- let ret = &self.bytes[..bytes];
- self.skip(bytes);
-
- return Some(ret);
- }
-
- None
- }
-}
diff --git a/vendor/fdt/src/pretty_print.rs b/vendor/fdt/src/pretty_print.rs
deleted file mode 100644
index aa57409d..00000000
--- a/vendor/fdt/src/pretty_print.rs
+++ /dev/null
@@ -1,100 +0,0 @@
-// This Source Code Form is subject to the terms of the Mozilla Public License,
-// v. 2.0. If a copy of the MPL was not distributed with this file, You can
-// obtain one at https://mozilla.org/MPL/2.0/.
-
-pub fn print_node(
- f: &mut core::fmt::Formatter<'_>,
- node: crate::node::FdtNode<'_, '_>,
- n_spaces: usize,
-) -> core::fmt::Result {
- write!(f, "{:width$}", ' ', width = n_spaces)?;
- writeln!(f, "{} {{", if node.name.is_empty() { "/" } else { node.name })?;
- let mut were_props = false;
- for prop in node.properties() {
- were_props = true;
-
- match prop.name {
- "reg" => {
- write!(f, "{:width$}reg = <", ' ', width = n_spaces + 4)?;
- for (i, reg) in node.reg().unwrap().enumerate() {
- if i > 0 {
- write!(f, " ")?;
- }
-
- match reg.size {
- Some(size) => {
- write!(f, "{:#x} {:#x}", reg.starting_address as usize, size)?
- }
- None => write!(f, "{:#x}", reg.starting_address as usize)?,
- }
- }
- writeln!(f, ">")?;
- }
- "compatible" => writeln!(
- f,
- "{:width$}compatible = {:?}",
- ' ',
- prop.as_str().unwrap(),
- width = n_spaces + 4
- )?,
- name if name.contains("-cells") => {
- writeln!(
- f,
- "{:width$}{} = <{:#x}>",
- ' ',
- name,
- prop.as_usize().unwrap(),
- width = n_spaces + 4
- )?;
- }
- _ => match prop.as_str() {
- Some(value)
- if (!value.is_empty() && value.chars().all(|c| c.is_ascii_graphic()))
- || prop.value == [0] =>
- {
- writeln!(f, "{:width$}{} = {:?}", ' ', prop.name, value, width = n_spaces + 4)?
- }
- _ => match prop.value.len() {
- 4 | 8 => writeln!(
- f,
- "{:width$}{} = <{:#x}>",
- ' ',
- prop.name,
- prop.as_usize().unwrap(),
- width = n_spaces + 4
- )?,
- _ => writeln!(
- f,
- "{:width$}{} = {:?}",
- ' ',
- prop.name,
- prop.value,
- width = n_spaces + 4
- )?,
- },
- },
- }
- }
-
- if node.children().next().is_some() && were_props {
- writeln!(f)?;
- }
-
- let mut first = true;
- for child in node.children() {
- if !first {
- writeln!(f)?;
- }
-
- print_node(f, child, n_spaces + 4)?;
- first = false;
- }
-
- if n_spaces > 0 {
- write!(f, "{:width$}", ' ', width = n_spaces)?;
- }
-
- writeln!(f, "}};")?;
-
- Ok(())
-}
diff --git a/vendor/fdt/src/standard_nodes.rs b/vendor/fdt/src/standard_nodes.rs
deleted file mode 100644
index cde37754..00000000
--- a/vendor/fdt/src/standard_nodes.rs
+++ /dev/null
@@ -1,300 +0,0 @@
-// This Source Code Form is subject to the terms of the Mozilla Public License,
-// v. 2.0. If a copy of the MPL was not distributed with this file, You can
-// obtain one at https://mozilla.org/MPL/2.0/.
-
-use crate::{
- node::{CellSizes, FdtNode, NodeProperty},
- parsing::{BigEndianU32, BigEndianU64, CStr, FdtData},
- Fdt,
-};
-
-/// Represents the `/chosen` node with specific helper methods
-#[derive(Debug, Clone, Copy)]
-pub struct Chosen<'b, 'a: 'b> {
- pub(crate) node: FdtNode<'b, 'a>,
-}
-
-impl<'b, 'a: 'b> Chosen<'b, 'a> {
- /// Contains the bootargs, if they exist
- pub fn bootargs(self) -> Option<&'a str> {
- self.node
- .properties()
- .find(|n| n.name == "bootargs")
- .and_then(|n| core::str::from_utf8(&n.value[..n.value.len() - 1]).ok())
- }
-
- /// Searches for the node representing `stdout`, if the property exists,
- /// attempting to resolve aliases if the node name doesn't exist as-is
- pub fn stdout(self) -> Option> {
- self.node
- .properties()
- .find(|n| n.name == "stdout-path")
- .and_then(|n| core::str::from_utf8(&n.value[..n.value.len() - 1]).ok())
- .and_then(|name| self.node.header.find_node(name))
- }
-
- /// Searches for the node representing `stdout`, if the property exists,
- /// attempting to resolve aliases if the node name doesn't exist as-is. If
- /// no `stdin` property exists, but `stdout` is present, it will return the
- /// node specified by the `stdout` property.
- pub fn stdin(self) -> Option> {
- self.node
- .properties()
- .find(|n| n.name == "stdin-path")
- .and_then(|n| core::str::from_utf8(&n.value[..n.value.len() - 1]).ok())
- .and_then(|name| self.node.header.find_node(name))
- .or_else(|| self.stdout())
- }
-}
-
-/// Represents the root (`/`) node with specific helper methods
-#[derive(Debug, Clone, Copy)]
-pub struct Root<'b, 'a: 'b> {
- pub(crate) node: FdtNode<'b, 'a>,
-}
-
-impl<'b, 'a: 'b> Root<'b, 'a> {
- /// Root node cell sizes
- pub fn cell_sizes(self) -> CellSizes {
- self.node.cell_sizes()
- }
-
- /// `model` property
- pub fn model(self) -> &'a str {
- self.node
- .properties()
- .find(|p| p.name == "model")
- .and_then(|p| core::str::from_utf8(p.value).map(|s| s.trim_end_matches('\0')).ok())
- .unwrap()
- }
-
- /// `compatible` property
- pub fn compatible(self) -> Compatible<'a> {
- self.node.compatible().unwrap()
- }
-
- /// Returns an iterator over all of the available properties
- pub fn properties(self) -> impl Iterator
- > + 'b {
- self.node.properties()
- }
-
- /// Attempts to find the a property by its name
- pub fn property(self, name: &str) -> Option> {
- self.node.properties().find(|p| p.name == name)
- }
-}
-
-/// Represents the `/aliases` node with specific helper methods
-#[derive(Debug, Clone, Copy)]
-pub struct Aliases<'b, 'a: 'b> {
- pub(crate) header: &'b Fdt<'a>,
- pub(crate) node: FdtNode<'b, 'a>,
-}
-
-impl<'b, 'a: 'b> Aliases<'b, 'a> {
- /// Attempt to resolve an alias to a node name
- pub fn resolve(self, alias: &str) -> Option<&'a str> {
- self.node
- .properties()
- .find(|p| p.name == alias)
- .and_then(|p| core::str::from_utf8(p.value).map(|s| s.trim_end_matches('\0')).ok())
- }
-
- /// Attempt to find the node specified by the given alias
- pub fn resolve_node(self, alias: &str) -> Option> {
- self.resolve(alias).and_then(|name| self.header.find_node(name))
- }
-
- /// Returns an iterator over all of the available aliases
- pub fn all(self) -> impl Iterator
- + 'b {
- self.node.properties().filter_map(|p| {
- Some((p.name, core::str::from_utf8(p.value).map(|s| s.trim_end_matches('\0')).ok()?))
- })
- }
-}
-
-/// Represents a `/cpus/cpu*` node with specific helper methods
-#[derive(Debug, Clone, Copy)]
-pub struct Cpu<'b, 'a: 'b> {
- pub(crate) parent: FdtNode<'b, 'a>,
- pub(crate) node: FdtNode<'b, 'a>,
-}
-
-impl<'b, 'a: 'b> Cpu<'b, 'a> {
- /// Return the IDs for the given CPU
- pub fn ids(self) -> CpuIds<'a> {
- let address_cells = self.node.parent_cell_sizes().address_cells;
-
- CpuIds {
- reg: self
- .node
- .properties()
- .find(|p| p.name == "reg")
- .expect("reg is a required property of cpu nodes"),
- address_cells,
- }
- }
-
- /// `clock-frequency` property
- pub fn clock_frequency(self) -> usize {
- self.node
- .properties()
- .find(|p| p.name == "clock-frequency")
- .or_else(|| self.parent.property("clock-frequency"))
- .map(|p| match p.value.len() {
- 4 => BigEndianU32::from_bytes(p.value).unwrap().get() as usize,
- 8 => BigEndianU64::from_bytes(p.value).unwrap().get() as usize,
- _ => unreachable!(),
- })
- .expect("clock-frequency is a required property of cpu nodes")
- }
-
- /// `timebase-frequency` property
- pub fn timebase_frequency(self) -> usize {
- self.node
- .properties()
- .find(|p| p.name == "timebase-frequency")
- .or_else(|| self.parent.property("timebase-frequency"))
- .map(|p| match p.value.len() {
- 4 => BigEndianU32::from_bytes(p.value).unwrap().get() as usize,
- 8 => BigEndianU64::from_bytes(p.value).unwrap().get() as usize,
- _ => unreachable!(),
- })
- .expect("timebase-frequency is a required property of cpu nodes")
- }
-
- /// Returns an iterator over all of the properties for the CPU node
- pub fn properties(self) -> impl Iterator
- > + 'b {
- self.node.properties()
- }
-
- /// Attempts to find the a property by its name
- pub fn property(self, name: &str) -> Option> {
- self.node.properties().find(|p| p.name == name)
- }
-}
-
-/// Represents the value of the `reg` property of a `/cpus/cpu*` node which may
-/// contain more than one CPU or thread ID
-#[derive(Debug, Clone, Copy)]
-pub struct CpuIds<'a> {
- pub(crate) reg: NodeProperty<'a>,
- pub(crate) address_cells: usize,
-}
-
-impl<'a> CpuIds<'a> {
- /// The first listed CPU ID, which will always exist
- pub fn first(self) -> usize {
- match self.address_cells {
- 1 => BigEndianU32::from_bytes(self.reg.value).unwrap().get() as usize,
- 2 => BigEndianU64::from_bytes(self.reg.value).unwrap().get() as usize,
- n => panic!("address-cells of size {} is currently not supported", n),
- }
- }
-
- /// Returns an iterator over all of the listed CPU IDs
- pub fn all(self) -> impl Iterator
- + 'a {
- let mut vals = FdtData::new(self.reg.value);
- core::iter::from_fn(move || match vals.remaining() {
- [] => None,
- _ => Some(match self.address_cells {
- 1 => vals.u32()?.get() as usize,
- 2 => vals.u64()?.get() as usize,
- n => panic!("address-cells of size {} is currently not supported", n),
- }),
- })
- }
-}
-
-/// Represents the `compatible` property of a node
-#[derive(Clone, Copy)]
-pub struct Compatible<'a> {
- pub(crate) data: &'a [u8],
-}
-
-impl<'a> Compatible<'a> {
- /// First compatible string
- pub fn first(self) -> &'a str {
- CStr::new(self.data).expect("expected C str").as_str().unwrap()
- }
-
- /// Returns an iterator over all available compatible strings
- pub fn all(self) -> impl Iterator
- {
- let mut data = self.data;
- core::iter::from_fn(move || {
- if data.is_empty() {
- return None;
- }
-
- match data.iter().position(|b| *b == b'\0') {
- Some(idx) => {
- let ret = Some(core::str::from_utf8(&data[..idx]).ok()?);
- data = &data[idx + 1..];
-
- ret
- }
- None => {
- let ret = Some(core::str::from_utf8(data).ok()?);
- data = &[];
-
- ret
- }
- }
- })
- }
-}
-
-/// Represents the `/memory` node with specific helper methods
-#[derive(Debug, Clone, Copy)]
-pub struct Memory<'b, 'a: 'b> {
- pub(crate) node: FdtNode<'b, 'a>,
-}
-
-impl Memory<'_, '_> {
- /// Returns an iterator over all of the available memory regions
- pub fn regions(&self) -> impl Iterator
- + '_ {
- self.node.reg().unwrap()
- }
-
- /// Returns the initial mapped area, if it exists
- pub fn initial_mapped_area(&self) -> Option {
- let mut mapped_area = None;
-
- if let Some(init_mapped_area) = self.node.property("initial_mapped_area") {
- let mut stream = FdtData::new(init_mapped_area.value);
- let effective_address = stream.u64().expect("effective address");
- let physical_address = stream.u64().expect("physical address");
- let size = stream.u32().expect("size");
-
- mapped_area = Some(MappedArea {
- effective_address: effective_address.get() as usize,
- physical_address: physical_address.get() as usize,
- size: size.get() as usize,
- });
- }
-
- mapped_area
- }
-}
-
-/// An area described by the `initial-mapped-area` property of the `/memory`
-/// node
-#[derive(Debug, Clone, Copy, PartialEq)]
-#[repr(C)]
-pub struct MappedArea {
- /// Effective address of the mapped area
- pub effective_address: usize,
- /// Physical address of the mapped area
- pub physical_address: usize,
- /// Size of the mapped area
- pub size: usize,
-}
-
-/// A memory region
-#[derive(Debug, Clone, Copy, PartialEq)]
-pub struct MemoryRegion {
- /// Starting address represented as a pointer
- pub starting_address: *const u8,
- /// Size of the memory region
- pub size: Option,
-}
diff --git a/vendor/fdt/src/tests.rs b/vendor/fdt/src/tests.rs
deleted file mode 100644
index 30a19bbc..00000000
--- a/vendor/fdt/src/tests.rs
+++ /dev/null
@@ -1,225 +0,0 @@
-// This Source Code Form is subject to the terms of the Mozilla Public License,
-// v. 2.0. If a copy of the MPL was not distributed with this file, You can
-// obtain one at https://mozilla.org/MPL/2.0/.
-
-extern crate std;
-
-use crate::{node::RawReg, *};
-
-static TEST: &[u8] = include_bytes!("../dtb/test.dtb");
-static ISSUE_3: &[u8] = include_bytes!("../dtb/issue-3.dtb");
-static SIFIVE: &[u8] = include_bytes!("../dtb/sifive.dtb");
-
-#[test]
-fn returns_fdt() {
- assert!(Fdt::new(TEST).is_ok());
-}
-
-#[test]
-fn finds_root_node() {
- let fdt = Fdt::new(TEST).unwrap();
- assert!(fdt.find_node("/").is_some(), "couldn't find root node");
-}
-
-#[test]
-fn finds_root_node_properties() {
- let fdt = Fdt::new(TEST).unwrap();
- let prop = fdt
- .find_node("/")
- .unwrap()
- .properties()
- .any(|p| p.name == "compatible" && p.value == b"riscv-virtio\0");
-
- assert!(prop);
-}
-
-#[test]
-fn finds_child_of_root_node() {
- let fdt = Fdt::new(TEST).unwrap();
- assert!(fdt.find_node("/cpus").is_some(), "couldn't find cpus node");
-}
-
-#[test]
-fn correct_flash_regions() {
- let fdt = Fdt::new(TEST).unwrap();
- let regions = fdt.find_node("/soc/flash").unwrap().reg().unwrap().collect::>();
-
- assert_eq!(
- regions,
- &[
- MemoryRegion { starting_address: 0x20000000 as *const u8, size: Some(0x2000000) },
- MemoryRegion { starting_address: 0x22000000 as *const u8, size: Some(0x2000000) }
- ]
- );
-}
-
-#[test]
-fn finds_with_addr() {
- let fdt = Fdt::new(TEST).unwrap();
- assert_eq!(fdt.find_node("/soc/virtio_mmio@10004000").unwrap().name, "virtio_mmio@10004000");
-}
-
-#[test]
-fn compatibles() {
- let fdt = Fdt::new(TEST).unwrap();
- let res = fdt
- .find_node("/soc/test")
- .unwrap()
- .compatible()
- .unwrap()
- .all()
- .all(|s| ["sifive,test1", "sifive,test0", "syscon"].contains(&s));
-
- assert!(res);
-}
-
-#[test]
-fn parent_cell_sizes() {
- let fdt = Fdt::new(TEST).unwrap();
- let regions = fdt.find_node("/memory").unwrap().reg().unwrap().collect::>();
-
- assert_eq!(
- regions,
- &[MemoryRegion { starting_address: 0x80000000 as *const u8, size: Some(0x20000000) }]
- );
-}
-
-#[test]
-fn no_properties() {
- let fdt = Fdt::new(TEST).unwrap();
- let regions = fdt.find_node("/emptyproptest").unwrap();
- assert_eq!(regions.properties().count(), 0);
-}
-
-#[test]
-fn finds_all_nodes() {
- let fdt = Fdt::new(TEST).unwrap();
-
- let mut all_nodes: std::vec::Vec<_> = fdt.all_nodes().map(|n| n.name).collect();
- all_nodes.sort_unstable();
-
- assert_eq!(
- all_nodes,
- &[
- "/",
- "chosen",
- "clint@2000000",
- "cluster0",
- "core0",
- "cpu-map",
- "cpu@0",
- "cpus",
- "emptyproptest",
- "flash@20000000",
- "interrupt-controller",
- "memory@80000000",
- "pci@30000000",
- "plic@c000000",
- "poweroff",
- "reboot",
- "rtc@101000",
- "soc",
- "test@100000",
- "uart@10000000",
- "virtio_mmio@10001000",
- "virtio_mmio@10002000",
- "virtio_mmio@10003000",
- "virtio_mmio@10004000",
- "virtio_mmio@10005000",
- "virtio_mmio@10006000",
- "virtio_mmio@10007000",
- "virtio_mmio@10008000"
- ]
- )
-}
-
-#[test]
-fn required_nodes() {
- let fdt = Fdt::new(TEST).unwrap();
- fdt.cpus().next().unwrap();
- fdt.memory();
- fdt.chosen();
-}
-
-#[test]
-fn doesnt_exist() {
- let fdt = Fdt::new(TEST).unwrap();
- assert!(fdt.find_node("/this/doesnt/exist").is_none());
-}
-
-#[test]
-fn raw_reg() {
- let fdt = Fdt::new(TEST).unwrap();
- let regions =
- fdt.find_node("/soc/flash").unwrap().raw_reg().unwrap().collect::>();
-
- assert_eq!(
- regions,
- &[
- RawReg { address: &0x20000000u64.to_be_bytes(), size: &0x2000000u64.to_be_bytes() },
- RawReg { address: &0x22000000u64.to_be_bytes(), size: &0x2000000u64.to_be_bytes() }
- ]
- );
-}
-
-#[test]
-fn issue_3() {
- let fdt = Fdt::new(ISSUE_3).unwrap();
- fdt.find_all_nodes("uart").for_each(|n| std::println!("{:?}", n));
-}
-
-#[test]
-fn issue_4() {
- let fdt = Fdt::new(ISSUE_3).unwrap();
- fdt.all_nodes().for_each(|n| std::println!("{:?}", n));
-}
-
-#[test]
-fn cpus() {
- let fdt = Fdt::new(TEST).unwrap();
- for cpu in fdt.cpus() {
- cpu.ids().all().for_each(|n| std::println!("{:?}", n));
- }
-}
-
-#[test]
-fn invalid_node() {
- let fdt = Fdt::new(TEST).unwrap();
- assert!(fdt.find_node("this/is/an invalid node///////////").is_none());
-}
-
-#[test]
-fn aliases() {
- let fdt = Fdt::new(SIFIVE).unwrap();
- let aliases = fdt.aliases().unwrap();
- for (_, node_path) in aliases.all() {
- assert!(fdt.find_node(node_path).is_some(), "path: {:?}", node_path);
- }
-}
-
-#[test]
-fn node_property_str_value() {
- let fdt = Fdt::new(TEST).unwrap();
- let cpu0 = fdt.find_node("/cpus/cpu@0").unwrap();
- assert_eq!(cpu0.property("riscv,isa").unwrap().as_str().unwrap(), "rv64imafdcsu");
-}
-
-#[test]
-fn model_value() {
- let fdt = Fdt::new(TEST).unwrap();
- assert_eq!(fdt.root().model(), "riscv-virtio,qemu");
-}
-
-#[test]
-fn memory_node() {
- let fdt = Fdt::new(TEST).unwrap();
- assert_eq!(fdt.memory().regions().count(), 1);
-}
-
-#[test]
-fn interrupt_cells() {
- let fdt = Fdt::new(TEST).unwrap();
- let uart = fdt.find_node("/soc/uart").unwrap();
- std::println!("{:?}", uart.parent_interrupt_cells());
- assert_eq!(uart.interrupts().unwrap().collect::>(), std::vec![0xA]);
-}