diff --git a/Cargo.toml b/Cargo.toml index 2f39c1c3..b45c1f06 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -51,23 +51,31 @@ raw-cpuid = "10.7.0" ############# general ############## iommu = [] # supported by: aarch64 pci = [] # supported by: aarch64 +no_autodetect_ncpus = [] + ############# aarch64 ############## # irqchip driver gicv2 = [] gicv3 = [] + # uart driver pl011 = [] xuartps = [] imx_uart = [] uart_16550 = [] + # pagetable layout pt_layout_qemu = [] pt_layout_rk3568 = [] -# cpu -a55 = [] -a53 = [] +pt_layout_rk3588 = [] + +# cpu +mpidr_rockchip = [] + # uart infos -rk3568_uart_base = [] +uart_base_rk3568 = [] +uart_base_rk3588 = [] + ############## riscv64 ############# # irqchip driver plic = [] @@ -85,4 +93,3 @@ loongson_uart = [] [profile.dev] # panic = "abort" # avoid cargo test failure, this is a bug of cargo debug = 2 -# panic = "abort" diff --git a/Makefile b/Makefile index dccf4599..7523ed3a 100644 --- a/Makefile +++ b/Makefile @@ -115,8 +115,7 @@ elf: disa: readelf -a $(hvisor_elf) > hvisor-elf.txt -# rust-objdump --disassemble $(hvisor_elf) > hvisor.S - rust-objdump --disassemble --source $(hvisor_elf) > hvisor.S + rust-objdump --disassemble --source --line-numbers $(hvisor_elf) > hvisor.S run: all $(QEMU) $(QEMU_ARGS) diff --git a/platform/aarch64/imx8mp/board.rs b/platform/aarch64/imx8mp/board.rs index 379ec996..555001f0 100644 --- a/platform/aarch64/imx8mp/board.rs +++ b/platform/aarch64/imx8mp/board.rs @@ -17,6 +17,8 @@ use crate::{arch::zone::HvArchZoneConfig, config::*}; pub const BOARD_NAME: &str = "imx8mp"; +pub const BOARD_NCPUS: usize = 4; + pub const ROOT_ZONE_DTB_ADDR: u64 = 0xa0000000; pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0xa0400000; pub const ROOT_ZONE_ENTRY: u64 = 0xa0400000; diff --git a/platform/aarch64/imx8mp/cargo/features b/platform/aarch64/imx8mp/cargo/features index e330a343..7acf44c6 100644 --- a/platform/aarch64/imx8mp/cargo/features +++ b/platform/aarch64/imx8mp/cargo/features @@ -1,3 +1,2 @@ gicv3 imx_uart -a53 diff --git a/platform/aarch64/qemu-gicv2/board.rs b/platform/aarch64/qemu-gicv2/board.rs index 4f405d3c..c9d6f8f8 100644 --- a/platform/aarch64/qemu-gicv2/board.rs +++ b/platform/aarch64/qemu-gicv2/board.rs @@ -17,6 +17,8 @@ use crate::{arch::zone::HvArchZoneConfig, config::*}; pub const BOARD_NAME: &str = "qemu-gicv2"; +pub const BOARD_NCPUS: usize = 4; + pub const ROOT_ZONE_DTB_ADDR: u64 = 0xa0000000; pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0xa0400000; pub const ROOT_ZONE_ENTRY: u64 = 0xa0400000; diff --git a/platform/aarch64/qemu-gicv2/cargo/features b/platform/aarch64/qemu-gicv2/cargo/features index efce9f0f..bd682521 100644 --- a/platform/aarch64/qemu-gicv2/cargo/features +++ b/platform/aarch64/qemu-gicv2/cargo/features @@ -2,5 +2,4 @@ gicv2 pl011 iommu pci -pt_layout_qemu -a53 \ No newline at end of file +pt_layout_qemu \ No newline at end of file diff --git a/platform/aarch64/qemu-gicv3/board.rs b/platform/aarch64/qemu-gicv3/board.rs index dcc9a72a..9ff4be52 100644 --- a/platform/aarch64/qemu-gicv3/board.rs +++ b/platform/aarch64/qemu-gicv3/board.rs @@ -15,7 +15,9 @@ // use crate::{arch::zone::HvArchZoneConfig, config::*}; -pub const BOARD_NAME: &str = "qemu-givc3"; +pub const BOARD_NAME: &str = "qemu-gicv3"; + +pub const BOARD_NCPUS: usize = 4; pub const ROOT_ZONE_DTB_ADDR: u64 = 0xa0000000; pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0xa0400000; diff --git a/platform/aarch64/qemu-gicv3/cargo/features b/platform/aarch64/qemu-gicv3/cargo/features index 0722dfa0..942d603a 100644 --- a/platform/aarch64/qemu-gicv3/cargo/features +++ b/platform/aarch64/qemu-gicv3/cargo/features @@ -2,5 +2,4 @@ gicv3 pl011 iommu pci -pt_layout_qemu -a53 \ No newline at end of file +pt_layout_qemu \ No newline at end of file diff --git a/platform/aarch64/rk3568/board.rs b/platform/aarch64/rk3568/board.rs index f1e2f214..737c0e77 100644 --- a/platform/aarch64/rk3568/board.rs +++ b/platform/aarch64/rk3568/board.rs @@ -2,6 +2,8 @@ use crate::{arch::zone::HvArchZoneConfig, config::*}; pub const BOARD_NAME: &str = "rk3568"; +pub const BOARD_NCPUS: usize = 4; + pub const ROOT_ZONE_DTB_ADDR: u64 = 0xa0000000; pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x60080000 ; pub const ROOT_ZONE_ENTRY: u64 = 0x60080000 ; diff --git a/platform/aarch64/rk3568/cargo/features b/platform/aarch64/rk3568/cargo/features index cf32460a..ca7d4a3d 100644 --- a/platform/aarch64/rk3568/cargo/features +++ b/platform/aarch64/rk3568/cargo/features @@ -1,5 +1,5 @@ gicv3 uart_16550 +uart_base_rk3568 pt_layout_rk3568 -rk3568_uart_base -a55 \ No newline at end of file +mpidr_rockchip \ No newline at end of file diff --git a/platform/aarch64/rk3588/board.rs b/platform/aarch64/rk3588/board.rs new file mode 100644 index 00000000..95680030 --- /dev/null +++ b/platform/aarch64/rk3588/board.rs @@ -0,0 +1,180 @@ +// Copyright (c) 2025 Syswonder +// hvisor is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR +// FIT FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. +// +// Syswonder Website: +// https://www.syswonder.org +// +// Authors: +// +use crate::{arch::zone::HvArchZoneConfig, config::*}; + +// [ 17.796762] node 0: [mem 0x0000000000200000-0x000000000047ffff] +// [ 17.797335] node 0: [mem 0x0000000000480000-0x000000000087ffff] +// [ 17.797907] node 0: [mem 0x0000000000880000-0x00000000083fffff] +// [ 17.798479] node 0: [mem 0x0000000009400000-0x00000000efffffff] +// [ 17.799053] node 0: [mem 0x0000000100000000-0x00000003fbffffff] +// [ 17.799628] node 0: [mem 0x00000003fc500000-0x00000003ffefffff] +// [ 17.800200] node 0: [mem 0x00000004f0000000-0x00000004ffffffff] + +pub const BOARD_NAME: &str = "rk3588"; + +pub const BOARD_NCPUS: usize = 8; + +pub const ROOT_ZONE_DTB_ADDR: u64 = 0x10000000; +pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x09400000; +pub const ROOT_ZONE_ENTRY: u64 = 0x09400000; +pub const ROOT_ZONE_CPUS: u64 = (1 << 0) | (1 << 1); + +pub const ROOT_ZONE_NAME: &str = "root-linux"; + +pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 9] = [ + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x100000, + virtual_start: 0x100000, + size: 0xf0000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x200000, + virtual_start: 0x200000, + size: 0x8200000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x9400000, + virtual_start: 0x9400000, + size: 0xe6c00000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x100000000, + virtual_start: 0x100000000, + size: 0x2fc000000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x3fc500000, + virtual_start: 0x3fc500000, + size: 0x3a00000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x4f0000000, + virtual_start: 0x4f0000000, + size: 0x10000000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfc000000, + virtual_start: 0xfc000000, + size: 0x2000000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfe800000, + virtual_start: 0xfe800000, + size: 0x800000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfe000000, + virtual_start: 0xfe000000, + size: 0x600000, + }, + // HvConfigMemoryRegion { + // mem_type: MEM_TYPE_RAM, + // physical_start: 0x0000000000200000, + // virtual_start: 0x0000000000200000, + // size: 0x00000000083fffff - 0x0000000000200000 + 1, + // }, // ram + // HvConfigMemoryRegion { + // mem_type: MEM_TYPE_RAM, + // physical_start: 0x0000000009400000, + // virtual_start: 0x0000000009400000, + // size: 0x00000000efffffff - 0x0000000009400000 + 1, + // }, // ram + // HvConfigMemoryRegion { + // mem_type: MEM_TYPE_RAM, + // physical_start: 0x0000000100000000, + // virtual_start: 0x0000000100000000, + // size: 0x00000003fbffffff - 0x0000000100000000 + 1, + // }, // ram + // HvConfigMemoryRegion { + // mem_type: MEM_TYPE_RAM, + // physical_start: 0x00000003fc500000, + // virtual_start: 0x00000003fc500000, + // size: 0x00000003ffefffff - 0x00000003fc500000 + 1, + // }, // ram + // HvConfigMemoryRegion { + // mem_type: MEM_TYPE_RAM, + // physical_start: 0x00000004f0000000, + // virtual_start: 0x00000004f0000000, + // size: 0x00000004ffffffff - 0x00000004f0000000 + 1, + // }, // ram + // HvConfigMemoryRegion { + // mem_type: MEM_TYPE_IO, + // physical_start: 0xfeb50000, + // virtual_start: 0xfeb50000, + // size: 0x100, + // }, // uart + // HvConfigMemoryRegion { + // mem_type: MEM_TYPE_IO, + // physical_start: 0xfd000000, + // virtual_start: 0xfd000000, + // size: 0x1000000, + // }, + // HvConfigMemoryRegion { + // mem_type: MEM_TYPE_IO, + // physical_start: 0x100000, + // virtual_start: 0x100000, + // size: 0x100000, + // } +]; + +// pub const ROOT_ZONE_IRQS: [u32; 10] = [39, 64, 235, 237, 309, 312, 360, 365, 429, 455]; +pub const ROOT_ZONE_IRQS: [u32; 29] = [ + 39, 41, 42, 43, 45, 46, 64, 120, 121, 235, 237, 247, 248, 250, 251, 252, 265, 266, 309, 312, + 313, 355, 360, 365, 423, 424, 425, 429, 455, +]; + +pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { + gicd_base: 0xfe600000, + gicd_size: 0x10000, + gicr_base: 0xfe680000, + gicr_size: 0x100000, + gicc_base: 0x8010000, + gicc_size: 0x10000, + gicc_offset: 0x0, + gich_base: 0x8030000, + gich_size: 0x10000, + gicv_base: 0x8040000, + gicv_size: 0x10000, + gits_base: 0x8080000, + gits_size: 0x20000, +}; + +pub const ROOT_PCI_CONFIG: HvPciConfig = HvPciConfig { + ecam_base: 0x4010000000, + ecam_size: 0x10000000, + io_base: 0x3eff0000, + io_size: 0x10000, + pci_io_base: 0x0, + mem32_base: 0x10000000, + mem32_size: 0x2eff0000, + pci_mem32_base: 0x10000000, + mem64_base: 0x8000000000, + mem64_size: 0x8000000000, + pci_mem64_base: 0x8000000000, +}; + +pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = []; + +pub const ROOT_PCI_DEVS: [u64; 2] = [0, 1 << 3]; diff --git a/platform/aarch64/rk3588/cargo/config.template.toml b/platform/aarch64/rk3588/cargo/config.template.toml new file mode 100644 index 00000000..85e2f56c --- /dev/null +++ b/platform/aarch64/rk3588/cargo/config.template.toml @@ -0,0 +1,7 @@ +[target.aarch64-unknown-none] +runner = "platform/__ARCH__/__BOARD__/test/runner.sh" +rustflags = [ + "-Clink-arg=-Tplatform/__ARCH__/__BOARD__/linker.ld", + "-Ctarget-feature=+a72,+v8a,+strict-align,-neon,-fp-armv8", + "-Cforce-frame-pointers=yes", +] \ No newline at end of file diff --git a/platform/aarch64/rk3588/cargo/features b/platform/aarch64/rk3588/cargo/features new file mode 100644 index 00000000..9e239f37 --- /dev/null +++ b/platform/aarch64/rk3588/cargo/features @@ -0,0 +1,6 @@ +gicv3 +uart_16550 +uart_base_rk3588 +pt_layout_rk3588 +mpidr_rockchip +no_autodetect_ncpus \ No newline at end of file diff --git a/platform/aarch64/rk3588/configs/zone1-linux-virtio.json b/platform/aarch64/rk3588/configs/zone1-linux-virtio.json new file mode 100644 index 00000000..26a8b889 --- /dev/null +++ b/platform/aarch64/rk3588/configs/zone1-linux-virtio.json @@ -0,0 +1,31 @@ +{ + "zones": [ + { + "id": 1, + "memory_region": [ + { + "zone0_ipa": "0x50000000", + "zonex_ipa": "0x50000000", + "size": "0x25000000" + } + ], + "devices": [ + { + "type": "blk", + "addr": "0xff9d0000", + "len": "0x200", + "irq": 78, + "img": "rootfs.ext4", + "status": "enable" + }, + { + "type": "console", + "addr": "0xff9e0000", + "len": "0x200", + "irq": 76, + "status": "enable" + } + ] + } + ] +} \ No newline at end of file diff --git a/platform/aarch64/rk3588/configs/zone1-linux.json b/platform/aarch64/rk3588/configs/zone1-linux.json new file mode 100644 index 00000000..e579f678 --- /dev/null +++ b/platform/aarch64/rk3588/configs/zone1-linux.json @@ -0,0 +1,50 @@ +{ + "arch": "arm64", + "name": "linux2", + "zone_id": 1, + "cpus": [2, 3], + "memory_regions": [ + { + "type": "ram", + "physical_start": "0x50000000", + "virtual_start": "0x50000000", + "size": "0x25000000" + }, + { + "type": "ram", + "physical_start": "0x0", + "virtual_start": "0x0", + "size": "0x200000" + }, + { + "type": "virtio", + "physical_start": "0xff9d0000", + "virtual_start": "0xff9d0000", + "size": "0x1000" + }, + { + "type": "virtio", + "physical_start": "0xff9e0000", + "virtual_start": "0xff9e0000", + "size": "0x1000" + } + ], + "interrupts": [76, 78], + "ivc_configs": [], + "kernel_filepath": "./Image-5.4", + "dtb_filepath": "./zone1-linux.dtb", + "kernel_load_paddr": "0x50400000", + "dtb_load_paddr": "0x50000000", + "entry_point": "0x50400000", + "kernel_args": "", + "arch_config": { + "gic_version": "v3", + "gicd_base": "0xfe600000", + "gicd_size": "0x10000", + "gicr_base": "0xfe680000", + "gicr_size": "0x100000", + "gits_base": "0x0", + "gits_size": "0x0" + } +} + diff --git a/platform/aarch64/rk3588/image/Makefile b/platform/aarch64/rk3588/image/Makefile new file mode 100644 index 00000000..2f795e7f --- /dev/null +++ b/platform/aarch64/rk3588/image/Makefile @@ -0,0 +1,8 @@ +DTS_FILES := $(wildcard *.dts) +DTB_FILES := $(DTS_FILES:.dts=.dtb) + +all: $(DTB_FILES) +%.dtb: %.dts + dtc -I dts -O dtb $< -o $@ +clean: + rm -f $(DTB_FILES) \ No newline at end of file diff --git a/platform/aarch64/rk3588/image/zone0.dts b/platform/aarch64/rk3588/image/zone0.dts new file mode 100644 index 00000000..daba0fab --- /dev/null +++ b/platform/aarch64/rk3588/image/zone0.dts @@ -0,0 +1,2228 @@ +/dts-v1/; + +/memreserve/ 0x0000000008300000 0x0000000000047000; +/ { + serial-number = "fe9d722c1f58159b"; + compatible = "rockchip,rk3588-evb7-v11\0rockchip,rk3588"; + interrupt-parent = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "Rockchip RK3588 EVB7 V11 Board"; + + memory { + reg = <0x00 0x200000 0x00 0x8200000 0x00 0x9400000 0x00 0xe6c00000 0x01 0x00 0x02 0xfc000000 0x03 0xfc500000 0x00 0x3a00000 0x04 0xf0000000 0x00 0x10000000>; + device_type = "memory"; + }; + + reserved-memory { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + ramoops@110000 { + compatible = "ramoops"; + reg = <0x00 0x110000 0x00 0xe0000>; + boot-log-size = <0x8000>; + boot-log-count = <0x01>; + console-size = <0x80000>; + pmsg-size = <0x30000>; + ftrace-size = <0x00>; + record-size = <0x14000>; + phandle = <0x4b0>; + }; + + hvisor@480000 { + no-map; + reg = <0x00 0x480000 0x00 0x400000>; + }; + + nonroot@50000000 { + no-map; + reg = <0x00 0x50000000 0x00 0x25000000>; + }; + }; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + + cpu-map { + cluster0 { + core0 { + cpu = <0x06>; + }; + core1 { + cpu = <0x07>; + }; + }; + }; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x00>; + enable-method = "psci"; + capacity-dmips-mhz = <0x212>; + clocks = <0x0e 0x00>; + cpu-idle-states = <0x10>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x80>; + next-level-cache = <0x11>; + #cooling-cells = <0x02>; + dynamic-power-coefficient = <0x64>; + cpu-supply = <0x12>; + mem-supply = <0x12>; + phandle = <0x06>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <0x212>; + clocks = <0x0e 0x00>; + cpu-idle-states = <0x10>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x80>; + next-level-cache = <0x13>; + phandle = <0x07>; + }; + + idle-states { + entry-method = "psci"; + cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x10000>; + entry-latency-us = <0x64>; + exit-latency-us = <0x78>; + min-residency-us = <0x3e8>; + phandle = <0x10>; + }; + }; + + l2-cache-l0 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x11>; + }; + + l2-cache-l1 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x13>; + }; + + l2-cache-l2 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x14>; + }; + + l2-cache-l3 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x15>; + }; + + l2-cache-b0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x17>; + }; + + l2-cache-b1 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x19>; + }; + + l2-cache-b2 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x1b>; + }; + + l2-cache-b3 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x1d>; + }; + + l3-cache { + compatible = "cache"; + cache-size = <0x300000>; + cache-line-size = <0x40>; + cache-sets = <0x1000>; + phandle = <0x1e>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0x01 0x07 0x08>; + interrupt-affinity = <0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d>; + phandle = <0x220>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + spll { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x29d7ab80>; + clock-output-names = "spll"; + phandle = <0x205>; + }; + + xin32k { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x8000>; + clock-output-names = "xin32k"; + phandle = <0x206>; + }; + + xin24m { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x16e3600>; + clock-output-names = "xin24m"; + phandle = <0x207>; + }; + + hclk_vo1@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08ec 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x264>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x05>; + }; + + aclk_vdpu_low_pre@fd7c08b0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08b0 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1bc>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x208>; + }; + + hclk_vo0@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08dc 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x26d>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x04>; + }; + + hclk_usb@fd7c08a8 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08a8 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x264>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x209>; + }; + + hclk_nvm@fd7c087c { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c087c 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x141>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x03>; + }; + + aclk_usb@fd7c08a8 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08a8 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x263>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x67>; + }; + + hclk_isp1_pre@fd7c0868 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c0868 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1e1>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x20a>; + }; + + aclk_isp1_pre@fd7c0868 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c0868 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1e0>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x20b>; + }; + + aclk_rkvdec0_pre@fd7c08a0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08a0 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1bc>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x20c>; + }; + + hclk_rkvdec0_pre@fd7c08a0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08a0 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1be>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x20d>; + }; + + aclk_rkvdec1_pre@fd7c08a4 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08a4 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1bc>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x20e>; + }; + + hclk_rkvdec1_pre@fd7c08a4 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08a4 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1be>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x20f>; + }; + + aclk_jpeg_decoder_pre@fd7c08b0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08b0 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1bc>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x210>; + }; + + aclk_rkvenc1_pre@fd7c08c0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08c0 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1c5>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x211>; + }; + + hclk_rkvenc1_pre@fd7c08c0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08c0 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1c4>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x212>; + }; + + aclk_hdcp0_pre@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08dc 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x26c>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x213>; + }; + + aclk_hdcp1_pre@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08ec 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x263>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x214>; + }; + + pclk_av1_pre@fd7c0910 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c0910 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1be>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x215>; + }; + + aclk_av1_pre@fd7c0910 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c0910 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1bc>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x216>; + }; + + hclk_sdio_pre@fd7c092c { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c092c 0x00 0x10>; + clock-names = "link"; + clocks = <0x03>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x217>; + }; + + pclk_vo0_grf@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08dc 0x00 0x04>; + clocks = <0x04>; + clock-names = "link"; + #clock-cells = <0x00>; + phandle = <0x6f>; + }; + + pclk_vo1_grf@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08ec 0x00 0x04>; + clocks = <0x05>; + clock-names = "link"; + #clock-cells = <0x00>; + phandle = <0x70>; + }; + + mclkin-i2s0 { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x00>; + clock-output-names = "i2s0_mclkin"; + phandle = <0x218>; + }; + + mclkin-i2s1 { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x00>; + clock-output-names = "i2s1_mclkin"; + phandle = <0x219>; + }; + + mclkin-i2s2 { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x00>; + clock-output-names = "i2s2_mclkin"; + phandle = <0x21a>; + }; + + mclkin-i2s3 { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x00>; + clock-output-names = "i2s3_mclkin"; + phandle = <0x21b>; + }; + + mclkout-i2s0@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x00 0xfd58c318 0x00 0x04>; + clocks = <0x02 0x39>; + #clock-cells = <0x00>; + clock-output-names = "i2s0_mclkout_to_io"; + rockchip,bit-shift = <0x00>; + rockchip,bit-set-to-disable; + rockchip,clk-ignore-unused; + phandle = <0x18d>; + }; + + mclkout-i2s1@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x00 0xfd58c318 0x00 0x04>; + clocks = <0x02 0x291>; + #clock-cells = <0x00>; + clock-output-names = "i2s1_mclkout_to_io"; + rockchip,bit-shift = <0x01>; + rockchip,bit-set-to-disable; + rockchip,clk-ignore-unused; + phandle = <0x21c>; + }; + + mclkout-i2s1@fd58a000 { + compatible = "rockchip,clk-out"; + reg = <0x00 0xfd58a000 0x00 0x04>; + clocks = <0x02 0x291>; + #clock-cells = <0x00>; + clock-output-names = "i2s1m1_mclkout_to_io"; + rockchip,bit-shift = <0x06>; + rockchip,clk-ignore-unused; + phandle = <0x21d>; + }; + + mclkout-i2s2@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x00 0xfd58c318 0x00 0x04>; + clocks = <0x02 0x28>; + #clock-cells = <0x00>; + clock-output-names = "i2s2_mclkout_to_io"; + rockchip,bit-shift = <0x02>; + rockchip,bit-set-to-disable; + rockchip,clk-ignore-unused; + phandle = <0x21e>; + }; + + mclkout-i2s3@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x00 0xfd58c318 0x00 0x04>; + clocks = <0x02 0x2e>; + #clock-cells = <0x00>; + clock-output-names = "i2s3_mclkout_to_io"; + rockchip,bit-shift = <0x07>; + rockchip,bit-set-to-disable; + rockchip,clk-ignore-unused; + phandle = <0x21f>; + }; + }; + + phy@fed80000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x00 0xfed80000 0x00 0x10000>; + rockchip,u2phy-grf = <0x194>; + rockchip,usb-grf = <0x71>; + rockchip,usbdpphy-grf = <0x195>; + rockchip,vo-grf = <0xfa>; + clocks = <0x02 0x2b6 0x02 0x27f 0x02 0x269 0x196>; + clock-names = "refclk\0immortal\0pclk\0utmi"; + resets = <0x02 0x28 0x02 0x29 0x02 0x2a 0x02 0x2b 0x02 0x482>; + reset-names = "init\0cmn\0lane\0pcs_apb\0pma_apb"; + status = "okay"; + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <0x104 0x00 0x00>; + sbu2-dc-gpios = <0x104 0x01 0x00>; + phandle = <0x301>; + + dp-port { + #phy-cells = <0x00>; + status = "okay"; + phandle = <0xfb>; + }; + + u3-port { + #phy-cells = <0x00>; + status = "okay"; + phandle = <0x64>; + }; + + port { + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x197>; + phandle = <0x189>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x198>; + phandle = <0x18a>; + }; + }; + }; + + phy@feda0000 { + compatible = "rockchip,rk3588-mipi-dcphy"; + reg = <0x00 0xfeda0000 0x00 0x10000>; + rockchip,grf = <0x199>; + clocks = <0x02 0x108 0x02 0x2b6>; + clock-names = "pclk\0ref"; + resets = <0x02 0xc0043 0x02 0x3e 0x02 0x3f 0x02 0xc0044>; + reset-names = "m_phy\0apb\0grf\0s_phy"; + #phy-cells = <0x00>; + status = "okay"; + phandle = <0x2f>; + }; + + phy@fedb0000 { + compatible = "rockchip,rk3588-mipi-dcphy"; + reg = <0x00 0xfedb0000 0x00 0x10000>; + rockchip,grf = <0x19a>; + clocks = <0x02 0x109 0x02 0x2b6>; + clock-names = "pclk\0ref"; + resets = <0x02 0xc0045 0x02 0x43 0x02 0x44 0x02 0xc0046>; + reset-names = "m_phy\0apb\0grf\0s_phy"; + #phy-cells = <0x00>; + status = "okay"; + phandle = <0x30>; + }; + + usbdrd3_0 { + compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3"; + clocks = <0x02 0x1a3 0x02 0x1a2 0x02 0x1a1>; + clock-names = "ref\0suspend\0bus"; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + status = "okay"; + phandle = <0x266>; + + usb@fc000000 { + compatible = "snps,dwc3"; + reg = <0x00 0xfc000000 0x00 0x400000>; + interrupts = <0x00 0xdc 0x04>; + power-domains = <0x5d 0x1f>; + resets = <0x02 0x2a4>; + reset-names = "usb3-otg"; + dr_mode = "otg"; + phys = <0x63 0x64>; + phy-names = "usb2-phy\0usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + quirk-skip-phy-init; + status = "okay"; + usb-role-switch; + phandle = <0x267>; + + port { + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x65>; + phandle = <0x188>; + }; + }; + }; + }; + + usb@fc800000 { + compatible = "rockchip,rk3588-ehci\0generic-ehci"; + reg = <0x00 0xfc800000 0x00 0x40000>; + interrupts = <0x00 0xd7 0x04>; + clocks = <0x02 0x19d 0x02 0x19e 0x66 0x67>; + clock-names = "usbhost\0arbiter\0utmi\0alk_usb"; + companion = <0x68>; + phys = <0x69>; + phy-names = "usb2-phy"; + power-domains = <0x5d 0x1f>; + status = "okay"; + phandle = <0x268>; + }; + + usb@fc840000 { + compatible = "rockchip,rk3588-ohci\0generic-ohci"; + reg = <0x00 0xfc840000 0x00 0x40000>; + interrupts = <0x00 0xd8 0x04>; + clocks = <0x02 0x19d 0x02 0x19e 0x66 0x67>; + clock-names = "usbhost\0arbiter\0utmi\0alk_usb"; + phys = <0x69>; + phy-names = "usb2-phy"; + power-domains = <0x5d 0x1f>; + status = "okay"; + phandle = <0x68>; + }; + + usb@fc880000 { + compatible = "rockchip,rk3588-ehci\0generic-ehci"; + reg = <0x00 0xfc880000 0x00 0x40000>; + interrupts = <0x00 0xda 0x04>; + clocks = <0x02 0x19f 0x02 0x1a0 0x6a 0x67>; + clock-names = "usbhost\0arbiter\0utmi\0alk_usb"; + companion = <0x6b>; + phys = <0x6c>; + phy-names = "usb2-phy"; + power-domains = <0x5d 0x1f>; + status = "okay"; + phandle = <0x269>; + }; + + usb@fc8c0000 { + compatible = "rockchip,rk3588-ohci\0generic-ohci"; + reg = <0x00 0xfc8c0000 0x00 0x40000>; + interrupts = <0x00 0xdb 0x04>; + clocks = <0x02 0x19f 0x02 0x1a0 0x6a 0x67>; + clock-names = "usbhost\0arbiter\0utmi\0alk_usb"; + phys = <0x6c>; + phy-names = "usb2-phy"; + power-domains = <0x5d 0x1f>; + status = "okay"; + phandle = <0x6b>; + }; + + interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x03>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + interrupt-controller; + reg = <0x00 0xfe600000 0x00 0x10000 0x00 0xfe680000 0x00 0x100000>; + interrupts = <0x01 0x09 0x04>; + phandle = <0x01>; + }; + + clock-controller@fd7c0000 { + compatible = "rockchip,rk3588-cru"; + rockchip,grf = <0x73>; + reg = <0x00 0xfd7c0000 0x00 0x5c000>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + assigned-clocks = <0x02 0x09 0x02 0x05 0x02 0x08 0x02 0x07 0x02 0xd8 0x02 0xda 0x02 0xd9 0x02 0x10e 0x02 0x10f 0x02 0x110 0x02 0x299 0x02 0x29a 0x02 0x7b 0x02 0xec 0x02 0x114 0x02 0x208 0x02 0x20e 0x02 0x21f 0x02 0x77>; + assigned-clock-rates = <0x4190ab00 0x2ee00000 0x32a9f880 0x46cf7100 0x29d7ab80 0x17d78400 0x1dcd6500 0x2cb41780 0x5f5e100 0x17d78400 0x5f5e100 0xbebc200 0x165a0bc0 0x8f0d180 0xbebc200 0xb71b00 0xb71b00 0x5e69ec0 0x1312d00>; + phandle = <0x02>; + }; + + pinctrl { + compatible = "rockchip,rk3588-pinctrl"; + rockchip,grf = <0x19f>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + phandle = <0x1a0>; + + gpio@fd8a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfd8a0000 0x00 0x100>; + interrupts = <0x00 0x115 0x04>; + clocks = <0x02 0x284 0x02 0x285>; + gpio-controller; + #gpio-cells = <0x02>; + gpio-ranges = <0x1a0 0x00 0x00 0x20>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0xf2>; + }; + + gpio@fec40000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfec40000 0x00 0x100>; + interrupts = <0x00 0x118 0x04>; + clocks = <0x02 0x81 0x02 0x82>; + gpio-controller; + #gpio-cells = <0x02>; + gpio-ranges = <0x1a0 0x00 0x60 0x20>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x113>; + }; + + gpio@fec50000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfec50000 0x00 0x100>; + interrupts = <0x00 0x119 0x04>; + clocks = <0x02 0x83 0x02 0x84>; + gpio-controller; + #gpio-cells = <0x02>; + gpio-ranges = <0x1a0 0x00 0x80 0x20>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x104>; + }; + + pcfg-pull-up { + bias-pull-up; + phandle = <0x1a6>; + }; + + pcfg-pull-down { + bias-pull-down; + phandle = <0x1aa>; + }; + + pcfg-pull-none { + bias-disable; + phandle = <0x1a1>; + }; + + pcfg-pull-none-drv-level-0 { + bias-disable; + drive-strength = <0x00>; + phandle = <0x303>; + }; + + pcfg-pull-none-drv-level-1 { + bias-disable; + drive-strength = <0x01>; + phandle = <0x304>; + }; + + pcfg-pull-none-drv-level-2 { + bias-disable; + drive-strength = <0x02>; + phandle = <0x1a9>; + }; + + pcfg-pull-none-drv-level-3 { + bias-disable; + drive-strength = <0x03>; + phandle = <0x305>; + }; + + pcfg-pull-none-drv-level-4 { + bias-disable; + drive-strength = <0x04>; + phandle = <0x306>; + }; + + pcfg-pull-none-drv-level-5 { + bias-disable; + drive-strength = <0x05>; + phandle = <0x307>; + }; + + pcfg-pull-none-drv-level-6 { + bias-disable; + drive-strength = <0x06>; + phandle = <0x308>; + }; + + pcfg-pull-up-drv-level-0 { + bias-pull-up; + drive-strength = <0x00>; + phandle = <0x309>; + }; + + pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <0x01>; + phandle = <0x1a8>; + }; + + pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <0x02>; + phandle = <0x1a2>; + }; + + pcfg-pull-up-drv-level-3 { + bias-pull-up; + drive-strength = <0x03>; + phandle = <0x30a>; + }; + + pcfg-pull-up-drv-level-4 { + bias-pull-up; + drive-strength = <0x04>; + phandle = <0x30b>; + }; + + pcfg-pull-up-drv-level-5 { + bias-pull-up; + drive-strength = <0x05>; + phandle = <0x30c>; + }; + + pcfg-pull-up-drv-level-6 { + bias-pull-up; + drive-strength = <0x06>; + phandle = <0x1a7>; + }; + + pcfg-pull-down-drv-level-0 { + bias-pull-down; + drive-strength = <0x00>; + phandle = <0x30d>; + }; + + pcfg-pull-down-drv-level-1 { + bias-pull-down; + drive-strength = <0x01>; + phandle = <0x30e>; + }; + + pcfg-pull-down-drv-level-2 { + bias-pull-down; + drive-strength = <0x02>; + phandle = <0x30f>; + }; + + pcfg-pull-down-drv-level-3 { + bias-pull-down; + drive-strength = <0x03>; + phandle = <0x310>; + }; + + pcfg-pull-down-drv-level-4 { + bias-pull-down; + drive-strength = <0x04>; + phandle = <0x311>; + }; + + pcfg-pull-down-drv-level-5 { + bias-pull-down; + drive-strength = <0x05>; + phandle = <0x312>; + }; + + pcfg-pull-down-drv-level-6 { + bias-pull-down; + drive-strength = <0x06>; + phandle = <0x313>; + }; + + pcfg-pull-up-smt { + bias-pull-up; + input-schmitt-enable; + phandle = <0x314>; + }; + + pcfg-pull-down-smt { + bias-pull-down; + input-schmitt-enable; + phandle = <0x315>; + }; + + pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + phandle = <0x1a5>; + }; + + pcfg-pull-none-drv-level-0-smt { + bias-disable; + drive-strength = <0x00>; + input-schmitt-enable; + phandle = <0x316>; + }; + + pcfg-pull-none-drv-level-1-smt { + bias-disable; + drive-strength = <0x01>; + input-schmitt-enable; + phandle = <0x1a4>; + }; + + pcfg-pull-none-drv-level-2-smt { + bias-disable; + drive-strength = <0x02>; + input-schmitt-enable; + phandle = <0x317>; + }; + + pcfg-pull-none-drv-level-3-smt { + bias-disable; + drive-strength = <0x03>; + input-schmitt-enable; + phandle = <0x318>; + }; + + pcfg-pull-none-drv-level-4-smt { + bias-disable; + drive-strength = <0x04>; + input-schmitt-enable; + phandle = <0x319>; + }; + + pcfg-pull-none-drv-level-5-smt { + bias-disable; + drive-strength = <0x05>; + input-schmitt-enable; + phandle = <0x1a3>; + }; + + pcfg-pull-none-drv-level-6-smt { + bias-disable; + drive-strength = <0x06>; + input-schmitt-enable; + phandle = <0x31a>; + }; + + pcfg-output-high { + output-high; + phandle = <0x31b>; + }; + + pcfg-output-high-pull-up { + output-high; + bias-pull-up; + phandle = <0x31c>; + }; + + pcfg-output-high-pull-down { + output-high; + bias-pull-down; + phandle = <0x31d>; + }; + + pcfg-output-high-pull-none { + output-high; + bias-disable; + phandle = <0x31e>; + }; + + pcfg-output-low { + output-low; + phandle = <0x1ab>; + }; + + pcfg-output-low-pull-up { + output-low; + bias-pull-up; + phandle = <0x31f>; + }; + + pcfg-output-low-pull-down { + output-low; + bias-pull-down; + phandle = <0x320>; + }; + + pcfg-output-low-pull-none { + output-low; + bias-disable; + phandle = <0x321>; + }; + + uart2 { + + uart2m0-xfer { + rockchip,pins = <0x00 0x0e 0x0a 0x1a6 0x00 0x0d 0x0a 0x1a6>; + phandle = <0x202>; + }; + + uart2m1-xfer { + rockchip,pins = <0x04 0x19 0x0a 0x1a6 0x04 0x18 0x0a 0x1a6>; + phandle = <0x16d>; + }; + + uart2m2-xfer { + rockchip,pins = <0x03 0x0a 0x0a 0x1a6 0x03 0x09 0x0a 0x1a6>; + phandle = <0x438>; + }; + + uart2-ctsn { + rockchip,pins = <0x03 0x0c 0x0a 0x1a1>; + phandle = <0x439>; + }; + + uart2-rtsn { + rockchip,pins = <0x03 0x0b 0x0a 0x1a1>; + phandle = <0x43a>; + }; + }; + + + sdmmc { + + sdmmc-bus4 { + rockchip,pins = <0x04 0x18 0x01 0x1a2 0x04 0x19 0x01 0x1a2 0x04 0x1a 0x01 0x1a2 0x04 0x1b 0x01 0x1a2>; + phandle = <0x11d>; + }; + + sdmmc-clk { + rockchip,pins = <0x04 0x1d 0x01 0x1a2>; + phandle = <0x11a>; + }; + + sdmmc-cmd { + rockchip,pins = <0x04 0x1c 0x01 0x1a2>; + phandle = <0x11b>; + }; + + sdmmc-det { + rockchip,pins = <0x00 0x04 0x01 0x1a6>; + phandle = <0x11c>; + }; + + sdmmc-pwren { + rockchip,pins = <0x00 0x05 0x02 0x1a1>; + phandle = <0x402>; + }; + + sd-s0-pwr { + rockchip,pins = <0x00 0x0f 0x00 0x1a6>; + phandle = <0x1fb>; + }; + }; + + gpio-func { + + tsadc-gpio-func { + rockchip,pins = <0x00 0x01 0x00 0x1a1>; + phandle = <0x182>; + }; + }; + + tsadc { + + tsadcm1-shut { + rockchip,pins = <0x00 0x02 0x02 0x1a1>; + phandle = <0x42a>; + }; + + tsadc-shut { + rockchip,pins = <0x00 0x01 0x02 0x1a1>; + phandle = <0x183>; + }; + + tsadc-shut-org { + rockchip,pins = <0x00 0x01 0x01 0x1a1>; + phandle = <0x42b>; + }; + }; + + spi2 { + spi2m2-pins { + rockchip,pins = <0x00 0x05 0x01 0x1a8 0x00 0x0b 0x01 0x1a8 0x00 0x06 0x01 0x1a8>; + phandle = <0x161>; + }; + + spi2m2-cs0 { + rockchip,pins = <0x00 0x09 0x01 0x1a8>; + phandle = <0x160>; + }; + }; + + pmic { + pmic-pins { + rockchip,pins = <0x00 0x07 0x00 0x1a6 0x00 0x02 0x01 0x1a1 0x00 0x03 0x01 0x1a1 0x00 0x11 0x01 0x1a1 0x00 0x12 0x01 0x1a1 0x00 0x13 0x01 0x1a1 0x00 0x1e 0x01 0x1a1>; + phandle = <0x162>; + }; + }; + + + gmac1 { + + gmac1-miim { + rockchip,pins = <0x03 0x12 0x01 0x1a1 0x03 0x13 0x01 0x1a1>; + phandle = <0x114>; + }; + + gmac1-clkinout { + rockchip,pins = <0x03 0x0e 0x01 0x1a1>; + phandle = <0x342>; + }; + + gmac1-rx-bus2 { + rockchip,pins = <0x03 0x07 0x01 0x1a1 0x03 0x08 0x01 0x1a1 0x03 0x09 0x01 0x1a1>; + phandle = <0x116>; + }; + + gmac1-tx-bus2 { + rockchip,pins = <0x03 0x0b 0x01 0x1a1 0x03 0x0c 0x01 0x1a1 0x03 0x0d 0x01 0x1a1>; + phandle = <0x115>; + }; + + gmac1-rgmii-clk { + rockchip,pins = <0x03 0x05 0x01 0x1a1 0x03 0x04 0x01 0x1a1>; + phandle = <0x117>; + }; + + gmac1-rgmii-bus { + rockchip,pins = <0x03 0x02 0x01 0x1a1 0x03 0x03 0x01 0x1a1 0x03 0x00 0x01 0x1a1 0x03 0x01 0x01 0x1a1>; + phandle = <0x118>; + }; + + gmac1-ppsclk { + rockchip,pins = <0x03 0x11 0x01 0x1a1>; + phandle = <0x343>; + }; + + gmac1-ppstrig { + rockchip,pins = <0x03 0x10 0x01 0x1a1>; + phandle = <0x344>; + }; + + gmac1-ptp-ref-clk { + rockchip,pins = <0x03 0x0f 0x01 0x1a1>; + phandle = <0x345>; + }; + + gmac1-txer { + rockchip,pins = <0x03 0x0a 0x01 0x1a1>; + phandle = <0x346>; + }; + }; + }; + + syscon@fd588000 { + compatible = "rockchip,rk3588-pmu0-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfd588000 0x00 0x2000>; + phandle = <0x26e>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x80>; + mode-bootloader = <0x5242c301>; + mode-charge = <0x5242c30b>; + mode-fastboot = <0x5242c309>; + mode-loader = <0x5242c301>; + mode-normal = <0x5242c300>; + mode-recovery = <0x5242c303>; + mode-ums = <0x5242c30c>; + mode-panic = <0x5242c307>; + mode-watchdog = <0x5242c308>; + mode-quiescent = <0x5242c30e>; + mode-winusb = <0x5242c30f>; + phandle = <0x26f>; + }; + }; + + syscon@fd58a000 { + compatible = "rockchip,rk3588-pmu1-grf\0syscon"; + reg = <0x00 0xfd58a000 0x00 0x2000>; + phandle = <0x10a>; + }; + + // syscon@fd58c000 { + // compatible = "rockchip,rk3588-sys-grf\0syscon\0simple-mfd"; + // reg = <0x00 0xfd58c000 0x00 0x1000>; + // phandle = <0xc3>; + + // rgb { + // compatible = "rockchip,rk3588-rgb"; + // pinctrl-names = "default"; + // pinctrl-0 = <0x6e>; + // status = "disabled"; + // phandle = <0x270>; + + // ports { + // #address-cells = <0x01>; + // #size-cells = <0x00>; + + // port@0 { + // reg = <0x00>; + // #address-cells = <0x01>; + // #size-cells = <0x00>; + + // endpoint@2 { + // reg = <0x02>; + // remote-endpoint = <0x3a>; + // status = "disabled"; + // phandle = <0xeb>; + // }; + // }; + // }; + // }; + // }; + + syscon@fd590000 { + compatible = "rockchip,rk3588-bigcore0-grf\0syscon"; + reg = <0x00 0xfd590000 0x00 0x100>; + phandle = <0x26>; + }; + + syscon@fd592000 { + compatible = "rockchip,rk3588-bigcore1-grf\0syscon"; + reg = <0x00 0xfd592000 0x00 0x100>; + phandle = <0x29>; + }; + + syscon@fd594000 { + compatible = "rockchip,rk3588-litcore-grf\0syscon"; + reg = <0x00 0xfd594000 0x00 0x100>; + phandle = <0x22>; + }; + + syscon@fd598000 { + compatible = "rockchip,rk3588-dsu-grf\0syscon"; + reg = <0x00 0xfd598000 0x00 0x100>; + phandle = <0x23>; + }; + + syscon@fd5a0000 { + compatible = "rockchip,rk3588-gpu-grf\0syscon"; + reg = <0x00 0xfd5a0000 0x00 0x100>; + phandle = <0x62>; + }; + + syscon@fd5a2000 { + compatible = "rockchip,rk3588-npu-grf\0syscon"; + reg = <0x00 0xfd5a2000 0x00 0x100>; + phandle = <0xb0>; + }; + + syscon@fd5a4000 { + compatible = "rockchip,rk3588-vop-grf\0syscon"; + reg = <0x00 0xfd5a4000 0x00 0x2000>; + phandle = <0xd2>; + }; + + syscon@fd5a6000 { + compatible = "rockchip,rk3588-vo-grf\0syscon"; + reg = <0x00 0xfd5a6000 0x00 0x2000>; + clocks = <0x6f>; + phandle = <0xfa>; + }; + + syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf\0syscon"; + reg = <0x00 0xfd5a8000 0x00 0x100>; + clocks = <0x70>; + phandle = <0xd3>; + }; + + syscon@fd5ac000 { + compatible = "rockchip,rk3588-usb-grf\0syscon"; + reg = <0x00 0xfd5ac000 0x00 0x4000>; + phandle = <0x71>; + }; + + syscon@fd5b0000 { + compatible = "rockchip,rk3588-php-grf\0syscon"; + reg = <0x00 0xfd5b0000 0x00 0x1000>; + phandle = <0x73>; + }; + + syscon@fd5b4000 { + compatible = "rockchip,mipi-dphy-grf\0syscon"; + reg = <0x00 0xfd5b4000 0x00 0x1000>; + phandle = <0x19b>; + }; + + syscon@fd5b5000 { + compatible = "rockchip,mipi-dphy-grf\0syscon"; + reg = <0x00 0xfd5b5000 0x00 0x1000>; + phandle = <0x19c>; + }; + + syscon@fd5bc000 { + compatible = "rockchip,pipe-phy-grf\0syscon"; + reg = <0x00 0xfd5bc000 0x00 0x100>; + phandle = <0x19d>; + }; + + syscon@fd5c4000 { + compatible = "rockchip,pipe-phy-grf\0syscon"; + reg = <0x00 0xfd5c4000 0x00 0x100>; + phandle = <0x19e>; + }; + + syscon@fd5c8000 { + compatible = "rockchip,rk3588-usbdpphy-grf\0syscon"; + reg = <0x00 0xfd5c8000 0x00 0x4000>; + phandle = <0x195>; + }; + + syscon@fd5d0000 { + compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfd5d0000 0x00 0x4000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x194>; + + usb2-phy@0 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x00 0x10>; + interrupts = <0x00 0x189 0x04>; + resets = <0x02 0xc0047 0x02 0x488>; + reset-names = "phy\0apb"; + clocks = <0x02 0x2b5>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0x00>; + rockchip,usbctrl-grf = <0x71>; + status = "okay"; + phandle = <0x196>; + + otg-port { + #phy-cells = <0x00>; + status = "okay"; + rockchip,typec-vbus-det; + phandle = <0x63>; + }; + }; + }; + + syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfd5d8000 0x00 0x4000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x271>; + + usb2-phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + interrupts = <0x00 0x187 0x04>; + resets = <0x02 0xc0049 0x02 0x48a>; + reset-names = "phy\0apb"; + clocks = <0x02 0x2b5>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy2"; + #clock-cells = <0x00>; + status = "okay"; + phandle = <0x66>; + + host-port { + #phy-cells = <0x00>; + status = "okay"; + phy-supply = <0x72>; + phandle = <0x69>; + }; + }; + }; + + syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfd5dc000 0x00 0x4000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x272>; + + usb2-phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + interrupts = <0x00 0x188 0x04>; + resets = <0x02 0xc004a 0x02 0x48b>; + reset-names = "phy\0apb"; + clocks = <0x02 0x2b5>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy3"; + #clock-cells = <0x00>; + status = "okay"; + phandle = <0x6a>; + + host-port { + #phy-cells = <0x00>; + status = "okay"; + phy-supply = <0x72>; + phandle = <0x6c>; + }; + }; + }; + + syscon@fd5e0000 { + compatible = "rockchip,rk3588-hdptxphy-grf\0syscon"; + reg = <0x00 0xfd5e0000 0x00 0x100>; + phandle = <0x193>; + }; + + syscon@fd5e8000 { + compatible = "rockchip,mipi-dcphy-grf\0syscon"; + reg = <0x00 0xfd5e8000 0x00 0x4000>; + phandle = <0x199>; + }; + + syscon@fd5ec000 { + compatible = "rockchip,mipi-dcphy-grf\0syscon"; + reg = <0x00 0xfd5ec000 0x00 0x4000>; + phandle = <0x19a>; + }; + + syscon@fd5f0000 { + compatible = "rockchip,rk3588-ioc\0syscon"; + reg = <0x00 0xfd5f0000 0x00 0x10000>; + phandle = <0x19f>; + }; + + mmc@fe2e0000 { + compatible = "rockchip,rk3588-dwcmshc\0rockchip,dwcmshc-sdhci"; + reg = <0x00 0xfe2e0000 0x00 0x10000>; + interrupts = <0x00 0xcd 0x04>; + assigned-clocks = <0x02 0x13b 0x02 0x13c 0x02 0x13a>; + assigned-clock-rates = <0xbebc200 0x16e3600 0xbebc200>; + clocks = <0x02 0x13a 0x02 0x138 0x02 0x139 0x02 0x13b 0x02 0x13c>; + clock-names = "core\0bus\0axi\0block\0timer"; + resets = <0x02 0x1f6 0x02 0x1f4 0x02 0x1f5 0x02 0x1f7 0x02 0x1f8>; + reset-names = "core\0bus\0axi\0block\0timer"; + max-frequency = <0xbebc200>; + status = "okay"; + bus-width = <0x08>; + no-sdio; + no-sd; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + phandle = <0x2aa>; + }; + + + firmware { + scmi { + compatible = "arm,scmi-smc"; + shmem = <0x43>; + arm,smc-id = <0x82000010>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x234>; + + protocol@14 { + reg = <0x14>; + #clock-cells = <0x01>; + assigned-clocks = <0x0e 0x00 0x0e 0x02 0x0e 0x03>; + assigned-clock-rates = <0x30a32c00 0x30a32c00 0x30a32c00>; + phandle = <0x0e>; + }; + + protocol@16 { + reg = <0x16>; + #reset-cells = <0x01>; + phandle = <0x122>; + }; + }; + + sdei { + compatible = "arm,sdei-1.0"; + method = "smc"; + phandle = <0x235>; + }; + + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + phandle = <0x236>; + }; + }; + + sram@10f000 { + compatible = "mmio-sram"; + reg = <0x00 0x10f000 0x00 0x100>; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges = <0x00 0x00 0x10f000 0x100>; + + sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x00 0x100>; + phandle = <0x43>; + }; + }; + + serial@feb50000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfeb50000 0x00 0x100>; + interrupts = <0x00 0x14d 0x04>; + clocks = <0x02 0xbb 0x02 0xac>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x16d>; + status = "disabled"; + phandle = <0x2e2>; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0x00>; + rockchip,wake-irq = <0x00>; + rockchip,irq-mode-enable = <0x01>; + rockchip,baudrate = <0x16e360>; + interrupts = <0x00 0x1a7 0x08>; + pinctrl-names = "default"; + pinctrl-0 = <0x202>; + status = "okay"; + phandle = <0x4bf>; + }; + + mmc@fe2c0000 { + compatible = "rockchip,rk3588-dw-mshc\0rockchip,rk3288-dw-mshc"; + reg = <0x00 0xfe2c0000 0x00 0x4000>; + interrupts = <0x00 0xcb 0x04>; + clocks = <0x0e 0x17 0x0e 0x09 0x02 0x2c2 0x02 0x2c3>; + clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <0x8f0d180>; + pinctrl-names = "default"; + pinctrl-0 = <0x11a 0x11b 0x11c 0x11d>; + power-domains = <0x5d 0x28>; + status = "okay"; + no-sdio; + no-mmc; + bus-width = <0x04>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <0x11e>; + vmmc-supply = <0x11f>; + phandle = <0x2a8>; + }; + + vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + vin-supply = <0x1e7>; + phandle = <0x75>; + }; + + + vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + gpio = <0xf2 0x0f 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <0x1fb>; + regulator-name = "vcc_3v3_sd_s0"; + enable-active-high; + phandle = <0x11f>; + }; + + tsadc@fec00000 { + compatible = "rockchip,rk3588-tsadc"; + reg = <0x00 0xfec00000 0x00 0x400>; + interrupts = <0x00 0x18d 0x04>; + clocks = <0x02 0xaa 0x02 0xa9>; + clock-names = "tsadc\0apb_pclk"; + assigned-clocks = <0x02 0xaa>; + assigned-clock-rates = <0x1e8480>; + resets = <0x02 0xc1 0x02 0xc0>; + reset-names = "tsadc\0tsadc-apb"; + #thermal-sensor-cells = <0x01>; + rockchip,hw-tshut-temp = <0x1d4c0>; + rockchip,hw-tshut-mode = <0x00>; + rockchip,hw-tshut-polarity = <0x00>; + pinctrl-names = "gpio\0otpout"; + pinctrl-0 = <0x182>; + pinctrl-1 = <0x183>; + status = "okay"; + phandle = <0x5a>; + }; + + power-management@fd8d8000 { + compatible = "rockchip,rk3588-pmu\0syscon\0simple-mfd"; + reg = <0x00 0xfd8d8000 0x00 0x400>; + phandle = <0xd4>; + + power-controller { + compatible = "rockchip,rk3588-power-controller"; + #power-domain-cells = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x5d>; + + power-domain@8 { + reg = <0x08>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + power-domain@9 { + reg = <0x09>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0x12f 0x02 0x131 0x02 0x130 0x02 0x126>; + pm_qos = <0x7c 0x7d 0x7e>; + + power-domain@10 { + reg = <0x0a>; + clocks = <0x02 0x12f 0x02 0x131 0x02 0x130>; + pm_qos = <0x7f>; + }; + + power-domain@11 { + reg = <0x0b>; + clocks = <0x02 0x12f 0x02 0x131 0x02 0x130>; + pm_qos = <0x80>; + }; + }; + }; + + power-domain@12 { + reg = <0x0c>; + clocks = <0x02 0x114 0x02 0x115 0x02 0x116>; + pm_qos = <0x81 0x82 0x83 0x84>; + }; + + power-domain@13 { + reg = <0x0d>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + power-domain@14 { + reg = <0x0e>; + clocks = <0x02 0x18f 0x02 0x1be 0x02 0x1bc 0x02 0x190 0x02 0x18e>; + pm_qos = <0x85>; + }; + + power-domain@15 { + reg = <0x0f>; + clocks = <0x02 0x194 0x02 0x1be 0x02 0x1bc 0x02 0x195>; + pm_qos = <0x86>; + }; + + power-domain@16 { + reg = <0x10>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0x1c4 0x02 0x1c5>; + pm_qos = <0x87 0x88 0x89>; + + power-domain@17 { + reg = <0x11>; + clocks = <0x02 0x1c9 0x02 0x1c4 0x02 0x1c5 0x02 0x1ca>; + pm_qos = <0x8a 0x8b 0x8c>; + }; + }; + }; + + power-domain@21 { + reg = <0x15>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0x1be 0x02 0x1bd 0x02 0x1bc 0x02 0x1bf 0x02 0x1aa 0x02 0x1a9 0x02 0x1ac 0x02 0x1ad 0x02 0x1ae 0x02 0x1af 0x02 0x1b0 0x02 0x1b1 0x02 0x1b2 0x02 0x1b3 0x02 0x1b4 0x02 0x1b5 0x02 0x1b7 0x02 0x1b6>; + pm_qos = <0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94>; + + power-domain@23 { + reg = <0x17>; + clocks = <0x02 0x4b 0x02 0x49 0x02 0x1be>; + pm_qos = <0x95>; + }; + + power-domain@14 { + reg = <0x0e>; + clocks = <0x02 0x18f 0x02 0x1be 0x02 0x1bc 0x02 0x190>; + pm_qos = <0x85>; + }; + + power-domain@15 { + reg = <0x0f>; + clocks = <0x02 0x194 0x02 0x1be 0x02 0x1bc>; + pm_qos = <0x86>; + }; + + power-domain@22 { + reg = <0x16>; + clocks = <0x02 0x1ba 0x02 0x1b9>; + pm_qos = <0x96>; + }; + }; + + power-domain@24 { + reg = <0x18>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0x26e 0x02 0x26d 0x02 0x270>; + pm_qos = <0x97 0x98>; + + power-domain@25 { + reg = <0x19>; + clocks = <0x02 0x1f6 0x02 0x1f7 0x02 0x1f5 0x02 0x1f3 0x02 0x1ee 0x02 0x1ed 0x02 0x26d>; + pm_qos = <0x99>; + }; + }; + + power-domain@26 { + reg = <0x1a>; + clocks = <0x02 0x22e 0x02 0x22f 0x02 0x22d 0x02 0x218 0x02 0x217 0x02 0x22b 0x02 0x264>; + pm_qos = <0x9a 0x9b>; + }; + + power-domain@27 { + reg = <0x1b>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0x1e1 0x02 0x1e2 0x02 0x1df 0x02 0x1de 0x02 0x1e5 0x02 0x1e4>; + pm_qos = <0x9c 0x9d 0x9e 0x9f>; + + power-domain@28 { + reg = <0x1c>; + clocks = <0x02 0x121 0x02 0x120 0x02 0x1e1 0x02 0x1e2>; + pm_qos = <0xa0 0xa1>; + }; + + power-domain@29 { + reg = <0x1d>; + clocks = <0x02 0x1d6 0x02 0x1d5 0x02 0x1d9 0x02 0x1d8 0x02 0x1e2>; + pm_qos = <0xa2 0xa3>; + }; + }; + + power-domain@30 { + reg = <0x1e>; + clocks = <0x02 0x189 0x02 0x18a>; + pm_qos = <0xa4>; + }; + + power-domain@31 { + reg = <0x1f>; + clocks = <0x02 0x166 0x02 0x1a1 0x02 0x1a4 0x02 0x19d 0x02 0x19e 0x02 0x19f 0x02 0x1a0>; + pm_qos = <0xa5 0xa6 0xa7 0xa8>; + }; + + power-domain@33 { + reg = <0x21>; + clocks = <0x02 0x166 0x02 0x169 0x02 0x16a>; + }; + + power-domain@34 { + reg = <0x22>; + clocks = <0x02 0x166 0x02 0x169 0x02 0x16a>; + }; + + power-domain@37 { + reg = <0x25>; + clocks = <0x02 0x199 0x02 0x140>; + pm_qos = <0xa9>; + }; + + power-domain@38 { + reg = <0x26>; + clocks = <0x02 0x3c 0x02 0x3d>; + }; + + power-domain@40 { + reg = <0x28>; + pm_qos = <0xaa>; + }; + }; + }; + + dma-controller@fea30000 { + compatible = "arm,pl330\0arm,primecell"; + reg = <0x00 0xfea30000 0x00 0x4000>; + interrupts = <0x00 0x58 0x04 0x00 0x59 0x04>; + clocks = <0x02 0x79>; + clock-names = "apb_pclk"; + #dma-cells = <0x01>; + arm,pl330-periph-burst; + phandle = <0xec>; + }; + + spi@feb20000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x00 0xfeb20000 0x00 0x1000>; + interrupts = <0x00 0x148 0x04>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0xa5 0x02 0xa0>; + clock-names = "spiclk\0apb_pclk"; + dmas = <0xec 0x0f 0xec 0x10>; + dma-names = "tx\0rx"; + pinctrl-names = "default"; + pinctrl-0 = <0x160 0x161>; + num-cs = <0x01>; + status = "okay"; + assigned-clocks = <0x02 0xa5>; + assigned-clock-rates = <0xbebc200>; + phandle = <0x2c7>; + + rk806single@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <0xf4240>; + reg = <0x00>; + interrupt-parent = <0xf2>; + interrupts = <0x07 0x08>; + pinctrl-names = "default\0pmic-power-off"; + pinctrl-0 = <0x162 0x163 0x164 0x165>; + pinctrl-1 = <0x166>; + low_voltage_threshold = <0xbb8>; + shutdown_voltage_threshold = <0xa8c>; + shutdown_temperture_threshold = <0xa0>; + hotdie_temperture_threshold = <0x73>; + pmic-reset-func = <0x01>; + vcc1-supply = <0x75>; + vcc2-supply = <0x75>; + vcc3-supply = <0x75>; + vcc4-supply = <0x75>; + vcc5-supply = <0x75>; + vcc6-supply = <0x75>; + vcc7-supply = <0x75>; + vcc8-supply = <0x75>; + vcc9-supply = <0x75>; + vcc10-supply = <0x75>; + vcc11-supply = <0x167>; + vcc12-supply = <0x75>; + vcc13-supply = <0x168>; + vcc14-supply = <0x168>; + vcca-supply = <0x75>; + phandle = <0x2c8>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk806 { + gpio-controller; + #gpio-cells = <0x02>; + phandle = <0x2c9>; + + rk806_dvs1_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + phandle = <0x163>; + }; + + rk806_dvs1_slp { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + phandle = <0x2ca>; + }; + + rk806_dvs1_pwrdn { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + phandle = <0x166>; + }; + + rk806_dvs1_rst { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + phandle = <0x2cb>; + }; + + rk806_dvs2_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + phandle = <0x164>; + }; + + rk806_dvs2_slp { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + phandle = <0x2cc>; + }; + + rk806_dvs2_pwrdn { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + phandle = <0x2cd>; + }; + + rk806_dvs2_rst { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + phandle = <0x2ce>; + }; + + rk806_dvs2_dvs { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + phandle = <0x2cf>; + }; + + rk806_dvs2_gpio { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + phandle = <0x2d0>; + }; + + rk806_dvs3_null { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + phandle = <0x165>; + }; + + rk806_dvs3_slp { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + phandle = <0x2d1>; + }; + + rk806_dvs3_pwrdn { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + phandle = <0x2d2>; + }; + + rk806_dvs3_rst { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + phandle = <0x2d3>; + }; + + rk806_dvs3_dvs { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + phandle = <0x2d4>; + }; + + rk806_dvs3_gpio { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + phandle = <0x2d5>; + }; + }; + + regulators { + PLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x325aa0>; + regulator-name = "vccio_sd_s0"; + phandle = <0x11e>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1e8480>; + regulator-max-microvolt = <0x1e8480>; + regulator-name = "vdd_2v0_pldo_s3"; + phandle = <0x167>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x1e8480>; + }; + }; + }; + }; + }; + + + i2c@fec80000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfec80000 0x00 0x1000>; + clocks = <0x02 0x92 0x02 0x8a>; + clock-names = "i2c\0pclk"; + interrupts = <0x00 0x143 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x185>; + resets = <0x02 0xb5 0x02 0xad>; + reset-names = "i2c\0apb"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x2f8>; + + husb311@4e { + compatible = "hynetek,husb311"; + reg = <0x4e>; + interrupt-parent = <0x113>; + interrupts = <0x0e 0x08>; + pinctrl-names = "default"; + pinctrl-0 = <0x186>; + vbus-supply = <0x187>; + status = "okay"; + phandle = <0x2f9>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint@0 { + remote-endpoint = <0x188>; + phandle = <0x65>; + }; + }; + }; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <0xf4240>; + sink-pdos = <0x4019064>; + source-pdos = <0x401912c>; + phandle = <0x2fa>; + + altmodes { + #address-cells = <0x01>; + #size-cells = <0x00>; + + altmode@0 { + reg = <0x00>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x189>; + phandle = <0x197>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x18a>; + phandle = <0x198>; + }; + }; + }; + }; + }; + + hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0x00>; + clock-frequency = <0x8000>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <0x18b>; + interrupt-parent = <0xf2>; + interrupts = <0x08 0x08>; + wakeup-source; + phandle = <0x1f2>; + }; + }; + + aliases { + serial0 = "/serial@feb50000"; + mmc0 = "/mmc@fe2e0000"; + mmc1 = "/mmc@fe2c0000"; + tsadc = "/tsadc@fec00000"; + spi0 = "/spi@feb20000"; + ethernet0 = "/ethernet@fe1c0000"; + }; + + hvisor_virtio_device { + compatible = "hvisor"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x20 0x01>; + }; + + ethernet@fe1c0000 { + local-mac-address = [0e f0 2e be b3 6c]; + compatible = "rockchip,rk3588-gmac\0snps,dwmac-4.20a"; + reg = <0x00 0xfe1c0000 0x00 0x10000>; + interrupts = <0x00 0xea 0x04 0x00 0xe9 0x04>; + interrupt-names = "macirq\0eth_wake_irq"; + rockchip,grf = <0xc3>; + rockchip,php_grf = <0x73>; + clocks = <0x02 0x144 0x02 0x145 0x02 0x168 0x02 0x16d 0x02 0x143>; + clock-names = "stmmaceth\0clk_mac_ref\0pclk_mac\0aclk_mac\0ptp_ref"; + resets = <0x02 0x20b>; + reset-names = "stmmaceth"; + power-domains = <0x5d 0x21>; + snps,mixed-burst; + snps,tso; + snps,axi-config = <0x110>; + snps,mtl-rx-config = <0x111>; + snps,mtl-tx-config = <0x112>; + status = "okay"; + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + snps,reset-gpio = <0x113 0x0f 0x01>; + snps,reset-active-low; + snps,reset-delays-us = <0x00 0x4e20 0x186a0>; + pinctrl-names = "default"; + pinctrl-0 = <0x114 0x115 0x116 0x117 0x118>; + tx_delay = <0x43>; + phy-handle = <0x119>; + phandle = <0x10f>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x2a4>; + + phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x01>; + phandle = <0x119>; + }; + }; + + stmmac-axi-config { + snps,wr_osr_lmt = <0x04>; + snps,rd_osr_lmt = <0x08>; + snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>; + phandle = <0x110>; + }; + + rx-queues-config { + snps,rx-queues-to-use = <0x01>; + phandle = <0x111>; + + queue0 { + }; + }; + + tx-queues-config { + snps,tx-queues-to-use = <0x01>; + phandle = <0x112>; + + queue0 { + }; + }; + }; + + chosen { + // bootargs = "rw rootwait earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 root=PARTUUID=614e0000-0000"; + // bootargs = "rw rootwait earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 root=/dev/mmcblk1p1"; + bootargs = "rw rootwait earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 root=/dev/sda1"; + phandle = <0x4bc>; + }; +}; diff --git a/platform/aarch64/rk3588/image/zone1-linux.dts b/platform/aarch64/rk3588/image/zone1-linux.dts new file mode 100644 index 00000000..804ae69a --- /dev/null +++ b/platform/aarch64/rk3588/image/zone1-linux.dts @@ -0,0 +1,234 @@ +/dts-v1/; + +/memreserve/ 0x0000000008300000 0x0000000000047000; +/ { + serial-number = "fe9d722c1f58159b"; + compatible = "rockchip,rk3588-evb7-v11\0rockchip,rk3588"; + interrupt-parent = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "Rockchip RK3588 EVB7 V11 Board"; + + memory { + reg = <0x00 0x50000000 0x00 0x25000000>; + device_type = "memory"; + }; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + + cpu-map { + cluster0 { + core2 { + cpu = <0x08>; + }; + core3 { + cpu = <0x09>; + }; + }; + }; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <0x212>; + clocks = <0x0e 0x00>; + cpu-idle-states = <0x10>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x80>; + next-level-cache = <0x14>; + phandle = <0x08>; + }; + + cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <0x212>; + clocks = <0x0e 0x00>; + cpu-idle-states = <0x10>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x80>; + next-level-cache = <0x15>; + phandle = <0x09>; + }; + + idle-states { + entry-method = "psci"; + cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x10000>; + entry-latency-us = <0x64>; + exit-latency-us = <0x78>; + min-residency-us = <0x3e8>; + phandle = <0x10>; + }; + }; + + l2-cache-l0 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x11>; + }; + + l2-cache-l1 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x13>; + }; + + l2-cache-l2 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x14>; + }; + + l2-cache-l3 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x15>; + }; + + l2-cache-b0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x17>; + }; + + l2-cache-b1 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x19>; + }; + + l2-cache-b2 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x1b>; + }; + + l2-cache-b3 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x1d>; + }; + + l3-cache { + compatible = "cache"; + cache-size = <0x300000>; + cache-line-size = <0x40>; + cache-sets = <0x1000>; + phandle = <0x1e>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0x01 0x07 0x08>; + interrupt-affinity = <0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d>; + phandle = <0x220>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>; + }; + + interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x03>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + interrupt-controller; + reg = <0x00 0xfe600000 0x00 0x10000 0x00 0xfe680000 0x00 0x100000>; + interrupts = <0x01 0x09 0x04>; + phandle = <0x01>; + }; + + + aliases { + }; + + // virtio blk + virtio_mmio@ff9d0000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x0 0x2e 0x1>; + reg = <0x0 0xff9d0000 0x0 0x200>; + compatible = "virtio,mmio"; + }; + + // virtio serial + virtio_mmio@ff9e0000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x0 0x2c 0x1>; + reg = <0x0 0xff9e0000 0x0 0x200>; + compatible = "virtio,mmio"; + }; + + + // serial@feb50000 { + // compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + // reg = <0x00 0xfeb50000 0x00 0x100>; + // interrupts = <0x00 0x14d 0x04>; + // //clocks = <0x02 0xbb 0x02 0xac>; + // //clock-names = "baudclk\0apb_pclk"; + // reg-shift = <0x02>; + // reg-io-width = <0x04>; + // //pinctrl-names = "default"; + // //pinctrl-0 = <0x16d>; + // status = "okay"; + // phandle = <0x2e2>; + // }; + + + + chosen { + bootargs = "earlycon=virtio,mmio,0xff9e0000 console=hvc0 root=/dev/vda rootwait rw"; + stdout-path = "/virtio_mmio@0xff9e0000"; + }; +}; \ No newline at end of file diff --git a/platform/aarch64/rk3588/linker.ld b/platform/aarch64/rk3588/linker.ld new file mode 100644 index 00000000..3f780a61 --- /dev/null +++ b/platform/aarch64/rk3588/linker.ld @@ -0,0 +1,54 @@ +ENTRY(arch_entry) +BASE_ADDRESS = 0x500000; + +SECTIONS +{ + . = BASE_ADDRESS; + skernel = .; + + .boot : { + *(.text.boot) + *(.data.boot) + } + + stext = .; + .text : { + *(.text.entry) + *(.text .text.*) + } + + . = ALIGN(4K); + etext = .; + srodata = .; + .rodata : { + *(.rodata .rodata.*) + *(.srodata .srodata.*) + } + + . = ALIGN(4K); + erodata = .; + sdata = .; + .data : { + *(.data .data.*) + *(.sdata .sdata.*) + } + + . = ALIGN(4K); + edata = .; + .bss : { + *(.bss.stack) + sbss = .; + *(.bss .bss.*) + *(.sbss .sbss.*) + } + + . = ALIGN(4K); + ebss = .; + ekernel = .; + + /DISCARD/ : { + *(.eh_frame) + } + . = ALIGN(4K); + __core_end = .; +} \ No newline at end of file diff --git a/platform/aarch64/rk3588/platform.mk b/platform/aarch64/rk3588/platform.mk new file mode 100644 index 00000000..e6888095 --- /dev/null +++ b/platform/aarch64/rk3588/platform.mk @@ -0,0 +1,8 @@ +$(hvisor_bin): elf + @if ! command -v mkimage > /dev/null; then \ + sudo apt update && sudo apt install u-boot-tools; \ + fi && \ + $(OBJCOPY) $(hvisor_elf) --strip-all -O binary $(hvisor_bin).tmp && \ + mkimage -n hvisor_img -A arm64 -O linux -C none -T kernel -a 0x00500000 \ + -e 0x00500000 -d $(hvisor_bin).tmp $(hvisor_bin) && \ + rm -rf $(hvisor_bin).tmp \ No newline at end of file diff --git a/platform/aarch64/zcu102/board.rs b/platform/aarch64/zcu102/board.rs index 6b4b3904..54049234 100644 --- a/platform/aarch64/zcu102/board.rs +++ b/platform/aarch64/zcu102/board.rs @@ -18,6 +18,8 @@ use crate::{arch::zone::HvArchZoneConfig, config::*}; pub const BOARD_NAME: &str = "zcu102"; +pub const BOARD_NCPUS: usize = 4; + pub const ROOT_ZONE_DTB_ADDR: u64 = 0x04000000; pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x00200000; pub const ROOT_ZONE_ENTRY: u64 = 0x00200000; diff --git a/platform/aarch64/zcu102/cargo/features b/platform/aarch64/zcu102/cargo/features index f51ca875..c5fd26a0 100644 --- a/platform/aarch64/zcu102/cargo/features +++ b/platform/aarch64/zcu102/cargo/features @@ -1,3 +1,2 @@ gicv2 -xuartps -a53 \ No newline at end of file +xuartps \ No newline at end of file diff --git a/platform/loongarch64/ls3a5000/board.rs b/platform/loongarch64/ls3a5000/board.rs index 903a87e0..c86952b3 100644 --- a/platform/loongarch64/ls3a5000/board.rs +++ b/platform/loongarch64/ls3a5000/board.rs @@ -18,6 +18,8 @@ use crate::{arch::zone::HvArchZoneConfig, config::*}; pub const BOARD_NAME: &str = "ls3a5000"; +pub const BOARD_NCPUS: usize = 4; + pub const ROOT_ZONE_DTB_ADDR: u64 = 0x10000f000; pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x200000; pub const ROOT_ZONE_ENTRY: u64 = 0x9000000000e71000; diff --git a/platform/riscv64/qemu-aia/board.rs b/platform/riscv64/qemu-aia/board.rs index 75c879de..1c0292de 100644 --- a/platform/riscv64/qemu-aia/board.rs +++ b/platform/riscv64/qemu-aia/board.rs @@ -17,6 +17,8 @@ use crate::{arch::zone::HvArchZoneConfig, config::*}; pub const BOARD_NAME: &str = "qemu-aia"; +pub const BOARD_NCPUS: usize = 4; + pub const ACLINT_SSWI_BASE: usize = 0x2F00000; pub const PLIC_BASE: usize = 0xc000000; diff --git a/platform/riscv64/qemu-plic/board.rs b/platform/riscv64/qemu-plic/board.rs index 1fd4aa70..a7f40c21 100644 --- a/platform/riscv64/qemu-plic/board.rs +++ b/platform/riscv64/qemu-plic/board.rs @@ -18,6 +18,8 @@ use crate::{arch::zone::HvArchZoneConfig, config::*}; #[allow(unused)] pub const BOARD_NAME: &str = "qem-plic"; +pub const BOARD_NCPUS: usize = 4; + pub const ACLINT_SSWI_BASE: usize = 0x2F00000; pub const PLIC_BASE: usize = 0xc000000; diff --git a/platform/x86_64/qemu/board.rs b/platform/x86_64/qemu/board.rs index 09836908..71147aea 100644 --- a/platform/x86_64/qemu/board.rs +++ b/platform/x86_64/qemu/board.rs @@ -21,6 +21,8 @@ use crate::{ pub const BOARD_NAME: &str = "qemu"; +pub const BOARD_NCPUS: usize = 4; + pub const ROOT_ZONE_DTB_ADDR: u64 = 0x00000000; pub const ROOT_ZONE_ENTRY: u64 = 0x8000; // 0x10_0000; pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x500_0000; // 0x500_0000; diff --git a/src/arch/aarch64/boot_pt.S b/src/arch/aarch64/boot_pt.S deleted file mode 100644 index d7d44a7f..00000000 --- a/src/arch/aarch64/boot_pt.S +++ /dev/null @@ -1,77 +0,0 @@ -// Copyright (c) 2025 Syswonder -// hvisor is licensed under Mulan PSL v2. -// You can use this software according to the terms and conditions of the Mulan PSL v2. -// You may obtain a copy of Mulan PSL v2 at: -// http://license.coscl.org.cn/MulanPSL2 -// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER -// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR -// FIT FOR A PARTICULAR PURPOSE. -// See the Mulan PSL v2 for more details. -// -// Syswonder Website: -// https://www.syswonder.org -// -// Authors: -// - - PTE_TABLE_FLAGS =0x3 //11 - PAGE_DEFAULT_FLAG=0x741 //11101000001 - PAGE_DEVICE_FLAG=0x745 //11101000101 - - MAIR_FLAG=0x004404ff //10001000000010011111111 - SCTLR_FLAG=0x30c51835 //110000110001010001100000110101 - TCR_FLAG=0x80853510 //10000000100001010011010100010000 - .extern uart_puts_1 - .extern uart_puts_2 - .section .bss - .align 12 // 对齐到页边界 -boot_pt_l0: - .zero 0x1000 - - .align 12 -boot_pt_l1: - .zero 0x1000 - - .section .text - .global set_boot_pt -boot_pt_init: - // TODO: re-enable hvisor pt when system boot success - adrp x1, boot_pt_l0 - adrp x2, boot_pt_l1 - add x2, x2, PTE_TABLE_FLAGS - str x2, [x1] // set boot_pt_l0, index=0 -> boot_pt_l1 - - adrp x1, boot_pt_l1 - ldr x2, =(0x0 | PAGE_DEFAULT_FLAG) // device memory at 0x0 ~ 0x40000000 - str x2, [x1] - ldr x2, =(0x40000000 | PAGE_DEFAULT_FLAG) // RAM at 0x40000000 ~ 0x80000000 - str x2, [x1, #0x8] - ldr x2, =(0x80000000 | PAGE_DEFAULT_FLAG) // RAM at 0x80000000 ~ 0xC0000000 - str x2, [x1, #0x10] - ldr x2, =(0xC0000000 | PAGE_DEVICE_FLAG) // RAM at 0xC0000000 ~ 0x100000000 - str x2, [x1, #0x18] - ret - - -enable_boot_pt: - adrp x1, boot_pt_l0 - msr ttbr0_el2, x1 - - isb - tlbi alle2 - dsb nsh - - // enable mmu... - ldr x1, =MAIR_FLAG - msr mair_el2, x1 // memory attributes for pagetable - ldr x1, =TCR_FLAG - msr tcr_el2, x1 // translate control, virt range = [0, 2^48) - - /* Enable MMU, allow cacheability for instructions and data */ - ldr x1, =SCTLR_FLAG - msr sctlr_el2, x1 // system control register - - isb - tlbi alle2 - dsb nsh - ret diff --git a/src/arch/aarch64/cpu.rs b/src/arch/aarch64/cpu.rs index 7ef2b2d2..fdf270b1 100644 --- a/src/arch/aarch64/cpu.rs +++ b/src/arch/aarch64/cpu.rs @@ -167,7 +167,11 @@ impl ArchCpu { this_cpu_data().activate_gpm(); self.reset(this_cpu_data().cpu_on_entry, this_cpu_data().dtb_ipa); self.power_on = true; - info!("cpu {} started", self.cpuid); + info!( + "cpu {} started at {:#x?}", + self.cpuid, + this_cpu_data().cpu_on_entry + ); unsafe { vmreturn(self.guest_reg() as *mut _ as usize); } @@ -207,14 +211,12 @@ impl ArchCpu { } } -#[cfg(not(feature = "a55"))] pub fn mpidr_to_cpuid(mpidr: u64) -> u64 { - mpidr & 0xff00ffffff -} - -#[cfg(feature = "a55")] -pub fn mpidr_to_cpuid(mpidr: u64) -> u64 { - (mpidr >> 8) & 0xff + if cfg!(feature = "mpidr_rockchip") { + (mpidr >> 8) & 0xff + } else { + mpidr & 0xff00ffffff + } } pub fn this_cpu_id() -> usize { diff --git a/src/arch/aarch64/entry.rs b/src/arch/aarch64/entry.rs index 62cc2225..c7bc056b 100644 --- a/src/arch/aarch64/entry.rs +++ b/src/arch/aarch64/entry.rs @@ -18,8 +18,6 @@ use core::arch::global_asm; use crate::consts::PER_CPU_SIZE; //global_asm!(include_str!("boot_pt.S")); - -#[cfg(feature = "a55")] #[naked] #[no_mangle] #[link_section = ".text.entry"] @@ -29,24 +27,44 @@ pub unsafe extern "C" fn arch_entry() -> i32 { " // x0 = dtbaddr mov x18, x0 - mrs x17, mpidr_el1 - lsr x17, x17, #0x8 - and x17, x17, #0xff + + /* Insert nop instruction to ensure byte at offset 10 in hvisor binary is non-zero. + * Rockchip U-Boot (arch_preboot_os@arch/arm/mach-rockchip/board.c:670) performs + * forced relocation if this byte is zero, causing boot failure. This padding + * prevents unintended relocation by maintaining non-zero value at this critical + * offset in the binary layout. */ + + nop + bl {boot_cpuid_get} + adrp x2, __core_end // x2 = &__core_end - mov x3, {per_cpu_size} // x3 = per_cpu_size - madd x4, x17, x3, x3 // x4 = cpuid * per_cpu_size + mov x3, {per_cpu_size} // x3 = per_cpu_size + madd x4, x17, x3, x3 // x4 = cpuid * per_cpu_size add x5, x2, x4 - mov sp, x5 // sp = &__core_end + (cpuid + 1) * per_cpu_size + mov sp, x5 // sp = &__core_end + (cpuid + 1) * per_cpu_size // disable cache and MMU mrs x1, sctlr_el2 bic x1, x1, #0xf msr sctlr_el2, x1 + // cache_invalidate(0): clear dl1$ + mov x0, #0 + bl {cache_invalidate} + + ic iallu + cmp x17, 0 b.ne 1f + // if (cpu_id == 0) cache_invalidate(2): clear l2$ + mov x0, #2 + bl {cache_invalidate} + + // ic iallu + bl {clear_bss} + //bl boot_pt_init adrp x0, {BOOT_PT_L0} adrp x1, {BOOT_PT_L1} @@ -57,7 +75,7 @@ pub unsafe extern "C" fn arch_entry() -> i32 { bl {mmu_enable} tlbi alle2 - dsb nsh + dsb nsh isb mov x1, x18 @@ -67,7 +85,9 @@ pub unsafe extern "C" fn arch_entry() -> i32 { bl {rust_main} // x0 = cpuid, x1 = dtbaddr ", options(noreturn), - per_cpu_size=const PER_CPU_SIZE, + boot_cpuid_get = sym boot_cpuid_get, + cache_invalidate = sym cache_invalidate, + per_cpu_size = const PER_CPU_SIZE, rust_main = sym crate::rust_main, clear_bss = sym crate::clear_bss, BOOT_PT_L0 = sym super::mmu::BOOT_PT_L0, @@ -75,84 +95,39 @@ pub unsafe extern "C" fn arch_entry() -> i32 { boot_pt_init = sym super::mmu::boot_pt_init, mmu_init = sym super::mmu::mmu_init, mmu_enable = sym super::mmu::mmu_enable, - // boot_cpuid_get = sym boot_cpuid_get, ); } } -#[cfg(not(feature = "a55"))] +#[cfg(feature = "mpidr_rockchip")] #[naked] #[no_mangle] -#[link_section = ".text.entry"] -pub unsafe extern "C" fn arch_entry() -> i32 { - unsafe { - core::arch::asm!( - " - // x0 = dtbaddr - mov x18, x0 - mrs x17, mpidr_el1 - and x17, x17, #0xff - adrp x2, __core_end // x2 = &__core_end - mov x3, {per_cpu_size} // x3 = per_cpu_size - madd x4, x17, x3, x3 // x4 = cpuid * per_cpu_size - add x5, x2, x4 - mov sp, x5 // sp = &__core_end + (cpuid + 1) * per_cpu_size - - // disable cache and MMU - mrs x1, sctlr_el2 - bic x1, x1, #0xf - msr sctlr_el2, x1 - - cmp x17, 0 - b.ne 1f - - bl {clear_bss} - //bl boot_pt_init - adrp x0, {BOOT_PT_L0} - adrp x1, {BOOT_PT_L1} - bl {boot_pt_init} - 1: - adrp x0, {BOOT_PT_L0} - bl {mmu_init} - bl {mmu_enable} - - tlbi alle2 - dsb nsh - isb +pub unsafe extern "C" fn boot_cpuid_get() { + core::arch::asm!( + " + mrs x17, mpidr_el1 + lsr x17, x17, #0x8 + and x17, x17, #0xff + ret + ", + options(noreturn) + ) +} - mov x1, x18 - mov x0, x17 - mov x18, 0 - mov x17, 0 - bl {rust_main} // x0 = cpuid, x1 = dtbaddr - ", - options(noreturn), - per_cpu_size=const PER_CPU_SIZE, - rust_main = sym crate::rust_main, - clear_bss = sym crate::clear_bss, - BOOT_PT_L0 = sym super::mmu::BOOT_PT_L0, - BOOT_PT_L1 = sym super::mmu::BOOT_PT_L1, - boot_pt_init = sym super::mmu::boot_pt_init, - mmu_init = sym super::mmu::mmu_init, - mmu_enable = sym super::mmu::mmu_enable, - // boot_cpuid_get = sym boot_cpuid_get, - ); - } +#[cfg(not(feature = "mpidr_rockchip"))] +#[naked] +#[no_mangle] +pub unsafe extern "C" fn boot_cpuid_get() { + core::arch::asm!( + " + mrs x17, mpidr_el1 + and x17, x17, #0xff + ret + ", + options(noreturn) + ) } -// #[naked] -// #[no_mangle] -// #[link_section = ".text.entry"] -// pub unsafe extern "C" fn boot_cpuid_get() { -// core::arch::asm!(" -// mrs x17, mpidr_el1 -// lsr x17, x17, #0x8 -// and x17, x17, #0xff -// ret -// " -// ,options(noreturn) -// ) -// } #[naked] #[no_mangle] #[link_section = ".trampoline"] @@ -197,3 +172,38 @@ pub unsafe extern "C" fn shutdown_el2(_gu_regs: usize) -> i32 { options(noreturn), ); } + +unsafe extern "C" fn cache_invalidate(cache_level: usize) { + core::arch::asm!( + r#" + msr csselr_el1, {0} + mrs x4, ccsidr_el1 // read cache size id. + and x1, x4, #0x7 + add x1, x1, #0x4 // x1 = cache line size. + ldr x3, =0x7fff + and x2, x3, x4, lsr #13 // x2 = cache set number - 1. + ldr x3, =0x3ff + and x3, x3, x4, lsr #3 // x3 = cache associativity number - 1. + clz w4, w3 // x4 = way position in the cisw instruction. + mov x5, #0 // x5 = way counter way_loop. + // way_loop: + 1: + mov x6, #0 // x6 = set counter set_loop. + // set_loop: + 2: + lsl x7, x5, x4 + orr x7, {0}, x7 // set way. + lsl x8, x6, x1 + orr x7, x7, x8 // set set. + dc cisw, x7 // clean and invalidate cache line. + add x6, x6, #1 // increment set counter. + cmp x6, x2 // last set reached yet? + ble 2b // if not, iterate set_loop, + add x5, x5, #1 // else, next way. + cmp x5, x3 // last way reached yet? + ble 1b // if not, iterate way_loop + "#, + in(reg) cache_level, + options(nostack) + ); +} diff --git a/src/arch/aarch64/ipi.rs b/src/arch/aarch64/ipi.rs index 0dcde79e..8d583c59 100644 --- a/src/arch/aarch64/ipi.rs +++ b/src/arch/aarch64/ipi.rs @@ -13,6 +13,9 @@ // // Authors: // + +use crate::arch::cpu; + #[cfg(feature = "gicv3")] use crate::arch::sysreg::write_sysreg; #[cfg(feature = "gicv2")] @@ -24,22 +27,24 @@ pub fn arch_send_event(cpu_id: u64, sgi_num: u64) { the MPIDR of the target CPU. However, since we cannot access this register on the sender side, we have reverse-engineered a value here using the cpu_id. - Therefore, we must differentiate the MPIDR format of the A55 architecture - from that of other CPUs. Here, we directly use conditional compilation - to handle this in a straightforward manner. + Due to differences in how some CPU implementations (e.g., RK3568 and RK3588) + encode affinity values in MPIDR, we use conditional compilation to handle + platform-specific mappings between cpu_id and interrupt target affinity. */ let aff3: u64 = 0 << 48; let aff2: u64 = 0 << 32; - #[cfg(feature = "a55")] - let aff1: u64 = cpu_id << 16; - #[cfg(not(feature = "a55"))] - let aff1: u64 = 0 << 16; + let aff1: u64; + let target_list: u64; + + if cfg!(feature = "mpidr_rockchip") { + aff1 = cpu_id << 16; + target_list = 1 << 0; + } else { + aff1 = 0 << 16; + target_list = 1 << cpu_id; + } let irm: u64 = 0 << 40; let sgi_id: u64 = sgi_num << 24; - #[cfg(feature = "a55")] - let target_list: u64 = 1; - #[cfg(not(feature = "a55"))] - let target_list: u64 = 1 << cpu_id; let val: u64 = aff1 | aff2 | aff3 | irm | sgi_id | target_list; write_sysreg!(icc_sgi1r_el1, val); debug!("write sgi sys value = {:#x}", val); diff --git a/src/arch/aarch64/mmu.rs b/src/arch/aarch64/mmu.rs index 2ced1434..4229f4f9 100644 --- a/src/arch/aarch64/mmu.rs +++ b/src/arch/aarch64/mmu.rs @@ -164,7 +164,7 @@ pub extern "C" fn boot_pt_init(l0_pt: &mut PageTables, l1_pt: &mut PageTables) { for i in 1..ENTRY_PER_PAGE { l0_pt.entry[i] = PTEDescriptor::new(0x40000000*i, MemoryType::Normal, PTEType::Block); } - } else if #[cfg(feature = "pt_layout_rk3568")]{ + } else if #[cfg(any(feature = "pt_layout_rk3568", feature = "pt_layout_rk3588"))] { // EMMC fe310000 0xfe200000-0xfe400000 // GIC fd400000 0xfd400000-0xfd600000 // UART fe660000 0xfe600000-0xfe800000 diff --git a/src/arch/aarch64/trap.rs b/src/arch/aarch64/trap.rs index f433f68f..8b67480d 100644 --- a/src/arch/aarch64/trap.rs +++ b/src/arch/aarch64/trap.rs @@ -58,7 +58,7 @@ pub mod SmcType { const PSCI_VERSION_1_1: u64 = 0x10001; const PSCI_TOS_NOT_PRESENT_MP: u64 = 2; -const ARM_SMCCC_VERSION_1_0: u64 = 0x10000; +const ARM_SMCCC_VERSION_1_1: u64 = 0x10001; const ARM_SMCCC_NOT_SUPPORTED: i64 = -1; extern "C" { @@ -173,9 +173,8 @@ fn arch_handle_trap_el2(_regs: &mut GeneralRegisters) { } Some(ESR_EL2::EC::Value::InstrAbortCurrentEL) => { println!( - "EL2 Exception: Instruction Abort, ELR_EL2: {:#x?}, FAR_EL2: {:#x?}", - ELR_EL2.get(), - FAR_EL2.get() + "EL2 Exception: Instruction Abort, ELR_EL2: {:#x?}, ESR_EL2: {:#x?},FAR_EL2: {:#x?}", + elr, esr, far ); } _ => { @@ -192,15 +191,19 @@ fn handle_iabt(_regs: &mut GeneralRegisters) { let iss = ESR_EL2.read(ESR_EL2::ISS); let op = iss >> 6 & 0x1; let hpfar = read_sysreg!(HPFAR_EL2); - let hdfar = read_sysreg!(FAR_EL2); - let mut address = hpfar << 8; - address |= hdfar & 0xfff; - error!("error ins access {} at {:#x?}!", op, address); - error!("esr_el2: iss {:#x?}", iss); + let far = read_sysreg!(FAR_EL2); + let address = (far & 0xfff) | (hpfar << 8); + error!( + "Failed to fetch instruction (op={}) at {:#x?}, ELR_EL2={:#x?}!", + op, + address, + ELR_EL2.get() + ); loop {} - //TODO finish dabt handle + // TODO: finish iabt handle // arch_skip_instruction(frame); } + fn handle_dabt(regs: &mut GeneralRegisters) { let iss = ESR_EL2.read(ESR_EL2::ISS); let is_write = (iss >> 6 & 0x1) != 0; @@ -416,7 +419,7 @@ fn handle_arch_smc( _arg2: u64, ) -> u64 { match code { - SMCccFnId::SMCCC_VERSION => ARM_SMCCC_VERSION_1_0, + SMCccFnId::SMCCC_VERSION => ARM_SMCCC_VERSION_1_1, SMCccFnId::SMCCC_ARCH_FEATURES => !0, _ => { error!("unsupported ARM smc service"); diff --git a/src/consts.rs b/src/consts.rs index 72bdc2de..7df36acf 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -28,11 +28,6 @@ pub const PER_CPU_ARRAY_PTR: *mut VirtAddr = __core_end as _; pub const INVALID_ADDRESS: usize = usize::MAX; -#[cfg(target_arch = "loongarch64")] -pub const MAX_CPU_NUM: usize = 32; -#[cfg(target_arch = "aarch64")] -pub const MAX_CPU_NUM: usize = 32; -#[cfg(target_arch = "riscv64")] pub const MAX_CPU_NUM: usize = 32; pub const MAX_ZONE_NUM: usize = 3; diff --git a/src/device/irqchip/gicv3/gicr.rs b/src/device/irqchip/gicv3/gicr.rs index 83f12371..2f23e1b2 100644 --- a/src/device/irqchip/gicv3/gicr.rs +++ b/src/device/irqchip/gicv3/gicr.rs @@ -65,8 +65,6 @@ pub fn enable_ipi() { gicr_igroupr0.write_volatile(gicr_igroupr0.read_volatile() | (1 << SGI_IPI_ID)); let gicr_isenabler0 = (base + GICR_ISENABLER) as *mut u32; - gicr_isenabler0.write_volatile(1 << SGI_IPI_ID | 1 << MAINTENACE_INTERRUPT); - trace!("gicr_isenabler0: {}", gicr_isenabler0.read_volatile()); let gicr_ipriorityr0 = (base + GICR_IPRIORITYR) as *mut u32; for irq_id in [SGI_IPI_ID, MAINTENACE_INTERRUPT] { let reg = irq_id / 4; @@ -76,6 +74,8 @@ pub fn enable_ipi() { let prio = p.read_volatile(); p.write_volatile((prio & !mask) | (0x01 << offset)); + + gicr_isenabler0.write_volatile(1 << irq_id); } } } diff --git a/src/device/irqchip/gicv3/mod.rs b/src/device/irqchip/gicv3/mod.rs index 94307df8..81aa14e1 100644 --- a/src/device/irqchip/gicv3/mod.rs +++ b/src/device/irqchip/gicv3/mod.rs @@ -150,11 +150,12 @@ fn gicv3_clear_pending_irqs() { static TIMER_INTERRUPT_COUNTER: AtomicU64 = AtomicU64::new(0); // how often to print timer interrupt counter -const TIMER_INTERRUPT_PRINT_TIMES: u64 = 50; +const TIMER_INTERRUPT_PRINT_INTERVAL: u64 = 50; pub fn gicv3_handle_irq_el1() { while let Some(irq_id) = pending_irq() { if irq_id < 8 { + trace!("sgi get {}, try to handle...", irq_id); deactivate_irq(irq_id); let mut ipi_handled = false; if irq_id == SGI_IPI_ID as _ { @@ -172,7 +173,7 @@ pub fn gicv3_handle_irq_el1() { // virtual timer interrupt TIMER_INTERRUPT_COUNTER.fetch_add(1, core::sync::atomic::Ordering::SeqCst); if TIMER_INTERRUPT_COUNTER.load(core::sync::atomic::Ordering::SeqCst) - % TIMER_INTERRUPT_PRINT_TIMES + % TIMER_INTERRUPT_PRINT_INTERVAL == 0 { trace!( diff --git a/src/device/irqchip/gicv3/vgic.rs b/src/device/irqchip/gicv3/vgic.rs index 316c887a..e2401abc 100644 --- a/src/device/irqchip/gicv3/vgic.rs +++ b/src/device/irqchip/gicv3/vgic.rs @@ -256,7 +256,7 @@ fn vgicv3_dist_misc_access(mmio: &mut MMIOAccess, gicd_base: usize) -> HvResult mmio_perform_access(gicd_base, mmio); } } else { - todo!() + todo!("vgicv3_dist_misc_access: MMIO.Address = {:#x?}", reg) } Ok(()) diff --git a/src/device/uart/mod.rs b/src/device/uart/mod.rs index 3bca25ba..6e3ac1be 100644 --- a/src/device/uart/mod.rs +++ b/src/device/uart/mod.rs @@ -41,6 +41,6 @@ mod loongson_uart; pub use loongson_uart::{console_getchar, console_putchar}; #[cfg(all(feature = "uart_16550", target_arch = "aarch64"))] -pub mod uart_16550; +mod uart_16550; #[cfg(all(feature = "uart_16550", target_arch = "aarch64"))] pub use uart_16550::{console_getchar, console_putchar}; diff --git a/src/device/uart/uart_16550.rs b/src/device/uart/uart_16550.rs index e5a1d772..a261aee8 100644 --- a/src/device/uart/uart_16550.rs +++ b/src/device/uart/uart_16550.rs @@ -6,9 +6,12 @@ use tock_registers::register_bitfields; use tock_registers::register_structs; use tock_registers::registers::*; -#[cfg(all(feature = "rk3568_uart_base"))] +#[cfg(feature = "uart_base_rk3568")] pub const UART_BASE: PhysAddr = 0xfe660000; +#[cfg(feature = "uart_base_rk3588")] +pub const UART_BASE: PhysAddr = 0xfeb50000; + /// Register struct representing the UART registers. register_structs! { /// Representation of the UART registers. @@ -51,18 +54,20 @@ impl Uart16550 { self.regs().IIR_FCR.set(0x1 << 0); } + #[inline] pub fn putchar(&mut self, c: u8) { while self.regs().LSR.get() & (1 << 5) == 0 {} self.regs().THR_RBR_DLL.set(c as u32); } + #[inline] fn getchar(&mut self) -> Option { todo!() } } -static mut UART: Uart16550 = { Uart16550::new(UART_BASE) }; +static mut UART: Uart16550 = Uart16550::new(UART_BASE); #[inline] pub fn console_putchar(c: u8) { diff --git a/src/device/virtio_trampoline.rs b/src/device/virtio_trampoline.rs index d938c54e..3241bfa1 100644 --- a/src/device/virtio_trampoline.rs +++ b/src/device/virtio_trampoline.rs @@ -41,7 +41,7 @@ pub static VIRTIO_BRIDGE: Mutex = Mutex::new(VirtioBridgeReg const QUEUE_NOTIFY: usize = 0x50; pub const MAX_REQ: u32 = 32; pub const MAX_DEVS: usize = 4; // Attention: The max virtio-dev number for vm is 4. -pub const MAX_CPUS: usize = 4; +pub const MAX_CPUS: usize = 32; #[cfg(not(target_arch = "riscv64"))] pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 32 + 0x20; @@ -236,8 +236,8 @@ pub struct VirtioBridge { pub res_rear: u32, pub req_list: [HvisorDeviceReq; MAX_REQ as usize], pub res_list: [HvisorDeviceRes; MAX_REQ as usize], // irqs - cfg_flags: [u64; MAX_CPU_NUM], - cfg_values: [u64; MAX_CPU_NUM], + cfg_flags: [u64; MAX_CPUS], + cfg_values: [u64; MAX_CPUS], pub mmio_addrs: [u64; MAX_DEVS], pub mmio_avail: u8, pub need_wakeup: u8, diff --git a/src/hypercall/mod.rs b/src/hypercall/mod.rs index e7f38392..a58218ef 100644 --- a/src/hypercall/mod.rs +++ b/src/hypercall/mod.rs @@ -25,7 +25,8 @@ use crate::device::virtio_trampoline::{MAX_DEVS, MAX_REQ, VIRTIO_BRIDGE, VIRTIO_ use crate::error::HvResult; use crate::percpu::{get_cpu_data, this_zone, PerCpu}; use crate::zone::{ - all_zones_info, find_zone, is_this_root_zone, remove_zone, this_zone_id, zone_create, ZoneInfo, + add_zone, all_zones_info, find_zone, is_this_root_zone, remove_zone, this_zone_id, zone_create, + ZoneInfo, }; use crate::event::{send_event, IPI_EVENT_SHUTDOWN, IPI_EVENT_VIRTIO_INJECT_IRQ, IPI_EVENT_WAKEUP}; @@ -272,6 +273,7 @@ impl<'a> HyperCall<'a> { let cpuid = this_cpu_id(); assert_eq!(cpuid, 0); } + add_zone(zone); drop(_lock); HyperCallResult::Ok(0) } @@ -292,7 +294,12 @@ impl<'a> HyperCall<'a> { let zone = match find_zone(zone_id as _) { Some(zone) => zone, - _ => return hv_result_err!(EEXIST), + _ => { + return hv_result_err!( + EINVAL, + format!("Shutdown zone: zone {} not found!", zone_id) + ) + } }; let zone_w = zone.write(); @@ -314,7 +321,7 @@ impl<'a> HyperCall<'a> { let power_on = get_cpu_data(cpu_id).arch_cpu.power_on; count += 1; if count > MAX_WAIT_TIMES { - if (power_on) { + if power_on { error!("cpu {} cannot be shut down", cpu_id); return false; } diff --git a/src/main.rs b/src/main.rs index 531e8a01..e442a158 100644 --- a/src/main.rs +++ b/src/main.rs @@ -78,7 +78,8 @@ use config::root_zone_config; use core::sync::atomic::{AtomicI32, AtomicU32, Ordering}; use fdt_rs::{base::DevTree, prelude::FallibleIterator}; use percpu::PerCpu; -use zone::zone_create; +use platform::BOARD_NCPUS; +use zone::{add_zone, zone_create}; #[cfg(all(feature = "iommu", target_arch = "aarch64"))] use crate::arch::iommu::iommu_init; @@ -141,8 +142,10 @@ fn primary_init_early(ncpu: usize) { iommu_init(); #[cfg(not(test))] - zone_create(root_zone_config()).unwrap(); - + { + let zone = zone_create(root_zone_config()).unwrap(); + add_zone(zone); + } INIT_EARLY_OK.store(1, Ordering::Release); } @@ -176,7 +179,10 @@ fn rust_main(cpuid: usize, host_dtb: usize) { arch::trap::install_trap_vector(); let mut is_primary = false; - println!("Hello, HVISOR!"); + extern "C" { + fn skernel(); + } + println!("Hello, start HVISOR at {:#x?}!", skernel as usize); if MASTER_CPU.load(Ordering::Acquire) == -1 { MASTER_CPU.store(cpuid as i32, Ordering::Release); is_primary = true; @@ -195,7 +201,10 @@ fn rust_main(cpuid: usize, host_dtb: usize) { // Don't you wanna know how many cpu(s) on board? :D let mut ncpu: usize = 0; - #[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] + #[cfg(all( + any(target_arch = "aarch64", target_arch = "riscv64"), + not(feature = "no_autodetect_ncpus") + ))] { let devtree = unsafe { DevTree::from_raw_pointer(host_dtb as *const u8).unwrap() }; @@ -212,10 +221,10 @@ fn rust_main(cpuid: usize, host_dtb: usize) { if is_primary { println!( "Failed to count cpu(s) from devicetree. Using default value {}.", - MAX_CPU_NUM + BOARD_NCPUS ); } - ncpu = MAX_CPU_NUM; + ncpu = BOARD_NCPUS; } else if ncpu > MAX_CPU_NUM { if is_primary { println!("{} cpu(s) detected, but using only {}.", ncpu, MAX_CPU_NUM); diff --git a/src/zone.rs b/src/zone.rs index 9f50ece2..7385842c 100644 --- a/src/zone.rs +++ b/src/zone.rs @@ -203,7 +203,10 @@ pub fn zone_create(config: &HvZoneConfig) -> HvResult>> { let zone_id = config.zone_id as usize; if find_zone(zone_id).is_some() { - return hv_result_err!(EEXIST); + return hv_result_err!( + EINVAL, + format!("Failed to create zone: zone_id {} already exists", zone_id) + ); } let mut zone = Zone::new(zone_id, &config.name); @@ -219,10 +222,21 @@ pub fn zone_create(config: &HvZoneConfig) -> HvResult>> { ); let mut cpu_num = 0; - config.cpus().iter().for_each(|cpu_id| { + + for cpu_id in config.cpus().iter() { + if let Some(zone) = get_cpu_data(*cpu_id as _).zone.clone() { + return hv_result_err!( + EBUSY, + format!( + "Failed to create zone: cpu {} already belongs to zone {}", + cpu_id, + zone.read().id + ) + ); + } zone.cpu_set.set_bit(*cpu_id as _); cpu_num += 1; - }); + } #[cfg(feature = "plic")] { @@ -260,7 +274,6 @@ pub fn zone_create(config: &HvZoneConfig) -> HvResult>> { cpu_data.dtb_ipa = dtb_ipa as _; }); } - add_zone(new_zone_pointer.clone()); Ok(new_zone_pointer) } @@ -275,7 +288,7 @@ pub struct ZoneInfo { } // Be careful about dead lock for zone.write() pub fn zone_error() { - if (is_this_root_zone()) { + if is_this_root_zone() { panic!("root zone has some error"); } let zone = this_zone();