Support DWC MSI Virtualization and VM-aware Interrupt Injection #232
Description
This issue tracks the work to support MSI virtualization for DesignWare PCIe controllers in the hypervisor.
Due to the hardware design of DWC PCIe controllers, all MSI vectors are aggregated into a single physical interrupt line. Whenever any MSI is triggered, the CPU always receives the same interrupt, regardless of which MSI vector or device caused it. As a result, the hypervisor must centrally handle this interrupt and perform software-based demultiplexing.
The proposed approach is to virtualize and partition the DWC MSI register region, assign MSI resources to individual virtual machines, and let the hypervisor parse MSI status information to determine interrupt ownership and correctly inject virtual interrupts into the target VM.