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Merge pull request #1686 from ABOSTM/UPDATE_H7
system(H7) update STM32H7xx HAL Drivers to v1.11.0 and CMSIS Drivers to v1.10.2
2 parents 2e92c39 + afee23e commit a04d6e1

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‎libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c

+2
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,8 @@
66
#include "stm32g0xx_hal_smbus_ex.c"
77
#elif STM32G4xx
88
#include "stm32g4xx_hal_smbus_ex.c"
9+
#elif STM32H7xx
10+
#include "stm32h7xx_hal_smbus_ex.c"
911
#elif STM32L0xx
1012
#include "stm32l0xx_hal_smbus_ex.c"
1113
#elif STM32L4xx

‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h

+8-3
Original file line numberDiff line numberDiff line change
@@ -2757,6 +2757,9 @@ typedef struct
27572757
#define ADC_ISR_JQOVF_Pos (10U)
27582758
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
27592759
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2760+
#define ADC_ISR_LDORDY_Pos (12U)
2761+
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
2762+
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
27602763

27612764
/******************** Bit definition for ADC_IER register ********************/
27622765
#define ADC_IER_ADRDYIE_Pos (0U)
@@ -20348,9 +20351,6 @@ typedef struct
2034820351
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
2034920352
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
2035020353
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
20351-
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
20352-
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
20353-
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
2035420354
#define OCTOSPI_DCR1_CSHT_Pos (8U)
2035520355
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
2035620356
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -20364,6 +20364,11 @@ typedef struct
2036420364
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
2036520365
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
2036620366

20367+
/* Legacy define */
20368+
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
20369+
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
20370+
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
20371+
2036720372
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
2036820373
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
2036920374
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */

‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h

+8-3
Original file line numberDiff line numberDiff line change
@@ -2758,6 +2758,9 @@ typedef struct
27582758
#define ADC_ISR_JQOVF_Pos (10U)
27592759
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
27602760
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2761+
#define ADC_ISR_LDORDY_Pos (12U)
2762+
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
2763+
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
27612764

27622765
/******************** Bit definition for ADC_IER register ********************/
27632766
#define ADC_IER_ADRDYIE_Pos (0U)
@@ -20360,9 +20363,6 @@ typedef struct
2036020363
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
2036120364
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
2036220365
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
20363-
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
20364-
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
20365-
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
2036620366
#define OCTOSPI_DCR1_CSHT_Pos (8U)
2036720367
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
2036820368
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -20376,6 +20376,11 @@ typedef struct
2037620376
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
2037720377
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
2037820378

20379+
/* Legacy define */
20380+
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
20381+
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
20382+
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
20383+
2037920384
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
2038020385
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
2038120386
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */

‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xx.h

+8-3
Original file line numberDiff line numberDiff line change
@@ -2892,6 +2892,9 @@ typedef struct
28922892
#define ADC_ISR_JQOVF_Pos (10U)
28932893
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
28942894
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2895+
#define ADC_ISR_LDORDY_Pos (12U)
2896+
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
2897+
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
28952898

28962899
/******************** Bit definition for ADC_IER register ********************/
28972900
#define ADC_IER_ADRDYIE_Pos (0U)
@@ -20835,9 +20838,6 @@ typedef struct
2083520838
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
2083620839
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
2083720840
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
20838-
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
20839-
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
20840-
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
2084120841
#define OCTOSPI_DCR1_CSHT_Pos (8U)
2084220842
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
2084320843
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -20851,6 +20851,11 @@ typedef struct
2085120851
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
2085220852
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
2085320853

20854+
/* Legacy define */
20855+
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
20856+
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
20857+
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
20858+
2085420859
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
2085520860
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
2085620861
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */

‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xxq.h

+8-3
Original file line numberDiff line numberDiff line change
@@ -2893,6 +2893,9 @@ typedef struct
28932893
#define ADC_ISR_JQOVF_Pos (10U)
28942894
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
28952895
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2896+
#define ADC_ISR_LDORDY_Pos (12U)
2897+
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
2898+
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
28962899

28972900
/******************** Bit definition for ADC_IER register ********************/
28982901
#define ADC_IER_ADRDYIE_Pos (0U)
@@ -20847,9 +20850,6 @@ typedef struct
2084720850
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
2084820851
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
2084920852
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
20850-
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
20851-
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
20852-
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
2085320853
#define OCTOSPI_DCR1_CSHT_Pos (8U)
2085420854
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
2085520855
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -20863,6 +20863,11 @@ typedef struct
2086320863
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
2086420864
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
2086520865

20866+
/* Legacy define */
20867+
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
20868+
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
20869+
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
20870+
2086620871
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
2086720872
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
2086820873
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */

‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h733xx.h

+8-3
Original file line numberDiff line numberDiff line change
@@ -2892,6 +2892,9 @@ typedef struct
28922892
#define ADC_ISR_JQOVF_Pos (10U)
28932893
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
28942894
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2895+
#define ADC_ISR_LDORDY_Pos (12U)
2896+
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
2897+
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
28952898

28962899
/******************** Bit definition for ADC_IER register ********************/
28972900
#define ADC_IER_ADRDYIE_Pos (0U)
@@ -20835,9 +20838,6 @@ typedef struct
2083520838
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
2083620839
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
2083720840
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
20838-
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
20839-
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
20840-
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
2084120841
#define OCTOSPI_DCR1_CSHT_Pos (8U)
2084220842
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
2084320843
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -20851,6 +20851,11 @@ typedef struct
2085120851
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
2085220852
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
2085320853

20854+
/* Legacy define */
20855+
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
20856+
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
20857+
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
20858+
2085420859
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
2085520860
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
2085620861
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */

‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h735xx.h

+8-3
Original file line numberDiff line numberDiff line change
@@ -2893,6 +2893,9 @@ typedef struct
28932893
#define ADC_ISR_JQOVF_Pos (10U)
28942894
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
28952895
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2896+
#define ADC_ISR_LDORDY_Pos (12U)
2897+
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
2898+
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
28962899

28972900
/******************** Bit definition for ADC_IER register ********************/
28982901
#define ADC_IER_ADRDYIE_Pos (0U)
@@ -20847,9 +20850,6 @@ typedef struct
2084720850
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
2084820851
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
2084920852
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
20850-
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
20851-
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
20852-
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
2085320853
#define OCTOSPI_DCR1_CSHT_Pos (8U)
2085420854
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
2085520855
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -20863,6 +20863,11 @@ typedef struct
2086320863
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
2086420864
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
2086520865

20866+
/* Legacy define */
20867+
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
20868+
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
20869+
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
20870+
2086620871
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
2086720872
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
2086820873
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */

‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h742xx.h

+3
Original file line numberDiff line numberDiff line change
@@ -2675,6 +2675,9 @@ typedef struct
26752675
#define ADC_ISR_JQOVF_Pos (10U)
26762676
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
26772677
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2678+
#define ADC_ISR_LDORDY_Pos (12U)
2679+
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
2680+
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
26782681

26792682
/******************** Bit definition for ADC_IER register ********************/
26802683
#define ADC_IER_ADRDYIE_Pos (0U)

‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h

+4-1
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
******************************************************************************
1313
* @attention
1414
*
15-
* Copyright (c) 2017 STMicroelectronics.
15+
* Copyright (c) 2019 STMicroelectronics.
1616
* All rights reserved.
1717
*
1818
* This software is licensed under terms that can be found in the LICENSE file
@@ -2770,6 +2770,9 @@ typedef struct
27702770
#define ADC_ISR_JQOVF_Pos (10U)
27712771
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
27722772
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2773+
#define ADC_ISR_LDORDY_Pos (12U)
2774+
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
2775+
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
27732776

27742777
/******************** Bit definition for ADC_IER register ********************/
27752778
#define ADC_IER_ADRDYIE_Pos (0U)

‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xg.h

+4-1
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
******************************************************************************
1313
* @attention
1414
*
15-
* Copyright (c) 2021 STMicroelectronics.
15+
* Copyright (c) 2019 STMicroelectronics.
1616
* All rights reserved.
1717
*
1818
* This software is licensed under terms that can be found in the LICENSE file
@@ -2864,6 +2864,9 @@ typedef struct
28642864
#define ADC_ISR_JQOVF_Pos (10U)
28652865
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
28662866
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2867+
#define ADC_ISR_LDORDY_Pos (12U)
2868+
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
2869+
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
28672870

28682871
/******************** Bit definition for ADC_IER register ********************/
28692872
#define ADC_IER_ADRDYIE_Pos (0U)

‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xx.h

+3
Original file line numberDiff line numberDiff line change
@@ -2864,6 +2864,9 @@ typedef struct
28642864
#define ADC_ISR_JQOVF_Pos (10U)
28652865
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
28662866
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2867+
#define ADC_ISR_LDORDY_Pos (12U)
2868+
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
2869+
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
28672870

28682871
/******************** Bit definition for ADC_IER register ********************/
28692872
#define ADC_IER_ADRDYIE_Pos (0U)

‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xg.h

+4-1
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
******************************************************************************
1313
* @attention
1414
*
15-
* Copyright (c) 2021 STMicroelectronics.
15+
* Copyright (c) 2019 STMicroelectronics.
1616
* All rights reserved.
1717
*
1818
* This software is licensed under terms that can be found in the LICENSE file
@@ -2947,6 +2947,9 @@ typedef struct
29472947
#define ADC_ISR_JQOVF_Pos (10U)
29482948
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
29492949
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2950+
#define ADC_ISR_LDORDY_Pos (12U)
2951+
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
2952+
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
29502953

29512954
/******************** Bit definition for ADC_IER register ********************/
29522955
#define ADC_IER_ADRDYIE_Pos (0U)

‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xx.h

+3
Original file line numberDiff line numberDiff line change
@@ -2947,6 +2947,9 @@ typedef struct
29472947
#define ADC_ISR_JQOVF_Pos (10U)
29482948
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
29492949
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2950+
#define ADC_ISR_LDORDY_Pos (12U)
2951+
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
2952+
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
29502953

29512954
/******************** Bit definition for ADC_IER register ********************/
29522955
#define ADC_IER_ADRDYIE_Pos (0U)

‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h

+4-1
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
******************************************************************************
1313
* @attention
1414
*
15-
* Copyright (c) 2018 STMicroelectronics.
15+
* Copyright (c) 2019 STMicroelectronics.
1616
* All rights reserved.
1717
*
1818
* This software is licensed under terms that can be found in the LICENSE file
@@ -2846,6 +2846,9 @@ typedef struct
28462846
#define ADC_ISR_JQOVF_Pos (10U)
28472847
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
28482848
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2849+
#define ADC_ISR_LDORDY_Pos (12U)
2850+
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
2851+
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
28492852

28502853
/******************** Bit definition for ADC_IER register ********************/
28512854
#define ADC_IER_ADRDYIE_Pos (0U)

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