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******************************************************************************
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* @attention
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*
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- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
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- * All rights reserved.</center></h2>
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+ * Copyright (c) 2017 STMicroelectronics.
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+ * All rights reserved.
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*
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- * This software component is licensed by ST under BSD 3-Clause license,
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- * the "License"; You may not use this file except in compliance with the
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- * License. You may obtain a copy of the License at:
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- * opensource.org/licenses/BSD-3-Clause
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+ * This software is licensed under terms that can be found in the LICENSE file
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+ * in the root directory of this software component.
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+ * If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
@@ -13247,7 +13246,7 @@ typedef struct
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/* Ethernet MMC Registers bits definition */
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/******************************************************************************/
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- /* Bit definition for Ethernet MMC Contol Register */
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+ /* Bit definition for Ethernet MMC Control Register */
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#define ETH_MMCCR_MCFHP_Pos (5U)
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#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
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#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
@@ -13331,7 +13330,7 @@ typedef struct
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#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
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#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
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- /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
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+ /* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
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#define ETH_MMCRFAECR_RFAEC_Pos (0U)
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#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
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#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
@@ -13345,34 +13344,37 @@ typedef struct
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/* Ethernet PTP Registers bits definition */
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/******************************************************************************/
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- /* Bit definition for Ethernet PTP Time Stamp Contol Register */
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+ /* Bit definition for Ethernet PTP Time Stamp Control Register */
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+ #define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
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+ #define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */
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+ #define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
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#define ETH_PTPTSCR_TSCNT_Pos (16U)
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#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
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#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
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- #define ETH_PTPTSSR_TSSMRME_Pos (15U)
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- #define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos ) /*!< 0x00008000 */
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- #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
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- #define ETH_PTPTSSR_TSSEME_Pos (14U)
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- #define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos ) /*!< 0x00004000 */
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- #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
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- #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
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- #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos ) /*!< 0x00002000 */
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- #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
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- #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
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- #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos ) /*!< 0x00001000 */
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- #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
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- #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
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- #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos ) /*!< 0x00000800 */
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- #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
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- #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
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- #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos ) /*!< 0x00000400 */
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- #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
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- #define ETH_PTPTSSR_TSSSR_Pos (9U)
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- #define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos ) /*!< 0x00000200 */
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- #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
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- #define ETH_PTPTSSR_TSSARFE_Pos (8U)
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- #define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos ) /*!< 0x00000100 */
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- #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
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+ #define ETH_PTPTSCR_TSSMRME_Pos (15U)
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+ #define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos ) /*!< 0x00008000 */
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+ #define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
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+ #define ETH_PTPTSCR_TSSEME_Pos (14U)
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+ #define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos ) /*!< 0x00004000 */
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+ #define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
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+ #define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
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+ #define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos ) /*!< 0x00002000 */
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+ #define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
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+ #define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
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+ #define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos ) /*!< 0x00001000 */
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+ #define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
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+ #define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
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+ #define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos ) /*!< 0x00000800 */
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+ #define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
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+ #define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
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+ #define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos ) /*!< 0x00000400 */
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+ #define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
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+ #define ETH_PTPTSCR_TSSSR_Pos (9U)
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+ #define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos ) /*!< 0x00000200 */
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+ #define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
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+ #define ETH_PTPTSCR_TSSARFE_Pos (8U)
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+ #define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos ) /*!< 0x00000100 */
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+ #define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
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#define ETH_PTPTSCR_TSARU_Pos (5U)
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#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
@@ -13452,6 +13454,9 @@ typedef struct
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/******************************************************************************/
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/* Bit definition for Ethernet DMA Bus Mode Register */
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+ #define ETH_DMABMR_MB_Pos (26U)
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+ #define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */
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+ #define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
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#define ETH_DMABMR_AAB_Pos (25U)
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#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
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#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
@@ -15295,7 +15300,7 @@ typedef struct
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#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
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((INSTANCE) == TIM5))
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- /***************** TIM Instances : external trigger input availabe ************/
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+ /***************** TIM Instances : external trigger input available ************/
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#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
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((INSTANCE) == TIM2) || \
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((INSTANCE) == TIM3) || \
@@ -15600,7 +15605,3 @@ typedef struct
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#endif /* __cplusplus */
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#endif /* __STM32F407xx_H */
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-
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-
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-
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- /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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