Expand ADC feature set

[Crzyrndm]

Was just looking at adding ADC2/ADC3, but adc's are a fairly big target feature wise so a full list of features and implmentation status seems like a good starting point (from RM0394 "ADC main features"). Significant chunks of this will work and can be checked off immediately (for ADC1 anyway).

Going through the C HAL, it seems very likely that other than the number of peripherals present, the ADC behaves pretty much the same for all L4 and L4+ devices (minimal feature gating)

• ADC2 for L412 / L422
• ADC2 and ADC3 for L47+
• 12 / 10 / 8 / 6 bit resolution
• Oversampler (2-256x conversions / sample. <=16-bit output)
• Fast / Slow channels (first 5 channels of each ADC are "fast". No changes to firmware)
• input types
  • single
  • differential
• calibration
  • VDDA calibration procedure
  • save/restore calibration (calibration is lost when peri[heral is powered down)
• programmable sampling time (channel-wise)
• conversion modes
  • single / one-shot
  • continuous
  • discontinuous (run <= 8 conversions of a sequence, then pause until next trigger. See RM0394 16.4.20)
• channel sequencing and injected channels
  • "Regular group" of up to 16 conversions
  • "Injected group" of up to 4 conversions
• DMA integration
• DAC1 integration
• DAC1/2 internal channel (ADC2/3, L47+)
• DFSDM routing for L45 / L46 / L49 / L4A
• SMPPLUS control for L41 / L42 / L49 / L4A (ADC2 only for L41 / L42)
• Low power mode
• auto-delayed conversion (wait for conversion to be read before continuing. CPU not running fast enough to read data at full rate)
• Internal reference voltage (ADC1)
• Internal temperature sensor
  • ADC1
  • ADC3
• vbat monitoring
  • ADC1
  • ADC3
• start conversion triggers
  • software
  • timers
  • GPIO
• Dual ADC mode (ADC2 linked to ADC1. Conversion timings are matched up according to the selected mode)
• Analog window watchdogs
  • TIMx trigger
• Interrupts
  • ready
  • end conversion regular
  • end sequence regular
  • end conversion injected
  • end conversion injected sequence
  • analog watchdog 1-3
  • end of sampling phase
  • overrun
  • injected context overflow
• state management
  • deep power down (calibration lost) <-> disabled
  • disabled <-> enabled

Questions / Needs Research / ...

• ADC_COMMON register block is shared across ADC instances. F4-hal crate uses unsafe direct register access and doesn't hold an instance of the peripheral. Can this be done sensibly while retaining concurrency guarantees?
  • perhaps supporting the common case (static configuration) in the normal way, while providing unsafe access for the uncommon case (dynamically updates)

[Crzyrndm]

ADC1 does have some DMA integration. Not sure how complete it is (sub features?)