Merge pull request #168 from siliconcompiler/fazyrv

gadfort · web-flow · commit fb4be9ea3233 · 2025-01-28T15:54:06.000-07:00
add fazyrv design
diff --git a/.github/workflows/config/designs.json b/.github/workflows/config/designs.json
@@ -351,6 +351,46 @@
         "remote": false,
         "target": "skywater130_sky130hd"
     },
+    {
+        "design": "fazyrv",
+        "remote": false,
+        "target": "asap7_asap7sc7p5t_lvt"
+    },
+    {
+        "design": "fazyrv",
+        "remote": false,
+        "target": "asap7_asap7sc7p5t_rvt"
+    },
+    {
+        "design": "fazyrv",
+        "remote": false,
+        "target": "asap7_asap7sc7p5t_slvt"
+    },
+    {
+        "design": "fazyrv",
+        "remote": false,
+        "target": "freepdk45_nangate45"
+    },
+    {
+        "design": "fazyrv",
+        "remote": false,
+        "target": "gf180_gf180mcu_fd_sc_mcu7t5v0"
+    },
+    {
+        "design": "fazyrv",
+        "remote": false,
+        "target": "gf180_gf180mcu_fd_sc_mcu9t5v0"
+    },
+    {
+        "design": "fazyrv",
+        "remote": false,
+        "target": "ihp130_sg13g2_stdcell"
+    },
+    {
+        "design": "fazyrv",
+        "remote": false,
+        "target": "skywater130_sky130hd"
+    },
     {
         "design": "gcd",
         "remote": false,
diff --git a/pyproject.toml b/pyproject.toml
@@ -72,6 +72,6 @@ ignore = [
 ]
 
 [tool.codespell]
-skip = './build,./scgallery/designs/*/build,*.json,./scgallery/designs/*/src/*.v,./scgallery/designs/*/extra/*.v,./scgallery/designs/swerv/config/common_defines.vh'
+skip = './build,./scgallery/designs/*/build,*.json,./scgallery/designs/*/src/*.v,./scgallery/designs/*/extra/*.v,./scgallery/designs/*/extra/*.sv,./scgallery/designs/swerv/config/common_defines.vh'
 count = true
 quiet-level = 3
diff --git a/scgallery/designs/__init__.py b/scgallery/designs/__init__.py
@@ -5,6 +5,7 @@
 from .black_parrot import black_parrot
 from .dynamic_node import dynamic_node
 from .ethmac import ethmac
+from .fazyrv import fazyrv
 from .gcd import gcd
 from .heartbeat import heartbeat
 from .ibex import ibex
@@ -53,6 +54,7 @@ def __get_rules(design):
     datavault,
     dynamic_node,
     ethmac,
+    fazyrv,
     gcd,
     heartbeat,
     ibex,
diff --git a/scgallery/designs/fazyrv/constraints/asap7sc7p5t_lvt.sdc b/scgallery/designs/fazyrv/constraints/asap7sc7p5t_lvt.sdc
@@ -0,0 +1,12 @@
+set clk_period 1000
+set clk_io_pct 0.2
+
+set clk_port [get_ports clk_i]
+
+create_clock -name clk -period $clk_period $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set_input_delay [expr {$clk_period * $clk_io_pct}] -clock clk $non_clock_inputs
+set_output_delay [expr {$clk_period * $clk_io_pct}] -clock clk [all_outputs]
+
+set_driving_cell -lib_cell BUFx2_ASAP7_75t_L [all_inputs]
diff --git a/scgallery/designs/fazyrv/constraints/asap7sc7p5t_rvt.sdc b/scgallery/designs/fazyrv/constraints/asap7sc7p5t_rvt.sdc
@@ -0,0 +1,12 @@
+set clk_period 1000
+set clk_io_pct 0.2
+
+set clk_port [get_ports clk_i]
+
+create_clock -name clk -period $clk_period $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set_input_delay [expr {$clk_period * $clk_io_pct}] -clock clk $non_clock_inputs
+set_output_delay [expr {$clk_period * $clk_io_pct}] -clock clk [all_outputs]
+
+set_driving_cell -lib_cell BUFx2_ASAP7_75t_R [all_inputs]
diff --git a/scgallery/designs/fazyrv/constraints/asap7sc7p5t_slvt.sdc b/scgallery/designs/fazyrv/constraints/asap7sc7p5t_slvt.sdc
@@ -0,0 +1,12 @@
+set clk_period 1000
+set clk_io_pct 0.2
+
+set clk_port [get_ports clk_i]
+
+create_clock -name clk -period $clk_period $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set_input_delay [expr {$clk_period * $clk_io_pct}] -clock clk $non_clock_inputs
+set_output_delay [expr {$clk_period * $clk_io_pct}] -clock clk [all_outputs]
+
+set_driving_cell -lib_cell BUFx2_ASAP7_75t_SL [all_inputs]
diff --git a/scgallery/designs/fazyrv/constraints/gf180mcu_fd_sc_mcu7t5v0.sdc b/scgallery/designs/fazyrv/constraints/gf180mcu_fd_sc_mcu7t5v0.sdc
@@ -0,0 +1,12 @@
+set clk_period 29.25
+set clk_io_pct 0.2
+
+set clk_port [get_ports clk_i]
+
+create_clock -name clk_i -period $clk_period $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set_input_delay [expr {$clk_period * $clk_io_pct}] -clock clk $non_clock_inputs
+set_output_delay [expr {$clk_period * $clk_io_pct}] -clock clk [all_outputs]
+
+set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__buf_2 [all_inputs]
diff --git a/scgallery/designs/fazyrv/constraints/gf180mcu_fd_sc_mcu9t5v0.sdc b/scgallery/designs/fazyrv/constraints/gf180mcu_fd_sc_mcu9t5v0.sdc
@@ -0,0 +1,12 @@
+set clk_period 29.0
+set clk_io_pct 0.2
+
+set clk_port [get_ports clk_i]
+
+create_clock -name clk_i -period $clk_period $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set_input_delay [expr {$clk_period * $clk_io_pct}] -clock clk $non_clock_inputs
+set_output_delay [expr {$clk_period * $clk_io_pct}] -clock clk [all_outputs]
+
+set_driving_cell -lib_cell gf180mcu_fd_sc_mcu9t5v0__buf_2 [all_inputs]
diff --git a/scgallery/designs/fazyrv/constraints/nangate45.sdc b/scgallery/designs/fazyrv/constraints/nangate45.sdc
@@ -0,0 +1,12 @@
+set clk_period 1.50
+set clk_io_pct 0.2
+
+set clk_port [get_ports clk_i]
+
+create_clock -name clk_i -period $clk_period $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set_input_delay [expr {$clk_period * $clk_io_pct}] -clock clk $non_clock_inputs
+set_output_delay [expr {$clk_period * $clk_io_pct}] -clock clk [all_outputs]
+
+set_driving_cell -lib_cell BUF_X2 [all_inputs]
diff --git a/scgallery/designs/fazyrv/constraints/sg13g2_stdcell.sdc b/scgallery/designs/fazyrv/constraints/sg13g2_stdcell.sdc
@@ -0,0 +1,12 @@
+set clk_period 9
+set clk_io_pct 0.2
+
+set clk_port [get_ports clk_i]
+
+create_clock -name clk_i -period $clk_period $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set_input_delay [expr {$clk_period * $clk_io_pct}] -clock clk $non_clock_inputs
+set_output_delay [expr {$clk_period * $clk_io_pct}] -clock clk [all_outputs]
+
+set_driving_cell -lib_cell sg13g2_buf_1 [all_inputs]
diff --git a/scgallery/designs/fazyrv/constraints/sky130hd.sdc b/scgallery/designs/fazyrv/constraints/sky130hd.sdc
@@ -0,0 +1,12 @@
+set clk_period 36.0
+set clk_io_pct 0.2
+
+set clk_port [get_ports clk_i]
+
+create_clock -name clk -period $clk_period $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set_input_delay [expr {$clk_period * $clk_io_pct}] -clock clk $non_clock_inputs
+set_output_delay [expr {$clk_period * $clk_io_pct}] -clock clk [all_outputs]
+
+set_driving_cell -lib_cell sky130_fd_sc_hd__buf_2 [all_inputs]
diff --git a/scgallery/designs/fazyrv/extra/fazyrv_ram_sp.sv b/scgallery/designs/fazyrv/extra/fazyrv_ram_sp.sv
@@ -0,0 +1,43 @@
+// Copyright (c) 2023 - 2024 Meinhard Kissich
+// SPDX-License-Identifier: MIT
+// -----------------------------------------------------------------------------
+// File  :  fazyrv_ram_sp.v
+// Usage :  General purpose RAM used in FazyRV SoCs.
+//
+// Param
+//  - REGW        Width of registers.
+//  - ADRW        Width of address.
+//  - DEPTH       Depth of memory.
+//
+// Ports
+//  - clk_i       Clock input, sensitive to rising edge.
+//  - we_i        Write enable.
+//  - waddr_i     Write address.
+//  - raddr_i     Read address.
+//  - wdata_i     Write data.
+//  - rdata_o     Read data.
+// -----------------------------------------------------------------------------
+
+module fazyrv_ram_sp #( parameter REGW=32, parameter ADRW=5, parameter DEPTH=32 ) (
+  input  logic            clk_i,
+  input  logic            we_i,
+  input  logic [ADRW-1:0] waddr_i,
+  input  logic [ADRW-1:0] raddr_i,
+  input  logic [REGW-1:0] wdata_i,
+  output logic [REGW-1:0] rdata_o
+);
+
+la_spram #(
+        .DW(REGW),
+        .AW(ADRW)
+    ) ram (
+        .clk(clk_i),
+        .ce('b1),
+        .we(we_i),
+        .wmask({REGW{1'b1}}),
+        .addr(we_i ? waddr_i : raddr_i),
+        .din(wdata_i),
+        .dout(rdata_o)
+    );
+
+endmodule
diff --git a/scgallery/designs/fazyrv/extra/wb_ram.sv b/scgallery/designs/fazyrv/extra/wb_ram.sv
@@ -0,0 +1,49 @@
+
+module wb_ram #(parameter DEPTH=128, parameter MEMFILE="")
+(
+   input  logic                     clk_i,
+   input  logic                     cyc_i,
+   input  logic                     stb_i,
+   input  logic                     we_i,
+   output logic                     ack_o,
+   input  logic [3:0]               be_i,
+   input  logic [$clog2(DEPTH)-1:0] adr_i,
+   input  logic [31:0]              dat_i,
+   output logic [31:0]              dat_o
+
+);
+
+logic read_enable;
+logic write_enable;
+logic chip_enable;
+logic [31:0] mask;
+
+assign read_enable   = cyc_i & stb_i & ~we_i;
+assign write_enable  = cyc_i & stb_i & we_i;
+assign chip_enable   = read_enable | write_enable;
+assign mask          = {{8{be_i[3]}}, {8{be_i[2]}}, {8{be_i[1]}}, {8{be_i[0]}}};
+
+always @(posedge clk_i) begin
+   ack_o <= 'b0;
+
+   if (read_enable) begin
+      ack_o <= ~ack_o;
+   end else if (write_enable) begin
+      ack_o <= ~ack_o;
+   end
+end
+
+la_spram #(
+    .DW(32),
+    .AW($clog2(DEPTH))
+) ram (
+    .clk(clk_i),
+    .ce(chip_enable),
+    .we(write_enable),
+    .wmask(mask),
+    .addr(adr_i),
+    .din(dat_i),
+    .dout(dat_o)
+);
+
+endmodule
diff --git a/scgallery/designs/fazyrv/fazyrv.py b/scgallery/designs/fazyrv/fazyrv.py
@@ -0,0 +1,74 @@
+#!/usr/bin/env python3
+'''
+FazyRV -- A Scalable RISC-V Core
+A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
+'''
+
+from siliconcompiler import Chip
+from siliconcompiler.targets import skywater130_demo
+from scgallery import Gallery
+from lambdalib import ramlib
+
+
+def setup():
+    chip = Chip('fazyrv')
+
+    chip.register_source(name='fazyrv',
+                         path='git+https://github.com/meiniKi/FazyRV.git',
+                         ref='f287cf56b06ed20ead2d1dd0aab0c64ee50c5133')
+
+    chip.set('option', 'entrypoint', 'fsoc')
+
+    chip.set('option', 'param', 'RFTYPE', 'BRAM')
+    chip.set('option', 'param', 'CONF', 'MIN')
+    chip.set('option', 'param', 'CHUNKSIZE', '8')
+
+    for src in (
+            'rtl/fazyrv_hadd.v',
+            'rtl/fazyrv_fadd.v',
+            'rtl/fazyrv_cmp.v',
+            'rtl/fazyrv_alu.sv',
+            'rtl/fazyrv_decode.sv',
+            'rtl/fazyrv_decode_mem1.sv',
+            'rtl/fazyrv_shftreg.sv',
+            'rtl/fazyrv_csr.sv',
+            'rtl/fazyrv_rf_lut.sv',
+            'rtl/fazyrv_rf.sv',
+            'rtl/fazyrv_pc.sv',
+            'rtl/fazyrv_cntrl.sv',
+            'rtl/fazyrv_spm_a.sv',
+            'rtl/fazyrv_spm_d.sv',
+            'rtl/fazyrv_core.sv',
+            'rtl/fazyrv_top.sv',
+            'soc/rtl/gpio.sv',
+            'soc/rtl/fsoc.sv'):
+        chip.input(src, package='fazyrv')
+
+    chip.input('fazyrv/extra/fazyrv_ram_sp.sv', package='scgallery-designs')
+    chip.input('fazyrv/extra/wb_ram.sv', package='scgallery-designs')
+    chip.use(ramlib)
+
+    return chip
+
+
+def setup_physical(chip):
+    chip.set('option', 'define', 'SYNTHESIS')
+
+    if chip.get('option', 'pdk') == 'asap7':
+        chip.set('tool', 'openroad', 'task', 'macro_placement', 'var', 'macro_place_halo',
+                 [5, 1])
+    if chip.get('option', 'pdk') == 'freepdk45':
+        chip.set('tool', 'openroad', 'task', 'macro_placement', 'var', 'macro_place_halo',
+                 [10, 10])
+    if chip.get('option', 'pdk') == 'ihp130':
+        chip.set('constraint', 'aspectratio', 0.40)
+        chip.set('tool', 'openroad', 'task', 'macro_placement', 'var', 'macro_place_halo',
+                 [10, 40])
+
+
+if __name__ == '__main__':
+    chip = setup()
+    Gallery.design_commandline(chip, target=skywater130_demo, module_path=__file__)
+
+    chip.run()
+    chip.summary()

Original file line number	Diff line number	Diff line change
`@@ -72,6 +72,6 @@ ignore = [`
`72`	`72`	`]`
`73`	`73`
`74`	`74`	`[tool.codespell]`
`75`		`-skip = './build,./scgallery/designs//build,.json,./scgallery/designs//src/.v,./scgallery/designs//extra/.v,./scgallery/designs/swerv/config/common_defines.vh'`
	`75`	`+skip = './build,./scgallery/designs//build,.json,./scgallery/designs//src/.v,./scgallery/designs//extra/.v,./scgallery/designs//extra/.sv,./scgallery/designs/swerv/config/common_defines.vh'`
`76`	`76`	`count = true`
`77`	`77`	`quiet-level = 3`