Merge pull request #95 from siliconcompiler/add-port-info

add use and direction to macro ports

Author: gadfort

sc_leflib/_leflib.pxd

@@ -368,6 +368,10 @@ cdef extern from "lefrReader.hpp" namespace "LefParser":
 
     cdef cppclass lefiPin:
         const char* name()
+        int hasUse()
+        const char* use()
+        int hasDirection()
+        const char* direction()
         int numPorts()
         lefiGeometries* port(int index)
 

sc_leflib/_leflib.pyx

@@ -394,6 +394,14 @@ cdef int pin_cb(lefrCallbackType_e cb_type, lefiPin* pin, lefiUserData data) noe
         name = pin.name().decode('ascii')
         _state.data['macros'][_state.cur_macro]['pins'][name] = {}
 
+        if pin.hasDirection():
+            direction = pin.direction().decode('ascii')
+            _state.data['macros'][_state.cur_macro]['pins'][name]['direction'] = direction
+
+        if pin.hasUse():
+            use = pin.use().decode('ascii')
+            _state.data['macros'][_state.cur_macro]['pins'][name]['use'] = use
+
         ports = []
         for i in range(pin.numPorts()):
             port = pin.port(i)

tests/test_leflib.py

@@ -102,6 +102,8 @@ def test_leflib_complete(datadir):
     assert chk3a['size'] == {'width': 10.8, 'height': 28.8}
     assert len(chk3a['pins']) == 7
     vdd = chk3a['pins']['VDD']
+    assert vdd['direction'] == "INOUT"
+    assert vdd['use'] == "POWER"
     assert len(vdd['ports']) == 2
     port = vdd['ports'][1]
     assert port['class'] == 'NONE'