I am filing this issue to track the progress of simulating FIR kernel, the dataflow and corresponding functionality on each tile is summarized/captured in https://github.com/tancheng/VectorCGRA/blob/9db73bc072886df7e2f4e66f0ac40749a3021776/cgra/test/CgraRTL_fir_test.py#L246-L367, which already pass the RTL simulation. Thanks~!
I am filing this issue to track the progress of simulating FIR kernel, the dataflow and corresponding functionality on each tile is summarized/captured in https://github.com/tancheng/VectorCGRA/blob/9db73bc072886df7e2f4e66f0ac40749a3021776/cgra/test/CgraRTL_fir_test.py#L246-L367, which already pass the RTL simulation. Thanks~!