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25 files changed

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‎crates/core_arch/src/aarch64/neon/generated.rs

+348-348
Large diffs are not rendered by default.

‎crates/core_arch/src/aarch64/neon/mod.rs

+28-7
Original file line numberDiff line numberDiff line change
@@ -2074,7 +2074,10 @@ pub unsafe fn vget_low_p64(a: poly64x2_t) -> poly64x1_t {
20742074
#[target_feature(enable = "neon")]
20752075
#[rustc_legacy_const_generics(1)]
20762076
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2077-
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, IMM5 = 0))]
2077+
#[cfg_attr(
2078+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2079+
assert_instr(nop, IMM5 = 0)
2080+
)]
20782081
pub unsafe fn vget_lane_f64<const IMM5: i32>(v: float64x1_t) -> f64 {
20792082
static_assert!(IMM5 == 0);
20802083
simd_extract!(v, IMM5 as u32)
@@ -2085,7 +2088,10 @@ pub unsafe fn vget_lane_f64<const IMM5: i32>(v: float64x1_t) -> f64 {
20852088
#[target_feature(enable = "neon")]
20862089
#[rustc_legacy_const_generics(1)]
20872090
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2088-
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, IMM5 = 0))]
2091+
#[cfg_attr(
2092+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2093+
assert_instr(nop, IMM5 = 0)
2094+
)]
20892095
pub unsafe fn vgetq_lane_f64<const IMM5: i32>(v: float64x2_t) -> f64 {
20902096
static_assert_uimm_bits!(IMM5, 1);
20912097
simd_extract!(v, IMM5 as u32)
@@ -3417,7 +3423,10 @@ pub unsafe fn vsm3tt1aq_u32<const IMM2: i32>(
34173423
static_assert_uimm_bits!(IMM2, 2);
34183424
#[allow(improper_ctypes)]
34193425
extern "unadjusted" {
3420-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sm3tt1a")]
3426+
#[cfg_attr(
3427+
any(target_arch = "aarch64", target_arch = "arm64ec"),
3428+
link_name = "llvm.aarch64.crypto.sm3tt1a"
3429+
)]
34213430
fn vsm3tt1aq_u32_(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, imm2: i64) -> uint32x4_t;
34223431
}
34233432
vsm3tt1aq_u32_(a, b, c, IMM2 as i64)
@@ -3437,7 +3446,10 @@ pub unsafe fn vsm3tt1bq_u32<const IMM2: i32>(
34373446
static_assert_uimm_bits!(IMM2, 2);
34383447
#[allow(improper_ctypes)]
34393448
extern "unadjusted" {
3440-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sm3tt1b")]
3449+
#[cfg_attr(
3450+
any(target_arch = "aarch64", target_arch = "arm64ec"),
3451+
link_name = "llvm.aarch64.crypto.sm3tt1b"
3452+
)]
34413453
fn vsm3tt1bq_u32_(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, imm2: i64) -> uint32x4_t;
34423454
}
34433455
vsm3tt1bq_u32_(a, b, c, IMM2 as i64)
@@ -3457,7 +3469,10 @@ pub unsafe fn vsm3tt2aq_u32<const IMM2: i32>(
34573469
static_assert_uimm_bits!(IMM2, 2);
34583470
#[allow(improper_ctypes)]
34593471
extern "unadjusted" {
3460-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sm3tt2a")]
3472+
#[cfg_attr(
3473+
any(target_arch = "aarch64", target_arch = "arm64ec"),
3474+
link_name = "llvm.aarch64.crypto.sm3tt2a"
3475+
)]
34613476
fn vsm3tt2aq_u32_(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, imm2: i64) -> uint32x4_t;
34623477
}
34633478
vsm3tt2aq_u32_(a, b, c, IMM2 as i64)
@@ -3477,7 +3492,10 @@ pub unsafe fn vsm3tt2bq_u32<const IMM2: i32>(
34773492
static_assert_uimm_bits!(IMM2, 2);
34783493
#[allow(improper_ctypes)]
34793494
extern "unadjusted" {
3480-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sm3tt2b")]
3495+
#[cfg_attr(
3496+
any(target_arch = "aarch64", target_arch = "arm64ec"),
3497+
link_name = "llvm.aarch64.crypto.sm3tt2b"
3498+
)]
34813499
fn vsm3tt2bq_u32_(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, imm2: i64) -> uint32x4_t;
34823500
}
34833501
vsm3tt2bq_u32_(a, b, c, IMM2 as i64)
@@ -3493,7 +3511,10 @@ pub unsafe fn vxarq_u64<const IMM6: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64
34933511
static_assert_uimm_bits!(IMM6, 6);
34943512
#[allow(improper_ctypes)]
34953513
extern "unadjusted" {
3496-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.xar")]
3514+
#[cfg_attr(
3515+
any(target_arch = "aarch64", target_arch = "arm64ec"),
3516+
link_name = "llvm.aarch64.crypto.xar"
3517+
)]
34973518
fn vxarq_u64_(a: uint64x2_t, b: uint64x2_t, n: i64) -> uint64x2_t;
34983519
}
34993520
vxarq_u64_(a, b, IMM6 as i64)

‎crates/core_arch/src/arm_shared/barrier/mod.rs

+29-7
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
#[cfg(not(any(
55
// v8
66
target_arch = "aarch64",
7+
target_arch = "arm64ec",
78
// v7
89
target_feature = "v7",
910
// v6-M
@@ -13,6 +14,7 @@ mod cp15;
1314

1415
#[cfg(not(any(
1516
target_arch = "aarch64",
17+
target_arch = "arm64ec",
1618
target_feature = "v7",
1719
target_feature = "mclass"
1820
)))]
@@ -22,6 +24,7 @@ pub use self::cp15::*;
2224
// Dedicated instructions
2325
#[cfg(any(
2426
target_arch = "aarch64",
27+
target_arch = "arm64ec",
2528
target_feature = "v7",
2629
target_feature = "mclass"
2730
))]
@@ -47,30 +50,40 @@ macro_rules! dmb_dsb {
4750

4851
#[cfg(any(
4952
target_arch = "aarch64",
53+
target_arch = "arm64ec",
5054
target_feature = "v7",
5155
target_feature = "mclass"
5256
))]
5357
mod common;
5458

5559
#[cfg(any(
5660
target_arch = "aarch64",
61+
target_arch = "arm64ec",
5762
target_feature = "v7",
5863
target_feature = "mclass"
5964
))]
6065
#[unstable(feature = "stdarch_arm_barrier", issue = "117219")]
6166
pub use self::common::*;
6267

63-
#[cfg(any(target_arch = "aarch64", target_feature = "v7",))]
68+
#[cfg(any(
69+
target_arch = "aarch64",
70+
target_arch = "arm64ec",
71+
target_feature = "v7",
72+
))]
6473
mod not_mclass;
6574

66-
#[cfg(any(target_arch = "aarch64", target_feature = "v7",))]
75+
#[cfg(any(
76+
target_arch = "aarch64",
77+
target_arch = "arm64ec",
78+
target_feature = "v7",
79+
))]
6780
#[unstable(feature = "stdarch_arm_barrier", issue = "117219")]
6881
pub use self::not_mclass::*;
6982

70-
#[cfg(target_arch = "aarch64")]
83+
#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
7184
mod v8;
7285

73-
#[cfg(target_arch = "aarch64")]
86+
#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
7487
#[unstable(feature = "stdarch_arm_barrier", issue = "117219")]
7588
pub use self::v8::*;
7689

@@ -132,15 +145,24 @@ where
132145
}
133146

134147
extern "unadjusted" {
135-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.dmb")]
148+
#[cfg_attr(
149+
any(target_arch = "aarch64", target_arch = "arm64ec"),
150+
link_name = "llvm.aarch64.dmb"
151+
)]
136152
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.dmb")]
137153
fn dmb(_: i32);
138154

139-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.dsb")]
155+
#[cfg_attr(
156+
any(target_arch = "aarch64", target_arch = "arm64ec"),
157+
link_name = "llvm.aarch64.dsb"
158+
)]
140159
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.dsb")]
141160
fn dsb(_: i32);
142161

143-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.isb")]
162+
#[cfg_attr(
163+
any(target_arch = "aarch64", target_arch = "arm64ec"),
164+
link_name = "llvm.aarch64.isb"
165+
)]
144166
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.isb")]
145167
fn isb(_: i32);
146168
}

‎crates/core_arch/src/arm_shared/crc.rs

+34-10
Original file line numberDiff line numberDiff line change
@@ -1,26 +1,50 @@
11
extern "unadjusted" {
2-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32b")]
2+
#[cfg_attr(
3+
any(target_arch = "aarch64", target_arch = "arm64ec"),
4+
link_name = "llvm.aarch64.crc32b"
5+
)]
36
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32b")]
47
fn crc32b_(crc: u32, data: u32) -> u32;
5-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32h")]
8+
#[cfg_attr(
9+
any(target_arch = "aarch64", target_arch = "arm64ec"),
10+
link_name = "llvm.aarch64.crc32h"
11+
)]
612
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32h")]
713
fn crc32h_(crc: u32, data: u32) -> u32;
8-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32w")]
14+
#[cfg_attr(
15+
any(target_arch = "aarch64", target_arch = "arm64ec"),
16+
link_name = "llvm.aarch64.crc32w"
17+
)]
918
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")]
1019
fn crc32w_(crc: u32, data: u32) -> u32;
1120

12-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32cb")]
21+
#[cfg_attr(
22+
any(target_arch = "aarch64", target_arch = "arm64ec"),
23+
link_name = "llvm.aarch64.crc32cb"
24+
)]
1325
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cb")]
1426
fn crc32cb_(crc: u32, data: u32) -> u32;
15-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32ch")]
27+
#[cfg_attr(
28+
any(target_arch = "aarch64", target_arch = "arm64ec"),
29+
link_name = "llvm.aarch64.crc32ch"
30+
)]
1631
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32ch")]
1732
fn crc32ch_(crc: u32, data: u32) -> u32;
18-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32cw")]
33+
#[cfg_attr(
34+
any(target_arch = "aarch64", target_arch = "arm64ec"),
35+
link_name = "llvm.aarch64.crc32cw"
36+
)]
1937
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")]
2038
fn crc32cw_(crc: u32, data: u32) -> u32;
21-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32x")]
39+
#[cfg_attr(
40+
any(target_arch = "aarch64", target_arch = "arm64ec"),
41+
link_name = "llvm.aarch64.crc32x"
42+
)]
2243
fn crc32x_(crc: u32, data: u64) -> u32;
23-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32cx")]
44+
#[cfg_attr(
45+
any(target_arch = "aarch64", target_arch = "arm64ec"),
46+
link_name = "llvm.aarch64.crc32cx"
47+
)]
2448
fn crc32cx_(crc: u32, data: u64) -> u32;
2549
}
2650

@@ -104,7 +128,7 @@ pub unsafe fn __crc32cw(crc: u32, data: u32) -> u32 {
104128
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)
105129
#[inline]
106130
#[target_feature(enable = "crc")]
107-
#[cfg(target_arch = "aarch64")]
131+
#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
108132
#[cfg_attr(test, assert_instr(crc32x))]
109133
#[unstable(feature = "stdarch_arm_crc32", issue = "117215")]
110134
pub unsafe fn __crc32d(crc: u32, data: u64) -> u32 {
@@ -133,7 +157,7 @@ pub unsafe fn __crc32d(crc: u32, data: u64) -> u32 {
133157
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)
134158
#[inline]
135159
#[target_feature(enable = "crc")]
136-
#[cfg(target_arch = "aarch64")]
160+
#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
137161
#[cfg_attr(test, assert_instr(crc32cx))]
138162
#[unstable(feature = "stdarch_arm_crc32", issue = "117215")]
139163
pub unsafe fn __crc32cd(crc: u32, data: u64) -> u32 {

‎crates/core_arch/src/arm_shared/crypto.rs

+56-14
Original file line numberDiff line numberDiff line change
@@ -2,48 +2,90 @@ use crate::core_arch::arm_shared::{uint32x4_t, uint8x16_t};
22

33
#[allow(improper_ctypes)]
44
extern "unadjusted" {
5-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.aese")]
5+
#[cfg_attr(
6+
any(target_arch = "aarch64", target_arch = "arm64ec"),
7+
link_name = "llvm.aarch64.crypto.aese"
8+
)]
69
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aese")]
710
fn vaeseq_u8_(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
8-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.aesd")]
11+
#[cfg_attr(
12+
any(target_arch = "aarch64", target_arch = "arm64ec"),
13+
link_name = "llvm.aarch64.crypto.aesd"
14+
)]
915
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesd")]
1016
fn vaesdq_u8_(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
11-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.aesmc")]
17+
#[cfg_attr(
18+
any(target_arch = "aarch64", target_arch = "arm64ec"),
19+
link_name = "llvm.aarch64.crypto.aesmc"
20+
)]
1221
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesmc")]
1322
fn vaesmcq_u8_(data: uint8x16_t) -> uint8x16_t;
14-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.aesimc")]
23+
#[cfg_attr(
24+
any(target_arch = "aarch64", target_arch = "arm64ec"),
25+
link_name = "llvm.aarch64.crypto.aesimc"
26+
)]
1527
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesimc")]
1628
fn vaesimcq_u8_(data: uint8x16_t) -> uint8x16_t;
1729

18-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha1h")]
30+
#[cfg_attr(
31+
any(target_arch = "aarch64", target_arch = "arm64ec"),
32+
link_name = "llvm.aarch64.crypto.sha1h"
33+
)]
1934
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1h")]
2035
fn vsha1h_u32_(hash_e: u32) -> u32;
21-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha1su0")]
36+
#[cfg_attr(
37+
any(target_arch = "aarch64", target_arch = "arm64ec"),
38+
link_name = "llvm.aarch64.crypto.sha1su0"
39+
)]
2240
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su0")]
2341
fn vsha1su0q_u32_(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t;
24-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha1su1")]
42+
#[cfg_attr(
43+
any(target_arch = "aarch64", target_arch = "arm64ec"),
44+
link_name = "llvm.aarch64.crypto.sha1su1"
45+
)]
2546
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su1")]
2647
fn vsha1su1q_u32_(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t;
27-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha1c")]
48+
#[cfg_attr(
49+
any(target_arch = "aarch64", target_arch = "arm64ec"),
50+
link_name = "llvm.aarch64.crypto.sha1c"
51+
)]
2852
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1c")]
2953
fn vsha1cq_u32_(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
30-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha1p")]
54+
#[cfg_attr(
55+
any(target_arch = "aarch64", target_arch = "arm64ec"),
56+
link_name = "llvm.aarch64.crypto.sha1p"
57+
)]
3158
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1p")]
3259
fn vsha1pq_u32_(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
33-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha1m")]
60+
#[cfg_attr(
61+
any(target_arch = "aarch64", target_arch = "arm64ec"),
62+
link_name = "llvm.aarch64.crypto.sha1m"
63+
)]
3464
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1m")]
3565
fn vsha1mq_u32_(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
3666

37-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha256h")]
67+
#[cfg_attr(
68+
any(target_arch = "aarch64", target_arch = "arm64ec"),
69+
link_name = "llvm.aarch64.crypto.sha256h"
70+
)]
3871
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h")]
3972
fn vsha256hq_u32_(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t;
40-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha256h2")]
73+
#[cfg_attr(
74+
any(target_arch = "aarch64", target_arch = "arm64ec"),
75+
link_name = "llvm.aarch64.crypto.sha256h2"
76+
)]
4177
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h2")]
4278
fn vsha256h2q_u32_(hash_efgh: uint32x4_t, hash_abcd: uint32x4_t, wk: uint32x4_t) -> uint32x4_t;
43-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha256su0")]
79+
#[cfg_attr(
80+
any(target_arch = "aarch64", target_arch = "arm64ec"),
81+
link_name = "llvm.aarch64.crypto.sha256su0"
82+
)]
4483
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su0")]
4584
fn vsha256su0q_u32_(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t;
46-
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha256su1")]
85+
#[cfg_attr(
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any(target_arch = "aarch64", target_arch = "arm64ec"),
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link_name = "llvm.aarch64.crypto.sha256su1"
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)]
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#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su1")]
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fn vsha256su1q_u32_(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t;
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}

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