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Make FalseEdges always have two targets
We never have more than one imaginary target, so we have no reason for a `Vec`
1 parent 7519eac commit eef7615

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7 files changed

+21
-32
lines changed

7 files changed

+21
-32
lines changed

src/librustc/mir/mod.rs

+9-12
Original file line numberDiff line numberDiff line change
@@ -1180,9 +1180,9 @@ pub enum TerminatorKind<'tcx> {
11801180
FalseEdges {
11811181
/// The target normal control flow will take
11821182
real_target: BasicBlock,
1183-
/// The list of blocks control flow could conceptually take, but won't
1183+
/// A block control flow could conceptually take, but won't
11841184
/// in practice
1185-
imaginary_targets: Vec<BasicBlock>,
1185+
imaginary_target: BasicBlock,
11861186
},
11871187
/// A terminator for blocks that only take one path in reality, but where we
11881188
/// reserve the right to unwind in borrowck, even if it won't happen in practice.
@@ -1319,8 +1319,8 @@ impl<'tcx> TerminatorKind<'tcx> {
13191319
SwitchInt { ref targets, .. } => None.into_iter().chain(&targets[..]),
13201320
FalseEdges {
13211321
ref real_target,
1322-
ref imaginary_targets,
1323-
} => Some(real_target).into_iter().chain(&imaginary_targets[..]),
1322+
ref imaginary_target,
1323+
} => Some(real_target).into_iter().chain(slice::from_ref(imaginary_target)),
13241324
}
13251325
}
13261326

@@ -1406,10 +1406,10 @@ impl<'tcx> TerminatorKind<'tcx> {
14061406
} => None.into_iter().chain(&mut targets[..]),
14071407
FalseEdges {
14081408
ref mut real_target,
1409-
ref mut imaginary_targets,
1409+
ref mut imaginary_target,
14101410
} => Some(real_target)
14111411
.into_iter()
1412-
.chain(&mut imaginary_targets[..]),
1412+
.chain(slice::from_mut(imaginary_target)),
14131413
}
14141414
}
14151415

@@ -1712,12 +1712,9 @@ impl<'tcx> TerminatorKind<'tcx> {
17121712
Assert { cleanup: None, .. } => vec!["".into()],
17131713
Assert { .. } => vec!["success".into(), "unwind".into()],
17141714
FalseEdges {
1715-
ref imaginary_targets,
17161715
..
17171716
} => {
1718-
let mut l = vec!["real".into()];
1719-
l.resize(imaginary_targets.len() + 1, "imaginary".into());
1720-
l
1717+
vec!["real".into(), "imaginary".into()]
17211718
}
17221719
FalseUnwind {
17231720
unwind: Some(_), ..
@@ -3402,10 +3399,10 @@ impl<'tcx> TypeFoldable<'tcx> for Terminator<'tcx> {
34023399
Unreachable => Unreachable,
34033400
FalseEdges {
34043401
real_target,
3405-
ref imaginary_targets,
3402+
imaginary_target,
34063403
} => FalseEdges {
34073404
real_target,
3408-
imaginary_targets: imaginary_targets.clone(),
3405+
imaginary_target,
34093406
},
34103407
FalseUnwind {
34113408
real_target,

src/librustc_mir/borrow_check/mod.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -804,7 +804,7 @@ impl<'cx, 'gcx, 'tcx> DataflowResultsConsumer<'cx, 'tcx> for MirBorrowckCtxt<'cx
804804
| TerminatorKind::Unreachable
805805
| TerminatorKind::FalseEdges {
806806
real_target: _,
807-
imaginary_targets: _,
807+
imaginary_target: _,
808808
}
809809
| TerminatorKind::FalseUnwind {
810810
real_target: _,

src/librustc_mir/borrow_check/nll/invalidation.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -244,7 +244,7 @@ impl<'cx, 'tcx, 'gcx> Visitor<'tcx> for InvalidationGenerator<'cx, 'tcx, 'gcx> {
244244
| TerminatorKind::Unreachable
245245
| TerminatorKind::FalseEdges {
246246
real_target: _,
247-
imaginary_targets: _,
247+
imaginary_target: _,
248248
}
249249
| TerminatorKind::FalseUnwind {
250250
real_target: _,

src/librustc_mir/borrow_check/nll/type_check/mod.rs

+2-4
Original file line numberDiff line numberDiff line change
@@ -1789,12 +1789,10 @@ impl<'a, 'gcx, 'tcx> TypeChecker<'a, 'gcx, 'tcx> {
17891789
}
17901790
TerminatorKind::FalseEdges {
17911791
real_target,
1792-
ref imaginary_targets,
1792+
imaginary_target,
17931793
} => {
17941794
self.assert_iscleanup(mir, block_data, real_target, is_cleanup);
1795-
for target in imaginary_targets {
1796-
self.assert_iscleanup(mir, block_data, *target, is_cleanup);
1797-
}
1795+
self.assert_iscleanup(mir, block_data, imaginary_target, is_cleanup);
17981796
}
17991797
TerminatorKind::FalseUnwind {
18001798
real_target,

src/librustc_mir/build/matches/mod.rs

+4-6
Original file line numberDiff line numberDiff line change
@@ -973,9 +973,7 @@ impl<'a, 'gcx, 'tcx> Builder<'a, 'gcx, 'tcx> {
973973
source_info,
974974
TerminatorKind::FalseEdges {
975975
real_target: second_candidate.pre_binding_block,
976-
imaginary_targets: vec![
977-
first_candidate.next_candidate_pre_binding_block
978-
],
976+
imaginary_target: first_candidate.next_candidate_pre_binding_block,
979977
}
980978
)
981979
} else {
@@ -996,7 +994,7 @@ impl<'a, 'gcx, 'tcx> Builder<'a, 'gcx, 'tcx> {
996994
source_info,
997995
TerminatorKind::FalseEdges {
998996
real_target: unreachable,
999-
imaginary_targets: vec![candidate.next_candidate_pre_binding_block],
997+
imaginary_targets: candidate.next_candidate_pre_binding_block,
1000998
}
1001999
);
10021000
self.cfg.terminate(unreachable, source_info, TerminatorKind::Unreachable);
@@ -1013,7 +1011,7 @@ impl<'a, 'gcx, 'tcx> Builder<'a, 'gcx, 'tcx> {
10131011
source_info,
10141012
TerminatorKind::FalseEdges {
10151013
real_target: block,
1016-
imaginary_targets: vec![last_candidate.next_candidate_pre_binding_block]
1014+
imaginary_target: last_candidate.next_candidate_pre_binding_block,
10171015
}
10181016
);
10191017
Some(block)
@@ -1341,7 +1339,7 @@ impl<'a, 'gcx, 'tcx> Builder<'a, 'gcx, 'tcx> {
13411339
candidate_source_info,
13421340
TerminatorKind::FalseEdges {
13431341
real_target: block,
1344-
imaginary_targets: vec![candidate.next_candidate_pre_binding_block],
1342+
imaginary_target: candidate.next_candidate_pre_binding_block,
13451343
},
13461344
);
13471345
self.ascribe_types(block, &candidate.ascriptions);

src/librustc_mir/dataflow/mod.rs

+2-4
Original file line numberDiff line numberDiff line change
@@ -796,11 +796,9 @@ impl<'a, 'tcx: 'a, D> DataflowAnalysis<'a, 'tcx, D> where D: BitDenotation<'tcx>
796796
self.propagate_bits_into_entry_set_for(in_out, dest_bb, dirty_list);
797797
}
798798
}
799-
mir::TerminatorKind::FalseEdges { real_target, ref imaginary_targets } => {
799+
mir::TerminatorKind::FalseEdges { real_target, imaginary_target } => {
800800
self.propagate_bits_into_entry_set_for(in_out, real_target, dirty_list);
801-
for target in imaginary_targets {
802-
self.propagate_bits_into_entry_set_for(in_out, *target, dirty_list);
803-
}
801+
self.propagate_bits_into_entry_set_for(in_out, imaginary_target, dirty_list);
804802
}
805803
mir::TerminatorKind::FalseUnwind { real_target, unwind } => {
806804
self.propagate_bits_into_entry_set_for(in_out, real_target, dirty_list);

src/librustc_mir/transform/inline.rs

+2-4
Original file line numberDiff line numberDiff line change
@@ -784,11 +784,9 @@ impl<'a, 'tcx> MutVisitor<'tcx> for Integrator<'a, 'tcx> {
784784
}
785785
TerminatorKind::Abort => { }
786786
TerminatorKind::Unreachable => { }
787-
TerminatorKind::FalseEdges { ref mut real_target, ref mut imaginary_targets } => {
787+
TerminatorKind::FalseEdges { ref mut real_target, ref mut imaginary_target } => {
788788
*real_target = self.update_target(*real_target);
789-
for target in imaginary_targets {
790-
*target = self.update_target(*target);
791-
}
789+
*imaginary_target = self.update_target(*imaginary_target);
792790
}
793791
TerminatorKind::FalseUnwind { real_target: _ , unwind: _ } =>
794792
// see the ordering of passes in the optimized_mir query.

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