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Refactor powerpc64 call ABI handling
1 parent a886938 commit 715728f

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2 files changed

+144
-55
lines changed

2 files changed

+144
-55
lines changed

‎compiler/rustc_target/src/abi/call/powerpc64.rs

+12-55
Original file line numberDiff line numberDiff line change
@@ -41,64 +41,23 @@ where
4141
})
4242
}
4343

44-
fn classify_ret<'a, Ty, C>(cx: &C, ret: &mut ArgAbi<'a, Ty>, abi: ABI)
44+
fn classify<'a, Ty, C>(cx: &C, arg: &mut ArgAbi<'a, Ty>, abi: ABI, is_ret: bool)
4545
where
4646
Ty: TyAbiInterface<'a, C> + Copy,
4747
C: HasDataLayout,
4848
{
49-
if !ret.layout.is_sized() {
49+
if arg.is_ignore() || !arg.layout.is_sized() {
5050
// Not touching this...
5151
return;
5252
}
53-
if !ret.layout.is_aggregate() {
54-
ret.extend_integer_width_to(64);
53+
if !arg.layout.is_aggregate() {
54+
arg.extend_integer_width_to(64);
5555
return;
5656
}
5757

5858
// The ELFv1 ABI doesn't return aggregates in registers
59-
if abi == ELFv1 {
60-
ret.make_indirect();
61-
return;
62-
}
63-
64-
if let Some(uniform) = is_homogeneous_aggregate(cx, ret, abi) {
65-
ret.cast_to(uniform);
66-
return;
67-
}
68-
69-
let size = ret.layout.size;
70-
let bits = size.bits();
71-
if bits <= 128 {
72-
let unit = if cx.data_layout().endian == Endian::Big {
73-
Reg { kind: RegKind::Integer, size }
74-
} else if bits <= 8 {
75-
Reg::i8()
76-
} else if bits <= 16 {
77-
Reg::i16()
78-
} else if bits <= 32 {
79-
Reg::i32()
80-
} else {
81-
Reg::i64()
82-
};
83-
84-
ret.cast_to(Uniform::new(unit, size));
85-
return;
86-
}
87-
88-
ret.make_indirect();
89-
}
90-
91-
fn classify_arg<'a, Ty, C>(cx: &C, arg: &mut ArgAbi<'a, Ty>, abi: ABI)
92-
where
93-
Ty: TyAbiInterface<'a, C> + Copy,
94-
C: HasDataLayout,
95-
{
96-
if !arg.layout.is_sized() {
97-
// Not touching this...
98-
return;
99-
}
100-
if !arg.layout.is_aggregate() {
101-
arg.extend_integer_width_to(64);
59+
if is_ret && abi == ELFv1 {
60+
arg.make_indirect();
10261
return;
10362
}
10463

@@ -108,7 +67,10 @@ where
10867
}
10968

11069
let size = arg.layout.size;
111-
if size.bits() <= 64 {
70+
if is_ret && size.bits() > 128 {
71+
// Non-homogeneous aggregates larger than two doublewords are returned indirectly.
72+
arg.make_indirect();
73+
} else if size.bits() <= 64 {
11274
// Aggregates smaller than a doubleword should appear in
11375
// the least-significant bits of the parameter doubleword.
11476
arg.cast_to(Reg { kind: RegKind::Integer, size })
@@ -138,14 +100,9 @@ where
138100
}
139101
};
140102

141-
if !fn_abi.ret.is_ignore() {
142-
classify_ret(cx, &mut fn_abi.ret, abi);
143-
}
103+
classify(cx, &mut fn_abi.ret, abi, true);
144104

145105
for arg in fn_abi.args.iter_mut() {
146-
if arg.is_ignore() {
147-
continue;
148-
}
149-
classify_arg(cx, arg, abi);
106+
classify(cx, arg, abi, false);
150107
}
151108
}

‎tests/assembly/powerpc64-struct-abi.rs

+132
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,132 @@
1+
//@ revisions: elfv1-be elfv2-be elfv2-le
2+
//@ assembly-output: emit-asm
3+
//@ compile-flags: -O
4+
//@[elfv1-be] compile-flags: --target powerpc64-unknown-linux-gnu
5+
//@[elfv1-be] needs-llvm-components: powerpc
6+
//@[elfv2-be] compile-flags: --target powerpc64-unknown-linux-musl
7+
//@[elfv2-be] needs-llvm-components: powerpc
8+
//@[elfv2-le] compile-flags: --target powerpc64le-unknown-linux-gnu
9+
//@[elfv2-le] needs-llvm-components: powerpc
10+
//@[elfv1-be] filecheck-flags: --check-prefix be
11+
//@[elfv2-be] filecheck-flags: --check-prefix be
12+
13+
#![feature(no_core, lang_items)]
14+
#![no_std]
15+
#![no_core]
16+
#![crate_type = "lib"]
17+
18+
#[lang = "sized"]
19+
trait Sized {}
20+
21+
#[lang = "copy"]
22+
trait Copy {}
23+
24+
#[lang = "freeze"]
25+
trait Freeze {}
26+
27+
#[lang = "unpin"]
28+
trait Unpin {}
29+
30+
impl Copy for u8 {}
31+
impl Copy for u16 {}
32+
impl Copy for u32 {}
33+
impl Copy for FiveU32s {}
34+
impl Copy for FiveU16s {}
35+
impl Copy for ThreeU8s {}
36+
37+
#[repr(C)]
38+
struct FiveU32s(u32, u32, u32, u32, u32);
39+
40+
#[repr(C)]
41+
struct FiveU16s(u16, u16, u16, u16, u16);
42+
43+
#[repr(C)]
44+
struct ThreeU8s(u8, u8, u8);
45+
46+
// CHECK-LABEL: read_large
47+
// be: lwz [[REG1:.*]], 16(4)
48+
// be-NEXT: stw [[REG1]], 16(3)
49+
// be-NEXT: ld [[REG2:.*]], 8(4)
50+
// be-NEXT: ld [[REG3:.*]], 0(4)
51+
// be-NEXT: std [[REG2]], 8(3)
52+
// be-NEXT: std [[REG3]], 0(3)
53+
// elfv2-le: lxvd2x [[REG1:.*]], 0, 4
54+
// elfv2-le-NEXT: lwz [[REG2:.*]], 16(4)
55+
// elfv2-le-NEXT: stw [[REG2]], 16(3)
56+
// elfv2-le-NEXT: stxvd2x [[REG1]], 0, 3
57+
// CHECK-NEXT: blr
58+
#[no_mangle]
59+
extern "C" fn read_large(x: &FiveU32s) -> FiveU32s {
60+
*x
61+
}
62+
63+
// CHECK-LABEL: read_medium
64+
// elfv1-be: lhz [[REG1:.*]], 8(4)
65+
// elfv1-be-NEXT: ld [[REG2:.*]], 0(4)
66+
// elfv1-be-NEXT: sth [[REG1]], 8(3)
67+
// elfv1-be-NEXT: std [[REG2]], 0(3)
68+
// elfv2-be: lhz [[REG1:.*]], 8(3)
69+
// elfv2-be-NEXT: ld 3, 0(3)
70+
// elfv2-be-NEXT: sldi 4, [[REG1]], 48
71+
// elfv2-le: ld [[REG1:.*]], 0(3)
72+
// elfv2-le-NEXT: lhz 4, 8(3)
73+
// elfv2-le-NEXT: mr 3, [[REG1]]
74+
// CHECK-NEXT: blr
75+
#[no_mangle]
76+
extern "C" fn read_medium(x: &FiveU16s) -> FiveU16s {
77+
*x
78+
}
79+
80+
// CHECK-LABEL: read_small
81+
// elfv1-be: lbz [[REG1:.*]], 2(4)
82+
// elfv1-be-NEXT: lhz [[REG2:.*]], 0(4)
83+
// elfv1-be-NEXT: stb [[REG1]], 2(3)
84+
// elfv1-be-NEXT: sth [[REG2]], 0(3)
85+
// elfv2-be: lhz [[REG1:.*]], 0(3)
86+
// elfv2-be-NEXT: lbz 3, 2(3)
87+
// elfv2-be-NEXT: rldimi 3, [[REG1]], 8, 0
88+
// elfv2-le: lbz [[REG1:.*]], 2(3)
89+
// elfv2-le-NEXT: lhz 3, 0(3)
90+
// elfv2-le-NEXT: rldimi 3, [[REG1]], 16, 0
91+
// CHECK-NEXT: blr
92+
#[no_mangle]
93+
extern "C" fn read_small(x: &ThreeU8s) -> ThreeU8s {
94+
*x
95+
}
96+
97+
// CHECK-LABEL: write_large
98+
// CHECK: std 3, 0(6)
99+
// be-NEXT: rldicl [[REG1:.*]], 5, 32, 32
100+
// CHECK-NEXT: std 4, 8(6)
101+
// be-NEXT: stw [[REG1]], 16(6)
102+
// elfv2-le-NEXT: stw 5, 16(6)
103+
// CHECK-NEXT: blr
104+
#[no_mangle]
105+
extern "C" fn write_large(x: FiveU32s, dest: &mut FiveU32s) {
106+
*dest = x;
107+
}
108+
109+
// CHECK-LABEL: write_medium
110+
// CHECK: std 3, 0(5)
111+
// be-NEXT: rldicl [[REG1:.*]], 4, 16, 48
112+
// be-NEXT: sth [[REG1]], 8(5)
113+
// elfv2-le-NEXT: sth 4, 8(5)
114+
// CHECK-NEXT: blr
115+
#[no_mangle]
116+
extern "C" fn write_medium(x: FiveU16s, dest: &mut FiveU16s) {
117+
*dest = x;
118+
}
119+
120+
// CHECK-LABEL: write_small
121+
// be: stb 3, 2(4)
122+
// be-NEXT: srwi [[REG1:.*]], 3, 8
123+
// be-NEXT: sth [[REG1]], 0(4)
124+
// The order these instructions are emitted in changed in LLVM 18.
125+
// elfv2-le-DAG: sth 3, 0(4)
126+
// elfv2-le-DAG: srwi [[REG1:.*]], 3, 16
127+
// elfv2-le-NEXT: stb [[REG1]], 2(4)
128+
// CHECK-NEXT: blr
129+
#[no_mangle]
130+
extern "C" fn write_small(x: ThreeU8s, dest: &mut ThreeU8s) {
131+
*dest = x;
132+
}

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