clk: rockchip: rk3066: print arm enter and init rate

Change-Id: Iaf4ffbb61830b7bb7cef31843f0e9b75c34d08ec
Signed-off-by: Elaine Zhang <[email protected]>

Author: Elaine Zhang

arch/arm/include/asm/arch-rockchip/cru_rk3066.h

@@ -29,6 +29,11 @@ struct rk3066_clk_priv {
 	struct rk3066_cru *cru;
 	ulong rate;
 	bool has_bwadj;
+	ulong armclk_hz;
+	ulong armclk_enter_hz;
+	ulong armclk_init_hz;
+	bool sync_kernel;
+	bool set_armclk_rate;
 };
 
 struct rk3066_cru {
@@ -52,6 +57,12 @@ struct rk3066_cru {
 };
 check_member(rk3066_cru, cru_glb_cnt_th, 0x0140);
 
+struct rk3066_clk_info {
+	unsigned long id;
+	char *name;
+	bool is_cru;
+};
+
 /* CRU_CLKSEL0_CON */
 enum {
 	/* a9_core_div: core = core_src / (a9_core_div + 1) */

drivers/clk/rockchip/clk_rk3066.c

@@ -36,6 +36,22 @@ struct rk3066_clk_plat {
 #endif
 };
 
+#ifndef CONFIG_SPL_BUILD
+#define RK3066_CLK_DUMP(_id, _name, _iscru)	\
+{						\
+	.id = _id,				\
+	.name = _name,				\
+	.is_cru = _iscru,			\
+}
+
+static const struct rk3066_clk_info clks_dump[] = {
+	RK3066_CLK_DUMP(PLL_APLL, "apll", true),
+	RK3066_CLK_DUMP(PLL_DPLL, "dpll", true),
+	RK3066_CLK_DUMP(PLL_GPLL, "gpll", true),
+	RK3066_CLK_DUMP(PLL_CPLL, "cpll", true),
+};
+#endif
+
 struct pll_div {
 	u32 nr;
 	u32 nf;
@@ -550,10 +566,15 @@ static int rk3066_clk_probe(struct udevice *dev)
 
 	priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
 #endif
-
+	priv->sync_kernel = false;
+	if (!priv->armclk_enter_hz)
+		priv->armclk_enter_hz = rkclk_pll_get_rate(priv->cru,
+							   CLK_ARM);
 	rkclk_init(priv->cru, priv->grf, 1);
+	if (!priv->armclk_init_hz)
+		priv->armclk_init_hz = rkclk_pll_get_rate(priv->cru,
+							  CLK_ARM);
 #endif
-
 	return 0;
 }
 
@@ -609,3 +630,69 @@ U_BOOT_DRIVER(rockchip_rk3066a_cru) = {
 	.ofdata_to_platdata	= rk3066_clk_ofdata_to_platdata,
 	.probe			= rk3066_clk_probe,
 };
+
+#ifndef CONFIG_SPL_BUILD
+/**
+ * soc_clk_dump() - Print clock frequencies
+ * Returns zero on success
+ *
+ * Implementation for the clk dump command.
+ */
+int soc_clk_dump(void)
+{
+	struct udevice *cru_dev;
+	struct rk3066_clk_priv *priv;
+	const struct rk3066_clk_info *clk_dump;
+	struct clk clk;
+	unsigned long clk_count = ARRAY_SIZE(clks_dump);
+	unsigned long rate;
+	int i, ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_CLK,
+					  DM_GET_DRIVER(rockchip_rk3066a_cru),
+					  &cru_dev);
+	if (ret) {
+		printf("%s failed to get cru device\n", __func__);
+		return ret;
+	}
+
+	priv = dev_get_priv(cru_dev);
+	printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n",
+	       priv->sync_kernel ? "sync kernel" : "uboot",
+	       priv->armclk_enter_hz / 1000,
+	       priv->armclk_init_hz / 1000,
+	       priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0,
+	       priv->set_armclk_rate ? " KHz" : "N/A");
+	for (i = 0; i < clk_count; i++) {
+		clk_dump = &clks_dump[i];
+		if (clk_dump->name) {
+			clk.id = clk_dump->id;
+			if (clk_dump->is_cru)
+				ret = clk_request(cru_dev, &clk);
+			if (ret < 0)
+				return ret;
+
+			rate = clk_get_rate(&clk);
+			clk_free(&clk);
+			if (i == 0) {
+				if (rate < 0)
+					printf("  %s %s\n", clk_dump->name,
+					       "unknown");
+				else
+					printf("  %s %lu KHz\n", clk_dump->name,
+					       rate / 1000);
+			} else {
+				if (rate < 0)
+					printf("  %s %s\n", clk_dump->name,
+					       "unknown");
+				else
+					printf("  %s %lu KHz\n", clk_dump->name,
+					       rate / 1000);
+			}
+		}
+	}
+
+	return 0;
+}
+#endif
+