diff --git a/extensions/unratified/rv64_zbhlrsc b/extensions/unratified/rv64_zbhlrsc
new file mode 100644
index 00000000..7a08a17e
--- /dev/null
+++ b/extensions/unratified/rv64_zbhlrsc
@@ -0,0 +1,4 @@
+lr.b        rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=0 6..2=0x0B 1..0=3
+lr.h        rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=1 6..2=0x0B 1..0=3
+sc.b        rd rs1 rs2      aq rl 31..29=0 28..27=3 14..12=0 6..2=0x0B 1..0=3
+sc.h        rd rs1 rs2      aq rl 31..29=0 28..27=3 14..12=1 6..2=0x0B 1..0=3
diff --git a/extensions/unratified/rv64_zcherihybrid b/extensions/unratified/rv64_zcherihybrid
new file mode 100644
index 00000000..271f0f9e
--- /dev/null
+++ b/extensions/unratified/rv64_zcherihybrid
@@ -0,0 +1,2 @@
+modesw.cap        31..25=9  24..15=0 14..12=1 11..7=0 6..2=0x0C 1..0=3
+modesw.int        31..25=10 24..15=0 14..12=1 11..7=0 6..2=0x0C 1..0=3
diff --git a/extensions/unratified/rv64_cheri b/extensions/unratified/rv64_zcheripurecap
similarity index 74%
rename from extensions/unratified/rv64_cheri
rename to extensions/unratified/rv64_zcheripurecap
index 1d0af714..cfd60f5d 100644
--- a/extensions/unratified/rv64_cheri
+++ b/extensions/unratified/rv64_zcheripurecap
@@ -31,21 +31,6 @@ gclen             rd rs1 31..25=8 24..20=6 14..12=0 6..2=0x0C 1..0=3
 cram              rd rs1 31..25=8 24..20=7 14..12=0 6..2=0x0C 1..0=3
 sentry            rd rs1 31..25=8 24..20=8 14..12=0 6..2=0x0C 1..0=3
 
-modesw.cap        31..25=9  24..15=0 14..12=1 11..7=0 6..2=0x0C 1..0=3
-modesw.int        31..25=10 24..15=0 14..12=1 11..7=0 6..2=0x0C 1..0=3
-
-#adjacent to sh[123]add
-sh4add     rd rs1 rs2 31..25=16 14..12=7 6..2=0x0C 1..0=3
-
-#adjacent to sh[123]add.uw
-sh4add.uw  rd rs1 rs2 31..25=16 14..12=7 6..2=0x0E 1..0=3
-
-#regular encodings - will become a separate extension
-lr.b        rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=0 6..2=0x0B 1..0=3
-lr.h        rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=1 6..2=0x0B 1..0=3
-sc.b        rd rs1 rs2      aq rl 31..29=0 28..27=3 14..12=0 6..2=0x0B 1..0=3
-sc.h        rd rs1 rs2      aq rl 31..29=0 28..27=3 14..12=1 6..2=0x0B 1..0=3
-
 #regular encodings for double width datatype
 amoswap.c   rd rs1 rs2      aq rl 31..29=0 28..27=1 14..12=4 6..2=0x0B 1..0=3
 lr.c        rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=4 6..2=0x0B 1..0=3