diff --git a/src/aclic.adoc b/src/aclic.adoc index 8cd8b51..4150de4 100644 --- a/src/aclic.adoc +++ b/src/aclic.adoc @@ -167,7 +167,15 @@ https://creativecommons.org/licenses/by/4.0/. == Introduction The set of extensions defined in this specification enhance the existing interrupt specifications. -The Advanced Core Local Interrupt Controller (ACLIC) is a single hart interrupt controller defined for: + +The Advanced Interrupt Architecture (AIA) defines two types of external interrupt controller: + + * An interrupt controller that closely coupled with a hart (IMSIC, supporting only message-signaled interrupts). + * A shared, memory-mapped, platform interrupt controller for wired platform interrupts (APLIC) + +This specification introduces a third type of AIA compliant interrupt controller. + +The Advanced Core Local Interrupt Controller (ACLIC) is a single hart external interrupt controller optimized for real-time systems: * Low latency interrupt handling (achieved through nested preemption) * High throughput interrupt handling @@ -175,12 +183,15 @@ The Advanced Core Local Interrupt Controller (ACLIC) is a single hart interrupt * Low area overhead * Maximize compatibility with AIA +The ACLIC is closely coupled with a hart, and provides the same CSR and indirect-CSR interface as an IMSIC. +Since its interrupt inputs are wired rather than message-signaled, AIA source configuration and prioritization are required, as in the APLIC. +Additional indirect CSRs are introduced for this purpose. + The table below provides a summary of the ACLIC extensions. [%autowidth] |=== | Extension Name | Description -| Smaiae | Advanced Interrupt Architecture for Embedded Systems | Smaclic | Advanced Core Local Interrupt Controller at Machine level | Ssaclic | Advanced Core Local Interrupt Controller at Supervisor level | Smivt | Support for interrupt vector table at Machine level @@ -194,26 +205,25 @@ The table below provides a summary of the ACLIC extensions. |=== As this specification aims for single-hart systems, no support for the H extension is foreseen. -Future specifications could extend the scope of these extension to also be applicable in systems with H extension. +Future specifications could extend the scope of these extension to also be applicable in systems with the H extension. -Some extension depend upon other extensions. +Some extensions depend upon other extensions. This table summarizes all dependencies. Each row contains the dependencies of the extension named in the first column. [%autowidth] |=== -| Extension Name | Sm | Ss | Smcsrind | Sscsrind | Smaiae | Smnip -| Smivt | x | | | | | -| Ssivt | | x | | | | -| Smcsps | x | | | | | -| Sscsps | | x | | | | -| Smtp | (x)| (x)| | | | -| Smaiae | x | (x)| x | (x) | | -| Smaclic | | | | | x | -| Ssaclic | | | | | x | -| Smnip | | | | | x | -| Ssnip | | | | | | x -| Smehv | | | | | | x +| Extension Name | Sm | Ss | Smcsrind | Sscsrind | Smaclic | Smnip +| Smivt | x | | | | | +| Ssivt | | x | | | | +| Smcsps | x | | | | | +| Sscsps | | x | | | | +| Smtp | (x)| (x)| | | | +| Smaclic | x | | x | | | +| Ssaclic | | x | | x | x | +| Smnip | | | | | x | +| Ssnip | | | | | | x +| Smehv | | | | | | x |=== In this table (x) denotes a dependency that is valid, @@ -222,28 +232,17 @@ if the corresponding privilege mode is implemented in the hart. NOTE: The extensions defined here are orthogonal to the NMI and RNMI mechanisms. Their behavior is unchanged by the extensions of ACLIC. -== Advanced Interrupt Architecture for Embedded Systems (Smaiae) - -The Smaia extension encompasses all added CSRs -and all modifications to interrupt response behavior -that the AIA specifies for a hart, -over all privilege levels. - -The Smaiae extension is a subset of Smaia. -To limit the implementation cost, -the interrupt filtering and virtual interrupts are not supported. - -Specifically, `xvip` and `xvien` are read-only 0. -When XLEN=32, `xviph` and `xvienh` are also read-only 0. - -NOTE: While other features of AIA like IMSIC or programmable IPRIO -might also not be needed resource constraint systems, -These are already controlled by WARL registers, -so implementations can already choose to not support these. - == Advanced Core Local Interrupt Controller (Smaclic and Ssaclic) -The Smaclic and Ssaclic extensions depend on the Smaiae extension. +The Smaclic and Ssaclic extensions depend on the Smaia extension and Smcsrind or Sscsrind. + +NOTE: + * Many AIA features such as programmable IPRIO may not be needed in resource constrained systems. + Since these are already controlled by WARL registers, implementations can already choose to not support them. + * A minimal implementation of the `mvip` CSR is suggested by the AIA specification: + When supervisor mode is implemented, the minimal required implementation of mvien and mvip has all bits being + read-only zeros except for mvip bits 1 and 9, and sometimes bit 5, each of which is an alias of an existing + writable bit in mip. When supervisor mode is not implemented, registers mvien and mvip do not exist. Of the main ACLIC goals, these targets are addressed here: @@ -252,58 +251,45 @@ Of the main ACLIC goals, these targets are addressed here: * Maximize compatibility with AIA To achieve this, ACLIC builds upon the hart-level extensions of AIA, -and the Advanced Platform Level Interrupt Controller (APLIC). -The ACLIC is a tailored APLIC, optimized for resource efficiency, directly integrated with one hart. +adding equivalents to the interrupt source configuration and prioritization +mechanisms of the Advanced Platform Level Interrupt Controller (APLIC). In terms of compatibility, the goal is that a hart with Smaclic/Ssaclic extensions can be used at with the same trap handlers as one developed for AIA. -At config-time, the interface differs, -but ACLIC uses the same structure for configuration as the APLIC. - -=== New Interrupt Delivery Mode - -The Incoming Message Signaled Interrupt Controller (IMSIC) contains the {eidelivery} CSR, -which defines the interrupt delivery mode. -A new delivery mode is defined: - -[%autowidth,float="center",align="center",cols=">,<",grid=none,frame=none] -|=== -|0 = | Interrupt delivery is disabled -|1 = | Interrupt delivery from the interrupt file is enabled -|0x20000000 = | Interrupt delivery from an ACLIC (new) -|0x40000000 = | Interrupt delivery from a PLIC or APLIC is enabled -|=== - -If Smaclic or Ssaclic extensions are present, reset initializes {eidelivery} to 0x20000000. - -When interrupts are delivered from an ACLIC, the following behavior is valid: +Since the ACLIC is closely coupled to a single hart for which AIA already defines an +indirect CSR access mechanism, interrupt source and priority configuration is performed +using new indirect CSRs instead of the memory-mapped registers of an external APLIC. +The source and priority configuration data follow the same definitions as the equivalent APLIC fields. -The IMSIC registers {eithreshold}, {eipk} and {eiek} serve the same functionality as with {eidelivery} = 1. +NOTE: + * A hart can have only one closely coupled external interrupt controller, since there is no provision for CSRind space to be shared. + * A system can contain an APLIC as well as a closely coupled ACLIC; in this case {eidelivery} is + used to select which interrupt controller is connected to each of the hart's {xeip} interrupt inputs. -The `eip` array and `eie` array act as an alias of the pending and enable bits of the connected APLIC domain. +An ACLIC supports one interrupt file for machine mode interrupts. +The Ssaclic extension adds a second interrupt file for supervisor mode interrupts. -The {eithreshold} CSR is an alias of the {ithreshold}. -For the interrupt enable and interrupt pending bits {eipk} and {eiek}, -a write with the value 1 performs a write access with the value 1 to the corresponding {setip} or {setie} register, -while a write with the value 0 performs a write access with value 1 to the corresponding {in_clrip} or {clrie} register. -On read of {eipk} or {eiek}, these CSRs are an alias of {setip}[_k_] and {setie}[_k_], respectively. +The AIA-defined interrupt file configuration registers {eidelivery}, {eithreshold} and {eiek} work as +described in AIA Chapter 3 "Incoming MSI Controller". This includes their reset behaviour. +{eipk} behaviour depends on the interrupt source configuration, and is detailed below. -For XLEN=32, {eipk} and {eiek} access {setip}[_k_]/{in_clrip}[_k_] and {setie}[_k_]/{clrie}[_k_], respectively. -For XLEN=64, {eipk} and {eiek} only exist for even numbered indices of _k_. In this case, -{eipk} and {eiek} access {setip}[_k_]/{in_clrip}[_k_] and {setie}[_k_]/{clrie}[_k_] in the lower half of the CSR, -and {setip}[_k+1_]/{in_clrip}[_k_] and {setie}[_k+1_]/{clrie}[_k_] in the upper half of the CSR, respectively. +The number of interrupt identities supported by an ACLIC interrupt file is one less than a multiple of 64. +An ACLIC implementation can implement fewer than 63 interrupt identities. +In this case the {eip} and {eie} bits and source and priority configuration for the unimplemented +identities are WARL 0. -NOTE: Mirroring these APLIC registers at a core level has several advantages. - * It removes unnecessary resource duplication between IMSIC and APLIC when integrated with a single hart. +NOTE: Implementing these APLIC-equivalent registers as core level indirect CSRs has several advantages. * It simplifies the address decoding logic within the interrupt controller by using CSR access over memory mapped ones. - * It simplifies the handling of level-sensitive interrupts, avoiding additional checking of the pending flag in the APLIC in a handler of a level sensitive interrupt. * It provides a unified interface for all harts from a SW point of view, without the need to know a platform defined start address. - * It simplifies the register interface, as CSR instructions have single bit operations + * It does not require the special considerations for level-sensitive interrupts that are needed when APLIC delivers interrupts to an IMSIC. + * It simplifies the register interface, as CSR instructions have single bit operations. + * It simplifies software, because CSR operations are atomic. -The {xtopei} registers work analogous to the IMSIC operation, -but map to the current highest-priority pending-and-enabled interrupt of the connected APLIC domain. -In this delivery mode, the {xtopei} CSR reflect both the interrupt identity and the interrupt priority. +The {xtopei} registers work analogous to the IMSIC operation. +When {eidelivery} specifies that interrupts are delivered from the ACLIC interrupt file, {xtopei} +reports the current highest-priority pending-and-enabled interrupt in the file. +In this delivery mode, the {xtopei} CSR reflects both the interrupt identity and the interrupt priority. [%autowidth,float="center",align="center",cols=">,<",grid=none,frame=none] |=== @@ -311,13 +297,18 @@ In this delivery mode, the {xtopei} CSR reflect both the interrupt identity and |bits 10:0 | Interrupt priority (configured target[identity].iprio) |=== -=== Indirect CSR access to APLIC registers +=== Indirect CSR access to ACLIC source and priority configuration registers -The APLIC registers used in the ACLIC configuration can all be accessed by indirect CSRs, +The ACLIC interrupt source and priority configuration registers can all be accessed by indirect CSRs, eliminating the overheads associated with a memory mapped device, and presenting a consistent SW interface for any hart. -To have full control over the necessary APLIC registers, the following indirect CSR access is added. +Smaclic provides a set of registers that are accessible in machine mode and associated with the +ACLIC machine-mode interrupt file. Ssaclic adds a second set of registers associated with the supervisor-mode +interrupt file. + +When `xiselect` has a value in the range 0x1000-0x10FF, +attempts to access alias CSRs `xireg4` through `xireg6` raise an illegal instruction exception. ==== Interrupt Priority (iprio) @@ -325,16 +316,22 @@ When XLEN = 32, each `xireg` register controls the ACLIC priority setting of fou [%autowidth] |=== -| `xiselect` | `xireg` size | `xireg` state -| 0x1000 | 4B | `xacliciprio0` -| ... | ... | ... -| 0x1100 | 4B | `xacliciprio255` +| `xiselect` | `xireg` size | `xireg` state +| 0x1000 | 4B | `eiprio0` +| ... | ... | ... +| 0x10FF | 4B | `eiprio255` |=== -Indirect access to `xacliciprio[k]` mirror `target[k*4].iprio` up to `target[k*4+3].iprio`. +Each `eiprio` register controls the priorities of four interrupts, with one 8-bit byte per interrupt. For a +number k in the range 0–15, register `eipriok` controls the priorities of interrupts k × 4 through +k × 4 + 3, formatted as follows: +bits 7:0 Priority number for interrupt k × 4 +bits 15:8 Priority number for interrupt k × 4 + 1 +bits 23:16 Priority number for interrupt k × 4 + 2 +bits 31:24 Priority number for interrupt k × 4 + 3 When XLEN = 64, only the even-numbered registers exist and each register controls the priority setting of eight interrupts. -Indirect access to `xacliciprio[k]` mirror `target[k*4].iprio` up to `target[k*4+7].iprio`. +Indirect access to `eipriok` provides access to the priorities of interrupts `k × 8` up to `(k x 8) + 7`. ==== Source Configuration (sourcecfg) @@ -345,90 +342,88 @@ When XLEN = 32, the `xireg2` and `xireg3` registers combined control the source [%autowidth] |=== -| `xiselect` | `xireg2/3` size | `xireg2` state | `xireg3` state -| 0x1000 | 4B | `xaclicsourcecfg0` | `xaclicsourcecfg1` -| ... | ... | ... | ... -| 0x1100 | 4B | `xaclicsourcecfg510` | `xaclicsourcecfg511` -|=== - -Indirect access to `xaclicsourcecfg[k]` mirrors `sourcecfg[k*2][15:0]` up to `sourcecfg[k*2+1][15:0]`. - -When XLEN = 64, only the even-numbered registers exist and the `xireg2` and `xireg3` registers combined control the source configuration of eight interrupts. -Indirect access to `xaclicsourcecfg[k]` mirrors `sourcecfg[k*4][15:0]` up to `sourcecfg[k*4+3][15:0]`. - -=== APLIC configured for ACLIC operation - -The APLIC contains a per-domain configuration register, -which, among other things, allows selecting the delivery mode. -The `DM` field is extended to two bits, -which allows encoding a new mode for ACLIC delivery. - -[%autowidth,float="center",align="center",cols=">,<",grid=none,frame=none] -|=== -|0 = |direct delivery mode -|1 =|MSI delivery mode -|2 =|ACLIC delivery mode (new) +| `xiselect` | `xireg2/3` size | `xireg2` state | `xireg3` state +| 0x1000 | 4B | `eisourcecfg0` | `eicsourcecfg1` +| ... | ... | ... | ... +| 0x10FF | 4B | `eisourcecfg510` | `eisourcecfg511` |=== -If Smaclic and/or Ssaclic are implemented, -the reset value of the delivery mode for the respective domains shall be 'ACLIC delivery mode'. +Indirect access to `eisourcecfg[k]` provides access to the source configuration of interrupts `k x 2` and `(k x 2) + 1`. -The extended `domaincfg` register has this format: +When XLEN = 64, only the even-numbered registers exist and the `xireg2` and `xireg3` registers combined control +the source configuration of eight interrupts. +Indirect access to `eisourcecfg[k]` mirrors `provides access to the source configuration of interrupts `k x 4` up to +`(k x 4) + 3`. -[%autowidth,float="center",align="center",cols="<,<",grid=none,frame=none] -|=== -|bits 31:24 |read-only 0x80 -|bit 8|IE -|bit 7|read-only 0 -|bits 3:2 |DM (*WARL*) -|bit 0 |BE (*WARL*) -|=== - -All other register bits are reserved and read as zeros. +Each 11-bit source configuration is laid out as described in the AIA "Source configurations" section. +Since at most two interrupt files are supported by an ACLIC, delegation is greatly simplified. +ACLIC interrupt delegation simply controls whether interrupts are delegated from the machine-mode +interrupt file to the supervisor-mode interrupt file. -When in ACLIC delivery mode, the following, additional restrictions are applied: +If the Ssaclic extension is not present, writing '1' to the D (delegate) bit of an interrupt's source configuration +causes the interrupt's entire source configuration to be set to zero instead. -[%autowidth,float="center",align="center",cols="<,<",grid=none,frame=none] -|=== -|bits 31:24 |read-only 0x80 -|bit 8|IE = 1 (read-only) -|bit 7|read-only 0 -|bits 3:2 |DM = 2 -|bit 0 |BE (*WARL*) -|=== +If the Ssaclic extension is present: + * The D bit of the source configuration in the machine-mode of bit is writable. + * If the D bit is set in a machine-mode source configuration register, bits 9:0 must be set to zero. + * Setting the D bit in machine-mode source configuration delegates that interrupt to the supervisor-mode interrupt file. + * Writing '1' to the D (delegate) bit of an interrupt's supervisor-mode source configuration + causes the interupt's entire source configuration to be set to zero instead. -Specifically, = `IE` bit is fixed to 1, as its functionality is subsumed by the {xstatus}.`xIE` bits at the hart. - -If Smaclic and/or Ssaclic are implemented, -the reset value of the delivery mode for the respective domains shall be 'ACLIC delivery mode'. -In ACLIC-only systems, access to this register is not needed, and therefore no indirect CSR access is provided. - -In the ACLIC delivery mode, there the following registers are not accessible and not used: - -* As the ACLIC is not MSI capable, xmsiaddrcfg[h] and genmsi registers are not required. -* Interrupt delivery control (IDC) structure is only needed in direct delivery mode, and not applicable to ACLIC delivery. -* The indirect CSR access simplifies setting and clearing of individual bits in the pending and enable arrays. -Therefore, the registers setipnum, clripnum, setienum, clrienum, setipnum_be, and setipnum_le are not used in the ACLIC configuration. -* The target registers are not fully implemented. -The iprio portion of it can be accessed as described in the section on indirect access. -The rest is not required. +NOTE: Interrupt ID 0 cannot be used, and implementations can choose to make its configuration bits WARL 0. === State Enable Access to existing and repurposed AIA CSRs is already controlled by the state enables defined in Smaia/Ssaia. -Additional control is provided for the newly added registers `xacliciprio[k]` and `xaclicsourcecfg[k]`. +Additional control is provided for the newly added registers `eiprio[k]` and `eisourcecfg[k]`. If the Smstateen extension is implemented, then the bit ?? in mstateen0 is implemented. If bit ?? of a controlling mstateen0 CSR is zero, -then access to the new CSRs (`macliciprio[k]`, `maclicsourcecfg[k]`, `sacliciprio[k]`, `saclicsourcecfg[k]`) by S-mode or a lower privilege mode +then access to the source and priority configuration indirect CSRs (`eiprio[k]` and `eisourcecfg[k]`) +of either M-mode or S-mode interrupt files by S-mode or a lower privilege mode results in an illegal instruction exception, except if the hypervisor extension is implemented, and the conditions for a virtual instruction exception apply, in which case a virtual instruction exception is raised when in VS or VU mode instead of an illegal instruction exception. +=== Precise effects on interrupt-pending bits + +This section is to be read in conjunction with the AIA "Source configurations" section. + +NOTE: + * The behaviour of interrupt-pending bits is a simplified form of the APLIC interrupt-pending bit behaviour. + * These simplifications are possible because ACLIC is closely coupled to the hart and does not generate message-signaled interrupts. + +An attempt to set or clear an interrupt source’s pending bit by writing to an {eip} register in the interrupt +file may or may not be successful, depending on the corresponding source mode +and the state of the source’s rectified input value (defined in the AIA "Source configurations" section). + +The following enumerates all the circumstances when a pending bit is set or cleared for a given source mode. + +If the source mode is Detached: + * The pending bit is set to one only by writing '1' to the relevant {eip} indirect-CSR bit. + * The pending bit is cleared when the interrupt is claimed by an {mtopei} write, or by writing + '0' to the relevant {eip} indirect-CSR bit. + +If the source mode is Edge1 or Edge0: + * The pending bit is set to one by a low-to-high transition in the rectified input value, + or by writing '1' to the relevant {eip} indirect-CSR bit. + * The pending bit is cleared when the interrupt is claimed by an {mtopei} write, or by writing + '0' to the relevant {eip} indirect-CSR bit. + +If the source mode is Level1 or Level0 + * The pending bit is always just a copy of the rectified input value. + The pending bit cannot be set by a write to its {eip} indirect-CSR bit. + The pending bit is not cleared when the interrupt is claimed by an {mtopei} write, + nor can it be cleared by clearing the relevant {eip} indirect-CSR bit. + +In addition to the rules above, +a write to an {eisourcecfg} register can cause the source’s interrupt pending bit to be set to one, +as specified in the AIA "Source configurations" section. + == Conditional Stack Pointer Swap extension (Smcsps, Sscsps) The Sscsps depends on the Smcsps extension and adds the ability for conditional stack pointer swap at supervisor level and below. @@ -622,7 +617,7 @@ Included in: <> == Horizontal Nested Interrupt Preemption Support (Smnip & Ssip) -The Smnip extension depends on the Smaiae extension and adds nested preemption support at machine level. +The Smnip extension depends on the Smaia extension and adds nested preemption support at machine level. The Ssnip extension depends on the Smnip extension and adds nested preemption support at supervisor level. The extensions enable higher priority interrupts to preempt a lower priority interrupts in a nested fashion.