Major & external interrupts unification

Author: Evgenii Paltsev

src/aclic.adoc

@@ -183,8 +183,6 @@ The table below provides a summary of the ACLIC extensions.
 | Smaiae       | Advanced Interrupt Architecture for Embedded Systems
 | Smaclic      | Advanced Core Local Interrupt Controller at Machine level
 | Ssaclic      | Advanced Core Local Interrupt Controller at Supervisor level
-| Smivt        | Support for interrupt vector table at Machine level
-| Ssivt        | Support for interrupt vector table at Supervisor level
 | Smehv        | Synchronous exceptions hardware vectoring
 | Smcsps       | Conditional stack pointer swap at Machine level
 | Sscsps       | Conditional stack pointer swap at Supervisor level
@@ -203,8 +201,6 @@ Each row contains the dependencies of the extension named in the first column.
 [%autowidth]
 |===
 | Extension Name | Sm | Ss | Smcsrind | Sscsrind | Smaiae | Smnip
-| Smivt          | x  |    |          |          |        |  
-| Ssivt          |    | x  |          |          |        |  
 | Smcsps         | x  |    |          |          |        |  
 | Sscsps         |    | x  |          |          |        |  
 | Smtp           | (x)| (x)|          |          |        |  
@@ -413,6 +409,10 @@ Therefore, the registers setipnum, clripnum, setienum, clrienum, setipnum_be, an
 The iprio portion of it can be accessed as described in the section on indirect access.
 The rest is not required.
 
+=== Major interrupt redirection to ACLIC
+
+In ACLIC mode major interrupt sources are forwarded to ACLIC, according to their major identity numbers. In that mode CLINT is not used and ACLIC becomes the only source of interrupts for M/S-modes.
+
 === State Enable
 
 Access to existing and repurposed AIA CSRs is already controlled by the state enables defined in Smaia/Ssaia.
@@ -782,89 +782,45 @@ and the conditions for a virtual instruction exception apply,
 in which case a virtual instruction exception is raised
 when in VS or VU mode instead of an illegal instruction exception.
 
-== Support for interrupt vector table (Smivt, Ssivt)
-
-These extensions adds a new mode for taking interrupts via a dedicated interrupt vector table.
-
-This increases the range of reachable addresses to the entire address space.
-This is useful when handlers are more than 2 MiB away from the vector table entry.
+== Smaclic / Ssaclic Changes to {xtvec} CSR Mode
 
-In this new mode, when an interrupt is taken, the hart hardware loads the vector
-table entry for the associated interrupt (table pointed to new {xivt} or {xeivt} CSR),
-masks off the least-significant bit (for IALIGN=16) or masks of the 2 least-significant bits (for IALIGN=32),
-and then jumps to the masked address.
-
-=== Changed and new CSRs
+=== Changed CSRs
 
 [source]
 ----
        Number  Name         Description
        0x305   mtvec        M-mode Trap-handler base address / interrupt mode
- (NEW) 0x307   mivt         M-mode Interrupt-handler vector table base address
- (NEW) 0x308   meivt        M-mode External Interrupt-handler vector table base address
        0x105   stvec        S-mode Trap-handler base address / interrupt mode
- (NEW) 0x107   sivt         S-mode Interrupt-handler vector table base address
- (NEW) 0x108   seivt        S-mode External Interrupt-handler vector table base address
 ----
 
-==== New {xivt} and {xeivt} CSR
-
-Two new base addresses for vector tables are introduced.
-One for internal interrupt (major and local interrupts),
-and one for external interrupts.
-
-Both {xivt} and {xeivt} are WARL XLEN-bit CSRs,
-which hold the base address of the interrupt vector table.
-The address held in {xeivt} is aligned on a 64-byte or greater power-of-two boundary.
-Values other than 0 in the low 6 bits are reserved of {xeivt} are reserved.
-
-NOTE: The actual alignment can be determined
-by writing ones to the low-order bits
-then reading them back.
-
-NOTE: The resulting vector tables, especially for external interrupts,
-can consume non-negligible memory space.
-To limit the overall memory footprint,
-{xivt} or {xeivt} values at different privilege levels may be configured to the same values, respectively.
-
-==== New {xtvec} CSR Mode
-
-Interrupt vector table mode is encoded as a new state in the
-existing {xtvec} WARL register, where {xtvec}.`mode` (the two
-least-significant bits) is `11`.
-
-==== Smivt Changes to {xtvec} CSR Mode
-
 The PC upon interrupt is changed as follows:
 
 [source]
 ----
  mode  PC on Interrupt
  00    OBASE                                # Direct mode
- 01    OBASE+4*exccode                      # Vectored mode
- 11    M[VTBASE+XLEN/8*vtoffset] & VTMASK   # Interrupt vector table mode
+ 01    VECT                                 # Vectored mode
+ 11    Reserved
  10    Reserved
 
 where:
   M[a]     = Contents of memory address at address "a"
   VTMASK   = ~0x1 if IALIGN=16 or ~0x3 if IALIGN=32
   exccode  = xcause.Exception Code
+  vtoffset = Minor Interrupt Identity       # Corresponds to ACLIC topi[25:16]
 
   OBASE  = xtvec[XLEN-1:2]<<2   # Vector base is at least 4-byte aligned
-  if external interrupt:
-    VTBASE = xeivt[XLEN-1:6]<<6   # External Interrupt Vector Table base is at least 64-byte aligned
-    vtoffset = Minor Interrupt Identity
-    # Corresponds to xtopei[26:16] with interrupt delivery from interrupt file or ACLIC
+  if APLIC mode:
+    VECT = M[OBASE+XLEN/8*vtoffset] & VTMASK
   else
-    VTBASE = xivt[XLEN-1:2]<<2    # Interrupt Vector Table base is at least 4-byte aligned
-    vtoffset = Major Interrupt Identity
+    VECT = OBASE+4*exccode
 ----
 
-In interrupt vector table mode, when interrupts are taken, the interrupt behavior is modified as follows:
+If vectored mode is selected in {xtvec}, and APLIC mode is selected in {eidelivery}, when interrupts are taken, the interrupt behavior is modified as follows:
 After executing the required side-effects as required with the existing behavior,
 the hart then fetches an XLEN-bit handler address with permissions corresponding to the handler's mode
-from the in-memory table whose base address (VTBASE).
-The trap handler function address is fetched from `VTBASE+XLEN/8*exccode`.
+from the in-memory table whose base address (OBASE).
+The trap handler function address is fetched from `OBASE+XLEN/8*exccode`.
 If the fetch is successful, the hart clears the low bit(s) (depending on IALIGN) of the handler address,
 and sets the PC to this handler address.
 The masked vector table entry bit(s) are reserved and should be zero.
@@ -883,7 +839,7 @@ Memory writes to the vector table require an instruction barrier (_fence.i_) to
 
 It is recommended that the second fetch be ignored for hardware triggers and breakpoints.
 
-==== Vector table fault handling
+=== Vector table fault handling
 
 Faults that occur during the fetch of interrupt vector table entries are only recoverable,
 if the double trap extension(s) are implemented.
@@ -910,7 +866,7 @@ side-affects of the trap may only be executed if they allow resuming of operatio
 
 NOTE: Resuming after a fault on a vector table fetch is currently only seen as useful for instruction page faults.
 
-==== State Enable
+=== State Enable
 
 If the Smstateen extension is implemented,
 then the bit 53 (ACLIC) in mstateen0 is implemented.
@@ -924,6 +880,8 @@ when in VS or VU mode instead of an illegal instruction exception.
 
 == Synchronous exceptions hardware vectoring- Smehv
 
+NOTE: TBD
+
 The Smehv extension depends upon the Smivt extension.
 
 Accelerating synchronous exception handlers through vectoring may reduce interrupt latency.