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Evgenii PaltsevEvgenii Paltsev
Evgenii Paltsev
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Evgenii Paltsev
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Implement ACLIC as a subset of APLIC interface
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‎src/aclic.adoc‎

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@@ -209,8 +209,8 @@ Each row contains the dependencies of the extension named in the first column.
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| Sscsps | | x | | | |
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| Smtp | (x)| (x)| | | |
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| Smaiae | x | (x)| x | (x) | |
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| Smaclic | | | | | x |
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| Ssaclic | | | | | x |
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| Smaclic | | | | | |
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| Ssaclic | | | | | |
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| Smnip | | | | | x |
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| Ssnip | | | | | | x
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| Smehv | | | | | | x
@@ -243,186 +243,111 @@ so implementations can already choose to not support these.
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== Advanced Core Local Interrupt Controller (Smaclic and Ssaclic)
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The Smaclic and Ssaclic extensions depend on the Smaiae extension.
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Of the main ACLIC goals, these targets are addressed here:
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* Up to 1023 external interrupts
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* Low area overhead
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* Maximize compatibility with AIA
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To achieve this, ACLIC builds upon the hart-level extensions of AIA,
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and the Advanced Platform Level Interrupt Controller (APLIC).
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The ACLIC is a tailored APLIC, optimized for resource efficiency, directly integrated with one hart.
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In terms of compatibility, the goal is that a hart with Smaclic/Ssaclic extensions
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can be used at with the same trap handlers as one developed for AIA.
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At config-time, the interface differs,
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but ACLIC uses the same structure for configuration as the APLIC.
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=== New Interrupt Delivery Mode
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The Incoming Message Signaled Interrupt Controller (IMSIC) contains the {eidelivery} CSR,
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which defines the interrupt delivery mode.
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A new delivery mode is defined:
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[%autowidth,float="center",align="center",cols=">,<",grid=none,frame=none]
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|===
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|0 = | Interrupt delivery is disabled
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|1 = | Interrupt delivery from the interrupt file is enabled
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|0x20000000 = | Interrupt delivery from an ACLIC (new)
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|0x40000000 = | Interrupt delivery from a PLIC or APLIC is enabled
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|===
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To achieve this, ACLIC builds upon the Advanced Platform-Level Interrupt Controller (APLIC).
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The ACLIC is a tailored APLIC, optimized for resource efficiency and tightly integrated with a single hart. It utilizes APLIC direct delivery mode.
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If Smaclic or Ssaclic extensions are present, reset initializes {eidelivery} to 0x20000000.
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=== Interface
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When interrupts are delivered from an ACLIC, the following behavior is valid:
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ACLIC implements subset of AIA APLIC configuration and control interface defined by RISC-V AIA.
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ACLIC allows maximum of two domains for Machine and Supervisor modes respectively. Each domain may include:
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The IMSIC registers {eithreshold}, {eipk} and {eiek} serve the same functionality as with {eidelivery} = 1.
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- 1 domain configuration register.
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- Up to 1023 source configuration registers.
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- 4 interrupt pending and enable control registers.
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- 4 interrupt delivery control registers.
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The `eip` array and `eie` array act as an alias of the pending and enable bits of the connected APLIC domain.
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NOTE: Entire ACLIC interface is optimized for access by interrupt identity number (IID) to avoid unnecessary calculation of fields positions for the specific interrupt.
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The {eithreshold} CSR is an alias of the {ithreshold}.
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For the interrupt enable and interrupt pending bits {eipk} and {eiek},
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a write with the value 1 performs a write access with the value 1 to the corresponding {setip} or {setie} register,
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while a write with the value 0 performs a write access with value 1 to the corresponding {in_clrip} or {clrie} register.
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On read of {eipk} or {eiek}, these CSRs are an alias of {setip}[_k_] and {setie}[_k_], respectively.
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==== Interrupt Domain Configuration (domaincfg)
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For XLEN=32, {eipk} and {eiek} access {setip}[_k_]/{in_clrip}[_k_] and {setie}[_k_]/{clrie}[_k_], respectively.
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For XLEN=64, {eipk} and {eiek} only exist for even numbered indices of _k_. In this case,
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{eipk} and {eiek} access {setip}[_k_]/{in_clrip}[_k_] and {setie}[_k_]/{clrie}[_k_] in the lower half of the CSR,
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and {setip}[_k+1_]/{in_clrip}[_k_] and {setie}[_k+1_]/{clrie}[_k_] in the upper half of the CSR, respectively.
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NOTE: Mirroring these APLIC registers at a core level has several advantages.
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* It removes unnecessary resource duplication between IMSIC and APLIC when integrated with a single hart.
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* It simplifies the address decoding logic within the interrupt controller by using CSR access over memory mapped ones.
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* It simplifies the handling of level-sensitive interrupts, avoiding additional checking of the pending flag in the APLIC in a handler of a level sensitive interrupt.
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* It provides a unified interface for all harts from a SW point of view, without the need to know a platform defined start address.
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* It simplifies the register interface, as CSR instructions have single bit operations
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The {xtopei} registers work analogous to the IMSIC operation,
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but map to the current highest-priority pending-and-enabled interrupt of the connected APLIC domain.
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In this delivery mode, the {xtopei} CSR reflect both the interrupt identity and the interrupt priority.
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[%autowidth,float="center",align="center",cols=">,<",grid=none,frame=none]
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[%autowidth]
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|===
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|bits 26:16| Interrupt identity
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|bits 10:0 | Interrupt priority (configured target[identity].iprio)
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| Field | Position | Access | Description
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| IE | 8 | RW | Domain wide interrupt-enable
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| DM | 3:2 | RW | Delivery Mode (fixed to `direct delivery`)
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|===
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=== Indirect CSR access to APLIC registers
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Rest of the optional bits are implemented as read-only zeros.
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316-
The APLIC registers used in the ACLIC configuration can all be accessed by indirect CSRs,
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eliminating the overheads associated with a memory mapped device,
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and presenting a consistent SW interface for any hart.
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==== Interrupt Source Configuration (sourcecfgK)
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320-
To have full control over the necessary APLIC registers, the following indirect CSR access is added.
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Each implemented ACLIC interrupt has dedicated source configuration register which integrates all parameters dedicated to this interrupt.
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==== Interrupt Priority (iprio)
282+
The register layout depends on value of delegation flag `D`, which is accessible in M-domain configuration and is
283+
always read-only zero in S-domain configuration (assuming S-domain has no children).
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When XLEN = 32, each `xireg` register controls the ACLIC priority setting of four interrupts.
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sourcecfgK format, when interrupt source is delegated to a child domain:
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[%autowidth]
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|===
328-
| `xiselect` | `xireg` size | `xireg` state
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| 0x1000 | 4B | `xacliciprio0`
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| ... | ... | ...
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| 0x1100 | 4B | `xacliciprio255`
289+
| Field | Position | Access | Description
290+
| D = 1 | 10 | RW | M-domain interrupt source delegation is enabled
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| Child Index = 0 | 9:0 | RO | Read-only zero (as M-domain has only one child)
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|===
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Indirect access to `xacliciprio[k]` mirror `target[k*4].iprio` up to `target[k*4+3].iprio`.
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When XLEN = 64, only the even-numbered registers exist and each register controls the priority setting of eight interrupts.
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Indirect access to `xacliciprio[k]` mirror `target[k*4].iprio` up to `target[k*4+7].iprio`.
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==== Source Configuration (sourcecfg)
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When accessing the source configuration via indirect CSR, only the lower 16b are accessible,
342-
as the rest of the register is reserved.
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When XLEN = 32, the `xireg2` and `xireg3` registers combined control the source configuration of four interrupts.
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sourcecfgK format, when interrupt source is not delegated to a child domain:
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[%autowidth]
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|===
348-
| `xiselect` | `xireg2/3` size | `xireg2` state | `xireg3` state
349-
| 0x1000 | 4B | `xaclicsourcecfg0` | `xaclicsourcecfg1`
350-
| ... | ... | ... | ...
351-
| 0x1100 | 4B | `xaclicsourcecfg510` | `xaclicsourcecfg511`
298+
| Field | Position | Access | Description
299+
| IE | 31 | RO | Read-only interrupt-enable
300+
| IP | 30 | RO | Read-only (rectified) interrupt-pending
301+
| IPRIO | 23:16 | RW | Interrupt priority
302+
| D = 0 | 10 | RW | M-domain interrupt source delegation, read-only zero in S-domain
303+
| SM | 2:0 | RW | Source mode
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|===
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Indirect access to `xaclicsourcecfg[k]` mirrors `sourcecfg[k*2][15:0]` up to `sourcecfg[k*2+1][15:0]`.
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When XLEN = 64, only the even-numbered registers exist and the `xireg2` and `xireg3` registers combined control the source configuration of eight interrupts.
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Indirect access to `xaclicsourcecfg[k]` mirrors `sourcecfg[k*4][15:0]` up to `sourcecfg[k*4+3][15:0]`.
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The IE and IP fields are specific to ACLIC (reserved in case of APLIC) and provide read-only view
307+
of the interrupt-pending and interrupt-enable bits replacing the pending and enable arrays used by APLIC.
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=== APLIC configured for ACLIC operation
309+
To reduce registers addresses reservation the IPRIO field is moved from APLIC targetK[1..1023] registers.
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The APLIC contains a per-domain configuration register,
362-
which, among other things, allows selecting the delivery mode.
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The `DM` field is extended to two bits,
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which allows encoding a new mode for ACLIC delivery.
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The effective value of the non-delegated source configuration in S-domain is read-only zero.
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[%autowidth,float="center",align="center",cols=">,<",grid=none,frame=none]
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|===
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|0 = |direct delivery mode
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|1 =|MSI delivery mode
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|2 =|ACLIC delivery mode (new)
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|===
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==== Interrupt-Enable and Interrupt-Pending Control Registers
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If Smaclic and/or Ssaclic are implemented,
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the reset value of the delivery mode for the respective domains shall be 'ACLIC delivery mode'.
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ACLIC implements subset of interrupt-pending and interrupt-enable APLIC control interface. In addition to set / clear bit by number there are read-only interrupt-pending and interrupt-enable bits mirrored in the sourcecfgK register.
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The extended `domaincfg` register has this format:
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[%autowidth,float="center",align="center",cols="<,<",grid=none,frame=none]
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[%autowidth]
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|===
380-
|bits 31:24 |read-only 0x80
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|bit 8|IE
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|bit 7|read-only 0
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|bits 3:2 |DM (*WARL*)
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|bit 0 |BE (*WARL*)
319+
| Offset | Register name | Access | Description
320+
| 0x1000 | setipnum | RW | Set interrupt-pending by number
321+
| 0x1001 | clripnum | RW | Clear interrupt-pending by number
322+
| 0x1002 | setienum | RW | Set interrupt-enable by number
323+
| 0x1003 | clrienum | RW | Clear interrupt-enable by number
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|===
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All other register bits are reserved and read as zeros.
326+
NOTE: Interface is optimized for access by interrupt identity number (IID) to
327+
avoid unnecessary calculation of the bit positions. Hardware implementation is also
328+
simplified as there is no need to construct 32-bit pending/enable values based
329+
on per-interrupt delegation configuration.
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==== Interrupt Delivery Control Registers
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When in ACLIC delivery mode, the following, additional restrictions are applied:
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Similar to the APLIC in direct delivery mode, ACLIC provides the interrupt delivery control (IDC)
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registers structure to control the interrupt handling.
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[%autowidth,float="center",align="center",cols="<,<",grid=none,frame=none]
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[%autowidth]
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|===
393-
|bits 31:24 |read-only 0x80
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|bit 8|IE = 1 (read-only)
395-
|bit 7|read-only 0
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|bits 3:2 |DM = 2
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|bit 0 |BE (*WARL*)
338+
| Offset | Register name | Access | Description
339+
| 0x1004 | idelivery | RW | External interrupt delivery enable
340+
| 0x1006 | ithreshold | RW | External interrupt threshold
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| 0x1007 | topi | RO | Top priority external interrupt information
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| 0x1008 | claimi | RW | Top priority external interrupt claim
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|===
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400-
Specifically, = `IE` bit is fixed to 1, as its functionality is subsumed by the {xstatus}.`xIE` bits at the hart.
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402-
If Smaclic and/or Ssaclic are implemented,
403-
the reset value of the delivery mode for the respective domains shall be 'ACLIC delivery mode'.
404-
In ACLIC-only systems, access to this register is not needed, and therefore no indirect CSR access is provided.
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In the ACLIC delivery mode, there the following registers are not accessible and not used:
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* As the ACLIC is not MSI capable, xmsiaddrcfg[h] and genmsi registers are not required.
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* Interrupt delivery control (IDC) structure is only needed in direct delivery mode, and not applicable to ACLIC delivery.
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* The indirect CSR access simplifies setting and clearing of individual bits in the pending and enable arrays.
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Therefore, the registers setipnum, clripnum, setienum, clrienum, setipnum_be, and setipnum_le are not used in the ACLIC configuration.
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* The target registers are not fully implemented.
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The iprio portion of it can be accessed as described in the section on indirect access.
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The rest is not required.
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=== State Enable
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418-
Access to existing and repurposed AIA CSRs is already controlled by the state enables defined in Smaia/Ssaia.
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Additional control is provided for the newly added registers `xacliciprio[k]` and `xaclicsourcecfg[k]`.
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If the Smstateen extension is implemented,
423348
then the bit ?? in mstateen0 is implemented.
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If bit ?? of a controlling mstateen0 CSR is zero,
425-
then access to the new CSRs (`macliciprio[k]`, `maclicsourcecfg[k]`, `sacliciprio[k]`, `saclicsourcecfg[k]`) by S-mode or a lower privilege mode
350+
then access to the ACLIC CSRs by S-mode or a lower privilege mode
426351
results in an illegal instruction exception,
427352
except if the hypervisor extension is implemented,
428353
and the conditions for a virtual instruction exception apply,

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