Clarification on .vx semantics

[preames]

The wording in the instruction reference for the .vx variants could stand to be clarified.

The instruction reference page says "The vector-scalar (.vx) variant reuses a single 32-bit element, read from integer register rs1, instead of a vector (vs1) of such elements.". I had originally read this to mean that the scalar was broadcast to all input lanes, and then incorporated into the quad-wise summation.

After reading other parts in more depth, it's clear this is not the intended semantic. In particular, Figure 1 seems to indicate each byte in the 32b scalar input is repeated in an alternating fashion. This also seems to match the pseudo code given for the operation.

A possible suggestion on rewording would be something along the lines of the following:
"The vector-scalar (.vx) variant reuses a single 32-bit element, read from integer register rs1. As with the .vv variant, the 32-bit element is interpreted as a list of four 8-bit signed integer sub-elements. The 32-bit element is implicitly broadcast to each SEW lane of the input."

Or, if you don't want to try to message the English text, you could say:
"The vector-scalar (.vx) variant reuses a single 32-bit element, read from integer register rs1 in the manner shown in Figure 1, instead of a vector (vs1) of such elements "

Beyond the clarification in wording, can I inquire as to why this data format was chosen? It seems like the common case would be applying the same offset to all (input, SEW=8) lanes, and this data format will require packing of 4 identical copies of the byte value into the scalar register.