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tariqkurd-repoarichardson
tariqkurd-repo
and
arichardson
authoredFeb 26, 2025··
Update for ratified spec: Zilsd, Zclsd (#545)
Zilsd/Zclsd mean that LD, SD, C.LD, C.SD, C.LDSP, C.SCSP are available in RV32 --------- Signed-off-by: Alexander Richardson <mail@alexrichardson.me> Signed-off-by: Tariq Kurd <tariq.kurd@codasip.com> Co-authored-by: Alexander Richardson <mail@alexrichardson.me>
1 parent fc799eb commit 82cbda6

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+74
-142
lines changed
 

‎src/insns/load_16bit.adoc

+6-18
Original file line numberDiff line numberDiff line change
@@ -10,34 +10,22 @@ See <<C_LW>>.
1010
Synopsis::
1111
Load (C.LD, C.LW), 16-bit encodings
1212

13-
{cheri_cap_mode_name} Mnemonics (RV64)::
13+
{cheri_cap_mode_name} Mnemonics::
1414
`c.ld rd', offset(cs1')` +
1515
`c.lw rd', offset(cs1')`
1616

17-
{cheri_cap_mode_name} Expansions (RV64)::
17+
{cheri_cap_mode_name} Expansions::
1818
`ld rd', offset(cs1')` +
1919
`lw rd', offset(cs1')`
2020

21-
{cheri_int_mode_name} Mnemonics (RV64)::
21+
{cheri_int_mode_name} Mnemonics::
2222
`c.ld rd', offset(rs1')` +
2323
`c.lw rd', offset(rs1')`
2424

25-
{cheri_int_mode_name} Expansions (RV64)::
25+
{cheri_int_mode_name} Expansions::
2626
`ld rd', offset(rs1')` +
2727
`lw rd', offset(rs1')`
2828

29-
{cheri_cap_mode_name} Mnemonic (RV32)::
30-
`c.lw rd', offset(cs1')`
31-
32-
{cheri_cap_mode_name} Expansion (RV32)::
33-
`lw rd', offset(cs1')`
34-
35-
{cheri_int_mode_name} Mnemonic (RV32)::
36-
`c.lw rd', offset(rs1')`
37-
38-
{cheri_int_mode_name} Expansion (RV32)::
39-
`lw rd', offset(rs1')`
40-
4129
Encoding::
4230
include::wavedrom/reg-based-ldnstr.adoc[]
4331

@@ -50,10 +38,10 @@ Standard load instructions, authorized by the capability in <<ddc>>.
5038
include::load_exceptions.adoc[]
5139

5240
Prerequisites for {cheri_cap_mode_name} C.LD::
53-
RV64, and {c_cheri_base_ext_names}
41+
RV64 or RV32 with Zclsd, and {c_cheri_base_ext_names}
5442

5543
Prerequisites for {cheri_int_mode_name} C.LD::
56-
RV64, {c_cheri_default_ext_names}
44+
RV64 or RV32 and Zclsd, {c_cheri_default_ext_names}
5745

5846
Prerequisites {cheri_cap_mode_name} C.LW::
5947
{c_cheri_base_ext_names}

‎src/insns/load_16bit_sprel.adoc

+6-18
Original file line numberDiff line numberDiff line change
@@ -11,30 +11,18 @@ See <<C_LDSP>>.
1111
Synopsis::
1212
Load (C.LWSP, C.LDSP), 16-bit encodings
1313

14-
{cheri_cap_mode_name} Mnemonics (RV64)::
14+
{cheri_cap_mode_name} Mnemonics::
1515
`c.ld/c.lw rd, offset(csp)`
1616

17-
{cheri_cap_mode_name} Expansions (RV64)::
17+
{cheri_cap_mode_name} Expansions::
1818
`ld/lw rd, offset(csp)`
1919

20-
{cheri_int_mode_name} Mnemonics (RV64)::
20+
{cheri_int_mode_name} Mnemonics::
2121
`c.ld/c.lw rd, offset(sp)`
2222

23-
{cheri_int_mode_name} Expansions (RV64)::
23+
{cheri_int_mode_name} Expansions::
2424
`ld/lw rd, offset(sp)`
2525

26-
{cheri_cap_mode_name} Mnemonic (RV32)::
27-
`c.lw rd, offset(csp)`
28-
29-
{cheri_cap_mode_name} Expansion (RV32)::
30-
`lw rd, offset(csp)`
31-
32-
{cheri_int_mode_name} Mnemonic (RV32)::
33-
`c.lw rd, offset(sp)`
34-
35-
{cheri_int_mode_name} Expansion (RV32)::
36-
`lw rd, offset(sp)`
37-
3826
Encoding::
3927
include::wavedrom/c-sp-load-store.adoc[]
4028

@@ -47,10 +35,10 @@ Standard stack pointer relative load instructions, authorized by the capability
4735
include::load_exceptions.adoc[]
4836

4937
Prerequisites for {cheri_cap_mode_name} C.LDSP::
50-
RV64, and {c_cheri_base_ext_names}
38+
RV64 or RV32 and Zclsd, and {c_cheri_base_ext_names}
5139

5240
Prerequisites for {cheri_int_mode_name} C.LDSP::
53-
RV64, and {c_cheri_default_ext_names}
41+
RV64 or RV32 and Zclsd, and {c_cheri_default_ext_names}
5442

5543
Prerequisites for {cheri_cap_mode_name} C.LWSP::
5644
{c_cheri_base_ext_names}

‎src/insns/load_32bit.adoc

+4-14
Original file line numberDiff line numberDiff line change
@@ -32,28 +32,18 @@ See <<LB>>.
3232
Synopsis::
3333
Load (LD, LW[U], LH[U], LB[U])
3434

35-
{cheri_cap_mode_name} Mnemonics (RV64)::
35+
{cheri_cap_mode_name} Mnemonics::
3636
`ld rd, offset(cs1)` +
3737
`lw[u] rd, offset(cs1)` +
3838
`lh[u] rd, offset(cs1)` +
3939
`lb[u] rd, offset(cs1)`
4040

41-
{cheri_int_mode_name} Mnemonics (RV64)::
41+
{cheri_int_mode_name} Mnemonics::
4242
`ld rd, offset(rs1)` +
4343
`lw[u] rd, offset(rs1)` +
4444
`lh[u] rd, offset(rs1)` +
4545
`lb[u] rd, offset(rs1)`
4646

47-
{cheri_cap_mode_name} Mnemonics (RV32)::
48-
`lw rd, offset(cs1)` +
49-
`lh[u] rd, offset(cs1)` +
50-
`lb[u] rd, offset(cs1)`
51-
52-
{cheri_int_mode_name} Mnemonics (RV32)::
53-
`lw rd, offset(rs1)` +
54-
`lh[u] rd, offset(rs1)` +
55-
`lb[u] rd, offset(rs1)`
56-
5747
Encoding::
5848
include::wavedrom/load.adoc[]
5949

@@ -74,10 +64,10 @@ operation is <<ddc>>. A copy of the loaded value is written to `rd`.
7464
include::load_exceptions.adoc[]
7565

7666
Prerequisites for {cheri_cap_mode_name} LD::
77-
RV64, {cheri_base_ext_name}
67+
RV64 or RV32 and Zilsd, {cheri_base_ext_name}
7868

7969
Prerequisites for {cheri_int_mode_name} LD::
80-
RV64, {cheri_default_ext_name}
70+
RV64 or RV32 and Zilsd, {cheri_default_ext_name}
8171

8272
Prerequisites for {cheri_cap_mode_name} LW[U], LH[U], LB[U]::
8373
{cheri_base_ext_name}, OR +

‎src/insns/store_16bit.adoc

+6-18
Original file line numberDiff line numberDiff line change
@@ -11,34 +11,22 @@ See <<C.SW>>.
1111
Synopsis::
1212
Stores (C.SD, C.SW), 16-bit encodings
1313

14-
{cheri_cap_mode_name} Mnemonics (RV64)::
14+
{cheri_cap_mode_name} Mnemonics::
1515
`c.sd rs2', offset(cs1')` +
1616
`c.sw rs2', offset(cs1')`
1717

18-
{cheri_cap_mode_name} Expansions (RV64)::
18+
{cheri_cap_mode_name} Expansions::
1919
`sd rs2', offset(cs1')` +
2020
`sw rs2', offset(cs1')`
2121

22-
{cheri_int_mode_name} Mnemonics (RV64)::
22+
{cheri_int_mode_name} Mnemonics::
2323
`c.sd rs2', offset(rs1')` +
2424
`c.sw rs2', offset(rs1')`
2525

26-
{cheri_int_mode_name} Expansions (RV64)::
26+
{cheri_int_mode_name} Expansions::
2727
`sd rs2', offset(rs1')` +
2828
`sw rs2', offset(rs1')`
2929

30-
{cheri_cap_mode_name} Mnemonic (RV32)::
31-
`c.sw rs2', offset(cs1')`
32-
33-
{cheri_cap_mode_name} Expansion (RV32)::
34-
`sw rs2', offset(cs1')`
35-
36-
{cheri_int_mode_name} Mnemonic (RV32)::
37-
`c.sw rs2', offset(rs1')`
38-
39-
{cheri_int_mode_name} Expansion (RV32)::
40-
`sw rs2', offset(rs1')`
41-
4230
Encoding::
4331
include::wavedrom/c-cs-format-ls.adoc[]
4432

@@ -51,10 +39,10 @@ Standard store instructions, authorized by the capability in <<ddc>>.
5139
include::store_exceptions.adoc[]
5240

5341
Prerequisites for {cheri_cap_mode_name} C.SD::
54-
RV64, and {c_cheri_base_ext_names}
42+
RV64 or RV32 and Zclsd, and {c_cheri_base_ext_names}
5543

5644
Prerequisites for {cheri_int_mode_name} C.SD::
57-
RV64, and {c_cheri_default_ext_names}
45+
RV64 or RV32 and Zclsd, and {c_cheri_default_ext_names}
5846

5947
Prerequisites for {cheri_cap_mode_name} C.SW::
6048
{c_cheri_base_ext_names}

‎src/insns/store_16bit_sprel.adoc

+6-18
Original file line numberDiff line numberDiff line change
@@ -11,34 +11,22 @@ See <<C_SDSP>>.
1111
Synopsis::
1212
Stack pointer relative stores (C.SWSP, C.SDSP), 16-bit encodings
1313

14-
{cheri_cap_mode_name} Mnemonics (RV64)::
14+
{cheri_cap_mode_name} Mnemonics::
1515
`c.sd rs2, offset(csp)` +
1616
`c.sw rs2, offset(csp)`
1717

18-
{cheri_cap_mode_name} Expansions (RV64)::
18+
{cheri_cap_mode_name} Expansions::
1919
`sd rs2, offset(csp)` +
2020
`sw rs2, offset(csp)`
2121

22-
{cheri_int_mode_name} Mnemonics (RV64)::
22+
{cheri_int_mode_name} Mnemonics::
2323
`c.sd rs2, offset(sp)` +
2424
`c.sw rs2, offset(sp)`
2525

26-
{cheri_int_mode_name} Expansions (RV64)::
26+
{cheri_int_mode_name} Expansions::
2727
`sd rs2, offset(sp)` +
2828
`sw rs2, offset(sp)`
2929

30-
{cheri_cap_mode_name} Mnemonic (RV32)::
31-
`c.sw rs2, offset(csp)`
32-
33-
{cheri_cap_mode_name} Expansion (RV32)::
34-
`sw rs2, offset(csp)`
35-
36-
{cheri_int_mode_name} Mnemonic (RV32)::
37-
`c.sw rs2, offset(sp)`
38-
39-
{cheri_int_mode_name} Expansion (RV32)::
40-
`sw rs2, offset(sp)`
41-
4230
Encoding::
4331
include::wavedrom/c-sp-load-store-css.adoc[]
4432

@@ -51,10 +39,10 @@ Standard stack pointer relative store instructions, authorized by the capability
5139
include::store_exceptions.adoc[]
5240

5341
Prerequisites for {cheri_cap_mode_name} C.SDSP::
54-
RV64, and {c_cheri_base_ext_names}
42+
RV64 or RV32 and Zclsd, and {c_cheri_base_ext_names}
5543

5644
Prerequisites for {cheri_int_mode_name} C.SDSP::
57-
RV64, and {c_cheri_default_ext_names}
45+
RV64 or RV32 and Zclsd, and {c_cheri_default_ext_names}
5846

5947
Prerequisites for {cheri_cap_mode_name} C.SWSP::
6048
{c_cheri_base_ext_names}

‎src/insns/store_32bit.adoc

+4-14
Original file line numberDiff line numberDiff line change
@@ -20,28 +20,18 @@ See <<SB>>
2020
Synopsis::
2121
Stores (SD, SW, SH, SB)
2222

23-
{cheri_cap_mode_name} Mnemonics (RV64)::
23+
{cheri_cap_mode_name} Mnemonics::
2424
`sd rs2, offset(cs1)` +
2525
`sw rs2, offset(cs1)` +
2626
`sh rs2, offset(cs1)` +
2727
`sb rs2, offset(cs1)`
2828

29-
{cheri_int_mode_name} Mnemonics (RV64)::
29+
{cheri_int_mode_name} Mnemonics::
3030
`sd rs2, offset(rs1)` +
3131
`sw rs2, offset(rs1)` +
3232
`sh rs2, offset(rs1)` +
3333
`sb rs2, offset(rs1)`
3434

35-
{cheri_cap_mode_name} Mnemonics (RV32)::
36-
`sw rs2, offset(cs1)` +
37-
`sh rs2, offset(cs1)` +
38-
`sb rs2, offset(cs1)`
39-
40-
{cheri_int_mode_name} Mnemonics (RV32)::
41-
`sw rs2, offset(rs1)` +
42-
`sh rs2, offset(rs1)` +
43-
`sb rs2, offset(rs1)`
44-
4535
Encoding::
4636
include::wavedrom/store.adoc[]
4737

@@ -66,10 +56,10 @@ naturally aligned to CLEN/8 is cleared.
6656
include::store_exceptions.adoc[]
6757

6858
Prerequisites for {cheri_cap_mode_name} SD::
69-
RV64, {cheri_base_ext_name}
59+
RV64 or RV32 and Zilsd, {cheri_base_ext_name}
7060

7161
Prerequisites for {cheri_int_mode_name} SD::
72-
RV64, {cheri_default_ext_name}
62+
RV64 or RV32 and Zilsd, {cheri_default_ext_name}
7363

7464
Prerequisites for {cheri_cap_mode_name} SW, SH, SB::
7565
{cheri_base_ext_name}

‎src/insns/wavedrom/c-cs-format-ls.adoc

+1-1
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,6 @@
99
{bits: 2, name: 'uimm', type: 2, attr: ['2', 'offset[2|6]','offset[7:6]']},
1010
{bits: 3, name: 'rs1\'/cs1\'', type: 3, attr: ['3', 'base']},
1111
{bits: 3, name: 'uimm', types:3, attr: ['3', 'offset[5:3]']},
12-
{bits: 3, name: 'funct3', type: 8, attr: ['3', 'C.SW=110', 'rv64: C.SD=111']},
12+
{bits: 3, name: 'funct3', type: 8, attr: ['3', 'C.SW=110', 'C.SD=111']},
1313
], config: {bits: 16}}
1414
....

‎src/insns/wavedrom/c-sp-load-store-css.adoc

+1-1
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,6 @@
66
{bits: 2, name: 'op', type: 8, attr: ['2','C2=10']},
77
{bits: 5, name: 'rs2/cs2', type: 4, attr: ['5','src']},
88
{bits: 6, name: 'imm', type: 3, attr: ['6','offset[5:3|8:6]', 'offset[5:2|7:6]']},
9-
{bits: 3, name: 'funct3', type: 8, attr: ['3', 'rv64: C.SDSP=111', 'C.SWSP=110']},
9+
{bits: 3, name: 'funct3', type: 8, attr: ['3', 'C.SDSP=111', 'C.SWSP=110']},
1010
], config: {bits: 16}}
1111
....

‎src/insns/wavedrom/c-sp-load-store.adoc

+1-1
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,6 @@
99
{bits: 5, name: 'imm', type: 5, attr: ['5', 'offset[4:2|7:6]','offset[4:3|8:6]']},
1010
{bits: 5, name: 'rd', type: 5, attr: ['5','dest!=0']},
1111
{bits: 1, name: 'imm', type: 1, attr: ['1','[5]']},
12-
{bits: 3, name: 'funct3', type: 3, attr: ['3', 'C.LWSP=010', 'rv64: C.LDSP=011']},
12+
{bits: 3, name: 'funct3', type: 3, attr: ['3', 'C.LWSP=010', 'C.LDSP=011']},
1313
], config: {bits: 16}}
1414
....

‎src/insns/wavedrom/load.adoc

+1-1
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
{reg: [
66
{bits: 7, name: 'opcode', attr: ['7', 'LOAD=0000011'], type: 8},
77
{bits: 5, name: 'rd', attr: ['5', 'dest'], type: 2},
8-
{bits: 3, name: 'funct3', attr: ['3', 'width', 'LB=000', 'LH=001', 'LW=010', 'LBU=100', 'LHU=101', 'rv64: LWU=110', 'rv64: LD=011'], type: 8},
8+
{bits: 3, name: 'funct3', attr: ['3', 'width', 'LB=000', 'LH=001', 'LW=010', 'LBU=100', 'LHU=101', 'rv64: LWU=110', 'LD=011'], type: 8},
99
{bits: 5, name: 'rs1/cs1!=0',attr: ['5', 'base'], type: 4},
1010
{bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'], type: 3},
1111
]}

‎src/insns/wavedrom/reg-based-ldnstr.adoc

+1-1
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,6 @@
88
{bits: 2, name: 'imm', attr: ['2', 'offset[2|6]','offset[7:6]'], type: 2},
99
{bits: 3, name: 'rs1\'/cs1\'', attr: ['3', 'base'], type: 2},
1010
{bits: 3, name: 'imm', attr: ['3', 'offset[5:3]'], type: 3},
11-
{bits: 3, name: 'funct3', attr: ['3', 'C.LW=010', 'rv64: C.LD=011',], type: 8},
11+
{bits: 3, name: 'funct3', attr: ['3', 'C.LW=010', 'C.LD=011',], type: 8},
1212
], config: {bits: 16}}
1313
....

‎src/insns/wavedrom/store.adoc

+1-1
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
{reg: [
66
{bits: 7, name: 'opcode', attr: ['7', 'STORE=0100011'], type: 8},
77
{bits: 5, name: 'imm[4:0]', attr: ['5', 'offset[4:0]'], type: 3},
8-
{bits: 3, name: 'funct3', attr: ['3', 'SB=000','SH=001','SW=010','rv64: SD=011'], type: 8},
8+
{bits: 3, name: 'funct3', attr: ['3', 'SB=000','SH=001','SW=010','SD=011'], type: 8},
99
{bits: 5, name: 'rs1/cs1!=0', attr: ['5', 'base'], type: 4},
1010
{bits: 5, name: 'rs2', attr: ['5', 'src'], type: 4},
1111
{bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]'], type: 3},

‎src/instructions.adoc

+36-36
Original file line numberDiff line numberDiff line change
@@ -132,7 +132,7 @@ include::insns/store_32bit_fp.adoc[]
132132
One group of 16-bit encodings are remapped to different instructions dependent
133133
upon the CHERI execution mode, MXLEN and which extensions are supported.
134134

135-
NOTE: Zcf and Zilsd are incompatible
135+
NOTE: Zcf and Zclsd are incompatible
136136

137137
NOTE: Zcd and <<Zcmp>>/<<Zcmt>> incompatible
138138

@@ -144,16 +144,16 @@ NOTE: Zcd and <<Zcmp>>/<<Zcmt>> incompatible
144144
[width="100%",options=header]
145145
|==============================================================================
146146
2+|Encoding 5+| Supported Extensions
147-
|[15:13]|[1:0] | Zca | Zcf | Zcd | Zcmp/ Zcmt | Zilsd
148-
|111 |00 | N/A | C.FSW | N/A | N/A | C.SD
149-
|011 |00 | N/A | C.FLW | N/A | N/A | C.LD
150-
|111 |10 | N/A | C.FSWSP | N/A | N/A | C.SDSP
151-
|011 |10 | N/A | C.FLWSP | N/A | N/A | C.LDSP
152-
153-
|101 |00 | N/A | N/A | C.FSD | reserved^1^ | N/A
154-
|001 |00 | N/A | N/A | C.FLD | reserved^1^ | N/A
155-
|101 |10 | N/A | N/A | C.FSDSP | <<Zcmp>>/<<Zcmt>> | N/A
156-
|001 |10 | N/A | N/A | C.FLDSP | reserved^1^ | N/A
147+
|[15:13]|[1:0] | Zca | Zcf | Zcd | Zcmp/ Zcmt | Zclsd
148+
|111 |00 | N/A | <<C.FSW>> | N/A | N/A | <<C.SD>>
149+
|011 |00 | N/A | <<C.FLW>> | N/A | N/A | <<C.LD>>
150+
|111 |10 | N/A | <<C.FSWSP>> | N/A | N/A | <<C.SDSP>>
151+
|011 |10 | N/A | <<C.FLWSP>> | N/A | N/A | <<C.LDSP>>
152+
153+
|101 |00 | N/A | N/A | <<C.FSD>> | reserved^1^ | N/A
154+
|001 |00 | N/A | N/A | <<C.FLD>> | reserved^1^ | N/A
155+
|101 |10 | N/A | N/A | <<C.FSDSP>> | <<Zcmp>>/<<Zcmt>> | N/A
156+
|001 |10 | N/A | N/A | <<C.FLDSP>> | reserved^1^ | N/A
157157
|==============================================================================
158158

159159
^1^ reserved for future standard Zcm extensions
@@ -163,11 +163,11 @@ NOTE: Zcd and <<Zcmp>>/<<Zcmt>> incompatible
163163
[width="100%",options=header]
164164
|==============================================================================
165165
2+|Encoding 5+| Supported Extensions
166-
|[15:13]|[1:0] | Zca | Zcf | Zcd | Zcmp/ Zcmt | Zilsd
167-
|111 |00 5+| C.SC
168-
|011 |00 5+| C.LC
169-
|111 |10 5+| C.SCSP
170-
|011 |10 5+| C.LCSP
166+
|[15:13]|[1:0] | Zca | Zcf | Zcd | Zcmp/ Zcmt | Zclsd
167+
|111 |00 5+| <<C.SC>>
168+
|011 |00 5+| <<C.LC>>
169+
|111 |10 5+| <<C.SCSP>>
170+
|011 |10 5+| <<C.LCSP>>
171171

172172
|101 |00 | N/A | N/A | C.FSD | reserved^1^ | N/A
173173
|001 |00 | N/A | N/A | C.FLD | reserved^1^ | N/A
@@ -185,33 +185,33 @@ NOTE: Zcd and <<Zcmp>>/<<Zcmt>> incompatible
185185
[width="100%",options=header]
186186
|==============================================================================
187187
2+|Encoding 5+| Supported Extensions
188-
|[15:13]|[1:0] | Zca | Zcf | Zcd | Zcmp/ Zcmt | Zilsd
189-
|111 |00 | C.SD | N/A | N/A | N/A | N/A
190-
|011 |00 | C.LD | N/A | N/A | N/A | N/A
191-
|111 |10 | C.SDSP | N/A | N/A | N/A | N/A
192-
|011 |10 | C.LDSP | N/A | N/A | N/A | N/A
193-
194-
|101 |00 | N/A | N/A | C.FSD | reserved^1^ | N/A
195-
|001 |00 | N/A | N/A | C.FLD | reserved^1^ | N/A
196-
|101 |10 | N/A | N/A | C.FSDSP | <<Zcmp>>/<<Zcmt>> | N/A
197-
|001 |10 | N/A | N/A | C.FLDSP | reserved^1^ | N/A
188+
|[15:13]|[1:0] | Zca | Zcf | Zcd | Zcmp/ Zcmt | Zclsd
189+
|111 |00 | <<C.SD>> | N/A | N/A | N/A | N/A
190+
|011 |00 | <<C.LD>> | N/A | N/A | N/A | N/A
191+
|111 |10 | <<C.SDSP>> | N/A | N/A | N/A | N/A
192+
|011 |10 | <<C.LDSP>> | N/A | N/A | N/A | N/A
193+
194+
|101 |00 | N/A | N/A | <<C.FSD>> | reserved^1^ | N/A
195+
|001 |00 | N/A | N/A | <<C.FLD>> | reserved^1^ | N/A
196+
|101 |10 | N/A | N/A | <<C.FSDSP>> | <<Zcmp>>/<<Zcmt>> | N/A
197+
|001 |10 | N/A | N/A | <<C.FLDSP>> | reserved^1^ | N/A
198198
|==============================================================================
199199

200200
.16-bit instruction remapping in {cheri_cap_mode_name}
201201
[#16bit_insn_remapping_rv64_b]
202202
[width="100%",options=header]
203203
|==============================================================================
204204
2+|Encoding 5+| Supported Extensions
205-
|[15:13]|[1:0] | Zca | Zcf | Zcd | Zcmp/ Zcmt | Zilsd
206-
|111 |00 | C.SD | N/A | N/A | N/A | N/A
207-
|011 |00 | C.LD | N/A | N/A | N/A | N/A
208-
|111 |10 | C.SDSP | N/A | N/A | N/A | N/A
209-
|011 |10 | C.LDSP | N/A | N/A | N/A | N/A
210-
211-
|101 |00 5+| C.SC
212-
|001 |00 5+| C.LC
213-
|101 |10 5+| C.SCSP
214-
|001 |10 5+| C.LCSP
205+
|[15:13]|[1:0] | Zca | Zcf | Zcd | Zcmp/ Zcmt | Zclsd
206+
|111 |00 | <<C.SD>> | N/A | N/A | N/A | N/A
207+
|011 |00 | <<C.LD>> | N/A | N/A | N/A | N/A
208+
|111 |10 | <<C.SDSP>> | N/A | N/A | N/A | N/A
209+
|011 |10 | <<C.LDSP>> | N/A | N/A | N/A | N/A
210+
211+
|101 |00 5+| <<C.SC>>
212+
|001 |00 5+| <<C.LC>>
213+
|101 |10 5+| <<C.SCSP>>
214+
|001 |10 5+| <<C.LCSP>>
215215
|==============================================================================
216216

217217
include::insns/condbr_16bit.adoc[]

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