From b50d51c63dc097cbd27b07ad437cd4ea83d4bf22 Mon Sep 17 00:00:00 2001 From: Shashank V M Date: Thu, 2 Oct 2025 12:16:25 +0000 Subject: [PATCH 01/14] add softfloat_normSubnormalF32Sig function. --- spec/std/isa/isa/fp.idl | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/spec/std/isa/isa/fp.idl b/spec/std/isa/isa/fp.idl index 1dcfe70b94..04c956b439 100644 --- a/spec/std/isa/isa/fp.idl +++ b/spec/std/isa/isa/fp.idl @@ -475,6 +475,19 @@ function softfloat_normSubnormalF16Sig { } } +function softfloat_normSubnormalF32Sig { + returns Bits<8>, Bits<23> + arguments + Bits<32> sp_value + description { + normalize subnormal single-precision value + } + body { + Bits<8> shift_dist = count_leading_zeros<32>(sp_value) - 8; + return 1 - shift_dist, sp_value << shift_dist; + } +} + function softfloat_roundPackToF32 { returns Bits<32> # single precision value arguments @@ -759,7 +772,7 @@ function softfloat_addMagsF32 { U32 sigZ = 0x20000000 + sigA + sigB; if ( sigZ < 0x40000000 ) { - expZ = expZ - 1; + expZ = expZ `- 1'b1; sigZ = sigZ << 1; } } From 5dff6b0f6572455cfe0dccecd919a2d95ae0de58 Mon Sep 17 00:00:00 2001 From: Shashank V M Date: Thu, 2 Oct 2025 14:37:35 +0000 Subject: [PATCH 02/14] feat(idl): implement single precision fmul --- spec/std/isa/isa/fp.idl | 84 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/spec/std/isa/isa/fp.idl b/spec/std/isa/isa/fp.idl index 04c956b439..e04aac3514 100644 --- a/spec/std/isa/isa/fp.idl +++ b/spec/std/isa/isa/fp.idl @@ -313,6 +313,7 @@ function softfloat_shiftRightJam32 { } } + function softfloat_shiftRightJam64 { returns Bits<64> arguments @@ -1249,3 +1250,86 @@ function round_f32_to_integral { return i32_to_f32_no_flag(intermediate, mode); } } + +function f32_mul { + returns U32 + arguments + U32 a, + U32 b, + RoundingMode mode + description { + Returns product of 2 floating point numbers + } + body { + Bits<1> signA = signF32UI(a); + Bits<8> expA = expF32UI(a); + Bits<23> sigA = fracF32UI(a); + Bits<1> signB = signF32UI(b); + Bits<8> expB = expF32UI(b); + Bits<23> sigB = fracF32UI(b); + + # declare a variable to store significand of product + U32 sigZ; + + # declare a variable to store sign of product + Bits<1> signZ; + + # declare a variable to store the exponent part of product + Bits<8> expZ; + + # calculate sign of product + signZ = signA ^ signB; + + U32 magBits; + + if (expA == 0xFF) { + if ((sigA != 0) || ((expB == 0xFF) && (sigB != 0))) { + return softfloat_propagateNaNF32UI(a, b); + magBits = expB | sigB; + if (magBits == 0) { + set_fp_flag(FpFlag::NV); + return UI32_NAN; + } else { + return packToF32UI(signZ, 0xFF, 0); + } + } + } + + if (expB == 0xFF) { + if (sigB != 0) { + return softfloat_propagateNaNF32UI(a, b); + } + magBits = expA | sigA; + if (magBits == 0) { + set_fp_flag(FpFlag::NV); + return UI32_NAN; + } else { + return packToF32UI(signZ, 0xFF, 0); + } + } + + if (expA == 0) { + if (sigA == 0) { + return packtoF32UI(signZ, 0, 0); + } + (expA, sigA) = softfloat_normSubnormalF32Sig(sigA); + } + + if (expB == 0) { + if (sigB == 0) { + return packtoF32UI(signZ, 0, 0); + } + (expB, sigB) = softfloat_normSubnormalF32Sig(sigB); + } + + expZ = expA + expB - 0x7F; + sigA = (sigA | 0x00800000)<<7; + sigB = (sigB | 0x00800000)<<8; + sigZ = softfloat_shiftRightJam64(sigA `* sigB, 32); + if (sigZ < 0x40000000) { + expZ = expZ `- 1'b1; + sigZ = sigZ << 1; + } + return softfloat_roundPackToF32(signZ, expZ, sigZ); + } +} From f608f286d7f275bf093f5192cb4a449b3c0ba7b8 Mon Sep 17 00:00:00 2001 From: Shashank V M Date: Thu, 2 Oct 2025 14:51:35 +0000 Subject: [PATCH 03/14] data: add IDL operation for fmul --- spec/std/isa/inst/F/fmul.s.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/spec/std/isa/inst/F/fmul.s.yaml b/spec/std/isa/inst/F/fmul.s.yaml index 092fc2e74f..205928e93e 100644 --- a/spec/std/isa/inst/F/fmul.s.yaml +++ b/spec/std/isa/inst/F/fmul.s.yaml @@ -30,6 +30,9 @@ access: vu: always data_independent_timing: true operation(): | + check_f_ok($encoding); + RoundingMode mode = rm_to_mode(rm, $encoding); + f[fd] = f32_mul(f[fs1], f[fs2], mode); # SPDX-SnippetBegin # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model From c1cae334f3958d22f42103d804b37f86245558ff Mon Sep 17 00:00:00 2001 From: Shashank V M Date: Thu, 2 Oct 2025 14:59:06 +0000 Subject: [PATCH 04/14] fix: typo in packToF32UI function call --- spec/std/isa/isa/fp.idl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/spec/std/isa/isa/fp.idl b/spec/std/isa/isa/fp.idl index e04aac3514..259fa6aad2 100644 --- a/spec/std/isa/isa/fp.idl +++ b/spec/std/isa/isa/fp.idl @@ -1310,14 +1310,14 @@ function f32_mul { if (expA == 0) { if (sigA == 0) { - return packtoF32UI(signZ, 0, 0); + return packToF32UI(signZ, 0, 0); } (expA, sigA) = softfloat_normSubnormalF32Sig(sigA); } if (expB == 0) { if (sigB == 0) { - return packtoF32UI(signZ, 0, 0); + return packToF32UI(signZ, 0, 0); } (expB, sigB) = softfloat_normSubnormalF32Sig(sigB); } From c37c1d73feca1fb75a48bf8d8eb0777091ddecf1 Mon Sep 17 00:00:00 2001 From: Shashank V M Date: Thu, 2 Oct 2025 15:08:36 +0000 Subject: [PATCH 05/14] fix: function call to roundPackToF32 --- spec/std/isa/isa/fp.idl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/spec/std/isa/isa/fp.idl b/spec/std/isa/isa/fp.idl index 259fa6aad2..6763a447ed 100644 --- a/spec/std/isa/isa/fp.idl +++ b/spec/std/isa/isa/fp.idl @@ -1330,6 +1330,6 @@ function f32_mul { expZ = expZ `- 1'b1; sigZ = sigZ << 1; } - return softfloat_roundPackToF32(signZ, expZ, sigZ); + return softfloat_roundPackToF32(signZ, expZ, sigZ, mode); } } From 2f34cf9c8f55b615cb235b8ac2b780add2dd179d Mon Sep 17 00:00:00 2001 From: Shashank V M Date: Thu, 2 Oct 2025 17:14:11 +0000 Subject: [PATCH 06/14] feat(idl): single precision floating point division --- spec/std/isa/isa/fp.idl | 84 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/spec/std/isa/isa/fp.idl b/spec/std/isa/isa/fp.idl index 6763a447ed..3e68503c71 100644 --- a/spec/std/isa/isa/fp.idl +++ b/spec/std/isa/isa/fp.idl @@ -1333,3 +1333,87 @@ function f32_mul { return softfloat_roundPackToF32(signZ, expZ, sigZ, mode); } } + +function f32_div { + returns U32 + arguments + U32 a, + U32 b, + RoundingMode mode + description { + Returns quotient of 2 floating point numbers + } + body { + Bits<1> signA = signF32UI(a); + Bits<8> expA = expF32UI(a); + Bits<23> sigA = fracF32UI(a); + Bits<1> signB = signF32UI(b); + Bits<8> expB = expF32UI(b); + Bits<23> sigB = fracF32UI(b); + Bits<1> signZ = signA ^ signB; + Bits<8> expZ; + Bits<23> sigZ; + + U64 sig64A; + + if (expA == 0xFF) { + if (sigA != 0) { + return softfloat_propagateNaNF32UI(a, b); + } + if ((expB == 0xFF) && (sigB != 0)) { + return softfloat_propagateNaNF32UI(a, b); + } + if ((expB == 0xFF) && (sigB == 0)) { + set_fp_flag(FpFlag::NV); + return SP_CANONICAL_NAN; + } + return packToF32UI(signZ, 0xFF, 0); + } + + if (expB == 0xFF) { + if (sigB != 0) { + return softfloat_propagateNaNF32UI(a, b); + } + return packToF32UI(signZ, 0, 0); + } + + if (expB == 0) { + if (sigB == 0) { + if ((expA == 0) && (sigA == 0)) { + set_fp_flag(FpFlag::NV); + return SP_CANONICAL_NAN; + } + set_fp_flag(FpFlag::OF); + set_fp_flag(FpFlag::NX); + return packToF32UI(signZ, 0xFF, 0); + } + (expB, sigB) = softfloat_normSubnormalF32Sig(sigB); + } + if (expA == 0) { + if (sigA == 0) { + return packToF32UI(signZ, 0, 0); + } + (expA, sigA) = softfloat_normSubnormalF32Sig(sigA); + } + + expZ = expA - expB + 0x7E; + sigA = (sigA | 0x800000); + sigB = (sigB | 0x800000); + + if (sigA < sigB) { + expZ = expZ - 1; + sig64A = sigA `<< 31; + } else { + sig64A = sigA `<< 30; + } + + sigZ = sig64A / sigB; + # Check if the lower 6 bits are zero, meaning the division was exact. + # This is used to determine if rounding/jamming is needed. + if (!(sigZ & 0x3F)) { + sigZ = sigZ | ((sigB `* sigZ) != sig64A); + } + + return softfloat_roundPackToF32(signZ, expZ, sigZ, mode); + } +} From a32893785f7417f13edd37ffc695e09dfa2bdbe2 Mon Sep 17 00:00:00 2001 From: Shashank V M Date: Thu, 2 Oct 2025 17:40:21 +0000 Subject: [PATCH 07/14] fix: mark_f_state_dirty in fmul and fdiv --- spec/std/isa/inst/F/fdiv.s.yaml | 5 ++++- spec/std/isa/inst/F/fmul.s.yaml | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/spec/std/isa/inst/F/fdiv.s.yaml b/spec/std/isa/inst/F/fdiv.s.yaml index fd6804438e..a25f758dd4 100644 --- a/spec/std/isa/inst/F/fdiv.s.yaml +++ b/spec/std/isa/inst/F/fdiv.s.yaml @@ -30,7 +30,10 @@ access: vu: always data_independent_timing: true operation(): | - + check_f_ok($encoding); + RoundingMode mode = rm_to_mode(rm, $encoding); + f[fd] = f32_div(f[fs1], f[fs2], mode); + mark_f_state_dirty(); # SPDX-SnippetBegin # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model # SPDX-License-Identifier: BSD-2-Clause diff --git a/spec/std/isa/inst/F/fmul.s.yaml b/spec/std/isa/inst/F/fmul.s.yaml index 205928e93e..388f44e57c 100644 --- a/spec/std/isa/inst/F/fmul.s.yaml +++ b/spec/std/isa/inst/F/fmul.s.yaml @@ -33,6 +33,7 @@ operation(): | check_f_ok($encoding); RoundingMode mode = rm_to_mode(rm, $encoding); f[fd] = f32_mul(f[fs1], f[fs2], mode); + mark_f_state_dirty(); # SPDX-SnippetBegin # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model From 2db76c4adaa82f5e3fea3aca68c6da9e1a2b3f0d Mon Sep 17 00:00:00 2001 From: Shashank V M Date: Sat, 4 Oct 2025 17:31:44 +0000 Subject: [PATCH 08/14] feat(IDL): single precision multiply add --- spec/std/isa/inst/F/fmadd.s.yaml | 5 + spec/std/isa/isa/fp.idl | 200 +++++++++++++++++++++++++++++++ 2 files changed, 205 insertions(+) diff --git a/spec/std/isa/inst/F/fmadd.s.yaml b/spec/std/isa/inst/F/fmadd.s.yaml index 78aaa32744..12a49dfff9 100644 --- a/spec/std/isa/inst/F/fmadd.s.yaml +++ b/spec/std/isa/inst/F/fmadd.s.yaml @@ -31,6 +31,11 @@ access: vu: always data_independent_timing: true operation(): | + check_f_ok($encoding); + RoundingMode mode = rm_to_mode(rm, $encoding); + F32MulAddOp op = Softfloat_mulAdd_addC; + f[fd] = f32_muladd(f[fs1], f[fs2], op, mode); + mark_f_state_dirty(); # SPDX-SnippetBegin # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model diff --git a/spec/std/isa/isa/fp.idl b/spec/std/isa/isa/fp.idl index 3e68503c71..ca1f37d1bc 100644 --- a/spec/std/isa/isa/fp.idl +++ b/spec/std/isa/isa/fp.idl @@ -49,6 +49,12 @@ enum FpFlag { NV 0b10000 # Invalid Operation } +enum F32MulAddOp { + Softfloat_mulAdd_addC # will get value 0 + Softfloat_mulAdd_subC # will get value 1 + Softfloat_mulAdd_subProd # will get value 2 +} + function set_fp_flag { arguments FpFlag flag @@ -1417,3 +1423,197 @@ function f32_div { return softfloat_roundPackToF32(signZ, expZ, sigZ, mode); } } + +function propagateNaN_ABC { + returns U32 + arguments + U32 a, + U32 b, + U32 c + description { + Applies softfloat_propagateNaNF32UI to 3 numbers + } + body { + U32 z = softfloat_propagateNaNF32UI(a, b); + return softfloat_propagateNaNF32UI(z, c); + } +} + +function f32_muladd { + returns U32 + arguments + U32 a, + U32 b, + U32 c, + F32MulAddOp op, + RoundingMode mode + description { + Sum of the product of `a` and `b` with `c`. Sign of `c` depends on `op` + } + body { + Bits<1> signA = signF32UI(a); + Bits<8> expA = expF32UI(a); + Bits<23> sigA = fracF32UI(a); + Bits<1> signB = signF32UI(b); + Bits<8> expB = expF32UI(b); + Bits<23> sigB = fracF32UI(b); + Bits<1> signC = signF32UI(c) ^ (op == F32MulAddOp::Softfloat_mulAdd_subC); + Bits<8> expC = expF32UI(c); + Bits<23> sigC = fracF32UI(c); + Bits<1> signProd = (signA ^ signB) ^ (op == F32MulAddOp::Softfloat_mulAdd_subProd); + Bits<8> expProd; + U64 sigProd; + Bits<1> signZ; + Bits<8> expZ; + Bits<23> sigZ; + + Bits<32> Z; + U64 sig64Z, sig64C; + + Bits<32> expDiff; + + if (expA == 0xFF) { + if ((sigA != 0) || ((expB == 0xFF) && (sigB != 0))) { + propagateNaN_ABC(a,b,c); + } + magBits = expB | sigB; + if (magBits != 0) { + Z = packToF32UI(signProd, 0xFF, 0); + if (expC != 0xFF) { + return Z; + } + if (sigC != 0) { + softfloat_propagateNaNF32UI(Z, c); + } + if (signProd == signC) { + return Z; + } + } + set_fp_flag(FpFlag::NV); + Z = UI32_NaN; + softfloat_propagateNaNF32UI(Z, c); + return Z; + } + + if (expB == 0xFF) { + if (sigB != 0) { + propagateNaN_ABC(a,b,c); + } + magBits = expA | sigA; + if (magBits != 0) { + Z = packToF32UI(signProd, 0xFF, 0); + if (expC != 0xFF) { + return Z; + } + if (sigC != 0) { + softfloat_propagateNaNF32UI(Z, c); + } + if (signProd == signC) { + return Z; + } + } + set_fp_flag(FpFlag::NV); + Z = UI32_NaN; + softfloat_propagateNaNF32UI(Z, c); + return Z; + } + + if (expC == 0xFF) { + if (sigC != 0) { + Z = 0; + softfloat_propagateNaNF32UI(Z, c); + } + Z = c; + return Z; + } + + if (expA == 0) { + if (sigA == 0) { + Z = c; + if (((expC | sigC) == 0) && (signProd != signC)) { + Z = packToF32UI((mode == RoundingMode::RDN), 0, 0); + } + return Z; + } + (expA, sigA) = softfloat_normSubnormalF32Sig(sigA); + } + + if (expB == 0) { + if (sigB == 0) { + Z = c; + if (((expC | sigC) == 0) && (signProd != signC)) { + Z = packToF32UI((mode == RoundingMode::RDN), 0, 0); + } + return Z; + } + (expB, sigB) = softfloat_normSubnormalF32Sig(sigB); + } + + expProd = expA + expB - 0x7E; + sigA = (sigA | 0x00800000)<<7; + sigB = (sigB | 0x00800000)<<7; + sigProd = sigA `* sigB; + if ( sigProd < 0x2000000000000000 ) { + expProd = expProd `- 1; + sigProd = sigProd << 1; + } + signZ = signProd; + if (expC == 0) { + if (sigC == 0) { + expZ = expProd - 1; + sigZ = softfloat_ShiftRightJam64(sigProd, 31); + return softfloat_roundPackToF32(signZ, expZ, sigZ); + } + (expC, sigC) = softfloat_normSubnormalF32Sig( sigC ); + } + sigC = (sigC | 0x00800000)<<6; + expDiff = expProd - expC; + if ( signProd == signC ) { + if ( expDiff <= 0 ) { + expZ = expC; + sigZ = sigC + softfloat_shiftRightJam64( sigProd, 32 - expDiff ); + } else { + expZ = expProd; + sig64Z = + sigProd + + softfloat_shiftRightJam64( + sigC `<< 32, expDiff ); + sigZ = softfloat_shortShiftRightJam64( sig64Z, 32 ); + } + if ( sigZ < 0x40000000 ) { + expZ = expZ - 1; + sigZ = sigZ - 1; + } + } else { + sig64C = sigC `<< 32; + if ( expDiff < 0 ) { + signZ = signC; + expZ = expC; + sig64Z = sig64C - softfloat_shiftRightJam64( sigProd, -expDiff ); + } else if ( expDiff == 0 ) { + expZ = expProd; + sig64Z = sigProd - sig64C; + if ( sig64Z == 0 ) { + return packToF32UI( + ((mode == RoundingMode::RDN)), 0, 0 ); + } + if ( (sig64Z & 0x8000000000000000) == 1 ) { + signZ = ! signZ; + sig64Z = -sig64Z; + } + } else { + expZ = expProd; + sig64Z = sigProd - softfloat_shiftRightJam64( sig64C, expDiff ); + } + shiftDist = softfloat_countLeadingZeros64( sig64Z ) - 1; + expZ = expZ - shiftDist; + shiftDist = shiftDist - 32; + if ( shiftDist < 0 ) { + sigZ = softfloat_ShiftRightJam64( sig64Z, -shiftDist ); + } else { + sigZ = sig64Z< Date: Sat, 4 Oct 2025 17:46:43 +0000 Subject: [PATCH 09/14] feat(IDL): single precision floating point multiply subtract --- spec/std/isa/inst/F/fmsub.s.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/spec/std/isa/inst/F/fmsub.s.yaml b/spec/std/isa/inst/F/fmsub.s.yaml index fe088c7324..f7de13c0de 100644 --- a/spec/std/isa/inst/F/fmsub.s.yaml +++ b/spec/std/isa/inst/F/fmsub.s.yaml @@ -31,6 +31,11 @@ access: vu: always data_independent_timing: true operation(): | + check_f_ok($encoding); + RoundingMode mode = rm_to_mode(rm, $encoding); + F32MulAddOp op = Softfloat_mulAdd_subC; + f[fd] = f32_muladd(f[fs1], f[fs2], op, mode); + mark_f_state_dirty(); # SPDX-SnippetBegin # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model From b84279fe1adee1f959100a6e48427717ad538918 Mon Sep 17 00:00:00 2001 From: Shashank V M Date: Sat, 4 Oct 2025 17:56:29 +0000 Subject: [PATCH 10/14] fix: enum assignment --- spec/std/isa/inst/F/fmadd.s.yaml | 2 +- spec/std/isa/inst/F/fmsub.s.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/spec/std/isa/inst/F/fmadd.s.yaml b/spec/std/isa/inst/F/fmadd.s.yaml index 12a49dfff9..265e7e9ffa 100644 --- a/spec/std/isa/inst/F/fmadd.s.yaml +++ b/spec/std/isa/inst/F/fmadd.s.yaml @@ -33,7 +33,7 @@ data_independent_timing: true operation(): | check_f_ok($encoding); RoundingMode mode = rm_to_mode(rm, $encoding); - F32MulAddOp op = Softfloat_mulAdd_addC; + F32MulAddOp op = F32MulAddOp::Softfloat_mulAdd_addC; f[fd] = f32_muladd(f[fs1], f[fs2], op, mode); mark_f_state_dirty(); diff --git a/spec/std/isa/inst/F/fmsub.s.yaml b/spec/std/isa/inst/F/fmsub.s.yaml index f7de13c0de..8b306d3cee 100644 --- a/spec/std/isa/inst/F/fmsub.s.yaml +++ b/spec/std/isa/inst/F/fmsub.s.yaml @@ -33,7 +33,7 @@ data_independent_timing: true operation(): | check_f_ok($encoding); RoundingMode mode = rm_to_mode(rm, $encoding); - F32MulAddOp op = Softfloat_mulAdd_subC; + F32MulAddOp op = F32MulAddOp::Softfloat_mulAdd_subC; f[fd] = f32_muladd(f[fs1], f[fs2], op, mode); mark_f_state_dirty(); From 83418f8b93ae85ddfbe51251c1aa375d80289053 Mon Sep 17 00:00:00 2001 From: Shashank V M Date: Sat, 4 Oct 2025 18:03:24 +0000 Subject: [PATCH 11/14] fix: function arguments in function call --- spec/std/isa/inst/F/fmadd.s.yaml | 2 +- spec/std/isa/inst/F/fmsub.s.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/spec/std/isa/inst/F/fmadd.s.yaml b/spec/std/isa/inst/F/fmadd.s.yaml index 265e7e9ffa..d4f21cfcf0 100644 --- a/spec/std/isa/inst/F/fmadd.s.yaml +++ b/spec/std/isa/inst/F/fmadd.s.yaml @@ -34,7 +34,7 @@ operation(): | check_f_ok($encoding); RoundingMode mode = rm_to_mode(rm, $encoding); F32MulAddOp op = F32MulAddOp::Softfloat_mulAdd_addC; - f[fd] = f32_muladd(f[fs1], f[fs2], op, mode); + f[fd] = f32_muladd(f[fs1], f[fs2], f[fs3], op, mode); mark_f_state_dirty(); # SPDX-SnippetBegin diff --git a/spec/std/isa/inst/F/fmsub.s.yaml b/spec/std/isa/inst/F/fmsub.s.yaml index 8b306d3cee..b132010115 100644 --- a/spec/std/isa/inst/F/fmsub.s.yaml +++ b/spec/std/isa/inst/F/fmsub.s.yaml @@ -34,7 +34,7 @@ operation(): | check_f_ok($encoding); RoundingMode mode = rm_to_mode(rm, $encoding); F32MulAddOp op = F32MulAddOp::Softfloat_mulAdd_subC; - f[fd] = f32_muladd(f[fs1], f[fs2], op, mode); + f[fd] = f32_muladd(f[fs1], f[fs2], f[fs3], op, mode); mark_f_state_dirty(); # SPDX-SnippetBegin From faa514d185ffd393f4c56c2b27a82e9d41ecf77c Mon Sep 17 00:00:00 2001 From: Shashank V M Date: Sat, 4 Oct 2025 18:14:27 +0000 Subject: [PATCH 12/14] fix: floating point IDL typos --- spec/std/isa/isa/fp.idl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/spec/std/isa/isa/fp.idl b/spec/std/isa/isa/fp.idl index ca1f37d1bc..a2229f4333 100644 --- a/spec/std/isa/isa/fp.idl +++ b/spec/std/isa/isa/fp.idl @@ -1561,7 +1561,7 @@ function f32_muladd { if (expC == 0) { if (sigC == 0) { expZ = expProd - 1; - sigZ = softfloat_ShiftRightJam64(sigProd, 31); + sigZ = softfloat_shiftRightJam64(sigProd, 31); return softfloat_roundPackToF32(signZ, expZ, sigZ); } (expC, sigC) = softfloat_normSubnormalF32Sig( sigC ); @@ -1578,7 +1578,7 @@ function f32_muladd { sigProd + softfloat_shiftRightJam64( sigC `<< 32, expDiff ); - sigZ = softfloat_shortShiftRightJam64( sig64Z, 32 ); + sigZ = softfloat_shiftRightJam64( sig64Z, 32 ); } if ( sigZ < 0x40000000 ) { expZ = expZ - 1; @@ -1605,11 +1605,11 @@ function f32_muladd { expZ = expProd; sig64Z = sigProd - softfloat_shiftRightJam64( sig64C, expDiff ); } - shiftDist = softfloat_countLeadingZeros64( sig64Z ) - 1; + shiftDist = count_leading_zeros<64>( sig64Z ) - 1; expZ = expZ - shiftDist; shiftDist = shiftDist - 32; if ( shiftDist < 0 ) { - sigZ = softfloat_ShiftRightJam64( sig64Z, -shiftDist ); + sigZ = softfloat_shiftRightJam64( sig64Z, -shiftDist ); } else { sigZ = sig64Z< Date: Sat, 4 Oct 2025 18:15:14 +0000 Subject: [PATCH 13/14] feat(IDL): single precision floating point negative multiply add --- spec/std/isa/inst/F/fnmadd.s.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/spec/std/isa/inst/F/fnmadd.s.yaml b/spec/std/isa/inst/F/fnmadd.s.yaml index 8e9cb77421..efe128bad4 100644 --- a/spec/std/isa/inst/F/fnmadd.s.yaml +++ b/spec/std/isa/inst/F/fnmadd.s.yaml @@ -32,6 +32,11 @@ access: vu: always data_independent_timing: true operation(): | + check_f_ok($encoding); + RoundingMode mode = rm_to_mode(rm, $encoding); + F32MulAddOp op = F32MulAddOp::Softfloat_mulAdd_subC; + f[fd] = f32_muladd(-f[fs1], f[fs2], -f[fs3], op, mode); + mark_f_state_dirty(); # SPDX-SnippetBegin # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model From 194f21c65b817cfd1a94cc6ff6855b4c42a773eb Mon Sep 17 00:00:00 2001 From: Shashank V M Date: Sat, 4 Oct 2025 18:29:36 +0000 Subject: [PATCH 14/14] feat(IDL): single precision floating point negative multiply subtraction --- spec/std/isa/inst/F/fnmsub.s.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/spec/std/isa/inst/F/fnmsub.s.yaml b/spec/std/isa/inst/F/fnmsub.s.yaml index 461f871446..6c6489a21b 100644 --- a/spec/std/isa/inst/F/fnmsub.s.yaml +++ b/spec/std/isa/inst/F/fnmsub.s.yaml @@ -32,6 +32,11 @@ access: vu: always data_independent_timing: true operation(): | + check_f_ok($encoding); + RoundingMode mode = rm_to_mode(rm, $encoding); + F32MulAddOp op = F32MulAddOp::Softfloat_mulAdd_addC; + f[fd] = f32_muladd(-f[fs1], f[fs2], f[fs3], op, mode); + mark_f_state_dirty(); # SPDX-SnippetBegin # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model