From 908dc9d0c4041e766ecc71b6564aee69f0747da7 Mon Sep 17 00:00:00 2001 From: Sergii Piatakov Date: Wed, 25 Jan 2023 09:31:19 +0000 Subject: [PATCH 1/2] mmngr_drv: mmngr: check result when setting DMA mode The `dma_set_mask_and_coherent` does not always perform successfully and it also might fail. Ignoring this error and attempting to use DMA in case of failure will lead to undefined behavior. See for details: Documentation/core-api/dma-api-howto.rst Also, this patch puts the second call of the function inside the conditional block based on `IPMMU_MMU_SUPPORT` value. This is necessary to avoid a double function call when the `IPMMU_MMU_SUPPORT` is true. Signed-off-by: Sergii Piatakov --- .../mmngr/mmngr-module/files/mmngr/drv/mmngr_drv.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/mmngr_drv/mmngr/mmngr-module/files/mmngr/drv/mmngr_drv.c b/mmngr_drv/mmngr/mmngr-module/files/mmngr/drv/mmngr_drv.c index 2a65f73..2925815 100644 --- a/mmngr_drv/mmngr/mmngr-module/files/mmngr/drv/mmngr_drv.c +++ b/mmngr_drv/mmngr/mmngr-module/files/mmngr/drv/mmngr_drv.c @@ -1749,17 +1749,25 @@ static int mm_probe(struct platform_device *pdev) if (p == NULL) return -1; - dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); - #ifdef IPMMU_MMU_SUPPORT if (!rcar_gen3_ipmmu) { pr_err("%s MMD ERROR\n", __func__); return -1; } - dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); + if (ret) { + pr_err("MMD mm_init ERROR unable to set DMA mode: %d.\n", ret); + return -1; + } ipmmu_mmu_startup(); ipmmu_mmu_initialize(); +#else + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); + if (ret) { + pr_err("MMD mm_init ERROR unable to set DMA mode: %d.\n", ret); + return -1; + } #endif misc_register(&misc); From f6e775c96159f979153966b144100820c20a23cb Mon Sep 17 00:00:00 2001 From: Oleksii Khramkov Date: Sun, 6 Aug 2023 21:21:18 +0300 Subject: [PATCH 2/2] mmngr_drv: mmngr: set 32-bit DMA mask for M3N and E3 With the current implementation, the MMNGR sets a 40-bit DMA bitmask (when IPMMU is enabled) regardless of the actual SoC. At the same time, M3N and E3 don't have 40-bit address space. IPMMU MMU supports physical address space in the legacy area. It is proposed to make changes that allow using the correct DMA bitmask for all devices. Signed-off-by: Oleksii Khramkov Signed-off-by: Sergii Piatakov --- mmngr_drv/mmngr/mmngr-module/files/mmngr/drv/mmngr_drv.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/mmngr_drv/mmngr/mmngr-module/files/mmngr/drv/mmngr_drv.c b/mmngr_drv/mmngr/mmngr-module/files/mmngr/drv/mmngr_drv.c index 2925815..6f85c3f 100644 --- a/mmngr_drv/mmngr/mmngr-module/files/mmngr/drv/mmngr_drv.c +++ b/mmngr_drv/mmngr/mmngr-module/files/mmngr/drv/mmngr_drv.c @@ -1754,8 +1754,10 @@ static int mm_probe(struct platform_device *pdev) pr_err("%s MMD ERROR\n", __func__); return -1; } - - ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); + if (soc_device_match(r8a77965) || soc_device_match(r8a77990)) + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); + else + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); if (ret) { pr_err("MMD mm_init ERROR unable to set DMA mode: %d.\n", ret); return -1;