diff --git a/src/main/scala/graphics/DiffInfo.scala b/src/main/scala/graphics/DiffInfo.scala deleted file mode 100644 index f1ac42d..0000000 --- a/src/main/scala/graphics/DiffInfo.scala +++ /dev/null @@ -1,168 +0,0 @@ -import chisel3._ -object DiffInfo { - def build(p0: (Int, Int), p1: (Int, Int), p2: (Int, Int)) = { - val diffInfo = Wire(new DiffInfo) - - val dx0 = p1._1 - p0._1 - val dx1 = p2._1 - p1._1 - val dx2 = p0._1 - p2._1 - - val dy0 = p0._2 - p1._2 - val dy1 = p1._2 - p2._2 - val dy2 = p2._2 - p0._2 - - diffInfo.dj0 := (-dy0).S // The negate operator of SInt is broken, WTF??? - diffInfo.dj1 := (-dy1).S - diffInfo.dj2 := (-dy2).S - - diffInfo.di0 := (-dx0 + dy0 * (Tile.size - 1)).S - diffInfo.di1 := (-dx1 + dy1 * (Tile.size - 1)).S - diffInfo.di2 := (-dx2 + dy2 * (Tile.size - 1)).S - - diffInfo.dc0 := ((-dy0 + dx0) * Tile.size).S - diffInfo.dc1 := ((-dy1 + dx1) * Tile.size).S - diffInfo.dc2 := ((-dy2 + dx2) * Tile.size).S - - diffInfo.dr0 := (dy0 * (Tile.nrCols - 1) * Tile.size).S - diffInfo.dr1 := (dy1 * (Tile.nrCols - 1) * Tile.size).S - diffInfo.dr2 := (dy2 * (Tile.nrCols - 1) * Tile.size).S - - val e0 = dx0 * p0._2 + dy0 * p0._1 - val e1 = dx1 * p1._2 + dy1 * p1._1 - val e2 = dx2 * p2._2 + dy2 * p2._1 - diffInfo.e0 := e0.S - diffInfo.e1 := e1.S - diffInfo.e2 := e2.S - - val a = dy0 * dx2 - dx0 * dy2 - diffInfo.a := math.abs(a).S - - val r = if (a == 0) 0 else e1 * 255 / a - val g = if (a == 0) 0 else e2 * 255 / a - val b = if (a == 0) 0 else e0 * 255 / a - diffInfo.r := r.S - diffInfo.g := g.S - diffInfo.b := b.S - - val er = if (a == 0) 0 else if (a > 0) e1 * 255 % a else -e1 * 255 % a - val eg = if (a == 0) 0 else if (a > 0) e2 * 255 % a else -e2 * 255 % a - val eb = if (a == 0) 0 else if (a > 0) e0 * 255 % a else -e0 * 255 % a - diffInfo.er := er.S - diffInfo.eg := eg.S - diffInfo.eb := eb.S - - val dividendrj = -dy1 * 255 - val dividendgj = -dy2 * 255 - val dividendbj = -dy0 * 255 - - diffInfo.dquorj := (if (a == 0) 0 else dividendrj / a).S - diffInfo.dquogj := (if (a == 0) 0 else dividendgj / a).S - diffInfo.dquobj := (if (a == 0) 0 else dividendbj / a).S - - diffInfo.dremrj := (if (a == 0) 0 else if (a > 0) dividendrj % a else -dividendrj % a).S - diffInfo.dremgj := (if (a == 0) 0 else if (a > 0) dividendgj % a else -dividendgj % a).S - diffInfo.drembj := (if (a == 0) 0 else if (a > 0) dividendbj % a else -dividendbj % a).S - - val dividendri = (dy1 * (Tile.size - 1) - dx1) * 255 - val dividendgi = (dy2 * (Tile.size - 1) - dx2) * 255 - val dividendbi = (dy0 * (Tile.size - 1) - dx0) * 255 - - diffInfo.dquori := (if (a == 0) 0 else dividendri / a).S - diffInfo.dquogi := (if (a == 0) 0 else dividendgi / a).S - diffInfo.dquobi := (if (a == 0) 0 else dividendbi / a).S - - diffInfo.dremri := (if (a == 0) 0 else if (a > 0) dividendri % a else -dividendri % a).S - diffInfo.dremgi := (if (a == 0) 0 else if (a > 0) dividendgi % a else -dividendgi % a).S - diffInfo.drembi := (if (a == 0) 0 else if (a > 0) dividendbi % a else -dividendbi % a).S - - val dividendrc = (-dy1 + dx1) * Tile.size * 255 - val dividendgc = (-dy2 + dx2) * Tile.size * 255 - val dividendbc = (-dy0 + dx0) * Tile.size * 255 - - diffInfo.dquorc := (if (a == 0) 0 else dividendrc / a).S - diffInfo.dquogc := (if (a == 0) 0 else dividendgc / a).S - diffInfo.dquobc := (if (a == 0) 0 else dividendbc / a).S - - diffInfo.dremrc := (if (a == 0) 0 else if (a > 0) dividendrc % a else -dividendrc % a).S - diffInfo.dremgc := (if (a == 0) 0 else if (a > 0) dividendgc % a else -dividendgc % a).S - diffInfo.drembc := (if (a == 0) 0 else if (a > 0) dividendbc % a else -dividendbc % a).S - - val dividendrr = dy1 * (Tile.nrCols - 1) * Tile.size * 255 - val dividendgr = dy2 * (Tile.nrCols - 1) * Tile.size * 255 - val dividendbr = dy0 * (Tile.nrCols - 1) * Tile.size * 255 - - diffInfo.dquorr := (if (a == 0) 0 else dividendrr / a).S - diffInfo.dquogr := (if (a == 0) 0 else dividendgr / a).S - diffInfo.dquobr := (if (a == 0) 0 else dividendbr / a).S - - diffInfo.dremrr := (if (a == 0) 0 else if (a > 0) dividendrr % a else -dividendrr % a).S - diffInfo.dremgr := (if (a == 0) 0 else if (a > 0) dividendgr % a else -dividendgr % a).S - diffInfo.drembr := (if (a == 0) 0 else if (a > 0) dividendbr % a else -dividendbr % a).S - - diffInfo - } -} - -class DiffInfo extends Bundle { - val e0 = SInt(24.W) - val e1 = SInt(24.W) - val e2 = SInt(24.W) - - val dj0 = SInt() - val dj1 = SInt() - val dj2 = SInt() - - val di0 = SInt() - val di1 = SInt() - val di2 = SInt() - - val dc0 = SInt() - val dc1 = SInt() - val dc2 = SInt() - - val dr0 = SInt() - val dr1 = SInt() - val dr2 = SInt() - - val a = SInt() - - val r = SInt(24.W) - val g = SInt(24.W) - val b = SInt(24.W) - - val er = SInt(24.W) - val eg = SInt(24.W) - val eb = SInt(24.W) - - val dquorj = SInt() - val dquogj = SInt() - val dquobj = SInt() - - val dremrj = SInt() - val dremgj = SInt() - val drembj = SInt() - - val dquori = SInt() - val dquogi = SInt() - val dquobi = SInt() - - val dremri = SInt() - val dremgi = SInt() - val drembi = SInt() - - val dquorc = SInt() - val dquogc = SInt() - val dquobc = SInt() - - val dremrc = SInt() - val dremgc = SInt() - val drembc = SInt() - - val dquorr = SInt() - val dquogr = SInt() - val dquobr = SInt() - - val dremrr = SInt() - val dremgr = SInt() - val drembr = SInt() -} diff --git a/src/main/scala/graphics/Graphics.scala b/src/main/scala/graphics/Graphics.scala index ea8287f..2fbb288 100644 --- a/src/main/scala/graphics/Graphics.scala +++ b/src/main/scala/graphics/Graphics.scala @@ -5,89 +5,96 @@ import chisel3._ import chisel3.util._ class Graphics extends Module { - def incrDiv(dquo: SInt, drem: SInt, divisor: SInt, quo: SInt, rem: SInt) = { - val nquo = quo + dquo; - val nrem = rem + drem; - val rquo = WireDefault(nquo) - val rrem = WireDefault(nrem) - when (drem > 0.S && rem >= divisor - drem) { - rquo := nquo + 1.S - rrem := nrem - divisor - } - when (drem < 0.S && rem <= -divisor - drem) { - rquo := nquo - 1.S - rrem := nrem + divisor - } - (rquo, rrem) - } - val io = IO(new Bundle { val fbId = Input(UInt(Fb.idWidth.W)) val vram = new WrAxi(Vram.addrWidth, Vram.dataWidth) val done = Output(Bool()) }) - val diffInfos = Wire(Vec(360, new DiffInfo)) + val cnt = RegInit(0.U(unsignedBitLength(1388888).W)) + val angle = RegInit(0.U(log2Up(360).W)) + cnt := cnt + 1.U + when (cnt === 1388888.U) { + cnt := 0.U + angle := angle + 1.U + when (angle === 359.U) { + angle := 0.U + } + } + + val nrDraws = 2 + val drawId = RegInit(0.U(log2Up(nrDraws).W)) + + val color = Wire(Vec(nrDraws, UInt(8.W))) + + val x0v = Wire(Vec(nrDraws, Vec(360, UInt()))) + val y0v = Wire(Vec(nrDraws, Vec(360, UInt()))) + val x1v = Wire(Vec(nrDraws, Vec(360, UInt()))) + val y1v = Wire(Vec(nrDraws, Vec(360, UInt()))) + val x2v = Wire(Vec(nrDraws, Vec(360, UInt()))) + val y2v = Wire(Vec(nrDraws, Vec(360, UInt()))) + + val dx0v = Wire(Vec(nrDraws, Vec(360, SInt()))) + val dy0v = Wire(Vec(nrDraws, Vec(360, SInt()))) + val dx1v = Wire(Vec(nrDraws, Vec(360, SInt()))) + val dy1v = Wire(Vec(nrDraws, Vec(360, SInt()))) + val dx2v = Wire(Vec(nrDraws, Vec(360, SInt()))) + val dy2v = Wire(Vec(nrDraws, Vec(360, SInt()))) for (i <- 0 until 360) { - val angle = math.toRadians(i) + color(0) := 0.U + + x0v(0)(i) := 0.U + y0v(0)(i) := 0.U + x1v(0)(i) := 0.U + y1v(0)(i) := 0.U + x2v(0)(i) := 0.U + y2v(0)(i) := 0.U + + dx0v(0)(i) := 0.S + dx1v(0)(i) := 0.S + dx2v(0)(i) := 0.S + dy0v(0)(i) := 0.S + dy1v(0)(i) := 0.S + dy2v(0)(i) := 0.S + val angle = math.toRadians(i) val x0 = 512 val y0 = 192 - val z1 = 1 / (2 - math.sin(angle)) val x1 = 512 - (222 * z1 * math.cos(angle)).toInt val y1 = 384 + (192 * z1).toInt - val z2 = 1 / (2 + math.sin(angle)) val x2 = 512 + (222 * z2 * math.cos(angle)).toInt val y2 = 384 + (192 * z2).toInt - diffInfos(i) := DiffInfo.build((x0, y0), (x1, y1), (x2, y2)) + color(1) := 255.U + + x0v(1)(i) := x0.U + y0v(1)(i) := y0.U + x1v(1)(i) := x1.U + y1v(1)(i) := y1.U + x2v(1)(i) := x2.U + y2v(1)(i) := y2.U + + dx0v(1)(i) := (x1 - x0).S + dx1v(1)(i) := (x2 - x1).S + dx2v(1)(i) := (x0 - x2).S + dy0v(1)(i) := (y0 - y1).S + dy1v(1)(i) := (y1 - y2).S + dy2v(1)(i) := (y2 - y0).S } - val cntReg = RegInit(0.U(unsignedBitLength(1388888).W)) - val angle = RegInit(0.U(log2Up(360).W)) - cntReg := cntReg + 1.U - when (cntReg === 1388888.U) { - cntReg := 0.U - angle := angle + 1.U - when (angle === 359.U) { - angle := 0.U - } - } - - val diffInfo = RegInit(diffInfos(0)) - - val e0 = RegInit(diffInfos(0).e0) - val e1 = RegInit(diffInfos(0).e1) - val e2 = RegInit(diffInfos(0).e2) - - val r = RegInit(diffInfos(0).r) - val g = RegInit(diffInfos(0).g) - val b = RegInit(diffInfos(0).b) - - val er = RegInit(diffInfos(0).er) - val eg = RegInit(diffInfos(0).eg) - val eb = RegInit(diffInfos(0).eb) - val col = RegInit(0.U(log2Up(Tile.nrCols).W)) val row = RegInit(0.U(unsignedBitLength(Tile.nrRows).W)) + val x = RegInit(0.U(log2Up(Fb.width).W)) + val y = RegInit(0.U(log2Up(Fb.height).W)) + val currAngle = RegInit(0.U(log2Up(360).W)) when (RegNext(io.fbId) =/= io.fbId) { - diffInfo := diffInfos(angle) - - e0 := diffInfos(angle).e0 - e1 := diffInfos(angle).e1 - e2 := diffInfos(angle).e2 - - r := diffInfos(angle).r - g := diffInfos(angle).g - b := diffInfos(angle).b - - er := diffInfos(angle).er - eg := diffInfos(angle).eg - eb := diffInfos(angle).eb - + drawId := 0.U + currAngle := angle row := 0.U + x := 0.U + y := 0.U } val tileWriter = Module(new TileWriter) @@ -95,96 +102,45 @@ class Graphics extends Module { tileWriter.io.inReq.valid := valid when (valid && tileWriter.io.inReq.ready) { valid := false.B - - e0 := e0 + diffInfo.dc0 - e1 := e1 + diffInfo.dc1 - e2 := e2 + diffInfo.dc2 - - val (rquo, rrem) = incrDiv(diffInfo.dquorc, diffInfo.dremrc, diffInfo.a, r, er) - r := rquo - er := rrem - - val (gquo, grem) = incrDiv(diffInfo.dquogc, diffInfo.dremgc, diffInfo.a, g, eg) - g := gquo - eg := grem - - val (bquo, brem) = incrDiv(diffInfo.dquobc, diffInfo.drembc, diffInfo.a, b, eb) - b := bquo - eb := brem - col := col + 1.U - + x := x + Tile.size.U when (col === (Tile.nrCols - 1).U) { - e0 := e0 + diffInfo.dr0 - e1 := e1 + diffInfo.dr1 - e2 := e2 + diffInfo.dr2 - - val (rquo, rrem) = incrDiv(diffInfo.dquorr, diffInfo.dremrr, diffInfo.a, r, er) - r := rquo - er := rrem - - val (gquo, grem) = incrDiv(diffInfo.dquogr, diffInfo.dremgr, diffInfo.a, g, eg) - g := gquo - eg := grem - - val (bquo, brem) = incrDiv(diffInfo.dquobr, diffInfo.drembr, diffInfo.a, b, eb) - b := bquo - eb := brem - col := 0.U row := row + 1.U + x := 0.U + y := y + Tile.size.U } } val tileBuffer = Reg(Vec(Tile.size, Vec(Tile.size, FbRGB()))) val i = RegInit(0.U(log2Up(Tile.size).W)) val j = RegInit(0.U(log2Up(Tile.size).W)) - val visible = e0 > 0.S && (e1 > 0.S && e2 > 0.S) || e0 < 0.S && (e1 < 0.S && e2 < 0.S) when (row =/= Tile.nrRows.U && !valid) { - val rgb = FbRGB(r.asUInt, g.asUInt, b.asUInt) - tileBuffer(i)(j) := Mux(visible, rgb, FbRGB(0)) + val e0 = dx0v(drawId)(currAngle) * (y0v(drawId)(currAngle).zext - y.zext) - dy0v(drawId)(currAngle) * (x.zext - x0v(drawId)(currAngle).zext) + val e1 = dx1v(drawId)(currAngle) * (y1v(drawId)(currAngle).zext - y.zext) - dy1v(drawId)(currAngle) * (x.zext - x1v(drawId)(currAngle).zext) + val e2 = dx2v(drawId)(currAngle) * (y2v(drawId)(currAngle).zext - y.zext) - dy2v(drawId)(currAngle) * (x.zext - x2v(drawId)(currAngle).zext) + val visible = e0 > 0.S && e1 > 0.S && e2 > 0.S || + e0 < 0.S && e1 < 0.S && e2 < 0.S || + e0 === 0.S && e1 === 0.S && e2 === 0.S + when (visible) { + tileBuffer(i)(j) := FbRGB(color(drawId)) + } j := j + 1.U - - e0 := e0 + diffInfo.dj0 - e1 := e1 + diffInfo.dj1 - e2 := e2 + diffInfo.dj2 - - val (rquo, rrem) = incrDiv(diffInfo.dquorj, diffInfo.dremrj, diffInfo.a, r, er) - r := rquo - er := rrem - - val (gquo, grem) = incrDiv(diffInfo.dquogj, diffInfo.dremgj, diffInfo.a, g, eg) - g := gquo - eg := grem - - val (bquo, brem) = incrDiv(diffInfo.dquobj, diffInfo.drembj, diffInfo.a, b, eb) - b := bquo - eb := brem - + x := x + 1.U when (j === (Tile.size - 1).U) { j := 0.U i := i + 1.U - - e0 := e0 + diffInfo.di0 - e1 := e1 + diffInfo.di1 - e2 := e2 + diffInfo.di2 - - val (rquo, rrem) = incrDiv(diffInfo.dquori, diffInfo.dremri, diffInfo.a, r, er) - r := rquo - er := rrem - - val (gquo, grem) = incrDiv(diffInfo.dquogi, diffInfo.dremgi, diffInfo.a, g, eg) - g := gquo - eg := grem - - val (bquo, brem) = incrDiv(diffInfo.dquobi, diffInfo.drembi, diffInfo.a, b, eb) - b := bquo - eb := brem - + x := x - (Tile.size - 1).U + y := y + 1.U when (i === (Tile.size - 1).U) { i := 0.U - valid := true.B + y := y - (Tile.size - 1).U + drawId := drawId + 1.U + when (drawId === (nrDraws - 1).U) { + drawId := 0.U + valid := true.B + } } } } diff --git a/src/main/scala/utils/Color.scala b/src/main/scala/utils/Color.scala index 334b7d0..b89ec3b 100644 --- a/src/main/scala/utils/Color.scala +++ b/src/main/scala/utils/Color.scala @@ -42,6 +42,14 @@ class RGBFactory(val rWidth: Int, val gWidth: Int, val bWidth: Int) { res } + def apply(x: UInt) = { + val res = Wire(new RGB(rWidth, gWidth, bWidth)) + res.r := x + res.g := x + res.b := x + res + } + def apply(r: UInt, g: UInt, b: UInt) = { val res = Wire(new RGB(rWidth, gWidth, bWidth)) res.r := r diff --git a/vivado/bd/vram/ip/vram_auto_cc_2/vram_auto_cc_2.xci b/vivado/bd/vram/ip/vram_auto_cc_2/vram_auto_cc_2.xci index 1113e49..34a7b61 100644 --- a/vivado/bd/vram/ip/vram_auto_cc_2/vram_auto_cc_2.xci +++ b/vivado/bd/vram/ip/vram_auto_cc_2/vram_auto_cc_2.xci @@ -119,7 +119,7 @@ "parameters": { "DATA_WIDTH": [ { "value": "128", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ID_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "28", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "AWUSER_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -235,7 +235,7 @@ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", "mode": "slave", "parameters": { - "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "vram_graphics_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/vivado/bd/vram/vram.bd b/vivado/bd/vram/vram.bd index 100e63d..0982246 100644 --- a/vivado/bd/vram/vram.bd +++ b/vivado/bd/vram/vram.bd @@ -1,7 +1,7 @@ { "design": { "design_info": { - "boundary_crc": "0x3A58F1BF9F623D5", + "boundary_crc": "0x3A58F1BC32486E6", "device": "xc7a100tcsg324-1", "name": "vram", "rev_ctrl_bd_flag": "RevCtrlBdOff", @@ -53,7 +53,7 @@ "value": "128" }, "FREQ_HZ": { - "value": "100000000" + "value": "50000000" }, "HAS_BRESP": { "value": "1" @@ -593,7 +593,7 @@ "value_src": "default" }, "FREQ_HZ": { - "value": "100000000" + "value": "50000000" }, "FREQ_TOLERANCE_HZ": { "value": "0", diff --git a/vivado/ip/clk_wiz/clk_wiz.xci b/vivado/ip/clk_wiz/clk_wiz.xci index b222dcc..0845c59 100644 --- a/vivado/ip/clk_wiz/clk_wiz.xci +++ b/vivado/ip/clk_wiz/clk_wiz.xci @@ -84,7 +84,7 @@ "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ], "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ], "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ], - "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -167,7 +167,7 @@ "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "9.750", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "19.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -245,7 +245,7 @@ "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ], "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT1_JITTER": [ { "value": "130.067", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_JITTER": [ { "value": "150.541", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_PHASE_ERROR": [ { "value": "99.281", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_JITTER": [ { "value": "142.278", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_PHASE_ERROR": [ { "value": "99.281", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -338,14 +338,14 @@ "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW1": [ { "value": "clk_graphics__100.00000______0.000______50.0______130.067_____99.281", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW1": [ { "value": "clk_graphics__50.00000______0.000______50.0______150.541_____99.281", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW2": [ { "value": "clk_display__65.00000______0.000______50.0______142.278_____99.281", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "100", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "50", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], @@ -366,7 +366,7 @@ "C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT1_OUT_FREQ": [ { "value": "100.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT1_OUT_FREQ": [ { "value": "50.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT2_OUT_FREQ": [ { "value": "65.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], @@ -408,7 +408,7 @@ "C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], - "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "9.750", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "19.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -540,12 +540,12 @@ "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE2_AUTO": [ { "value": "1.5384615384615385", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE3_AUTO": [ { "value": "0.10256410256410256", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE4_AUTO": [ { "value": "0.10256410256410256", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE5_AUTO": [ { "value": "0.10256410256410256", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE6_AUTO": [ { "value": "0.10256410256410256", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE7_AUTO": [ { "value": "0.10256410256410256", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE2_AUTO": [ { "value": "0.7692307692307693", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE3_AUTO": [ { "value": "0.05128205128205128", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE4_AUTO": [ { "value": "0.05128205128205128", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE5_AUTO": [ { "value": "0.05128205128205128", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE6_AUTO": [ { "value": "0.05128205128205128", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE7_AUTO": [ { "value": "0.05128205128205128", "resolve_type": "generated", "usage": "all" } ], "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], @@ -566,7 +566,7 @@ "C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "100.00000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "50.00000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "65.00000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],