diff --git a/src/main/scala/core/Fb.scala b/src/main/scala/core/Fb.scala index 61aaf7b..da3211d 100644 --- a/src/main/scala/core/Fb.scala +++ b/src/main/scala/core/Fb.scala @@ -47,7 +47,7 @@ class vram extends BlackBox { class Vram extends Module { val io = IO(new Bundle { - val axiGraphics = Flipped(new WrAxi(Vram.addrWidth, Vram.dataWidth)) + val axiGraphics = new WrAxiExtUpper(Vram.addrWidth, Vram.dataWidth) val aclkGraphics = Input(Clock()) val arstnGraphics = Input(Reset()) @@ -62,7 +62,7 @@ class Vram extends Module { vram.io.clk := clock.asBool vram.io.reset := reset.asBool - vram.io.graphics_axi.connect(io.axiGraphics) + io.axiGraphics.connect(vram.io.graphics_axi) vram.io.graphics_aclk := io.aclkGraphics.asBool vram.io.graphics_aresetn := io.arstnGraphics.asBool diff --git a/src/main/scala/core/Trinity.scala b/src/main/scala/core/Trinity.scala index 00cca7e..7a817bc 100644 --- a/src/main/scala/core/Trinity.scala +++ b/src/main/scala/core/Trinity.scala @@ -36,10 +36,10 @@ class Trinity extends Module { vram.io.aclkGraphics := clkWiz.io.clkGraphics vram.io.arstnGraphics := graphicsSysRst.io.periArstn withClockAndReset(clkWiz.io.clkGraphics, graphicsSysRst.io.periRst) { - val graphics = Module(new Graphics) - vram.io.axiGraphics <> graphics.io.vram - graphics.io.fbId := RegNext(RegNext(fbSwapper.io.graphicsFbId)) - graphicsDone := RegNext(graphics.io.done) + val renderer = Module(new Renderer) + vram.io.axiGraphics <> renderer.io.vram + renderer.io.fbId := RegNext(RegNext(fbSwapper.io.graphicsFbId)) + graphicsDone := RegNext(renderer.io.done) } } diff --git a/src/main/scala/graphics/GammaCorrection.scala b/src/main/scala/graphics/GammaCorrection.scala deleted file mode 100644 index 3ce22f9..0000000 --- a/src/main/scala/graphics/GammaCorrection.scala +++ /dev/null @@ -1,20 +0,0 @@ -// Copyright (C) 2023 Alan Jian (alanjian85@outlook.com) -// SPDX-License-Identifier: MIT - -import chisel3._ -import scala.math._ - -object gammaCorrect { - val gamma = 2.2 - - def apply(x: UInt) = { - val res = WireDefault(0.U(x.getWidth.W)) - for (i <- 1 until 1 << x.getWidth) { - when (x === i.U) { - val max = (1 << x.getWidth) - 1 - res := (pow(i.toDouble / max, gamma) * max).toInt.U - } - } - res - } -} diff --git a/src/main/scala/graphics/Graphics.scala b/src/main/scala/graphics/Graphics.scala deleted file mode 100644 index 2a72067..0000000 --- a/src/main/scala/graphics/Graphics.scala +++ /dev/null @@ -1,203 +0,0 @@ -// Copyright (C) 2023 Alan Jian (alanjian85@outlook.com) -// SPDX-License-Identifier: MIT - -import chisel3._ -import chisel3.util._ - -class Graphics extends Module { - val io = IO(new Bundle { - val fbId = Input(UInt(Fb.idWidth.W)) - val vram = new WrAxi(Vram.addrWidth, Vram.dataWidth) - val done = Output(Bool()) - }) - - val cnt = RegInit(0.U(unsignedBitLength(1388888).W)) - val angle = RegInit(0.U(log2Up(360).W)) - cnt := cnt + 1.U - when (cnt === 1388888.U) { - cnt := 0.U - angle := angle + 1.U - when (angle === 359.U) { - angle := 0.U - } - } - - val nrDraws = 3 - val drawId = RegInit(0.U(log2Up(nrDraws).W)) - - val r = Wire(Vec(nrDraws, UInt(8.W))) - val g = Wire(Vec(nrDraws, UInt(8.W))) - val b = Wire(Vec(nrDraws, UInt(8.W))) - - val x0v = Wire(Vec(nrDraws, Vec(360, UInt()))) - val y0v = Wire(Vec(nrDraws, Vec(360, UInt()))) - val x1v = Wire(Vec(nrDraws, Vec(360, UInt()))) - val y1v = Wire(Vec(nrDraws, Vec(360, UInt()))) - val x2v = Wire(Vec(nrDraws, Vec(360, UInt()))) - val y2v = Wire(Vec(nrDraws, Vec(360, UInt()))) - - val dx0v = Wire(Vec(nrDraws, Vec(360, SInt()))) - val dy0v = Wire(Vec(nrDraws, Vec(360, SInt()))) - val dx1v = Wire(Vec(nrDraws, Vec(360, SInt()))) - val dy1v = Wire(Vec(nrDraws, Vec(360, SInt()))) - val dx2v = Wire(Vec(nrDraws, Vec(360, SInt()))) - val dy2v = Wire(Vec(nrDraws, Vec(360, SInt()))) - for (i <- 0 until 360) { - r(0) := 0.U - g(0) := 0.U - b(0) := 0.U - - x0v(0)(i) := 0.U - y0v(0)(i) := 0.U - x1v(0)(i) := 0.U - y1v(0)(i) := 0.U - x2v(0)(i) := 0.U - y2v(0)(i) := 0.U - - dx0v(0)(i) := 0.S - dx1v(0)(i) := 0.S - dx2v(0)(i) := 0.S - dy0v(0)(i) := 0.S - dy1v(0)(i) := 0.S - dy2v(0)(i) := 0.S - - val angle = math.toRadians(i) - val x0 = 512 - val y0 = 192 - val z1 = 1 / (2 - math.sin(angle)) - val x1 = 512 - (222 * z1 * math.cos(angle)).toInt - val y1 = 384 + (192 * z1).toInt - val z2 = 1 / (2 + math.sin(angle)) - val x2 = 512 + (222 * z2 * math.cos(angle)).toInt - val y2 = 384 + (192 * z2).toInt - - r(1) := 255.U - g(1) := 0.U - b(1) := 0.U - - x0v(1)(i) := (x0 - 200).U - y0v(1)(i) := y0.U - x1v(1)(i) := (x1 - 200).U - y1v(1)(i) := y1.U - x2v(1)(i) := (x2 - 200).U - y2v(1)(i) := y2.U - - dx0v(1)(i) := (x1 - x0).S - dx1v(1)(i) := (x2 - x1).S - dx2v(1)(i) := (x0 - x2).S - dy0v(1)(i) := (y0 - y1).S - dy1v(1)(i) := (y1 - y2).S - dy2v(1)(i) := (y2 - y0).S - - r(2) := 0.U - g(2) := 255.U - b(2) := 0.U - - x0v(2)(i) := (x0 + 200).U - y0v(2)(i) := y0.U - x1v(2)(i) := (x1 + 200).U - y1v(2)(i) := y1.U - x2v(2)(i) := (x2 + 200).U - y2v(2)(i) := y2.U - - dx0v(2)(i) := (x1 - x0).S - dx1v(2)(i) := (x2 - x1).S - dx2v(2)(i) := (x0 - x2).S - dy0v(2)(i) := (y0 - y1).S - dy1v(2)(i) := (y1 - y2).S - dy2v(2)(i) := (y2 - y0).S - } - - val x0 = RegInit(x0v(0)(0)) - val x1 = RegInit(x1v(0)(0)) - val x2 = RegInit(x2v(0)(0)) - val y0 = RegInit(y0v(0)(0)) - val y1 = RegInit(y1v(0)(0)) - val y2 = RegInit(y2v(0)(0)) - - val col = RegInit(0.U(log2Up(Tile.nrCols).W)) - val row = RegInit(0.U(unsignedBitLength(Tile.nrRows).W)) - val x = RegInit(0.U(log2Up(Fb.width).W)) - val y = RegInit(0.U(log2Up(Fb.height).W)) - val currAngle = RegInit(0.U(log2Up(360).W)) - when (RegNext(io.fbId) =/= io.fbId) { - drawId := 0.U - x0 := x0v(0)(angle) - x1 := x1v(0)(angle) - x2 := x2v(0)(angle) - y0 := y0v(0)(angle) - y1 := y1v(0)(angle) - y2 := y2v(0)(angle) - currAngle := angle - row := 0.U - x := 0.U - y := 0.U - } - - val tileWriter = Module(new TileWriter) - val valid = RegInit(false.B) - tileWriter.io.inReq.valid := valid - when (valid && tileWriter.io.inReq.ready) { - valid := false.B - col := col + 1.U - x := x + Tile.size.U - when (col === (Tile.nrCols - 1).U) { - col := 0.U - row := row + 1.U - x := 0.U - y := y + Tile.size.U - } - } - - val tileBuffer = Reg(Vec(Tile.size, Vec(Tile.size, FbRGB()))) - val i = RegInit(0.U(log2Up(Tile.size).W)) - val j = RegInit(0.U(log2Up(Tile.size).W)) - when (row =/= Tile.nrRows.U && !valid) { - val e0 = dx0v(drawId)(currAngle) * (y0.zext - y.zext) - dy0v(drawId)(currAngle) * (x.zext - x0.zext) - val e1 = dx1v(drawId)(currAngle) * (y1.zext - y.zext) - dy1v(drawId)(currAngle) * (x.zext - x1.zext) - val e2 = dx2v(drawId)(currAngle) * (y2.zext - y.zext) - dy2v(drawId)(currAngle) * (x.zext - x2.zext) - val visible = e0 > 0.S && e1 > 0.S && e2 > 0.S || - e0 < 0.S && e1 < 0.S && e2 < 0.S || - e0 === 0.S && e1 === 0.S && e2 === 0.S - when (visible) { - tileBuffer(i)(j) := FbRGB(r(drawId), g(drawId), b(drawId)) - } - - j := j + 1.U - x := x + 1.U - when (j === (Tile.size - 1).U) { - j := 0.U - i := i + 1.U - x := x - (Tile.size - 1).U - y := y + 1.U - when (i === (Tile.size - 1).U) { - val ndrawId = WireDefault(drawId + 1.U) - x0 := x0v(ndrawId)(currAngle) - x1 := x1v(ndrawId)(currAngle) - x2 := x2v(ndrawId)(currAngle) - y0 := y0v(ndrawId)(currAngle) - y1 := y1v(ndrawId)(currAngle) - y2 := y2v(ndrawId)(currAngle) - i := 0.U - y := y - (Tile.size - 1).U - drawId := ndrawId - when (drawId === (nrDraws - 1).U) { - ndrawId := 0.U - valid := true.B - } - } - } - } - - for (i <- 0 until Tile.size) { - for (j <- 0 until Tile.size) { - tileWriter.io.inReq.bits(i)(j) := tileBuffer(i)(j) - } - } - - val fbWriter = Module(new FbWriter) - io.vram <> fbWriter.io.vram - fbWriter.io.fbId := io.fbId - fbWriter.io.req <> tileWriter.io.outReq - io.done := row === Tile.nrRows.U && fbWriter.io.done -} diff --git a/src/main/scala/graphics/TileWriter.scala b/src/main/scala/graphics/TileWriter.scala deleted file mode 100644 index ed45c1b..0000000 --- a/src/main/scala/graphics/TileWriter.scala +++ /dev/null @@ -1,82 +0,0 @@ -// Copyright (C) 2023 Alan Jian (alanjian85@outlook.com) -// SPDX-License-Identifier: MIT - -import chisel3._ -import chisel3.util._ - -object Tile { - val size = 16 - - val nrCols = (Fb.width + size - 1) / size - val nrRows = (Fb.height + size - 1) / size - - val width = nrCols * size - val height = nrRows * size - - def apply() = new Tile -} - -class Tile extends Bundle { - val elem = Vec(Tile.size, Vec(Tile.size, FbRGB())) - - def apply(idx: Int) = elem(idx) - def apply(idx: UInt) = elem(idx) -} - -class TileWriter extends Module { - val io = IO(new Bundle { - val inReq = Flipped(Decoupled(new Tile)) - val outReq = Irrevocable(new FbWrReq) - }) - - val buf = SyncReadMem(2 * Tile.nrCols, Tile()) - val fron = RegInit(0.U(log2Up(buf.length).W)) - val rear = RegInit(0.U(log2Up(buf.length).W)) - val size = RegInit(0.U(unsignedBitLength(buf.length).W)) - - val nextRear = Mux(rear =/= (buf.length - 1).U, rear + 1.U, 0.U) - val nextSize = WireDefault(size) - val full = nextRear === fron - io.inReq.ready := !full - when (!full && io.inReq.valid) { - buf.write(rear, io.inReq.bits) - rear := nextRear - nextSize := size + 1.U - size := nextSize - } - - val col = RegInit(0.U(log2Up(Tile.nrCols).W)) - val row = RegInit(0.U(log2Up(Tile.size).W)) - val idx = RegInit(0.U(log2Up(Tile.size / Fb.nrBanks).W)) - val nextFron = WireDefault(fron) - val nextCol = WireDefault(col) - val writing = size >= Tile.nrCols.U - io.outReq.valid := writing - val pix = Wire(Vec(Fb.nrBanks, FbRGB())) - val tile = buf.read(nextFron + nextCol) - for (i <- 0 until Fb.nrBanks) { - pix(i) := tile(row)(idx << log2Up(Fb.nrBanks) | i.U) - } - io.outReq.bits.pix := pix - when (writing && io.outReq.ready) { - idx := idx + 1.U - when (idx === (Tile.size / Fb.nrBanks - 1).U) { - idx := 0.U - nextCol := col + 1.U - col := nextCol - when (col === (Tile.nrCols - 1).U) { - nextCol := 0.U - row := row + 1.U - when (row === (Tile.size - 1).U) { - row := 0.U - nextFron := fron + Tile.nrCols.U - fron := nextFron - when (fron === (buf.length - Tile.nrCols).U) { - nextFron := 0.U - } - size := nextSize - Tile.nrCols.U - } - } - } - } -} diff --git a/src/main/scala/renderer/Renderer.scala b/src/main/scala/renderer/Renderer.scala new file mode 100644 index 0000000..172d8e4 --- /dev/null +++ b/src/main/scala/renderer/Renderer.scala @@ -0,0 +1,26 @@ +import chisel3._ + +class renderer extends BlackBox { + val io = IO(new Bundle { + val ap_clk = Input(Bool()) + val ap_rst_n = Input(Bool()) + val fb_id = Input(UInt(Fb.idWidth.W)) + val m_axi_vram = Flipped(new WrAxiExtUpper(64, 128)) + val done = Output(Bool()) + }) +} + +class Renderer extends Module { + val io = IO(new Bundle { + val fbId = Input(UInt(Fb.idWidth.W)) + val vram = Flipped(new WrAxiExtUpper(64, 128)) + val done = Output(Bool()) + }) + + val renderer = Module(new renderer) + renderer.io.ap_clk := clock.asBool + renderer.io.ap_rst_n := !reset.asBool + renderer.io.fb_id := io.fbId + renderer.io.m_axi_vram <> io.vram + io.done := renderer.io.done +} diff --git a/src/main/scala/utils/Axi.scala b/src/main/scala/utils/Axi.scala index 2a36f0e..e59a797 100644 --- a/src/main/scala/utils/Axi.scala +++ b/src/main/scala/utils/Axi.scala @@ -171,6 +171,58 @@ class WrAxiExt(addrWidth: Int, dataWidth: Int, idWidth: Int = 0) extends Bundle } } +class WrAxiExtUpper(addrWidth: Int, dataWidth: Int, idWidth: Int = 0) extends Bundle { + val AWID = Input(UInt(idWidth.W)) + val AWADDR = Input(UInt(addrWidth.W)) + val AWLEN = Input(UInt(8.W)) + val AWSIZE = Input(UInt(3.W)) + val AWBURST = Input(UInt(2.W)) + val AWLOCK = Input(Bool()) + val AWCACHE = Input(UInt(4.W)) + val AWPROT = Input(UInt(3.W)) + val AWQOS = Input(UInt(4.W)) + val AWREGION = Input(UInt(4.W)) + val AWVALID = Input(Bool()) + val AWREADY = Output(Bool()) + + val WDATA = Input(UInt(dataWidth.W)) + val WSTRB = Input(UInt((dataWidth / 8).W)) + val WLAST = Input(Bool()) + val WVALID = Input(Bool()) + val WREADY = Output(Bool()) + + val BID = Output(UInt(idWidth.W)) + val BRESP = Output(UInt(2.W)) + val BVALID = Output(Bool()) + val BREADY = Input(Bool()) + + def connect(that: WrAxiExt) = { + that.awid := AWID + that.awaddr := AWADDR + that.awlen := AWLEN + that.awsize := AWSIZE + that.awburst := AWBURST + that.awlock := AWLOCK + that.awcache := AWCACHE + that.awprot := AWPROT + that.awqos := AWQOS + that.awregion := AWREGION + that.awvalid := AWVALID + AWREADY := that.awready + + that.wdata := WDATA + that.wstrb := WSTRB + that.wlast := WLAST + that.wvalid := WVALID + WREADY := that.wready + + BID := that.bid + BRESP := that.bresp + BVALID := that.bvalid + that.bready := BREADY + } +} + class RdWrAxiExt(addrWidth: Int, dataWidth: Int, rdIdWidth: Int = 0, wrIdWidth: Int = 0) extends Bundle { val arid = Input(UInt(rdIdWidth.W)) val araddr = Input(UInt(addrWidth.W)) diff --git a/vivado/bd/vram/ip/vram_auto_cc_0/vram_auto_cc_0.xci b/vivado/bd/vram/ip/vram_auto_cc_0/vram_auto_cc_0.xci index 66dbc97..e45551e 100644 --- a/vivado/bd/vram/ip/vram_auto_cc_0/vram_auto_cc_0.xci +++ b/vivado/bd/vram/ip/vram_auto_cc_0/vram_auto_cc_0.xci @@ -353,7 +353,7 @@ "parameters": { "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], - "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "RST": [ { "physical_name": "s_axi_aresetn" } ] @@ -366,7 +366,7 @@ "parameters": { "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], - "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "RST": [ { "physical_name": "m_axi_aresetn" } ] diff --git a/vivado/bd/vram/ip/vram_auto_cc_1/vram_auto_cc_1.xci b/vivado/bd/vram/ip/vram_auto_cc_1/vram_auto_cc_1.xci index afde30f..fab179a 100644 --- a/vivado/bd/vram/ip/vram_auto_cc_1/vram_auto_cc_1.xci +++ b/vivado/bd/vram/ip/vram_auto_cc_1/vram_auto_cc_1.xci @@ -261,7 +261,7 @@ "parameters": { "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], - "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "RST": [ { "physical_name": "s_axi_aresetn" } ] @@ -274,7 +274,7 @@ "parameters": { "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], - "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "RST": [ { "physical_name": "m_axi_aresetn" } ] diff --git a/vivado/bd/vram/ip/vram_auto_cc_2/vram_auto_cc_2.xci b/vivado/bd/vram/ip/vram_auto_cc_2/vram_auto_cc_2.xci index 34a7b61..e56b706 100644 --- a/vivado/bd/vram/ip/vram_auto_cc_2/vram_auto_cc_2.xci +++ b/vivado/bd/vram/ip/vram_auto_cc_2/vram_auto_cc_2.xci @@ -273,7 +273,7 @@ "parameters": { "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], - "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "RST": [ { "physical_name": "s_axi_aresetn" } ] @@ -286,7 +286,7 @@ "parameters": { "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], - "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "RST": [ { "physical_name": "m_axi_aresetn" } ] diff --git a/vivado/bd/vram/ip/vram_clk_wiz_0_0/vram_clk_wiz_0_0.xci b/vivado/bd/vram/ip/vram_clk_wiz_0_0/vram_clk_wiz_0_0.xci index a1858a4..01da1bb 100644 --- a/vivado/bd/vram/ip/vram_clk_wiz_0_0/vram_clk_wiz_0_0.xci +++ b/vivado/bd/vram/ip/vram_clk_wiz_0_0/vram_clk_wiz_0_0.xci @@ -619,10 +619,10 @@ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", "mode": "slave", "parameters": { - "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "vram_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],