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Moved to 16 matrix registers and adapted encoding
1 parent 794e485 commit 91d1d37

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3 files changed

+191
-96
lines changed

3 files changed

+191
-96
lines changed

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -186,7 +186,7 @@ static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo,
186186
static DecodeStatus DecodeMRRegisterClass(MCInst &Inst, uint64_t RegNo,
187187
uint64_t Address,
188188
const void *Decoder) {
189-
if (RegNo >= 8)
189+
if (RegNo >= 16)
190190
return MCDisassembler::Fail;
191191

192192
MCRegister Reg = RISCV::M0 + RegNo;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td‎

Lines changed: 169 additions & 82 deletions
Original file line numberDiff line numberDiff line change
@@ -14,125 +14,212 @@
1414
// Experimental RV64 i32 legalization patterns.
1515
//===----------------------------------------------------------------------===//
1616

17-
class RVMArithBase<bits<4> funct4_h, bits<5> funct5_l, dag outs, dag ins,
17+
// Matrix Memory Instructions
18+
class RVMLoadStore<bits<3> ldst, dag outs, dag ins,
1819
string opcodestr, string argstr>
1920
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
21+
bits<5> rs2;
22+
bits<5> rs1;
23+
bits<4> mds3;
24+
25+
let Inst{31-29} = 0b000;
26+
let Inst{28-26} = ldst;
27+
let Inst{25} = 0b0;
28+
let Inst{24-20} = rs2;
29+
let Inst{19-15} = rs1;
30+
let Inst{14-11} = mds3;
31+
let Inst{10-7} = 0b0000;
2032

21-
let Inst{31-28} = funct4_h;
22-
let Inst{27-25} = 0b000;
23-
let Inst{14-12} = 0b000;
24-
let Inst{11-7} = funct5_l;
2533
let Inst{6-0} = OPC_CUSTOM_0.Value;
2634
}
2735

28-
class RVMArith<bits<4> funct4_h, bits<5> funct5_l, dag outs, dag ins,
29-
string opcodestr, string argstr>
30-
: RVMArithBase<funct4_h, funct5_l, outs, ins, opcodestr, argstr> {
31-
bits<3> ms2;
32-
bits<3> ms1;
36+
// Matrix Arithmetic Instructions
37+
class RVMArithBase<dag outs, dag ins, string opcodestr, string argstr>
38+
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
39+
40+
let Inst{31-29} = 0b001;
41+
let Inst{25} = 0b0;
42+
let Inst{14-11} = 0b0000;
43+
let Inst{10-7} = 0b0000;
44+
45+
let Inst{6-0} = OPC_CUSTOM_0.Value;
46+
}
47+
class RVMMACC<dag outs, dag ins, string opcodestr, string argstr>
48+
: RVMArithBase<outs, ins, opcodestr, argstr> {
49+
50+
bits<4> ms2;
51+
bits<4> ms1;
3352
bits<2> md ;
3453

35-
let Inst{24} = 0b0;
36-
let Inst{23-21} = ms2;
37-
let Inst{20-18} = ms1;
38-
let Inst{17} = 0b0;
39-
let Inst{16-15} = md ;
54+
let Inst{28-26} = 0b010;
55+
let Inst{24-23} = md;
56+
let Inst{22-19} = ms2;
57+
let Inst{18-15} = ms1;
4058
}
59+
class RVMZeroA<dag outs, dag ins, string opcodestr, string argstr>
60+
: RVMArithBase<outs, ins, opcodestr, argstr> {
4161

42-
class RVMMove<bits<4> funct4_h, bits<5> funct5_l, dag outs, dag ins,
43-
string opcodestr, string argstr>
44-
: RVMArithBase<funct4_h, funct5_l, outs, ins, opcodestr, argstr> {
45-
bits<3> ms1;
46-
bits<3> md ;
62+
bits<2> md ;
4763

48-
let Inst{24-21} = 0b0000;
49-
let Inst{20-18} = ms1;
50-
let Inst{17-15} = md ;
64+
let Inst{28-26} = 0b000;
65+
let Inst{24-23} = md;
66+
let Inst{22-19} = 0b0000;
67+
let Inst{18-15} = 0b0000;
5168
}
69+
class RVMZeroM<dag outs, dag ins, string opcodestr, string argstr>
70+
: RVMArithBase<outs, ins, opcodestr, argstr> {
5271

53-
class RVMZero<bits<4> funct4_h, bits<5> funct5_l, bits<1> funct, dag outs, dag ins,
54-
string opcodestr, string argstr>
55-
: RVMArithBase<funct4_h, funct5_l, outs, ins, opcodestr, argstr> {
56-
bits<3> ms1;
57-
bits<3> md ;
72+
bits<4> ms1;
5873

59-
let Inst{24} = funct;
60-
let Inst{23-18} = 0b000000;
61-
let Inst{17-15} = md ;
74+
let Inst{28-26} = 0b001;
75+
let Inst{24-23} = 0b00;
76+
let Inst{22-19} = 0b0000;
77+
let Inst{18-15} = ms1;
6278
}
6379

64-
class RVMLoadStore<bits<1> matrix, bits<3> ldst, bits<2> size, dag outs, dag ins,
65-
string opcodestr, string argstr>
80+
// Matrix Move Instructions
81+
class RVMMoveBase<dag outs, dag ins, string opcodestr, string argstr>
6682
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
67-
bits<5> rs2;
68-
bits<5> rs1;
69-
bits<3> mds3;
7083

71-
let Inst{31-29} = 0b000;
72-
let Inst{28} = matrix;
73-
let Inst{27-25} = ldst;
74-
let Inst{24-20} = rs2;
75-
let Inst{19-15} = rs1;
76-
let Inst{11-10} = size;
77-
let Inst{9-7} = mds3;
84+
let Inst{31-29} = 0b010;
85+
let Inst{25} = 0b0;
86+
let Inst{20-19} = 0b00;
87+
let Inst{10-7} = 0b0000;
88+
89+
let Inst{6-0} = OPC_CUSTOM_0.Value;
90+
}
91+
class RVMMoveAM<dag outs, dag ins, string opcodestr, string argstr>
92+
: RVMMoveBase<outs, ins, opcodestr, argstr> {
93+
94+
bits<2> ms1;
95+
bits<4> md ;
96+
97+
let Inst{28-26} = 0b000;
98+
let Inst{24-23} = ms1;
99+
let Inst{22-21} = 0b00;
100+
let Inst{18-15} = 0b0000;
101+
let Inst{14-11} = md;
102+
}
103+
class RVMMoveAA<dag outs, dag ins, string opcodestr, string argstr>
104+
: RVMMoveBase<outs, ins, opcodestr, argstr> {
105+
106+
bits<2> ms1;
107+
bits<2> md ;
108+
109+
let Inst{28-26} = 0b001;
110+
let Inst{24-23} = ms1;
111+
let Inst{22-21} = md;
112+
let Inst{18-15} = 0b0000;
113+
let Inst{14-11} = 0b0000;
114+
}
115+
class RVMMoveMA<dag outs, dag ins, string opcodestr, string argstr>
116+
: RVMMoveBase<outs, ins, opcodestr, argstr> {
117+
118+
bits<2> md;
119+
bits<4> ms1 ;
120+
121+
let Inst{28-26} = 0b010;
122+
let Inst{24-23} = 0b00;
123+
let Inst{22-21} = md;
124+
let Inst{18-15} = ms1;
125+
let Inst{14-11} = 0b0000;
126+
}
127+
class RVMMoveMM<dag outs, dag ins, string opcodestr, string argstr>
128+
: RVMMoveBase<outs, ins, opcodestr, argstr> {
129+
130+
bits<4> md;
131+
bits<4> ms1 ;
132+
133+
let Inst{28-26} = 0b011;
134+
let Inst{24-23} = 0b00;
135+
let Inst{22-21} = 0b00;
136+
let Inst{18-15} = ms1;
137+
let Inst{14-11} = md;
138+
}
139+
140+
// Matrix Configuration Instructions
141+
class RVMCfgBase<dag outs, dag ins, string opcodestr, string argstr>
142+
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
143+
144+
let Inst{31-29} = 0b011;
145+
let Inst{25} = 0b0;
146+
let Inst{9-7} = 0b000;
78147

79148
let Inst{6-0} = OPC_CUSTOM_0.Value;
80149
}
81150

82-
class RVMConfigK<bits<3> funct3_h, dag outs, dag ins, string opcodestr, string argstr>
83-
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
151+
class RVMCfgK<dag outs, dag ins, string opcodestr, string argstr>
152+
: RVMCfgBase<outs, ins, opcodestr, argstr> {
84153
bits<5> rs1;
85154
bits<5> rd;
86155

87-
let Inst{31} = 0b0;
88-
let Inst{30-28} = funct3_h;
89-
let Inst{27-22} = 0b111000;
156+
let Inst{28-26} = 0b000;
157+
let Inst{24-20} = rd ;
90158
let Inst{19-15} = rs1;
91-
let Inst{14-12} = 0b000;
92-
let Inst{11-7} = rd;
93-
let Inst{6-0} = OPC_CUSTOM_0.Value;
159+
let Inst{14-13} = 0b00;
160+
let Inst{12-10} = 0b000;
94161
}
162+
class RVMCfgM<dag outs, dag ins, string opcodestr, string argstr>
163+
: RVMCfgBase<outs, ins, opcodestr, argstr> {
164+
bits<5> rs1;
165+
bits<5> rd;
166+
bits<2> imm2;
95167

96-
class RVMConfig<bits<3> funct3_h, dag outs, dag ins, string opcodestr, string argstr>
97-
: RVMConfigK<funct3_h, outs, ins, opcodestr, argstr> {
168+
let Inst{28-26} = 0b001;
169+
let Inst{24-20} = rd ;
170+
let Inst{19-15} = rs1;
171+
let Inst{14-13} = imm2{1-0};
172+
let Inst{12-10} = 0b000;
173+
}
174+
class RVMCfgN<dag outs, dag ins, string opcodestr, string argstr>
175+
: RVMCfgBase<outs, ins, opcodestr, argstr> {
176+
bits<5> rs1;
177+
bits<5> rd;
98178
bits<2> imm2;
99-
let Inst{21-20} = imm2{1-0};
179+
180+
let Inst{28-26} = 0b010;
181+
let Inst{24-20} = rd ;
182+
let Inst{19-15} = rs1;
183+
let Inst{14-13} = imm2{1-0};
184+
let Inst{12-10} = 0b000;
185+
}
186+
class RVMCfgDT<dag outs, dag ins, string opcodestr, string argstr>
187+
: RVMCfgBase<outs, ins, opcodestr, argstr> {
188+
bits<5> Aimm5;
189+
bits<5> Bimm5;
190+
bits<5> Cimm5;
191+
192+
let Inst{28-26} = 0b011;
193+
let Inst{24-20} = Cimm5{4-0};
194+
let Inst{19-15} = Aimm5{4-0};
195+
let Inst{14-10} = Bimm5{4-0};
100196
}
101197

102198
let Predicates = [HasVendorXTHeadMatrix], DecoderNamespace = "XTHeadMatrix",hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
103-
let hasSideEffects = 1 in {
104-
def MCFGK : RVMConfigK<0b000, (outs GPR:$rd), (ins GPR:$rs1 ), "mcfgk", "$rd, $rs1">;
105-
def MCFGM : RVMConfig <0b001, (outs GPR:$rd), (ins GPR:$rs1, uimm2:$imm2), "mcfgm", "$rd, $rs1, $imm2">;
106-
def MCFGN : RVMConfig <0b010, (outs GPR:$rd), (ins GPR:$rs1, uimm2:$imm2), "mcfgn", "$rd, $rs1, $imm2">;
107-
}
108-
def FMMACC_B : RVMArith<0b0001, 0b00000, (outs ACC:$md), (ins MR:$ms1, MR:$ms2), "fmmacc.b", "$md, $ms2, $ms1">;
109-
def FMMACC_H : RVMArith<0b0001, 0b01000, (outs ACC:$md), (ins MR:$ms1, MR:$ms2), "fmmacc.h", "$md, $ms2, $ms1">;
110-
def FMMACC_S : RVMArith<0b0001, 0b10000, (outs ACC:$md), (ins MR:$ms1, MR:$ms2), "fmmacc.s", "$md, $ms2, $ms1">;
111-
def MMAQA_B : RVMArith<0b0010, 0b00000, (outs ACC:$md), (ins MR:$ms1, MR:$ms2), "mmaqa.b" , "$md, $ms2, $ms1">;
112-
def MMADA_H : RVMArith<0b0010, 0b01000, (outs ACC:$md), (ins MR:$ms1, MR:$ms2), "mmada.h" , "$md, $ms2, $ms1">;
113-
def MMASA_W : RVMArith<0b0010, 0b10000, (outs ACC:$md), (ins MR:$ms1, MR:$ms2), "mmasa.w" , "$md, $ms2, $ms1">;
114-
115-
def MMOV_MM : RVMMove<0b0000, 0b00001, (outs MR:$md), (ins MR:$ms1), "mmov.mm" , "$md, $ms1">;
116-
def MMOV_MA : RVMMove<0b0000, 0b01001, (outs ACC:$md), (ins MR:$ms1), "mmov.ma" , "$md, $ms1">;
117-
def MMOV_AM : RVMMove<0b0000, 0b10001, (outs MR:$md), (ins ACC:$ms1), "mmov.am" , "$md, $ms1">;
118-
def MMOV_AA : RVMMove<0b0000, 0b11001, (outs ACC:$md), (ins ACC:$ms1), "mmov.aa" , "$md, $ms1">;
119-
120-
def MZERO_M : RVMZero<0b1010, 0b00000, 0b0, (outs MR:$md), (ins), "mzero.m", "$md">;
121-
def MZERO_A : RVMZero<0b1010, 0b00000, 0b1, (outs ACC:$md), (ins), "mzero.a", "$md">;
122199

123200
let mayLoad = 1 in {
124-
def MLD_LHS_B : RVMLoadStore<0b0, 0b100, 0b00, (outs MR:$mds3), (ins GPR:$rs1, GPR:$rs2), "mld.lhs.b", "$mds3, (${rs1}), $rs2">;
125-
def MLD_LHS_H : RVMLoadStore<0b0, 0b100, 0b01, (outs MR:$mds3), (ins GPR:$rs1, GPR:$rs2), "mld.lhs.h", "$mds3, (${rs1}), $rs2">;
126-
def MLD_LHS_W : RVMLoadStore<0b0, 0b100, 0b10, (outs MR:$mds3), (ins GPR:$rs1, GPR:$rs2), "mld.lhs.w", "$mds3, (${rs1}), $rs2">;
127-
def MLD_RHS_B : RVMLoadStore<0b1, 0b100, 0b00, (outs MR:$mds3), (ins GPR:$rs1, GPR:$rs2), "mld.rhs.b", "$mds3, (${rs1}), $rs2">;
128-
def MLD_RHS_H : RVMLoadStore<0b1, 0b100, 0b01, (outs MR:$mds3), (ins GPR:$rs1, GPR:$rs2), "mld.rhs.h", "$mds3, (${rs1}), $rs2">;
129-
def MLD_RHS_W : RVMLoadStore<0b1, 0b100, 0b10, (outs MR:$mds3), (ins GPR:$rs1, GPR:$rs2), "mld.rhs.w", "$mds3, (${rs1}), $rs2">;
201+
def MLD_LHS : RVMLoadStore<0b000, (outs MR:$mds3), (ins GPR:$rs1, GPR:$rs2), "mld.lhs", "$mds3, (${rs1}), $rs2">;
202+
def MLD_RHS : RVMLoadStore<0b001, (outs MR:$mds3), (ins GPR:$rs1, GPR:$rs2), "mld.rhs", "$mds3, (${rs1}), $rs2">;
130203
}
131204

132205
let mayStore = 1 in {
133-
def MST_B : RVMLoadStore<0b0, 0b101, 0b00, (outs), (ins MR:$mds3, GPR:$rs1, GPR:$rs2), "mst.b", "$mds3, (${rs1}), $rs2">;
134-
def MST_H : RVMLoadStore<0b0, 0b101, 0b01, (outs), (ins MR:$mds3, GPR:$rs1, GPR:$rs2), "mst.h", "$mds3, (${rs1}), $rs2">;
135-
def MST_W : RVMLoadStore<0b0, 0b101, 0b10, (outs), (ins MR:$mds3, GPR:$rs1, GPR:$rs2), "mst.w", "$mds3, (${rs1}), $rs2">;
206+
def MST : RVMLoadStore<0b010, (outs), (ins MR:$mds3, GPR:$rs1, GPR:$rs2), "mst", "$mds3, (${rs1}), $rs2">;
207+
}
208+
209+
def MMACC : RVMMACC <(outs ACC:$md), (ins MR:$ms1, MR:$ms2), "mmacc", "$md, $ms2, $ms1">;
210+
def MZERO_M : RVMZeroM<(outs MR:$md) , (ins) , "mzero.m", "$md">;
211+
def MZERO_A : RVMZeroA<(outs ACC:$md), (ins) , "mzero.a", "$md">;
212+
213+
def MMOV_MM : RVMMoveMM<(outs MR:$md) , (ins MR:$ms1) , "mmov.mm" , "$md, $ms1">;
214+
def MMOV_MA : RVMMoveMA<(outs ACC:$md), (ins MR:$ms1) , "mmov.ma" , "$md, $ms1">;
215+
def MMOV_AM : RVMMoveAM<(outs MR:$md) , (ins ACC:$ms1), "mmov.am" , "$md, $ms1">;
216+
def MMOV_AA : RVMMoveAA<(outs ACC:$md), (ins ACC:$ms1), "mmov.aa" , "$md, $ms1">;
217+
218+
let hasSideEffects = 1 in {
219+
def MCFGK : RVMCfgK <(outs GPR:$rd), (ins GPR:$rs1 ), "mcfgk" , "$rd, $rs1">;
220+
def MCFGM : RVMCfgM <(outs GPR:$rd), (ins GPR:$rs1, uimm2:$imm2), "mcfgm" , "$rd, $rs1, $imm2">;
221+
def MCFGN : RVMCfgN <(outs GPR:$rd), (ins GPR:$rs1, uimm2:$imm2), "mcfgn" , "$rd, $rs1, $imm2">;
222+
def MMAC_DT : RVMCfgDT<(outs),(ins uimm5:$immC, uimm5:$immA, uimm5:$immB), "mmac.dt", "$immC, $immA, $immB">;
136223
}
137224

138225
}

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.td‎

Lines changed: 21 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -623,20 +623,28 @@ def AnyReg : RegisterClass<"RISCV", [untyped], 32,
623623
// borrowed from tile definition in X86RegisterInfo.td
624624
let CopyCost = -1 in // Don't allow copying of matrix registers
625625
def MR : RegisterClass<"RISCV", [i32], 2048,
626-
(sequence "M%u", 0, 7)> {
626+
(sequence "M%u", 0, 15)> {
627627
let Size = 2048;
628628
let DecoderMethod = "DecodeMRRegisterClass";
629629
}
630630

631631
let RegAltNameIndices = [ABIRegAltName] in {
632-
def M0 : RISCVReg<0, "m0", ["m0"]>, DwarfRegNum<[97]>;
633-
def M1 : RISCVReg<1, "m1", ["m1"]>, DwarfRegNum<[98]>;
634-
def M2 : RISCVReg<2, "m2", ["m2"]>, DwarfRegNum<[99]>;
635-
def M3 : RISCVReg<3, "m3", ["m3"]>, DwarfRegNum<[100]>;
636-
def M4 : RISCVReg<4, "m4", ["m4"]>, DwarfRegNum<[101]>;
637-
def M5 : RISCVReg<5, "m5", ["m5"]>, DwarfRegNum<[102]>;
638-
def M6 : RISCVReg<6, "m6", ["m6"]>, DwarfRegNum<[103]>;
639-
def M7 : RISCVReg<7, "m7", ["m7"]>, DwarfRegNum<[104]>;
632+
def M0 : RISCVReg< 0, "m0" , ["m0"]> , DwarfRegNum<[97]>;
633+
def M1 : RISCVReg< 1, "m1" , ["m1"]> , DwarfRegNum<[98]>;
634+
def M2 : RISCVReg< 2, "m2" , ["m2"]> , DwarfRegNum<[99]>;
635+
def M3 : RISCVReg< 3, "m3" , ["m3"]> , DwarfRegNum<[100]>;
636+
def M4 : RISCVReg< 4, "m4" , ["m4"]> , DwarfRegNum<[101]>;
637+
def M5 : RISCVReg< 5, "m5" , ["m5"]> , DwarfRegNum<[102]>;
638+
def M6 : RISCVReg< 6, "m6" , ["m6"]> , DwarfRegNum<[103]>;
639+
def M7 : RISCVReg< 7, "m7" , ["m7"]> , DwarfRegNum<[104]>;
640+
def M8 : RISCVReg< 8, "m8" , ["m8"]> , DwarfRegNum<[105]>;
641+
def M9 : RISCVReg< 9, "m9" , ["m9"]> , DwarfRegNum<[106]>;
642+
def M10 : RISCVReg<10, "m10", ["m10"]>, DwarfRegNum<[107]>;
643+
def M11 : RISCVReg<11, "m11", ["m11"]>, DwarfRegNum<[108]>;
644+
def M12 : RISCVReg<12, "m12", ["m12"]>, DwarfRegNum<[109]>;
645+
def M13 : RISCVReg<13, "m13", ["m13"]>, DwarfRegNum<[110]>;
646+
def M14 : RISCVReg<14, "m14", ["m14"]>, DwarfRegNum<[111]>;
647+
def M15 : RISCVReg<15, "m15", ["m15"]>, DwarfRegNum<[112]>;
640648
}
641649

642650
// Accumulators
@@ -648,8 +656,8 @@ def ACC : RegisterClass<"RISCV", [i32], 2048,
648656
}
649657

650658
let RegAltNameIndices = [ABIRegAltName] in {
651-
def ACC0 : RISCVReg<0, "acc0", ["acc0"]>, DwarfRegNum<[105]>;
652-
def ACC1 : RISCVReg<1, "acc1", ["acc1"]>, DwarfRegNum<[106]>;
653-
def ACC2 : RISCVReg<2, "acc2", ["acc2"]>, DwarfRegNum<[107]>;
654-
def ACC3 : RISCVReg<3, "acc3", ["acc3"]>, DwarfRegNum<[108]>;
659+
def ACC0 : RISCVReg<0, "acc0", ["acc0"]>, DwarfRegNum<[113]>;
660+
def ACC1 : RISCVReg<1, "acc1", ["acc1"]>, DwarfRegNum<[114]>;
661+
def ACC2 : RISCVReg<2, "acc2", ["acc2"]>, DwarfRegNum<[115]>;
662+
def ACC3 : RISCVReg<3, "acc3", ["acc3"]>, DwarfRegNum<[116]>;
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}

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