diff --git a/.gitmodules b/.gitmodules index 0742a31..ec8cbac 100644 --- a/.gitmodules +++ b/.gitmodules @@ -69,7 +69,8 @@ url = https://github.com/pulp-platform/icache-intc.git [submodule "hw/ips/jtag_pulp"] path = hw/ips/jtag_pulp - url = https://github.com/pulp-platform/jtag_pulp.git + url = git@github.com:smanoni/jtag_pulp.git + branch = sm/lint [submodule "hw/ips/l2_tcdm_hybrid_interco"] path = hw/ips/l2_tcdm_hybrid_interco url = https://github.com/pulp-platform/L2_tcdm_hybrid_interco.git @@ -99,7 +100,8 @@ url = git@github.com:pulp-platform/tech_cells_generic.git [submodule "hw/ips/timer_unit"] path = hw/ips/timer_unit - url = https://github.com/pulp-platform/timer_unit.git + url = git@github.com:smanoni/timer_unit.git + branch = sm/cp-lint [submodule "hw/ips/udma_core"] path = hw/ips/udma_core url = https://github.com/pulp-platform/udma_core.git diff --git a/Bender.yml b/Bender.yml index 16dbbf4..c8f7f05 100644 --- a/Bender.yml +++ b/Bender.yml @@ -36,7 +36,7 @@ dependencies: wdt: { path: "hw/ips/wdt" } axi2mem: { path: "hw/ips/axi2mem" } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } - jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.3.0 } + jtag_pulp: { git: "git@github.com:smanoni/jtag_pulp.git", rev: "sm/lint" } idma: { git: "https://github.com/pulp-platform/idma.git", rev: 5af5d10 } pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: "control-pulp" } pulp_cluster: { git: "https://github.com/pulp-platform/pulp_cluster.git", rev: "control-pulp" } diff --git a/CHANGELOG.md b/CHANGELOG.md index f159aab..ecfad93 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -5,6 +5,21 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/), and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). ## Unreleased +## [5.4.0] - 2026-02-12 +### DARE v2.2 Release +### Added +- Lint flow based on Slang and Spyglass + +### Changed +- Updated tc_sram dependency (memory macros sim-only models) to avoid + unsythesizable errors in Spyglass. pragma translate on/off has been + added to the whole module resulting in 'empty module' error, to be waived + in linting, to be properly addressed during backend. +- Updated SIM_STDOUT default param of pms_top to 0, to avoid instantiation of tbs + in Spyglass where is not possible to drive top-level parameters externally. +- Exposed testmode_i of axi_to_reg instance in axi_scmi_mailbox module. Tied + it to zero in control_pulp_fpga, as currently DFT is disabled in our FPGA platform. + ## [5.3.0] - 2022-04-07 ### Added - Add switch between cluster and non-cluster configuration: elaboration time diff --git a/hw/includes/cluster_bus_defines.sv b/hw/includes/cluster_bus_defines.sv index d6b93ff..0c441aa 100644 --- a/hw/includes/cluster_bus_defines.sv +++ b/hw/includes/cluster_bus_defines.sv @@ -19,10 +19,10 @@ // CLUSTER BUS PARAMETRES -`define NB_SLAVE 4 -`define NB_MASTER 3 +`define CLUSTER_BUS_NB_SLAVE 4 +`define CLUSTER_BUS_NB_MASTER 3 -`define NB_REGION 1 +`define CLUSTER_BUS_NB_REGION 1 // MSTER PORT TO TCDM `define MASTER_0_START_ADDR 32'h1000_0000 diff --git a/hw/includes/instr_bus_defines.sv b/hw/includes/instr_bus_defines.sv index a8fd418..b3e9fc0 100644 --- a/hw/includes/instr_bus_defines.sv +++ b/hw/includes/instr_bus_defines.sv @@ -20,7 +20,7 @@ // INSTRUCTION BUS PARAMETRES // L2 -`define NB_REGION 2 +`define INSTR_BUS_NB_REGION 2 `define MASTER_0_REGION_0_START_ADDR 32'h1A00_0000 `define MASTER_0_REGION_0_END_ADDR 32'h1DFF_FFFF diff --git a/hw/includes/soc_bus_defines.sv b/hw/includes/soc_bus_defines.sv index 62d03aa..7699d07 100644 --- a/hw/includes/soc_bus_defines.sv +++ b/hw/includes/soc_bus_defines.sv @@ -17,9 +17,9 @@ // SOC BUS PARAMETRES `include "pulp_soc_defines.sv" -`define NB_SLAVE 4 -`define NB_MASTER 4 -`define NB_REGION 4 +`define SOC_BUS_NB_SLAVE 4 +`define SOC_BUS_NB_MASTER 4 +`define SOC_BUS_NB_REGION 4 // MASTER PORT TO CLUSTER(3MB) `define CLUSTER_DATA_START_ADDR 32'h1000_0000 diff --git a/hw/ips/axi b/hw/ips/axi index 038e2a8..68a2925 160000 --- a/hw/ips/axi +++ b/hw/ips/axi @@ -1 +1 @@ -Subproject commit 038e2a8fd849426bddc37dc02a4ee2934a977cab +Subproject commit 68a2925c0f57e5796bc20712b99643676c672e5a diff --git a/hw/ips/cluster_peripherals b/hw/ips/cluster_peripherals index 04821de..5b58335 160000 --- a/hw/ips/cluster_peripherals +++ b/hw/ips/cluster_peripherals @@ -1 +1 @@ -Subproject commit 04821de99cbfe634025a5f3dfb6d170c668e2c78 +Subproject commit 5b58335d9494e696e97022f1d0ab54a79f951348 diff --git a/hw/ips/common_cells b/hw/ips/common_cells index 0a9dc98..ae5965e 160000 --- a/hw/ips/common_cells +++ b/hw/ips/common_cells @@ -1 +1 @@ -Subproject commit 0a9dc988745b64e12f929a1dd9bc44d8068a2bc3 +Subproject commit ae5965e0f8dc1764a58b29e7c43d86993e7cb66c diff --git a/hw/ips/cv32e40p b/hw/ips/cv32e40p index 860fb0d..0b0b5d6 160000 --- a/hw/ips/cv32e40p +++ b/hw/ips/cv32e40p @@ -1 +1 @@ -Subproject commit 860fb0dc55ea5eb75cee2767cc0c77ead81f23e0 +Subproject commit 0b0b5d68c24081c329ed8f00edd5f2b4fb344c5a diff --git a/hw/ips/event_unit_flex b/hw/ips/event_unit_flex index 387ea2c..7b07365 160000 --- a/hw/ips/event_unit_flex +++ b/hw/ips/event_unit_flex @@ -1 +1 @@ -Subproject commit 387ea2c5012134f0aaa6658745a96ed5745ec530 +Subproject commit 7b07365f857d58bca6c1c05d49a64e6cc5f9b567 diff --git a/hw/ips/idma b/hw/ips/idma index 4c763f9..3705a46 160000 --- a/hw/ips/idma +++ b/hw/ips/idma @@ -1 +1 @@ -Subproject commit 4c763f9be2decd53c9cbe01d3d7b912d453201e6 +Subproject commit 3705a46eec65e43203b835ad1d5e2563276099b3 diff --git a/hw/ips/jtag_pulp b/hw/ips/jtag_pulp index 605a3de..72d7211 160000 --- a/hw/ips/jtag_pulp +++ b/hw/ips/jtag_pulp @@ -1 +1 @@ -Subproject commit 605a3de07f581a9c839fb45eb0c6fe73e8507670 +Subproject commit 72d7211d686d49f0f53643d00aab9ffcb02dd8b1 diff --git a/hw/ips/pulp_cluster b/hw/ips/pulp_cluster index d485967..b2621ca 160000 --- a/hw/ips/pulp_cluster +++ b/hw/ips/pulp_cluster @@ -1 +1 @@ -Subproject commit d485967b92feacd65e4411232e931d98e985686f +Subproject commit b2621ca2809c09e22935ee87504ca28a77240631 diff --git a/hw/ips/timer_unit b/hw/ips/timer_unit index 4c69615..4bcab4a 160000 --- a/hw/ips/timer_unit +++ b/hw/ips/timer_unit @@ -1 +1 @@ -Subproject commit 4c69615c89db9397a9747d6f6d6a36727854f0bc +Subproject commit 4bcab4a10987b96fbd0495329e85e4f79710eb63 diff --git a/hw/ips/udma_i2c b/hw/ips/udma_i2c index 99049c7..a6eeeb3 160000 --- a/hw/ips/udma_i2c +++ b/hw/ips/udma_i2c @@ -1 +1 @@ -Subproject commit 99049c7a463abd702765b0af4668052525dcbe7e +Subproject commit a6eeeb329f520d9b39ca5a9dabba18444dbc9189 diff --git a/hw/ips/udma_qspi b/hw/ips/udma_qspi index 44bc0d4..2a03dd0 160000 --- a/hw/ips/udma_qspi +++ b/hw/ips/udma_qspi @@ -1 +1 @@ -Subproject commit 44bc0d4b01326540378f307f2c010f3463c0b3bb +Subproject commit 2a03dd095e80cb7ccb44490f65a098e971049dae diff --git a/hw/ips/udma_uart b/hw/ips/udma_uart index ffac2f9..09de801 160000 --- a/hw/ips/udma_uart +++ b/hw/ips/udma_uart @@ -1 +1 @@ -Subproject commit ffac2f9693cb065f750120e98e0aa6d2af0674ed +Subproject commit 09de80126adbac908e10f06a44e4bb60d6bc8eb0 diff --git a/hw/pulp/control_pulp.sv b/hw/pulp/control_pulp.sv index 47bce5b..8d548a8 100644 --- a/hw/pulp/control_pulp.sv +++ b/hw/pulp/control_pulp.sv @@ -203,7 +203,7 @@ module control_pulp import control_pulp_pkg::*; #( localparam int unsigned AXI_CLUSTER_SOC_DATA_WIDTH = 64; localparam int unsigned AXI_SOC_CLUSTER_DATA_WIDTH = 32; localparam int unsigned AXI_SOC_CLUSTER_ID_WIDTH = pkg_soc_interconnect::AXI_ID_OUT_WIDTH; // = 1 + clog2(13) = 5 - localparam int unsigned AXI_CLUSTER_SOC_ID_WIDTH = AXI_SOC_CLUSTER_ID_WIDTH + $clog2(`NB_SLAVE); // = 5 + clog2(4) = 7; + localparam int unsigned AXI_CLUSTER_SOC_ID_WIDTH = AXI_SOC_CLUSTER_ID_WIDTH + $clog2(`SOC_BUS_NB_SLAVE); // = 5 + clog2(4) = 7; localparam int unsigned AXI_USER_WIDTH = 6; localparam int unsigned AXI_CLUSTER_SOC_STRB_WIDTH = AXI_CLUSTER_SOC_DATA_WIDTH/8; diff --git a/hw/pulp/system_clk_rst_gen.sv b/hw/pulp/system_clk_rst_gen.sv index 5770329..1a9976c 100644 --- a/hw/pulp/system_clk_rst_gen.sv +++ b/hw/pulp/system_clk_rst_gen.sv @@ -89,16 +89,19 @@ module system_clk_rst_gen ( // ref_clk -> divider -> 32 Khz timer clock // fixed division by integer factor - clk_div #( - .RATIO(3125) // TODO: ADJUST RATIO to match ref clk - // 100 Mhz / 32 Khz = 3125 - ) i_clk_div_timer ( - .clk_i (ref_clk_i), - .rst_ni (rstn_glob_i), - .testmode_i(test_mode_i), - .en_i (1'b1), // TODO: maybe we can map this to reg - .clk_o (clk_for_slow) - ); + clk_int_div #( + .DIV_VALUE_WIDTH($clog2(3125+1)), + .DEFAULT_DIV_VALUE(3125) + ) i_clk_div_timer( + .clk_i ( ref_clk_i ), + .rst_ni ( rstn_glob_i ), + .test_mode_en_i ( test_mode_i ), + .en_i ( 1'b1 ), // TODO: maybe we can map this to reg + .div_i ( '1 ), + .div_valid_i ( 1'b0 ), + .div_ready_o ( ), + .clk_o ( clk_for_slow ) + ); // Allow clock muxing if dividers are faulty: ref_clk passthrough pulp_clock_mux2 i_clk_mux_soc (