If we set parameter bit AxiVldRdy = 1'b0 with NumIn > 1
assign gnt_o[l*2] = gnt_nodes[Idx0] & (AxiVldRdy | req_d[l*2]) & ~sel;
assign gnt_o[l*2+1] = gnt_nodes[Idx0] & (AxiVldRdy | req_d[l*2+1]) & sel;
above code shows that if gnt_o would not be asserted if req_i == 0.
But if we set NumIn == 1, the following code shows that gnt_o is just the same value as gnt_i and don't depend on req_i
// just pass through in this corner case
if (NumIn == unsigned'(1)) begin : gen_pass_through
assign req_o = req_i[0];
assign gnt_o[0] = gnt_i;
assign data_o = data_i[0];
assign idx_o = '0;
// non-degenerate cases
end
This causes inconsistent grant behavior between NumIn == 1 and NumIn > 1 and subtle bugs on my design which only occurs when NumIn == 1.
Making the following changes in NumIn == 1 maybe makes it better?
// just pass through in this corner case
if (NumIn == unsigned'(1)) begin : gen_pass_through
assign req_o = req_i[0];
assign gnt_o[0] = gnt_i & (AxiVldRdy | req_i[0];
assign data_o = data_i[0];
assign idx_o = '0;
// non-degenerate cases
end
If we set
parameter bit AxiVldRdy = 1'b0withNumIn > 1above code shows that if
gnt_owould not be asserted ifreq_i == 0.But if we set
NumIn == 1, the following code shows thatgnt_ois just the same value asgnt_iand don't depend onreq_iThis causes inconsistent grant behavior between
NumIn == 1andNumIn > 1and subtle bugs on my design which only occurs whenNumIn == 1.Making the following changes in
NumIn == 1maybe makes it better?