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Align req and rsp types to #153 
1 parent 7e00f3e commit c870707

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+924
-924
lines changed

‎doc/axi_lite_mailbox.md‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ This table describes the parameters of the module.
1616
| `AxiAddrWidth` | `int unsigned` | The AXI4-Lite address width on the AW and AR channels |
1717
| `AxiDataWidth` | `int unsigned` | The AXI4-Lite data width on the W and R channels |
1818
| `req_lite_t` | `type` | In accordance with the `AXI_LITE_TYPEDEF_REQ_T` macro |
19-
| `resp_lite_t` | `type` | In accordance with the `AXI_LITE_TYPEDEF_RESP_T` macro |
19+
| `rsp_lite_t` | `type` | In accordance with the `AXI_LITE_TYPEDEF_RSP_T` macro |
2020

2121

2222
## Module Ports

‎doc/axi_lite_xbar.md‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg
4040
| `AxiDataWidth` | `int unsigned` | The AXI4-Lite data width. |
4141
| `NoAddrRules` | `int unsigned` | The number of address map rules. |
4242

43-
The other parameters are types to define the ports of the crossbar. The `*_chan_t` and `*_req_t`/`*_resp_t` types must be bound in accordance to the configuration with the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`. The `rule_t` type must be bound to an address decoding rule with the same address width as in the configuration, and `axi_pkg` contains definitions for 64- and 32-bit addresses.
43+
The other parameters are types to define the ports of the crossbar. The `*_chan_t` and `*_req_t`/`*_rsp_t` types must be bound in accordance to the configuration with the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`. The `rule_t` type must be bound to an address decoding rule with the same address width as in the configuration, and `axi_pkg` contains definitions for 64- and 32-bit addresses.
4444

4545
### Pipelining and Latency
4646

‎doc/axi_xbar.md‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg
5454
| `AxiDataWidth` | `int unsigned` | The AXI data width. |
5555
| `NoAddrRules` | `int unsigned` | The number of address map rules. |
5656

57-
The other parameters are types to define the ports of the crossbar. The `*_chan_t` and `*_req_t`/`*_resp_t` types must be bound in accordance to the configuration with the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`. The `rule_t` type must be bound to an address decoding rule with the same address width as in the configuration, and `axi_pkg` contains definitions for 64- and 32-bit addresses.
57+
The other parameters are types to define the ports of the crossbar. The `*_chan_t` and `*_req_t`/`*_rsp_t` types must be bound in accordance to the configuration with the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`. The `rule_t` type must be bound to an address decoding rule with the same address width as in the configuration, and `axi_pkg` contains definitions for 64- and 32-bit addresses.
5858

5959
### Pipelining and Latency
6060

‎include/axi/typedef.svh‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929
// `AXI_TYPEDEF_AR_CHAN_T(axi_ar_t, axi_addr_t, axi_id_t, axi_user_t)
3030
// `AXI_TYPEDEF_R_CHAN_T(axi_r_t, axi_data_t, axi_id_t, axi_user_t)
3131
// `AXI_TYPEDEF_REQ_T(axi_req_t, axi_aw_t, axi_w_t, axi_ar_t)
32-
// `AXI_TYPEDEF_RESP_T(axi_resp_t, axi_b_t, axi_r_t)
32+
// `AXI_TYPEDEF_RSP_T(axi_rsp_t, axi_b_t, axi_r_t)
3333
`define AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) \
3434
typedef struct packed { \
3535
id_t id; \
@@ -91,7 +91,7 @@
9191
logic ar_valid; \
9292
logic r_ready; \
9393
} req_t;
94-
`define AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) \
94+
`define AXI_TYPEDEF_RSP_T(rsp_t, b_chan_t, r_chan_t) \
9595
typedef struct packed { \
9696
logic aw_ready; \
9797
logic ar_ready; \
@@ -100,7 +100,7 @@
100100
b_chan_t b; \
101101
logic r_valid; \
102102
r_chan_t r; \
103-
} resp_t;
103+
} rsp_t;
104104
////////////////////////////////////////////////////////////////////////////////////////////////////
105105

106106

@@ -113,7 +113,7 @@
113113
// Usage Example:
114114
// `AXI_TYPEDEF_ALL(axi, addr_t, id_t, data_t, strb_t, user_t)
115115
//
116-
// This defines `axi_req_t` and `axi_resp_t` request/response structs as well as `axi_aw_chan_t`,
116+
// This defines `axi_req_t` and `axi_rsp_t` request/response structs as well as `axi_aw_chan_t`,
117117
// `axi_w_chan_t`, `axi_b_chan_t`, `axi_ar_chan_t`, and `axi_r_chan_t` channel structs.
118118
`define AXI_TYPEDEF_ALL(__name, __addr_t, __id_t, __data_t, __strb_t, __user_t) \
119119
`AXI_TYPEDEF_AW_CHAN_T(__name``_aw_chan_t, __addr_t, __id_t, __user_t) \
@@ -122,7 +122,7 @@
122122
`AXI_TYPEDEF_AR_CHAN_T(__name``_ar_chan_t, __addr_t, __id_t, __user_t) \
123123
`AXI_TYPEDEF_R_CHAN_T(__name``_r_chan_t, __data_t, __id_t, __user_t) \
124124
`AXI_TYPEDEF_REQ_T(__name``_req_t, __name``_aw_chan_t, __name``_w_chan_t, __name``_ar_chan_t) \
125-
`AXI_TYPEDEF_RESP_T(__name``_resp_t, __name``_b_chan_t, __name``_r_chan_t)
125+
`AXI_TYPEDEF_RSP_T(__name``_rsp_t, __name``_b_chan_t, __name``_r_chan_t)
126126
////////////////////////////////////////////////////////////////////////////////////////////////////
127127

128128

@@ -136,7 +136,7 @@
136136
// `AXI_LITE_TYPEDEF_AR_CHAN_T(axi_lite_ar_t, axi_lite_addr_t)
137137
// `AXI_LITE_TYPEDEF_R_CHAN_T(axi_lite_r_t, axi_lite_data_t)
138138
// `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, axi_lite_aw_t, axi_lite_w_t, axi_lite_ar_t)
139-
// `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, axi_lite_b_t, axi_lite_r_t)
139+
// `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, axi_lite_b_t, axi_lite_r_t)
140140
`define AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_lite_t, addr_t) \
141141
typedef struct packed { \
142142
addr_t addr; \
@@ -172,7 +172,7 @@
172172
logic ar_valid; \
173173
logic r_ready; \
174174
} req_lite_t;
175-
`define AXI_LITE_TYPEDEF_RESP_T(resp_lite_t, b_chan_lite_t, r_chan_lite_t) \
175+
`define AXI_LITE_TYPEDEF_RSP_T(rsp_lite_t, b_chan_lite_t, r_chan_lite_t) \
176176
typedef struct packed { \
177177
logic aw_ready; \
178178
logic w_ready; \
@@ -181,7 +181,7 @@
181181
logic ar_ready; \
182182
r_chan_lite_t r; \
183183
logic r_valid; \
184-
} resp_lite_t;
184+
} rsp_lite_t;
185185
////////////////////////////////////////////////////////////////////////////////////////////////////
186186

187187

@@ -194,7 +194,7 @@
194194
// Usage Example:
195195
// `AXI_LITE_TYPEDEF_ALL(axi_lite, addr_t, data_t, strb_t)
196196
//
197-
// This defines `axi_lite_req_t` and `axi_lite_resp_t` request/response structs as well as
197+
// This defines `axi_lite_req_t` and `axi_lite_rsp_t` request/response structs as well as
198198
// `axi_lite_aw_chan_t`, `axi_lite_w_chan_t`, `axi_lite_b_chan_t`, `axi_lite_ar_chan_t`, and
199199
// `axi_lite_r_chan_t` channel structs.
200200
`define AXI_LITE_TYPEDEF_ALL(__name, __addr_t, __data_t, __strb_t) \
@@ -204,7 +204,7 @@
204204
`AXI_LITE_TYPEDEF_AR_CHAN_T(__name``_ar_chan_t, __addr_t) \
205205
`AXI_LITE_TYPEDEF_R_CHAN_T(__name``_r_chan_t, __data_t) \
206206
`AXI_LITE_TYPEDEF_REQ_T(__name``_req_t, __name``_aw_chan_t, __name``_w_chan_t, __name``_ar_chan_t) \
207-
`AXI_LITE_TYPEDEF_RESP_T(__name``_resp_t, __name``_b_chan_t, __name``_r_chan_t)
207+
`AXI_LITE_TYPEDEF_RSP_T(__name``_rsp_t, __name``_b_chan_t, __name``_r_chan_t)
208208
////////////////////////////////////////////////////////////////////////////////////////////////////
209209

210210

‎scripts/axi_intercon_gen.py‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -378,9 +378,9 @@ def write(self):
378378
`AXI_TYPEDEF_R_CHAN_T(r_chan_slv_t, data_t, id_slv_t, user_t)
379379
380380
`AXI_TYPEDEF_REQ_T(slv_req_t, aw_chan_mst_t, w_chan_t, ar_chan_mst_t)
381-
`AXI_TYPEDEF_RESP_T(slv_resp_t, b_chan_mst_t, r_chan_mst_t)
381+
`AXI_TYPEDEF_RSP_T(slv_rsp_t, b_chan_mst_t, r_chan_mst_t)
382382
`AXI_TYPEDEF_REQ_T(mst_req_t, aw_chan_slv_t, w_chan_t, ar_chan_slv_t)
383-
`AXI_TYPEDEF_RESP_T(mst_resp_t, b_chan_slv_t, r_chan_slv_t)
383+
`AXI_TYPEDEF_RSP_T(mst_rsp_t, b_chan_slv_t, r_chan_slv_t)
384384
385385
"""
386386

‎src/axi_atop_filter.sv‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -40,22 +40,22 @@ module axi_atop_filter #(
4040
/// Maximum number of in-flight AXI write transactions
4141
parameter int unsigned AxiMaxWriteTxns = 0,
4242
/// AXI request type
43-
parameter type axi_req_t = logic,
43+
parameter type axi_req_t = logic,
4444
/// AXI response type
45-
parameter type axi_resp_t = logic
45+
parameter type axi_rsp_t = logic
4646
) (
4747
/// Rising-edge clock of both ports
48-
input logic clk_i,
48+
input logic clk_i,
4949
/// Asynchronous reset, active low
50-
input logic rst_ni,
50+
input logic rst_ni,
5151
/// Slave port request
52-
input axi_req_t slv_req_i,
52+
input axi_req_t slv_req_i,
5353
/// Slave port response
54-
output axi_resp_t slv_resp_o,
54+
output axi_rsp_t slv_resp_o,
5555
/// Master port request
56-
output axi_req_t mst_req_o,
56+
output axi_req_t mst_req_o,
5757
/// Master port response
58-
input axi_resp_t mst_resp_i
58+
input axi_rsp_t mst_resp_i
5959
);
6060

6161
// Minimum counter width is 2 to detect underflows.
@@ -406,10 +406,10 @@ module axi_atop_filter_intf #(
406406
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
407407
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
408408
`AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t)
409-
`AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t)
409+
`AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t)
410410

411411
axi_req_t slv_req, mst_req;
412-
axi_resp_t slv_resp, mst_resp;
412+
axi_rsp_t slv_resp, mst_resp;
413413

414414
`AXI_ASSIGN_TO_REQ(slv_req, slv)
415415
`AXI_ASSIGN_FROM_RESP(slv, slv_resp)
@@ -423,7 +423,7 @@ module axi_atop_filter_intf #(
423423
.AxiMaxWriteTxns ( AXI_MAX_WRITE_TXNS ),
424424
// AXI request & response type
425425
.axi_req_t ( axi_req_t ),
426-
.axi_resp_t ( axi_resp_t )
426+
.axi_rsp_t ( axi_rsp_t )
427427
) i_axi_atop_filter (
428428
.clk_i,
429429
.rst_ni,

‎src/axi_burst_splitter.sv‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -36,18 +36,18 @@ module axi_burst_splitter #(
3636
parameter int unsigned IdWidth = 32'd0,
3737
parameter int unsigned UserWidth = 32'd0,
3838
parameter type axi_req_t = logic,
39-
parameter type axi_resp_t = logic
39+
parameter type axi_rsp_t = logic
4040
) (
41-
input logic clk_i,
42-
input logic rst_ni,
41+
input logic clk_i,
42+
input logic rst_ni,
4343

4444
// Input / Slave Port
45-
input axi_req_t slv_req_i,
46-
output axi_resp_t slv_resp_o,
45+
input axi_req_t slv_req_i,
46+
output axi_rsp_t slv_resp_o,
4747

4848
// Output / Master Port
49-
output axi_req_t mst_req_o,
50-
input axi_resp_t mst_resp_i
49+
output axi_req_t mst_req_o,
50+
input axi_rsp_t mst_resp_i
5151
);
5252

5353
typedef logic [AddrWidth-1:0] addr_t;
@@ -62,8 +62,8 @@ module axi_burst_splitter #(
6262
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
6363

6464
// Demultiplex between supported and unsupported transactions.
65-
axi_req_t act_req, unsupported_req;
66-
axi_resp_t act_resp, unsupported_resp;
65+
axi_req_t act_req, unsupported_req;
66+
axi_rsp_t act_resp, unsupported_resp;
6767
logic sel_aw_unsupported, sel_ar_unsupported;
6868
localparam int unsigned MaxTxns = (MaxReadTxns > MaxWriteTxns) ? MaxReadTxns : MaxWriteTxns;
6969
axi_demux #(
@@ -74,7 +74,7 @@ module axi_burst_splitter #(
7474
.ar_chan_t ( ar_chan_t ),
7575
.r_chan_t ( r_chan_t ),
7676
.axi_req_t ( axi_req_t ),
77-
.axi_resp_t ( axi_resp_t ),
77+
.axi_rsp_t ( axi_rsp_t ),
7878
.NoMstPorts ( 2 ),
7979
.MaxTrans ( MaxTxns ),
8080
.AxiLookBits ( IdWidth ),
@@ -120,7 +120,7 @@ module axi_burst_splitter #(
120120
axi_err_slv #(
121121
.AxiIdWidth ( IdWidth ),
122122
.axi_req_t ( axi_req_t ),
123-
.axi_resp_t ( axi_resp_t ),
123+
.axi_rsp_t ( axi_rsp_t ),
124124
.Resp ( axi_pkg::RESP_SLVERR ),
125125
.ATOPs ( 1'b0 ), // The burst splitter does not support ATOPs.
126126
.MaxTrans ( 1 ) // Splitting bursts implies a low-performance bus.

‎src/axi_cdc.sv‎

Lines changed: 35 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -24,26 +24,26 @@
2424
/// ports are in separate clock domains. IMPORTANT: For each AXI channel, you MUST properly
2525
/// constrain three paths through the FIFO; see the header of `cdc_fifo_gray` for instructions.
2626
module axi_cdc #(
27-
parameter type aw_chan_t = logic, // AW Channel Type
28-
parameter type w_chan_t = logic, // W Channel Type
29-
parameter type b_chan_t = logic, // B Channel Type
30-
parameter type ar_chan_t = logic, // AR Channel Type
31-
parameter type r_chan_t = logic, // R Channel Type
32-
parameter type axi_req_t = logic, // encapsulates request channels
33-
parameter type axi_resp_t = logic, // encapsulates request channels
27+
parameter type aw_chan_t = logic, // AW Channel Type
28+
parameter type w_chan_t = logic, // W Channel Type
29+
parameter type b_chan_t = logic, // B Channel Type
30+
parameter type ar_chan_t = logic, // AR Channel Type
31+
parameter type r_chan_t = logic, // R Channel Type
32+
parameter type axi_req_t = logic, // encapsulates request channels
33+
parameter type axi_rsp_t = logic, // encapsulates request channels
3434
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
3535
parameter int unsigned LogDepth = 1
3636
) (
3737
// slave side - clocked by `src_clk_i`
38-
input logic src_clk_i,
39-
input logic src_rst_ni,
40-
input axi_req_t src_req_i,
41-
output axi_resp_t src_resp_o,
38+
input logic src_clk_i,
39+
input logic src_rst_ni,
40+
input axi_req_t src_req_i,
41+
output axi_rsp_t src_resp_o,
4242
// master side - clocked by `dst_clk_i`
43-
input logic dst_clk_i,
44-
input logic dst_rst_ni,
45-
output axi_req_t dst_req_o,
46-
input axi_resp_t dst_resp_i
43+
input logic dst_clk_i,
44+
input logic dst_rst_ni,
45+
output axi_req_t dst_req_o,
46+
input axi_rsp_t dst_resp_i
4747
);
4848

4949
aw_chan_t [2**LogDepth-1:0] async_data_aw_data;
@@ -64,7 +64,7 @@ module axi_cdc #(
6464
.ar_chan_t ( ar_chan_t ),
6565
.r_chan_t ( r_chan_t ),
6666
.axi_req_t ( axi_req_t ),
67-
.axi_resp_t ( axi_resp_t ),
67+
.axi_rsp_t ( axi_rsp_t ),
6868
.LogDepth ( LogDepth )
6969
) i_axi_cdc_src (
7070
.src_clk_i,
@@ -95,7 +95,7 @@ module axi_cdc #(
9595
.ar_chan_t ( ar_chan_t ),
9696
.r_chan_t ( r_chan_t ),
9797
.axi_req_t ( axi_req_t ),
98-
.axi_resp_t ( axi_resp_t ),
98+
.axi_rsp_t ( axi_rsp_t ),
9999
.LogDepth ( LogDepth )
100100
) i_axi_cdc_dst (
101101
.dst_clk_i,
@@ -153,11 +153,11 @@ module axi_cdc_intf #(
153153
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
154154
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
155155
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
156-
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
157-
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
156+
`AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t)
157+
`AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t)
158158

159-
req_t src_req, dst_req;
160-
resp_t src_resp, dst_resp;
159+
axi_req_t src_req, dst_req;
160+
axi_rsp_t src_resp, dst_resp;
161161

162162
`AXI_ASSIGN_TO_REQ(src_req, src)
163163
`AXI_ASSIGN_FROM_RESP(src, src_resp)
@@ -171,8 +171,8 @@ module axi_cdc_intf #(
171171
.b_chan_t ( b_chan_t ),
172172
.ar_chan_t ( ar_chan_t ),
173173
.r_chan_t ( r_chan_t ),
174-
.axi_req_t ( req_t ),
175-
.axi_resp_t ( resp_t ),
174+
.axi_req_t ( axi_req_t ),
175+
.axi_rsp_t ( axi_rsp_t ),
176176
.LogDepth ( LOG_DEPTH )
177177
) i_axi_cdc (
178178
.src_clk_i,
@@ -211,11 +211,11 @@ module axi_lite_cdc_intf #(
211211
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)
212212
`AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)
213213
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)
214-
`AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
215-
`AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
214+
`AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, aw_chan_t, w_chan_t, ar_chan_t)
215+
`AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, b_chan_t, r_chan_t)
216216

217-
req_t src_req, dst_req;
218-
resp_t src_resp, dst_resp;
217+
axi_lite_req_t src_req, dst_req;
218+
axi_lite_rsp_t src_resp, dst_resp;
219219

220220
`AXI_LITE_ASSIGN_TO_REQ(src_req, src)
221221
`AXI_LITE_ASSIGN_FROM_RESP(src, src_resp)
@@ -224,14 +224,14 @@ module axi_lite_cdc_intf #(
224224
`AXI_LITE_ASSIGN_TO_RESP(dst_resp, dst)
225225

226226
axi_cdc #(
227-
.aw_chan_t ( aw_chan_t ),
228-
.w_chan_t ( w_chan_t ),
229-
.b_chan_t ( b_chan_t ),
230-
.ar_chan_t ( ar_chan_t ),
231-
.r_chan_t ( r_chan_t ),
232-
.axi_req_t ( req_t ),
233-
.axi_resp_t ( resp_t ),
234-
.LogDepth ( LOG_DEPTH )
227+
.aw_chan_t ( aw_chan_t ),
228+
.w_chan_t ( w_chan_t ),
229+
.b_chan_t ( b_chan_t ),
230+
.ar_chan_t ( ar_chan_t ),
231+
.r_chan_t ( r_chan_t ),
232+
.axi_req_t ( axi_lite_req_t ),
233+
.axi_rsp_t ( axi_lite_rsp_t ),
234+
.LogDepth ( LOG_DEPTH )
235235
) i_axi_cdc (
236236
.src_clk_i,
237237
.src_rst_ni,

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